1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
102 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
106 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
107 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
109 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
111 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
113 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
115 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
117 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
121 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
122 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
123 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
124 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
126 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
127 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
129 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
130 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
132 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
133 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
135 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
136 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137 SDNPMayLoad, SDNPMemOperand]>;
138 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140 SDNPMayLoad, SDNPMemOperand]>;
141 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
143 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
161 [SDNPHasChain, SDNPMayStore,
162 SDNPMayLoad, SDNPMemOperand]>;
163 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
164 [SDNPHasChain, SDNPMayStore,
165 SDNPMayLoad, SDNPMemOperand]>;
166 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
169 def X86vastart_save_xmm_regs :
170 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
171 SDT_X86VASTART_SAVE_XMM_REGS,
172 [SDNPHasChain, SDNPVariadic]>;
174 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
175 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
177 def X86callseq_start :
178 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
179 [SDNPHasChain, SDNPOutGlue]>;
181 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
184 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
185 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
188 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
189 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
190 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
191 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
194 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
195 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
197 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
198 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
200 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
201 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
206 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
211 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
212 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
214 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
216 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
217 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
219 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
220 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
221 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
223 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
225 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
227 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
229 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
230 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
231 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
233 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
235 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
236 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
238 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
241 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
242 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
244 //===----------------------------------------------------------------------===//
245 // X86 Operand Definitions.
248 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
249 // the index operand of an address, to conform to x86 encoding restrictions.
250 def ptr_rc_nosp : PointerLikeRegClass<1>;
252 // *mem - Operand definitions for the funky X86 addressing mode operands.
254 def X86MemAsmOperand : AsmOperandClass {
256 let SuperClasses = [];
258 def X86AbsMemAsmOperand : AsmOperandClass {
260 let SuperClasses = [X86MemAsmOperand];
262 class X86MemOperand<string printMethod> : Operand<iPTR> {
263 let PrintMethod = printMethod;
264 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
265 let ParserMatchClass = X86MemAsmOperand;
268 let OperandType = "OPERAND_MEMORY" in {
269 def opaque32mem : X86MemOperand<"printopaquemem">;
270 def opaque48mem : X86MemOperand<"printopaquemem">;
271 def opaque80mem : X86MemOperand<"printopaquemem">;
272 def opaque512mem : X86MemOperand<"printopaquemem">;
274 def i8mem : X86MemOperand<"printi8mem">;
275 def i16mem : X86MemOperand<"printi16mem">;
276 def i32mem : X86MemOperand<"printi32mem">;
277 def i64mem : X86MemOperand<"printi64mem">;
278 def i128mem : X86MemOperand<"printi128mem">;
279 def i256mem : X86MemOperand<"printi256mem">;
280 def f32mem : X86MemOperand<"printf32mem">;
281 def f64mem : X86MemOperand<"printf64mem">;
282 def f80mem : X86MemOperand<"printf80mem">;
283 def f128mem : X86MemOperand<"printf128mem">;
284 def f256mem : X86MemOperand<"printf256mem">;
287 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
288 // plain GR64, so that it doesn't potentially require a REX prefix.
289 def i8mem_NOREX : Operand<i64> {
290 let PrintMethod = "printi8mem";
291 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
292 let ParserMatchClass = X86MemAsmOperand;
293 let OperandType = "OPERAND_MEMORY";
296 // GPRs available for tailcall.
297 // It represents GR64_TC or GR64_TCW64.
298 def ptr_rc_tailcall : PointerLikeRegClass<2>;
300 // Special i32mem for addresses of load folding tail calls. These are not
301 // allowed to use callee-saved registers since they must be scheduled
302 // after callee-saved register are popped.
303 def i32mem_TC : Operand<i32> {
304 let PrintMethod = "printi32mem";
305 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
306 let ParserMatchClass = X86MemAsmOperand;
307 let OperandType = "OPERAND_MEMORY";
310 // Special i64mem for addresses of load folding tail calls. These are not
311 // allowed to use callee-saved registers since they must be scheduled
312 // after callee-saved register are popped.
313 def i64mem_TC : Operand<i64> {
314 let PrintMethod = "printi64mem";
315 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
316 ptr_rc_tailcall, i32imm, i8imm);
317 let ParserMatchClass = X86MemAsmOperand;
318 let OperandType = "OPERAND_MEMORY";
321 let OperandType = "OPERAND_PCREL",
322 ParserMatchClass = X86AbsMemAsmOperand,
323 PrintMethod = "print_pcrel_imm" in {
324 def i32imm_pcrel : Operand<i32>;
325 def i16imm_pcrel : Operand<i16>;
327 def offset8 : Operand<i64>;
328 def offset16 : Operand<i64>;
329 def offset32 : Operand<i64>;
330 def offset64 : Operand<i64>;
332 // Branch targets have OtherVT type and print as pc-relative values.
333 def brtarget : Operand<OtherVT>;
334 def brtarget8 : Operand<OtherVT>;
338 def SSECC : Operand<i8> {
339 let PrintMethod = "printSSECC";
340 let OperandType = "OPERAND_IMMEDIATE";
343 class ImmSExtAsmOperandClass : AsmOperandClass {
344 let SuperClasses = [ImmAsmOperand];
345 let RenderMethod = "addImmOperands";
348 class ImmZExtAsmOperandClass : AsmOperandClass {
349 let SuperClasses = [ImmAsmOperand];
350 let RenderMethod = "addImmOperands";
353 // Sign-extended immediate classes. We don't need to define the full lattice
354 // here because there is no instruction with an ambiguity between ImmSExti64i32
357 // The strange ranges come from the fact that the assembler always works with
358 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
359 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
362 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
363 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
364 let Name = "ImmSExti64i32";
367 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
368 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
369 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
370 let Name = "ImmSExti16i8";
371 let SuperClasses = [ImmSExti64i32AsmOperand];
374 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
375 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
376 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
377 let Name = "ImmSExti32i8";
381 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
382 let Name = "ImmZExtu32u8";
387 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
388 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
389 let Name = "ImmSExti64i8";
390 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
391 ImmSExti64i32AsmOperand];
394 // A couple of more descriptive operand definitions.
395 // 16-bits but only 8 bits are significant.
396 def i16i8imm : Operand<i16> {
397 let ParserMatchClass = ImmSExti16i8AsmOperand;
398 let OperandType = "OPERAND_IMMEDIATE";
400 // 32-bits but only 8 bits are significant.
401 def i32i8imm : Operand<i32> {
402 let ParserMatchClass = ImmSExti32i8AsmOperand;
403 let OperandType = "OPERAND_IMMEDIATE";
405 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
406 def u32u8imm : Operand<i32> {
407 let ParserMatchClass = ImmZExtu32u8AsmOperand;
408 let OperandType = "OPERAND_IMMEDIATE";
411 // 64-bits but only 32 bits are significant.
412 def i64i32imm : Operand<i64> {
413 let ParserMatchClass = ImmSExti64i32AsmOperand;
414 let OperandType = "OPERAND_IMMEDIATE";
417 // 64-bits but only 32 bits are significant, and those bits are treated as being
419 def i64i32imm_pcrel : Operand<i64> {
420 let PrintMethod = "print_pcrel_imm";
421 let ParserMatchClass = X86AbsMemAsmOperand;
422 let OperandType = "OPERAND_PCREL";
425 // 64-bits but only 8 bits are significant.
426 def i64i8imm : Operand<i64> {
427 let ParserMatchClass = ImmSExti64i8AsmOperand;
428 let OperandType = "OPERAND_IMMEDIATE";
431 def lea64_32mem : Operand<i32> {
432 let PrintMethod = "printi32mem";
433 let AsmOperandLowerMethod = "lower_lea64_32mem";
434 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
435 let ParserMatchClass = X86MemAsmOperand;
439 //===----------------------------------------------------------------------===//
440 // X86 Complex Pattern Definitions.
443 // Define X86 specific addressing mode.
444 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
445 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
446 [add, sub, mul, X86mul_imm, shl, or, frameindex],
448 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
449 [tglobaltlsaddr], []>;
451 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
452 [add, sub, mul, X86mul_imm, shl, or, frameindex,
455 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
456 [tglobaltlsaddr], []>;
458 //===----------------------------------------------------------------------===//
459 // X86 Instruction Predicate Definitions.
460 def HasCMov : Predicate<"Subtarget->hasCMov()">;
461 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
463 def HasMMX : Predicate<"Subtarget->hasMMX()">;
464 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
465 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
466 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
467 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
468 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
469 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
470 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
471 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
472 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
474 def HasAVX : Predicate<"Subtarget->hasAVX()">;
475 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
476 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
478 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
479 def HasAES : Predicate<"Subtarget->hasAES()">;
480 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
481 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
482 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
483 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
484 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
485 def HasF16C : Predicate<"Subtarget->hasF16C()">;
486 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
487 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
488 def HasBMI : Predicate<"Subtarget->hasBMI()">;
489 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
490 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
491 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
492 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
493 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
494 AssemblerPredicate<"!Mode64Bit">;
495 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
496 AssemblerPredicate<"Mode64Bit">;
497 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
498 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
499 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
500 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
501 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
502 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
503 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
504 "TM.getCodeModel() != CodeModel::Kernel">;
505 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
506 "TM.getCodeModel() == CodeModel::Kernel">;
507 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
508 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
509 def OptForSize : Predicate<"OptForSize">;
510 def OptForSpeed : Predicate<"!OptForSize">;
511 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
512 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
514 //===----------------------------------------------------------------------===//
515 // X86 Instruction Format Definitions.
518 include "X86InstrFormats.td"
520 //===----------------------------------------------------------------------===//
521 // Pattern fragments.
524 // X86 specific condition code. These correspond to CondCode in
525 // X86InstrInfo.h. They must be kept in synch.
526 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
527 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
528 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
529 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
530 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
531 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
532 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
533 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
534 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
535 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
536 def X86_COND_NO : PatLeaf<(i8 10)>;
537 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
538 def X86_COND_NS : PatLeaf<(i8 12)>;
539 def X86_COND_O : PatLeaf<(i8 13)>;
540 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
541 def X86_COND_S : PatLeaf<(i8 15)>;
543 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
544 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
545 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
546 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
549 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
552 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
554 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
556 def i64immZExt32SExt8 : ImmLeaf<i64, [{
557 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
560 // Helper fragments for loads.
561 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
562 // known to be 32-bit aligned or better. Ditto for i8 to i16.
563 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
564 LoadSDNode *LD = cast<LoadSDNode>(N);
565 ISD::LoadExtType ExtType = LD->getExtensionType();
566 if (ExtType == ISD::NON_EXTLOAD)
568 if (ExtType == ISD::EXTLOAD)
569 return LD->getAlignment() >= 2 && !LD->isVolatile();
573 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
574 LoadSDNode *LD = cast<LoadSDNode>(N);
575 ISD::LoadExtType ExtType = LD->getExtensionType();
576 if (ExtType == ISD::EXTLOAD)
577 return LD->getAlignment() >= 2 && !LD->isVolatile();
581 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
582 LoadSDNode *LD = cast<LoadSDNode>(N);
583 ISD::LoadExtType ExtType = LD->getExtensionType();
584 if (ExtType == ISD::NON_EXTLOAD)
586 if (ExtType == ISD::EXTLOAD)
587 return LD->getAlignment() >= 4 && !LD->isVolatile();
591 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
592 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
593 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
594 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
595 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
597 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
598 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
599 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
600 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
601 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
602 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
604 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
605 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
606 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
607 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
608 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
609 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
610 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
611 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
612 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
613 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
615 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
616 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
617 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
618 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
619 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
620 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
621 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
622 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
623 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
624 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
627 // An 'and' node with a single use.
628 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
629 return N->hasOneUse();
631 // An 'srl' node with a single use.
632 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
633 return N->hasOneUse();
635 // An 'trunc' node with a single use.
636 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
637 return N->hasOneUse();
640 //===----------------------------------------------------------------------===//
645 let neverHasSideEffects = 1 in {
646 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
647 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
648 "nop{w}\t$zero", []>, TB, OpSize;
649 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
650 "nop{l}\t$zero", []>, TB;
654 // Constructing a stack frame.
655 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
656 "enter\t$len, $lvl", []>;
658 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
659 def LEAVE : I<0xC9, RawFrm,
660 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
662 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
663 def LEAVE64 : I<0xC9, RawFrm,
664 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
666 //===----------------------------------------------------------------------===//
667 // Miscellaneous Instructions.
670 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
672 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
674 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
675 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
677 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
679 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
680 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
682 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
683 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
684 Requires<[In32BitMode]>;
687 let mayStore = 1 in {
688 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
690 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
691 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
693 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
695 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
696 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
698 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
699 "push{l}\t$imm", []>;
700 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
701 "push{w}\t$imm", []>, OpSize;
702 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
703 "push{l}\t$imm", []>;
705 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
706 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
707 Requires<[In32BitMode]>;
712 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
714 def POP64r : I<0x58, AddRegFrm,
715 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
716 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
717 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
719 let mayStore = 1 in {
720 def PUSH64r : I<0x50, AddRegFrm,
721 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
722 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
723 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
727 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
728 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
729 "push{q}\t$imm", []>;
730 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
731 "push{q}\t$imm", []>;
732 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
733 "push{q}\t$imm", []>;
736 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
737 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
738 Requires<[In64BitMode]>;
739 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
740 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
741 Requires<[In64BitMode]>;
745 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
746 mayLoad=1, neverHasSideEffects=1 in {
747 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
748 Requires<[In32BitMode]>;
750 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
751 mayStore=1, neverHasSideEffects=1 in {
752 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
753 Requires<[In32BitMode]>;
756 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
757 def BSWAP32r : I<0xC8, AddRegFrm,
758 (outs GR32:$dst), (ins GR32:$src),
760 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
762 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
764 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
765 } // Constraints = "$src = $dst"
767 // Bit scan instructions.
768 let Defs = [EFLAGS] in {
769 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
770 "bsf{w}\t{$src, $dst|$dst, $src}",
771 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
772 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
773 "bsf{w}\t{$src, $dst|$dst, $src}",
774 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
776 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
777 "bsf{l}\t{$src, $dst|$dst, $src}",
778 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
779 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
780 "bsf{l}\t{$src, $dst|$dst, $src}",
781 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
782 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
783 "bsf{q}\t{$src, $dst|$dst, $src}",
784 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
785 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
786 "bsf{q}\t{$src, $dst|$dst, $src}",
787 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
789 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
790 "bsr{w}\t{$src, $dst|$dst, $src}",
791 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
792 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
793 "bsr{w}\t{$src, $dst|$dst, $src}",
794 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
796 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
797 "bsr{l}\t{$src, $dst|$dst, $src}",
798 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
799 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
800 "bsr{l}\t{$src, $dst|$dst, $src}",
801 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
802 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
803 "bsr{q}\t{$src, $dst|$dst, $src}",
804 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
805 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
806 "bsr{q}\t{$src, $dst|$dst, $src}",
807 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
811 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
812 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
813 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
814 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
815 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
816 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
819 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
820 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
821 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
822 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
823 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
824 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
825 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
826 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
827 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
829 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
830 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
831 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
832 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
834 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
835 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
836 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
837 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
840 //===----------------------------------------------------------------------===//
841 // Move Instructions.
844 let neverHasSideEffects = 1 in {
845 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
846 "mov{b}\t{$src, $dst|$dst, $src}", []>;
847 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
848 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
849 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
850 "mov{l}\t{$src, $dst|$dst, $src}", []>;
851 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
852 "mov{q}\t{$src, $dst|$dst, $src}", []>;
854 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
855 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
856 "mov{b}\t{$src, $dst|$dst, $src}",
857 [(set GR8:$dst, imm:$src)]>;
858 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
859 "mov{w}\t{$src, $dst|$dst, $src}",
860 [(set GR16:$dst, imm:$src)]>, OpSize;
861 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
862 "mov{l}\t{$src, $dst|$dst, $src}",
863 [(set GR32:$dst, imm:$src)]>;
864 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
865 "movabs{q}\t{$src, $dst|$dst, $src}",
866 [(set GR64:$dst, imm:$src)]>;
867 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
868 "mov{q}\t{$src, $dst|$dst, $src}",
869 [(set GR64:$dst, i64immSExt32:$src)]>;
872 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
873 "mov{b}\t{$src, $dst|$dst, $src}",
874 [(store (i8 imm:$src), addr:$dst)]>;
875 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
876 "mov{w}\t{$src, $dst|$dst, $src}",
877 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
878 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
879 "mov{l}\t{$src, $dst|$dst, $src}",
880 [(store (i32 imm:$src), addr:$dst)]>;
881 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
882 "mov{q}\t{$src, $dst|$dst, $src}",
883 [(store i64immSExt32:$src, addr:$dst)]>;
885 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
886 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
887 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
888 "mov{b}\t{$src, %al|AL, $src}", []>,
889 Requires<[In32BitMode]>;
890 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
891 "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
892 Requires<[In32BitMode]>;
893 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
894 "mov{l}\t{$src, %eax|EAX, $src}", []>,
895 Requires<[In32BitMode]>;
896 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
897 "mov{b}\t{%al, $dst|$dst, AL}", []>,
898 Requires<[In32BitMode]>;
899 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
900 "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
901 Requires<[In32BitMode]>;
902 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
903 "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
904 Requires<[In32BitMode]>;
906 // FIXME: These definitions are utterly broken
907 // Just leave them commented out for now because they're useless outside
908 // of the large code model, and most compilers won't generate the instructions
911 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
912 "mov{q}\t{$src, %rax|RAX, $src}", []>;
913 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
914 "mov{q}\t{$src, %rax|RAX, $src}", []>;
915 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
916 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
917 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
918 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
922 let isCodeGenOnly = 1 in {
923 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
924 "mov{b}\t{$src, $dst|$dst, $src}", []>;
925 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
926 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
927 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
928 "mov{l}\t{$src, $dst|$dst, $src}", []>;
929 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
930 "mov{q}\t{$src, $dst|$dst, $src}", []>;
933 let canFoldAsLoad = 1, isReMaterializable = 1 in {
934 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
935 "mov{b}\t{$src, $dst|$dst, $src}",
936 [(set GR8:$dst, (loadi8 addr:$src))]>;
937 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
938 "mov{w}\t{$src, $dst|$dst, $src}",
939 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
940 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
941 "mov{l}\t{$src, $dst|$dst, $src}",
942 [(set GR32:$dst, (loadi32 addr:$src))]>;
943 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
944 "mov{q}\t{$src, $dst|$dst, $src}",
945 [(set GR64:$dst, (load addr:$src))]>;
948 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
949 "mov{b}\t{$src, $dst|$dst, $src}",
950 [(store GR8:$src, addr:$dst)]>;
951 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
952 "mov{w}\t{$src, $dst|$dst, $src}",
953 [(store GR16:$src, addr:$dst)]>, OpSize;
954 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
955 "mov{l}\t{$src, $dst|$dst, $src}",
956 [(store GR32:$src, addr:$dst)]>;
957 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
958 "mov{q}\t{$src, $dst|$dst, $src}",
959 [(store GR64:$src, addr:$dst)]>;
961 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
962 // that they can be used for copying and storing h registers, which can't be
963 // encoded when a REX prefix is present.
964 let isCodeGenOnly = 1 in {
965 let neverHasSideEffects = 1 in
966 def MOV8rr_NOREX : I<0x88, MRMDestReg,
967 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
968 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
970 def MOV8mr_NOREX : I<0x88, MRMDestMem,
971 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
972 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
973 let mayLoad = 1, neverHasSideEffects = 1,
974 canFoldAsLoad = 1, isReMaterializable = 1 in
975 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
976 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
977 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
981 // Condition code ops, incl. set if equal/not equal/...
982 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
983 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
984 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
985 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
988 //===----------------------------------------------------------------------===//
989 // Bit tests instructions: BT, BTS, BTR, BTC.
991 let Defs = [EFLAGS] in {
992 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
993 "bt{w}\t{$src2, $src1|$src1, $src2}",
994 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
995 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
996 "bt{l}\t{$src2, $src1|$src1, $src2}",
997 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
998 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
999 "bt{q}\t{$src2, $src1|$src1, $src2}",
1000 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1002 // Unlike with the register+register form, the memory+register form of the
1003 // bt instruction does not ignore the high bits of the index. From ISel's
1004 // perspective, this is pretty bizarre. Make these instructions disassembly
1007 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1008 "bt{w}\t{$src2, $src1|$src1, $src2}",
1009 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1010 // (implicit EFLAGS)]
1012 >, OpSize, TB, Requires<[FastBTMem]>;
1013 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1014 "bt{l}\t{$src2, $src1|$src1, $src2}",
1015 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1016 // (implicit EFLAGS)]
1018 >, TB, Requires<[FastBTMem]>;
1019 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1020 "bt{q}\t{$src2, $src1|$src1, $src2}",
1021 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1022 // (implicit EFLAGS)]
1026 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1027 "bt{w}\t{$src2, $src1|$src1, $src2}",
1028 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1030 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1031 "bt{l}\t{$src2, $src1|$src1, $src2}",
1032 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1033 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1034 "bt{q}\t{$src2, $src1|$src1, $src2}",
1035 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1037 // Note that these instructions don't need FastBTMem because that
1038 // only applies when the other operand is in a register. When it's
1039 // an immediate, bt is still fast.
1040 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1041 "bt{w}\t{$src2, $src1|$src1, $src2}",
1042 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1044 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1045 "bt{l}\t{$src2, $src1|$src1, $src2}",
1046 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1048 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1049 "bt{q}\t{$src2, $src1|$src1, $src2}",
1050 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1051 i64immSExt8:$src2))]>, TB;
1054 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1055 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1056 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1057 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1058 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1059 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1060 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1061 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1062 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1063 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1064 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1065 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1066 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1067 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1068 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1069 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1070 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1071 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1072 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1073 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1074 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1075 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1076 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1077 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1079 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1080 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1081 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1082 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1083 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1084 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1085 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1086 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1087 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1088 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1089 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1090 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1091 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1092 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1093 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1094 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1095 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1096 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1097 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1098 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1099 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1100 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1101 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1102 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1104 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1105 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1106 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1107 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1108 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1109 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1110 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1111 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1112 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1113 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1114 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1115 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1116 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1117 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1118 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1119 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1120 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1121 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1122 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1123 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1124 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1125 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1126 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1127 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1128 } // Defs = [EFLAGS]
1131 //===----------------------------------------------------------------------===//
1136 // Atomic swap. These are just normal xchg instructions. But since a memory
1137 // operand is referenced, the atomicity is ensured.
1138 let Constraints = "$val = $dst" in {
1139 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1140 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1141 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1142 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1143 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1144 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1146 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1147 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1148 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1149 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1150 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1151 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1153 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1154 "xchg{b}\t{$val, $src|$src, $val}", []>;
1155 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1156 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1157 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1158 "xchg{l}\t{$val, $src|$src, $val}", []>;
1159 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1160 "xchg{q}\t{$val, $src|$src, $val}", []>;
1163 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1164 "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
1165 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1166 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
1167 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1168 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1169 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1170 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
1171 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1172 "xchg{q}\t{$src, %rax|RAX, $src}", []>;
1176 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1177 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1178 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1179 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1180 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1181 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1182 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1183 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1185 let mayLoad = 1, mayStore = 1 in {
1186 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1187 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1188 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1189 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1190 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1191 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1192 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1193 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1197 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1198 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1199 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1200 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1201 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1202 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1203 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1204 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1206 let mayLoad = 1, mayStore = 1 in {
1207 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1208 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1209 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1210 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1211 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1212 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1213 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1214 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1217 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1218 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1219 "cmpxchg8b\t$dst", []>, TB;
1221 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1222 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1223 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1227 // Lock instruction prefix
1228 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1230 // Rex64 instruction prefix
1231 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1233 // Data16 instruction prefix
1234 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1236 // Repeat string operation instruction prefixes
1237 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1238 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1239 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1240 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1241 // Repeat while not equal (used with CMPS and SCAS)
1242 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1246 // String manipulation instructions
1247 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1248 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1249 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1250 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1252 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1253 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1254 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1257 // Flag instructions
1258 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1259 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1260 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1261 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1262 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1263 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1264 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1266 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1268 // Table lookup instructions
1269 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1271 // ASCII Adjust After Addition
1272 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1273 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1275 // ASCII Adjust AX Before Division
1276 // sets AL, AH and EFLAGS and uses AL and AH
1277 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1278 "aad\t$src", []>, Requires<[In32BitMode]>;
1280 // ASCII Adjust AX After Multiply
1281 // sets AL, AH and EFLAGS and uses AL
1282 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1283 "aam\t$src", []>, Requires<[In32BitMode]>;
1285 // ASCII Adjust AL After Subtraction - sets
1286 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1287 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1289 // Decimal Adjust AL after Addition
1290 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1291 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1293 // Decimal Adjust AL after Subtraction
1294 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1295 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1297 // Check Array Index Against Bounds
1298 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1299 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1300 Requires<[In32BitMode]>;
1301 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1302 "bound\t{$src, $dst|$dst, $src}", []>,
1303 Requires<[In32BitMode]>;
1305 // Adjust RPL Field of Segment Selector
1306 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1307 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1308 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1309 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1311 //===----------------------------------------------------------------------===//
1312 // MOVBE Instructions
1314 let Predicates = [HasMOVBE] in {
1315 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1316 "movbe{w}\t{$src, $dst|$dst, $src}",
1317 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
1318 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1319 "movbe{l}\t{$src, $dst|$dst, $src}",
1320 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
1321 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1322 "movbe{q}\t{$src, $dst|$dst, $src}",
1323 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
1324 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1325 "movbe{w}\t{$src, $dst|$dst, $src}",
1326 [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
1327 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1328 "movbe{l}\t{$src, $dst|$dst, $src}",
1329 [(store (bswap GR32:$src), addr:$dst)]>, T8;
1330 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1331 "movbe{q}\t{$src, $dst|$dst, $src}",
1332 [(store (bswap GR64:$src), addr:$dst)]>, T8;
1335 //===----------------------------------------------------------------------===//
1336 // RDRAND Instruction
1338 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1339 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1340 "rdrand{w}\t$dst", []>, OpSize, TB;
1341 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1342 "rdrand{l}\t$dst", []>, TB;
1343 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1344 "rdrand{q}\t$dst", []>, TB;
1347 //===----------------------------------------------------------------------===//
1348 // LZCNT Instruction
1350 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1351 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1352 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1353 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1355 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1356 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1357 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1358 (implicit EFLAGS)]>, XS, OpSize;
1360 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1361 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1362 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1363 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1364 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1365 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1366 (implicit EFLAGS)]>, XS;
1368 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1369 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1370 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1372 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1373 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1374 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1375 (implicit EFLAGS)]>, XS;
1378 //===----------------------------------------------------------------------===//
1381 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1382 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1383 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1384 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1386 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1387 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1388 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1389 (implicit EFLAGS)]>, XS, OpSize;
1391 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1392 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1393 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1394 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1395 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1396 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1397 (implicit EFLAGS)]>, XS;
1399 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1400 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1401 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1403 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1404 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1405 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1406 (implicit EFLAGS)]>, XS;
1409 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1410 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1412 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1413 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1414 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1415 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1416 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1417 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1421 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1422 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1423 X86blsr_flag, loadi32>;
1424 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1425 X86blsr_flag, loadi64>, VEX_W;
1426 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1427 X86blsmsk_flag, loadi32>;
1428 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1429 X86blsmsk_flag, loadi64>, VEX_W;
1430 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1431 X86blsi_flag, loadi32>;
1432 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1433 X86blsi_flag, loadi64>, VEX_W;
1436 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1437 X86MemOperand x86memop, Intrinsic Int,
1439 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1440 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1441 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1443 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1444 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1445 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1446 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1449 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1450 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1451 int_x86_bmi_bextr_32, loadi32>;
1452 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1453 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1456 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1457 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1458 int_x86_bmi_bzhi_32, loadi32>;
1459 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1460 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1463 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1464 X86MemOperand x86memop, Intrinsic Int,
1466 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1467 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1468 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1470 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1471 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1472 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1475 let Predicates = [HasBMI2] in {
1476 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1477 int_x86_bmi_pdep_32, loadi32>, T8XD;
1478 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1479 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1480 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1481 int_x86_bmi_pext_32, loadi32>, T8XS;
1482 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1483 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1486 //===----------------------------------------------------------------------===//
1488 //===----------------------------------------------------------------------===//
1490 include "X86InstrArithmetic.td"
1491 include "X86InstrCMovSetCC.td"
1492 include "X86InstrExtension.td"
1493 include "X86InstrControl.td"
1494 include "X86InstrShiftRotate.td"
1496 // X87 Floating Point Stack.
1497 include "X86InstrFPStack.td"
1499 // SIMD support (SSE, MMX and AVX)
1500 include "X86InstrFragmentsSIMD.td"
1502 // FMA - Fused Multiply-Add support (requires FMA)
1503 include "X86InstrFMA.td"
1505 // SSE, MMX and 3DNow! vector support.
1506 include "X86InstrSSE.td"
1507 include "X86InstrMMX.td"
1508 include "X86Instr3DNow.td"
1510 include "X86InstrVMX.td"
1512 // System instructions.
1513 include "X86InstrSystem.td"
1515 // Compiler Pseudo Instructions and Pat Patterns
1516 include "X86InstrCompiler.td"
1518 //===----------------------------------------------------------------------===//
1519 // Assembler Mnemonic Aliases
1520 //===----------------------------------------------------------------------===//
1522 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1523 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1525 def : MnemonicAlias<"cbw", "cbtw">;
1526 def : MnemonicAlias<"cwde", "cwtl">;
1527 def : MnemonicAlias<"cwd", "cwtd">;
1528 def : MnemonicAlias<"cdq", "cltd">;
1529 def : MnemonicAlias<"cdqe", "cltq">;
1530 def : MnemonicAlias<"cqo", "cqto">;
1532 // lret maps to lretl, it is not ambiguous with lretq.
1533 def : MnemonicAlias<"lret", "lretl">;
1535 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1536 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1538 def : MnemonicAlias<"loopz", "loope">;
1539 def : MnemonicAlias<"loopnz", "loopne">;
1541 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1542 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1543 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1544 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1545 def : MnemonicAlias<"popfd", "popfl">;
1547 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1548 // all modes. However: "push (addr)" and "push $42" should default to
1549 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1550 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1551 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1552 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1553 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1554 def : MnemonicAlias<"pushfd", "pushfl">;
1556 def : MnemonicAlias<"repe", "rep">;
1557 def : MnemonicAlias<"repz", "rep">;
1558 def : MnemonicAlias<"repnz", "repne">;
1560 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1561 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1563 def : MnemonicAlias<"salb", "shlb">;
1564 def : MnemonicAlias<"salw", "shlw">;
1565 def : MnemonicAlias<"sall", "shll">;
1566 def : MnemonicAlias<"salq", "shlq">;
1568 def : MnemonicAlias<"smovb", "movsb">;
1569 def : MnemonicAlias<"smovw", "movsw">;
1570 def : MnemonicAlias<"smovl", "movsl">;
1571 def : MnemonicAlias<"smovq", "movsq">;
1573 def : MnemonicAlias<"ud2a", "ud2">;
1574 def : MnemonicAlias<"verrw", "verr">;
1576 // System instruction aliases.
1577 def : MnemonicAlias<"iret", "iretl">;
1578 def : MnemonicAlias<"sysret", "sysretl">;
1579 def : MnemonicAlias<"sysexit", "sysexitl">;
1581 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1582 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1583 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1584 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1585 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1586 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1587 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1588 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1591 // Floating point stack aliases.
1592 def : MnemonicAlias<"fcmovz", "fcmove">;
1593 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1594 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1595 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1596 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1597 def : MnemonicAlias<"fcomip", "fcompi">;
1598 def : MnemonicAlias<"fildq", "fildll">;
1599 def : MnemonicAlias<"fldcww", "fldcw">;
1600 def : MnemonicAlias<"fnstcww", "fnstcw">;
1601 def : MnemonicAlias<"fnstsww", "fnstsw">;
1602 def : MnemonicAlias<"fucomip", "fucompi">;
1603 def : MnemonicAlias<"fwait", "wait">;
1606 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1607 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1608 !strconcat(Prefix, NewCond, Suffix)>;
1610 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1611 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1612 /// example "setz" -> "sete".
1613 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1614 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1615 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1616 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1617 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1618 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1619 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1620 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1621 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1622 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1623 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1625 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1626 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1627 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1628 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1631 // Aliases for set<CC>
1632 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1633 // Aliases for j<CC>
1634 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1635 // Aliases for cmov<CC>{w,l,q}
1636 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1637 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1638 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1641 //===----------------------------------------------------------------------===//
1642 // Assembler Instruction Aliases
1643 //===----------------------------------------------------------------------===//
1645 // aad/aam default to base 10 if no operand is specified.
1646 def : InstAlias<"aad", (AAD8i8 10)>;
1647 def : InstAlias<"aam", (AAM8i8 10)>;
1649 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1650 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1653 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1654 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1655 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1656 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1658 // div and idiv aliases for explicit A register.
1659 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1660 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1661 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1662 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1663 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1664 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1665 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1666 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1667 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1668 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1669 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1670 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1671 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1672 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1673 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1674 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1678 // Various unary fpstack operations default to operating on on ST1.
1679 // For example, "fxch" -> "fxch %st(1)"
1680 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1681 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1682 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1683 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1684 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1685 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1686 def : InstAlias<"fxch", (XCH_F ST1)>;
1687 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1688 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1689 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1690 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1691 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1692 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1694 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1695 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1696 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1698 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1699 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1700 (Inst RST:$op), EmitAlias>;
1701 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1702 (Inst ST0), EmitAlias>;
1705 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1706 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1707 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1708 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1709 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1710 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1711 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1712 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1713 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1714 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1715 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1716 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1717 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1718 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1719 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1720 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1723 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1724 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1725 // solely because gas supports it.
1726 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1727 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1728 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1729 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1730 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1731 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1733 // We accept "fnstsw %eax" even though it only writes %ax.
1734 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1735 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1736 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1738 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1739 // this is compatible with what GAS does.
1740 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1741 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1742 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1743 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1745 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1746 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1747 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1748 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1749 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1750 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1751 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1753 // inb %dx -> inb %al, %dx
1754 def : InstAlias<"inb %dx", (IN8rr)>;
1755 def : InstAlias<"inw %dx", (IN16rr)>;
1756 def : InstAlias<"inl %dx", (IN32rr)>;
1757 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1758 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1759 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1762 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1763 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1764 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1765 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1766 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1767 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1768 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1770 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1771 // the move. All segment/mem forms are equivalent, this has the shortest
1773 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1774 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1776 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1777 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1779 // Match 'movq GR64, MMX' as an alias for movd.
1780 def : InstAlias<"movq $src, $dst",
1781 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1782 def : InstAlias<"movq $src, $dst",
1783 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1785 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1786 // alias for movsl. (as in rep; movsd)
1787 def : InstAlias<"movsd", (MOVSD)>;
1790 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1791 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1792 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1793 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1794 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1795 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1796 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1799 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1800 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1801 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1802 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1803 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1804 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1805 // Note: No GR32->GR64 movzx form.
1807 // outb %dx -> outb %al, %dx
1808 def : InstAlias<"outb %dx", (OUT8rr)>;
1809 def : InstAlias<"outw %dx", (OUT16rr)>;
1810 def : InstAlias<"outl %dx", (OUT32rr)>;
1811 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1812 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1813 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1815 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1816 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1817 // errors, since its encoding is the most compact.
1818 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1820 // shld/shrd op,op -> shld op, op, 1
1821 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1822 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1823 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1824 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1825 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1826 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1828 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1829 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1830 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1831 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1832 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1833 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1835 /* FIXME: This is disabled because the asm matcher is currently incapable of
1836 * matching a fixed immediate like $1.
1837 // "shl X, $1" is an alias for "shl X".
1838 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1839 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1840 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1841 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1842 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1843 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1844 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1845 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1846 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1847 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1848 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1849 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1850 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1851 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1852 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1853 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1854 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1857 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1858 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1859 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1860 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1863 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1864 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1865 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1866 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1867 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1869 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1870 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1871 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1872 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1873 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
1875 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
1876 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
1877 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
1878 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
1879 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;