1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
19 class X86MemOperand<ValueType Ty> : Operand<Ty> {
20 let NumMIOperands = 4;
21 let PrintMethod = "printMemoryOperand";
23 def SSECC : Operand<i8> {
24 let PrintMethod = "printSSECC";
27 def i8mem : X86MemOperand<i8>;
28 def i16mem : X86MemOperand<i16>;
29 def i32mem : X86MemOperand<i32>;
30 def i64mem : X86MemOperand<i64>;
31 def f32mem : X86MemOperand<f32>;
32 def f64mem : X86MemOperand<f64>;
33 def f80mem : X86MemOperand<f80>;
35 // PCRelative calls need special operand formatting.
36 let PrintMethod = "printCallOperand" in
37 def calltarget : Operand<i32>;
39 // Format specifies the encoding used by the instruction. This is part of the
40 // ad-hoc solution used to emit machine instruction encodings by our machine
42 class Format<bits<5> val> {
46 def Pseudo : Format<0>; def RawFrm : Format<1>;
47 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
48 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
49 def MRMSrcMem : Format<6>;
50 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
51 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
52 def MRM6r : Format<22>; def MRM7r : Format<23>;
53 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
54 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
55 def MRM6m : Format<30>; def MRM7m : Format<31>;
57 // ImmType - This specifies the immediate type used by an instruction. This is
58 // part of the ad-hoc solution used to emit machine instruction encodings by our
59 // machine code emitter.
60 class ImmType<bits<2> val> {
63 def NoImm : ImmType<0>;
64 def Imm8 : ImmType<1>;
65 def Imm16 : ImmType<2>;
66 def Imm32 : ImmType<3>;
68 // FPFormat - This specifies what form this FP instruction has. This is used by
69 // the Floating-Point stackifier pass.
70 class FPFormat<bits<3> val> {
73 def NotFP : FPFormat<0>;
74 def ZeroArgFP : FPFormat<1>;
75 def OneArgFP : FPFormat<2>;
76 def OneArgFPRW : FPFormat<3>;
77 def TwoArgFP : FPFormat<4>;
78 def CompareFP : FPFormat<5>;
79 def CondMovFP : FPFormat<6>;
80 def SpecialFP : FPFormat<7>;
83 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
85 let Namespace = "X86";
87 bits<8> Opcode = opcod;
89 bits<5> FormBits = Form.Value;
91 bits<2> ImmTypeBits = ImmT.Value;
93 dag OperandList = ops;
94 string AsmString = AsmStr;
97 // Attributes specific to X86 instructions...
99 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
101 bits<4> Prefix = 0; // Which prefix byte does this inst have?
102 FPFormat FPForm; // What flavor of FP instruction is this?
103 bits<3> FPFormBits = 0;
106 class Imp<list<Register> uses, list<Register> defs> {
107 list<Register> Uses = uses;
108 list<Register> Defs = defs;
112 // Prefix byte classes which are used to indicate to the ad-hoc machine code
113 // emitter that various prefix bytes are required.
114 class OpSize { bit hasOpSizePrefix = 1; }
115 class TB { bits<4> Prefix = 1; }
116 class REP { bits<4> Prefix = 2; }
117 class D8 { bits<4> Prefix = 3; }
118 class D9 { bits<4> Prefix = 4; }
119 class DA { bits<4> Prefix = 5; }
120 class DB { bits<4> Prefix = 6; }
121 class DC { bits<4> Prefix = 7; }
122 class DD { bits<4> Prefix = 8; }
123 class DE { bits<4> Prefix = 9; }
124 class DF { bits<4> Prefix = 10; }
125 class XD { bits<4> Prefix = 11; }
126 class XS { bits<4> Prefix = 12; }
129 //===----------------------------------------------------------------------===//
130 // Instruction templates...
132 class I<bits<8> o, Format f, dag ops, string asm>
133 : X86Inst<o, f, NoImm, ops, asm>;
134 class Ii8 <bits<8> o, Format f, dag ops, string asm>
135 : X86Inst<o, f, Imm8 , ops, asm>;
136 class Ii16<bits<8> o, Format f, dag ops, string asm>
137 : X86Inst<o, f, Imm16, ops, asm>;
138 class Ii32<bits<8> o, Format f, dag ops, string asm>
139 : X86Inst<o, f, Imm32, ops, asm>;
141 //===----------------------------------------------------------------------===//
142 // Instruction list...
145 def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">; // PHI node.
146 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
148 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm), "#ADJCALLSTACKDOWN">;
149 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm, i32imm), "#ADJCALLSTACKUP">;
150 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE">;
151 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF">;
152 let isTerminator = 1 in
153 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
154 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
156 //===----------------------------------------------------------------------===//
157 // Control Flow Instructions...
160 // Return instructions.
161 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
162 def RET : I<0xC3, RawFrm, (ops), "ret">;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
164 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt">;
166 // All branches are RawFrm, Void, Branch, and Terminators
167 let isBranch = 1, isTerminator = 1 in
168 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
171 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
172 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
173 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
174 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
175 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
176 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
177 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
178 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
179 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
180 def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB;
181 def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB;
182 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
183 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
184 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
185 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
188 //===----------------------------------------------------------------------===//
189 // Call Instructions...
192 // All calls clobber the non-callee saved registers...
193 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
194 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
195 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
196 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">;
197 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">;
201 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
202 def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">;
203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
204 def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL">;
205 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
206 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst # TAIL CALL">;
208 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
209 // way, except that it is marked as being a terminator. This causes the epilog
210 // inserter to insert reloads of callee saved registers BEFORE this. We need
211 // this until we have a more accurate way of tracking where the stack pointer is
212 // within a function.
213 let isTerminator = 1, isTwoAddress = 1 in
214 def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
215 "add{l} {$src2, $dst|$dst, $src2}">;
217 //===----------------------------------------------------------------------===//
218 // Miscellaneous Instructions...
220 def LEAVE : I<0xC9, RawFrm,
221 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
222 def POP32r : I<0x58, AddRegFrm,
223 (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>;
225 let isTwoAddress = 1 in // R32 = bswap R32
226 def BSWAP32r : I<0xC8, AddRegFrm,
227 (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB;
229 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
230 (ops R8:$src1, R8:$src2),
231 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
232 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
233 (ops R16:$src1, R16:$src2),
234 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
235 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
236 (ops R32:$src1, R32:$src2),
237 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
239 def XCHG8mr : I<0x86, MRMDestMem,
240 (ops i8mem:$src1, R8:$src2),
241 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
242 def XCHG16mr : I<0x87, MRMDestMem,
243 (ops i16mem:$src1, R16:$src2),
244 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
245 def XCHG32mr : I<0x87, MRMDestMem,
246 (ops i32mem:$src1, R32:$src2),
247 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
248 def XCHG8rm : I<0x86, MRMSrcMem,
249 (ops R8:$src1, i8mem:$src2),
250 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
251 def XCHG16rm : I<0x87, MRMSrcMem,
252 (ops R16:$src1, i16mem:$src2),
253 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
254 def XCHG32rm : I<0x87, MRMSrcMem,
255 (ops R32:$src1, i32mem:$src2),
256 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
258 def LEA16r : I<0x8D, MRMSrcMem,
259 (ops R16:$dst, i32mem:$src),
260 "lea{w} {$src|$dst}, {$dst|$src}">, OpSize;
261 def LEA32r : I<0x8D, MRMSrcMem,
262 (ops R32:$dst, i32mem:$src),
263 "lea{l} {$src|$dst}, {$dst|$src}">;
266 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">,
267 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
268 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">,
269 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
270 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">,
271 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
273 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">,
274 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
275 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">,
276 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
277 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">,
278 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
281 //===----------------------------------------------------------------------===//
282 // Input/Output Instructions...
284 def IN8rr : I<0xEC, RawFrm, (ops),
285 "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>;
286 def IN16rr : I<0xED, RawFrm, (ops),
287 "in{w} {%dx, %ax|%AX, %DX}">, Imp<[DX], [AX]>, OpSize;
288 def IN32rr : I<0xED, RawFrm, (ops),
289 "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>;
291 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
292 "in{b} {$port, %al|%AL, $port}">, Imp<[], [AL]>;
293 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
294 "in{w} {$port, %ax|%AX, $port}">, Imp<[], [AX]>, OpSize;
295 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
296 "in{l} {$port, %eax|%EAX, $port}">, Imp<[],[EAX]>;
298 def OUT8rr : I<0xEE, RawFrm, (ops),
299 "out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>;
300 def OUT16rr : I<0xEF, RawFrm, (ops),
301 "out{w} {%ax, %dx|%DX, %AX}">, Imp<[DX, AX], []>, OpSize;
302 def OUT32rr : I<0xEF, RawFrm, (ops),
303 "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>;
305 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
306 "out{b} {%al, $port|$port, %AL}">, Imp<[AL], []>;
307 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
308 "out{w} {%ax, $port|$port, %AX}">, Imp<[AX], []>, OpSize;
309 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
310 "out{l} {%eax, $port|$port, %EAX}">, Imp<[EAX], []>;
312 //===----------------------------------------------------------------------===//
313 // Move Instructions...
315 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
316 "mov{b} {$src, $dst|$dst, $src}">;
317 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
318 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
319 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
320 "mov{l} {$src, $dst|$dst, $src}">;
321 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
322 "mov{b} {$src, $dst|$dst, $src}">;
323 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
324 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
325 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
326 "mov{l} {$src, $dst|$dst, $src}">;
327 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
328 "mov{b} {$src, $dst|$dst, $src}">;
329 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
330 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
331 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
332 "mov{l} {$src, $dst|$dst, $src}">;
334 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
335 "mov{b} {$src, $dst|$dst, $src}">;
336 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
337 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
338 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
339 "mov{l} {$src, $dst|$dst, $src}">;
341 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
342 "mov{b} {$src, $dst|$dst, $src}">;
343 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
344 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
345 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
346 "mov{l} {$src, $dst|$dst, $src}">;
348 //===----------------------------------------------------------------------===//
349 // Fixed-Register Multiplication and Division Instructions...
352 // Extra precision multiplication
353 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">,
354 Imp<[AL],[AX]>; // AL,AH = AL*R8
355 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">,
356 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
357 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">,
358 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
359 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
360 "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
361 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
362 "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
363 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
364 "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
366 def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src">,
367 Imp<[AL],[AX]>; // AL,AH = AL*R8
368 def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src">,
369 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
370 def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src">,
371 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
372 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
373 "imul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
374 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
375 "imul{w} $src">, Imp<[AX],[AX,DX]>, OpSize;// AX,DX = AX*[mem16]
376 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
377 "imul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
379 // unsigned division/remainder
380 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
381 "div{b} $src">, Imp<[AX],[AX]>;
382 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
383 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
384 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
385 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
386 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
387 "div{b} $src">, Imp<[AX],[AX]>;
388 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
389 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
390 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
391 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
393 // Signed division/remainder.
394 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
395 "idiv{b} $src">, Imp<[AX],[AX]>;
396 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
397 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
398 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
399 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
400 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
401 "idiv{b} $src">, Imp<[AX],[AX]>;
402 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
403 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
404 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
405 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
407 // Sign-extenders for division.
408 def CBW : I<0x98, RawFrm, (ops),
409 "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL)
410 def CWD : I<0x99, RawFrm, (ops),
411 "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
412 def CDQ : I<0x99, RawFrm, (ops),
413 "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
416 //===----------------------------------------------------------------------===//
417 // Two address Instructions...
419 let isTwoAddress = 1 in {
422 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
423 (ops R16:$dst, R16:$src1, R16:$src2),
424 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
425 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
426 (ops R16:$dst, R16:$src1, i16mem:$src2),
427 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
428 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
429 (ops R32:$dst, R32:$src1, R32:$src2),
430 "cmovb {$src2, $dst|$dst, $src2}">, TB;
431 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
432 (ops R32:$dst, R32:$src1, i32mem:$src2),
433 "cmovb {$src2, $dst|$dst, $src2}">, TB;
435 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
436 (ops R16:$dst, R16:$src1, R16:$src2),
437 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
438 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
439 (ops R16:$dst, R16:$src1, i16mem:$src2),
440 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
441 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
442 (ops R32:$dst, R32:$src1, R32:$src2),
443 "cmovae {$src2, $dst|$dst, $src2}">, TB;
444 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
445 (ops R32:$dst, R32:$src1, i32mem:$src2),
446 "cmovae {$src2, $dst|$dst, $src2}">, TB;
448 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
449 (ops R16:$dst, R16:$src1, R16:$src2),
450 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
451 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
452 (ops R16:$dst, R16:$src1, i16mem:$src2),
453 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
454 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
455 (ops R32:$dst, R32:$src1, R32:$src2),
456 "cmove {$src2, $dst|$dst, $src2}">, TB;
457 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
458 (ops R32:$dst, R32:$src1, i32mem:$src2),
459 "cmove {$src2, $dst|$dst, $src2}">, TB;
461 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
462 (ops R16:$dst, R16:$src1, R16:$src2),
463 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
464 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
465 (ops R16:$dst, R16:$src1, i16mem:$src2),
466 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
467 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
468 (ops R32:$dst, R32:$src1, R32:$src2),
469 "cmovne {$src2, $dst|$dst, $src2}">, TB;
470 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
471 (ops R32:$dst, R32:$src1, i32mem:$src2),
472 "cmovne {$src2, $dst|$dst, $src2}">, TB;
474 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
475 (ops R16:$dst, R16:$src1, R16:$src2),
476 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
477 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
478 (ops R16:$dst, R16:$src1, i16mem:$src2),
479 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
480 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
481 (ops R32:$dst, R32:$src1, R32:$src2),
482 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
483 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
484 (ops R32:$dst, R32:$src1, i32mem:$src2),
485 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
487 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
488 (ops R16:$dst, R16:$src1, R16:$src2),
489 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
490 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
491 (ops R16:$dst, R16:$src1, i16mem:$src2),
492 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
493 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
494 (ops R32:$dst, R32:$src1, R32:$src2),
495 "cmova {$src2, $dst|$dst, $src2}">, TB;
496 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
497 (ops R32:$dst, R32:$src1, i32mem:$src2),
498 "cmova {$src2, $dst|$dst, $src2}">, TB;
500 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
501 (ops R16:$dst, R16:$src1, R16:$src2),
502 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
503 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
504 (ops R16:$dst, R16:$src1, i16mem:$src2),
505 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
506 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
507 (ops R32:$dst, R32:$src1, R32:$src2),
508 "cmovs {$src2, $dst|$dst, $src2}">, TB;
509 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
510 (ops R32:$dst, R32:$src1, i32mem:$src2),
511 "cmovs {$src2, $dst|$dst, $src2}">, TB;
513 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
514 (ops R16:$dst, R16:$src1, R16:$src2),
515 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
516 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
517 (ops R16:$dst, R16:$src1, i16mem:$src2),
518 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
519 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
520 (ops R32:$dst, R32:$src1, R32:$src2),
521 "cmovns {$src2, $dst|$dst, $src2}">, TB;
522 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
523 (ops R32:$dst, R32:$src1, i32mem:$src2),
524 "cmovns {$src2, $dst|$dst, $src2}">, TB;
526 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
527 (ops R16:$dst, R16:$src1, R16:$src2),
528 "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
529 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
530 (ops R16:$dst, R16:$src1, i16mem:$src2),
531 "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
532 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
533 (ops R32:$dst, R32:$src1, R32:$src2),
534 "cmovp {$src2, $dst|$dst, $src2}">, TB;
535 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
536 (ops R32:$dst, R32:$src1, i32mem:$src2),
537 "cmovp {$src2, $dst|$dst, $src2}">, TB;
540 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
541 (ops R16:$dst, R16:$src1, R16:$src2),
542 "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
543 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
544 (ops R16:$dst, R16:$src1, i16mem:$src2),
545 "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
546 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
547 (ops R32:$dst, R32:$src1, R32:$src2),
548 "cmovnp {$src2, $dst|$dst, $src2}">, TB;
549 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
550 (ops R32:$dst, R32:$src1, i32mem:$src2),
551 "cmovnp {$src2, $dst|$dst, $src2}">, TB;
554 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
555 (ops R16:$dst, R16:$src1, R16:$src2),
556 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
557 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
558 (ops R16:$dst, R16:$src1, i16mem:$src2),
559 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
560 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
561 (ops R32:$dst, R32:$src1, R32:$src2),
562 "cmovl {$src2, $dst|$dst, $src2}">, TB;
563 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
564 (ops R32:$dst, R32:$src1, i32mem:$src2),
565 "cmovl {$src2, $dst|$dst, $src2}">, TB;
567 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
568 (ops R16:$dst, R16:$src1, R16:$src2),
569 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
570 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
571 (ops R16:$dst, R16:$src1, i16mem:$src2),
572 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
573 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
574 (ops R32:$dst, R32:$src1, R32:$src2),
575 "cmovge {$src2, $dst|$dst, $src2}">, TB;
576 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
577 (ops R32:$dst, R32:$src1, i32mem:$src2),
578 "cmovge {$src2, $dst|$dst, $src2}">, TB;
580 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
581 (ops R16:$dst, R16:$src1, R16:$src2),
582 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
583 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
584 (ops R16:$dst, R16:$src1, i16mem:$src2),
585 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
586 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
587 (ops R32:$dst, R32:$src1, R32:$src2),
588 "cmovle {$src2, $dst|$dst, $src2}">, TB;
589 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
590 (ops R32:$dst, R32:$src1, i32mem:$src2),
591 "cmovle {$src2, $dst|$dst, $src2}">, TB;
593 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
594 (ops R16:$dst, R16:$src1, R16:$src2),
595 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
596 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
597 (ops R16:$dst, R16:$src1, i16mem:$src2),
598 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
599 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
600 (ops R32:$dst, R32:$src1, R32:$src2),
601 "cmovg {$src2, $dst|$dst, $src2}">, TB;
602 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
603 (ops R32:$dst, R32:$src1, i32mem:$src2),
604 "cmovg {$src2, $dst|$dst, $src2}">, TB;
606 // unary instructions
607 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">;
608 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize;
609 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">;
610 let isTwoAddress = 0 in {
611 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">;
612 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize;
613 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">;
616 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">;
617 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize;
618 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">;
619 let isTwoAddress = 0 in {
620 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">;
621 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize;
622 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">;
625 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">;
626 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
627 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize;
628 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">;
630 let isTwoAddress = 0 in {
631 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">;
632 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize;
633 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">;
636 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">;
637 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
638 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize;
639 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">;
642 let isTwoAddress = 0 in {
643 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">;
644 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize;
645 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">;
648 // Logical operators...
649 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
650 def AND8rr : I<0x20, MRMDestReg,
651 (ops R8 :$dst, R8 :$src1, R8 :$src2),
652 "and{b} {$src2, $dst|$dst, $src2}">;
653 def AND16rr : I<0x21, MRMDestReg,
654 (ops R16:$dst, R16:$src1, R16:$src2),
655 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
656 def AND32rr : I<0x21, MRMDestReg,
657 (ops R32:$dst, R32:$src1, R32:$src2),
658 "and{l} {$src2, $dst|$dst, $src2}">;
661 def AND8rm : I<0x22, MRMSrcMem,
662 (ops R8 :$dst, R8 :$src1, i8mem :$src2),
663 "and{b} {$src2, $dst|$dst, $src2}">;
664 def AND16rm : I<0x23, MRMSrcMem,
665 (ops R16:$dst, R16:$src1, i16mem:$src2),
666 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
667 def AND32rm : I<0x23, MRMSrcMem,
668 (ops R32:$dst, R32:$src1, i32mem:$src2),
669 "and{l} {$src2, $dst|$dst, $src2}">;
671 def AND8ri : Ii8<0x80, MRM4r,
672 (ops R8 :$dst, R8 :$src1, i8imm :$src2),
673 "and{b} {$src2, $dst|$dst, $src2}">;
674 def AND16ri : Ii16<0x81, MRM4r,
675 (ops R16:$dst, R16:$src1, i16imm:$src2),
676 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
677 def AND32ri : Ii32<0x81, MRM4r,
678 (ops R32:$dst, R32:$src1, i32imm:$src2),
679 "and{l} {$src2, $dst|$dst, $src2}">;
680 def AND16ri8 : Ii8<0x83, MRM4r,
681 (ops R16:$dst, R16:$src1, i8imm:$src2),
682 "and{w} {$src2, $dst|$dst, $src2}" >, OpSize;
683 def AND32ri8 : Ii8<0x83, MRM4r,
684 (ops R32:$dst, R32:$src1, i8imm:$src2),
685 "and{l} {$src2, $dst|$dst, $src2}">;
687 let isTwoAddress = 0 in {
688 def AND8mr : I<0x20, MRMDestMem,
689 (ops i8mem :$dst, R8 :$src),
690 "and{b} {$src, $dst|$dst, $src}">;
691 def AND16mr : I<0x21, MRMDestMem,
692 (ops i16mem:$dst, R16:$src),
693 "and{w} {$src, $dst|$dst, $src}">, OpSize;
694 def AND32mr : I<0x21, MRMDestMem,
695 (ops i32mem:$dst, R32:$src),
696 "and{l} {$src, $dst|$dst, $src}">;
697 def AND8mi : Ii8<0x80, MRM4m,
698 (ops i8mem :$dst, i8imm :$src),
699 "and{b} {$src, $dst|$dst, $src}">;
700 def AND16mi : Ii16<0x81, MRM4m,
701 (ops i16mem:$dst, i16imm:$src),
702 "and{w} {$src, $dst|$dst, $src}">, OpSize;
703 def AND32mi : Ii32<0x81, MRM4m,
704 (ops i32mem:$dst, i32imm:$src),
705 "and{l} {$src, $dst|$dst, $src}">;
706 def AND16mi8 : Ii8<0x83, MRM4m,
707 (ops i16mem:$dst, i8imm :$src),
708 "and{w} {$src, $dst|$dst, $src}">, OpSize;
709 def AND32mi8 : Ii8<0x83, MRM4m,
710 (ops i32mem:$dst, i8imm :$src),
711 "and{l} {$src, $dst|$dst, $src}">;
715 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
716 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
717 "or{b} {$src2, $dst|$dst, $src2}">;
718 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
719 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
720 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
721 "or{l} {$src2, $dst|$dst, $src2}">;
723 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
724 "or{b} {$src2, $dst|$dst, $src2}">;
725 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
726 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
727 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
728 "or{l} {$src2, $dst|$dst, $src2}">;
730 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
731 "or{b} {$src2, $dst|$dst, $src2}">;
732 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
733 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
734 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
735 "or{l} {$src2, $dst|$dst, $src2}">;
737 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
738 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
739 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
740 "or{l} {$src2, $dst|$dst, $src2}">;
741 let isTwoAddress = 0 in {
742 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
743 "or{b} {$src, $dst|$dst, $src}">;
744 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
745 "or{w} {$src, $dst|$dst, $src}">, OpSize;
746 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
747 "or{l} {$src, $dst|$dst, $src}">;
748 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
749 "or{b} {$src, $dst|$dst, $src}">;
750 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
751 "or{w} {$src, $dst|$dst, $src}">, OpSize;
752 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
753 "or{l} {$src, $dst|$dst, $src}">;
754 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
755 "or{w} {$src, $dst|$dst, $src}">, OpSize;
756 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
757 "or{l} {$src, $dst|$dst, $src}">;
761 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
762 def XOR8rr : I<0x30, MRMDestReg,
763 (ops R8 :$dst, R8 :$src1, R8 :$src2),
764 "xor{b} {$src2, $dst|$dst, $src2}">;
765 def XOR16rr : I<0x31, MRMDestReg,
766 (ops R16:$dst, R16:$src1, R16:$src2),
767 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
768 def XOR32rr : I<0x31, MRMDestReg,
769 (ops R32:$dst, R32:$src1, R32:$src2),
770 "xor{l} {$src2, $dst|$dst, $src2}">;
773 def XOR8rm : I<0x32, MRMSrcMem ,
774 (ops R8 :$dst, R8:$src1, i8mem :$src2),
775 "xor{b} {$src2, $dst|$dst, $src2}">;
776 def XOR16rm : I<0x33, MRMSrcMem ,
777 (ops R16:$dst, R8:$src1, i16mem:$src2),
778 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
779 def XOR32rm : I<0x33, MRMSrcMem ,
780 (ops R32:$dst, R8:$src1, i32mem:$src2),
781 "xor{l} {$src2, $dst|$dst, $src2}">;
783 def XOR8ri : Ii8<0x80, MRM6r,
784 (ops R8:$dst, R8:$src1, i8imm:$src2),
785 "xor{b} {$src2, $dst|$dst, $src2}">;
786 def XOR16ri : Ii16<0x81, MRM6r,
787 (ops R16:$dst, R16:$src1, i16imm:$src2),
788 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
789 def XOR32ri : Ii32<0x81, MRM6r,
790 (ops R32:$dst, R32:$src1, i32imm:$src2),
791 "xor{l} {$src2, $dst|$dst, $src2}">;
792 def XOR16ri8 : Ii8<0x83, MRM6r,
793 (ops R16:$dst, R16:$src1, i8imm:$src2),
794 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
795 def XOR32ri8 : Ii8<0x83, MRM6r,
796 (ops R32:$dst, R32:$src1, i8imm:$src2),
797 "xor{l} {$src2, $dst|$dst, $src2}">;
798 let isTwoAddress = 0 in {
799 def XOR8mr : I<0x30, MRMDestMem,
800 (ops i8mem :$dst, R8 :$src),
801 "xor{b} {$src, $dst|$dst, $src}">;
802 def XOR16mr : I<0x31, MRMDestMem,
803 (ops i16mem:$dst, R16:$src),
804 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
805 def XOR32mr : I<0x31, MRMDestMem,
806 (ops i32mem:$dst, R32:$src),
807 "xor{l} {$src, $dst|$dst, $src}">;
808 def XOR8mi : Ii8<0x80, MRM6m,
809 (ops i8mem :$dst, i8imm :$src),
810 "xor{b} {$src, $dst|$dst, $src}">;
811 def XOR16mi : Ii16<0x81, MRM6m,
812 (ops i16mem:$dst, i16imm:$src),
813 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
814 def XOR32mi : Ii32<0x81, MRM6m,
815 (ops i32mem:$dst, i32imm:$src),
816 "xor{l} {$src, $dst|$dst, $src}">;
817 def XOR16mi8 : Ii8<0x83, MRM6m,
818 (ops i16mem:$dst, i8imm :$src),
819 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
820 def XOR32mi8 : Ii8<0x83, MRM6m,
821 (ops i32mem:$dst, i8imm :$src),
822 "xor{l} {$src, $dst|$dst, $src}">;
825 // Shift instructions
826 // FIXME: provide shorter instructions when imm8 == 1
827 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
828 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
829 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
830 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
831 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
832 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
834 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
835 "shl{b} {$src2, $dst|$dst, $src2}">;
836 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
837 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
838 "shl{w} {$src2, $dst|$dst, $src2}">, OpSize;
839 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
840 "shl{l} {$src2, $dst|$dst, $src2}">;
843 let isTwoAddress = 0 in {
844 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
845 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
846 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
847 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
848 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
849 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
850 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
851 "shl{b} {$src, $dst|$dst, $src}">;
852 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
853 "shl{w} {$src, $dst|$dst, $src}">, OpSize;
854 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
855 "shl{l} {$src, $dst|$dst, $src}">;
858 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
859 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
860 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
861 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
862 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
863 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
865 def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
866 "shr{b} {$src2, $dst|$dst, $src2}">;
867 def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
868 "shr{w} {$src2, $dst|$dst, $src2}">, OpSize;
869 def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
870 "shr{l} {$src2, $dst|$dst, $src2}">;
872 let isTwoAddress = 0 in {
873 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
874 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
875 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
876 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
877 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
878 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
879 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
880 "shr{b} {$src, $dst|$dst, $src}">;
881 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
882 "shr{w} {$src, $dst|$dst, $src}">, OpSize;
883 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
884 "shr{l} {$src, $dst|$dst, $src}">;
887 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
888 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
889 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
890 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
891 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
892 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
894 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
895 "sar{b} {$src2, $dst|$dst, $src2}">;
896 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
897 "sar{w} {$src2, $dst|$dst, $src2}">, OpSize;
898 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
899 "sar{l} {$src2, $dst|$dst, $src2}">;
900 let isTwoAddress = 0 in {
901 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
902 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
903 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
904 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
905 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
906 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
907 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
908 "sar{b} {$src, $dst|$dst, $src}">;
909 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
910 "sar{w} {$src, $dst|$dst, $src}">, OpSize;
911 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
912 "sar{l} {$src, $dst|$dst, $src}">;
915 // Rotate instructions
916 // FIXME: provide shorter instructions when imm8 == 1
917 def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
918 "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
919 def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
920 "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
921 def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
922 "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
924 def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
925 "rol{b} {$src2, $dst|$dst, $src2}">;
926 def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
927 "rol{w} {$src2, $dst|$dst, $src2}">, OpSize;
928 def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
929 "rol{l} {$src2, $dst|$dst, $src2}">;
931 let isTwoAddress = 0 in {
932 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
933 "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
934 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
935 "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
936 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
937 "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
938 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
939 "rol{b} {$src, $dst|$dst, $src}">;
940 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
941 "rol{w} {$src, $dst|$dst, $src}">, OpSize;
942 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
943 "rol{l} {$src, $dst|$dst, $src}">;
946 def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
947 "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
948 def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
949 "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
950 def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
951 "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
953 def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
954 "ror{b} {$src2, $dst|$dst, $src2}">;
955 def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
956 "ror{w} {$src2, $dst|$dst, $src2}">, OpSize;
957 def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
958 "ror{l} {$src2, $dst|$dst, $src2}">;
959 let isTwoAddress = 0 in {
960 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
961 "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
962 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
963 "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
964 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
965 "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
966 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
967 "ror{b} {$src, $dst|$dst, $src}">;
968 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
969 "ror{w} {$src, $dst|$dst, $src}">, OpSize;
970 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
971 "ror{l} {$src, $dst|$dst, $src}">;
976 // Double shift instructions (generalizations of rotate)
978 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
979 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
981 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
982 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
984 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
985 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
986 Imp<[CL],[]>, TB, OpSize;
987 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
988 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
989 Imp<[CL],[]>, TB, OpSize;
991 let isCommutable = 1 in { // These instructions commute to each other.
992 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
993 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
994 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
995 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
996 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
997 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
998 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
999 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1000 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1002 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1003 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1004 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1008 let isTwoAddress = 0 in {
1009 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1010 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1012 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1013 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1015 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1016 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1017 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
1018 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1019 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1020 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
1022 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1023 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1024 Imp<[CL],[]>, TB, OpSize;
1025 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1026 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1027 Imp<[CL],[]>, TB, OpSize;
1028 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1029 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1030 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1032 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1033 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1034 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1040 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1041 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1042 "add{b} {$src2, $dst|$dst, $src2}">;
1043 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1044 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1045 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1046 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1047 "add{l} {$src2, $dst|$dst, $src2}">;
1048 } // end isConvertibleToThreeAddress
1049 } // end isCommutable
1050 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1051 "add{b} {$src2, $dst|$dst, $src2}">;
1052 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1053 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1054 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1055 "add{l} {$src2, $dst|$dst, $src2}">;
1057 def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1058 "add{b} {$src2, $dst|$dst, $src2}">;
1060 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1061 def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1062 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1063 def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1064 "add{l} {$src2, $dst|$dst, $src2}">;
1067 def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1068 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1069 def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1070 "add{l} {$src2, $dst|$dst, $src2}">;
1072 let isTwoAddress = 0 in {
1073 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1074 "add{b} {$src2, $dst|$dst, $src2}">;
1075 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1076 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1077 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1078 "add{l} {$src2, $dst|$dst, $src2}">;
1079 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1080 "add{b} {$src2, $dst|$dst, $src2}">;
1081 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1082 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1083 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1084 "add{l} {$src2, $dst|$dst, $src2}">;
1085 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
1086 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1087 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2),
1088 "add{l} {$src2, $dst|$dst, $src2}">;
1091 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1092 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1093 "adc{l} {$src2, $dst|$dst, $src2}">;
1095 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
1096 "adc{l} {$src2, $dst|$dst, $src2}">;
1097 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1098 "adc{l} {$src2, $dst|$dst, $src2}">;
1099 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1100 "adc{l} {$src2, $dst|$dst, $src2}">;
1102 let isTwoAddress = 0 in {
1103 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1104 "adc{l} {$src2, $dst|$dst, $src2}">;
1105 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1106 "adc{l} {$src2, $dst|$dst, $src2}">;
1107 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
1108 "adc{l} {$src2, $dst|$dst, $src2}">;
1111 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1112 "sub{b} {$src2, $dst|$dst, $src2}">;
1113 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1114 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1115 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1116 "sub{l} {$src2, $dst|$dst, $src2}">;
1117 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1118 "sub{b} {$src2, $dst|$dst, $src2}">;
1119 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1120 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1121 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1122 "sub{l} {$src2, $dst|$dst, $src2}">;
1124 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1125 "sub{b} {$src2, $dst|$dst, $src2}">;
1126 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1127 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1128 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1129 "sub{l} {$src2, $dst|$dst, $src2}">;
1130 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1131 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1132 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1133 "sub{l} {$src2, $dst|$dst, $src2}">;
1134 let isTwoAddress = 0 in {
1135 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1136 "sub{b} {$src2, $dst|$dst, $src2}">;
1137 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1138 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1139 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1140 "sub{l} {$src2, $dst|$dst, $src2}">;
1141 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1142 "sub{b} {$src2, $dst|$dst, $src2}">;
1143 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1144 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1145 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1146 "sub{l} {$src2, $dst|$dst, $src2}">;
1147 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2),
1148 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1149 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2),
1150 "sub{l} {$src2, $dst|$dst, $src2}">;
1153 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1154 "sbb{l} {$src2, $dst|$dst, $src2}">;
1156 let isTwoAddress = 0 in {
1157 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1158 "sbb{l} {$src2, $dst|$dst, $src2}">;
1159 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1160 "sbb{b} {$src2, $dst|$dst, $src2}">;
1161 def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
1162 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1163 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
1164 "sbb{l} {$src2, $dst|$dst, $src2}">;
1165 def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
1166 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1167 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
1168 "sbb{l} {$src2, $dst|$dst, $src2}">;
1170 def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1171 "sbb{b} {$src2, $dst|$dst, $src2}">;
1172 def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1173 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1175 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1176 "sbb{l} {$src2, $dst|$dst, $src2}">;
1177 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1178 "sbb{l} {$src2, $dst|$dst, $src2}">;
1180 def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1181 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1182 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1183 "sbb{l} {$src2, $dst|$dst, $src2}">;
1185 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
1186 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
1187 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1188 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
1189 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1191 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1192 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1193 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1194 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1196 } // end Two Address instructions
1198 // Suprisingly enough, these are not two address instructions!
1199 def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
1200 (ops R16:$dst, R16:$src1, i16imm:$src2),
1201 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">,
1203 def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
1204 (ops R32:$dst, R32:$src1, i32imm:$src2),
1205 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1206 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
1207 (ops R16:$dst, R16:$src1, i8imm:$src2),
1208 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1209 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
1210 (ops R32:$dst, R32:$src1, i8imm:$src2),
1211 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1213 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
1214 (ops R32:$dst, i16mem:$src1, i16imm:$src2),
1215 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1216 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
1217 (ops R32:$dst, i32mem:$src1, i32imm:$src2),
1218 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1219 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
1220 (ops R32:$dst, i16mem:$src1, i8imm :$src2),
1221 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1222 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
1223 (ops R32:$dst, i32mem:$src1, i8imm: $src2),
1224 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1226 //===----------------------------------------------------------------------===//
1227 // Test instructions are just like AND, except they don't generate a result.
1229 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1230 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
1231 "test{b} {$src2, $src1|$src1, $src2}">;
1232 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
1233 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1234 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
1235 "test{l} {$src2, $src1|$src1, $src2}">;
1237 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
1238 "test{b} {$src2, $src1|$src1, $src2}">;
1239 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
1240 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1241 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
1242 "test{l} {$src2, $src1|$src1, $src2}">;
1243 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
1244 "test{b} {$src2, $src1|$src1, $src2}">;
1245 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
1246 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1247 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
1248 "test{l} {$src2, $src1|$src1, $src2}">;
1250 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
1251 (ops R8:$src1, i8imm:$src2),
1252 "test{b} {$src2, $src1|$src1, $src2}">;
1253 def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
1254 (ops R16:$src1, i16imm:$src2),
1255 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1256 def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
1257 (ops R32:$src1, i32imm:$src2),
1258 "test{l} {$src2, $src1|$src1, $src2}">;
1259 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1260 (ops i32mem:$src1, i8imm:$src2),
1261 "test{b} {$src2, $src1|$src1, $src2}">;
1262 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1263 (ops i16mem:$src1, i16imm:$src2),
1264 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1265 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1266 (ops i32mem:$src1, i32imm:$src2),
1267 "test{l} {$src2, $src1|$src1, $src2}">;
1271 // Condition code ops, incl. set if equal/not equal/...
1272 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
1273 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
1275 def SETBr : I<0x92, MRM0r,
1276 (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign
1277 def SETBm : I<0x92, MRM0m,
1278 (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign
1279 def SETAEr : I<0x93, MRM0r,
1280 (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign
1281 def SETAEm : I<0x93, MRM0m,
1282 (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign
1283 def SETEr : I<0x94, MRM0r,
1284 (ops R8 :$dst), "sete $dst">, TB; // R8 = ==
1285 def SETEm : I<0x94, MRM0m,
1286 (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = ==
1287 def SETNEr : I<0x95, MRM0r,
1288 (ops R8 :$dst), "setne $dst">, TB; // R8 = !=
1289 def SETNEm : I<0x95, MRM0m,
1290 (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = !=
1291 def SETBEr : I<0x96, MRM0r,
1292 (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign
1293 def SETBEm : I<0x96, MRM0m,
1294 (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign
1295 def SETAr : I<0x97, MRM0r,
1296 (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed
1297 def SETAm : I<0x97, MRM0m,
1298 (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed
1299 def SETSr : I<0x98, MRM0r,
1300 (ops R8 :$dst), "sets $dst">, TB; // R8 = <sign bit>
1301 def SETSm : I<0x98, MRM0m,
1302 (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = <sign bit>
1303 def SETNSr : I<0x99, MRM0r,
1304 (ops R8 :$dst), "setns $dst">, TB; // R8 = !<sign bit>
1305 def SETNSm : I<0x99, MRM0m,
1306 (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = !<sign bit>
1307 def SETPr : I<0x9A, MRM0r,
1308 (ops R8 :$dst), "setp $dst">, TB; // R8 = parity
1309 def SETPm : I<0x9A, MRM0m,
1310 (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity
1311 def SETNPr : I<0x9B, MRM0r,
1312 (ops R8 :$dst), "setnp $dst">, TB; // R8 = not parity
1313 def SETNPm : I<0x9B, MRM0m,
1314 (ops i8mem:$dst), "setnp $dst">, TB; // [mem8] = not parity
1315 def SETLr : I<0x9C, MRM0r,
1316 (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed
1317 def SETLm : I<0x9C, MRM0m,
1318 (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed
1319 def SETGEr : I<0x9D, MRM0r,
1320 (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed
1321 def SETGEm : I<0x9D, MRM0m,
1322 (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed
1323 def SETLEr : I<0x9E, MRM0r,
1324 (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed
1325 def SETLEm : I<0x9E, MRM0m,
1326 (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed
1327 def SETGr : I<0x9F, MRM0r,
1328 (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed
1329 def SETGm : I<0x9F, MRM0m,
1330 (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed
1332 // Integer comparisons
1333 def CMP8rr : I<0x38, MRMDestReg,
1334 (ops R8 :$src1, R8 :$src2),
1335 "cmp{b} {$src2, $src1|$src1, $src2}">;
1336 def CMP16rr : I<0x39, MRMDestReg,
1337 (ops R16:$src1, R16:$src2),
1338 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1339 def CMP32rr : I<0x39, MRMDestReg,
1340 (ops R32:$src1, R32:$src2),
1341 "cmp{l} {$src2, $src1|$src1, $src2}">;
1342 def CMP8mr : I<0x38, MRMDestMem,
1343 (ops i8mem :$src1, R8 :$src2),
1344 "cmp{b} {$src2, $src1|$src1, $src2}">;
1345 def CMP16mr : I<0x39, MRMDestMem,
1346 (ops i16mem:$src1, R16:$src2),
1347 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1348 def CMP32mr : I<0x39, MRMDestMem,
1349 (ops i32mem:$src1, R32:$src2),
1350 "cmp{l} {$src2, $src1|$src1, $src2}">;
1351 def CMP8rm : I<0x3A, MRMSrcMem,
1352 (ops R8 :$src1, i8mem :$src2),
1353 "cmp{b} {$src2, $src1|$src1, $src2}">;
1354 def CMP16rm : I<0x3B, MRMSrcMem,
1355 (ops R16:$src1, i16mem:$src2),
1356 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1357 def CMP32rm : I<0x3B, MRMSrcMem,
1358 (ops R32:$src1, i32mem:$src2),
1359 "cmp{l} {$src2, $src1|$src1, $src2}">;
1360 def CMP8ri : Ii8<0x80, MRM7r,
1361 (ops R16:$src1, i8imm:$src2),
1362 "cmp{b} {$src2, $src1|$src1, $src2}">;
1363 def CMP16ri : Ii16<0x81, MRM7r,
1364 (ops R16:$src1, i16imm:$src2),
1365 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1366 def CMP32ri : Ii32<0x81, MRM7r,
1367 (ops R32:$src1, i32imm:$src2),
1368 "cmp{l} {$src2, $src1|$src1, $src2}">;
1369 def CMP8mi : Ii8 <0x80, MRM7m,
1370 (ops i8mem :$src1, i8imm :$src2),
1371 "cmp{b} {$src2, $src1|$src1, $src2}">;
1372 def CMP16mi : Ii16<0x81, MRM7m,
1373 (ops i16mem:$src1, i16imm:$src2),
1374 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1375 def CMP32mi : Ii32<0x81, MRM7m,
1376 (ops i32mem:$src1, i32imm:$src2),
1377 "cmp{l} {$src2, $src1|$src1, $src2}">;
1379 // Sign/Zero extenders
1380 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
1381 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1382 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1383 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1384 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
1385 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1386 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1387 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1388 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
1389 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1390 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1391 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1393 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
1394 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1395 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1396 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1397 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
1398 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1399 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1400 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1401 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
1402 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1403 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1404 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1406 //===----------------------------------------------------------------------===//
1407 // XMM Floating point support (requires SSE2)
1408 //===----------------------------------------------------------------------===//
1410 def MOVSSrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1411 "movss {$src, $dst|$dst, $src}">, XS;
1412 def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
1413 "movss {$src, $dst|$dst, $src}">, XS;
1414 def MOVSDrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1415 "movsd {$src, $dst|$dst, $src}">, XD;
1416 def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
1417 "movsd {$src, $dst|$dst, $src}">, XD;
1418 def MOVAPSrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1419 "movaps {$src, $dst|$dst, $src}">, TB;
1420 def MOVAPSrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1421 "movaps {$src, $dst|$dst, $src}">, TB;
1422 def MOVAPSmr: I<0x29, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
1423 "movaps {$src, $dst|$dst, $src}">, TB;
1424 def MOVAPDrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1425 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1426 def MOVAPDrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1427 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1428 def MOVAPDmr: I<0x29, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
1429 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1431 def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1432 "cvttsd2si {$src, $dst|$dst, $src}">, XD;
1433 def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
1434 "cvttsd2si {$src, $dst|$dst, $src}">, XD;
1435 def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1436 "cvttss2si {$src, $dst|$dst, $src}">, XS;
1437 def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1438 "cvttss2si {$src, $dst|$dst, $src}">, XS;
1439 def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1440 "cvtsd2ss {$src, $dst|$dst, $src}">, XS;
1441 def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1442 "cvtsd2ss {$src, $dst|$dst, $src}">, XS;
1443 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1444 "cvtss2sd {$src, $dst|$dst, $src}">, XD;
1445 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1446 "cvtss2sd {$src, $dst|$dst, $src}">, XD;
1447 def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1448 "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
1449 def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1450 "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
1451 def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1452 "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
1453 def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f64mem:$src),
1454 "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
1456 def SQRTSSrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1457 "subss {$src, $dst|$dst, $src}">, XS;
1458 def SQRTSSrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1459 "subss {$src, $dst|$dst, $src}">, XS;
1460 def SQRTSDrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1461 "subsd {$src, $dst|$dst, $src}">, XD;
1462 def SQRTSDrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1463 "subsd {$src, $dst|$dst, $src}">, XD;
1465 def UCOMISDrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1466 "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
1467 def UCOMISDrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1468 "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
1469 def UCOMISSrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1470 "ucomiss {$src, $dst|$dst, $src}">, TB;
1471 def UCOMISSrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1472 "ucomiss {$src, $dst|$dst, $src}">, TB;
1474 // Pseudo-instructions that map to fld0 to xorps/xorpd for sse.
1475 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1476 def FLD0SS : I<0x57, MRMSrcReg, (ops RXMM:$dst),
1477 "xorps $dst, $dst">, TB;
1478 def FLD0SD : I<0x57, MRMSrcReg, (ops RXMM:$dst),
1479 "xorpd $dst, $dst">, TB, OpSize;
1481 let isTwoAddress = 1 in {
1482 let isCommutable = 1 in {
1483 def ADDSSrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1484 "addss {$src, $dst|$dst, $src}">, XS;
1485 def ADDSDrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1486 "addsd {$src, $dst|$dst, $src}">, XD;
1487 def ANDPSrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1488 "andps {$src, $dst|$dst, $src}">, TB;
1489 def ANDPDrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1490 "andpd {$src, $dst|$dst, $src}">, TB, OpSize;
1491 def MULSSrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1492 "mulss {$src, $dst|$dst, $src}">, XS;
1493 def MULSDrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1494 "mulsd {$src, $dst|$dst, $src}">, XD;
1495 def ORPSrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1496 "orps {$src, $dst|$dst, $src}">, TB;
1497 def ORPDrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1498 "orpd {$src, $dst|$dst, $src}">, TB, OpSize;
1499 def XORPSrr : I<0x57, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1500 "xorps {$src, $dst|$dst, $src}">, TB;
1501 def XORPDrr : I<0x57, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1502 "xorpd {$src, $dst|$dst, $src}">, TB, OpSize;
1504 def ANDNPSrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1505 "andnps {$src, $dst|$dst, $src}">, TB;
1506 def ANDNPDrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1507 "andnpd {$src, $dst|$dst, $src}">, TB, OpSize;
1508 def ADDSSrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1509 "addss {$src, $dst|$dst, $src}">, XS;
1510 def ADDSDrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1511 "addsd {$src, $dst|$dst, $src}">, XD;
1512 def MULSSrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1513 "mulss {$src, $dst|$dst, $src}">, XS;
1514 def MULSDrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1515 "mulsd {$src, $dst|$dst, $src}">, XD;
1517 def DIVSSrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1518 "divss {$src, $dst|$dst, $src}">, XS;
1519 def DIVSSrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1520 "divss {$src, $dst|$dst, $src}">, XS;
1521 def DIVSDrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1522 "divsd {$src, $dst|$dst, $src}">, XD;
1523 def DIVSDrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1524 "divsd {$src, $dst|$dst, $src}">, XD;
1526 def SUBSSrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1527 "subss {$src, $dst|$dst, $src}">, XS;
1528 def SUBSSrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1529 "subss {$src, $dst|$dst, $src}">, XS;
1530 def SUBSDrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1531 "subsd {$src, $dst|$dst, $src}">, XD;
1532 def SUBSDrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1533 "subsd {$src, $dst|$dst, $src}">, XD;
1535 def CMPSSrr : I<0xC2, MRMSrcReg,
1536 (ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc),
1537 "cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
1538 def CMPSSrm : I<0xC2, MRMSrcMem,
1539 (ops RXMM:$dst, RXMM:$src1, f32mem:$src, SSECC:$cc),
1540 "cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
1541 def CMPSDrr : I<0xC2, MRMSrcReg,
1542 (ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc),
1543 "cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
1544 def CMPSDrm : I<0xC2, MRMSrcMem,
1545 (ops RXMM:$dst, RXMM:$src1, f64mem:$src, SSECC:$cc),
1546 "cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
1549 //===----------------------------------------------------------------------===//
1550 // Stack-based Floating point support
1551 //===----------------------------------------------------------------------===//
1553 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
1555 // Floating point instruction template
1556 class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
1557 : X86Inst<o, F, NoImm, ops, asm> {
1558 let FPForm = fp; let FPFormBits = FPForm.Value;
1561 // Pseudo instructions for floating point. We use these pseudo instructions
1562 // because they can be expanded by the fp spackifier into one of many different
1563 // forms of instructions for doing these operations. Until the stackifier runs,
1564 // we prefer to be abstract.
1565 def FpMOV : FPI<0, Pseudo, SpecialFP,
1566 (ops RFP, RFP), "">; // f1 = fmov f2
1567 def FpADD : FPI<0, Pseudo, TwoArgFP ,
1568 (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3
1569 def FpSUB : FPI<0, Pseudo, TwoArgFP ,
1570 (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3
1571 def FpMUL : FPI<0, Pseudo, TwoArgFP ,
1572 (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3
1573 def FpDIV : FPI<0, Pseudo, TwoArgFP ,
1574 (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3
1576 def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1577 Imp<[ST0], []>; // FPR = ST(0)
1579 def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1580 Imp<[], [ST0]>; // ST(0) = FPR
1582 // FADD reg, mem: Before stackification, these are represented by:
1583 // R1 = FADD* R2, [mem]
1584 def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
1585 (ops f32mem:$src, variable_ops),
1587 def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
1588 (ops f64mem:$src, variable_ops),
1590 //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
1591 //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
1593 // FMUL reg, mem: Before stackification, these are represented by:
1594 // R1 = FMUL* R2, [mem]
1595 def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
1596 (ops f32mem:$src, variable_ops),
1598 def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
1599 (ops f64mem:$src, variable_ops),
1601 // ST(0) = ST(0) * [mem16int]
1602 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
1603 // ST(0) = ST(0) * [mem32int]
1604 //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
1606 // FSUB reg, mem: Before stackification, these are represented by:
1607 // R1 = FSUB* R2, [mem]
1608 def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
1609 (ops f32mem:$src, variable_ops),
1611 def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
1612 (ops f64mem:$src, variable_ops),
1614 // ST(0) = ST(0) - [mem16int]
1615 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
1616 // ST(0) = ST(0) - [mem32int]
1617 //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
1619 // FSUBR reg, mem: Before stackification, these are represented by:
1620 // R1 = FSUBR* R2, [mem]
1622 // Note that the order of operands does not reflect the operation being
1624 def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
1625 (ops f32mem:$src, variable_ops),
1627 def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
1628 (ops f64mem:$src, variable_ops),
1630 // ST(0) = [mem16int] - ST(0)
1631 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
1632 // ST(0) = [mem32int] - ST(0)
1633 //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
1635 // FDIV reg, mem: Before stackification, these are represented by:
1636 // R1 = FDIV* R2, [mem]
1637 def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
1638 (ops f32mem:$src, variable_ops),
1640 def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
1641 (ops f64mem:$src, variable_ops),
1643 // ST(0) = ST(0) / [mem16int]
1644 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
1645 // ST(0) = ST(0) / [mem32int]
1646 //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
1648 // FDIVR reg, mem: Before stackification, these are represented by:
1649 // R1 = FDIVR* R2, [mem]
1650 // Note that the order of operands does not reflect the operation being
1652 def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
1653 (ops f32mem:$src, variable_ops),
1655 def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
1656 (ops f64mem:$src, variable_ops),
1658 // ST(0) = [mem16int] / ST(0)
1659 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
1660 // ST(0) = [mem32int] / ST(0)
1661 //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
1664 // Floating point cmovs...
1665 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
1666 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
1667 (ops RST:$op, variable_ops),
1668 "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
1669 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
1670 (ops RST:$op, variable_ops),
1671 "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
1672 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
1673 (ops RST:$op, variable_ops),
1674 "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
1675 def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP,
1676 (ops RST:$op, variable_ops),
1677 "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
1678 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
1679 (ops RST:$op, variable_ops),
1680 "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
1681 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
1682 (ops RST:$op, variable_ops),
1683 "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
1684 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
1685 (ops RST:$op, variable_ops),
1686 "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
1687 def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
1688 (ops RST:$op, variable_ops),
1689 "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
1692 // Floating point loads & stores...
1693 // FIXME: these are all marked variable_ops because they have an implicit
1694 // destination. Instructions like FILD* that are generated by the instruction
1695 // selector (not the fp stackifier) need more accurate operand accounting.
1696 def FLDrr : FPI<0xC0, AddRegFrm, NotFP,
1697 (ops RST:$src, variable_ops),
1699 def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP,
1700 (ops f32mem:$src, variable_ops),
1702 def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP,
1703 (ops f64mem:$src, variable_ops),
1705 def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP,
1706 (ops f80mem:$src, variable_ops),
1708 def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
1709 (ops i16mem:$src, variable_ops),
1711 def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
1712 (ops i32mem:$src, variable_ops),
1714 def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
1715 (ops i64mem:$src, variable_ops),
1718 def FSTrr : FPI<0xD0, AddRegFrm, NotFP,
1719 (ops RST:$op, variable_ops),
1721 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP,
1722 (ops RST:$op, variable_ops),
1724 def FST32m : FPI<0xD9, MRM2m, OneArgFP,
1725 (ops f32mem:$op, variable_ops),
1727 def FST64m : FPI<0xDD, MRM2m, OneArgFP,
1728 (ops f64mem:$op, variable_ops),
1730 def FSTP32m : FPI<0xD9, MRM3m, OneArgFP,
1731 (ops f32mem:$op, variable_ops),
1733 def FSTP64m : FPI<0xDD, MRM3m, OneArgFP,
1734 (ops f64mem:$op, variable_ops),
1736 def FSTP80m : FPI<0xDB, MRM7m, OneArgFP,
1737 (ops f80mem:$op, variable_ops),
1740 def FIST16m : FPI<0xDF, MRM2m , OneArgFP,
1741 (ops i16mem:$op, variable_ops),
1743 def FIST32m : FPI<0xDB, MRM2m , OneArgFP,
1744 (ops i32mem:$op, variable_ops),
1746 def FISTP16m : FPI<0xDF, MRM3m , NotFP ,
1747 (ops i16mem:$op, variable_ops),
1749 def FISTP32m : FPI<0xDB, MRM3m , NotFP ,
1750 (ops i32mem:$op, variable_ops),
1752 def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
1753 (ops i64mem:$op, variable_ops),
1756 def FXCH : FPI<0xC8, AddRegFrm, NotFP,
1757 (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
1759 // Floating point constant loads...
1760 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
1761 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;
1764 // Unary operations...
1765 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, // f1 = fchs f2
1768 def FABS : FPI<0xE1, RawFrm, OneArgFPRW, // f1 = fabs f2
1771 def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, // fsqrt ST(0)
1774 def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, // fsin ST(0)
1777 def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, // fcos ST(0)
1780 def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0)
1784 // Binary arithmetic operations...
1785 class FPST0rInst<bits<8> o, dag ops, string asm>
1786 : I<o, AddRegFrm, ops, asm>, D8 {
1787 list<Register> Uses = [ST0];
1788 list<Register> Defs = [ST0];
1790 class FPrST0Inst<bits<8> o, dag ops, string asm>
1791 : I<o, AddRegFrm, ops, asm>, DC {
1792 list<Register> Uses = [ST0];
1794 class FPrST0PInst<bits<8> o, dag ops, string asm>
1795 : I<o, AddRegFrm, ops, asm>, DE {
1796 list<Register> Uses = [ST0];
1799 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
1801 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
1802 "fadd {%ST(0), $op|$op, %ST(0)}">;
1803 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
1806 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
1807 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
1808 // we have to put some 'r's in and take them out of weird places.
1809 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
1811 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
1812 "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
1813 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
1816 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
1818 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
1819 "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
1820 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
1823 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
1825 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
1826 "fmul {%ST(0), $op|$op, %ST(0)}">;
1827 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
1830 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
1832 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
1833 "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
1834 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
1837 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
1839 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
1840 "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
1841 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
1844 // Floating point compares
1845 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
1846 (ops RST:$reg, variable_ops),
1847 "fucom $reg">, DD, Imp<[ST0],[]>;
1848 def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
1849 (ops RST:$reg, variable_ops),
1850 "fucomp $reg">, DD, Imp<[ST0],[]>;
1851 def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
1853 "fucompp">, DA, Imp<[ST0],[]>;
1855 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
1856 (ops RST:$reg, variable_ops),
1857 "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
1858 def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
1859 (ops RST:$reg, variable_ops),
1860 "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
1863 // Floating point flag ops
1864 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
1865 (ops), "fnstsw">, DF, Imp<[],[AX]>;
1867 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
1868 (ops i16mem:$dst), "fnstcw $dst">;
1869 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
1870 (ops i16mem:$dst), "fldcw $dst">;