3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
164 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
165 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
166 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
167 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
168 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
169 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags>;
170 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags>;
171 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags>;
173 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
175 //===----------------------------------------------------------------------===//
176 // X86 Operand Definitions.
179 def i32imm_pcrel : Operand<i32> {
180 let PrintMethod = "print_pcrel_imm";
183 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
184 // the index operand of an address, to conform to x86 encoding restrictions.
185 def ptr_rc_nosp : PointerLikeRegClass<1>;
187 // *mem - Operand definitions for the funky X86 addressing mode operands.
189 def X86MemAsmOperand : AsmOperandClass {
193 class X86MemOperand<string printMethod> : Operand<iPTR> {
194 let PrintMethod = printMethod;
195 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
196 let ParserMatchClass = X86MemAsmOperand;
199 def opaque32mem : X86MemOperand<"printopaquemem">;
200 def opaque48mem : X86MemOperand<"printopaquemem">;
201 def opaque80mem : X86MemOperand<"printopaquemem">;
202 def opaque512mem : X86MemOperand<"printopaquemem">;
204 def offset8 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
205 def offset16 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
206 def offset32 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
207 def offset64 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
209 def i8mem : X86MemOperand<"printi8mem">;
210 def i16mem : X86MemOperand<"printi16mem">;
211 def i32mem : X86MemOperand<"printi32mem">;
212 def i64mem : X86MemOperand<"printi64mem">;
213 def i128mem : X86MemOperand<"printi128mem">;
214 //def i256mem : X86MemOperand<"printi256mem">;
215 def f32mem : X86MemOperand<"printf32mem">;
216 def f64mem : X86MemOperand<"printf64mem">;
217 def f80mem : X86MemOperand<"printf80mem">;
218 def f128mem : X86MemOperand<"printf128mem">;
219 //def f256mem : X86MemOperand<"printf256mem">;
221 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
222 // plain GR64, so that it doesn't potentially require a REX prefix.
223 def i8mem_NOREX : Operand<i64> {
224 let PrintMethod = "printi8mem";
225 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
226 let ParserMatchClass = X86MemAsmOperand;
229 def lea32mem : Operand<i32> {
230 let PrintMethod = "printlea32mem";
231 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
232 let ParserMatchClass = X86MemAsmOperand;
235 def SSECC : Operand<i8> {
236 let PrintMethod = "printSSECC";
239 def ImmSExt8AsmOperand : AsmOperandClass {
240 let Name = "ImmSExt8";
241 let SuperClass = ImmAsmOperand;
244 // A couple of more descriptive operand definitions.
245 // 16-bits but only 8 bits are significant.
246 def i16i8imm : Operand<i16> {
247 let ParserMatchClass = ImmSExt8AsmOperand;
249 // 32-bits but only 8 bits are significant.
250 def i32i8imm : Operand<i32> {
251 let ParserMatchClass = ImmSExt8AsmOperand;
254 // Branch targets have OtherVT type and print as pc-relative values.
255 def brtarget : Operand<OtherVT> {
256 let PrintMethod = "print_pcrel_imm";
259 def brtarget8 : Operand<OtherVT> {
260 let PrintMethod = "print_pcrel_imm";
263 //===----------------------------------------------------------------------===//
264 // X86 Complex Pattern Definitions.
267 // Define X86 specific addressing mode.
268 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
269 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
270 [add, sub, mul, X86mul_imm, shl, or, frameindex],
272 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
273 [tglobaltlsaddr], []>;
275 //===----------------------------------------------------------------------===//
276 // X86 Instruction Predicate Definitions.
277 def HasMMX : Predicate<"Subtarget->hasMMX()">;
278 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
279 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
280 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
281 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
282 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
283 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
284 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
285 def HasAVX : Predicate<"Subtarget->hasAVX()">;
286 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
287 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
288 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
289 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
290 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
291 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
292 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
293 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
294 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
295 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
296 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
297 "TM.getCodeModel() != CodeModel::Kernel">;
298 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
299 "TM.getCodeModel() == CodeModel::Kernel">;
300 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
301 def OptForSize : Predicate<"OptForSize">;
302 def OptForSpeed : Predicate<"!OptForSize">;
303 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
304 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
306 //===----------------------------------------------------------------------===//
307 // X86 Instruction Format Definitions.
310 include "X86InstrFormats.td"
312 //===----------------------------------------------------------------------===//
313 // Pattern fragments...
316 // X86 specific condition code. These correspond to CondCode in
317 // X86InstrInfo.h. They must be kept in synch.
318 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
319 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
320 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
321 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
322 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
323 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
324 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
325 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
326 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
327 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
328 def X86_COND_NO : PatLeaf<(i8 10)>;
329 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
330 def X86_COND_NS : PatLeaf<(i8 12)>;
331 def X86_COND_O : PatLeaf<(i8 13)>;
332 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
333 def X86_COND_S : PatLeaf<(i8 15)>;
335 def i16immSExt8 : PatLeaf<(i16 imm), [{
336 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
337 // sign extended field.
338 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
341 def i32immSExt8 : PatLeaf<(i32 imm), [{
342 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
343 // sign extended field.
344 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
347 // Helper fragments for loads.
348 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
349 // known to be 32-bit aligned or better. Ditto for i8 to i16.
350 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
351 LoadSDNode *LD = cast<LoadSDNode>(N);
352 if (const Value *Src = LD->getSrcValue())
353 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
354 if (PT->getAddressSpace() > 255)
356 ISD::LoadExtType ExtType = LD->getExtensionType();
357 if (ExtType == ISD::NON_EXTLOAD)
359 if (ExtType == ISD::EXTLOAD)
360 return LD->getAlignment() >= 2 && !LD->isVolatile();
364 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
366 LoadSDNode *LD = cast<LoadSDNode>(N);
367 if (const Value *Src = LD->getSrcValue())
368 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
369 if (PT->getAddressSpace() > 255)
371 ISD::LoadExtType ExtType = LD->getExtensionType();
372 if (ExtType == ISD::EXTLOAD)
373 return LD->getAlignment() >= 2 && !LD->isVolatile();
377 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
378 LoadSDNode *LD = cast<LoadSDNode>(N);
379 if (const Value *Src = LD->getSrcValue())
380 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
381 if (PT->getAddressSpace() > 255)
383 ISD::LoadExtType ExtType = LD->getExtensionType();
384 if (ExtType == ISD::NON_EXTLOAD)
386 if (ExtType == ISD::EXTLOAD)
387 return LD->getAlignment() >= 4 && !LD->isVolatile();
391 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
392 LoadSDNode *LD = cast<LoadSDNode>(N);
393 if (const Value *Src = LD->getSrcValue())
394 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
395 if (PT->getAddressSpace() > 255)
397 if (LD->isVolatile())
399 ISD::LoadExtType ExtType = LD->getExtensionType();
400 if (ExtType == ISD::NON_EXTLOAD)
402 if (ExtType == ISD::EXTLOAD)
403 return LD->getAlignment() >= 4;
407 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
408 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
409 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
410 return PT->getAddressSpace() == 256;
414 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
415 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
416 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
417 return PT->getAddressSpace() == 257;
421 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
422 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
423 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
424 if (PT->getAddressSpace() > 255)
428 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
429 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
430 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
431 if (PT->getAddressSpace() > 255)
436 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
437 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
438 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
439 if (PT->getAddressSpace() > 255)
443 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
444 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
445 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
446 if (PT->getAddressSpace() > 255)
450 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
451 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
452 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
453 if (PT->getAddressSpace() > 255)
458 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
459 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
460 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
462 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
463 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
464 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
465 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
466 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
467 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
469 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
470 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
471 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
472 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
473 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
474 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
477 // An 'and' node with a single use.
478 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
479 return N->hasOneUse();
481 // An 'srl' node with a single use.
482 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
483 return N->hasOneUse();
485 // An 'trunc' node with a single use.
486 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
487 return N->hasOneUse();
490 // 'shld' and 'shrd' instruction patterns. Note that even though these have
491 // the srl and shl in their patterns, the C++ code must still check for them,
492 // because predicates are tested before children nodes are explored.
494 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
495 (or (srl node:$src1, node:$amt1),
496 (shl node:$src2, node:$amt2)), [{
497 assert(N->getOpcode() == ISD::OR);
498 return N->getOperand(0).getOpcode() == ISD::SRL &&
499 N->getOperand(1).getOpcode() == ISD::SHL &&
500 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
501 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
502 N->getOperand(0).getConstantOperandVal(1) ==
503 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
506 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
507 (or (shl node:$src1, node:$amt1),
508 (srl node:$src2, node:$amt2)), [{
509 assert(N->getOpcode() == ISD::OR);
510 return N->getOperand(0).getOpcode() == ISD::SHL &&
511 N->getOperand(1).getOpcode() == ISD::SRL &&
512 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
513 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
514 N->getOperand(0).getConstantOperandVal(1) ==
515 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
518 //===----------------------------------------------------------------------===//
519 // Instruction list...
522 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
523 // a stack adjustment and the codegen must know that they may modify the stack
524 // pointer before prolog-epilog rewriting occurs.
525 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
526 // sub / add which can clobber EFLAGS.
527 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
528 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
530 [(X86callseq_start timm:$amt)]>,
531 Requires<[In32BitMode]>;
532 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
534 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
535 Requires<[In32BitMode]>;
538 // x86-64 va_start lowering magic.
539 let usesCustomInserter = 1 in
540 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
543 i64imm:$regsavefi, i64imm:$offset,
545 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
546 [(X86vastart_save_xmm_regs GR8:$al,
551 let neverHasSideEffects = 1 in {
552 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
553 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
554 "nop{w}\t$zero", []>, TB, OpSize;
555 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
556 "nop{l}\t$zero", []>, TB;
560 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
561 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
562 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
563 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
565 // PIC base construction. This expands to code that looks like this:
568 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
569 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
572 //===----------------------------------------------------------------------===//
573 // Control Flow Instructions...
576 // Return instructions.
577 let isTerminator = 1, isReturn = 1, isBarrier = 1,
578 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
579 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
582 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
584 [(X86retflag timm:$amt)]>;
585 def LRET : I <0xCB, RawFrm, (outs), (ins),
587 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
591 // All branches are RawFrm, Void, Branch, and Terminators
592 let isBranch = 1, isTerminator = 1 in
593 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
594 I<opcode, RawFrm, (outs), ins, asm, pattern>;
596 let isBranch = 1, isBarrier = 1 in {
597 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
598 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
602 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
603 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
604 [(brind GR32:$dst)]>;
605 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
606 [(brind (loadi32 addr:$dst))]>;
608 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
609 (ins i16imm:$seg, i16imm:$off),
610 "ljmp{w}\t$seg, $off", []>, OpSize;
611 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
612 (ins i16imm:$seg, i32imm:$off),
613 "ljmp{l}\t$seg, $off", []>;
615 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
616 "ljmp{w}\t{*}$dst", []>, OpSize;
617 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
618 "ljmp{l}\t{*}$dst", []>;
621 // Conditional branches
622 let Uses = [EFLAGS] in {
623 // Short conditional jumps
624 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
625 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
626 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
627 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
628 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
629 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
630 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
631 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
632 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
633 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
634 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
635 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
636 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
637 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
638 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
639 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
641 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
643 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
644 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
645 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
646 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
647 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
648 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
649 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
650 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
651 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
652 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
653 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
654 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
656 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
657 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
658 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
659 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
660 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
661 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
662 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
663 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
665 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
666 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
667 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
668 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
669 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
670 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
671 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
672 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
673 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
674 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
675 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
676 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
681 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
682 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
683 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
685 //===----------------------------------------------------------------------===//
686 // Call Instructions...
689 // All calls clobber the non-callee saved registers. ESP is marked as
690 // a use to prevent stack-pointer assignments that appear immediately
691 // before calls from potentially appearing dead. Uses for argument
692 // registers are added manually.
693 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
694 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
695 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
696 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
698 def CALLpcrel32 : Ii32<0xE8, RawFrm,
699 (outs), (ins i32imm_pcrel:$dst,variable_ops),
701 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
702 "call\t{*}$dst", [(X86call GR32:$dst)]>;
703 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
704 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
706 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
707 (ins i16imm:$seg, i16imm:$off),
708 "lcall{w}\t$seg, $off", []>, OpSize;
709 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
710 (ins i16imm:$seg, i32imm:$off),
711 "lcall{l}\t$seg, $off", []>;
713 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
714 "lcall{w}\t{*}$dst", []>, OpSize;
715 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
716 "lcall{l}\t{*}$dst", []>;
719 // Constructing a stack frame.
721 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
722 "enter\t$len, $lvl", []>;
726 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
727 def TCRETURNdi : I<0, Pseudo, (outs),
728 (ins i32imm:$dst, i32imm:$offset, variable_ops),
729 "#TC_RETURN $dst $offset",
732 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
733 def TCRETURNri : I<0, Pseudo, (outs),
734 (ins GR32:$dst, i32imm:$offset, variable_ops),
735 "#TC_RETURN $dst $offset",
738 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
739 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
741 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
742 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst),
743 "jmp{l}\t{*}$dst # TAILCALL",
745 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
746 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
747 "jmp\t{*}$dst # TAILCALL", []>;
749 //===----------------------------------------------------------------------===//
750 // Miscellaneous Instructions...
752 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
753 def LEAVE : I<0xC9, RawFrm,
754 (outs), (ins), "leave", []>;
756 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
757 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
758 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
759 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
760 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
761 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
762 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
763 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
765 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
767 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
769 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
770 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
772 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
774 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
775 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
778 let mayStore = 1 in {
779 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
781 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
782 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
784 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
786 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
787 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
791 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
792 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
793 "push{l}\t$imm", []>;
794 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
795 "push{l}\t$imm", []>;
796 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
797 "push{l}\t$imm", []>;
800 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
801 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
802 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
804 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
805 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
806 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
809 let isTwoAddress = 1 in // GR32 = bswap GR32
810 def BSWAP32r : I<0xC8, AddRegFrm,
811 (outs GR32:$dst), (ins GR32:$src),
813 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
816 // Bit scan instructions.
817 let Defs = [EFLAGS] in {
818 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
819 "bsf{w}\t{$src, $dst|$dst, $src}",
820 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
821 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
822 "bsf{w}\t{$src, $dst|$dst, $src}",
823 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
824 (implicit EFLAGS)]>, TB;
825 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
826 "bsf{l}\t{$src, $dst|$dst, $src}",
827 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
828 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
829 "bsf{l}\t{$src, $dst|$dst, $src}",
830 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
831 (implicit EFLAGS)]>, TB;
833 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
834 "bsr{w}\t{$src, $dst|$dst, $src}",
835 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
836 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
837 "bsr{w}\t{$src, $dst|$dst, $src}",
838 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
839 (implicit EFLAGS)]>, TB;
840 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
841 "bsr{l}\t{$src, $dst|$dst, $src}",
842 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
843 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
844 "bsr{l}\t{$src, $dst|$dst, $src}",
845 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
846 (implicit EFLAGS)]>, TB;
849 let neverHasSideEffects = 1 in
850 def LEA16r : I<0x8D, MRMSrcMem,
851 (outs GR16:$dst), (ins lea32mem:$src),
852 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
853 let isReMaterializable = 1 in
854 def LEA32r : I<0x8D, MRMSrcMem,
855 (outs GR32:$dst), (ins lea32mem:$src),
856 "lea{l}\t{$src|$dst}, {$dst|$src}",
857 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
859 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
860 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
861 [(X86rep_movs i8)]>, REP;
862 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
863 [(X86rep_movs i16)]>, REP, OpSize;
864 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
865 [(X86rep_movs i32)]>, REP;
868 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
869 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
870 [(X86rep_stos i8)]>, REP;
871 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
872 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
873 [(X86rep_stos i16)]>, REP, OpSize;
874 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
875 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
876 [(X86rep_stos i32)]>, REP;
878 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
879 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
880 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
882 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
883 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
884 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
886 let Defs = [RAX, RDX] in
887 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
890 let isBarrier = 1, hasCtrlDep = 1 in {
891 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
894 def SYSCALL : I<0x05, RawFrm,
895 (outs), (ins), "syscall", []>, TB;
896 def SYSRET : I<0x07, RawFrm,
897 (outs), (ins), "sysret", []>, TB;
898 def SYSENTER : I<0x34, RawFrm,
899 (outs), (ins), "sysenter", []>, TB;
900 def SYSEXIT : I<0x35, RawFrm,
901 (outs), (ins), "sysexit", []>, TB;
903 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
906 //===----------------------------------------------------------------------===//
907 // Input/Output Instructions...
909 let Defs = [AL], Uses = [DX] in
910 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
911 "in{b}\t{%dx, %al|%AL, %DX}", []>;
912 let Defs = [AX], Uses = [DX] in
913 def IN16rr : I<0xED, RawFrm, (outs), (ins),
914 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
915 let Defs = [EAX], Uses = [DX] in
916 def IN32rr : I<0xED, RawFrm, (outs), (ins),
917 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
920 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
921 "in{b}\t{$port, %al|%AL, $port}", []>;
923 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
924 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
926 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
927 "in{l}\t{$port, %eax|%EAX, $port}", []>;
929 let Uses = [DX, AL] in
930 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
931 "out{b}\t{%al, %dx|%DX, %AL}", []>;
932 let Uses = [DX, AX] in
933 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
934 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
935 let Uses = [DX, EAX] in
936 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
937 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
940 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
941 "out{b}\t{%al, $port|$port, %AL}", []>;
943 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
944 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
946 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
947 "out{l}\t{%eax, $port|$port, %EAX}", []>;
949 def IN8 : I<0x6C, RawFrm, (outs), (ins),
951 def IN16 : I<0x6D, RawFrm, (outs), (ins),
952 "ins{w}", []>, OpSize;
953 def IN32 : I<0x6D, RawFrm, (outs), (ins),
956 //===----------------------------------------------------------------------===//
957 // Move Instructions...
959 let neverHasSideEffects = 1 in {
960 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
961 "mov{b}\t{$src, $dst|$dst, $src}", []>;
962 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
963 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
964 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
965 "mov{l}\t{$src, $dst|$dst, $src}", []>;
967 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
968 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
969 "mov{b}\t{$src, $dst|$dst, $src}",
970 [(set GR8:$dst, imm:$src)]>;
971 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
972 "mov{w}\t{$src, $dst|$dst, $src}",
973 [(set GR16:$dst, imm:$src)]>, OpSize;
974 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
975 "mov{l}\t{$src, $dst|$dst, $src}",
976 [(set GR32:$dst, imm:$src)]>;
978 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
979 "mov{b}\t{$src, $dst|$dst, $src}",
980 [(store (i8 imm:$src), addr:$dst)]>;
981 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
982 "mov{w}\t{$src, $dst|$dst, $src}",
983 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
984 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
985 "mov{l}\t{$src, $dst|$dst, $src}",
986 [(store (i32 imm:$src), addr:$dst)]>;
988 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
989 "mov{b}\t{$src, %al|%al, $src}", []>;
990 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
991 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
992 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
993 "mov{l}\t{$src, %eax|%eax, $src}", []>;
995 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
996 "mov{b}\t{%al, $dst|$dst, %al}", []>;
997 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
998 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
999 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1000 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1002 // Moves to and from segment registers
1003 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1004 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1005 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1006 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1007 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1008 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1009 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1010 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1012 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1013 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1014 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1015 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1016 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1017 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1019 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1020 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1021 "mov{b}\t{$src, $dst|$dst, $src}",
1022 [(set GR8:$dst, (loadi8 addr:$src))]>;
1023 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}",
1025 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1026 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1027 "mov{l}\t{$src, $dst|$dst, $src}",
1028 [(set GR32:$dst, (loadi32 addr:$src))]>;
1031 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1032 "mov{b}\t{$src, $dst|$dst, $src}",
1033 [(store GR8:$src, addr:$dst)]>;
1034 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1035 "mov{w}\t{$src, $dst|$dst, $src}",
1036 [(store GR16:$src, addr:$dst)]>, OpSize;
1037 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1038 "mov{l}\t{$src, $dst|$dst, $src}",
1039 [(store GR32:$src, addr:$dst)]>;
1041 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1042 // that they can be used for copying and storing h registers, which can't be
1043 // encoded when a REX prefix is present.
1044 let neverHasSideEffects = 1 in
1045 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1046 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1047 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1049 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1050 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1051 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1053 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1054 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1055 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1056 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1058 // Moves to and from debug registers
1059 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1061 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1062 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1064 // Moves to and from control registers
1065 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1066 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1067 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1068 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1070 //===----------------------------------------------------------------------===//
1071 // Fixed-Register Multiplication and Division Instructions...
1074 // Extra precision multiplication
1075 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1076 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1077 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1078 // This probably ought to be moved to a def : Pat<> if the
1079 // syntax can be accepted.
1080 [(set AL, (mul AL, GR8:$src)),
1081 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1083 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1084 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1086 []>, OpSize; // AX,DX = AX*GR16
1088 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1089 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1091 []>; // EAX,EDX = EAX*GR32
1093 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1094 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1096 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1097 // This probably ought to be moved to a def : Pat<> if the
1098 // syntax can be accepted.
1099 [(set AL, (mul AL, (loadi8 addr:$src))),
1100 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1102 let mayLoad = 1, neverHasSideEffects = 1 in {
1103 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1104 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1106 []>, OpSize; // AX,DX = AX*[mem16]
1108 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1109 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1111 []>; // EAX,EDX = EAX*[mem32]
1114 let neverHasSideEffects = 1 in {
1115 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1116 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1118 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1119 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1120 OpSize; // AX,DX = AX*GR16
1121 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1122 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1123 // EAX,EDX = EAX*GR32
1124 let mayLoad = 1 in {
1125 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1126 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1127 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1128 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1129 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1130 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1131 let Defs = [EAX,EDX], Uses = [EAX] in
1132 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1133 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1135 } // neverHasSideEffects
1137 // unsigned division/remainder
1138 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1139 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1140 "div{b}\t$src", []>;
1141 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1142 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1143 "div{w}\t$src", []>, OpSize;
1144 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1145 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1146 "div{l}\t$src", []>;
1147 let mayLoad = 1 in {
1148 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1149 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1150 "div{b}\t$src", []>;
1151 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1152 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1153 "div{w}\t$src", []>, OpSize;
1154 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1155 // EDX:EAX/[mem32] = EAX,EDX
1156 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1157 "div{l}\t$src", []>;
1160 // Signed division/remainder.
1161 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1162 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1163 "idiv{b}\t$src", []>;
1164 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1165 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1166 "idiv{w}\t$src", []>, OpSize;
1167 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1168 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1169 "idiv{l}\t$src", []>;
1170 let mayLoad = 1, mayLoad = 1 in {
1171 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1172 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1173 "idiv{b}\t$src", []>;
1174 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1175 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1176 "idiv{w}\t$src", []>, OpSize;
1177 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1178 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1179 // EDX:EAX/[mem32] = EAX,EDX
1180 "idiv{l}\t$src", []>;
1183 //===----------------------------------------------------------------------===//
1184 // Two address Instructions.
1186 let isTwoAddress = 1 in {
1188 // Conditional moves
1189 let Uses = [EFLAGS] in {
1191 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1192 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1193 // however that requires promoting the operands, and can induce additional
1194 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1195 // clobber EFLAGS, because if one of the operands is zero, the expansion
1196 // could involve an xor.
1197 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1198 def CMOV_GR8 : I<0, Pseudo,
1199 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1200 "#CMOV_GR8 PSEUDO!",
1201 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1202 imm:$cond, EFLAGS))]>;
1204 let isCommutable = 1 in {
1205 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1206 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1207 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1208 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1209 X86_COND_B, EFLAGS))]>,
1211 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1212 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1213 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1215 X86_COND_B, EFLAGS))]>,
1217 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1218 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1219 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1221 X86_COND_AE, EFLAGS))]>,
1223 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1224 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1225 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1226 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1227 X86_COND_AE, EFLAGS))]>,
1229 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1230 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1231 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1233 X86_COND_E, EFLAGS))]>,
1235 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1236 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1237 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1239 X86_COND_E, EFLAGS))]>,
1241 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1242 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1243 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1245 X86_COND_NE, EFLAGS))]>,
1247 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1248 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1249 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1251 X86_COND_NE, EFLAGS))]>,
1253 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1254 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1255 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1256 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1257 X86_COND_BE, EFLAGS))]>,
1259 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1260 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1261 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1263 X86_COND_BE, EFLAGS))]>,
1265 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1266 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1267 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1269 X86_COND_A, EFLAGS))]>,
1271 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1272 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1273 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1275 X86_COND_A, EFLAGS))]>,
1277 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1278 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1279 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1281 X86_COND_L, EFLAGS))]>,
1283 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1284 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1285 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1287 X86_COND_L, EFLAGS))]>,
1289 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1290 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1291 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1293 X86_COND_GE, EFLAGS))]>,
1295 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1296 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1297 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1299 X86_COND_GE, EFLAGS))]>,
1301 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1302 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1303 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1305 X86_COND_LE, EFLAGS))]>,
1307 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1308 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1309 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1311 X86_COND_LE, EFLAGS))]>,
1313 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1314 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1315 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1317 X86_COND_G, EFLAGS))]>,
1319 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1320 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1321 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1323 X86_COND_G, EFLAGS))]>,
1325 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1326 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1327 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1329 X86_COND_S, EFLAGS))]>,
1331 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1332 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1333 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1335 X86_COND_S, EFLAGS))]>,
1337 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1338 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1339 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1341 X86_COND_NS, EFLAGS))]>,
1343 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1344 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1345 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1347 X86_COND_NS, EFLAGS))]>,
1349 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1350 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1351 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1353 X86_COND_P, EFLAGS))]>,
1355 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1356 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1357 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1359 X86_COND_P, EFLAGS))]>,
1361 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1362 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1363 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1365 X86_COND_NP, EFLAGS))]>,
1367 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1368 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1369 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1371 X86_COND_NP, EFLAGS))]>,
1373 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1374 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1375 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1377 X86_COND_O, EFLAGS))]>,
1379 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1380 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1381 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1383 X86_COND_O, EFLAGS))]>,
1385 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1386 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1387 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1389 X86_COND_NO, EFLAGS))]>,
1391 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1392 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1393 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1395 X86_COND_NO, EFLAGS))]>,
1397 } // isCommutable = 1
1399 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1400 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1401 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1403 X86_COND_B, EFLAGS))]>,
1405 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1406 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1407 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1408 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1409 X86_COND_B, EFLAGS))]>,
1411 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1412 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1413 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1414 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1415 X86_COND_AE, EFLAGS))]>,
1417 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1418 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1419 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1421 X86_COND_AE, EFLAGS))]>,
1423 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1424 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1425 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1427 X86_COND_E, EFLAGS))]>,
1429 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1430 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1431 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1433 X86_COND_E, EFLAGS))]>,
1435 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1436 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1437 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1439 X86_COND_NE, EFLAGS))]>,
1441 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1442 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1443 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1445 X86_COND_NE, EFLAGS))]>,
1447 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1448 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1449 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1451 X86_COND_BE, EFLAGS))]>,
1453 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1454 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1455 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1457 X86_COND_BE, EFLAGS))]>,
1459 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1460 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1461 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1463 X86_COND_A, EFLAGS))]>,
1465 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1466 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1467 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1469 X86_COND_A, EFLAGS))]>,
1471 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1472 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1473 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1475 X86_COND_L, EFLAGS))]>,
1477 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1478 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1479 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1481 X86_COND_L, EFLAGS))]>,
1483 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1484 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1485 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1487 X86_COND_GE, EFLAGS))]>,
1489 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1490 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1491 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1493 X86_COND_GE, EFLAGS))]>,
1495 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1496 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1497 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1499 X86_COND_LE, EFLAGS))]>,
1501 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1502 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1503 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1505 X86_COND_LE, EFLAGS))]>,
1507 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1508 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1509 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1511 X86_COND_G, EFLAGS))]>,
1513 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1514 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1515 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1517 X86_COND_G, EFLAGS))]>,
1519 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1520 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1521 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1523 X86_COND_S, EFLAGS))]>,
1525 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1526 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1527 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1529 X86_COND_S, EFLAGS))]>,
1531 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1532 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1533 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1534 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1535 X86_COND_NS, EFLAGS))]>,
1537 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1538 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1539 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1541 X86_COND_NS, EFLAGS))]>,
1543 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1544 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1545 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1547 X86_COND_P, EFLAGS))]>,
1549 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1550 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1551 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1553 X86_COND_P, EFLAGS))]>,
1555 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1556 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1557 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1559 X86_COND_NP, EFLAGS))]>,
1561 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1562 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1563 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1565 X86_COND_NP, EFLAGS))]>,
1567 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1568 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1569 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1571 X86_COND_O, EFLAGS))]>,
1573 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1574 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1575 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1577 X86_COND_O, EFLAGS))]>,
1579 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1580 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1581 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1583 X86_COND_NO, EFLAGS))]>,
1585 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1586 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1587 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1589 X86_COND_NO, EFLAGS))]>,
1591 } // Uses = [EFLAGS]
1594 // unary instructions
1595 let CodeSize = 2 in {
1596 let Defs = [EFLAGS] in {
1597 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1598 [(set GR8:$dst, (ineg GR8:$src)),
1599 (implicit EFLAGS)]>;
1600 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1601 [(set GR16:$dst, (ineg GR16:$src)),
1602 (implicit EFLAGS)]>, OpSize;
1603 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1604 [(set GR32:$dst, (ineg GR32:$src)),
1605 (implicit EFLAGS)]>;
1606 let isTwoAddress = 0 in {
1607 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1608 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1609 (implicit EFLAGS)]>;
1610 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1611 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1612 (implicit EFLAGS)]>, OpSize;
1613 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1614 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1615 (implicit EFLAGS)]>;
1617 } // Defs = [EFLAGS]
1619 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1620 let AddedComplexity = 15 in {
1621 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1622 [(set GR8:$dst, (not GR8:$src))]>;
1623 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1624 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1625 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1626 [(set GR32:$dst, (not GR32:$src))]>;
1628 let isTwoAddress = 0 in {
1629 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1630 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1631 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1632 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1633 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1634 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1638 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1639 let Defs = [EFLAGS] in {
1641 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1642 [(set GR8:$dst, (add GR8:$src, 1)),
1643 (implicit EFLAGS)]>;
1644 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1645 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1647 [(set GR16:$dst, (add GR16:$src, 1)),
1648 (implicit EFLAGS)]>,
1649 OpSize, Requires<[In32BitMode]>;
1650 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1652 [(set GR32:$dst, (add GR32:$src, 1)),
1653 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1655 let isTwoAddress = 0, CodeSize = 2 in {
1656 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1657 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1658 (implicit EFLAGS)]>;
1659 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1660 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1661 (implicit EFLAGS)]>,
1662 OpSize, Requires<[In32BitMode]>;
1663 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1664 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1665 (implicit EFLAGS)]>,
1666 Requires<[In32BitMode]>;
1670 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1671 [(set GR8:$dst, (add GR8:$src, -1)),
1672 (implicit EFLAGS)]>;
1673 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1674 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1676 [(set GR16:$dst, (add GR16:$src, -1)),
1677 (implicit EFLAGS)]>,
1678 OpSize, Requires<[In32BitMode]>;
1679 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1681 [(set GR32:$dst, (add GR32:$src, -1)),
1682 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1685 let isTwoAddress = 0, CodeSize = 2 in {
1686 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1687 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1688 (implicit EFLAGS)]>;
1689 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1690 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1691 (implicit EFLAGS)]>,
1692 OpSize, Requires<[In32BitMode]>;
1693 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1694 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1695 (implicit EFLAGS)]>,
1696 Requires<[In32BitMode]>;
1698 } // Defs = [EFLAGS]
1700 // Logical operators...
1701 let Defs = [EFLAGS] in {
1702 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1703 def AND8rr : I<0x20, MRMDestReg,
1704 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1705 "and{b}\t{$src2, $dst|$dst, $src2}",
1706 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1707 (implicit EFLAGS)]>;
1708 def AND16rr : I<0x21, MRMDestReg,
1709 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1710 "and{w}\t{$src2, $dst|$dst, $src2}",
1711 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1712 (implicit EFLAGS)]>, OpSize;
1713 def AND32rr : I<0x21, MRMDestReg,
1714 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1715 "and{l}\t{$src2, $dst|$dst, $src2}",
1716 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1717 (implicit EFLAGS)]>;
1720 // AND instructions with the destination register in REG and the source register
1721 // in R/M. Included for the disassembler.
1722 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1723 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1724 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1725 (ins GR16:$src1, GR16:$src2),
1726 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1727 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1728 (ins GR32:$src1, GR32:$src2),
1729 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1731 def AND8rm : I<0x22, MRMSrcMem,
1732 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1733 "and{b}\t{$src2, $dst|$dst, $src2}",
1734 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1735 (implicit EFLAGS)]>;
1736 def AND16rm : I<0x23, MRMSrcMem,
1737 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1738 "and{w}\t{$src2, $dst|$dst, $src2}",
1739 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1740 (implicit EFLAGS)]>, OpSize;
1741 def AND32rm : I<0x23, MRMSrcMem,
1742 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1743 "and{l}\t{$src2, $dst|$dst, $src2}",
1744 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1745 (implicit EFLAGS)]>;
1747 def AND8ri : Ii8<0x80, MRM4r,
1748 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1749 "and{b}\t{$src2, $dst|$dst, $src2}",
1750 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1751 (implicit EFLAGS)]>;
1752 def AND16ri : Ii16<0x81, MRM4r,
1753 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1754 "and{w}\t{$src2, $dst|$dst, $src2}",
1755 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1756 (implicit EFLAGS)]>, OpSize;
1757 def AND32ri : Ii32<0x81, MRM4r,
1758 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1759 "and{l}\t{$src2, $dst|$dst, $src2}",
1760 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1761 (implicit EFLAGS)]>;
1762 def AND16ri8 : Ii8<0x83, MRM4r,
1763 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1764 "and{w}\t{$src2, $dst|$dst, $src2}",
1765 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1766 (implicit EFLAGS)]>,
1768 def AND32ri8 : Ii8<0x83, MRM4r,
1769 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1770 "and{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1772 (implicit EFLAGS)]>;
1774 let isTwoAddress = 0 in {
1775 def AND8mr : I<0x20, MRMDestMem,
1776 (outs), (ins i8mem :$dst, GR8 :$src),
1777 "and{b}\t{$src, $dst|$dst, $src}",
1778 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1779 (implicit EFLAGS)]>;
1780 def AND16mr : I<0x21, MRMDestMem,
1781 (outs), (ins i16mem:$dst, GR16:$src),
1782 "and{w}\t{$src, $dst|$dst, $src}",
1783 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1784 (implicit EFLAGS)]>,
1786 def AND32mr : I<0x21, MRMDestMem,
1787 (outs), (ins i32mem:$dst, GR32:$src),
1788 "and{l}\t{$src, $dst|$dst, $src}",
1789 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1790 (implicit EFLAGS)]>;
1791 def AND8mi : Ii8<0x80, MRM4m,
1792 (outs), (ins i8mem :$dst, i8imm :$src),
1793 "and{b}\t{$src, $dst|$dst, $src}",
1794 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1795 (implicit EFLAGS)]>;
1796 def AND16mi : Ii16<0x81, MRM4m,
1797 (outs), (ins i16mem:$dst, i16imm:$src),
1798 "and{w}\t{$src, $dst|$dst, $src}",
1799 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1800 (implicit EFLAGS)]>,
1802 def AND32mi : Ii32<0x81, MRM4m,
1803 (outs), (ins i32mem:$dst, i32imm:$src),
1804 "and{l}\t{$src, $dst|$dst, $src}",
1805 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1806 (implicit EFLAGS)]>;
1807 def AND16mi8 : Ii8<0x83, MRM4m,
1808 (outs), (ins i16mem:$dst, i16i8imm :$src),
1809 "and{w}\t{$src, $dst|$dst, $src}",
1810 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1811 (implicit EFLAGS)]>,
1813 def AND32mi8 : Ii8<0x83, MRM4m,
1814 (outs), (ins i32mem:$dst, i32i8imm :$src),
1815 "and{l}\t{$src, $dst|$dst, $src}",
1816 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1817 (implicit EFLAGS)]>;
1819 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1820 "and{b}\t{$src, %al|%al, $src}", []>;
1821 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1822 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1823 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1824 "and{l}\t{$src, %eax|%eax, $src}", []>;
1829 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1830 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1831 (ins GR8 :$src1, GR8 :$src2),
1832 "or{b}\t{$src2, $dst|$dst, $src2}",
1833 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1834 (implicit EFLAGS)]>;
1835 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1836 (ins GR16:$src1, GR16:$src2),
1837 "or{w}\t{$src2, $dst|$dst, $src2}",
1838 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1839 (implicit EFLAGS)]>, OpSize;
1840 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1841 (ins GR32:$src1, GR32:$src2),
1842 "or{l}\t{$src2, $dst|$dst, $src2}",
1843 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1844 (implicit EFLAGS)]>;
1847 // OR instructions with the destination register in REG and the source register
1848 // in R/M. Included for the disassembler.
1849 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1850 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1851 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1852 (ins GR16:$src1, GR16:$src2),
1853 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1854 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1855 (ins GR32:$src1, GR32:$src2),
1856 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1858 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1859 (ins GR8 :$src1, i8mem :$src2),
1860 "or{b}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1862 (implicit EFLAGS)]>;
1863 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1864 (ins GR16:$src1, i16mem:$src2),
1865 "or{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1867 (implicit EFLAGS)]>, OpSize;
1868 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1869 (ins GR32:$src1, i32mem:$src2),
1870 "or{l}\t{$src2, $dst|$dst, $src2}",
1871 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1872 (implicit EFLAGS)]>;
1874 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1875 (ins GR8 :$src1, i8imm:$src2),
1876 "or{b}\t{$src2, $dst|$dst, $src2}",
1877 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1878 (implicit EFLAGS)]>;
1879 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1880 (ins GR16:$src1, i16imm:$src2),
1881 "or{w}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1883 (implicit EFLAGS)]>, OpSize;
1884 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1885 (ins GR32:$src1, i32imm:$src2),
1886 "or{l}\t{$src2, $dst|$dst, $src2}",
1887 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1888 (implicit EFLAGS)]>;
1890 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1891 (ins GR16:$src1, i16i8imm:$src2),
1892 "or{w}\t{$src2, $dst|$dst, $src2}",
1893 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1894 (implicit EFLAGS)]>, OpSize;
1895 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1896 (ins GR32:$src1, i32i8imm:$src2),
1897 "or{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1899 (implicit EFLAGS)]>;
1900 let isTwoAddress = 0 in {
1901 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1902 "or{b}\t{$src, $dst|$dst, $src}",
1903 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1904 (implicit EFLAGS)]>;
1905 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1906 "or{w}\t{$src, $dst|$dst, $src}",
1907 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1908 (implicit EFLAGS)]>, OpSize;
1909 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1910 "or{l}\t{$src, $dst|$dst, $src}",
1911 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1912 (implicit EFLAGS)]>;
1913 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1914 "or{b}\t{$src, $dst|$dst, $src}",
1915 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1916 (implicit EFLAGS)]>;
1917 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1918 "or{w}\t{$src, $dst|$dst, $src}",
1919 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1920 (implicit EFLAGS)]>,
1922 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1923 "or{l}\t{$src, $dst|$dst, $src}",
1924 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1925 (implicit EFLAGS)]>;
1926 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1927 "or{w}\t{$src, $dst|$dst, $src}",
1928 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1929 (implicit EFLAGS)]>,
1931 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1932 "or{l}\t{$src, $dst|$dst, $src}",
1933 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1934 (implicit EFLAGS)]>;
1936 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1937 "or{b}\t{$src, %al|%al, $src}", []>;
1938 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1939 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1940 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1941 "or{l}\t{$src, %eax|%eax, $src}", []>;
1942 } // isTwoAddress = 0
1945 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1946 def XOR8rr : I<0x30, MRMDestReg,
1947 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1948 "xor{b}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1950 (implicit EFLAGS)]>;
1951 def XOR16rr : I<0x31, MRMDestReg,
1952 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1953 "xor{w}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1955 (implicit EFLAGS)]>, OpSize;
1956 def XOR32rr : I<0x31, MRMDestReg,
1957 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1958 "xor{l}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1960 (implicit EFLAGS)]>;
1961 } // isCommutable = 1
1963 // XOR instructions with the destination register in REG and the source register
1964 // in R/M. Included for the disassembler.
1965 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1966 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1967 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1968 (ins GR16:$src1, GR16:$src2),
1969 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1970 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1971 (ins GR32:$src1, GR32:$src2),
1972 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1974 def XOR8rm : I<0x32, MRMSrcMem ,
1975 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1976 "xor{b}\t{$src2, $dst|$dst, $src2}",
1977 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1978 (implicit EFLAGS)]>;
1979 def XOR16rm : I<0x33, MRMSrcMem ,
1980 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1981 "xor{w}\t{$src2, $dst|$dst, $src2}",
1982 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1983 (implicit EFLAGS)]>,
1985 def XOR32rm : I<0x33, MRMSrcMem ,
1986 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1987 "xor{l}\t{$src2, $dst|$dst, $src2}",
1988 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1989 (implicit EFLAGS)]>;
1991 def XOR8ri : Ii8<0x80, MRM6r,
1992 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1993 "xor{b}\t{$src2, $dst|$dst, $src2}",
1994 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1995 (implicit EFLAGS)]>;
1996 def XOR16ri : Ii16<0x81, MRM6r,
1997 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1998 "xor{w}\t{$src2, $dst|$dst, $src2}",
1999 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2000 (implicit EFLAGS)]>, OpSize;
2001 def XOR32ri : Ii32<0x81, MRM6r,
2002 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2003 "xor{l}\t{$src2, $dst|$dst, $src2}",
2004 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2005 (implicit EFLAGS)]>;
2006 def XOR16ri8 : Ii8<0x83, MRM6r,
2007 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2008 "xor{w}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2010 (implicit EFLAGS)]>,
2012 def XOR32ri8 : Ii8<0x83, MRM6r,
2013 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2014 "xor{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2016 (implicit EFLAGS)]>;
2018 let isTwoAddress = 0 in {
2019 def XOR8mr : I<0x30, MRMDestMem,
2020 (outs), (ins i8mem :$dst, GR8 :$src),
2021 "xor{b}\t{$src, $dst|$dst, $src}",
2022 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2023 (implicit EFLAGS)]>;
2024 def XOR16mr : I<0x31, MRMDestMem,
2025 (outs), (ins i16mem:$dst, GR16:$src),
2026 "xor{w}\t{$src, $dst|$dst, $src}",
2027 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2028 (implicit EFLAGS)]>,
2030 def XOR32mr : I<0x31, MRMDestMem,
2031 (outs), (ins i32mem:$dst, GR32:$src),
2032 "xor{l}\t{$src, $dst|$dst, $src}",
2033 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2034 (implicit EFLAGS)]>;
2035 def XOR8mi : Ii8<0x80, MRM6m,
2036 (outs), (ins i8mem :$dst, i8imm :$src),
2037 "xor{b}\t{$src, $dst|$dst, $src}",
2038 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2039 (implicit EFLAGS)]>;
2040 def XOR16mi : Ii16<0x81, MRM6m,
2041 (outs), (ins i16mem:$dst, i16imm:$src),
2042 "xor{w}\t{$src, $dst|$dst, $src}",
2043 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2044 (implicit EFLAGS)]>,
2046 def XOR32mi : Ii32<0x81, MRM6m,
2047 (outs), (ins i32mem:$dst, i32imm:$src),
2048 "xor{l}\t{$src, $dst|$dst, $src}",
2049 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2050 (implicit EFLAGS)]>;
2051 def XOR16mi8 : Ii8<0x83, MRM6m,
2052 (outs), (ins i16mem:$dst, i16i8imm :$src),
2053 "xor{w}\t{$src, $dst|$dst, $src}",
2054 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2055 (implicit EFLAGS)]>,
2057 def XOR32mi8 : Ii8<0x83, MRM6m,
2058 (outs), (ins i32mem:$dst, i32i8imm :$src),
2059 "xor{l}\t{$src, $dst|$dst, $src}",
2060 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2061 (implicit EFLAGS)]>;
2063 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2064 "xor{b}\t{$src, %al|%al, $src}", []>;
2065 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2066 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2067 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2068 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2069 } // isTwoAddress = 0
2070 } // Defs = [EFLAGS]
2072 // Shift instructions
2073 let Defs = [EFLAGS] in {
2074 let Uses = [CL] in {
2075 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2076 "shl{b}\t{%cl, $dst|$dst, CL}",
2077 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2078 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2079 "shl{w}\t{%cl, $dst|$dst, CL}",
2080 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2081 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2082 "shl{l}\t{%cl, $dst|$dst, CL}",
2083 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2086 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2087 "shl{b}\t{$src2, $dst|$dst, $src2}",
2088 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2089 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2090 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2091 "shl{w}\t{$src2, $dst|$dst, $src2}",
2092 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2093 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2094 "shl{l}\t{$src2, $dst|$dst, $src2}",
2095 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2097 // NOTE: We don't include patterns for shifts of a register by one, because
2098 // 'add reg,reg' is cheaper.
2100 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2101 "shl{b}\t$dst", []>;
2102 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2103 "shl{w}\t$dst", []>, OpSize;
2104 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2105 "shl{l}\t$dst", []>;
2107 } // isConvertibleToThreeAddress = 1
2109 let isTwoAddress = 0 in {
2110 let Uses = [CL] in {
2111 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2112 "shl{b}\t{%cl, $dst|$dst, CL}",
2113 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2114 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2115 "shl{w}\t{%cl, $dst|$dst, CL}",
2116 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2117 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2118 "shl{l}\t{%cl, $dst|$dst, CL}",
2119 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2121 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2122 "shl{b}\t{$src, $dst|$dst, $src}",
2123 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2124 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2125 "shl{w}\t{$src, $dst|$dst, $src}",
2126 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2128 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2129 "shl{l}\t{$src, $dst|$dst, $src}",
2130 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2133 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2135 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2136 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2138 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2140 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2142 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2145 let Uses = [CL] in {
2146 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2147 "shr{b}\t{%cl, $dst|$dst, CL}",
2148 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2149 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2150 "shr{w}\t{%cl, $dst|$dst, CL}",
2151 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2152 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2153 "shr{l}\t{%cl, $dst|$dst, CL}",
2154 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2157 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2158 "shr{b}\t{$src2, $dst|$dst, $src2}",
2159 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2160 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2161 "shr{w}\t{$src2, $dst|$dst, $src2}",
2162 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2163 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2164 "shr{l}\t{$src2, $dst|$dst, $src2}",
2165 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2168 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2170 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2171 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2173 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2174 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2176 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2178 let isTwoAddress = 0 in {
2179 let Uses = [CL] in {
2180 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2181 "shr{b}\t{%cl, $dst|$dst, CL}",
2182 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2183 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2184 "shr{w}\t{%cl, $dst|$dst, CL}",
2185 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2187 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2188 "shr{l}\t{%cl, $dst|$dst, CL}",
2189 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2191 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2192 "shr{b}\t{$src, $dst|$dst, $src}",
2193 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2194 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2195 "shr{w}\t{$src, $dst|$dst, $src}",
2196 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2198 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2199 "shr{l}\t{$src, $dst|$dst, $src}",
2200 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2203 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2205 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2206 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2208 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2209 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2211 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2214 let Uses = [CL] in {
2215 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2216 "sar{b}\t{%cl, $dst|$dst, CL}",
2217 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2218 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2219 "sar{w}\t{%cl, $dst|$dst, CL}",
2220 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2221 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2222 "sar{l}\t{%cl, $dst|$dst, CL}",
2223 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2226 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2227 "sar{b}\t{$src2, $dst|$dst, $src2}",
2228 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2229 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2230 "sar{w}\t{$src2, $dst|$dst, $src2}",
2231 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2233 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2234 "sar{l}\t{$src2, $dst|$dst, $src2}",
2235 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2238 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2240 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2241 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2243 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2244 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2246 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2248 let isTwoAddress = 0 in {
2249 let Uses = [CL] in {
2250 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2251 "sar{b}\t{%cl, $dst|$dst, CL}",
2252 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2253 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2254 "sar{w}\t{%cl, $dst|$dst, CL}",
2255 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2256 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2257 "sar{l}\t{%cl, $dst|$dst, CL}",
2258 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2260 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2261 "sar{b}\t{$src, $dst|$dst, $src}",
2262 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2263 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2264 "sar{w}\t{$src, $dst|$dst, $src}",
2265 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2267 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2268 "sar{l}\t{$src, $dst|$dst, $src}",
2269 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2272 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2274 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2275 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2277 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2279 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2281 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2284 // Rotate instructions
2286 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2287 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2288 def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2289 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2290 let Uses = [CL] in {
2291 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2292 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2293 def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2294 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2296 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2297 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2298 def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2299 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2301 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2302 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2303 def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2304 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2305 let Uses = [CL] in {
2306 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2307 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2308 def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2309 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2311 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2312 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2313 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst),
2314 (ins i16mem:$src, i8imm:$cnt),
2315 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2317 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2318 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2319 def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2320 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2321 let Uses = [CL] in {
2322 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2323 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2324 def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2325 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2327 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2328 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2329 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst),
2330 (ins i32mem:$src, i8imm:$cnt),
2331 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2333 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2334 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2335 def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2336 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2337 let Uses = [CL] in {
2338 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2339 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2340 def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2341 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2343 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2344 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2345 def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2346 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2348 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2349 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2350 def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2351 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2352 let Uses = [CL] in {
2353 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2354 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2355 def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2356 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2358 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2359 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2360 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst),
2361 (ins i16mem:$src, i8imm:$cnt),
2362 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2364 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2365 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2366 def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2367 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2368 let Uses = [CL] in {
2369 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2370 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2371 def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2372 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2374 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2375 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2376 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst),
2377 (ins i32mem:$src, i8imm:$cnt),
2378 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2380 // FIXME: provide shorter instructions when imm8 == 1
2381 let Uses = [CL] in {
2382 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2383 "rol{b}\t{%cl, $dst|$dst, CL}",
2384 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2385 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2386 "rol{w}\t{%cl, $dst|$dst, CL}",
2387 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2388 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2389 "rol{l}\t{%cl, $dst|$dst, CL}",
2390 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2393 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2394 "rol{b}\t{$src2, $dst|$dst, $src2}",
2395 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2396 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2397 "rol{w}\t{$src2, $dst|$dst, $src2}",
2398 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2400 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2401 "rol{l}\t{$src2, $dst|$dst, $src2}",
2402 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2405 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2407 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2408 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2410 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2411 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2413 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2415 let isTwoAddress = 0 in {
2416 let Uses = [CL] in {
2417 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2418 "rol{b}\t{%cl, $dst|$dst, CL}",
2419 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2420 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2421 "rol{w}\t{%cl, $dst|$dst, CL}",
2422 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2423 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2424 "rol{l}\t{%cl, $dst|$dst, CL}",
2425 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2427 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2428 "rol{b}\t{$src, $dst|$dst, $src}",
2429 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2430 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2431 "rol{w}\t{$src, $dst|$dst, $src}",
2432 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2434 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2435 "rol{l}\t{$src, $dst|$dst, $src}",
2436 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2439 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2441 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2442 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2444 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2446 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2448 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2451 let Uses = [CL] in {
2452 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2453 "ror{b}\t{%cl, $dst|$dst, CL}",
2454 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2455 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2456 "ror{w}\t{%cl, $dst|$dst, CL}",
2457 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2458 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2459 "ror{l}\t{%cl, $dst|$dst, CL}",
2460 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2463 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2464 "ror{b}\t{$src2, $dst|$dst, $src2}",
2465 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2466 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2467 "ror{w}\t{$src2, $dst|$dst, $src2}",
2468 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2470 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2471 "ror{l}\t{$src2, $dst|$dst, $src2}",
2472 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2475 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2477 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2478 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2480 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2481 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2483 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2485 let isTwoAddress = 0 in {
2486 let Uses = [CL] in {
2487 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2488 "ror{b}\t{%cl, $dst|$dst, CL}",
2489 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2490 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2491 "ror{w}\t{%cl, $dst|$dst, CL}",
2492 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2493 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2494 "ror{l}\t{%cl, $dst|$dst, CL}",
2495 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2497 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2498 "ror{b}\t{$src, $dst|$dst, $src}",
2499 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2500 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2501 "ror{w}\t{$src, $dst|$dst, $src}",
2502 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2504 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2505 "ror{l}\t{$src, $dst|$dst, $src}",
2506 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2509 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2511 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2512 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2514 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2516 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2518 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2523 // Double shift instructions (generalizations of rotate)
2524 let Uses = [CL] in {
2525 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2526 (ins GR32:$src1, GR32:$src2),
2527 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2528 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2529 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2530 (ins GR32:$src1, GR32:$src2),
2531 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2532 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2533 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2534 (ins GR16:$src1, GR16:$src2),
2535 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2536 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2538 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2539 (ins GR16:$src1, GR16:$src2),
2540 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2541 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2545 let isCommutable = 1 in { // These instructions commute to each other.
2546 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2548 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2549 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2550 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2553 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2555 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2556 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2557 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2560 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2562 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2563 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2564 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2567 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2569 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2570 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2571 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2576 let isTwoAddress = 0 in {
2577 let Uses = [CL] in {
2578 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2579 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2580 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2582 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2583 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2584 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2587 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2588 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2589 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2590 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2591 (i8 imm:$src3)), addr:$dst)]>,
2593 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2594 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2595 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2596 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2597 (i8 imm:$src3)), addr:$dst)]>,
2600 let Uses = [CL] in {
2601 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2602 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2603 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2604 addr:$dst)]>, TB, OpSize;
2605 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2606 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2607 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2608 addr:$dst)]>, TB, OpSize;
2610 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2611 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2612 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2613 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2614 (i8 imm:$src3)), addr:$dst)]>,
2616 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2617 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2618 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2619 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2620 (i8 imm:$src3)), addr:$dst)]>,
2623 } // Defs = [EFLAGS]
2627 let Defs = [EFLAGS] in {
2628 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2629 // Register-Register Addition
2630 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2631 (ins GR8 :$src1, GR8 :$src2),
2632 "add{b}\t{$src2, $dst|$dst, $src2}",
2633 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2634 (implicit EFLAGS)]>;
2636 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2637 // Register-Register Addition
2638 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2639 (ins GR16:$src1, GR16:$src2),
2640 "add{w}\t{$src2, $dst|$dst, $src2}",
2641 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2642 (implicit EFLAGS)]>, OpSize;
2643 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2644 (ins GR32:$src1, GR32:$src2),
2645 "add{l}\t{$src2, $dst|$dst, $src2}",
2646 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2647 (implicit EFLAGS)]>;
2648 } // end isConvertibleToThreeAddress
2649 } // end isCommutable
2651 // Register-Memory Addition
2652 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2653 (ins GR8 :$src1, i8mem :$src2),
2654 "add{b}\t{$src2, $dst|$dst, $src2}",
2655 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2656 (implicit EFLAGS)]>;
2657 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2658 (ins GR16:$src1, i16mem:$src2),
2659 "add{w}\t{$src2, $dst|$dst, $src2}",
2660 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2661 (implicit EFLAGS)]>, OpSize;
2662 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2663 (ins GR32:$src1, i32mem:$src2),
2664 "add{l}\t{$src2, $dst|$dst, $src2}",
2665 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2666 (implicit EFLAGS)]>;
2668 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2669 // ADD16rr, and ADD32rr), but differently encoded.
2670 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2671 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2672 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2673 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2674 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2675 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2677 // Register-Integer Addition
2678 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2679 "add{b}\t{$src2, $dst|$dst, $src2}",
2680 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2681 (implicit EFLAGS)]>;
2683 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2684 // Register-Integer Addition
2685 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2686 (ins GR16:$src1, i16imm:$src2),
2687 "add{w}\t{$src2, $dst|$dst, $src2}",
2688 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2689 (implicit EFLAGS)]>, OpSize;
2690 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2691 (ins GR32:$src1, i32imm:$src2),
2692 "add{l}\t{$src2, $dst|$dst, $src2}",
2693 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2694 (implicit EFLAGS)]>;
2695 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2696 (ins GR16:$src1, i16i8imm:$src2),
2697 "add{w}\t{$src2, $dst|$dst, $src2}",
2698 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2699 (implicit EFLAGS)]>, OpSize;
2700 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2701 (ins GR32:$src1, i32i8imm:$src2),
2702 "add{l}\t{$src2, $dst|$dst, $src2}",
2703 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2704 (implicit EFLAGS)]>;
2707 let isTwoAddress = 0 in {
2708 // Memory-Register Addition
2709 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2710 "add{b}\t{$src2, $dst|$dst, $src2}",
2711 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2712 (implicit EFLAGS)]>;
2713 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2714 "add{w}\t{$src2, $dst|$dst, $src2}",
2715 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2716 (implicit EFLAGS)]>, OpSize;
2717 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2718 "add{l}\t{$src2, $dst|$dst, $src2}",
2719 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2720 (implicit EFLAGS)]>;
2721 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2722 "add{b}\t{$src2, $dst|$dst, $src2}",
2723 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2724 (implicit EFLAGS)]>;
2725 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2726 "add{w}\t{$src2, $dst|$dst, $src2}",
2727 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2728 (implicit EFLAGS)]>, OpSize;
2729 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2730 "add{l}\t{$src2, $dst|$dst, $src2}",
2731 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2732 (implicit EFLAGS)]>;
2733 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2734 "add{w}\t{$src2, $dst|$dst, $src2}",
2735 [(store (add (load addr:$dst), i16immSExt8:$src2),
2737 (implicit EFLAGS)]>, OpSize;
2738 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2739 "add{l}\t{$src2, $dst|$dst, $src2}",
2740 [(store (add (load addr:$dst), i32immSExt8:$src2),
2742 (implicit EFLAGS)]>;
2745 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2746 "add{b}\t{$src, %al|%al, $src}", []>;
2747 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2748 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2749 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2750 "add{l}\t{$src, %eax|%eax, $src}", []>;
2753 let Uses = [EFLAGS] in {
2754 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2755 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2756 "adc{b}\t{$src2, $dst|$dst, $src2}",
2757 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2758 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2759 (ins GR16:$src1, GR16:$src2),
2760 "adc{w}\t{$src2, $dst|$dst, $src2}",
2761 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2762 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2763 (ins GR32:$src1, GR32:$src2),
2764 "adc{l}\t{$src2, $dst|$dst, $src2}",
2765 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2768 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2769 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2770 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2771 (ins GR16:$src1, GR16:$src2),
2772 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2773 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2774 (ins GR32:$src1, GR32:$src2),
2775 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2777 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2778 (ins GR8:$src1, i8mem:$src2),
2779 "adc{b}\t{$src2, $dst|$dst, $src2}",
2780 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2781 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2782 (ins GR16:$src1, i16mem:$src2),
2783 "adc{w}\t{$src2, $dst|$dst, $src2}",
2784 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2786 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2787 (ins GR32:$src1, i32mem:$src2),
2788 "adc{l}\t{$src2, $dst|$dst, $src2}",
2789 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2790 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2791 "adc{b}\t{$src2, $dst|$dst, $src2}",
2792 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2793 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2794 (ins GR16:$src1, i16imm:$src2),
2795 "adc{w}\t{$src2, $dst|$dst, $src2}",
2796 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2797 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2798 (ins GR16:$src1, i16i8imm:$src2),
2799 "adc{w}\t{$src2, $dst|$dst, $src2}",
2800 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2802 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2803 (ins GR32:$src1, i32imm:$src2),
2804 "adc{l}\t{$src2, $dst|$dst, $src2}",
2805 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2806 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2807 (ins GR32:$src1, i32i8imm:$src2),
2808 "adc{l}\t{$src2, $dst|$dst, $src2}",
2809 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2811 let isTwoAddress = 0 in {
2812 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2813 "adc{b}\t{$src2, $dst|$dst, $src2}",
2814 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2815 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2816 "adc{w}\t{$src2, $dst|$dst, $src2}",
2817 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2819 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2820 "adc{l}\t{$src2, $dst|$dst, $src2}",
2821 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2822 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2823 "adc{b}\t{$src2, $dst|$dst, $src2}",
2824 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2825 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2826 "adc{w}\t{$src2, $dst|$dst, $src2}",
2827 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2829 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2830 "adc{w}\t{$src2, $dst|$dst, $src2}",
2831 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2833 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2834 "adc{l}\t{$src2, $dst|$dst, $src2}",
2835 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2836 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2837 "adc{l}\t{$src2, $dst|$dst, $src2}",
2838 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2840 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2841 "adc{b}\t{$src, %al|%al, $src}", []>;
2842 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2843 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2844 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2845 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2847 } // Uses = [EFLAGS]
2849 // Register-Register Subtraction
2850 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2851 "sub{b}\t{$src2, $dst|$dst, $src2}",
2852 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2853 (implicit EFLAGS)]>;
2854 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2855 "sub{w}\t{$src2, $dst|$dst, $src2}",
2856 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2857 (implicit EFLAGS)]>, OpSize;
2858 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2859 "sub{l}\t{$src2, $dst|$dst, $src2}",
2860 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2861 (implicit EFLAGS)]>;
2863 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2864 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2865 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2866 (ins GR16:$src1, GR16:$src2),
2867 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2868 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2869 (ins GR32:$src1, GR32:$src2),
2870 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2872 // Register-Memory Subtraction
2873 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2874 (ins GR8 :$src1, i8mem :$src2),
2875 "sub{b}\t{$src2, $dst|$dst, $src2}",
2876 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2877 (implicit EFLAGS)]>;
2878 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2879 (ins GR16:$src1, i16mem:$src2),
2880 "sub{w}\t{$src2, $dst|$dst, $src2}",
2881 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2882 (implicit EFLAGS)]>, OpSize;
2883 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2884 (ins GR32:$src1, i32mem:$src2),
2885 "sub{l}\t{$src2, $dst|$dst, $src2}",
2886 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2887 (implicit EFLAGS)]>;
2889 // Register-Integer Subtraction
2890 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2891 (ins GR8:$src1, i8imm:$src2),
2892 "sub{b}\t{$src2, $dst|$dst, $src2}",
2893 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2894 (implicit EFLAGS)]>;
2895 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2896 (ins GR16:$src1, i16imm:$src2),
2897 "sub{w}\t{$src2, $dst|$dst, $src2}",
2898 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2899 (implicit EFLAGS)]>, OpSize;
2900 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2901 (ins GR32:$src1, i32imm:$src2),
2902 "sub{l}\t{$src2, $dst|$dst, $src2}",
2903 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2904 (implicit EFLAGS)]>;
2905 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2906 (ins GR16:$src1, i16i8imm:$src2),
2907 "sub{w}\t{$src2, $dst|$dst, $src2}",
2908 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2909 (implicit EFLAGS)]>, OpSize;
2910 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2911 (ins GR32:$src1, i32i8imm:$src2),
2912 "sub{l}\t{$src2, $dst|$dst, $src2}",
2913 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2914 (implicit EFLAGS)]>;
2916 let isTwoAddress = 0 in {
2917 // Memory-Register Subtraction
2918 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2919 "sub{b}\t{$src2, $dst|$dst, $src2}",
2920 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2921 (implicit EFLAGS)]>;
2922 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2923 "sub{w}\t{$src2, $dst|$dst, $src2}",
2924 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2925 (implicit EFLAGS)]>, OpSize;
2926 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2927 "sub{l}\t{$src2, $dst|$dst, $src2}",
2928 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2929 (implicit EFLAGS)]>;
2931 // Memory-Integer Subtraction
2932 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2933 "sub{b}\t{$src2, $dst|$dst, $src2}",
2934 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2935 (implicit EFLAGS)]>;
2936 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2937 "sub{w}\t{$src2, $dst|$dst, $src2}",
2938 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2939 (implicit EFLAGS)]>, OpSize;
2940 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2941 "sub{l}\t{$src2, $dst|$dst, $src2}",
2942 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2943 (implicit EFLAGS)]>;
2944 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2945 "sub{w}\t{$src2, $dst|$dst, $src2}",
2946 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2948 (implicit EFLAGS)]>, OpSize;
2949 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2950 "sub{l}\t{$src2, $dst|$dst, $src2}",
2951 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2953 (implicit EFLAGS)]>;
2955 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2956 "sub{b}\t{$src, %al|%al, $src}", []>;
2957 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2958 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2959 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2960 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2963 let Uses = [EFLAGS] in {
2964 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2965 (ins GR8:$src1, GR8:$src2),
2966 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2967 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2968 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2969 (ins GR16:$src1, GR16:$src2),
2970 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2971 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2972 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2973 (ins GR32:$src1, GR32:$src2),
2974 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2975 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2977 let isTwoAddress = 0 in {
2978 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2979 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2980 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2981 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2982 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2983 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2985 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2986 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2987 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2988 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2989 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2990 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2991 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2992 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2993 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2995 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2996 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2997 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2999 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3000 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3001 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3002 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3003 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3004 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3006 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3007 "sbb{b}\t{$src, %al|%al, $src}", []>;
3008 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3009 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3010 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3011 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3014 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3015 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3016 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3017 (ins GR16:$src1, GR16:$src2),
3018 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3019 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3020 (ins GR32:$src1, GR32:$src2),
3021 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3023 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3024 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3025 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3026 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3027 (ins GR16:$src1, i16mem:$src2),
3028 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3029 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3031 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3032 (ins GR32:$src1, i32mem:$src2),
3033 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3034 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3035 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3036 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3037 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3038 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3039 (ins GR16:$src1, i16imm:$src2),
3040 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3041 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3042 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3043 (ins GR16:$src1, i16i8imm:$src2),
3044 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3047 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3048 (ins GR32:$src1, i32imm:$src2),
3049 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3050 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3051 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3052 (ins GR32:$src1, i32i8imm:$src2),
3053 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3054 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3055 } // Uses = [EFLAGS]
3056 } // Defs = [EFLAGS]
3058 let Defs = [EFLAGS] in {
3059 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3060 // Register-Register Signed Integer Multiply
3061 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3062 "imul{w}\t{$src2, $dst|$dst, $src2}",
3063 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3064 (implicit EFLAGS)]>, TB, OpSize;
3065 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3066 "imul{l}\t{$src2, $dst|$dst, $src2}",
3067 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3068 (implicit EFLAGS)]>, TB;
3071 // Register-Memory Signed Integer Multiply
3072 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3073 (ins GR16:$src1, i16mem:$src2),
3074 "imul{w}\t{$src2, $dst|$dst, $src2}",
3075 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3076 (implicit EFLAGS)]>, TB, OpSize;
3077 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3078 (ins GR32:$src1, i32mem:$src2),
3079 "imul{l}\t{$src2, $dst|$dst, $src2}",
3080 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3081 (implicit EFLAGS)]>, TB;
3082 } // Defs = [EFLAGS]
3083 } // end Two Address instructions
3085 // Suprisingly enough, these are not two address instructions!
3086 let Defs = [EFLAGS] in {
3087 // Register-Integer Signed Integer Multiply
3088 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3089 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3090 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3091 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3092 (implicit EFLAGS)]>, OpSize;
3093 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3094 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3095 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3096 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3097 (implicit EFLAGS)]>;
3098 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3099 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3100 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3101 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3102 (implicit EFLAGS)]>, OpSize;
3103 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3104 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3105 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3106 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3107 (implicit EFLAGS)]>;
3109 // Memory-Integer Signed Integer Multiply
3110 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3111 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3112 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3113 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3114 (implicit EFLAGS)]>, OpSize;
3115 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3116 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3117 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3118 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3119 (implicit EFLAGS)]>;
3120 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3121 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3122 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3123 [(set GR16:$dst, (mul (load addr:$src1),
3124 i16immSExt8:$src2)),
3125 (implicit EFLAGS)]>, OpSize;
3126 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3127 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3128 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3129 [(set GR32:$dst, (mul (load addr:$src1),
3130 i32immSExt8:$src2)),
3131 (implicit EFLAGS)]>;
3132 } // Defs = [EFLAGS]
3134 //===----------------------------------------------------------------------===//
3135 // Test instructions are just like AND, except they don't generate a result.
3137 let Defs = [EFLAGS] in {
3138 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3139 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3140 "test{b}\t{$src2, $src1|$src1, $src2}",
3141 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3142 (implicit EFLAGS)]>;
3143 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3144 "test{w}\t{$src2, $src1|$src1, $src2}",
3145 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3146 (implicit EFLAGS)]>,
3148 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3149 "test{l}\t{$src2, $src1|$src1, $src2}",
3150 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3151 (implicit EFLAGS)]>;
3154 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3155 "test{b}\t{$src, %al|%al, $src}", []>;
3156 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3157 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3158 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3159 "test{l}\t{$src, %eax|%eax, $src}", []>;
3161 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3162 "test{b}\t{$src2, $src1|$src1, $src2}",
3163 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3164 (implicit EFLAGS)]>;
3165 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3166 "test{w}\t{$src2, $src1|$src1, $src2}",
3167 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3168 (implicit EFLAGS)]>, OpSize;
3169 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3170 "test{l}\t{$src2, $src1|$src1, $src2}",
3171 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3172 (implicit EFLAGS)]>;
3174 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3175 (outs), (ins GR8:$src1, i8imm:$src2),
3176 "test{b}\t{$src2, $src1|$src1, $src2}",
3177 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3178 (implicit EFLAGS)]>;
3179 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3180 (outs), (ins GR16:$src1, i16imm:$src2),
3181 "test{w}\t{$src2, $src1|$src1, $src2}",
3182 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3183 (implicit EFLAGS)]>, OpSize;
3184 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3185 (outs), (ins GR32:$src1, i32imm:$src2),
3186 "test{l}\t{$src2, $src1|$src1, $src2}",
3187 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3188 (implicit EFLAGS)]>;
3190 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3191 (outs), (ins i8mem:$src1, i8imm:$src2),
3192 "test{b}\t{$src2, $src1|$src1, $src2}",
3193 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3194 (implicit EFLAGS)]>;
3195 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3196 (outs), (ins i16mem:$src1, i16imm:$src2),
3197 "test{w}\t{$src2, $src1|$src1, $src2}",
3198 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3199 (implicit EFLAGS)]>, OpSize;
3200 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3201 (outs), (ins i32mem:$src1, i32imm:$src2),
3202 "test{l}\t{$src2, $src1|$src1, $src2}",
3203 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3204 (implicit EFLAGS)]>;
3205 } // Defs = [EFLAGS]
3208 // Condition code ops, incl. set if equal/not equal/...
3209 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3210 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3211 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3212 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3214 let Uses = [EFLAGS] in {
3215 // Use sbb to materialize carry bit.
3217 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3218 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
3219 "sbb{b}\t$dst, $dst",
3220 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3221 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
3222 "sbb{w}\t$dst, $dst",
3223 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3225 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
3226 "sbb{l}\t$dst, $dst",
3227 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3230 def SETEr : I<0x94, MRM0r,
3231 (outs GR8 :$dst), (ins),
3233 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3235 def SETEm : I<0x94, MRM0m,
3236 (outs), (ins i8mem:$dst),
3238 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3241 def SETNEr : I<0x95, MRM0r,
3242 (outs GR8 :$dst), (ins),
3244 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3246 def SETNEm : I<0x95, MRM0m,
3247 (outs), (ins i8mem:$dst),
3249 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3252 def SETLr : I<0x9C, MRM0r,
3253 (outs GR8 :$dst), (ins),
3255 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3256 TB; // GR8 = < signed
3257 def SETLm : I<0x9C, MRM0m,
3258 (outs), (ins i8mem:$dst),
3260 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3261 TB; // [mem8] = < signed
3263 def SETGEr : I<0x9D, MRM0r,
3264 (outs GR8 :$dst), (ins),
3266 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3267 TB; // GR8 = >= signed
3268 def SETGEm : I<0x9D, MRM0m,
3269 (outs), (ins i8mem:$dst),
3271 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3272 TB; // [mem8] = >= signed
3274 def SETLEr : I<0x9E, MRM0r,
3275 (outs GR8 :$dst), (ins),
3277 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3278 TB; // GR8 = <= signed
3279 def SETLEm : I<0x9E, MRM0m,
3280 (outs), (ins i8mem:$dst),
3282 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3283 TB; // [mem8] = <= signed
3285 def SETGr : I<0x9F, MRM0r,
3286 (outs GR8 :$dst), (ins),
3288 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3289 TB; // GR8 = > signed
3290 def SETGm : I<0x9F, MRM0m,
3291 (outs), (ins i8mem:$dst),
3293 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3294 TB; // [mem8] = > signed
3296 def SETBr : I<0x92, MRM0r,
3297 (outs GR8 :$dst), (ins),
3299 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3300 TB; // GR8 = < unsign
3301 def SETBm : I<0x92, MRM0m,
3302 (outs), (ins i8mem:$dst),
3304 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3305 TB; // [mem8] = < unsign
3307 def SETAEr : I<0x93, MRM0r,
3308 (outs GR8 :$dst), (ins),
3310 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3311 TB; // GR8 = >= unsign
3312 def SETAEm : I<0x93, MRM0m,
3313 (outs), (ins i8mem:$dst),
3315 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3316 TB; // [mem8] = >= unsign
3318 def SETBEr : I<0x96, MRM0r,
3319 (outs GR8 :$dst), (ins),
3321 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3322 TB; // GR8 = <= unsign
3323 def SETBEm : I<0x96, MRM0m,
3324 (outs), (ins i8mem:$dst),
3326 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3327 TB; // [mem8] = <= unsign
3329 def SETAr : I<0x97, MRM0r,
3330 (outs GR8 :$dst), (ins),
3332 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3333 TB; // GR8 = > signed
3334 def SETAm : I<0x97, MRM0m,
3335 (outs), (ins i8mem:$dst),
3337 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3338 TB; // [mem8] = > signed
3340 def SETSr : I<0x98, MRM0r,
3341 (outs GR8 :$dst), (ins),
3343 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3344 TB; // GR8 = <sign bit>
3345 def SETSm : I<0x98, MRM0m,
3346 (outs), (ins i8mem:$dst),
3348 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3349 TB; // [mem8] = <sign bit>
3350 def SETNSr : I<0x99, MRM0r,
3351 (outs GR8 :$dst), (ins),
3353 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3354 TB; // GR8 = !<sign bit>
3355 def SETNSm : I<0x99, MRM0m,
3356 (outs), (ins i8mem:$dst),
3358 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3359 TB; // [mem8] = !<sign bit>
3361 def SETPr : I<0x9A, MRM0r,
3362 (outs GR8 :$dst), (ins),
3364 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3366 def SETPm : I<0x9A, MRM0m,
3367 (outs), (ins i8mem:$dst),
3369 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3370 TB; // [mem8] = parity
3371 def SETNPr : I<0x9B, MRM0r,
3372 (outs GR8 :$dst), (ins),
3374 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3375 TB; // GR8 = not parity
3376 def SETNPm : I<0x9B, MRM0m,
3377 (outs), (ins i8mem:$dst),
3379 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3380 TB; // [mem8] = not parity
3382 def SETOr : I<0x90, MRM0r,
3383 (outs GR8 :$dst), (ins),
3385 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3386 TB; // GR8 = overflow
3387 def SETOm : I<0x90, MRM0m,
3388 (outs), (ins i8mem:$dst),
3390 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3391 TB; // [mem8] = overflow
3392 def SETNOr : I<0x91, MRM0r,
3393 (outs GR8 :$dst), (ins),
3395 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3396 TB; // GR8 = not overflow
3397 def SETNOm : I<0x91, MRM0m,
3398 (outs), (ins i8mem:$dst),
3400 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3401 TB; // [mem8] = not overflow
3402 } // Uses = [EFLAGS]
3405 // Integer comparisons
3406 let Defs = [EFLAGS] in {
3407 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3408 "cmp{b}\t{$src, %al|%al, $src}", []>;
3409 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3410 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3411 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3412 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3414 def CMP8rr : I<0x38, MRMDestReg,
3415 (outs), (ins GR8 :$src1, GR8 :$src2),
3416 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3417 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3418 def CMP16rr : I<0x39, MRMDestReg,
3419 (outs), (ins GR16:$src1, GR16:$src2),
3420 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3421 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3422 def CMP32rr : I<0x39, MRMDestReg,
3423 (outs), (ins GR32:$src1, GR32:$src2),
3424 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3425 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3426 def CMP8mr : I<0x38, MRMDestMem,
3427 (outs), (ins i8mem :$src1, GR8 :$src2),
3428 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3429 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3430 (implicit EFLAGS)]>;
3431 def CMP16mr : I<0x39, MRMDestMem,
3432 (outs), (ins i16mem:$src1, GR16:$src2),
3433 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3434 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3435 (implicit EFLAGS)]>, OpSize;
3436 def CMP32mr : I<0x39, MRMDestMem,
3437 (outs), (ins i32mem:$src1, GR32:$src2),
3438 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3439 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3440 (implicit EFLAGS)]>;
3441 def CMP8rm : I<0x3A, MRMSrcMem,
3442 (outs), (ins GR8 :$src1, i8mem :$src2),
3443 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3444 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3445 (implicit EFLAGS)]>;
3446 def CMP16rm : I<0x3B, MRMSrcMem,
3447 (outs), (ins GR16:$src1, i16mem:$src2),
3448 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3449 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3450 (implicit EFLAGS)]>, OpSize;
3451 def CMP32rm : I<0x3B, MRMSrcMem,
3452 (outs), (ins GR32:$src1, i32mem:$src2),
3453 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3454 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3455 (implicit EFLAGS)]>;
3456 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3457 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3458 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3459 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3460 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3461 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3462 def CMP8ri : Ii8<0x80, MRM7r,
3463 (outs), (ins GR8:$src1, i8imm:$src2),
3464 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3465 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3466 def CMP16ri : Ii16<0x81, MRM7r,
3467 (outs), (ins GR16:$src1, i16imm:$src2),
3468 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3469 [(X86cmp GR16:$src1, imm:$src2),
3470 (implicit EFLAGS)]>, OpSize;
3471 def CMP32ri : Ii32<0x81, MRM7r,
3472 (outs), (ins GR32:$src1, i32imm:$src2),
3473 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3474 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3475 def CMP8mi : Ii8 <0x80, MRM7m,
3476 (outs), (ins i8mem :$src1, i8imm :$src2),
3477 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3478 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3479 (implicit EFLAGS)]>;
3480 def CMP16mi : Ii16<0x81, MRM7m,
3481 (outs), (ins i16mem:$src1, i16imm:$src2),
3482 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3483 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3484 (implicit EFLAGS)]>, OpSize;
3485 def CMP32mi : Ii32<0x81, MRM7m,
3486 (outs), (ins i32mem:$src1, i32imm:$src2),
3487 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3488 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3489 (implicit EFLAGS)]>;
3490 def CMP16ri8 : Ii8<0x83, MRM7r,
3491 (outs), (ins GR16:$src1, i16i8imm:$src2),
3492 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3493 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3494 (implicit EFLAGS)]>, OpSize;
3495 def CMP16mi8 : Ii8<0x83, MRM7m,
3496 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3497 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3498 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3499 (implicit EFLAGS)]>, OpSize;
3500 def CMP32mi8 : Ii8<0x83, MRM7m,
3501 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3502 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3503 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3504 (implicit EFLAGS)]>;
3505 def CMP32ri8 : Ii8<0x83, MRM7r,
3506 (outs), (ins GR32:$src1, i32i8imm:$src2),
3507 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3508 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3509 (implicit EFLAGS)]>;
3510 } // Defs = [EFLAGS]
3513 // TODO: BTC, BTR, and BTS
3514 let Defs = [EFLAGS] in {
3515 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3516 "bt{w}\t{$src2, $src1|$src1, $src2}",
3517 [(X86bt GR16:$src1, GR16:$src2),
3518 (implicit EFLAGS)]>, OpSize, TB;
3519 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3520 "bt{l}\t{$src2, $src1|$src1, $src2}",
3521 [(X86bt GR32:$src1, GR32:$src2),
3522 (implicit EFLAGS)]>, TB;
3524 // Unlike with the register+register form, the memory+register form of the
3525 // bt instruction does not ignore the high bits of the index. From ISel's
3526 // perspective, this is pretty bizarre. Make these instructions disassembly
3529 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3530 "bt{w}\t{$src2, $src1|$src1, $src2}",
3531 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3532 // (implicit EFLAGS)]
3534 >, OpSize, TB, Requires<[FastBTMem]>;
3535 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3536 "bt{l}\t{$src2, $src1|$src1, $src2}",
3537 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3538 // (implicit EFLAGS)]
3540 >, TB, Requires<[FastBTMem]>;
3542 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3543 "bt{w}\t{$src2, $src1|$src1, $src2}",
3544 [(X86bt GR16:$src1, i16immSExt8:$src2),
3545 (implicit EFLAGS)]>, OpSize, TB;
3546 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3547 "bt{l}\t{$src2, $src1|$src1, $src2}",
3548 [(X86bt GR32:$src1, i32immSExt8:$src2),
3549 (implicit EFLAGS)]>, TB;
3550 // Note that these instructions don't need FastBTMem because that
3551 // only applies when the other operand is in a register. When it's
3552 // an immediate, bt is still fast.
3553 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3554 "bt{w}\t{$src2, $src1|$src1, $src2}",
3555 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3556 (implicit EFLAGS)]>, OpSize, TB;
3557 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3558 "bt{l}\t{$src2, $src1|$src1, $src2}",
3559 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3560 (implicit EFLAGS)]>, TB;
3562 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3563 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3564 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3565 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3566 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3567 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3568 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3569 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3570 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3571 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3572 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3573 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3574 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3575 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3576 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3577 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3579 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3580 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3581 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3582 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3583 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3584 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3585 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3586 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3587 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3588 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3589 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3590 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3591 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3592 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3593 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3594 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3596 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3597 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3598 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3599 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3600 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3601 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3602 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3603 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3604 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3605 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3606 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3607 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3608 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3609 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3610 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3611 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3612 } // Defs = [EFLAGS]
3614 // Sign/Zero extenders
3615 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3616 // of the register here. This has a smaller encoding and avoids a
3617 // partial-register update. Actual movsbw included for the disassembler.
3618 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3619 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3620 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3621 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3622 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3623 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3624 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3625 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3626 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3627 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3628 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3629 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3630 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3631 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3632 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3633 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3634 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3635 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3636 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3637 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3639 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3640 // of the register here. This has a smaller encoding and avoids a
3641 // partial-register update. Actual movzbw included for the disassembler.
3642 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3643 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3644 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3645 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3646 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3647 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3648 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3649 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3650 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3651 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3653 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3654 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3656 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3657 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3659 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3660 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3661 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3663 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3664 // except that they use GR32_NOREX for the output operand register class
3665 // instead of GR32. This allows them to operate on h registers on x86-64.
3666 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3667 (outs GR32_NOREX:$dst), (ins GR8:$src),
3668 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3671 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3672 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3673 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3676 let neverHasSideEffects = 1 in {
3677 let Defs = [AX], Uses = [AL] in
3678 def CBW : I<0x98, RawFrm, (outs), (ins),
3679 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3680 let Defs = [EAX], Uses = [AX] in
3681 def CWDE : I<0x98, RawFrm, (outs), (ins),
3682 "{cwtl|cwde}", []>; // EAX = signext(AX)
3684 let Defs = [AX,DX], Uses = [AX] in
3685 def CWD : I<0x99, RawFrm, (outs), (ins),
3686 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3687 let Defs = [EAX,EDX], Uses = [EAX] in
3688 def CDQ : I<0x99, RawFrm, (outs), (ins),
3689 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3692 //===----------------------------------------------------------------------===//
3693 // Alias Instructions
3694 //===----------------------------------------------------------------------===//
3696 // Alias instructions that map movr0 to xor.
3697 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3698 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3699 isCodeGenOnly = 1 in {
3700 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3701 "xor{b}\t$dst, $dst",
3702 [(set GR8:$dst, 0)]>;
3704 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3705 "xor{l}\t$dst, $dst",
3706 [(set GR32:$dst, 0)]>;
3708 // Use xorl instead of xorw since we don't care about the high 16 bits,
3709 // it's smaller, and it avoids a partial-register update.
3710 //def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3711 // "", [/*(set GR16:$dst, 0)*/]>;
3714 let AddedComplexity = 1 in
3716 (EXTRACT_SUBREG (MOV32r0), x86_subreg_16bit)>;
3718 //===----------------------------------------------------------------------===//
3719 // Thread Local Storage Instructions
3722 // All calls clobber the non-callee saved registers. ESP is marked as
3723 // a use to prevent stack-pointer assignments that appear immediately
3724 // before calls from potentially appearing dead.
3725 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3726 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3727 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3728 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3730 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3731 "leal\t$sym, %eax; "
3732 "call\t___tls_get_addr@PLT",
3733 [(X86tlsaddr tls32addr:$sym)]>,
3734 Requires<[In32BitMode]>;
3736 let AddedComplexity = 5, isCodeGenOnly = 1 in
3737 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3738 "movl\t%gs:$src, $dst",
3739 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3741 let AddedComplexity = 5, isCodeGenOnly = 1 in
3742 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3743 "movl\t%fs:$src, $dst",
3744 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3746 //===----------------------------------------------------------------------===//
3747 // EH Pseudo Instructions
3749 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3750 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3751 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3752 "ret\t#eh_return, addr: $addr",
3753 [(X86ehret GR32:$addr)]>;
3757 //===----------------------------------------------------------------------===//
3761 // Atomic swap. These are just normal xchg instructions. But since a memory
3762 // operand is referenced, the atomicity is ensured.
3763 let Constraints = "$val = $dst" in {
3764 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3765 (ins GR32:$val, i32mem:$ptr),
3766 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3767 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3768 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3769 (ins GR16:$val, i16mem:$ptr),
3770 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3771 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3773 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3774 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3775 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3777 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3778 "xchg{l}\t{$val, $src|$src, $val}", []>;
3779 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3780 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3781 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3782 "xchg{b}\t{$val, $src|$src, $val}", []>;
3785 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3786 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3787 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3788 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3790 // Atomic compare and swap.
3791 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3792 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3794 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3795 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3797 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3798 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3801 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3804 let Defs = [AX, EFLAGS], Uses = [AX] in {
3805 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3807 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3808 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3810 let Defs = [AL, EFLAGS], Uses = [AL] in {
3811 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3813 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3814 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3817 // Atomic exchange and add
3818 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3819 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3821 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3822 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3824 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3826 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3827 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3829 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3831 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3832 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3836 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3837 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3838 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3839 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3840 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3841 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3843 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3844 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3845 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3846 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3847 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3848 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3850 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3851 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3852 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3853 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3854 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3855 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3857 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3858 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3859 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3860 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3861 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3862 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3864 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3865 "cmpxchg8b\t$dst", []>, TB;
3867 // Optimized codegen when the non-memory output is not used.
3868 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3869 let Defs = [EFLAGS] in {
3870 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3872 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3873 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3875 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3876 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3878 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3879 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3881 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3882 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3884 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3885 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3887 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3888 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3890 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3891 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3893 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3895 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3897 "inc{b}\t$dst", []>, LOCK;
3898 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3900 "inc{w}\t$dst", []>, OpSize, LOCK;
3901 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3903 "inc{l}\t$dst", []>, LOCK;
3905 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3907 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3908 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3910 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3911 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3913 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3914 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3916 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3917 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3919 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3920 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3922 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3923 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3925 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3926 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3928 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3930 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3932 "dec{b}\t$dst", []>, LOCK;
3933 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3935 "dec{w}\t$dst", []>, OpSize, LOCK;
3936 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3938 "dec{l}\t$dst", []>, LOCK;
3941 // Atomic exchange, and, or, xor
3942 let Constraints = "$val = $dst", Defs = [EFLAGS],
3943 usesCustomInserter = 1 in {
3944 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3945 "#ATOMAND32 PSEUDO!",
3946 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3947 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3948 "#ATOMOR32 PSEUDO!",
3949 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3950 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3951 "#ATOMXOR32 PSEUDO!",
3952 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3953 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3954 "#ATOMNAND32 PSEUDO!",
3955 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3956 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3957 "#ATOMMIN32 PSEUDO!",
3958 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3959 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3960 "#ATOMMAX32 PSEUDO!",
3961 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3962 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3963 "#ATOMUMIN32 PSEUDO!",
3964 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3965 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3966 "#ATOMUMAX32 PSEUDO!",
3967 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3969 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3970 "#ATOMAND16 PSEUDO!",
3971 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3972 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3973 "#ATOMOR16 PSEUDO!",
3974 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3975 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3976 "#ATOMXOR16 PSEUDO!",
3977 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3978 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3979 "#ATOMNAND16 PSEUDO!",
3980 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3981 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3982 "#ATOMMIN16 PSEUDO!",
3983 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3984 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3985 "#ATOMMAX16 PSEUDO!",
3986 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3987 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3988 "#ATOMUMIN16 PSEUDO!",
3989 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3990 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3991 "#ATOMUMAX16 PSEUDO!",
3992 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3994 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3995 "#ATOMAND8 PSEUDO!",
3996 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3997 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3999 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4000 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4001 "#ATOMXOR8 PSEUDO!",
4002 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4003 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4004 "#ATOMNAND8 PSEUDO!",
4005 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4008 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4009 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4010 Uses = [EAX, EBX, ECX, EDX],
4011 mayLoad = 1, mayStore = 1,
4012 usesCustomInserter = 1 in {
4013 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4014 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4015 "#ATOMAND6432 PSEUDO!", []>;
4016 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4017 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4018 "#ATOMOR6432 PSEUDO!", []>;
4019 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4020 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4021 "#ATOMXOR6432 PSEUDO!", []>;
4022 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4023 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4024 "#ATOMNAND6432 PSEUDO!", []>;
4025 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4026 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4027 "#ATOMADD6432 PSEUDO!", []>;
4028 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4029 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4030 "#ATOMSUB6432 PSEUDO!", []>;
4031 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4032 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4033 "#ATOMSWAP6432 PSEUDO!", []>;
4036 // Segmentation support instructions.
4038 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4039 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4040 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4041 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4043 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4044 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4045 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4046 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4047 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4049 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4050 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4051 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4052 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4053 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4054 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4055 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4056 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4058 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4060 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4061 "str{w}\t{$dst}", []>, TB;
4062 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4063 "str{w}\t{$dst}", []>, TB;
4064 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4065 "ltr{w}\t{$src}", []>, TB;
4066 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4067 "ltr{w}\t{$src}", []>, TB;
4069 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4070 "push{w}\t%fs", []>, OpSize, TB;
4071 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4072 "push{l}\t%fs", []>, TB;
4073 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4074 "push{w}\t%gs", []>, OpSize, TB;
4075 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4076 "push{l}\t%gs", []>, TB;
4078 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4079 "pop{w}\t%fs", []>, OpSize, TB;
4080 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4081 "pop{l}\t%fs", []>, TB;
4082 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4083 "pop{w}\t%gs", []>, OpSize, TB;
4084 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4085 "pop{l}\t%gs", []>, TB;
4087 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4088 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4089 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4090 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4091 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4092 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4093 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4094 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4095 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4096 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4097 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4098 "les{l}\t{$src, $dst|$dst, $src}", []>;
4099 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4100 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4101 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4102 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4103 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4104 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4105 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4106 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4108 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4109 "verr\t$seg", []>, TB;
4110 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4111 "verr\t$seg", []>, TB;
4112 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4113 "verw\t$seg", []>, TB;
4114 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4115 "verw\t$seg", []>, TB;
4117 // Descriptor-table support instructions
4119 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4120 "sgdt\t$dst", []>, TB;
4121 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4122 "sidt\t$dst", []>, TB;
4123 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4124 "sldt{w}\t$dst", []>, TB;
4125 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4126 "sldt{w}\t$dst", []>, TB;
4127 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4128 "lgdt\t$src", []>, TB;
4129 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4130 "lidt\t$src", []>, TB;
4131 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4132 "lldt{w}\t$src", []>, TB;
4133 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4134 "lldt{w}\t$src", []>, TB;
4136 // String manipulation instructions
4138 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4139 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4140 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4142 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4143 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4144 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4146 // CPU flow control instructions
4148 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4149 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4151 // FPU control instructions
4153 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4155 // Flag instructions
4157 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4158 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4159 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4160 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4161 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4162 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4163 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4165 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4167 // Table lookup instructions
4169 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4171 // Specialized register support
4173 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4174 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4175 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4177 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4178 "smsw{w}\t$dst", []>, OpSize, TB;
4179 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4180 "smsw{l}\t$dst", []>, TB;
4181 // For memory operands, there is only a 16-bit form
4182 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4183 "smsw{w}\t$dst", []>, TB;
4185 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4186 "lmsw{w}\t$src", []>, TB;
4187 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4188 "lmsw{w}\t$src", []>, TB;
4190 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4192 // Cache instructions
4194 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4195 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4200 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4202 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4204 def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB;
4205 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4206 "vmclear\t$vmcs", []>, OpSize, TB;
4208 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4210 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4211 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4212 "vmptrld\t$vmcs", []>, TB;
4213 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4214 "vmptrst\t$vmcs", []>, TB;
4215 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4216 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4217 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4218 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4219 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4220 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4221 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4222 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4223 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4224 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4225 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4226 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4227 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4228 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4229 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4230 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4232 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4233 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4234 "vmxon\t{$vmxon}", []>, XD;
4236 //===----------------------------------------------------------------------===//
4237 // Non-Instruction Patterns
4238 //===----------------------------------------------------------------------===//
4240 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4241 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4242 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4243 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4244 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4245 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4246 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4248 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4249 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4250 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4251 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4252 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4253 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4254 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4255 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4256 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4257 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4259 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4260 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4261 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4262 (MOV32mi addr:$dst, texternalsym:$src)>;
4263 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4264 (MOV32mi addr:$dst, tblockaddress:$src)>;
4268 def : Pat<(X86tcret GR32:$dst, imm:$off),
4269 (TCRETURNri GR32:$dst, imm:$off)>;
4271 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4272 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4274 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4275 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4277 // Normal calls, with various flavors of addresses.
4278 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4279 (CALLpcrel32 tglobaladdr:$dst)>;
4280 def : Pat<(X86call (i32 texternalsym:$dst)),
4281 (CALLpcrel32 texternalsym:$dst)>;
4282 def : Pat<(X86call (i32 imm:$dst)),
4283 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4285 // X86 specific add which produces a flag.
4286 def : Pat<(addc GR32:$src1, GR32:$src2),
4287 (ADD32rr GR32:$src1, GR32:$src2)>;
4288 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4289 (ADD32rm GR32:$src1, addr:$src2)>;
4290 def : Pat<(addc GR32:$src1, imm:$src2),
4291 (ADD32ri GR32:$src1, imm:$src2)>;
4292 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4293 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4295 def : Pat<(subc GR32:$src1, GR32:$src2),
4296 (SUB32rr GR32:$src1, GR32:$src2)>;
4297 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4298 (SUB32rm GR32:$src1, addr:$src2)>;
4299 def : Pat<(subc GR32:$src1, imm:$src2),
4300 (SUB32ri GR32:$src1, imm:$src2)>;
4301 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4302 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4306 // TEST R,R is smaller than CMP R,0
4307 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4308 (TEST8rr GR8:$src1, GR8:$src1)>;
4309 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4310 (TEST16rr GR16:$src1, GR16:$src1)>;
4311 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4312 (TEST32rr GR32:$src1, GR32:$src1)>;
4314 // Conditional moves with folded loads with operands swapped and conditions
4316 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4317 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4318 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4319 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4320 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4321 (CMOVB16rm GR16:$src2, addr:$src1)>;
4322 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4323 (CMOVB32rm GR32:$src2, addr:$src1)>;
4324 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4325 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4326 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4327 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4328 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4329 (CMOVE16rm GR16:$src2, addr:$src1)>;
4330 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4331 (CMOVE32rm GR32:$src2, addr:$src1)>;
4332 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4333 (CMOVA16rm GR16:$src2, addr:$src1)>;
4334 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4335 (CMOVA32rm GR32:$src2, addr:$src1)>;
4336 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4337 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4338 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4339 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4340 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4341 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4342 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4343 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4344 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4345 (CMOVL16rm GR16:$src2, addr:$src1)>;
4346 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4347 (CMOVL32rm GR32:$src2, addr:$src1)>;
4348 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4349 (CMOVG16rm GR16:$src2, addr:$src1)>;
4350 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4351 (CMOVG32rm GR32:$src2, addr:$src1)>;
4352 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4353 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4354 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4355 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4356 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4357 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4358 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4359 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4360 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4361 (CMOVP16rm GR16:$src2, addr:$src1)>;
4362 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4363 (CMOVP32rm GR32:$src2, addr:$src1)>;
4364 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4365 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4366 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4367 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4368 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4369 (CMOVS16rm GR16:$src2, addr:$src1)>;
4370 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4371 (CMOVS32rm GR32:$src2, addr:$src1)>;
4372 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4373 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4374 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4375 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4376 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4377 (CMOVO16rm GR16:$src2, addr:$src1)>;
4378 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4379 (CMOVO32rm GR32:$src2, addr:$src1)>;
4381 // zextload bool -> zextload byte
4382 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4383 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4384 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4386 // extload bool -> extload byte
4387 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4388 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4389 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4390 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4391 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4392 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4394 // anyext. Define these to do an explicit zero-extend to
4395 // avoid partial-register updates.
4396 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4397 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4398 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4400 // (and (i32 load), 255) -> (zextload i8)
4401 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4402 (MOVZX32rm8 addr:$src)>;
4403 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4404 (MOVZX32rm16 addr:$src)>;
4406 //===----------------------------------------------------------------------===//
4408 //===----------------------------------------------------------------------===//
4410 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4411 // +128 doesn't, so in this special case use a sub instead of an add.
4412 def : Pat<(add GR16:$src1, 128),
4413 (SUB16ri8 GR16:$src1, -128)>;
4414 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4415 (SUB16mi8 addr:$dst, -128)>;
4416 def : Pat<(add GR32:$src1, 128),
4417 (SUB32ri8 GR32:$src1, -128)>;
4418 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4419 (SUB32mi8 addr:$dst, -128)>;
4421 // r & (2^16-1) ==> movz
4422 def : Pat<(and GR32:$src1, 0xffff),
4423 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4424 // r & (2^8-1) ==> movz
4425 def : Pat<(and GR32:$src1, 0xff),
4426 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4429 Requires<[In32BitMode]>;
4430 // r & (2^8-1) ==> movz
4431 def : Pat<(and GR16:$src1, 0xff),
4432 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4435 Requires<[In32BitMode]>;
4437 // sext_inreg patterns
4438 def : Pat<(sext_inreg GR32:$src, i16),
4439 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4440 def : Pat<(sext_inreg GR32:$src, i8),
4441 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4444 Requires<[In32BitMode]>;
4445 def : Pat<(sext_inreg GR16:$src, i8),
4446 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4449 Requires<[In32BitMode]>;
4452 def : Pat<(i16 (trunc GR32:$src)),
4453 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4454 def : Pat<(i8 (trunc GR32:$src)),
4455 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4457 Requires<[In32BitMode]>;
4458 def : Pat<(i8 (trunc GR16:$src)),
4459 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4461 Requires<[In32BitMode]>;
4463 // h-register tricks
4464 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4465 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4466 x86_subreg_8bit_hi)>,
4467 Requires<[In32BitMode]>;
4468 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4469 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4470 x86_subreg_8bit_hi)>,
4471 Requires<[In32BitMode]>;
4472 def : Pat<(srl_su GR16:$src, (i8 8)),
4475 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4476 x86_subreg_8bit_hi)),
4478 Requires<[In32BitMode]>;
4479 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4480 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4482 x86_subreg_8bit_hi))>,
4483 Requires<[In32BitMode]>;
4484 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4485 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4487 x86_subreg_8bit_hi))>,
4488 Requires<[In32BitMode]>;
4489 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4490 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4492 x86_subreg_8bit_hi))>,
4493 Requires<[In32BitMode]>;
4495 // (shl x, 1) ==> (add x, x)
4496 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4497 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4498 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4500 // (shl x (and y, 31)) ==> (shl x, y)
4501 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4502 (SHL8rCL GR8:$src1)>;
4503 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4504 (SHL16rCL GR16:$src1)>;
4505 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4506 (SHL32rCL GR32:$src1)>;
4507 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4508 (SHL8mCL addr:$dst)>;
4509 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4510 (SHL16mCL addr:$dst)>;
4511 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4512 (SHL32mCL addr:$dst)>;
4514 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4515 (SHR8rCL GR8:$src1)>;
4516 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4517 (SHR16rCL GR16:$src1)>;
4518 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4519 (SHR32rCL GR32:$src1)>;
4520 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4521 (SHR8mCL addr:$dst)>;
4522 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4523 (SHR16mCL addr:$dst)>;
4524 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4525 (SHR32mCL addr:$dst)>;
4527 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4528 (SAR8rCL GR8:$src1)>;
4529 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4530 (SAR16rCL GR16:$src1)>;
4531 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4532 (SAR32rCL GR32:$src1)>;
4533 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4534 (SAR8mCL addr:$dst)>;
4535 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4536 (SAR16mCL addr:$dst)>;
4537 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4538 (SAR32mCL addr:$dst)>;
4540 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4541 def : Pat<(or (srl GR32:$src1, CL:$amt),
4542 (shl GR32:$src2, (sub 32, CL:$amt))),
4543 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4545 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4546 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4547 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4549 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4550 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4551 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4553 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4554 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4556 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4558 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4559 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4561 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4562 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4563 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4565 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4566 def : Pat<(or (shl GR32:$src1, CL:$amt),
4567 (srl GR32:$src2, (sub 32, CL:$amt))),
4568 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4570 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4571 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4572 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4574 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4575 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4576 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4578 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4579 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4581 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4583 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4584 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4586 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4587 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4588 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4590 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4591 def : Pat<(or (srl GR16:$src1, CL:$amt),
4592 (shl GR16:$src2, (sub 16, CL:$amt))),
4593 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4595 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4596 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4597 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4599 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4600 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4601 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4603 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4604 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4606 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4608 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4609 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4611 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4612 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4613 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4615 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4616 def : Pat<(or (shl GR16:$src1, CL:$amt),
4617 (srl GR16:$src2, (sub 16, CL:$amt))),
4618 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4620 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4621 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4622 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4624 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4625 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4626 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4628 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4629 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4631 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4633 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4634 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4636 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4637 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4638 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4640 // (anyext (setcc_carry)) -> (setcc_carry)
4641 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4643 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4646 //===----------------------------------------------------------------------===//
4647 // EFLAGS-defining Patterns
4648 //===----------------------------------------------------------------------===//
4650 // Register-Register Addition with EFLAGS result
4651 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4653 (ADD8rr GR8:$src1, GR8:$src2)>;
4654 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4656 (ADD16rr GR16:$src1, GR16:$src2)>;
4657 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4659 (ADD32rr GR32:$src1, GR32:$src2)>;
4661 // Register-Memory Addition with EFLAGS result
4662 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4664 (ADD8rm GR8:$src1, addr:$src2)>;
4665 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4667 (ADD16rm GR16:$src1, addr:$src2)>;
4668 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4670 (ADD32rm GR32:$src1, addr:$src2)>;
4672 // Register-Integer Addition with EFLAGS result
4673 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4675 (ADD8ri GR8:$src1, imm:$src2)>;
4676 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4678 (ADD16ri GR16:$src1, imm:$src2)>;
4679 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4681 (ADD32ri GR32:$src1, imm:$src2)>;
4682 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4684 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4685 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4687 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4689 // Memory-Register Addition with EFLAGS result
4690 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4693 (ADD8mr addr:$dst, GR8:$src2)>;
4694 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4697 (ADD16mr addr:$dst, GR16:$src2)>;
4698 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4701 (ADD32mr addr:$dst, GR32:$src2)>;
4703 // Memory-Integer Addition with EFLAGS result
4704 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4707 (ADD8mi addr:$dst, imm:$src2)>;
4708 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4711 (ADD16mi addr:$dst, imm:$src2)>;
4712 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4715 (ADD32mi addr:$dst, imm:$src2)>;
4716 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4719 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4720 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4723 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4725 // Register-Register Subtraction with EFLAGS result
4726 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4728 (SUB8rr GR8:$src1, GR8:$src2)>;
4729 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4731 (SUB16rr GR16:$src1, GR16:$src2)>;
4732 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4734 (SUB32rr GR32:$src1, GR32:$src2)>;
4736 // Register-Memory Subtraction with EFLAGS result
4737 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4739 (SUB8rm GR8:$src1, addr:$src2)>;
4740 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4742 (SUB16rm GR16:$src1, addr:$src2)>;
4743 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4745 (SUB32rm GR32:$src1, addr:$src2)>;
4747 // Register-Integer Subtraction with EFLAGS result
4748 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4750 (SUB8ri GR8:$src1, imm:$src2)>;
4751 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4753 (SUB16ri GR16:$src1, imm:$src2)>;
4754 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4756 (SUB32ri GR32:$src1, imm:$src2)>;
4757 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4759 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4760 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4762 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4764 // Memory-Register Subtraction with EFLAGS result
4765 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4768 (SUB8mr addr:$dst, GR8:$src2)>;
4769 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4772 (SUB16mr addr:$dst, GR16:$src2)>;
4773 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4776 (SUB32mr addr:$dst, GR32:$src2)>;
4778 // Memory-Integer Subtraction with EFLAGS result
4779 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4782 (SUB8mi addr:$dst, imm:$src2)>;
4783 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4786 (SUB16mi addr:$dst, imm:$src2)>;
4787 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4790 (SUB32mi addr:$dst, imm:$src2)>;
4791 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4794 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4795 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4798 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4801 // Register-Register Signed Integer Multiply with EFLAGS result
4802 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4804 (IMUL16rr GR16:$src1, GR16:$src2)>;
4805 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4807 (IMUL32rr GR32:$src1, GR32:$src2)>;
4809 // Register-Memory Signed Integer Multiply with EFLAGS result
4810 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4812 (IMUL16rm GR16:$src1, addr:$src2)>;
4813 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4815 (IMUL32rm GR32:$src1, addr:$src2)>;
4817 // Register-Integer Signed Integer Multiply with EFLAGS result
4818 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4820 (IMUL16rri GR16:$src1, imm:$src2)>;
4821 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4823 (IMUL32rri GR32:$src1, imm:$src2)>;
4824 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4826 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4827 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4829 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4831 // Memory-Integer Signed Integer Multiply with EFLAGS result
4832 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4834 (IMUL16rmi addr:$src1, imm:$src2)>;
4835 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4837 (IMUL32rmi addr:$src1, imm:$src2)>;
4838 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4840 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4841 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4843 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4845 // Optimize multiply by 2 with EFLAGS result.
4846 let AddedComplexity = 2 in {
4847 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4849 (ADD16rr GR16:$src1, GR16:$src1)>;
4851 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4853 (ADD32rr GR32:$src1, GR32:$src1)>;
4856 // INC and DEC with EFLAGS result. Note that these do not set CF.
4857 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4859 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4862 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4864 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4868 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4869 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4870 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4872 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4873 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4874 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4875 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4877 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4879 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4880 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4881 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4883 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4884 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4885 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4886 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4888 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4890 // Register-Register Or with EFLAGS result
4891 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4893 (OR8rr GR8:$src1, GR8:$src2)>;
4894 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4896 (OR16rr GR16:$src1, GR16:$src2)>;
4897 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4899 (OR32rr GR32:$src1, GR32:$src2)>;
4901 // Register-Memory Or with EFLAGS result
4902 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4904 (OR8rm GR8:$src1, addr:$src2)>;
4905 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4907 (OR16rm GR16:$src1, addr:$src2)>;
4908 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4910 (OR32rm GR32:$src1, addr:$src2)>;
4912 // Register-Integer Or with EFLAGS result
4913 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4915 (OR8ri GR8:$src1, imm:$src2)>;
4916 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4918 (OR16ri GR16:$src1, imm:$src2)>;
4919 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4921 (OR32ri GR32:$src1, imm:$src2)>;
4922 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4924 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4925 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4927 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4929 // Memory-Register Or with EFLAGS result
4930 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4933 (OR8mr addr:$dst, GR8:$src2)>;
4934 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4937 (OR16mr addr:$dst, GR16:$src2)>;
4938 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4941 (OR32mr addr:$dst, GR32:$src2)>;
4943 // Memory-Integer Or with EFLAGS result
4944 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4947 (OR8mi addr:$dst, imm:$src2)>;
4948 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4951 (OR16mi addr:$dst, imm:$src2)>;
4952 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4955 (OR32mi addr:$dst, imm:$src2)>;
4956 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4959 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4960 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4963 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
4965 // Register-Register XOr with EFLAGS result
4966 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
4968 (XOR8rr GR8:$src1, GR8:$src2)>;
4969 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
4971 (XOR16rr GR16:$src1, GR16:$src2)>;
4972 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
4974 (XOR32rr GR32:$src1, GR32:$src2)>;
4976 // Register-Memory XOr with EFLAGS result
4977 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
4979 (XOR8rm GR8:$src1, addr:$src2)>;
4980 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
4982 (XOR16rm GR16:$src1, addr:$src2)>;
4983 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
4985 (XOR32rm GR32:$src1, addr:$src2)>;
4987 // Register-Integer XOr with EFLAGS result
4988 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
4990 (XOR8ri GR8:$src1, imm:$src2)>;
4991 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
4993 (XOR16ri GR16:$src1, imm:$src2)>;
4994 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
4996 (XOR32ri GR32:$src1, imm:$src2)>;
4997 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
4999 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5000 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5002 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5004 // Memory-Register XOr with EFLAGS result
5005 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5008 (XOR8mr addr:$dst, GR8:$src2)>;
5009 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5012 (XOR16mr addr:$dst, GR16:$src2)>;
5013 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5016 (XOR32mr addr:$dst, GR32:$src2)>;
5018 // Memory-Integer XOr with EFLAGS result
5019 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5022 (XOR8mi addr:$dst, imm:$src2)>;
5023 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5026 (XOR16mi addr:$dst, imm:$src2)>;
5027 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5030 (XOR32mi addr:$dst, imm:$src2)>;
5031 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5034 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5035 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5038 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5040 // Register-Register And with EFLAGS result
5041 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5043 (AND8rr GR8:$src1, GR8:$src2)>;
5044 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5046 (AND16rr GR16:$src1, GR16:$src2)>;
5047 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5049 (AND32rr GR32:$src1, GR32:$src2)>;
5051 // Register-Memory And with EFLAGS result
5052 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5054 (AND8rm GR8:$src1, addr:$src2)>;
5055 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5057 (AND16rm GR16:$src1, addr:$src2)>;
5058 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5060 (AND32rm GR32:$src1, addr:$src2)>;
5062 // Register-Integer And with EFLAGS result
5063 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5065 (AND8ri GR8:$src1, imm:$src2)>;
5066 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5068 (AND16ri GR16:$src1, imm:$src2)>;
5069 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5071 (AND32ri GR32:$src1, imm:$src2)>;
5072 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5074 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5075 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5077 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5079 // Memory-Register And with EFLAGS result
5080 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5083 (AND8mr addr:$dst, GR8:$src2)>;
5084 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5087 (AND16mr addr:$dst, GR16:$src2)>;
5088 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5091 (AND32mr addr:$dst, GR32:$src2)>;
5093 // Memory-Integer And with EFLAGS result
5094 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5097 (AND8mi addr:$dst, imm:$src2)>;
5098 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5101 (AND16mi addr:$dst, imm:$src2)>;
5102 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5105 (AND32mi addr:$dst, imm:$src2)>;
5106 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5109 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5110 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5113 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5115 // -disable-16bit support.
5116 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5117 (MOV16mi addr:$dst, imm:$src)>;
5118 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5119 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5120 def : Pat<(i32 (sextloadi16 addr:$dst)),
5121 (MOVSX32rm16 addr:$dst)>;
5122 def : Pat<(i32 (zextloadi16 addr:$dst)),
5123 (MOVZX32rm16 addr:$dst)>;
5124 def : Pat<(i32 (extloadi16 addr:$dst)),
5125 (MOVZX32rm16 addr:$dst)>;
5127 //===----------------------------------------------------------------------===//
5128 // Floating Point Stack Support
5129 //===----------------------------------------------------------------------===//
5131 include "X86InstrFPStack.td"
5133 //===----------------------------------------------------------------------===//
5135 //===----------------------------------------------------------------------===//
5137 include "X86Instr64bit.td"
5139 //===----------------------------------------------------------------------===//
5140 // XMM Floating point support (requires SSE / SSE2)
5141 //===----------------------------------------------------------------------===//
5143 include "X86InstrSSE.td"
5145 //===----------------------------------------------------------------------===//
5146 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5147 //===----------------------------------------------------------------------===//
5149 include "X86InstrMMX.td"