1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
70 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
72 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
73 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
74 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
76 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
77 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
80 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
82 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
86 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
92 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
94 def SDTX86Void : SDTypeProfile<0, 0, []>;
96 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
98 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
106 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
108 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
110 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
112 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
114 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
116 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
118 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
120 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
124 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
125 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
126 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
127 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
129 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
130 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
132 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
133 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
135 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
136 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
138 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
140 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
141 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
142 SDNPMayLoad, SDNPMemOperand]>;
143 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
144 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
145 SDNPMayLoad, SDNPMemOperand]>;
146 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
147 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
148 SDNPMayLoad, SDNPMemOperand]>;
150 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
151 [SDNPHasChain, SDNPMayStore,
152 SDNPMayLoad, SDNPMemOperand]>;
153 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
154 [SDNPHasChain, SDNPMayStore,
155 SDNPMayLoad, SDNPMemOperand]>;
156 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
157 [SDNPHasChain, SDNPMayStore,
158 SDNPMayLoad, SDNPMemOperand]>;
159 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
160 [SDNPHasChain, SDNPMayStore,
161 SDNPMayLoad, SDNPMemOperand]>;
162 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
163 [SDNPHasChain, SDNPMayStore,
164 SDNPMayLoad, SDNPMemOperand]>;
165 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
166 [SDNPHasChain, SDNPMayStore,
167 SDNPMayLoad, SDNPMemOperand]>;
168 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
169 [SDNPHasChain, SDNPMayStore,
170 SDNPMayLoad, SDNPMemOperand]>;
171 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
174 def X86vastart_save_xmm_regs :
175 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
176 SDT_X86VASTART_SAVE_XMM_REGS,
177 [SDNPHasChain, SDNPVariadic]>;
179 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
180 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
182 def X86callseq_start :
183 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
184 [SDNPHasChain, SDNPOutGlue]>;
186 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
187 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
189 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
190 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
193 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
194 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
195 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
196 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
199 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
200 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
202 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
203 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
205 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
206 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
208 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
209 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
211 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
214 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
215 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
217 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
219 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
220 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
222 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
224 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
225 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
227 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
228 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
229 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
231 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
233 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
235 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
237 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
238 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
239 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
241 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
243 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
244 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
246 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
249 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
250 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
252 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
253 [SDNPHasChain, SDNPOutGlue]>;
255 //===----------------------------------------------------------------------===//
256 // X86 Operand Definitions.
259 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
260 // the index operand of an address, to conform to x86 encoding restrictions.
261 def ptr_rc_nosp : PointerLikeRegClass<1>;
263 // *mem - Operand definitions for the funky X86 addressing mode operands.
265 def X86MemAsmOperand : AsmOperandClass {
266 let Name = "Mem"; let PredicateMethod = "isMem";
268 def X86Mem8AsmOperand : AsmOperandClass {
269 let Name = "Mem8"; let PredicateMethod = "isMem8";
271 def X86Mem16AsmOperand : AsmOperandClass {
272 let Name = "Mem16"; let PredicateMethod = "isMem16";
274 def X86Mem32AsmOperand : AsmOperandClass {
275 let Name = "Mem32"; let PredicateMethod = "isMem32";
277 def X86Mem64AsmOperand : AsmOperandClass {
278 let Name = "Mem64"; let PredicateMethod = "isMem64";
280 def X86Mem80AsmOperand : AsmOperandClass {
281 let Name = "Mem80"; let PredicateMethod = "isMem80";
283 def X86Mem128AsmOperand : AsmOperandClass {
284 let Name = "Mem128"; let PredicateMethod = "isMem128";
286 def X86Mem256AsmOperand : AsmOperandClass {
287 let Name = "Mem256"; let PredicateMethod = "isMem256";
290 def X86AbsMemAsmOperand : AsmOperandClass {
292 let SuperClasses = [X86MemAsmOperand];
294 class X86MemOperand<string printMethod> : Operand<iPTR> {
295 let PrintMethod = printMethod;
296 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
297 let ParserMatchClass = X86MemAsmOperand;
300 let OperandType = "OPERAND_MEMORY" in {
301 def opaque32mem : X86MemOperand<"printopaquemem">;
302 def opaque48mem : X86MemOperand<"printopaquemem">;
303 def opaque80mem : X86MemOperand<"printopaquemem">;
304 def opaque512mem : X86MemOperand<"printopaquemem">;
306 def i8mem : X86MemOperand<"printi8mem"> {
307 let ParserMatchClass = X86Mem8AsmOperand; }
308 def i16mem : X86MemOperand<"printi16mem"> {
309 let ParserMatchClass = X86Mem16AsmOperand; }
310 def i32mem : X86MemOperand<"printi32mem"> {
311 let ParserMatchClass = X86Mem32AsmOperand; }
312 def i64mem : X86MemOperand<"printi64mem"> {
313 let ParserMatchClass = X86Mem64AsmOperand; }
314 def i128mem : X86MemOperand<"printi128mem"> {
315 let ParserMatchClass = X86Mem128AsmOperand; }
316 def i256mem : X86MemOperand<"printi256mem"> {
317 let ParserMatchClass = X86Mem256AsmOperand; }
318 def f32mem : X86MemOperand<"printf32mem"> {
319 let ParserMatchClass = X86Mem32AsmOperand; }
320 def f64mem : X86MemOperand<"printf64mem"> {
321 let ParserMatchClass = X86Mem64AsmOperand; }
322 def f80mem : X86MemOperand<"printf80mem"> {
323 let ParserMatchClass = X86Mem80AsmOperand; }
324 def f128mem : X86MemOperand<"printf128mem"> {
325 let ParserMatchClass = X86Mem128AsmOperand; }
326 def f256mem : X86MemOperand<"printf256mem">{
327 let ParserMatchClass = X86Mem256AsmOperand; }
330 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
331 // plain GR64, so that it doesn't potentially require a REX prefix.
332 def i8mem_NOREX : Operand<i64> {
333 let PrintMethod = "printi8mem";
334 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
335 let ParserMatchClass = X86Mem8AsmOperand;
336 let OperandType = "OPERAND_MEMORY";
339 // GPRs available for tailcall.
340 // It represents GR32_TC, GR64_TC or GR64_TCW64.
341 def ptr_rc_tailcall : PointerLikeRegClass<2>;
343 // Special i32mem for addresses of load folding tail calls. These are not
344 // allowed to use callee-saved registers since they must be scheduled
345 // after callee-saved register are popped.
346 def i32mem_TC : Operand<i32> {
347 let PrintMethod = "printi32mem";
348 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
350 let ParserMatchClass = X86Mem32AsmOperand;
351 let OperandType = "OPERAND_MEMORY";
354 // Special i64mem for addresses of load folding tail calls. These are not
355 // allowed to use callee-saved registers since they must be scheduled
356 // after callee-saved register are popped.
357 def i64mem_TC : Operand<i64> {
358 let PrintMethod = "printi64mem";
359 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
360 ptr_rc_tailcall, i32imm, i8imm);
361 let ParserMatchClass = X86Mem64AsmOperand;
362 let OperandType = "OPERAND_MEMORY";
365 let OperandType = "OPERAND_PCREL",
366 ParserMatchClass = X86AbsMemAsmOperand,
367 PrintMethod = "print_pcrel_imm" in {
368 def i32imm_pcrel : Operand<i32>;
369 def i16imm_pcrel : Operand<i16>;
371 def offset8 : Operand<i64>;
372 def offset16 : Operand<i64>;
373 def offset32 : Operand<i64>;
374 def offset64 : Operand<i64>;
376 // Branch targets have OtherVT type and print as pc-relative values.
377 def brtarget : Operand<OtherVT>;
378 def brtarget8 : Operand<OtherVT>;
382 def SSECC : Operand<i8> {
383 let PrintMethod = "printSSECC";
384 let OperandType = "OPERAND_IMMEDIATE";
387 def AVXCC : Operand<i8> {
388 let PrintMethod = "printSSECC";
389 let OperandType = "OPERAND_IMMEDIATE";
392 class ImmSExtAsmOperandClass : AsmOperandClass {
393 let SuperClasses = [ImmAsmOperand];
394 let RenderMethod = "addImmOperands";
397 class ImmZExtAsmOperandClass : AsmOperandClass {
398 let SuperClasses = [ImmAsmOperand];
399 let RenderMethod = "addImmOperands";
402 // Sign-extended immediate classes. We don't need to define the full lattice
403 // here because there is no instruction with an ambiguity between ImmSExti64i32
406 // The strange ranges come from the fact that the assembler always works with
407 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
408 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
411 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
412 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
413 let Name = "ImmSExti64i32";
416 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
417 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
418 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
419 let Name = "ImmSExti16i8";
420 let SuperClasses = [ImmSExti64i32AsmOperand];
423 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
424 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
425 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
426 let Name = "ImmSExti32i8";
430 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
431 let Name = "ImmZExtu32u8";
436 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
437 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
438 let Name = "ImmSExti64i8";
439 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
440 ImmSExti64i32AsmOperand];
443 // A couple of more descriptive operand definitions.
444 // 16-bits but only 8 bits are significant.
445 def i16i8imm : Operand<i16> {
446 let ParserMatchClass = ImmSExti16i8AsmOperand;
447 let OperandType = "OPERAND_IMMEDIATE";
449 // 32-bits but only 8 bits are significant.
450 def i32i8imm : Operand<i32> {
451 let ParserMatchClass = ImmSExti32i8AsmOperand;
452 let OperandType = "OPERAND_IMMEDIATE";
454 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
455 def u32u8imm : Operand<i32> {
456 let ParserMatchClass = ImmZExtu32u8AsmOperand;
457 let OperandType = "OPERAND_IMMEDIATE";
460 // 64-bits but only 32 bits are significant.
461 def i64i32imm : Operand<i64> {
462 let ParserMatchClass = ImmSExti64i32AsmOperand;
463 let OperandType = "OPERAND_IMMEDIATE";
466 // 64-bits but only 32 bits are significant, and those bits are treated as being
468 def i64i32imm_pcrel : Operand<i64> {
469 let PrintMethod = "print_pcrel_imm";
470 let ParserMatchClass = X86AbsMemAsmOperand;
471 let OperandType = "OPERAND_PCREL";
474 // 64-bits but only 8 bits are significant.
475 def i64i8imm : Operand<i64> {
476 let ParserMatchClass = ImmSExti64i8AsmOperand;
477 let OperandType = "OPERAND_IMMEDIATE";
480 def lea64_32mem : Operand<i32> {
481 let PrintMethod = "printi32mem";
482 let AsmOperandLowerMethod = "lower_lea64_32mem";
483 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
484 let ParserMatchClass = X86MemAsmOperand;
488 //===----------------------------------------------------------------------===//
489 // X86 Complex Pattern Definitions.
492 // Define X86 specific addressing mode.
493 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
494 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
495 [add, sub, mul, X86mul_imm, shl, or, frameindex],
497 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
498 [tglobaltlsaddr], []>;
500 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
501 [tglobaltlsaddr], []>;
503 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
504 [add, sub, mul, X86mul_imm, shl, or, frameindex,
507 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
508 [tglobaltlsaddr], []>;
510 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
511 [tglobaltlsaddr], []>;
513 //===----------------------------------------------------------------------===//
514 // X86 Instruction Predicate Definitions.
515 def HasCMov : Predicate<"Subtarget->hasCMov()">;
516 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
518 def HasMMX : Predicate<"Subtarget->hasMMX()">;
519 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
520 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
521 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
522 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
523 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
524 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
525 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
526 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
527 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
528 def HasAVX : Predicate<"Subtarget->hasAVX()">;
529 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
531 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
532 def HasAES : Predicate<"Subtarget->hasAES()">;
533 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
534 def HasFMA : Predicate<"Subtarget->hasFMA()">;
535 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
536 def HasXOP : Predicate<"Subtarget->hasXOP()">;
537 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
538 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
539 def HasF16C : Predicate<"Subtarget->hasF16C()">;
540 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
541 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
542 def HasBMI : Predicate<"Subtarget->hasBMI()">;
543 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
544 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
545 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
546 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
547 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
548 AssemblerPredicate<"!Mode64Bit">;
549 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
550 AssemblerPredicate<"Mode64Bit">;
551 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
552 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
553 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
554 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
555 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
556 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
557 "TM.getCodeModel() != CodeModel::Kernel">;
558 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
559 "TM.getCodeModel() == CodeModel::Kernel">;
560 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
561 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
562 def OptForSize : Predicate<"OptForSize">;
563 def OptForSpeed : Predicate<"!OptForSize">;
564 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
565 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
567 //===----------------------------------------------------------------------===//
568 // X86 Instruction Format Definitions.
571 include "X86InstrFormats.td"
573 //===----------------------------------------------------------------------===//
574 // Pattern fragments.
577 // X86 specific condition code. These correspond to CondCode in
578 // X86InstrInfo.h. They must be kept in synch.
579 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
580 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
581 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
582 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
583 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
584 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
585 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
586 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
587 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
588 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
589 def X86_COND_NO : PatLeaf<(i8 10)>;
590 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
591 def X86_COND_NS : PatLeaf<(i8 12)>;
592 def X86_COND_O : PatLeaf<(i8 13)>;
593 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
594 def X86_COND_S : PatLeaf<(i8 15)>;
596 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
597 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
598 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
599 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
602 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
605 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
607 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
609 def i64immZExt32SExt8 : ImmLeaf<i64, [{
610 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
613 // Helper fragments for loads.
614 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
615 // known to be 32-bit aligned or better. Ditto for i8 to i16.
616 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
617 LoadSDNode *LD = cast<LoadSDNode>(N);
618 ISD::LoadExtType ExtType = LD->getExtensionType();
619 if (ExtType == ISD::NON_EXTLOAD)
621 if (ExtType == ISD::EXTLOAD)
622 return LD->getAlignment() >= 2 && !LD->isVolatile();
626 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
627 LoadSDNode *LD = cast<LoadSDNode>(N);
628 ISD::LoadExtType ExtType = LD->getExtensionType();
629 if (ExtType == ISD::EXTLOAD)
630 return LD->getAlignment() >= 2 && !LD->isVolatile();
634 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
635 LoadSDNode *LD = cast<LoadSDNode>(N);
636 ISD::LoadExtType ExtType = LD->getExtensionType();
637 if (ExtType == ISD::NON_EXTLOAD)
639 if (ExtType == ISD::EXTLOAD)
640 return LD->getAlignment() >= 4 && !LD->isVolatile();
644 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
645 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
646 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
647 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
648 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
650 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
651 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
652 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
653 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
654 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
655 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
657 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
658 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
659 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
660 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
661 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
662 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
663 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
664 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
665 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
666 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
668 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
669 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
670 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
671 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
672 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
673 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
674 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
675 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
676 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
677 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
680 // An 'and' node with a single use.
681 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
682 return N->hasOneUse();
684 // An 'srl' node with a single use.
685 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
686 return N->hasOneUse();
688 // An 'trunc' node with a single use.
689 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
690 return N->hasOneUse();
693 //===----------------------------------------------------------------------===//
698 let neverHasSideEffects = 1 in {
699 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
700 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
701 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
702 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
703 "nop{l}\t$zero", [], IIC_NOP>, TB;
707 // Constructing a stack frame.
708 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
709 "enter\t$len, $lvl", [], IIC_ENTER>;
711 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
712 def LEAVE : I<0xC9, RawFrm,
713 (outs), (ins), "leave", [], IIC_LEAVE>,
714 Requires<[In32BitMode]>;
716 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
717 def LEAVE64 : I<0xC9, RawFrm,
718 (outs), (ins), "leave", [], IIC_LEAVE>,
719 Requires<[In64BitMode]>;
721 //===----------------------------------------------------------------------===//
722 // Miscellaneous Instructions.
725 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
727 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
728 IIC_POP_REG16>, OpSize;
729 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
731 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
732 IIC_POP_REG>, OpSize;
733 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
734 IIC_POP_MEM>, OpSize;
735 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
737 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
740 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
741 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
742 Requires<[In32BitMode]>;
745 let mayStore = 1 in {
746 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
747 IIC_PUSH_REG>, OpSize;
748 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
750 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
751 IIC_PUSH_REG>, OpSize;
752 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
755 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
757 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
760 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
761 "push{l}\t$imm", [], IIC_PUSH_IMM>;
762 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
763 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
764 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
765 "push{l}\t$imm", [], IIC_PUSH_IMM>;
767 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
769 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
770 Requires<[In32BitMode]>;
775 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
777 def POP64r : I<0x58, AddRegFrm,
778 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
779 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
781 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
784 let mayStore = 1 in {
785 def PUSH64r : I<0x50, AddRegFrm,
786 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
787 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
789 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
794 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
795 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
796 "push{q}\t$imm", [], IIC_PUSH_IMM>;
797 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
798 "push{q}\t$imm", [], IIC_PUSH_IMM>;
799 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
800 "push{q}\t$imm", [], IIC_PUSH_IMM>;
803 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
804 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
805 Requires<[In64BitMode]>;
806 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
807 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
808 Requires<[In64BitMode]>;
812 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
813 mayLoad=1, neverHasSideEffects=1 in {
814 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
815 Requires<[In32BitMode]>;
817 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
818 mayStore=1, neverHasSideEffects=1 in {
819 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
820 Requires<[In32BitMode]>;
823 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
824 def BSWAP32r : I<0xC8, AddRegFrm,
825 (outs GR32:$dst), (ins GR32:$src),
827 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
829 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
831 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
832 } // Constraints = "$src = $dst"
834 // Bit scan instructions.
835 let Defs = [EFLAGS] in {
836 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
837 "bsf{w}\t{$src, $dst|$dst, $src}",
838 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
839 IIC_BSF>, TB, OpSize;
840 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
841 "bsf{w}\t{$src, $dst|$dst, $src}",
842 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
843 IIC_BSF>, TB, OpSize;
844 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
845 "bsf{l}\t{$src, $dst|$dst, $src}",
846 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
847 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
848 "bsf{l}\t{$src, $dst|$dst, $src}",
849 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
851 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
852 "bsf{q}\t{$src, $dst|$dst, $src}",
853 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
855 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
856 "bsf{q}\t{$src, $dst|$dst, $src}",
857 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
860 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
861 "bsr{w}\t{$src, $dst|$dst, $src}",
862 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
864 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
865 "bsr{w}\t{$src, $dst|$dst, $src}",
866 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
869 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
870 "bsr{l}\t{$src, $dst|$dst, $src}",
871 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
872 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
873 "bsr{l}\t{$src, $dst|$dst, $src}",
874 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
876 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
877 "bsr{q}\t{$src, $dst|$dst, $src}",
878 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
879 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
880 "bsr{q}\t{$src, $dst|$dst, $src}",
881 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
886 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
887 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
888 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
889 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
890 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
891 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
894 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
895 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
896 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
897 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
898 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
899 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
900 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
901 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
902 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
904 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
905 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
906 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
907 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
909 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
910 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
911 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
912 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
915 //===----------------------------------------------------------------------===//
916 // Move Instructions.
919 let neverHasSideEffects = 1 in {
920 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
921 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
922 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
923 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
924 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
925 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
926 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
927 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
929 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
930 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
931 "mov{b}\t{$src, $dst|$dst, $src}",
932 [(set GR8:$dst, imm:$src)], IIC_MOV>;
933 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
934 "mov{w}\t{$src, $dst|$dst, $src}",
935 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
936 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
937 "mov{l}\t{$src, $dst|$dst, $src}",
938 [(set GR32:$dst, imm:$src)], IIC_MOV>;
939 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
940 "movabs{q}\t{$src, $dst|$dst, $src}",
941 [(set GR64:$dst, imm:$src)], IIC_MOV>;
942 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
943 "mov{q}\t{$src, $dst|$dst, $src}",
944 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
947 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
948 "mov{b}\t{$src, $dst|$dst, $src}",
949 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
950 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
951 "mov{w}\t{$src, $dst|$dst, $src}",
952 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
953 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
954 "mov{l}\t{$src, $dst|$dst, $src}",
955 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
956 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
957 "mov{q}\t{$src, $dst|$dst, $src}",
958 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
960 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
961 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
962 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
963 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
964 Requires<[In32BitMode]>;
965 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
966 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
967 Requires<[In32BitMode]>;
968 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
969 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
970 Requires<[In32BitMode]>;
971 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
972 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
973 Requires<[In32BitMode]>;
974 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
975 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
976 Requires<[In32BitMode]>;
977 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
978 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
979 Requires<[In32BitMode]>;
981 // FIXME: These definitions are utterly broken
982 // Just leave them commented out for now because they're useless outside
983 // of the large code model, and most compilers won't generate the instructions
986 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
987 "mov{q}\t{$src, %rax|RAX, $src}", []>;
988 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
989 "mov{q}\t{$src, %rax|RAX, $src}", []>;
990 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
991 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
992 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
993 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
997 let isCodeGenOnly = 1 in {
998 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
999 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1000 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1001 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1002 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1003 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1004 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1005 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1008 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1009 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1010 "mov{b}\t{$src, $dst|$dst, $src}",
1011 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1012 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}",
1014 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1015 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1016 "mov{l}\t{$src, $dst|$dst, $src}",
1017 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1018 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1019 "mov{q}\t{$src, $dst|$dst, $src}",
1020 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1023 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1024 "mov{b}\t{$src, $dst|$dst, $src}",
1025 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1026 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1027 "mov{w}\t{$src, $dst|$dst, $src}",
1028 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1029 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1030 "mov{l}\t{$src, $dst|$dst, $src}",
1031 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1032 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1033 "mov{q}\t{$src, $dst|$dst, $src}",
1034 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1036 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1037 // that they can be used for copying and storing h registers, which can't be
1038 // encoded when a REX prefix is present.
1039 let isCodeGenOnly = 1 in {
1040 let neverHasSideEffects = 1 in
1041 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1042 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1043 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
1045 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1046 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1047 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1049 let mayLoad = 1, neverHasSideEffects = 1,
1050 canFoldAsLoad = 1, isReMaterializable = 1 in
1051 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1052 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1053 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1058 // Condition code ops, incl. set if equal/not equal/...
1059 let Defs = [EFLAGS], Uses = [AH] in
1060 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1061 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1062 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1063 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1064 IIC_AHF>; // AH = flags
1067 //===----------------------------------------------------------------------===//
1068 // Bit tests instructions: BT, BTS, BTR, BTC.
1070 let Defs = [EFLAGS] in {
1071 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1072 "bt{w}\t{$src2, $src1|$src1, $src2}",
1073 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1075 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1076 "bt{l}\t{$src2, $src1|$src1, $src2}",
1077 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1078 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1079 "bt{q}\t{$src2, $src1|$src1, $src2}",
1080 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1082 // Unlike with the register+register form, the memory+register form of the
1083 // bt instruction does not ignore the high bits of the index. From ISel's
1084 // perspective, this is pretty bizarre. Make these instructions disassembly
1087 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1088 "bt{w}\t{$src2, $src1|$src1, $src2}",
1089 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1090 // (implicit EFLAGS)]
1092 >, OpSize, TB, Requires<[FastBTMem]>;
1093 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1094 "bt{l}\t{$src2, $src1|$src1, $src2}",
1095 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1096 // (implicit EFLAGS)]
1098 >, TB, Requires<[FastBTMem]>;
1099 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1100 "bt{q}\t{$src2, $src1|$src1, $src2}",
1101 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1102 // (implicit EFLAGS)]
1106 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1107 "bt{w}\t{$src2, $src1|$src1, $src2}",
1108 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1109 IIC_BT_RI>, OpSize, TB;
1110 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1111 "bt{l}\t{$src2, $src1|$src1, $src2}",
1112 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1114 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1115 "bt{q}\t{$src2, $src1|$src1, $src2}",
1116 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1119 // Note that these instructions don't need FastBTMem because that
1120 // only applies when the other operand is in a register. When it's
1121 // an immediate, bt is still fast.
1122 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1123 "bt{w}\t{$src2, $src1|$src1, $src2}",
1124 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1125 ], IIC_BT_MI>, OpSize, TB;
1126 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1127 "bt{l}\t{$src2, $src1|$src1, $src2}",
1128 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1130 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1131 "bt{q}\t{$src2, $src1|$src1, $src2}",
1132 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1133 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1136 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1137 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1139 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1140 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1141 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1142 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1143 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1144 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1146 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1147 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1148 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1149 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1150 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1151 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1153 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1154 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1155 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1156 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1157 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1158 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1160 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1161 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1162 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1163 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1165 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1166 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1168 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1169 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1170 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1171 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1172 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1173 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1175 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1176 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1177 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1178 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1179 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1180 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1182 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1183 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1184 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1185 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1186 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1187 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1189 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1190 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1191 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1192 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1194 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1195 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1197 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1198 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1199 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1200 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1201 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1202 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1204 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1205 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1206 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1207 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1208 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1209 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1211 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1212 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1213 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1214 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1215 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1216 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1218 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1219 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1220 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1221 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1222 } // Defs = [EFLAGS]
1225 //===----------------------------------------------------------------------===//
1230 // Atomic swap. These are just normal xchg instructions. But since a memory
1231 // operand is referenced, the atomicity is ensured.
1232 let Constraints = "$val = $dst" in {
1233 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1234 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1235 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))],
1237 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1238 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1239 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))],
1242 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1243 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1244 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))],
1246 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1247 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1248 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))],
1251 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1252 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1253 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1254 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1255 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1256 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1257 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1258 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1261 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1262 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1263 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1264 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1265 Requires<[In32BitMode]>;
1266 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1267 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1268 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1269 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1270 Requires<[In64BitMode]>;
1271 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1272 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1276 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1277 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1278 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1279 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1281 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1282 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1283 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1284 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1286 let mayLoad = 1, mayStore = 1 in {
1287 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1288 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1289 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1290 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1292 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1293 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1294 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1295 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1299 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1300 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1301 IIC_CMPXCHG_REG8>, TB;
1302 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1303 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1304 IIC_CMPXCHG_REG>, TB, OpSize;
1305 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1306 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1307 IIC_CMPXCHG_REG>, TB;
1308 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1309 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1310 IIC_CMPXCHG_REG>, TB;
1312 let mayLoad = 1, mayStore = 1 in {
1313 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1314 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1315 IIC_CMPXCHG_MEM8>, TB;
1316 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1317 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1318 IIC_CMPXCHG_MEM>, TB, OpSize;
1319 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1320 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1321 IIC_CMPXCHG_MEM>, TB;
1322 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1323 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1324 IIC_CMPXCHG_MEM>, TB;
1327 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1328 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1329 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1331 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1332 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1333 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1334 TB, Requires<[HasCmpxchg16b]>;
1338 // Lock instruction prefix
1339 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1341 // Rex64 instruction prefix
1342 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1344 // Data16 instruction prefix
1345 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1347 // Repeat string operation instruction prefixes
1348 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1349 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1350 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1351 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1352 // Repeat while not equal (used with CMPS and SCAS)
1353 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1357 // String manipulation instructions
1358 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1359 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1360 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1361 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1363 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1364 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1365 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1368 // Flag instructions
1369 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1370 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1371 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1372 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1373 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1374 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1375 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1377 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1379 // Table lookup instructions
1380 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
1382 // ASCII Adjust After Addition
1383 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1384 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1385 Requires<[In32BitMode]>;
1387 // ASCII Adjust AX Before Division
1388 // sets AL, AH and EFLAGS and uses AL and AH
1389 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1390 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1392 // ASCII Adjust AX After Multiply
1393 // sets AL, AH and EFLAGS and uses AL
1394 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1395 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1397 // ASCII Adjust AL After Subtraction - sets
1398 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1399 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1400 Requires<[In32BitMode]>;
1402 // Decimal Adjust AL after Addition
1403 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1404 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1405 Requires<[In32BitMode]>;
1407 // Decimal Adjust AL after Subtraction
1408 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1409 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1410 Requires<[In32BitMode]>;
1412 // Check Array Index Against Bounds
1413 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1414 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1415 Requires<[In32BitMode]>;
1416 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1417 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1418 Requires<[In32BitMode]>;
1420 // Adjust RPL Field of Segment Selector
1421 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1422 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1423 Requires<[In32BitMode]>;
1424 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1425 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1426 Requires<[In32BitMode]>;
1428 //===----------------------------------------------------------------------===//
1429 // MOVBE Instructions
1431 let Predicates = [HasMOVBE] in {
1432 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1433 "movbe{w}\t{$src, $dst|$dst, $src}",
1434 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1436 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1437 "movbe{l}\t{$src, $dst|$dst, $src}",
1438 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1440 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1441 "movbe{q}\t{$src, $dst|$dst, $src}",
1442 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1444 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1445 "movbe{w}\t{$src, $dst|$dst, $src}",
1446 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1448 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1449 "movbe{l}\t{$src, $dst|$dst, $src}",
1450 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1452 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1453 "movbe{q}\t{$src, $dst|$dst, $src}",
1454 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1458 //===----------------------------------------------------------------------===//
1459 // RDRAND Instruction
1461 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1462 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1463 "rdrand{w}\t$dst", []>, OpSize, TB;
1464 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1465 "rdrand{l}\t$dst", []>, TB;
1466 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1467 "rdrand{q}\t$dst", []>, TB;
1470 //===----------------------------------------------------------------------===//
1471 // LZCNT Instruction
1473 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1474 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1475 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1476 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1478 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1479 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1480 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1481 (implicit EFLAGS)]>, XS, OpSize;
1483 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1484 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1485 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1486 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1487 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1488 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1489 (implicit EFLAGS)]>, XS;
1491 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1492 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1493 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1495 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1496 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1497 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1498 (implicit EFLAGS)]>, XS;
1501 //===----------------------------------------------------------------------===//
1504 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1505 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1506 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1507 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1509 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1510 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1511 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1512 (implicit EFLAGS)]>, XS, OpSize;
1514 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1515 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1516 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1517 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1518 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1519 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1520 (implicit EFLAGS)]>, XS;
1522 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1523 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1524 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1526 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1527 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1528 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1529 (implicit EFLAGS)]>, XS;
1532 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1533 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1535 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1536 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1537 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1538 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1539 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1540 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1544 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1545 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1546 X86blsr_flag, loadi32>;
1547 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1548 X86blsr_flag, loadi64>, VEX_W;
1549 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1550 X86blsmsk_flag, loadi32>;
1551 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1552 X86blsmsk_flag, loadi64>, VEX_W;
1553 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1554 X86blsi_flag, loadi32>;
1555 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1556 X86blsi_flag, loadi64>, VEX_W;
1559 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1560 X86MemOperand x86memop, Intrinsic Int,
1562 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1563 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1564 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1566 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1567 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1568 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1569 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1572 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1573 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1574 int_x86_bmi_bextr_32, loadi32>;
1575 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1576 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1579 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1580 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1581 int_x86_bmi_bzhi_32, loadi32>;
1582 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1583 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1586 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1587 X86MemOperand x86memop, Intrinsic Int,
1589 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1590 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1591 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1593 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1594 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1595 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1598 let Predicates = [HasBMI2] in {
1599 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1600 int_x86_bmi_pdep_32, loadi32>, T8XD;
1601 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1602 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1603 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1604 int_x86_bmi_pext_32, loadi32>, T8XS;
1605 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1606 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1609 //===----------------------------------------------------------------------===//
1611 //===----------------------------------------------------------------------===//
1613 include "X86InstrArithmetic.td"
1614 include "X86InstrCMovSetCC.td"
1615 include "X86InstrExtension.td"
1616 include "X86InstrControl.td"
1617 include "X86InstrShiftRotate.td"
1619 // X87 Floating Point Stack.
1620 include "X86InstrFPStack.td"
1622 // SIMD support (SSE, MMX and AVX)
1623 include "X86InstrFragmentsSIMD.td"
1625 // FMA - Fused Multiply-Add support (requires FMA)
1626 include "X86InstrFMA.td"
1629 include "X86InstrXOP.td"
1631 // SSE, MMX and 3DNow! vector support.
1632 include "X86InstrSSE.td"
1633 include "X86InstrMMX.td"
1634 include "X86Instr3DNow.td"
1636 include "X86InstrVMX.td"
1637 include "X86InstrSVM.td"
1639 // System instructions.
1640 include "X86InstrSystem.td"
1642 // Compiler Pseudo Instructions and Pat Patterns
1643 include "X86InstrCompiler.td"
1645 //===----------------------------------------------------------------------===//
1646 // Assembler Mnemonic Aliases
1647 //===----------------------------------------------------------------------===//
1649 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1650 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1652 def : MnemonicAlias<"cbw", "cbtw">;
1653 def : MnemonicAlias<"cwde", "cwtl">;
1654 def : MnemonicAlias<"cwd", "cwtd">;
1655 def : MnemonicAlias<"cdq", "cltd">;
1656 def : MnemonicAlias<"cdqe", "cltq">;
1657 def : MnemonicAlias<"cqo", "cqto">;
1659 // lret maps to lretl, it is not ambiguous with lretq.
1660 def : MnemonicAlias<"lret", "lretl">;
1662 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1663 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1665 def : MnemonicAlias<"loopz", "loope">;
1666 def : MnemonicAlias<"loopnz", "loopne">;
1668 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1669 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1670 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1671 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1672 def : MnemonicAlias<"popfd", "popfl">;
1674 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1675 // all modes. However: "push (addr)" and "push $42" should default to
1676 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1677 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1678 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1679 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1680 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1681 def : MnemonicAlias<"pushfd", "pushfl">;
1683 def : MnemonicAlias<"repe", "rep">;
1684 def : MnemonicAlias<"repz", "rep">;
1685 def : MnemonicAlias<"repnz", "repne">;
1687 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1688 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1690 def : MnemonicAlias<"salb", "shlb">;
1691 def : MnemonicAlias<"salw", "shlw">;
1692 def : MnemonicAlias<"sall", "shll">;
1693 def : MnemonicAlias<"salq", "shlq">;
1695 def : MnemonicAlias<"smovb", "movsb">;
1696 def : MnemonicAlias<"smovw", "movsw">;
1697 def : MnemonicAlias<"smovl", "movsl">;
1698 def : MnemonicAlias<"smovq", "movsq">;
1700 def : MnemonicAlias<"ud2a", "ud2">;
1701 def : MnemonicAlias<"verrw", "verr">;
1703 // System instruction aliases.
1704 def : MnemonicAlias<"iret", "iretl">;
1705 def : MnemonicAlias<"sysret", "sysretl">;
1706 def : MnemonicAlias<"sysexit", "sysexitl">;
1708 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1709 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1710 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1711 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1712 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1713 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1714 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1715 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1718 // Floating point stack aliases.
1719 def : MnemonicAlias<"fcmovz", "fcmove">;
1720 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1721 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1722 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1723 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1724 def : MnemonicAlias<"fcomip", "fcompi">;
1725 def : MnemonicAlias<"fildq", "fildll">;
1726 def : MnemonicAlias<"fistpq", "fistpll">;
1727 def : MnemonicAlias<"fisttpq", "fisttpll">;
1728 def : MnemonicAlias<"fldcww", "fldcw">;
1729 def : MnemonicAlias<"fnstcww", "fnstcw">;
1730 def : MnemonicAlias<"fnstsww", "fnstsw">;
1731 def : MnemonicAlias<"fucomip", "fucompi">;
1732 def : MnemonicAlias<"fwait", "wait">;
1735 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1736 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1737 !strconcat(Prefix, NewCond, Suffix)>;
1739 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1740 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1741 /// example "setz" -> "sete".
1742 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1743 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1744 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1745 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1746 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1747 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1748 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1749 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1750 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1751 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1752 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1754 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1755 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1756 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1757 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1760 // Aliases for set<CC>
1761 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1762 // Aliases for j<CC>
1763 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1764 // Aliases for cmov<CC>{w,l,q}
1765 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1766 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1767 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1770 //===----------------------------------------------------------------------===//
1771 // Assembler Instruction Aliases
1772 //===----------------------------------------------------------------------===//
1774 // aad/aam default to base 10 if no operand is specified.
1775 def : InstAlias<"aad", (AAD8i8 10)>;
1776 def : InstAlias<"aam", (AAM8i8 10)>;
1778 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1779 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1782 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1783 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1784 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1785 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1787 // div and idiv aliases for explicit A register.
1788 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1789 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1790 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1791 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1792 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1793 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1794 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1795 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1796 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1797 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1798 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1799 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1800 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1801 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1802 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1803 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1807 // Various unary fpstack operations default to operating on on ST1.
1808 // For example, "fxch" -> "fxch %st(1)"
1809 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1810 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1811 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1812 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1813 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1814 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1815 def : InstAlias<"fxch", (XCH_F ST1)>;
1816 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1817 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1818 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1819 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1820 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1821 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1823 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1824 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1825 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1827 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1828 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1829 (Inst RST:$op), EmitAlias>;
1830 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1831 (Inst ST0), EmitAlias>;
1834 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1835 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1836 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1837 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1838 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1839 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1840 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1841 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1842 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1843 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1844 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1845 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1846 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1847 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1848 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1849 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1852 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1853 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1854 // solely because gas supports it.
1855 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1856 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1857 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1858 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1859 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1860 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1862 // We accept "fnstsw %eax" even though it only writes %ax.
1863 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
1864 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
1865 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
1867 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1868 // this is compatible with what GAS does.
1869 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1870 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1871 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1872 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1874 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1875 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1876 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1877 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1878 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1879 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1880 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1882 // inb %dx -> inb %al, %dx
1883 def : InstAlias<"inb %dx", (IN8rr)>;
1884 def : InstAlias<"inw %dx", (IN16rr)>;
1885 def : InstAlias<"inl %dx", (IN32rr)>;
1886 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1887 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1888 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1891 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1892 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1893 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1894 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1895 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1896 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1897 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1899 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1900 // the move. All segment/mem forms are equivalent, this has the shortest
1902 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1903 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1905 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1906 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1908 // Match 'movq GR64, MMX' as an alias for movd.
1909 def : InstAlias<"movq $src, $dst",
1910 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1911 def : InstAlias<"movq $src, $dst",
1912 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1914 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1915 // alias for movsl. (as in rep; movsd)
1916 def : InstAlias<"movsd", (MOVSD)>;
1919 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1920 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1921 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1922 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1923 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1924 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1925 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1928 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1929 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1930 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1931 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1932 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1933 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1934 // Note: No GR32->GR64 movzx form.
1936 // outb %dx -> outb %al, %dx
1937 def : InstAlias<"outb %dx", (OUT8rr)>;
1938 def : InstAlias<"outw %dx", (OUT16rr)>;
1939 def : InstAlias<"outl %dx", (OUT32rr)>;
1940 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1941 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1942 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1944 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1945 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1946 // errors, since its encoding is the most compact.
1947 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1949 // shld/shrd op,op -> shld op, op, CL
1950 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
1951 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
1952 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
1953 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
1954 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
1955 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
1957 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
1958 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
1959 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
1960 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
1961 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
1962 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
1964 /* FIXME: This is disabled because the asm matcher is currently incapable of
1965 * matching a fixed immediate like $1.
1966 // "shl X, $1" is an alias for "shl X".
1967 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1968 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1969 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1970 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1971 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1972 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1973 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1974 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1975 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1976 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1977 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1978 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1979 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1980 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1981 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1982 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1983 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1986 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1987 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1988 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1989 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1992 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1993 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1994 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1995 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1996 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1998 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1999 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2000 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2001 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2002 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2004 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2005 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2006 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2007 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2008 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;