1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
102 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
106 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
108 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
110 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
112 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
114 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
118 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
119 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
120 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
121 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
123 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
124 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
126 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
127 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
129 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
130 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
132 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
133 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
134 SDNPMayLoad, SDNPMemOperand]>;
135 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
136 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137 SDNPMayLoad, SDNPMemOperand]>;
138 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140 SDNPMayLoad, SDNPMemOperand]>;
142 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
143 [SDNPHasChain, SDNPMayStore,
144 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
161 [SDNPHasChain, SDNPMayStore,
162 SDNPMayLoad, SDNPMemOperand]>;
163 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
164 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
166 def X86vastart_save_xmm_regs :
167 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
168 SDT_X86VASTART_SAVE_XMM_REGS,
169 [SDNPHasChain, SDNPVariadic]>;
171 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
172 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
174 def X86callseq_start :
175 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
176 [SDNPHasChain, SDNPOutGlue]>;
178 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
181 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
182 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
185 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
186 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
187 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
188 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
191 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
198 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
200 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
203 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
204 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
206 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
208 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
209 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
211 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
213 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
214 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
216 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
217 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
218 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
220 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
222 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
224 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
226 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
227 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
228 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
230 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
232 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
233 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
235 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
238 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
239 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
241 //===----------------------------------------------------------------------===//
242 // X86 Operand Definitions.
245 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
246 // the index operand of an address, to conform to x86 encoding restrictions.
247 def ptr_rc_nosp : PointerLikeRegClass<1>;
249 // *mem - Operand definitions for the funky X86 addressing mode operands.
251 def X86MemAsmOperand : AsmOperandClass {
252 let Name = "Mem"; let PredicateMethod = "isMem";
254 def X86Mem8AsmOperand : AsmOperandClass {
255 let Name = "Mem8"; let PredicateMethod = "isMem8";
257 def X86Mem16AsmOperand : AsmOperandClass {
258 let Name = "Mem16"; let PredicateMethod = "isMem16";
260 def X86Mem32AsmOperand : AsmOperandClass {
261 let Name = "Mem32"; let PredicateMethod = "isMem32";
263 def X86Mem64AsmOperand : AsmOperandClass {
264 let Name = "Mem64"; let PredicateMethod = "isMem64";
266 def X86Mem80AsmOperand : AsmOperandClass {
267 let Name = "Mem80"; let PredicateMethod = "isMem80";
269 def X86Mem128AsmOperand : AsmOperandClass {
270 let Name = "Mem128"; let PredicateMethod = "isMem128";
272 def X86Mem256AsmOperand : AsmOperandClass {
273 let Name = "Mem256"; let PredicateMethod = "isMem256";
276 def X86AbsMemAsmOperand : AsmOperandClass {
278 let SuperClasses = [X86MemAsmOperand];
280 class X86MemOperand<string printMethod> : Operand<iPTR> {
281 let PrintMethod = printMethod;
282 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
283 let ParserMatchClass = X86MemAsmOperand;
286 let OperandType = "OPERAND_MEMORY" in {
287 def opaque32mem : X86MemOperand<"printopaquemem">;
288 def opaque48mem : X86MemOperand<"printopaquemem">;
289 def opaque80mem : X86MemOperand<"printopaquemem">;
290 def opaque512mem : X86MemOperand<"printopaquemem">;
292 def i8mem : X86MemOperand<"printi8mem"> {
293 let ParserMatchClass = X86Mem8AsmOperand; }
294 def i16mem : X86MemOperand<"printi16mem"> {
295 let ParserMatchClass = X86Mem16AsmOperand; }
296 def i32mem : X86MemOperand<"printi32mem"> {
297 let ParserMatchClass = X86Mem32AsmOperand; }
298 def i64mem : X86MemOperand<"printi64mem"> {
299 let ParserMatchClass = X86Mem64AsmOperand; }
300 def i128mem : X86MemOperand<"printi128mem"> {
301 let ParserMatchClass = X86Mem128AsmOperand; }
302 def i256mem : X86MemOperand<"printi256mem"> {
303 let ParserMatchClass = X86Mem256AsmOperand; }
304 def f32mem : X86MemOperand<"printf32mem"> {
305 let ParserMatchClass = X86Mem32AsmOperand; }
306 def f64mem : X86MemOperand<"printf64mem"> {
307 let ParserMatchClass = X86Mem64AsmOperand; }
308 def f80mem : X86MemOperand<"printf80mem"> {
309 let ParserMatchClass = X86Mem80AsmOperand; }
310 def f128mem : X86MemOperand<"printf128mem"> {
311 let ParserMatchClass = X86Mem128AsmOperand; }
312 def f256mem : X86MemOperand<"printf256mem">{
313 let ParserMatchClass = X86Mem256AsmOperand; }
316 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
317 // plain GR64, so that it doesn't potentially require a REX prefix.
318 def i8mem_NOREX : Operand<i64> {
319 let PrintMethod = "printi8mem";
320 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
321 let ParserMatchClass = X86MemAsmOperand;
322 let OperandType = "OPERAND_MEMORY";
325 // GPRs available for tailcall.
326 // It represents GR64_TC or GR64_TCW64.
327 def ptr_rc_tailcall : PointerLikeRegClass<2>;
329 // Special i32mem for addresses of load folding tail calls. These are not
330 // allowed to use callee-saved registers since they must be scheduled
331 // after callee-saved register are popped.
332 def i32mem_TC : Operand<i32> {
333 let PrintMethod = "printi32mem";
334 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
335 let ParserMatchClass = X86MemAsmOperand;
336 let OperandType = "OPERAND_MEMORY";
339 // Special i64mem for addresses of load folding tail calls. These are not
340 // allowed to use callee-saved registers since they must be scheduled
341 // after callee-saved register are popped.
342 def i64mem_TC : Operand<i64> {
343 let PrintMethod = "printi64mem";
344 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
345 ptr_rc_tailcall, i32imm, i8imm);
346 let ParserMatchClass = X86MemAsmOperand;
347 let OperandType = "OPERAND_MEMORY";
350 let OperandType = "OPERAND_PCREL",
351 ParserMatchClass = X86AbsMemAsmOperand,
352 PrintMethod = "print_pcrel_imm" in {
353 def i32imm_pcrel : Operand<i32>;
354 def i16imm_pcrel : Operand<i16>;
356 def offset8 : Operand<i64>;
357 def offset16 : Operand<i64>;
358 def offset32 : Operand<i64>;
359 def offset64 : Operand<i64>;
361 // Branch targets have OtherVT type and print as pc-relative values.
362 def brtarget : Operand<OtherVT>;
363 def brtarget8 : Operand<OtherVT>;
367 def SSECC : Operand<i8> {
368 let PrintMethod = "printSSECC";
369 let OperandType = "OPERAND_IMMEDIATE";
372 class ImmSExtAsmOperandClass : AsmOperandClass {
373 let SuperClasses = [ImmAsmOperand];
374 let RenderMethod = "addImmOperands";
377 class ImmZExtAsmOperandClass : AsmOperandClass {
378 let SuperClasses = [ImmAsmOperand];
379 let RenderMethod = "addImmOperands";
382 // Sign-extended immediate classes. We don't need to define the full lattice
383 // here because there is no instruction with an ambiguity between ImmSExti64i32
386 // The strange ranges come from the fact that the assembler always works with
387 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
388 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
391 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
392 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
393 let Name = "ImmSExti64i32";
396 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
397 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
398 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
399 let Name = "ImmSExti16i8";
400 let SuperClasses = [ImmSExti64i32AsmOperand];
403 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
404 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
405 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
406 let Name = "ImmSExti32i8";
410 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
411 let Name = "ImmZExtu32u8";
416 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
417 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
418 let Name = "ImmSExti64i8";
419 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
420 ImmSExti64i32AsmOperand];
423 // A couple of more descriptive operand definitions.
424 // 16-bits but only 8 bits are significant.
425 def i16i8imm : Operand<i16> {
426 let ParserMatchClass = ImmSExti16i8AsmOperand;
427 let OperandType = "OPERAND_IMMEDIATE";
429 // 32-bits but only 8 bits are significant.
430 def i32i8imm : Operand<i32> {
431 let ParserMatchClass = ImmSExti32i8AsmOperand;
432 let OperandType = "OPERAND_IMMEDIATE";
434 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
435 def u32u8imm : Operand<i32> {
436 let ParserMatchClass = ImmZExtu32u8AsmOperand;
437 let OperandType = "OPERAND_IMMEDIATE";
440 // 64-bits but only 32 bits are significant.
441 def i64i32imm : Operand<i64> {
442 let ParserMatchClass = ImmSExti64i32AsmOperand;
443 let OperandType = "OPERAND_IMMEDIATE";
446 // 64-bits but only 32 bits are significant, and those bits are treated as being
448 def i64i32imm_pcrel : Operand<i64> {
449 let PrintMethod = "print_pcrel_imm";
450 let ParserMatchClass = X86AbsMemAsmOperand;
451 let OperandType = "OPERAND_PCREL";
454 // 64-bits but only 8 bits are significant.
455 def i64i8imm : Operand<i64> {
456 let ParserMatchClass = ImmSExti64i8AsmOperand;
457 let OperandType = "OPERAND_IMMEDIATE";
460 def lea64_32mem : Operand<i32> {
461 let PrintMethod = "printi32mem";
462 let AsmOperandLowerMethod = "lower_lea64_32mem";
463 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
464 let ParserMatchClass = X86MemAsmOperand;
468 //===----------------------------------------------------------------------===//
469 // X86 Complex Pattern Definitions.
472 // Define X86 specific addressing mode.
473 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
474 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
475 [add, sub, mul, X86mul_imm, shl, or, frameindex],
477 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
478 [tglobaltlsaddr], []>;
480 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
481 [add, sub, mul, X86mul_imm, shl, or, frameindex,
484 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
485 [tglobaltlsaddr], []>;
487 //===----------------------------------------------------------------------===//
488 // X86 Instruction Predicate Definitions.
489 def HasCMov : Predicate<"Subtarget->hasCMov()">;
490 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
492 def HasMMX : Predicate<"Subtarget->hasMMX()">;
493 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
494 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
495 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
496 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
497 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
498 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
499 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
500 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
501 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
502 def HasAVX : Predicate<"Subtarget->hasAVX()">;
503 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
505 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
506 def HasAES : Predicate<"Subtarget->hasAES()">;
507 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
508 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
509 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
510 def HasXOP : Predicate<"Subtarget->hasXOP()">;
511 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
512 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
513 def HasF16C : Predicate<"Subtarget->hasF16C()">;
514 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
515 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
516 def HasBMI : Predicate<"Subtarget->hasBMI()">;
517 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
518 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
519 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
520 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
521 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
522 AssemblerPredicate<"!Mode64Bit">;
523 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
524 AssemblerPredicate<"Mode64Bit">;
525 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
526 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
527 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
528 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
529 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
530 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
531 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
532 "TM.getCodeModel() != CodeModel::Kernel">;
533 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
534 "TM.getCodeModel() == CodeModel::Kernel">;
535 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
536 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
537 def OptForSize : Predicate<"OptForSize">;
538 def OptForSpeed : Predicate<"!OptForSize">;
539 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
540 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
542 //===----------------------------------------------------------------------===//
543 // X86 Instruction Format Definitions.
546 include "X86InstrFormats.td"
548 //===----------------------------------------------------------------------===//
549 // Pattern fragments.
552 // X86 specific condition code. These correspond to CondCode in
553 // X86InstrInfo.h. They must be kept in synch.
554 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
555 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
556 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
557 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
558 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
559 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
560 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
561 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
562 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
563 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
564 def X86_COND_NO : PatLeaf<(i8 10)>;
565 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
566 def X86_COND_NS : PatLeaf<(i8 12)>;
567 def X86_COND_O : PatLeaf<(i8 13)>;
568 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
569 def X86_COND_S : PatLeaf<(i8 15)>;
571 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
572 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
573 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
574 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
577 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
580 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
582 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
584 def i64immZExt32SExt8 : ImmLeaf<i64, [{
585 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
588 // Helper fragments for loads.
589 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
590 // known to be 32-bit aligned or better. Ditto for i8 to i16.
591 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
592 LoadSDNode *LD = cast<LoadSDNode>(N);
593 ISD::LoadExtType ExtType = LD->getExtensionType();
594 if (ExtType == ISD::NON_EXTLOAD)
596 if (ExtType == ISD::EXTLOAD)
597 return LD->getAlignment() >= 2 && !LD->isVolatile();
601 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
602 LoadSDNode *LD = cast<LoadSDNode>(N);
603 ISD::LoadExtType ExtType = LD->getExtensionType();
604 if (ExtType == ISD::EXTLOAD)
605 return LD->getAlignment() >= 2 && !LD->isVolatile();
609 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
610 LoadSDNode *LD = cast<LoadSDNode>(N);
611 ISD::LoadExtType ExtType = LD->getExtensionType();
612 if (ExtType == ISD::NON_EXTLOAD)
614 if (ExtType == ISD::EXTLOAD)
615 return LD->getAlignment() >= 4 && !LD->isVolatile();
619 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
620 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
621 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
622 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
623 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
625 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
626 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
627 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
628 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
629 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
630 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
632 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
633 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
634 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
635 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
636 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
637 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
638 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
639 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
640 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
641 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
643 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
644 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
645 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
646 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
647 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
648 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
649 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
650 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
651 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
652 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
655 // An 'and' node with a single use.
656 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
657 return N->hasOneUse();
659 // An 'srl' node with a single use.
660 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
661 return N->hasOneUse();
663 // An 'trunc' node with a single use.
664 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
665 return N->hasOneUse();
668 //===----------------------------------------------------------------------===//
673 let neverHasSideEffects = 1 in {
674 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
675 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
676 "nop{w}\t$zero", []>, TB, OpSize;
677 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
678 "nop{l}\t$zero", []>, TB;
682 // Constructing a stack frame.
683 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
684 "enter\t$len, $lvl", []>;
686 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
687 def LEAVE : I<0xC9, RawFrm,
688 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
690 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
691 def LEAVE64 : I<0xC9, RawFrm,
692 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
694 //===----------------------------------------------------------------------===//
695 // Miscellaneous Instructions.
698 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
700 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
702 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
703 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
705 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
707 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
708 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
710 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
711 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
712 Requires<[In32BitMode]>;
715 let mayStore = 1 in {
716 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
718 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
719 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
721 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
723 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
724 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
726 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
727 "push{l}\t$imm", []>;
728 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
729 "push{w}\t$imm", []>, OpSize;
730 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
731 "push{l}\t$imm", []>;
733 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
734 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
735 Requires<[In32BitMode]>;
740 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
742 def POP64r : I<0x58, AddRegFrm,
743 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
744 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
745 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
747 let mayStore = 1 in {
748 def PUSH64r : I<0x50, AddRegFrm,
749 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
750 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
751 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
755 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
756 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
757 "push{q}\t$imm", []>;
758 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
759 "push{q}\t$imm", []>;
760 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
761 "push{q}\t$imm", []>;
764 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
765 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
766 Requires<[In64BitMode]>;
767 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
768 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
769 Requires<[In64BitMode]>;
773 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
774 mayLoad=1, neverHasSideEffects=1 in {
775 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
776 Requires<[In32BitMode]>;
778 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
779 mayStore=1, neverHasSideEffects=1 in {
780 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
781 Requires<[In32BitMode]>;
784 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
785 def BSWAP32r : I<0xC8, AddRegFrm,
786 (outs GR32:$dst), (ins GR32:$src),
788 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
790 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
792 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
793 } // Constraints = "$src = $dst"
795 // Bit scan instructions.
796 let Defs = [EFLAGS] in {
797 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
798 "bsf{w}\t{$src, $dst|$dst, $src}",
799 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
800 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
801 "bsf{w}\t{$src, $dst|$dst, $src}",
802 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
804 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
805 "bsf{l}\t{$src, $dst|$dst, $src}",
806 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
807 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
808 "bsf{l}\t{$src, $dst|$dst, $src}",
809 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
810 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
811 "bsf{q}\t{$src, $dst|$dst, $src}",
812 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
813 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
814 "bsf{q}\t{$src, $dst|$dst, $src}",
815 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
817 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
818 "bsr{w}\t{$src, $dst|$dst, $src}",
819 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
820 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
821 "bsr{w}\t{$src, $dst|$dst, $src}",
822 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
824 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
825 "bsr{l}\t{$src, $dst|$dst, $src}",
826 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
827 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
828 "bsr{l}\t{$src, $dst|$dst, $src}",
829 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
830 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
831 "bsr{q}\t{$src, $dst|$dst, $src}",
832 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
833 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
834 "bsr{q}\t{$src, $dst|$dst, $src}",
835 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
839 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
840 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
841 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
842 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
843 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
844 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
847 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
848 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
849 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
850 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
851 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
852 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
853 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
854 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
855 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
857 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
858 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
859 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
860 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
862 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
863 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
864 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
865 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
868 //===----------------------------------------------------------------------===//
869 // Move Instructions.
872 let neverHasSideEffects = 1 in {
873 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
874 "mov{b}\t{$src, $dst|$dst, $src}", []>;
875 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
876 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
877 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
878 "mov{l}\t{$src, $dst|$dst, $src}", []>;
879 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
880 "mov{q}\t{$src, $dst|$dst, $src}", []>;
882 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
883 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
884 "mov{b}\t{$src, $dst|$dst, $src}",
885 [(set GR8:$dst, imm:$src)]>;
886 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
887 "mov{w}\t{$src, $dst|$dst, $src}",
888 [(set GR16:$dst, imm:$src)]>, OpSize;
889 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
890 "mov{l}\t{$src, $dst|$dst, $src}",
891 [(set GR32:$dst, imm:$src)]>;
892 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
893 "movabs{q}\t{$src, $dst|$dst, $src}",
894 [(set GR64:$dst, imm:$src)]>;
895 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
896 "mov{q}\t{$src, $dst|$dst, $src}",
897 [(set GR64:$dst, i64immSExt32:$src)]>;
900 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
901 "mov{b}\t{$src, $dst|$dst, $src}",
902 [(store (i8 imm:$src), addr:$dst)]>;
903 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
904 "mov{w}\t{$src, $dst|$dst, $src}",
905 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
906 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
907 "mov{l}\t{$src, $dst|$dst, $src}",
908 [(store (i32 imm:$src), addr:$dst)]>;
909 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
910 "mov{q}\t{$src, $dst|$dst, $src}",
911 [(store i64immSExt32:$src, addr:$dst)]>;
913 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
914 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
915 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
916 "mov{b}\t{$src, %al|AL, $src}", []>,
917 Requires<[In32BitMode]>;
918 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
919 "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
920 Requires<[In32BitMode]>;
921 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
922 "mov{l}\t{$src, %eax|EAX, $src}", []>,
923 Requires<[In32BitMode]>;
924 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
925 "mov{b}\t{%al, $dst|$dst, AL}", []>,
926 Requires<[In32BitMode]>;
927 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
928 "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
929 Requires<[In32BitMode]>;
930 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
931 "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
932 Requires<[In32BitMode]>;
934 // FIXME: These definitions are utterly broken
935 // Just leave them commented out for now because they're useless outside
936 // of the large code model, and most compilers won't generate the instructions
939 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
940 "mov{q}\t{$src, %rax|RAX, $src}", []>;
941 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
942 "mov{q}\t{$src, %rax|RAX, $src}", []>;
943 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
944 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
945 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
946 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
950 let isCodeGenOnly = 1 in {
951 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
952 "mov{b}\t{$src, $dst|$dst, $src}", []>;
953 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
954 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
955 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
956 "mov{l}\t{$src, $dst|$dst, $src}", []>;
957 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
958 "mov{q}\t{$src, $dst|$dst, $src}", []>;
961 let canFoldAsLoad = 1, isReMaterializable = 1 in {
962 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
963 "mov{b}\t{$src, $dst|$dst, $src}",
964 [(set GR8:$dst, (loadi8 addr:$src))]>;
965 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
966 "mov{w}\t{$src, $dst|$dst, $src}",
967 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
968 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
969 "mov{l}\t{$src, $dst|$dst, $src}",
970 [(set GR32:$dst, (loadi32 addr:$src))]>;
971 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
972 "mov{q}\t{$src, $dst|$dst, $src}",
973 [(set GR64:$dst, (load addr:$src))]>;
976 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
977 "mov{b}\t{$src, $dst|$dst, $src}",
978 [(store GR8:$src, addr:$dst)]>;
979 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
980 "mov{w}\t{$src, $dst|$dst, $src}",
981 [(store GR16:$src, addr:$dst)]>, OpSize;
982 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
983 "mov{l}\t{$src, $dst|$dst, $src}",
984 [(store GR32:$src, addr:$dst)]>;
985 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
986 "mov{q}\t{$src, $dst|$dst, $src}",
987 [(store GR64:$src, addr:$dst)]>;
989 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
990 // that they can be used for copying and storing h registers, which can't be
991 // encoded when a REX prefix is present.
992 let isCodeGenOnly = 1 in {
993 let neverHasSideEffects = 1 in
994 def MOV8rr_NOREX : I<0x88, MRMDestReg,
995 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
996 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
998 def MOV8mr_NOREX : I<0x88, MRMDestMem,
999 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1000 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1001 let mayLoad = 1, neverHasSideEffects = 1,
1002 canFoldAsLoad = 1, isReMaterializable = 1 in
1003 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1004 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1005 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1009 // Condition code ops, incl. set if equal/not equal/...
1010 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
1011 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
1012 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1013 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
1016 //===----------------------------------------------------------------------===//
1017 // Bit tests instructions: BT, BTS, BTR, BTC.
1019 let Defs = [EFLAGS] in {
1020 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1021 "bt{w}\t{$src2, $src1|$src1, $src2}",
1022 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
1023 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1024 "bt{l}\t{$src2, $src1|$src1, $src2}",
1025 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
1026 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1027 "bt{q}\t{$src2, $src1|$src1, $src2}",
1028 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1030 // Unlike with the register+register form, the memory+register form of the
1031 // bt instruction does not ignore the high bits of the index. From ISel's
1032 // perspective, this is pretty bizarre. Make these instructions disassembly
1035 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1036 "bt{w}\t{$src2, $src1|$src1, $src2}",
1037 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1038 // (implicit EFLAGS)]
1040 >, OpSize, TB, Requires<[FastBTMem]>;
1041 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1042 "bt{l}\t{$src2, $src1|$src1, $src2}",
1043 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1044 // (implicit EFLAGS)]
1046 >, TB, Requires<[FastBTMem]>;
1047 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1048 "bt{q}\t{$src2, $src1|$src1, $src2}",
1049 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1050 // (implicit EFLAGS)]
1054 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1055 "bt{w}\t{$src2, $src1|$src1, $src2}",
1056 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1058 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1059 "bt{l}\t{$src2, $src1|$src1, $src2}",
1060 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1061 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1062 "bt{q}\t{$src2, $src1|$src1, $src2}",
1063 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1065 // Note that these instructions don't need FastBTMem because that
1066 // only applies when the other operand is in a register. When it's
1067 // an immediate, bt is still fast.
1068 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1069 "bt{w}\t{$src2, $src1|$src1, $src2}",
1070 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1072 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1073 "bt{l}\t{$src2, $src1|$src1, $src2}",
1074 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1076 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1077 "bt{q}\t{$src2, $src1|$src1, $src2}",
1078 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1079 i64immSExt8:$src2))]>, TB;
1082 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1083 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1084 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1085 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1086 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1087 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1088 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1089 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1090 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1091 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1092 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1093 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1094 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1095 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1096 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1097 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1098 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1099 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1100 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1101 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1102 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1103 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1104 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1105 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1107 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1108 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1109 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1110 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1111 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1112 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1113 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1114 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1115 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1116 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1117 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1118 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1119 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1120 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1121 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1122 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1123 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1124 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1125 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1126 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1127 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1128 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1129 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1130 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1132 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1133 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1134 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1135 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1136 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1137 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1138 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1139 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1140 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1141 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1142 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1143 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1144 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1145 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1146 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1147 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1148 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1149 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1150 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1151 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1152 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1153 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1154 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1155 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1156 } // Defs = [EFLAGS]
1159 //===----------------------------------------------------------------------===//
1164 // Atomic swap. These are just normal xchg instructions. But since a memory
1165 // operand is referenced, the atomicity is ensured.
1166 let Constraints = "$val = $dst" in {
1167 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1168 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1169 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1170 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1171 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1172 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1174 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1175 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1176 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1177 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1178 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1179 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1181 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1182 "xchg{b}\t{$val, $src|$src, $val}", []>;
1183 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1184 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1185 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1186 "xchg{l}\t{$val, $src|$src, $val}", []>;
1187 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1188 "xchg{q}\t{$val, $src|$src, $val}", []>;
1191 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1192 "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
1193 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1194 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
1195 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1196 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1197 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1198 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
1199 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1200 "xchg{q}\t{$src, %rax|RAX, $src}", []>;
1204 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1205 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1206 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1207 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1208 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1209 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1210 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1211 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1213 let mayLoad = 1, mayStore = 1 in {
1214 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1215 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1216 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1217 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1218 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1219 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1220 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1221 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1225 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1226 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1227 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1228 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1229 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1230 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1231 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1232 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1234 let mayLoad = 1, mayStore = 1 in {
1235 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1236 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1237 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1238 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1239 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1240 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1241 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1242 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1245 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1246 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1247 "cmpxchg8b\t$dst", []>, TB;
1249 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1250 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1251 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1255 // Lock instruction prefix
1256 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1258 // Rex64 instruction prefix
1259 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1261 // Data16 instruction prefix
1262 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1264 // Repeat string operation instruction prefixes
1265 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1266 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1267 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1268 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1269 // Repeat while not equal (used with CMPS and SCAS)
1270 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1274 // String manipulation instructions
1275 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1276 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1277 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1278 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1280 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1281 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1282 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1285 // Flag instructions
1286 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1287 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1288 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1289 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1290 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1291 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1292 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1294 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1296 // Table lookup instructions
1297 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1299 // ASCII Adjust After Addition
1300 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1301 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1303 // ASCII Adjust AX Before Division
1304 // sets AL, AH and EFLAGS and uses AL and AH
1305 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1306 "aad\t$src", []>, Requires<[In32BitMode]>;
1308 // ASCII Adjust AX After Multiply
1309 // sets AL, AH and EFLAGS and uses AL
1310 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1311 "aam\t$src", []>, Requires<[In32BitMode]>;
1313 // ASCII Adjust AL After Subtraction - sets
1314 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1315 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1317 // Decimal Adjust AL after Addition
1318 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1319 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1321 // Decimal Adjust AL after Subtraction
1322 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1323 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1325 // Check Array Index Against Bounds
1326 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1327 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1328 Requires<[In32BitMode]>;
1329 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1330 "bound\t{$src, $dst|$dst, $src}", []>,
1331 Requires<[In32BitMode]>;
1333 // Adjust RPL Field of Segment Selector
1334 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1335 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1336 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1337 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1339 //===----------------------------------------------------------------------===//
1340 // MOVBE Instructions
1342 let Predicates = [HasMOVBE] in {
1343 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1344 "movbe{w}\t{$src, $dst|$dst, $src}",
1345 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
1346 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1347 "movbe{l}\t{$src, $dst|$dst, $src}",
1348 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
1349 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1350 "movbe{q}\t{$src, $dst|$dst, $src}",
1351 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
1352 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1353 "movbe{w}\t{$src, $dst|$dst, $src}",
1354 [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
1355 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1356 "movbe{l}\t{$src, $dst|$dst, $src}",
1357 [(store (bswap GR32:$src), addr:$dst)]>, T8;
1358 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1359 "movbe{q}\t{$src, $dst|$dst, $src}",
1360 [(store (bswap GR64:$src), addr:$dst)]>, T8;
1363 //===----------------------------------------------------------------------===//
1364 // RDRAND Instruction
1366 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1367 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1368 "rdrand{w}\t$dst", []>, OpSize, TB;
1369 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1370 "rdrand{l}\t$dst", []>, TB;
1371 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1372 "rdrand{q}\t$dst", []>, TB;
1375 //===----------------------------------------------------------------------===//
1376 // LZCNT Instruction
1378 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1379 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1380 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1381 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1383 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1384 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1385 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1386 (implicit EFLAGS)]>, XS, OpSize;
1388 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1389 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1390 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1391 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1392 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1393 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1394 (implicit EFLAGS)]>, XS;
1396 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1397 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1398 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1400 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1401 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1402 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1403 (implicit EFLAGS)]>, XS;
1406 //===----------------------------------------------------------------------===//
1409 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1410 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1411 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1412 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1414 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1415 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1416 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1417 (implicit EFLAGS)]>, XS, OpSize;
1419 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1420 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1421 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1422 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1423 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1424 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1425 (implicit EFLAGS)]>, XS;
1427 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1428 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1429 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1431 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1432 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1433 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1434 (implicit EFLAGS)]>, XS;
1437 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1438 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1440 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1441 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1442 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1443 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1444 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1445 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1449 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1450 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1451 X86blsr_flag, loadi32>;
1452 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1453 X86blsr_flag, loadi64>, VEX_W;
1454 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1455 X86blsmsk_flag, loadi32>;
1456 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1457 X86blsmsk_flag, loadi64>, VEX_W;
1458 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1459 X86blsi_flag, loadi32>;
1460 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1461 X86blsi_flag, loadi64>, VEX_W;
1464 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1465 X86MemOperand x86memop, Intrinsic Int,
1467 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1468 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1469 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1471 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1472 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1473 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1474 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1477 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1478 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1479 int_x86_bmi_bextr_32, loadi32>;
1480 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1481 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1484 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1485 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1486 int_x86_bmi_bzhi_32, loadi32>;
1487 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1488 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1491 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1492 X86MemOperand x86memop, Intrinsic Int,
1494 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1495 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1496 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1498 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1499 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1500 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1503 let Predicates = [HasBMI2] in {
1504 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1505 int_x86_bmi_pdep_32, loadi32>, T8XD;
1506 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1507 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1508 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1509 int_x86_bmi_pext_32, loadi32>, T8XS;
1510 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1511 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1514 //===----------------------------------------------------------------------===//
1516 //===----------------------------------------------------------------------===//
1518 include "X86InstrArithmetic.td"
1519 include "X86InstrCMovSetCC.td"
1520 include "X86InstrExtension.td"
1521 include "X86InstrControl.td"
1522 include "X86InstrShiftRotate.td"
1524 // X87 Floating Point Stack.
1525 include "X86InstrFPStack.td"
1527 // SIMD support (SSE, MMX and AVX)
1528 include "X86InstrFragmentsSIMD.td"
1530 // FMA - Fused Multiply-Add support (requires FMA)
1531 include "X86InstrFMA.td"
1534 include "X86InstrXOP.td"
1536 // SSE, MMX and 3DNow! vector support.
1537 include "X86InstrSSE.td"
1538 include "X86InstrMMX.td"
1539 include "X86Instr3DNow.td"
1541 include "X86InstrVMX.td"
1543 // System instructions.
1544 include "X86InstrSystem.td"
1546 // Compiler Pseudo Instructions and Pat Patterns
1547 include "X86InstrCompiler.td"
1549 //===----------------------------------------------------------------------===//
1550 // Assembler Mnemonic Aliases
1551 //===----------------------------------------------------------------------===//
1553 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1554 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1556 def : MnemonicAlias<"cbw", "cbtw">;
1557 def : MnemonicAlias<"cwde", "cwtl">;
1558 def : MnemonicAlias<"cwd", "cwtd">;
1559 def : MnemonicAlias<"cdq", "cltd">;
1560 def : MnemonicAlias<"cdqe", "cltq">;
1561 def : MnemonicAlias<"cqo", "cqto">;
1563 // lret maps to lretl, it is not ambiguous with lretq.
1564 def : MnemonicAlias<"lret", "lretl">;
1566 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1567 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1569 def : MnemonicAlias<"loopz", "loope">;
1570 def : MnemonicAlias<"loopnz", "loopne">;
1572 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1573 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1574 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1575 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1576 def : MnemonicAlias<"popfd", "popfl">;
1578 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1579 // all modes. However: "push (addr)" and "push $42" should default to
1580 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1581 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1582 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1583 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1584 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1585 def : MnemonicAlias<"pushfd", "pushfl">;
1587 def : MnemonicAlias<"repe", "rep">;
1588 def : MnemonicAlias<"repz", "rep">;
1589 def : MnemonicAlias<"repnz", "repne">;
1591 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1592 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1594 def : MnemonicAlias<"salb", "shlb">;
1595 def : MnemonicAlias<"salw", "shlw">;
1596 def : MnemonicAlias<"sall", "shll">;
1597 def : MnemonicAlias<"salq", "shlq">;
1599 def : MnemonicAlias<"smovb", "movsb">;
1600 def : MnemonicAlias<"smovw", "movsw">;
1601 def : MnemonicAlias<"smovl", "movsl">;
1602 def : MnemonicAlias<"smovq", "movsq">;
1604 def : MnemonicAlias<"ud2a", "ud2">;
1605 def : MnemonicAlias<"verrw", "verr">;
1607 // System instruction aliases.
1608 def : MnemonicAlias<"iret", "iretl">;
1609 def : MnemonicAlias<"sysret", "sysretl">;
1610 def : MnemonicAlias<"sysexit", "sysexitl">;
1612 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1613 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1614 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1615 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1616 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1617 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1618 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1619 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1622 // Floating point stack aliases.
1623 def : MnemonicAlias<"fcmovz", "fcmove">;
1624 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1625 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1626 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1627 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1628 def : MnemonicAlias<"fcomip", "fcompi">;
1629 def : MnemonicAlias<"fildq", "fildll">;
1630 def : MnemonicAlias<"fldcww", "fldcw">;
1631 def : MnemonicAlias<"fnstcww", "fnstcw">;
1632 def : MnemonicAlias<"fnstsww", "fnstsw">;
1633 def : MnemonicAlias<"fucomip", "fucompi">;
1634 def : MnemonicAlias<"fwait", "wait">;
1637 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1638 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1639 !strconcat(Prefix, NewCond, Suffix)>;
1641 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1642 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1643 /// example "setz" -> "sete".
1644 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1645 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1646 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1647 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1648 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1649 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1650 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1651 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1652 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1653 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1654 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1656 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1657 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1658 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1659 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1662 // Aliases for set<CC>
1663 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1664 // Aliases for j<CC>
1665 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1666 // Aliases for cmov<CC>{w,l,q}
1667 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1668 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1669 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1672 //===----------------------------------------------------------------------===//
1673 // Assembler Instruction Aliases
1674 //===----------------------------------------------------------------------===//
1676 // aad/aam default to base 10 if no operand is specified.
1677 def : InstAlias<"aad", (AAD8i8 10)>;
1678 def : InstAlias<"aam", (AAM8i8 10)>;
1680 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1681 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1684 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1685 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1686 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1687 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1689 // div and idiv aliases for explicit A register.
1690 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1691 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1692 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1693 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1694 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1695 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1696 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1697 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1698 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1699 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1700 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1701 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1702 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1703 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1704 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1705 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1709 // Various unary fpstack operations default to operating on on ST1.
1710 // For example, "fxch" -> "fxch %st(1)"
1711 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1712 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1713 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1714 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1715 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1716 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1717 def : InstAlias<"fxch", (XCH_F ST1)>;
1718 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1719 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1720 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1721 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1722 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1723 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1725 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1726 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1727 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1729 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1730 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1731 (Inst RST:$op), EmitAlias>;
1732 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1733 (Inst ST0), EmitAlias>;
1736 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1737 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1738 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1739 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1740 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1741 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1742 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1743 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1744 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1745 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1746 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1747 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1748 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1749 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1750 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1751 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1754 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1755 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1756 // solely because gas supports it.
1757 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1758 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1759 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1760 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1761 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1762 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1764 // We accept "fnstsw %eax" even though it only writes %ax.
1765 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1766 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1767 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1769 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1770 // this is compatible with what GAS does.
1771 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1772 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1773 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1774 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1776 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1777 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1778 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1779 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1780 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1781 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1782 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1784 // inb %dx -> inb %al, %dx
1785 def : InstAlias<"inb %dx", (IN8rr)>;
1786 def : InstAlias<"inw %dx", (IN16rr)>;
1787 def : InstAlias<"inl %dx", (IN32rr)>;
1788 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1789 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1790 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1793 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1794 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1795 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1796 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1797 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1798 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1799 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1801 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1802 // the move. All segment/mem forms are equivalent, this has the shortest
1804 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1805 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1807 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1808 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1810 // Match 'movq GR64, MMX' as an alias for movd.
1811 def : InstAlias<"movq $src, $dst",
1812 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1813 def : InstAlias<"movq $src, $dst",
1814 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1816 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1817 // alias for movsl. (as in rep; movsd)
1818 def : InstAlias<"movsd", (MOVSD)>;
1821 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1822 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1823 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1824 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1825 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1826 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1827 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1830 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1831 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1832 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1833 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1834 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1835 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1836 // Note: No GR32->GR64 movzx form.
1838 // outb %dx -> outb %al, %dx
1839 def : InstAlias<"outb %dx", (OUT8rr)>;
1840 def : InstAlias<"outw %dx", (OUT16rr)>;
1841 def : InstAlias<"outl %dx", (OUT32rr)>;
1842 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1843 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1844 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1846 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1847 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1848 // errors, since its encoding is the most compact.
1849 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1851 // shld/shrd op,op -> shld op, op, 1
1852 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1853 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1854 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1855 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1856 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1857 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1859 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1860 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1861 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1862 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1863 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1864 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1866 /* FIXME: This is disabled because the asm matcher is currently incapable of
1867 * matching a fixed immediate like $1.
1868 // "shl X, $1" is an alias for "shl X".
1869 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1870 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1871 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1872 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1873 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1874 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1875 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1876 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1877 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1878 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1879 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1880 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1881 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1882 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1883 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1884 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1885 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1888 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1889 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1890 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1891 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1894 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1895 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1896 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1897 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1898 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1900 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1901 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1902 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1903 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1904 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
1906 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
1907 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
1908 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
1909 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
1910 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;