1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
198 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
200 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
201 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
206 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
207 SDTypeProfile<1, 1, [SDTCisInt<0>,
209 [SDNPHasChain, SDNPSideEffect]>;
210 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
211 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
212 [SDNPHasChain, SDNPSideEffect]>;
214 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
215 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
217 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
219 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
220 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
222 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
224 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
225 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
227 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
228 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
229 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
231 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
233 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
236 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
238 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
240 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
241 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
243 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
246 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
247 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
249 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
250 [SDNPHasChain, SDNPOutGlue]>;
252 //===----------------------------------------------------------------------===//
253 // X86 Operand Definitions.
256 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
257 // the index operand of an address, to conform to x86 encoding restrictions.
258 def ptr_rc_nosp : PointerLikeRegClass<1>;
260 // *mem - Operand definitions for the funky X86 addressing mode operands.
262 def X86MemAsmOperand : AsmOperandClass {
265 let RenderMethod = "addMemOperands" in {
266 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
267 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
268 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
269 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
270 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
271 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
272 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
273 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
274 // Gather mem operands
275 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
276 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
277 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
278 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
279 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
280 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
283 def X86AbsMemAsmOperand : AsmOperandClass {
285 let SuperClasses = [X86MemAsmOperand];
288 class X86MemOperand<string printMethod,
289 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
290 let PrintMethod = printMethod;
291 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
292 let ParserMatchClass = parserMatchClass;
293 let OperandType = "OPERAND_MEMORY";
296 // Gather mem operands
297 class X86VMemOperand<RegisterClass RC, string printMethod,
298 AsmOperandClass parserMatchClass>
299 : X86MemOperand<printMethod, parserMatchClass> {
300 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
303 def opaque32mem : X86MemOperand<"printopaquemem">;
304 def opaque48mem : X86MemOperand<"printopaquemem">;
305 def opaque80mem : X86MemOperand<"printopaquemem">;
306 def opaque512mem : X86MemOperand<"printopaquemem">;
308 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
309 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
310 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
311 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
312 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
313 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
314 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
315 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
316 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
317 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
318 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
319 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
320 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
322 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
324 // Gather mem operands
325 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
326 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
327 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
328 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
329 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
330 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
331 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
333 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
334 // plain GR64, so that it doesn't potentially require a REX prefix.
335 def i8mem_NOREX : Operand<i64> {
336 let PrintMethod = "printi8mem";
337 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
338 let ParserMatchClass = X86Mem8AsmOperand;
339 let OperandType = "OPERAND_MEMORY";
342 // GPRs available for tailcall.
343 // It represents GR32_TC, GR64_TC or GR64_TCW64.
344 def ptr_rc_tailcall : PointerLikeRegClass<2>;
346 // Special i32mem for addresses of load folding tail calls. These are not
347 // allowed to use callee-saved registers since they must be scheduled
348 // after callee-saved register are popped.
349 def i32mem_TC : Operand<i32> {
350 let PrintMethod = "printi32mem";
351 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
353 let ParserMatchClass = X86Mem32AsmOperand;
354 let OperandType = "OPERAND_MEMORY";
357 // Special i64mem for addresses of load folding tail calls. These are not
358 // allowed to use callee-saved registers since they must be scheduled
359 // after callee-saved register are popped.
360 def i64mem_TC : Operand<i64> {
361 let PrintMethod = "printi64mem";
362 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
363 ptr_rc_tailcall, i32imm, i8imm);
364 let ParserMatchClass = X86Mem64AsmOperand;
365 let OperandType = "OPERAND_MEMORY";
368 let OperandType = "OPERAND_PCREL",
369 ParserMatchClass = X86AbsMemAsmOperand,
370 PrintMethod = "printPCRelImm" in {
371 def i32imm_pcrel : Operand<i32>;
372 def i16imm_pcrel : Operand<i16>;
374 // Branch targets have OtherVT type and print as pc-relative values.
375 def brtarget : Operand<OtherVT>;
376 def brtarget8 : Operand<OtherVT>;
380 let RenderMethod = "addSrcIdxOperands" in {
381 def X86SrcIdx8Operand : AsmOperandClass {
382 let Name = "SrcIdx8";
383 let SuperClasses = [X86Mem8AsmOperand];
385 def X86SrcIdx16Operand : AsmOperandClass {
386 let Name = "SrcIdx16";
387 let SuperClasses = [X86Mem16AsmOperand];
389 def X86SrcIdx32Operand : AsmOperandClass {
390 let Name = "SrcIdx32";
391 let SuperClasses = [X86Mem32AsmOperand];
393 def X86SrcIdx64Operand : AsmOperandClass {
394 let Name = "SrcIdx64";
395 let SuperClasses = [X86Mem64AsmOperand];
397 } // RenderMethod = "addSrcIdxOperands"
399 let RenderMethod = "addDstIdxOperands" in {
400 def X86DstIdx8Operand : AsmOperandClass {
401 let Name = "DstIdx8";
402 let SuperClasses = [X86Mem8AsmOperand];
404 def X86DstIdx16Operand : AsmOperandClass {
405 let Name = "DstIdx16";
406 let SuperClasses = [X86Mem16AsmOperand];
408 def X86DstIdx32Operand : AsmOperandClass {
409 let Name = "DstIdx32";
410 let SuperClasses = [X86Mem32AsmOperand];
412 def X86DstIdx64Operand : AsmOperandClass {
413 let Name = "DstIdx64";
414 let SuperClasses = [X86Mem64AsmOperand];
416 } // RenderMethod = "addDstIdxOperands"
418 let RenderMethod = "addMemOffsOperands" in {
419 def X86MemOffs16_8AsmOperand : AsmOperandClass {
420 let Name = "MemOffs16_8";
421 let SuperClasses = [X86Mem8AsmOperand];
423 def X86MemOffs16_16AsmOperand : AsmOperandClass {
424 let Name = "MemOffs16_16";
425 let SuperClasses = [X86Mem16AsmOperand];
427 def X86MemOffs16_32AsmOperand : AsmOperandClass {
428 let Name = "MemOffs16_32";
429 let SuperClasses = [X86Mem32AsmOperand];
431 def X86MemOffs32_8AsmOperand : AsmOperandClass {
432 let Name = "MemOffs32_8";
433 let SuperClasses = [X86Mem8AsmOperand];
435 def X86MemOffs32_16AsmOperand : AsmOperandClass {
436 let Name = "MemOffs32_16";
437 let SuperClasses = [X86Mem16AsmOperand];
439 def X86MemOffs32_32AsmOperand : AsmOperandClass {
440 let Name = "MemOffs32_32";
441 let SuperClasses = [X86Mem32AsmOperand];
443 def X86MemOffs32_64AsmOperand : AsmOperandClass {
444 let Name = "MemOffs32_64";
445 let SuperClasses = [X86Mem64AsmOperand];
447 def X86MemOffs64_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs64_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs64_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs64_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs64_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs64_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs64_64AsmOperand : AsmOperandClass {
460 let Name = "MemOffs64_64";
461 let SuperClasses = [X86Mem64AsmOperand];
463 } // RenderMethod = "addMemOffsOperands"
465 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
466 : X86MemOperand<printMethod, parserMatchClass> {
467 let MIOperandInfo = (ops ptr_rc, i8imm);
470 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
471 : X86MemOperand<printMethod, parserMatchClass> {
472 let MIOperandInfo = (ops ptr_rc);
475 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
476 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
477 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
478 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
479 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
480 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
481 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
482 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
484 class X86MemOffsOperand<Operand immOperand, string printMethod,
485 AsmOperandClass parserMatchClass>
486 : X86MemOperand<printMethod, parserMatchClass> {
487 let MIOperandInfo = (ops immOperand, i8imm);
490 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
491 X86MemOffs16_8AsmOperand>;
492 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
493 X86MemOffs16_16AsmOperand>;
494 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
495 X86MemOffs16_32AsmOperand>;
496 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
497 X86MemOffs32_8AsmOperand>;
498 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
499 X86MemOffs32_16AsmOperand>;
500 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
501 X86MemOffs32_32AsmOperand>;
502 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
503 X86MemOffs32_64AsmOperand>;
504 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
505 X86MemOffs64_8AsmOperand>;
506 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
507 X86MemOffs64_16AsmOperand>;
508 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
509 X86MemOffs64_32AsmOperand>;
510 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
511 X86MemOffs64_64AsmOperand>;
513 def SSECC : Operand<i8> {
514 let PrintMethod = "printSSECC";
515 let OperandType = "OPERAND_IMMEDIATE";
518 def i8immZExt3 : ImmLeaf<i8, [{
519 return Imm >= 0 && Imm < 8;
522 def AVXCC : Operand<i8> {
523 let PrintMethod = "printAVXCC";
524 let OperandType = "OPERAND_IMMEDIATE";
527 def i8immZExt5 : ImmLeaf<i8, [{
528 return Imm >= 0 && Imm < 32;
530 // AVX-512 uses a 32-bit immediate in their intrinsics
531 def i32immZExt5 : ImmLeaf<i32, [{
532 return Imm >= 0 && Imm < 32;
535 class ImmSExtAsmOperandClass : AsmOperandClass {
536 let SuperClasses = [ImmAsmOperand];
537 let RenderMethod = "addImmOperands";
540 def X86GR32orGR64AsmOperand : AsmOperandClass {
541 let Name = "GR32orGR64";
544 def GR32orGR64 : RegisterOperand<GR32> {
545 let ParserMatchClass = X86GR32orGR64AsmOperand;
548 def AVX512RC : Operand<i32> {
549 let PrintMethod = "printRoundingControl";
550 let OperandType = "OPERAND_IMMEDIATE";
553 // Sign-extended immediate classes. We don't need to define the full lattice
554 // here because there is no instruction with an ambiguity between ImmSExti64i32
557 // The strange ranges come from the fact that the assembler always works with
558 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
559 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
562 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
563 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
564 let Name = "ImmSExti64i32";
567 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
568 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
569 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
570 let Name = "ImmSExti16i8";
571 let SuperClasses = [ImmSExti64i32AsmOperand];
574 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
575 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
576 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
577 let Name = "ImmSExti32i8";
581 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
582 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
583 let Name = "ImmSExti64i8";
584 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
585 ImmSExti64i32AsmOperand];
588 // A couple of more descriptive operand definitions.
589 // 16-bits but only 8 bits are significant.
590 def i16i8imm : Operand<i16> {
591 let ParserMatchClass = ImmSExti16i8AsmOperand;
592 let OperandType = "OPERAND_IMMEDIATE";
594 // 32-bits but only 8 bits are significant.
595 def i32i8imm : Operand<i32> {
596 let ParserMatchClass = ImmSExti32i8AsmOperand;
597 let OperandType = "OPERAND_IMMEDIATE";
600 // 64-bits but only 32 bits are significant.
601 def i64i32imm : Operand<i64> {
602 let ParserMatchClass = ImmSExti64i32AsmOperand;
603 let OperandType = "OPERAND_IMMEDIATE";
606 // 64-bits but only 32 bits are significant, and those bits are treated as being
608 def i64i32imm_pcrel : Operand<i64> {
609 let PrintMethod = "printPCRelImm";
610 let ParserMatchClass = X86AbsMemAsmOperand;
611 let OperandType = "OPERAND_PCREL";
614 // 64-bits but only 8 bits are significant.
615 def i64i8imm : Operand<i64> {
616 let ParserMatchClass = ImmSExti64i8AsmOperand;
617 let OperandType = "OPERAND_IMMEDIATE";
620 def lea64_32mem : Operand<i32> {
621 let PrintMethod = "printi32mem";
622 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
623 let ParserMatchClass = X86MemAsmOperand;
626 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
627 def lea64mem : Operand<i64> {
628 let PrintMethod = "printi64mem";
629 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
630 let ParserMatchClass = X86MemAsmOperand;
634 //===----------------------------------------------------------------------===//
635 // X86 Complex Pattern Definitions.
638 // Define X86 specific addressing mode.
639 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
640 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
641 [add, sub, mul, X86mul_imm, shl, or, frameindex],
643 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
644 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
645 [add, sub, mul, X86mul_imm, shl, or,
646 frameindex, X86WrapperRIP],
649 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
650 [tglobaltlsaddr], []>;
652 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
653 [tglobaltlsaddr], []>;
655 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
656 [add, sub, mul, X86mul_imm, shl, or, frameindex,
659 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
660 [tglobaltlsaddr], []>;
662 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
663 [tglobaltlsaddr], []>;
665 //===----------------------------------------------------------------------===//
666 // X86 Instruction Predicate Definitions.
667 def HasCMov : Predicate<"Subtarget->hasCMov()">;
668 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
670 def HasMMX : Predicate<"Subtarget->hasMMX()">;
671 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
672 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
673 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
674 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
675 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
676 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
677 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
678 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
679 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
680 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
681 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
682 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
683 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
684 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
685 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
686 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
687 def HasAVX : Predicate<"Subtarget->hasAVX()">;
688 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
689 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
690 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
691 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
692 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
693 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
694 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
695 def HasCDI : Predicate<"Subtarget->hasCDI()">;
696 def HasPFI : Predicate<"Subtarget->hasPFI()">;
697 def HasERI : Predicate<"Subtarget->hasERI()">;
698 def HasDQI : Predicate<"Subtarget->hasDQI()">;
699 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
700 def HasBWI : Predicate<"Subtarget->hasBWI()">;
701 def HasVLX : Predicate<"Subtarget->hasVLX()">,
702 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
703 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
705 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
706 def HasAES : Predicate<"Subtarget->hasAES()">;
707 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
708 def HasFMA : Predicate<"Subtarget->hasFMA()">;
709 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
710 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
711 def HasXOP : Predicate<"Subtarget->hasXOP()">;
712 def HasTBM : Predicate<"Subtarget->hasTBM()">;
713 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
714 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
715 def HasF16C : Predicate<"Subtarget->hasF16C()">;
716 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
717 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
718 def HasBMI : Predicate<"Subtarget->hasBMI()">;
719 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
720 def HasRTM : Predicate<"Subtarget->hasRTM()">;
721 def HasHLE : Predicate<"Subtarget->hasHLE()">;
722 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
723 def HasADX : Predicate<"Subtarget->hasADX()">;
724 def HasSHA : Predicate<"Subtarget->hasSHA()">;
725 def HasSGX : Predicate<"Subtarget->hasSGX()">;
726 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
727 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
728 def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
729 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
730 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
731 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
732 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
733 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
734 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
735 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
736 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
737 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
738 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
739 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
740 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
741 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
742 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
743 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
744 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
745 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
746 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
747 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
748 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
749 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
750 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
751 "TM.getCodeModel() != CodeModel::Kernel">;
752 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
753 "TM.getCodeModel() == CodeModel::Kernel">;
754 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
755 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
756 def OptForSize : Predicate<"OptForSize">;
757 def OptForSpeed : Predicate<"!OptForSize">;
758 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
759 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
760 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
761 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
762 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
764 //===----------------------------------------------------------------------===//
765 // X86 Instruction Format Definitions.
768 include "X86InstrFormats.td"
770 //===----------------------------------------------------------------------===//
771 // Pattern fragments.
774 // X86 specific condition code. These correspond to CondCode in
775 // X86InstrInfo.h. They must be kept in synch.
776 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
777 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
778 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
779 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
780 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
781 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
782 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
783 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
784 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
785 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
786 def X86_COND_NO : PatLeaf<(i8 10)>;
787 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
788 def X86_COND_NS : PatLeaf<(i8 12)>;
789 def X86_COND_O : PatLeaf<(i8 13)>;
790 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
791 def X86_COND_S : PatLeaf<(i8 15)>;
793 // Predicate used to help when pattern matching LZCNT/TZCNT.
794 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
795 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
798 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
799 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
800 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
801 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
804 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
807 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
809 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
811 def i64immZExt32SExt8 : ImmLeaf<i64, [{
812 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
815 // Helper fragments for loads.
816 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
817 // known to be 32-bit aligned or better. Ditto for i8 to i16.
818 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
819 LoadSDNode *LD = cast<LoadSDNode>(N);
820 ISD::LoadExtType ExtType = LD->getExtensionType();
821 if (ExtType == ISD::NON_EXTLOAD)
823 if (ExtType == ISD::EXTLOAD)
824 return LD->getAlignment() >= 2 && !LD->isVolatile();
828 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
829 LoadSDNode *LD = cast<LoadSDNode>(N);
830 ISD::LoadExtType ExtType = LD->getExtensionType();
831 if (ExtType == ISD::EXTLOAD)
832 return LD->getAlignment() >= 2 && !LD->isVolatile();
836 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
837 LoadSDNode *LD = cast<LoadSDNode>(N);
838 ISD::LoadExtType ExtType = LD->getExtensionType();
839 if (ExtType == ISD::NON_EXTLOAD)
841 if (ExtType == ISD::EXTLOAD)
842 return LD->getAlignment() >= 4 && !LD->isVolatile();
846 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
847 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
848 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
849 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
850 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
852 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
853 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
854 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
855 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
856 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
857 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
859 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
860 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
861 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
862 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
863 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
864 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
865 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
866 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
867 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
868 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
870 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
871 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
872 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
873 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
874 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
875 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
876 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
877 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
878 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
879 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
882 // An 'and' node with a single use.
883 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
884 return N->hasOneUse();
886 // An 'srl' node with a single use.
887 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
888 return N->hasOneUse();
890 // An 'trunc' node with a single use.
891 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
892 return N->hasOneUse();
895 //===----------------------------------------------------------------------===//
900 let hasSideEffects = 0, SchedRW = [WriteZero] in {
901 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
902 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
903 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
904 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
905 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
909 // Constructing a stack frame.
910 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
911 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
913 let SchedRW = [WriteALU] in {
914 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
915 def LEAVE : I<0xC9, RawFrm,
916 (outs), (ins), "leave", [], IIC_LEAVE>,
917 Requires<[Not64BitMode]>;
919 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
920 def LEAVE64 : I<0xC9, RawFrm,
921 (outs), (ins), "leave", [], IIC_LEAVE>,
922 Requires<[In64BitMode]>;
925 //===----------------------------------------------------------------------===//
926 // Miscellaneous Instructions.
929 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
930 let mayLoad = 1, SchedRW = [WriteLoad] in {
931 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
932 IIC_POP_REG16>, OpSize16;
933 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
934 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
935 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
936 IIC_POP_REG>, OpSize16;
937 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
938 IIC_POP_MEM>, OpSize16;
939 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
940 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
941 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
942 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
943 } // mayLoad, SchedRW
945 let mayStore = 1, SchedRW = [WriteStore] in {
946 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
947 IIC_PUSH_REG>, OpSize16;
948 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
949 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
950 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
951 IIC_PUSH_REG>, OpSize16;
952 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
953 IIC_PUSH_MEM>, OpSize16;
954 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
955 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
956 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
957 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
959 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
960 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
961 Requires<[Not64BitMode]>;
962 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
963 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
964 Requires<[Not64BitMode]>;
965 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
966 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
967 Requires<[Not64BitMode]>;
968 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
969 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
970 Requires<[Not64BitMode]>;
971 } // mayStore, SchedRW
974 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
975 SchedRW = [WriteLoad] in {
976 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
978 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
979 OpSize32, Requires<[Not64BitMode]>;
982 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
983 SchedRW = [WriteStore] in {
984 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
986 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
987 OpSize32, Requires<[Not64BitMode]>;
990 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
991 let mayLoad = 1, SchedRW = [WriteLoad] in {
992 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
993 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
994 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
995 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
996 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
997 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
998 } // mayLoad, SchedRW
999 let mayStore = 1, SchedRW = [WriteStore] in {
1000 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1001 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1002 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1003 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1004 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1005 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1006 } // mayStore, SchedRW
1009 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1010 SchedRW = [WriteStore] in {
1011 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1012 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1013 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1014 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1015 Requires<[In64BitMode]>;
1016 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1017 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1018 Requires<[In64BitMode]>;
1021 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1022 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1023 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1024 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1025 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1026 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1028 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1029 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1030 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1031 OpSize32, Requires<[Not64BitMode]>;
1032 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1033 OpSize16, Requires<[Not64BitMode]>;
1035 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1036 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1037 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1038 OpSize32, Requires<[Not64BitMode]>;
1039 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1040 OpSize16, Requires<[Not64BitMode]>;
1043 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1044 // GR32 = bswap GR32
1045 def BSWAP32r : I<0xC8, AddRegFrm,
1046 (outs GR32:$dst), (ins GR32:$src),
1048 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1050 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1052 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1053 } // Constraints = "$src = $dst", SchedRW
1055 // Bit scan instructions.
1056 let Defs = [EFLAGS] in {
1057 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1058 "bsf{w}\t{$src, $dst|$dst, $src}",
1059 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1060 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1061 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1062 "bsf{w}\t{$src, $dst|$dst, $src}",
1063 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1064 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1065 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1066 "bsf{l}\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1068 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1069 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1070 "bsf{l}\t{$src, $dst|$dst, $src}",
1071 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1072 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1073 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1074 "bsf{q}\t{$src, $dst|$dst, $src}",
1075 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1076 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1077 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1078 "bsf{q}\t{$src, $dst|$dst, $src}",
1079 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1080 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1082 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1083 "bsr{w}\t{$src, $dst|$dst, $src}",
1084 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1085 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1086 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1087 "bsr{w}\t{$src, $dst|$dst, $src}",
1088 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1089 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1090 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1091 "bsr{l}\t{$src, $dst|$dst, $src}",
1092 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1093 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1094 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1095 "bsr{l}\t{$src, $dst|$dst, $src}",
1096 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1097 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1098 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1099 "bsr{q}\t{$src, $dst|$dst, $src}",
1100 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1101 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1102 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1103 "bsr{q}\t{$src, $dst|$dst, $src}",
1104 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1105 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1106 } // Defs = [EFLAGS]
1108 let SchedRW = [WriteMicrocoded] in {
1109 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1110 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1111 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1112 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1113 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1114 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1115 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1116 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1117 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1118 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1121 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1122 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1123 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1124 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1125 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1126 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1127 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1128 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1129 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1130 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1131 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1132 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1133 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1135 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1136 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1137 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1138 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1139 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1140 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1141 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1142 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1143 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1144 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1145 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1146 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1147 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1149 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1150 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1151 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1152 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1153 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1154 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1155 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1156 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1157 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1158 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1162 //===----------------------------------------------------------------------===//
1163 // Move Instructions.
1165 let SchedRW = [WriteMove] in {
1166 let hasSideEffects = 0 in {
1167 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1168 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1169 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1170 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1171 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1172 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1173 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1174 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1177 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1178 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1179 "mov{b}\t{$src, $dst|$dst, $src}",
1180 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1181 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1182 "mov{w}\t{$src, $dst|$dst, $src}",
1183 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1184 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1185 "mov{l}\t{$src, $dst|$dst, $src}",
1186 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1187 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1188 "mov{q}\t{$src, $dst|$dst, $src}",
1189 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1191 let isReMaterializable = 1 in {
1192 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1193 "movabs{q}\t{$src, $dst|$dst, $src}",
1194 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1197 // Longer forms that use a ModR/M byte. Needed for disassembler
1198 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1199 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1200 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1201 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1202 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1203 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1204 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1208 let SchedRW = [WriteStore] in {
1209 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1210 "mov{b}\t{$src, $dst|$dst, $src}",
1211 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1212 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1213 "mov{w}\t{$src, $dst|$dst, $src}",
1214 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1215 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1216 "mov{l}\t{$src, $dst|$dst, $src}",
1217 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1218 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1219 "mov{q}\t{$src, $dst|$dst, $src}",
1220 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1223 let hasSideEffects = 0 in {
1225 /// Memory offset versions of moves. The immediate is an address mode sized
1226 /// offset from the segment base.
1227 let SchedRW = [WriteALU] in {
1228 let mayLoad = 1 in {
1230 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1231 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1234 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1235 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1238 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1239 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1242 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1243 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1247 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1248 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1250 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1251 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1254 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1255 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1258 let mayStore = 1 in {
1260 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1261 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1263 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1264 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1267 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1268 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1271 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1272 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1276 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1277 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1279 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1280 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1283 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1284 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1289 // These forms all have full 64-bit absolute addresses in their instructions
1290 // and use the movabs mnemonic to indicate this specific form.
1291 let mayLoad = 1 in {
1293 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1294 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1296 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1297 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1299 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1300 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1303 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1304 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1307 let mayStore = 1 in {
1309 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1310 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1312 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1313 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1315 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1316 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1319 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1320 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1322 } // hasSideEffects = 0
1324 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1325 SchedRW = [WriteMove] in {
1326 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1327 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1328 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1329 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1330 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1331 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1332 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1333 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1336 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1337 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1338 "mov{b}\t{$src, $dst|$dst, $src}",
1339 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1340 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1341 "mov{w}\t{$src, $dst|$dst, $src}",
1342 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1343 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1344 "mov{l}\t{$src, $dst|$dst, $src}",
1345 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1346 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1347 "mov{q}\t{$src, $dst|$dst, $src}",
1348 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1351 let SchedRW = [WriteStore] in {
1352 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1353 "mov{b}\t{$src, $dst|$dst, $src}",
1354 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1355 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1356 "mov{w}\t{$src, $dst|$dst, $src}",
1357 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1358 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1359 "mov{l}\t{$src, $dst|$dst, $src}",
1360 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1361 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1362 "mov{q}\t{$src, $dst|$dst, $src}",
1363 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1366 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1367 // that they can be used for copying and storing h registers, which can't be
1368 // encoded when a REX prefix is present.
1369 let isCodeGenOnly = 1 in {
1370 let hasSideEffects = 0 in
1371 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1372 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1373 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1375 let mayStore = 1, hasSideEffects = 0 in
1376 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1377 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1378 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1379 IIC_MOV_MEM>, Sched<[WriteStore]>;
1380 let mayLoad = 1, hasSideEffects = 0,
1381 canFoldAsLoad = 1, isReMaterializable = 1 in
1382 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1383 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1384 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1385 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1389 // Condition code ops, incl. set if equal/not equal/...
1390 let SchedRW = [WriteALU] in {
1391 let Defs = [EFLAGS], Uses = [AH] in
1392 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1393 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1394 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1395 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1396 IIC_AHF>; // AH = flags
1399 //===----------------------------------------------------------------------===//
1400 // Bit tests instructions: BT, BTS, BTR, BTC.
1402 let Defs = [EFLAGS] in {
1403 let SchedRW = [WriteALU] in {
1404 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1405 "bt{w}\t{$src2, $src1|$src1, $src2}",
1406 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1408 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1409 "bt{l}\t{$src2, $src1|$src1, $src2}",
1410 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1412 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1413 "bt{q}\t{$src2, $src1|$src1, $src2}",
1414 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1417 // Unlike with the register+register form, the memory+register form of the
1418 // bt instruction does not ignore the high bits of the index. From ISel's
1419 // perspective, this is pretty bizarre. Make these instructions disassembly
1422 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1423 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1424 "bt{w}\t{$src2, $src1|$src1, $src2}",
1425 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1426 // (implicit EFLAGS)]
1428 >, OpSize16, TB, Requires<[FastBTMem]>;
1429 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1430 "bt{l}\t{$src2, $src1|$src1, $src2}",
1431 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1432 // (implicit EFLAGS)]
1434 >, OpSize32, TB, Requires<[FastBTMem]>;
1435 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1436 "bt{q}\t{$src2, $src1|$src1, $src2}",
1437 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1438 // (implicit EFLAGS)]
1443 let SchedRW = [WriteALU] in {
1444 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1445 "bt{w}\t{$src2, $src1|$src1, $src2}",
1446 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1447 IIC_BT_RI>, OpSize16, TB;
1448 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1449 "bt{l}\t{$src2, $src1|$src1, $src2}",
1450 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1451 IIC_BT_RI>, OpSize32, TB;
1452 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1453 "bt{q}\t{$src2, $src1|$src1, $src2}",
1454 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1458 // Note that these instructions don't need FastBTMem because that
1459 // only applies when the other operand is in a register. When it's
1460 // an immediate, bt is still fast.
1461 let SchedRW = [WriteALU] in {
1462 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1463 "bt{w}\t{$src2, $src1|$src1, $src2}",
1464 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1465 ], IIC_BT_MI>, OpSize16, TB;
1466 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1467 "bt{l}\t{$src2, $src1|$src1, $src2}",
1468 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1469 ], IIC_BT_MI>, OpSize32, TB;
1470 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1471 "bt{q}\t{$src2, $src1|$src1, $src2}",
1472 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1473 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1476 let hasSideEffects = 0 in {
1477 let SchedRW = [WriteALU] in {
1478 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1479 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1481 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1482 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1484 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1485 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1488 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1489 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1490 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1492 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1493 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1495 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1496 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1499 let SchedRW = [WriteALU] in {
1500 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1501 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1503 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1504 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1506 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1507 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1510 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1511 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1512 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1514 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1515 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1517 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1518 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1521 let SchedRW = [WriteALU] in {
1522 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1523 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1525 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1526 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1528 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1529 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1532 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1533 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1534 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1536 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1537 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1539 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1540 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1543 let SchedRW = [WriteALU] in {
1544 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1545 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1547 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1548 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1550 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1551 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1554 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1555 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1556 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1558 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1559 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1561 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1562 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1565 let SchedRW = [WriteALU] in {
1566 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1567 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1569 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1570 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1572 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1573 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1576 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1577 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1578 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1580 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1581 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1583 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1584 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1587 let SchedRW = [WriteALU] in {
1588 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1589 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1591 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1592 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1594 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1595 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1598 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1599 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1600 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1602 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1603 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1605 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1606 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1608 } // hasSideEffects = 0
1609 } // Defs = [EFLAGS]
1612 //===----------------------------------------------------------------------===//
1616 // Atomic swap. These are just normal xchg instructions. But since a memory
1617 // operand is referenced, the atomicity is ensured.
1618 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1619 InstrItinClass itin> {
1620 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1621 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1622 (ins GR8:$val, i8mem:$ptr),
1623 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1626 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1628 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1629 (ins GR16:$val, i16mem:$ptr),
1630 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1633 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1635 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1636 (ins GR32:$val, i32mem:$ptr),
1637 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1640 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1642 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1643 (ins GR64:$val, i64mem:$ptr),
1644 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1647 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1652 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1654 // Swap between registers.
1655 let SchedRW = [WriteALU] in {
1656 let Constraints = "$val = $dst" in {
1657 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1658 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1659 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1660 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1662 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1663 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1665 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1666 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1669 // Swap between EAX and other registers.
1670 let Uses = [AX], Defs = [AX] in
1671 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1672 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1673 let Uses = [EAX], Defs = [EAX] in
1674 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1675 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1676 OpSize32, Requires<[Not64BitMode]>;
1677 let Uses = [EAX], Defs = [EAX] in
1678 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1679 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1680 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1681 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1682 OpSize32, Requires<[In64BitMode]>;
1683 let Uses = [RAX], Defs = [RAX] in
1684 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1685 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1688 let SchedRW = [WriteALU] in {
1689 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1690 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1691 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1692 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1694 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1695 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1697 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1698 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1701 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1702 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1703 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1704 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1705 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1707 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1708 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1710 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1711 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1715 let SchedRW = [WriteALU] in {
1716 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1717 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1718 IIC_CMPXCHG_REG8>, TB;
1719 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1720 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1721 IIC_CMPXCHG_REG>, TB, OpSize16;
1722 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1723 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1724 IIC_CMPXCHG_REG>, TB, OpSize32;
1725 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1726 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1727 IIC_CMPXCHG_REG>, TB;
1730 let SchedRW = [WriteALULd, WriteRMW] in {
1731 let mayLoad = 1, mayStore = 1 in {
1732 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1733 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1734 IIC_CMPXCHG_MEM8>, TB;
1735 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1736 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1737 IIC_CMPXCHG_MEM>, TB, OpSize16;
1738 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1739 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1740 IIC_CMPXCHG_MEM>, TB, OpSize32;
1741 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1742 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1743 IIC_CMPXCHG_MEM>, TB;
1746 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1747 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1748 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1750 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1751 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1752 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1753 TB, Requires<[HasCmpxchg16b]>;
1757 // Lock instruction prefix
1758 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1760 // Rex64 instruction prefix
1761 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1762 Requires<[In64BitMode]>;
1764 // Data16 instruction prefix
1765 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1767 // Repeat string operation instruction prefixes
1768 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1769 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1770 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1771 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1772 // Repeat while not equal (used with CMPS and SCAS)
1773 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1777 // String manipulation instructions
1778 let SchedRW = [WriteMicrocoded] in {
1779 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1780 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1781 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1782 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1783 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1784 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1785 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1786 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1787 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1788 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1789 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1790 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1791 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1794 let SchedRW = [WriteSystem] in {
1795 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1796 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1797 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1798 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1799 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1800 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1801 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1802 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1805 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1806 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1807 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1808 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1809 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1810 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1811 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1812 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1816 // Flag instructions
1817 let SchedRW = [WriteALU] in {
1818 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1819 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1820 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1821 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1822 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1823 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1824 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1826 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1829 // Table lookup instructions
1830 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1833 let SchedRW = [WriteMicrocoded] in {
1834 // ASCII Adjust After Addition
1835 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1836 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1837 Requires<[Not64BitMode]>;
1839 // ASCII Adjust AX Before Division
1840 // sets AL, AH and EFLAGS and uses AL and AH
1841 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1842 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1844 // ASCII Adjust AX After Multiply
1845 // sets AL, AH and EFLAGS and uses AL
1846 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1847 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1849 // ASCII Adjust AL After Subtraction - sets
1850 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1851 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1852 Requires<[Not64BitMode]>;
1854 // Decimal Adjust AL after Addition
1855 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1856 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1857 Requires<[Not64BitMode]>;
1859 // Decimal Adjust AL after Subtraction
1860 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1861 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1862 Requires<[Not64BitMode]>;
1865 let SchedRW = [WriteSystem] in {
1866 // Check Array Index Against Bounds
1867 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1868 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1869 Requires<[Not64BitMode]>;
1870 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1871 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1872 Requires<[Not64BitMode]>;
1874 // Adjust RPL Field of Segment Selector
1875 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1876 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1877 Requires<[Not64BitMode]>;
1878 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1879 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1880 Requires<[Not64BitMode]>;
1883 //===----------------------------------------------------------------------===//
1884 // MOVBE Instructions
1886 let Predicates = [HasMOVBE] in {
1887 let SchedRW = [WriteALULd] in {
1888 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1889 "movbe{w}\t{$src, $dst|$dst, $src}",
1890 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1892 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1893 "movbe{l}\t{$src, $dst|$dst, $src}",
1894 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1896 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1897 "movbe{q}\t{$src, $dst|$dst, $src}",
1898 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1901 let SchedRW = [WriteStore] in {
1902 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1903 "movbe{w}\t{$src, $dst|$dst, $src}",
1904 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1906 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1907 "movbe{l}\t{$src, $dst|$dst, $src}",
1908 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1910 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1911 "movbe{q}\t{$src, $dst|$dst, $src}",
1912 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1917 //===----------------------------------------------------------------------===//
1918 // RDRAND Instruction
1920 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1921 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1923 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1924 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1926 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1927 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1929 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1932 //===----------------------------------------------------------------------===//
1933 // RDSEED Instruction
1935 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1936 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1938 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1939 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1941 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1942 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1944 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1947 //===----------------------------------------------------------------------===//
1948 // LZCNT Instruction
1950 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1951 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1952 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1953 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1955 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1956 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1957 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1958 (implicit EFLAGS)]>, XS, OpSize16;
1960 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1961 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1962 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1964 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1965 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1966 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1967 (implicit EFLAGS)]>, XS, OpSize32;
1969 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1970 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1971 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1973 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1974 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1975 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1976 (implicit EFLAGS)]>, XS;
1979 let Predicates = [HasLZCNT] in {
1980 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
1981 (X86cmp GR16:$src, (i16 0))),
1982 (LZCNT16rr GR16:$src)>;
1983 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
1984 (X86cmp GR32:$src, (i32 0))),
1985 (LZCNT32rr GR32:$src)>;
1986 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
1987 (X86cmp GR64:$src, (i64 0))),
1988 (LZCNT64rr GR64:$src)>;
1989 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
1990 (X86cmp GR16:$src, (i16 0))),
1991 (LZCNT16rr GR16:$src)>;
1992 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
1993 (X86cmp GR32:$src, (i32 0))),
1994 (LZCNT32rr GR32:$src)>;
1995 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
1996 (X86cmp GR64:$src, (i64 0))),
1997 (LZCNT64rr GR64:$src)>;
1999 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2000 (X86cmp (loadi16 addr:$src), (i16 0))),
2001 (LZCNT16rm addr:$src)>;
2002 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2003 (X86cmp (loadi32 addr:$src), (i32 0))),
2004 (LZCNT32rm addr:$src)>;
2005 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2006 (X86cmp (loadi64 addr:$src), (i64 0))),
2007 (LZCNT64rm addr:$src)>;
2008 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2009 (X86cmp (loadi16 addr:$src), (i16 0))),
2010 (LZCNT16rm addr:$src)>;
2011 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2012 (X86cmp (loadi32 addr:$src), (i32 0))),
2013 (LZCNT32rm addr:$src)>;
2014 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2015 (X86cmp (loadi64 addr:$src), (i64 0))),
2016 (LZCNT64rm addr:$src)>;
2019 //===----------------------------------------------------------------------===//
2022 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2023 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2024 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2025 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2027 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2028 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2029 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2030 (implicit EFLAGS)]>, XS, OpSize16;
2032 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2033 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2034 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2036 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2037 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2038 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2039 (implicit EFLAGS)]>, XS, OpSize32;
2041 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2042 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2043 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2045 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2046 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2047 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2048 (implicit EFLAGS)]>, XS;
2051 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2052 RegisterClass RC, X86MemOperand x86memop> {
2053 let hasSideEffects = 0 in {
2054 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2055 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2058 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2059 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2064 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2065 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2066 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2067 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2068 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2069 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2070 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2073 //===----------------------------------------------------------------------===//
2074 // Pattern fragments to auto generate BMI instructions.
2075 //===----------------------------------------------------------------------===//
2077 let Predicates = [HasBMI] in {
2078 // FIXME: patterns for the load versions are not implemented
2079 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2080 (BLSR32rr GR32:$src)>;
2081 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2082 (BLSR64rr GR64:$src)>;
2084 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2085 (BLSMSK32rr GR32:$src)>;
2086 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2087 (BLSMSK64rr GR64:$src)>;
2089 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2090 (BLSI32rr GR32:$src)>;
2091 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2092 (BLSI64rr GR64:$src)>;
2095 let Predicates = [HasBMI] in {
2096 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2097 (X86cmp GR16:$src, (i16 0))),
2098 (TZCNT16rr GR16:$src)>;
2099 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2100 (X86cmp GR32:$src, (i32 0))),
2101 (TZCNT32rr GR32:$src)>;
2102 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2103 (X86cmp GR64:$src, (i64 0))),
2104 (TZCNT64rr GR64:$src)>;
2105 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2106 (X86cmp GR16:$src, (i16 0))),
2107 (TZCNT16rr GR16:$src)>;
2108 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2109 (X86cmp GR32:$src, (i32 0))),
2110 (TZCNT32rr GR32:$src)>;
2111 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2112 (X86cmp GR64:$src, (i64 0))),
2113 (TZCNT64rr GR64:$src)>;
2115 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2116 (X86cmp (loadi16 addr:$src), (i16 0))),
2117 (TZCNT16rm addr:$src)>;
2118 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2119 (X86cmp (loadi32 addr:$src), (i32 0))),
2120 (TZCNT32rm addr:$src)>;
2121 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2122 (X86cmp (loadi64 addr:$src), (i64 0))),
2123 (TZCNT64rm addr:$src)>;
2124 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2125 (X86cmp (loadi16 addr:$src), (i16 0))),
2126 (TZCNT16rm addr:$src)>;
2127 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2128 (X86cmp (loadi32 addr:$src), (i32 0))),
2129 (TZCNT32rm addr:$src)>;
2130 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2131 (X86cmp (loadi64 addr:$src), (i64 0))),
2132 (TZCNT64rm addr:$src)>;
2136 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2137 X86MemOperand x86memop, Intrinsic Int,
2139 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2140 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2141 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2143 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2144 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2145 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2146 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2149 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2150 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2151 int_x86_bmi_bextr_32, loadi32>;
2152 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2153 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2156 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2157 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2158 int_x86_bmi_bzhi_32, loadi32>;
2159 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2160 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2164 def CountTrailingOnes : SDNodeXForm<imm, [{
2165 // Count the trailing ones in the immediate.
2166 return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
2169 def BZHIMask : ImmLeaf<i64, [{
2170 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
2173 let Predicates = [HasBMI2] in {
2174 def : Pat<(and GR64:$src, BZHIMask:$mask),
2175 (BZHI64rr GR64:$src,
2176 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2177 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2179 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2180 (BZHI32rr GR32:$src,
2181 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2183 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2184 (BZHI32rm addr:$src,
2185 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2187 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2188 (BZHI64rr GR64:$src,
2189 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2191 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2192 (BZHI64rm addr:$src,
2193 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2196 let Predicates = [HasBMI] in {
2197 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2198 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2199 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2200 (BEXTR32rm addr:$src1, GR32:$src2)>;
2201 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2202 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2203 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2204 (BEXTR64rm addr:$src1, GR64:$src2)>;
2207 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2208 X86MemOperand x86memop, Intrinsic Int,
2210 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2211 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2212 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2214 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2215 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2216 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2219 let Predicates = [HasBMI2] in {
2220 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2221 int_x86_bmi_pdep_32, loadi32>, T8XD;
2222 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2223 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2224 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2225 int_x86_bmi_pext_32, loadi32>, T8XS;
2226 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2227 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2230 //===----------------------------------------------------------------------===//
2233 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2235 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2236 X86MemOperand x86memop, PatFrag ld_frag,
2237 Intrinsic Int, Operand immtype,
2238 SDPatternOperator immoperator> {
2239 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2240 !strconcat(OpcodeStr,
2241 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2242 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2244 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2245 (ins x86memop:$src1, immtype:$cntl),
2246 !strconcat(OpcodeStr,
2247 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2248 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2252 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2253 int_x86_tbm_bextri_u32, i32imm, imm>;
2254 let ImmT = Imm32S in
2255 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2256 int_x86_tbm_bextri_u64, i64i32imm,
2257 i64immSExt32>, VEX_W;
2259 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2260 RegisterClass RC, string OpcodeStr,
2261 X86MemOperand x86memop, PatFrag ld_frag> {
2262 let hasSideEffects = 0 in {
2263 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2264 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2267 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2268 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2273 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2274 Format FormReg, Format FormMem> {
2275 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2277 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2281 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2282 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2283 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2284 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2285 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2286 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2287 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2288 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2289 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2292 //===----------------------------------------------------------------------===//
2293 // Pattern fragments to auto generate TBM instructions.
2294 //===----------------------------------------------------------------------===//
2296 let Predicates = [HasTBM] in {
2297 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2298 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2299 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2300 (BEXTRI32mi addr:$src1, imm:$src2)>;
2301 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2302 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2303 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2304 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2306 // FIXME: patterns for the load versions are not implemented
2307 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2308 (BLCFILL32rr GR32:$src)>;
2309 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2310 (BLCFILL64rr GR64:$src)>;
2312 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2313 (BLCI32rr GR32:$src)>;
2314 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2315 (BLCI64rr GR64:$src)>;
2317 // Extra patterns because opt can optimize the above patterns to this.
2318 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2319 (BLCI32rr GR32:$src)>;
2320 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2321 (BLCI64rr GR64:$src)>;
2323 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2324 (BLCIC32rr GR32:$src)>;
2325 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2326 (BLCIC64rr GR64:$src)>;
2328 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2329 (BLCMSK32rr GR32:$src)>;
2330 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2331 (BLCMSK64rr GR64:$src)>;
2333 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2334 (BLCS32rr GR32:$src)>;
2335 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2336 (BLCS64rr GR64:$src)>;
2338 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2339 (BLSFILL32rr GR32:$src)>;
2340 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2341 (BLSFILL64rr GR64:$src)>;
2343 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2344 (BLSIC32rr GR32:$src)>;
2345 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2346 (BLSIC64rr GR64:$src)>;
2348 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2349 (T1MSKC32rr GR32:$src)>;
2350 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2351 (T1MSKC64rr GR64:$src)>;
2353 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2354 (TZMSK32rr GR32:$src)>;
2355 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2356 (TZMSK64rr GR64:$src)>;
2359 //===----------------------------------------------------------------------===//
2361 //===----------------------------------------------------------------------===//
2363 include "X86InstrArithmetic.td"
2364 include "X86InstrCMovSetCC.td"
2365 include "X86InstrExtension.td"
2366 include "X86InstrControl.td"
2367 include "X86InstrShiftRotate.td"
2369 // X87 Floating Point Stack.
2370 include "X86InstrFPStack.td"
2372 // SIMD support (SSE, MMX and AVX)
2373 include "X86InstrFragmentsSIMD.td"
2375 // FMA - Fused Multiply-Add support (requires FMA)
2376 include "X86InstrFMA.td"
2379 include "X86InstrXOP.td"
2381 // SSE, MMX and 3DNow! vector support.
2382 include "X86InstrSSE.td"
2383 include "X86InstrAVX512.td"
2384 include "X86InstrMMX.td"
2385 include "X86Instr3DNow.td"
2387 include "X86InstrVMX.td"
2388 include "X86InstrSVM.td"
2390 include "X86InstrTSX.td"
2391 include "X86InstrSGX.td"
2393 // System instructions.
2394 include "X86InstrSystem.td"
2396 // Compiler Pseudo Instructions and Pat Patterns
2397 include "X86InstrCompiler.td"
2399 //===----------------------------------------------------------------------===//
2400 // Assembler Mnemonic Aliases
2401 //===----------------------------------------------------------------------===//
2403 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2404 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2405 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2407 def : MnemonicAlias<"cbw", "cbtw", "att">;
2408 def : MnemonicAlias<"cwde", "cwtl", "att">;
2409 def : MnemonicAlias<"cwd", "cwtd", "att">;
2410 def : MnemonicAlias<"cdq", "cltd", "att">;
2411 def : MnemonicAlias<"cdqe", "cltq", "att">;
2412 def : MnemonicAlias<"cqo", "cqto", "att">;
2414 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2415 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2416 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2418 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2419 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2421 def : MnemonicAlias<"loopz", "loope", "att">;
2422 def : MnemonicAlias<"loopnz", "loopne", "att">;
2424 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2425 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2426 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2427 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2428 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2429 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2430 def : MnemonicAlias<"popfd", "popfl", "att">;
2432 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2433 // all modes. However: "push (addr)" and "push $42" should default to
2434 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2435 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2436 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2437 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2438 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2439 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2440 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2441 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2443 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2444 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2445 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2446 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2447 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2448 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2450 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2451 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2452 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2453 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2455 def : MnemonicAlias<"repe", "rep", "att">;
2456 def : MnemonicAlias<"repz", "rep", "att">;
2457 def : MnemonicAlias<"repnz", "repne", "att">;
2459 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2460 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2461 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2463 def : MnemonicAlias<"salb", "shlb", "att">;
2464 def : MnemonicAlias<"salw", "shlw", "att">;
2465 def : MnemonicAlias<"sall", "shll", "att">;
2466 def : MnemonicAlias<"salq", "shlq", "att">;
2468 def : MnemonicAlias<"smovb", "movsb", "att">;
2469 def : MnemonicAlias<"smovw", "movsw", "att">;
2470 def : MnemonicAlias<"smovl", "movsl", "att">;
2471 def : MnemonicAlias<"smovq", "movsq", "att">;
2473 def : MnemonicAlias<"ud2a", "ud2", "att">;
2474 def : MnemonicAlias<"verrw", "verr", "att">;
2476 // System instruction aliases.
2477 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2478 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2479 def : MnemonicAlias<"sysret", "sysretl", "att">;
2480 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2482 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2483 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2484 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2485 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2486 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2487 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2488 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2489 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2490 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2491 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2492 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2493 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2496 // Floating point stack aliases.
2497 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2498 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2499 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2500 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2501 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2502 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2503 def : MnemonicAlias<"fildq", "fildll", "att">;
2504 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2505 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2506 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2507 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2508 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2509 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2510 def : MnemonicAlias<"fwait", "wait">;
2513 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2515 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2516 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2518 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2519 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2520 /// example "setz" -> "sete".
2521 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2523 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2524 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2525 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2526 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2527 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2528 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2529 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2530 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2531 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2532 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2534 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2535 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2536 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2537 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2540 // Aliases for set<CC>
2541 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2542 // Aliases for j<CC>
2543 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2544 // Aliases for cmov<CC>{w,l,q}
2545 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2546 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2547 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2548 // No size suffix for intel-style asm.
2549 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2552 //===----------------------------------------------------------------------===//
2553 // Assembler Instruction Aliases
2554 //===----------------------------------------------------------------------===//
2556 // aad/aam default to base 10 if no operand is specified.
2557 def : InstAlias<"aad", (AAD8i8 10)>;
2558 def : InstAlias<"aam", (AAM8i8 10)>;
2560 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2561 // Likewise for btc/btr/bts.
2562 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2563 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2564 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2565 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2566 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2567 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2568 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2569 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2572 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2573 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2574 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2575 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2577 // lods aliases. Accept the destination being omitted because it's implicit
2578 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2579 // in the destination.
2580 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2581 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2582 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2583 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2584 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2585 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2586 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2587 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2589 // stos aliases. Accept the source being omitted because it's implicit in
2590 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2592 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2593 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2594 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2595 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2596 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2597 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2598 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2599 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2601 // scas aliases. Accept the destination being omitted because it's implicit
2602 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2603 // in the destination.
2604 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2605 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2606 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2607 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2608 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2609 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2610 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2611 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2613 // div and idiv aliases for explicit A register.
2614 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2615 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2616 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2617 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2618 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2619 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2620 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2621 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2622 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2623 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2624 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2625 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2626 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2627 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2628 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2629 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2633 // Various unary fpstack operations default to operating on on ST1.
2634 // For example, "fxch" -> "fxch %st(1)"
2635 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2636 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2637 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2638 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2639 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2640 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2641 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2642 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2643 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2644 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2645 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2646 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2647 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2648 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2649 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2651 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2652 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2653 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2655 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2656 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2657 (Inst RST:$op), EmitAlias>;
2658 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2659 (Inst ST0), EmitAlias>;
2662 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2663 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2664 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2665 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2666 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2667 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2668 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2669 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2670 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2671 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2672 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2673 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2674 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2675 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2676 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2677 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2680 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2681 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2682 // solely because gas supports it.
2683 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2684 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2685 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2686 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2687 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2688 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2690 // We accept "fnstsw %eax" even though it only writes %ax.
2691 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2692 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2693 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2695 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2696 // this is compatible with what GAS does.
2697 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2698 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2699 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2700 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2701 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2702 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2703 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2704 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2706 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2707 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2708 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2709 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2710 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2711 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2714 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2715 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2716 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2717 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2718 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2719 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2720 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2722 // inb %dx -> inb %al, %dx
2723 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2724 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2725 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2726 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2727 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2728 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2731 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2732 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2733 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2734 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2735 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2736 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2737 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2738 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2739 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2741 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2742 // the move. All segment/mem forms are equivalent, this has the shortest
2744 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2745 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2747 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2748 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2750 // Match 'movq GR64, MMX' as an alias for movd.
2751 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2752 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2753 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2754 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2757 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2758 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2759 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2760 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2761 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2762 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2763 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2766 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2767 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2768 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2769 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2770 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2771 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2772 // Note: No GR32->GR64 movzx form.
2774 // outb %dx -> outb %al, %dx
2775 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2776 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2777 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2778 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2779 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2780 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2782 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2783 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2784 // errors, since its encoding is the most compact.
2785 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2787 // shld/shrd op,op -> shld op, op, CL
2788 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2789 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2790 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2791 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2792 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2793 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2795 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2796 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2797 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2798 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2799 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2800 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2802 /* FIXME: This is disabled because the asm matcher is currently incapable of
2803 * matching a fixed immediate like $1.
2804 // "shl X, $1" is an alias for "shl X".
2805 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2806 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2807 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2808 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2809 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2810 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2811 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2812 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2813 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2814 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2815 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2816 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2817 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2818 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2819 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2820 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2821 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2824 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2825 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2826 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2827 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2830 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2831 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2832 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2833 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2834 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2835 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2836 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2837 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2838 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2840 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2841 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2842 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2843 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2844 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2845 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2846 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2847 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2848 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2850 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2851 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2852 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2853 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2854 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2855 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2856 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;