1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
82 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
84 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
86 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
88 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
90 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
92 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
96 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
97 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
98 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
99 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
101 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
102 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
104 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
105 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
107 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
108 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
110 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
114 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
138 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def X86vastart_save_xmm_regs :
141 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
142 SDT_X86VASTART_SAVE_XMM_REGS,
143 [SDNPHasChain, SDNPVariadic]>;
145 def X86callseq_start :
146 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
147 [SDNPHasChain, SDNPOutFlag]>;
149 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
150 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
152 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
153 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
156 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
157 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
158 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
162 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
163 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
165 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
166 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
168 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
169 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
171 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
174 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
175 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
177 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
179 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
180 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
182 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
185 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
186 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
187 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
189 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
191 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
194 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
196 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
197 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
199 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
202 //===----------------------------------------------------------------------===//
203 // X86 Operand Definitions.
206 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
207 // the index operand of an address, to conform to x86 encoding restrictions.
208 def ptr_rc_nosp : PointerLikeRegClass<1>;
210 // *mem - Operand definitions for the funky X86 addressing mode operands.
212 def X86MemAsmOperand : AsmOperandClass {
214 let SuperClasses = [];
216 def X86AbsMemAsmOperand : AsmOperandClass {
218 let SuperClasses = [X86MemAsmOperand];
220 class X86MemOperand<string printMethod> : Operand<iPTR> {
221 let PrintMethod = printMethod;
222 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
223 let ParserMatchClass = X86MemAsmOperand;
226 def opaque32mem : X86MemOperand<"printopaquemem">;
227 def opaque48mem : X86MemOperand<"printopaquemem">;
228 def opaque80mem : X86MemOperand<"printopaquemem">;
229 def opaque512mem : X86MemOperand<"printopaquemem">;
231 def i8mem : X86MemOperand<"printi8mem">;
232 def i16mem : X86MemOperand<"printi16mem">;
233 def i32mem : X86MemOperand<"printi32mem">;
234 def i64mem : X86MemOperand<"printi64mem">;
235 def i128mem : X86MemOperand<"printi128mem">;
236 def i256mem : X86MemOperand<"printi256mem">;
237 def f32mem : X86MemOperand<"printf32mem">;
238 def f64mem : X86MemOperand<"printf64mem">;
239 def f80mem : X86MemOperand<"printf80mem">;
240 def f128mem : X86MemOperand<"printf128mem">;
241 def f256mem : X86MemOperand<"printf256mem">;
243 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
244 // plain GR64, so that it doesn't potentially require a REX prefix.
245 def i8mem_NOREX : Operand<i64> {
246 let PrintMethod = "printi8mem";
247 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
248 let ParserMatchClass = X86MemAsmOperand;
251 // Special i32mem for addresses of load folding tail calls. These are not
252 // allowed to use callee-saved registers since they must be scheduled
253 // after callee-saved register are popped.
254 def i32mem_TC : Operand<i32> {
255 let PrintMethod = "printi32mem";
256 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
260 // Special i64mem for addresses of load folding tail calls. These are not
261 // allowed to use callee-saved registers since they must be scheduled
262 // after callee-saved register are popped.
263 def i64mem_TC : Operand<i64> {
264 let PrintMethod = "printi64mem";
265 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
266 let ParserMatchClass = X86MemAsmOperand;
269 let ParserMatchClass = X86AbsMemAsmOperand,
270 PrintMethod = "print_pcrel_imm" in {
271 def i32imm_pcrel : Operand<i32>;
272 def i16imm_pcrel : Operand<i16>;
274 def offset8 : Operand<i64>;
275 def offset16 : Operand<i64>;
276 def offset32 : Operand<i64>;
277 def offset64 : Operand<i64>;
279 // Branch targets have OtherVT type and print as pc-relative values.
280 def brtarget : Operand<OtherVT>;
281 def brtarget8 : Operand<OtherVT>;
285 def SSECC : Operand<i8> {
286 let PrintMethod = "printSSECC";
289 class ImmSExtAsmOperandClass : AsmOperandClass {
290 let SuperClasses = [ImmAsmOperand];
291 let RenderMethod = "addImmOperands";
294 // Sign-extended immediate classes. We don't need to define the full lattice
295 // here because there is no instruction with an ambiguity between ImmSExti64i32
298 // The strange ranges come from the fact that the assembler always works with
299 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
300 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
303 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
304 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
305 let Name = "ImmSExti64i32";
308 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
309 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
310 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
311 let Name = "ImmSExti16i8";
312 let SuperClasses = [ImmSExti64i32AsmOperand];
315 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
316 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
317 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
318 let Name = "ImmSExti32i8";
322 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
323 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
324 let Name = "ImmSExti64i8";
325 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
326 ImmSExti64i32AsmOperand];
329 // A couple of more descriptive operand definitions.
330 // 16-bits but only 8 bits are significant.
331 def i16i8imm : Operand<i16> {
332 let ParserMatchClass = ImmSExti16i8AsmOperand;
334 // 32-bits but only 8 bits are significant.
335 def i32i8imm : Operand<i32> {
336 let ParserMatchClass = ImmSExti32i8AsmOperand;
339 // 64-bits but only 32 bits are significant.
340 def i64i32imm : Operand<i64> {
341 let ParserMatchClass = ImmSExti64i32AsmOperand;
344 // 64-bits but only 32 bits are significant, and those bits are treated as being
346 def i64i32imm_pcrel : Operand<i64> {
347 let PrintMethod = "print_pcrel_imm";
348 let ParserMatchClass = X86AbsMemAsmOperand;
351 // 64-bits but only 8 bits are significant.
352 def i64i8imm : Operand<i64> {
353 let ParserMatchClass = ImmSExti64i8AsmOperand;
356 def lea64_32mem : Operand<i32> {
357 let PrintMethod = "printi32mem";
358 let AsmOperandLowerMethod = "lower_lea64_32mem";
359 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
360 let ParserMatchClass = X86MemAsmOperand;
364 //===----------------------------------------------------------------------===//
365 // X86 Complex Pattern Definitions.
368 // Define X86 specific addressing mode.
369 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
370 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
371 [add, sub, mul, X86mul_imm, shl, or, frameindex],
373 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
374 [tglobaltlsaddr], []>;
376 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
377 [add, sub, mul, X86mul_imm, shl, or, frameindex,
380 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
381 [tglobaltlsaddr], []>;
383 //===----------------------------------------------------------------------===//
384 // X86 Instruction Predicate Definitions.
385 def HasCMov : Predicate<"Subtarget->hasCMov()">;
386 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
388 // FIXME: temporary hack to let codegen assert or generate poor code in case
389 // no AVX version of the desired intructions is present, this is better for
390 // incremental dev (without fallbacks it's easier to spot what's missing)
391 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
392 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
393 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
394 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
395 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
396 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
397 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
398 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
399 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
400 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
402 def HasAVX : Predicate<"Subtarget->hasAVX()">;
403 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
404 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
405 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
406 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
407 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
408 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
409 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
410 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
411 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
412 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
413 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
414 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
415 "TM.getCodeModel() != CodeModel::Kernel">;
416 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
417 "TM.getCodeModel() == CodeModel::Kernel">;
418 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
419 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
420 def OptForSize : Predicate<"OptForSize">;
421 def OptForSpeed : Predicate<"!OptForSize">;
422 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
423 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
424 def HasAES : Predicate<"Subtarget->hasAES()">;
426 //===----------------------------------------------------------------------===//
427 // X86 Instruction Format Definitions.
430 include "X86InstrFormats.td"
432 //===----------------------------------------------------------------------===//
433 // Pattern fragments...
436 // X86 specific condition code. These correspond to CondCode in
437 // X86InstrInfo.h. They must be kept in synch.
438 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
439 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
440 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
441 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
442 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
443 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
444 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
445 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
446 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
447 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
448 def X86_COND_NO : PatLeaf<(i8 10)>;
449 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
450 def X86_COND_NS : PatLeaf<(i8 12)>;
451 def X86_COND_O : PatLeaf<(i8 13)>;
452 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
453 def X86_COND_S : PatLeaf<(i8 15)>;
455 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
457 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
458 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
459 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
460 def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
461 def i64immZExt32 : PatLeaf<(i64 imm), [{
462 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
463 // unsignedsign extended field.
464 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
467 // Helper fragments for loads.
468 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
469 // known to be 32-bit aligned or better. Ditto for i8 to i16.
470 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
471 LoadSDNode *LD = cast<LoadSDNode>(N);
472 ISD::LoadExtType ExtType = LD->getExtensionType();
473 if (ExtType == ISD::NON_EXTLOAD)
475 if (ExtType == ISD::EXTLOAD)
476 return LD->getAlignment() >= 2 && !LD->isVolatile();
480 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
481 LoadSDNode *LD = cast<LoadSDNode>(N);
482 ISD::LoadExtType ExtType = LD->getExtensionType();
483 if (ExtType == ISD::EXTLOAD)
484 return LD->getAlignment() >= 2 && !LD->isVolatile();
488 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
489 LoadSDNode *LD = cast<LoadSDNode>(N);
490 ISD::LoadExtType ExtType = LD->getExtensionType();
491 if (ExtType == ISD::NON_EXTLOAD)
493 if (ExtType == ISD::EXTLOAD)
494 return LD->getAlignment() >= 4 && !LD->isVolatile();
498 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
499 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
500 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
501 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
502 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
504 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
505 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
506 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
507 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
508 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
509 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
511 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
512 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
513 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
514 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
515 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
516 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
517 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
518 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
519 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
520 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
522 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
523 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
524 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
525 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
526 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
527 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
528 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
529 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
530 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
531 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
534 // An 'and' node with a single use.
535 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
536 return N->hasOneUse();
538 // An 'srl' node with a single use.
539 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
540 return N->hasOneUse();
542 // An 'trunc' node with a single use.
543 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
544 return N->hasOneUse();
547 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
548 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
549 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
550 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
552 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
553 APInt Mask = APInt::getAllOnesValue(BitWidth);
554 APInt KnownZero0, KnownOne0;
555 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
556 APInt KnownZero1, KnownOne1;
557 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
558 return (~KnownZero0 & ~KnownZero1) == 0;
561 //===----------------------------------------------------------------------===//
566 let neverHasSideEffects = 1 in {
567 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
568 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
569 "nop{w}\t$zero", []>, TB, OpSize;
570 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
571 "nop{l}\t$zero", []>, TB;
575 // Constructing a stack frame.
576 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
577 "enter\t$len, $lvl", []>;
579 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
580 def LEAVE : I<0xC9, RawFrm,
581 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
583 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
584 def LEAVE64 : I<0xC9, RawFrm,
585 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
587 //===----------------------------------------------------------------------===//
588 // Miscellaneous Instructions.
591 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
593 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
595 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
596 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
598 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
600 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
601 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
603 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
604 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
605 Requires<[In32BitMode]>;
608 let mayStore = 1 in {
609 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
611 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
612 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
614 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
616 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
617 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
619 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
620 "push{l}\t$imm", []>;
621 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
622 "push{w}\t$imm", []>, OpSize;
623 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
624 "push{l}\t$imm", []>;
626 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
627 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
628 Requires<[In32BitMode]>;
633 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
635 def POP64r : I<0x58, AddRegFrm,
636 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
637 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
638 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
640 let mayStore = 1 in {
641 def PUSH64r : I<0x50, AddRegFrm,
642 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
643 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
644 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
648 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
649 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
650 "push{q}\t$imm", []>;
651 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
652 "push{q}\t$imm", []>;
653 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
654 "push{q}\t$imm", []>;
657 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
658 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
659 Requires<[In64BitMode]>;
660 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
661 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
662 Requires<[In64BitMode]>;
666 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
667 mayLoad=1, neverHasSideEffects=1 in {
668 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
669 Requires<[In32BitMode]>;
671 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
672 mayStore=1, neverHasSideEffects=1 in {
673 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
674 Requires<[In32BitMode]>;
677 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
678 def BSWAP32r : I<0xC8, AddRegFrm,
679 (outs GR32:$dst), (ins GR32:$src),
681 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
683 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
685 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
686 } // Constraints = "$src = $dst"
688 // Bit scan instructions.
689 let Defs = [EFLAGS] in {
690 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
691 "bsf{w}\t{$src, $dst|$dst, $src}",
692 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
693 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
694 "bsf{w}\t{$src, $dst|$dst, $src}",
695 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
697 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
698 "bsf{l}\t{$src, $dst|$dst, $src}",
699 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
700 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
701 "bsf{l}\t{$src, $dst|$dst, $src}",
702 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
703 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
704 "bsf{q}\t{$src, $dst|$dst, $src}",
705 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
706 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
707 "bsf{q}\t{$src, $dst|$dst, $src}",
708 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
710 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
711 "bsr{w}\t{$src, $dst|$dst, $src}",
712 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
713 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
714 "bsr{w}\t{$src, $dst|$dst, $src}",
715 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
717 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
718 "bsr{l}\t{$src, $dst|$dst, $src}",
719 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
720 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
721 "bsr{l}\t{$src, $dst|$dst, $src}",
722 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
723 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
724 "bsr{q}\t{$src, $dst|$dst, $src}",
725 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
726 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
727 "bsr{q}\t{$src, $dst|$dst, $src}",
728 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
732 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
733 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
734 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
735 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
736 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
737 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
740 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
741 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
742 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
743 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
744 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
745 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
746 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
747 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
748 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
750 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
751 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
752 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
753 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
755 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
756 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
757 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
758 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
761 //===----------------------------------------------------------------------===//
762 // Move Instructions.
765 let neverHasSideEffects = 1 in {
766 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
767 "mov{b}\t{$src, $dst|$dst, $src}", []>;
768 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
769 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
770 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
771 "mov{l}\t{$src, $dst|$dst, $src}", []>;
772 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
773 "mov{q}\t{$src, $dst|$dst, $src}", []>;
775 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
776 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
777 "mov{b}\t{$src, $dst|$dst, $src}",
778 [(set GR8:$dst, imm:$src)]>;
779 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
780 "mov{w}\t{$src, $dst|$dst, $src}",
781 [(set GR16:$dst, imm:$src)]>, OpSize;
782 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
783 "mov{l}\t{$src, $dst|$dst, $src}",
784 [(set GR32:$dst, imm:$src)]>;
785 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
786 "movabs{q}\t{$src, $dst|$dst, $src}",
787 [(set GR64:$dst, imm:$src)]>;
788 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
789 "mov{q}\t{$src, $dst|$dst, $src}",
790 [(set GR64:$dst, i64immSExt32:$src)]>;
793 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
794 "mov{b}\t{$src, $dst|$dst, $src}",
795 [(store (i8 imm:$src), addr:$dst)]>;
796 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
797 "mov{w}\t{$src, $dst|$dst, $src}",
798 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
799 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
800 "mov{l}\t{$src, $dst|$dst, $src}",
801 [(store (i32 imm:$src), addr:$dst)]>;
802 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
803 "mov{q}\t{$src, $dst|$dst, $src}",
804 [(store i64immSExt32:$src, addr:$dst)]>;
806 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
807 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
808 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
809 "mov{b}\t{$src, %al|%al, $src}", []>,
810 Requires<[In32BitMode]>;
811 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
812 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
813 Requires<[In32BitMode]>;
814 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
815 "mov{l}\t{$src, %eax|%eax, $src}", []>,
816 Requires<[In32BitMode]>;
817 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
818 "mov{b}\t{%al, $dst|$dst, %al}", []>,
819 Requires<[In32BitMode]>;
820 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
821 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
822 Requires<[In32BitMode]>;
823 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
824 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
825 Requires<[In32BitMode]>;
827 // FIXME: These definitions are utterly broken
828 // Just leave them commented out for now because they're useless outside
829 // of the large code model, and most compilers won't generate the instructions
832 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
833 "mov{q}\t{$src, %rax|%rax, $src}", []>;
834 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
835 "mov{q}\t{$src, %rax|%rax, $src}", []>;
836 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
837 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
838 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
839 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
843 let isCodeGenOnly = 1 in {
844 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
845 "mov{b}\t{$src, $dst|$dst, $src}", []>;
846 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
847 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
848 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
849 "mov{l}\t{$src, $dst|$dst, $src}", []>;
850 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
851 "mov{q}\t{$src, $dst|$dst, $src}", []>;
854 let canFoldAsLoad = 1, isReMaterializable = 1 in {
855 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
856 "mov{b}\t{$src, $dst|$dst, $src}",
857 [(set GR8:$dst, (loadi8 addr:$src))]>;
858 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
859 "mov{w}\t{$src, $dst|$dst, $src}",
860 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
861 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
862 "mov{l}\t{$src, $dst|$dst, $src}",
863 [(set GR32:$dst, (loadi32 addr:$src))]>;
864 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
865 "mov{q}\t{$src, $dst|$dst, $src}",
866 [(set GR64:$dst, (load addr:$src))]>;
869 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
870 "mov{b}\t{$src, $dst|$dst, $src}",
871 [(store GR8:$src, addr:$dst)]>;
872 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
873 "mov{w}\t{$src, $dst|$dst, $src}",
874 [(store GR16:$src, addr:$dst)]>, OpSize;
875 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
876 "mov{l}\t{$src, $dst|$dst, $src}",
877 [(store GR32:$src, addr:$dst)]>;
878 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
879 "mov{q}\t{$src, $dst|$dst, $src}",
880 [(store GR64:$src, addr:$dst)]>;
882 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
883 let isCodeGenOnly = 1 in {
884 let neverHasSideEffects = 1 in {
885 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
886 "mov{l}\t{$src, $dst|$dst, $src}", []>;
887 def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
888 "mov{q}\t{$src, $dst|$dst, $src}", []>;
891 let mayLoad = 1, canFoldAsLoad = 1, isReMaterializable = 1 in {
892 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
893 "mov{l}\t{$src, $dst|$dst, $src}",
895 def MOV64rm_TC : RI<0x8B, MRMSrcMem, (outs GR64_TC:$dst), (ins i64mem_TC:$src),
896 "mov{q}\t{$src, $dst|$dst, $src}",
900 let mayStore = 1 in {
901 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
902 "mov{l}\t{$src, $dst|$dst, $src}",
904 def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
905 "mov{q}\t{$src, $dst|$dst, $src}",
910 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
911 // that they can be used for copying and storing h registers, which can't be
912 // encoded when a REX prefix is present.
913 let isCodeGenOnly = 1 in {
914 let neverHasSideEffects = 1 in
915 def MOV8rr_NOREX : I<0x88, MRMDestReg,
916 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
917 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
919 def MOV8mr_NOREX : I<0x88, MRMDestMem,
920 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
921 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
923 canFoldAsLoad = 1, isReMaterializable = 1 in
924 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
925 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
926 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
930 // Condition code ops, incl. set if equal/not equal/...
931 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
932 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
933 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
934 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
937 //===----------------------------------------------------------------------===//
938 // Bit tests instructions: BT, BTS, BTR, BTC.
940 let Defs = [EFLAGS] in {
941 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
942 "bt{w}\t{$src2, $src1|$src1, $src2}",
943 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
944 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
945 "bt{l}\t{$src2, $src1|$src1, $src2}",
946 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
947 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
948 "bt{q}\t{$src2, $src1|$src1, $src2}",
949 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
951 // Unlike with the register+register form, the memory+register form of the
952 // bt instruction does not ignore the high bits of the index. From ISel's
953 // perspective, this is pretty bizarre. Make these instructions disassembly
956 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
957 "bt{w}\t{$src2, $src1|$src1, $src2}",
958 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
959 // (implicit EFLAGS)]
961 >, OpSize, TB, Requires<[FastBTMem]>;
962 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
963 "bt{l}\t{$src2, $src1|$src1, $src2}",
964 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
965 // (implicit EFLAGS)]
967 >, TB, Requires<[FastBTMem]>;
968 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
969 "bt{q}\t{$src2, $src1|$src1, $src2}",
970 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
971 // (implicit EFLAGS)]
975 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
976 "bt{w}\t{$src2, $src1|$src1, $src2}",
977 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
979 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
980 "bt{l}\t{$src2, $src1|$src1, $src2}",
981 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
982 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
983 "bt{q}\t{$src2, $src1|$src1, $src2}",
984 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
986 // Note that these instructions don't need FastBTMem because that
987 // only applies when the other operand is in a register. When it's
988 // an immediate, bt is still fast.
989 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
990 "bt{w}\t{$src2, $src1|$src1, $src2}",
991 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
993 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
994 "bt{l}\t{$src2, $src1|$src1, $src2}",
995 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
997 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
998 "bt{q}\t{$src2, $src1|$src1, $src2}",
999 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1000 i64immSExt8:$src2))]>, TB;
1003 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1004 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1005 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1006 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1007 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1008 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1009 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1010 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1011 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1012 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1013 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1014 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1015 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1016 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1017 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1018 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1019 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1020 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1021 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1022 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1023 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1024 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1025 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1026 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1028 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1029 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1030 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1031 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1032 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1033 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1034 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1035 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1036 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1037 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1038 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1039 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1040 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1041 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1042 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1043 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1044 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1045 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1046 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1047 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1048 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1049 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1050 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1051 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1053 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1054 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1055 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1056 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1057 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1058 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1059 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1060 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1061 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1062 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1063 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1064 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1065 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1066 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1067 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1068 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1069 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1070 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1071 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1072 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1073 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1074 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1075 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1076 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1077 } // Defs = [EFLAGS]
1080 //===----------------------------------------------------------------------===//
1085 // Atomic swap. These are just normal xchg instructions. But since a memory
1086 // operand is referenced, the atomicity is ensured.
1087 let Constraints = "$val = $dst" in {
1088 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1089 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1090 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1091 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
1092 (ins GR16:$val, i16mem:$ptr),
1093 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1094 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1096 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
1097 (ins GR32:$val, i32mem:$ptr),
1098 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1099 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1100 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1101 (ins GR64:$val,i64mem:$ptr),
1102 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1103 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1105 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1106 "xchg{b}\t{$val, $src|$src, $val}", []>;
1107 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1108 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1109 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1110 "xchg{l}\t{$val, $src|$src, $val}", []>;
1111 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1112 "xchg{q}\t{$val, $src|$src, $val}", []>;
1115 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1116 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1117 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1118 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1119 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1120 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1124 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1125 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1126 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1127 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1128 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1129 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1130 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1131 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1133 let mayLoad = 1, mayStore = 1 in {
1134 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1135 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1136 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1137 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1138 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1139 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1140 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1141 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1145 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1146 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1147 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1148 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1149 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1150 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1151 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1152 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1154 let mayLoad = 1, mayStore = 1 in {
1155 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1156 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1157 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1158 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1159 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1160 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1161 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1162 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1165 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1166 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1167 "cmpxchg8b\t$dst", []>, TB;
1169 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1170 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1171 "cmpxchg16b\t$dst", []>, TB;
1175 // Lock instruction prefix
1176 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1178 // Repeat string operation instruction prefixes
1179 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1180 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1181 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1182 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1183 // Repeat while not equal (used with CMPS and SCAS)
1184 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1188 // String manipulation instructions
1189 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1190 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1191 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1192 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1194 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1195 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1196 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1199 // Flag instructions
1200 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1201 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1202 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1203 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1204 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1205 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1206 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1208 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1210 // Table lookup instructions
1211 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1215 //===----------------------------------------------------------------------===//
1217 //===----------------------------------------------------------------------===//
1219 include "X86InstrArithmetic.td"
1220 include "X86InstrCMovSetCC.td"
1221 include "X86InstrExtension.td"
1222 include "X86InstrControl.td"
1223 include "X86InstrShiftRotate.td"
1225 // X87 Floating Point Stack.
1226 include "X86InstrFPStack.td"
1228 // SIMD support (SSE, MMX and AVX)
1229 include "X86InstrFragmentsSIMD.td"
1231 // FMA - Fused Multiply-Add support (requires FMA)
1232 include "X86InstrFMA.td"
1234 // SSE, MMX and 3DNow! vector support.
1235 include "X86InstrSSE.td"
1236 include "X86InstrMMX.td"
1237 include "X86Instr3DNow.td"
1239 include "X86InstrVMX.td"
1241 // System instructions.
1242 include "X86InstrSystem.td"
1244 // Compiler Pseudo Instructions and Pat Patterns
1245 include "X86InstrCompiler.td"