1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
251 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
253 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
254 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
255 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
257 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
259 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
260 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
262 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
265 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
266 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
268 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
269 [SDNPHasChain, SDNPOutGlue]>;
271 //===----------------------------------------------------------------------===//
272 // X86 Operand Definitions.
275 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
276 // the index operand of an address, to conform to x86 encoding restrictions.
277 def ptr_rc_nosp : PointerLikeRegClass<1>;
279 // *mem - Operand definitions for the funky X86 addressing mode operands.
281 def X86MemAsmOperand : AsmOperandClass {
282 let Name = "Mem"; let PredicateMethod = "isMem";
284 def X86Mem8AsmOperand : AsmOperandClass {
285 let Name = "Mem8"; let PredicateMethod = "isMem8";
287 def X86Mem16AsmOperand : AsmOperandClass {
288 let Name = "Mem16"; let PredicateMethod = "isMem16";
290 def X86Mem32AsmOperand : AsmOperandClass {
291 let Name = "Mem32"; let PredicateMethod = "isMem32";
293 def X86Mem64AsmOperand : AsmOperandClass {
294 let Name = "Mem64"; let PredicateMethod = "isMem64";
296 def X86Mem80AsmOperand : AsmOperandClass {
297 let Name = "Mem80"; let PredicateMethod = "isMem80";
299 def X86Mem128AsmOperand : AsmOperandClass {
300 let Name = "Mem128"; let PredicateMethod = "isMem128";
302 def X86Mem256AsmOperand : AsmOperandClass {
303 let Name = "Mem256"; let PredicateMethod = "isMem256";
305 def X86Mem512AsmOperand : AsmOperandClass {
306 let Name = "Mem512"; let PredicateMethod = "isMem512";
309 // Gather mem operands
310 def X86MemVX32Operand : AsmOperandClass {
311 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
313 def X86MemVY32Operand : AsmOperandClass {
314 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
316 def X86MemVZ32Operand : AsmOperandClass {
317 let Name = "MemVZ32"; let PredicateMethod = "isMemVZ32";
319 def X86MemVX64Operand : AsmOperandClass {
320 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
322 def X86MemVY64Operand : AsmOperandClass {
323 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
325 def X86MemVZ64Operand : AsmOperandClass {
326 let Name = "MemVZ64"; let PredicateMethod = "isMemVZ64";
329 def X86AbsMemAsmOperand : AsmOperandClass {
331 let SuperClasses = [X86MemAsmOperand];
333 class X86MemOperand<string printMethod> : Operand<iPTR> {
334 let PrintMethod = printMethod;
335 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
336 let ParserMatchClass = X86MemAsmOperand;
339 let OperandType = "OPERAND_MEMORY" in {
340 def opaque32mem : X86MemOperand<"printopaquemem">;
341 def opaque48mem : X86MemOperand<"printopaquemem">;
342 def opaque80mem : X86MemOperand<"printopaquemem">;
343 def opaque512mem : X86MemOperand<"printopaquemem">;
345 def i8mem : X86MemOperand<"printi8mem"> {
346 let ParserMatchClass = X86Mem8AsmOperand; }
347 def i16mem : X86MemOperand<"printi16mem"> {
348 let ParserMatchClass = X86Mem16AsmOperand; }
349 def i32mem : X86MemOperand<"printi32mem"> {
350 let ParserMatchClass = X86Mem32AsmOperand; }
351 def i64mem : X86MemOperand<"printi64mem"> {
352 let ParserMatchClass = X86Mem64AsmOperand; }
353 def i128mem : X86MemOperand<"printi128mem"> {
354 let ParserMatchClass = X86Mem128AsmOperand; }
355 def i256mem : X86MemOperand<"printi256mem"> {
356 let ParserMatchClass = X86Mem256AsmOperand; }
357 def i512mem : X86MemOperand<"printi512mem"> {
358 let ParserMatchClass = X86Mem512AsmOperand; }
359 def f32mem : X86MemOperand<"printf32mem"> {
360 let ParserMatchClass = X86Mem32AsmOperand; }
361 def f64mem : X86MemOperand<"printf64mem"> {
362 let ParserMatchClass = X86Mem64AsmOperand; }
363 def f80mem : X86MemOperand<"printf80mem"> {
364 let ParserMatchClass = X86Mem80AsmOperand; }
365 def f128mem : X86MemOperand<"printf128mem"> {
366 let ParserMatchClass = X86Mem128AsmOperand; }
367 def f256mem : X86MemOperand<"printf256mem">{
368 let ParserMatchClass = X86Mem256AsmOperand; }
369 def f512mem : X86MemOperand<"printf512mem">{
370 let ParserMatchClass = X86Mem512AsmOperand; }
371 def v512mem : Operand<iPTR> {
372 let PrintMethod = "printf512mem";
373 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
374 let ParserMatchClass = X86Mem512AsmOperand; }
376 // Gather mem operands
377 def vx32mem : X86MemOperand<"printi32mem">{
378 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
379 let ParserMatchClass = X86MemVX32Operand; }
380 def vy32mem : X86MemOperand<"printi32mem">{
381 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
382 let ParserMatchClass = X86MemVY32Operand; }
383 def vx64mem : X86MemOperand<"printi64mem">{
384 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
385 let ParserMatchClass = X86MemVX64Operand; }
386 def vy64mem : X86MemOperand<"printi64mem">{
387 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
388 let ParserMatchClass = X86MemVY64Operand; }
389 def vy64xmem : X86MemOperand<"printi64mem">{
390 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
391 let ParserMatchClass = X86MemVY64Operand; }
392 def vz32mem : X86MemOperand<"printi32mem">{
393 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
394 let ParserMatchClass = X86MemVZ32Operand; }
395 def vz64mem : X86MemOperand<"printi64mem">{
396 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
397 let ParserMatchClass = X86MemVZ64Operand; }
400 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
401 // plain GR64, so that it doesn't potentially require a REX prefix.
402 def i8mem_NOREX : Operand<i64> {
403 let PrintMethod = "printi8mem";
404 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
405 let ParserMatchClass = X86Mem8AsmOperand;
406 let OperandType = "OPERAND_MEMORY";
409 // GPRs available for tailcall.
410 // It represents GR32_TC, GR64_TC or GR64_TCW64.
411 def ptr_rc_tailcall : PointerLikeRegClass<2>;
413 // Special i32mem for addresses of load folding tail calls. These are not
414 // allowed to use callee-saved registers since they must be scheduled
415 // after callee-saved register are popped.
416 def i32mem_TC : Operand<i32> {
417 let PrintMethod = "printi32mem";
418 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
420 let ParserMatchClass = X86Mem32AsmOperand;
421 let OperandType = "OPERAND_MEMORY";
424 // Special i64mem for addresses of load folding tail calls. These are not
425 // allowed to use callee-saved registers since they must be scheduled
426 // after callee-saved register are popped.
427 def i64mem_TC : Operand<i64> {
428 let PrintMethod = "printi64mem";
429 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
430 ptr_rc_tailcall, i32imm, i8imm);
431 let ParserMatchClass = X86Mem64AsmOperand;
432 let OperandType = "OPERAND_MEMORY";
435 let OperandType = "OPERAND_PCREL",
436 ParserMatchClass = X86AbsMemAsmOperand,
437 PrintMethod = "printPCRelImm" in {
438 def i32imm_pcrel : Operand<i32>;
439 def i16imm_pcrel : Operand<i16>;
441 // Branch targets have OtherVT type and print as pc-relative values.
442 def brtarget : Operand<OtherVT>;
443 def brtarget8 : Operand<OtherVT>;
447 def X86MemOffs8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs64AsmOperand : AsmOperandClass {
460 let Name = "MemOffs64";
461 let SuperClasses = [X86Mem64AsmOperand];
464 let OperandType = "OPERAND_MEMORY" in {
465 def offset8 : Operand<i64> {
466 let ParserMatchClass = X86MemOffs8AsmOperand;
467 let PrintMethod = "printMemOffs8"; }
468 def offset16 : Operand<i64> {
469 let ParserMatchClass = X86MemOffs16AsmOperand;
470 let PrintMethod = "printMemOffs16"; }
471 def offset32 : Operand<i64> {
472 let ParserMatchClass = X86MemOffs32AsmOperand;
473 let PrintMethod = "printMemOffs32"; }
474 def offset64 : Operand<i64> {
475 let ParserMatchClass = X86MemOffs64AsmOperand;
476 let PrintMethod = "printMemOffs64"; }
480 def SSECC : Operand<i8> {
481 let PrintMethod = "printSSECC";
482 let OperandType = "OPERAND_IMMEDIATE";
485 def AVXCC : Operand<i8> {
486 let PrintMethod = "printAVXCC";
487 let OperandType = "OPERAND_IMMEDIATE";
490 class ImmSExtAsmOperandClass : AsmOperandClass {
491 let SuperClasses = [ImmAsmOperand];
492 let RenderMethod = "addImmOperands";
495 class ImmZExtAsmOperandClass : AsmOperandClass {
496 let SuperClasses = [ImmAsmOperand];
497 let RenderMethod = "addImmOperands";
500 // Sign-extended immediate classes. We don't need to define the full lattice
501 // here because there is no instruction with an ambiguity between ImmSExti64i32
504 // The strange ranges come from the fact that the assembler always works with
505 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
506 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
509 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
510 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
511 let Name = "ImmSExti64i32";
514 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
515 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
516 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
517 let Name = "ImmSExti16i8";
518 let SuperClasses = [ImmSExti64i32AsmOperand];
521 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
522 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
523 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
524 let Name = "ImmSExti32i8";
528 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
529 let Name = "ImmZExtu32u8";
534 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
535 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
536 let Name = "ImmSExti64i8";
537 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
538 ImmSExti64i32AsmOperand];
541 // A couple of more descriptive operand definitions.
542 // 16-bits but only 8 bits are significant.
543 def i16i8imm : Operand<i16> {
544 let ParserMatchClass = ImmSExti16i8AsmOperand;
545 let OperandType = "OPERAND_IMMEDIATE";
547 // 32-bits but only 8 bits are significant.
548 def i32i8imm : Operand<i32> {
549 let ParserMatchClass = ImmSExti32i8AsmOperand;
550 let OperandType = "OPERAND_IMMEDIATE";
552 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
553 def u32u8imm : Operand<i32> {
554 let ParserMatchClass = ImmZExtu32u8AsmOperand;
555 let OperandType = "OPERAND_IMMEDIATE";
558 // 64-bits but only 32 bits are significant.
559 def i64i32imm : Operand<i64> {
560 let ParserMatchClass = ImmSExti64i32AsmOperand;
561 let OperandType = "OPERAND_IMMEDIATE";
564 // 64-bits but only 32 bits are significant, and those bits are treated as being
566 def i64i32imm_pcrel : Operand<i64> {
567 let PrintMethod = "printPCRelImm";
568 let ParserMatchClass = X86AbsMemAsmOperand;
569 let OperandType = "OPERAND_PCREL";
572 // 64-bits but only 8 bits are significant.
573 def i64i8imm : Operand<i64> {
574 let ParserMatchClass = ImmSExti64i8AsmOperand;
575 let OperandType = "OPERAND_IMMEDIATE";
578 def lea64_32mem : Operand<i32> {
579 let PrintMethod = "printi32mem";
580 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
581 let ParserMatchClass = X86MemAsmOperand;
584 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
585 def lea64mem : Operand<i64> {
586 let PrintMethod = "printi64mem";
587 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
588 let ParserMatchClass = X86MemAsmOperand;
592 //===----------------------------------------------------------------------===//
593 // X86 Complex Pattern Definitions.
596 // Define X86 specific addressing mode.
597 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
598 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
599 [add, sub, mul, X86mul_imm, shl, or, frameindex],
601 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
602 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
603 [add, sub, mul, X86mul_imm, shl, or,
604 frameindex, X86WrapperRIP],
607 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
608 [tglobaltlsaddr], []>;
610 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
611 [tglobaltlsaddr], []>;
613 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
614 [add, sub, mul, X86mul_imm, shl, or, frameindex,
617 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
618 [tglobaltlsaddr], []>;
620 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
621 [tglobaltlsaddr], []>;
623 //===----------------------------------------------------------------------===//
624 // X86 Instruction Predicate Definitions.
625 def HasCMov : Predicate<"Subtarget->hasCMov()">;
626 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
628 def HasMMX : Predicate<"Subtarget->hasMMX()">;
629 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
630 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
631 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
632 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
633 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
634 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
635 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
636 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
637 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
638 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
639 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
640 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
641 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
642 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
643 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
644 def HasAVX : Predicate<"Subtarget->hasAVX()">;
645 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
646 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
647 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
648 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
649 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
650 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
651 def HasCDI : Predicate<"Subtarget->hasCDI()">;
652 def HasPFI : Predicate<"Subtarget->hasPFI()">;
653 def HasEMI : Predicate<"Subtarget->hasERI()">;
655 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
656 def HasAES : Predicate<"Subtarget->hasAES()">;
657 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
658 def HasFMA : Predicate<"Subtarget->hasFMA()">;
659 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
660 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
661 def HasXOP : Predicate<"Subtarget->hasXOP()">;
662 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
663 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
664 def HasF16C : Predicate<"Subtarget->hasF16C()">;
665 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
666 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
667 def HasBMI : Predicate<"Subtarget->hasBMI()">;
668 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
669 def HasRTM : Predicate<"Subtarget->hasRTM()">;
670 def HasHLE : Predicate<"Subtarget->hasHLE()">;
671 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
672 def HasADX : Predicate<"Subtarget->hasADX()">;
673 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
674 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
675 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
676 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
677 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
678 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
679 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
680 AssemblerPredicate<"!Mode64Bit", "32-bit mode">;
681 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
682 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
683 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
684 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
685 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
686 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
687 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
688 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
689 "TM.getCodeModel() != CodeModel::Kernel">;
690 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
691 "TM.getCodeModel() == CodeModel::Kernel">;
692 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
693 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
694 def OptForSize : Predicate<"OptForSize">;
695 def OptForSpeed : Predicate<"!OptForSize">;
696 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
697 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
698 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
700 //===----------------------------------------------------------------------===//
701 // X86 Instruction Format Definitions.
704 include "X86InstrFormats.td"
706 //===----------------------------------------------------------------------===//
707 // Pattern fragments.
710 // X86 specific condition code. These correspond to CondCode in
711 // X86InstrInfo.h. They must be kept in synch.
712 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
713 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
714 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
715 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
716 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
717 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
718 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
719 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
720 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
721 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
722 def X86_COND_NO : PatLeaf<(i8 10)>;
723 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
724 def X86_COND_NS : PatLeaf<(i8 12)>;
725 def X86_COND_O : PatLeaf<(i8 13)>;
726 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
727 def X86_COND_S : PatLeaf<(i8 15)>;
729 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
730 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
731 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
732 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
735 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
738 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
740 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
742 def i64immZExt32SExt8 : ImmLeaf<i64, [{
743 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
746 // Helper fragments for loads.
747 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
748 // known to be 32-bit aligned or better. Ditto for i8 to i16.
749 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
750 LoadSDNode *LD = cast<LoadSDNode>(N);
751 ISD::LoadExtType ExtType = LD->getExtensionType();
752 if (ExtType == ISD::NON_EXTLOAD)
754 if (ExtType == ISD::EXTLOAD)
755 return LD->getAlignment() >= 2 && !LD->isVolatile();
759 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
760 LoadSDNode *LD = cast<LoadSDNode>(N);
761 ISD::LoadExtType ExtType = LD->getExtensionType();
762 if (ExtType == ISD::EXTLOAD)
763 return LD->getAlignment() >= 2 && !LD->isVolatile();
767 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
768 LoadSDNode *LD = cast<LoadSDNode>(N);
769 ISD::LoadExtType ExtType = LD->getExtensionType();
770 if (ExtType == ISD::NON_EXTLOAD)
772 if (ExtType == ISD::EXTLOAD)
773 return LD->getAlignment() >= 4 && !LD->isVolatile();
777 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
778 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
779 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
780 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
781 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
783 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
784 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
785 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
786 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
787 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
788 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
790 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
791 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
792 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
793 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
794 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
795 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
796 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
797 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
798 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
799 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
801 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
802 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
803 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
804 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
805 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
806 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
807 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
808 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
809 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
810 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
813 // An 'and' node with a single use.
814 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
815 return N->hasOneUse();
817 // An 'srl' node with a single use.
818 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
819 return N->hasOneUse();
821 // An 'trunc' node with a single use.
822 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
823 return N->hasOneUse();
826 //===----------------------------------------------------------------------===//
831 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
832 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
833 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
834 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
835 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
836 "nop{l}\t$zero", [], IIC_NOP>, TB;
840 // Constructing a stack frame.
841 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
842 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
844 let SchedRW = [WriteALU] in {
845 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
846 def LEAVE : I<0xC9, RawFrm,
847 (outs), (ins), "leave", [], IIC_LEAVE>,
848 Requires<[In32BitMode]>;
850 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
851 def LEAVE64 : I<0xC9, RawFrm,
852 (outs), (ins), "leave", [], IIC_LEAVE>,
853 Requires<[In64BitMode]>;
856 //===----------------------------------------------------------------------===//
857 // Miscellaneous Instructions.
860 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
861 let mayLoad = 1, SchedRW = [WriteLoad] in {
862 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
863 IIC_POP_REG16>, OpSize;
864 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
866 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
867 IIC_POP_REG>, OpSize;
868 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
869 IIC_POP_MEM>, OpSize;
870 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
872 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
875 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
876 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
877 Requires<[In32BitMode]>;
878 } // mayLoad, SchedRW
880 let mayStore = 1, SchedRW = [WriteStore] in {
881 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
882 IIC_PUSH_REG>, OpSize;
883 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
885 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
886 IIC_PUSH_REG>, OpSize;
887 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
890 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
892 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
895 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
896 "push{l}\t$imm", [], IIC_PUSH_IMM>;
897 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
898 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
899 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
900 "push{l}\t$imm", [], IIC_PUSH_IMM>;
902 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
904 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
905 Requires<[In32BitMode]>;
907 } // mayStore, SchedRW
910 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
911 let mayLoad = 1, SchedRW = [WriteLoad] in {
912 def POP64r : I<0x58, AddRegFrm,
913 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
914 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
916 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
918 } // mayLoad, SchedRW
919 let mayStore = 1, SchedRW = [WriteStore] in {
920 def PUSH64r : I<0x50, AddRegFrm,
921 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
922 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
924 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
926 } // mayStore, SchedRW
929 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
930 SchedRW = [WriteStore] in {
931 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
932 "push{q}\t$imm", [], IIC_PUSH_IMM>;
933 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
934 "push{q}\t$imm", [], IIC_PUSH_IMM>;
935 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
936 "push{q}\t$imm", [], IIC_PUSH_IMM>;
939 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
940 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
941 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
942 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
943 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
944 Requires<[In64BitMode]>, Sched<[WriteStore]>;
946 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
947 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
948 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
949 Requires<[In32BitMode]>;
951 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
952 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
953 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
954 Requires<[In32BitMode]>;
957 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
959 def BSWAP32r : I<0xC8, AddRegFrm,
960 (outs GR32:$dst), (ins GR32:$src),
962 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
964 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
966 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
967 } // Constraints = "$src = $dst", SchedRW
969 // Bit scan instructions.
970 let Defs = [EFLAGS] in {
971 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
972 "bsf{w}\t{$src, $dst|$dst, $src}",
973 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
974 IIC_BSF>, TB, OpSize, Sched<[WriteShift]>;
975 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
976 "bsf{w}\t{$src, $dst|$dst, $src}",
977 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
978 IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>;
979 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
980 "bsf{l}\t{$src, $dst|$dst, $src}",
981 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB,
983 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
984 "bsf{l}\t{$src, $dst|$dst, $src}",
985 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
986 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
987 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
988 "bsf{q}\t{$src, $dst|$dst, $src}",
989 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
990 IIC_BSF>, TB, Sched<[WriteShift]>;
991 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
992 "bsf{q}\t{$src, $dst|$dst, $src}",
993 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
994 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
996 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
997 "bsr{w}\t{$src, $dst|$dst, $src}",
998 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
999 TB, OpSize, Sched<[WriteShift]>;
1000 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1001 "bsr{w}\t{$src, $dst|$dst, $src}",
1002 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1004 OpSize, Sched<[WriteShiftLd]>;
1005 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1006 "bsr{l}\t{$src, $dst|$dst, $src}",
1007 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB,
1008 Sched<[WriteShift]>;
1009 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1010 "bsr{l}\t{$src, $dst|$dst, $src}",
1011 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1012 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
1013 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1014 "bsr{q}\t{$src, $dst|$dst, $src}",
1015 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB,
1016 Sched<[WriteShift]>;
1017 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1018 "bsr{q}\t{$src, $dst|$dst, $src}",
1019 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1020 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
1021 } // Defs = [EFLAGS]
1023 let SchedRW = [WriteMicrocoded] in {
1024 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1025 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1026 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
1027 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1028 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
1029 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
1032 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1033 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1034 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
1035 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1036 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
1037 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1038 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
1039 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1040 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
1042 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
1043 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
1044 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
1045 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
1047 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
1048 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
1049 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
1050 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
1053 //===----------------------------------------------------------------------===//
1054 // Move Instructions.
1056 let SchedRW = [WriteMove] in {
1057 let neverHasSideEffects = 1 in {
1058 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1059 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1060 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1061 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1062 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1063 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1064 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1065 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1068 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1069 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1070 "mov{b}\t{$src, $dst|$dst, $src}",
1071 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1072 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1073 "mov{w}\t{$src, $dst|$dst, $src}",
1074 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1075 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1076 "mov{l}\t{$src, $dst|$dst, $src}",
1077 [(set GR32:$dst, imm:$src)], IIC_MOV>;
1078 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1079 "movabs{q}\t{$src, $dst|$dst, $src}",
1080 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1081 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1082 "mov{q}\t{$src, $dst|$dst, $src}",
1083 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1087 let SchedRW = [WriteStore] in {
1088 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1089 "mov{b}\t{$src, $dst|$dst, $src}",
1090 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1091 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1092 "mov{w}\t{$src, $dst|$dst, $src}",
1093 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1094 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1095 "mov{l}\t{$src, $dst|$dst, $src}",
1096 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1097 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1098 "mov{q}\t{$src, $dst|$dst, $src}",
1099 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1102 let hasSideEffects = 0 in {
1104 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1105 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1106 let SchedRW = [WriteALU] in {
1107 let mayLoad = 1 in {
1108 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1109 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1110 Requires<[In32BitMode]>;
1111 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1112 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1113 Requires<[In32BitMode]>;
1114 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1115 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1116 Requires<[In32BitMode]>;
1118 let mayStore = 1 in {
1119 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1120 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1121 Requires<[In32BitMode]>;
1122 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1123 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1124 Requires<[In32BitMode]>;
1125 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1126 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1127 Requires<[In32BitMode]>;
1131 // These forms all have full 64-bit absolute addresses in their instructions
1132 // and use the movabs mnemonic to indicate this specific form.
1133 let mayLoad = 1 in {
1134 def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset8:$src),
1135 "movabs{b}\t{$src, %al|al, $src}", []>,
1136 Requires<[In64BitMode]>;
1137 def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset16:$src),
1138 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1139 Requires<[In64BitMode]>;
1140 def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset32:$src),
1141 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1142 Requires<[In64BitMode]>;
1143 def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
1144 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1145 Requires<[In64BitMode]>;
1148 let mayStore = 1 in {
1149 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset8:$dst), (ins),
1150 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1151 Requires<[In64BitMode]>;
1152 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset16:$dst), (ins),
1153 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1154 Requires<[In64BitMode]>;
1155 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset32:$dst), (ins),
1156 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1157 Requires<[In64BitMode]>;
1158 def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
1159 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1160 Requires<[In64BitMode]>;
1162 } // hasSideEffects = 0
1164 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
1165 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1166 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1167 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1168 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1169 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1170 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1171 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1172 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1175 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1176 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1177 "mov{b}\t{$src, $dst|$dst, $src}",
1178 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1179 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1180 "mov{w}\t{$src, $dst|$dst, $src}",
1181 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1182 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1183 "mov{l}\t{$src, $dst|$dst, $src}",
1184 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1185 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1186 "mov{q}\t{$src, $dst|$dst, $src}",
1187 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1190 let SchedRW = [WriteStore] in {
1191 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1192 "mov{b}\t{$src, $dst|$dst, $src}",
1193 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1194 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1195 "mov{w}\t{$src, $dst|$dst, $src}",
1196 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1197 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1198 "mov{l}\t{$src, $dst|$dst, $src}",
1199 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1200 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1201 "mov{q}\t{$src, $dst|$dst, $src}",
1202 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1205 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1206 // that they can be used for copying and storing h registers, which can't be
1207 // encoded when a REX prefix is present.
1208 let isCodeGenOnly = 1 in {
1209 let neverHasSideEffects = 1 in
1210 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1211 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1212 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1215 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1216 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1217 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1218 IIC_MOV_MEM>, Sched<[WriteStore]>;
1219 let mayLoad = 1, neverHasSideEffects = 1,
1220 canFoldAsLoad = 1, isReMaterializable = 1 in
1221 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1222 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1223 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1224 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1228 // Condition code ops, incl. set if equal/not equal/...
1229 let SchedRW = [WriteALU] in {
1230 let Defs = [EFLAGS], Uses = [AH] in
1231 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1232 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1233 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1234 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1235 IIC_AHF>; // AH = flags
1238 //===----------------------------------------------------------------------===//
1239 // Bit tests instructions: BT, BTS, BTR, BTC.
1241 let Defs = [EFLAGS] in {
1242 let SchedRW = [WriteALU] in {
1243 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1244 "bt{w}\t{$src2, $src1|$src1, $src2}",
1245 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1247 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1248 "bt{l}\t{$src2, $src1|$src1, $src2}",
1249 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1250 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1251 "bt{q}\t{$src2, $src1|$src1, $src2}",
1252 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1255 // Unlike with the register+register form, the memory+register form of the
1256 // bt instruction does not ignore the high bits of the index. From ISel's
1257 // perspective, this is pretty bizarre. Make these instructions disassembly
1260 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1261 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1262 "bt{w}\t{$src2, $src1|$src1, $src2}",
1263 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1264 // (implicit EFLAGS)]
1266 >, OpSize, TB, Requires<[FastBTMem]>;
1267 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1268 "bt{l}\t{$src2, $src1|$src1, $src2}",
1269 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1270 // (implicit EFLAGS)]
1272 >, TB, Requires<[FastBTMem]>;
1273 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1274 "bt{q}\t{$src2, $src1|$src1, $src2}",
1275 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1276 // (implicit EFLAGS)]
1281 let SchedRW = [WriteALU] in {
1282 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1283 "bt{w}\t{$src2, $src1|$src1, $src2}",
1284 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1285 IIC_BT_RI>, OpSize, TB;
1286 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1287 "bt{l}\t{$src2, $src1|$src1, $src2}",
1288 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1290 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1291 "bt{q}\t{$src2, $src1|$src1, $src2}",
1292 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1296 // Note that these instructions don't need FastBTMem because that
1297 // only applies when the other operand is in a register. When it's
1298 // an immediate, bt is still fast.
1299 let SchedRW = [WriteALU] in {
1300 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1301 "bt{w}\t{$src2, $src1|$src1, $src2}",
1302 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1303 ], IIC_BT_MI>, OpSize, TB;
1304 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1305 "bt{l}\t{$src2, $src1|$src1, $src2}",
1306 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1308 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1309 "bt{q}\t{$src2, $src1|$src1, $src2}",
1310 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1311 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1314 let hasSideEffects = 0 in {
1315 let SchedRW = [WriteALU] in {
1316 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1317 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1319 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1320 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1321 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1322 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1325 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1326 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1327 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1329 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1330 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1331 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1332 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1335 let SchedRW = [WriteALU] in {
1336 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1337 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1339 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1340 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1341 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1342 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1345 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1346 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1347 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1349 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1350 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1351 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1352 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1355 let SchedRW = [WriteALU] in {
1356 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1357 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1359 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1360 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1361 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1362 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1365 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1366 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1367 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1369 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1370 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1371 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1372 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1375 let SchedRW = [WriteALU] in {
1376 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1377 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1379 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1380 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1381 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1382 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1385 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1386 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1387 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1389 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1390 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1391 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1392 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1395 let SchedRW = [WriteALU] in {
1396 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1397 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1399 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1400 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1401 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1402 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1405 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1406 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1407 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1409 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1410 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1411 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1412 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1415 let SchedRW = [WriteALU] in {
1416 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1417 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1419 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1420 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1421 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1422 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1425 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1426 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1427 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1429 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1430 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1431 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1432 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1434 } // hasSideEffects = 0
1435 } // Defs = [EFLAGS]
1438 //===----------------------------------------------------------------------===//
1442 // Atomic swap. These are just normal xchg instructions. But since a memory
1443 // operand is referenced, the atomicity is ensured.
1444 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1445 InstrItinClass itin> {
1446 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1447 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1448 (ins GR8:$val, i8mem:$ptr),
1449 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1452 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1454 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1455 (ins GR16:$val, i16mem:$ptr),
1456 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1459 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1461 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1462 (ins GR32:$val, i32mem:$ptr),
1463 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1466 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1468 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1469 (ins GR64:$val, i64mem:$ptr),
1470 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1473 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1478 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1480 // Swap between registers.
1481 let SchedRW = [WriteALU] in {
1482 let Constraints = "$val = $dst" in {
1483 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1484 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1485 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1486 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1487 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1488 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1489 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1490 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1493 // Swap between EAX and other registers.
1494 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1495 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1496 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1497 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1498 Requires<[In32BitMode]>;
1499 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1500 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1501 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1502 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1503 Requires<[In64BitMode]>;
1504 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1505 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1508 let SchedRW = [WriteALU] in {
1509 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1510 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1511 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1512 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1514 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1515 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1516 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1517 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1520 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1521 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1522 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1523 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1524 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1526 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1527 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1528 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1529 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1533 let SchedRW = [WriteALU] in {
1534 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1535 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1536 IIC_CMPXCHG_REG8>, TB;
1537 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1538 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1539 IIC_CMPXCHG_REG>, TB, OpSize;
1540 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1541 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1542 IIC_CMPXCHG_REG>, TB;
1543 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1544 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1545 IIC_CMPXCHG_REG>, TB;
1548 let SchedRW = [WriteALULd, WriteRMW] in {
1549 let mayLoad = 1, mayStore = 1 in {
1550 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1551 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1552 IIC_CMPXCHG_MEM8>, TB;
1553 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1554 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1555 IIC_CMPXCHG_MEM>, TB, OpSize;
1556 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1557 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1558 IIC_CMPXCHG_MEM>, TB;
1559 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1560 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1561 IIC_CMPXCHG_MEM>, TB;
1564 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1565 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1566 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1568 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1569 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1570 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1571 TB, Requires<[HasCmpxchg16b]>;
1575 // Lock instruction prefix
1576 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1578 // Rex64 instruction prefix
1579 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1581 // Data16 instruction prefix
1582 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1584 // Repeat string operation instruction prefixes
1585 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1586 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1587 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1588 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1589 // Repeat while not equal (used with CMPS and SCAS)
1590 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1594 // String manipulation instructions
1595 let SchedRW = [WriteMicrocoded] in {
1596 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1597 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1598 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1599 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1602 let SchedRW = [WriteSystem] in {
1603 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1604 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1605 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1608 // Flag instructions
1609 let SchedRW = [WriteALU] in {
1610 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1611 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1612 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1613 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1614 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1615 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1616 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1618 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1621 // Table lookup instructions
1622 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1625 let SchedRW = [WriteMicrocoded] in {
1626 // ASCII Adjust After Addition
1627 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1628 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1629 Requires<[In32BitMode]>;
1631 // ASCII Adjust AX Before Division
1632 // sets AL, AH and EFLAGS and uses AL and AH
1633 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1634 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1636 // ASCII Adjust AX After Multiply
1637 // sets AL, AH and EFLAGS and uses AL
1638 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1639 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1641 // ASCII Adjust AL After Subtraction - sets
1642 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1643 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1644 Requires<[In32BitMode]>;
1646 // Decimal Adjust AL after Addition
1647 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1648 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1649 Requires<[In32BitMode]>;
1651 // Decimal Adjust AL after Subtraction
1652 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1653 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1654 Requires<[In32BitMode]>;
1657 let SchedRW = [WriteSystem] in {
1658 // Check Array Index Against Bounds
1659 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1660 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1661 Requires<[In32BitMode]>;
1662 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1663 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1664 Requires<[In32BitMode]>;
1666 // Adjust RPL Field of Segment Selector
1667 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1668 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1669 Requires<[In32BitMode]>;
1670 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1671 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1672 Requires<[In32BitMode]>;
1675 //===----------------------------------------------------------------------===//
1676 // MOVBE Instructions
1678 let Predicates = [HasMOVBE] in {
1679 let SchedRW = [WriteALULd] in {
1680 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1681 "movbe{w}\t{$src, $dst|$dst, $src}",
1682 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1684 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1685 "movbe{l}\t{$src, $dst|$dst, $src}",
1686 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1688 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1689 "movbe{q}\t{$src, $dst|$dst, $src}",
1690 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1693 let SchedRW = [WriteStore] in {
1694 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1695 "movbe{w}\t{$src, $dst|$dst, $src}",
1696 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1698 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1699 "movbe{l}\t{$src, $dst|$dst, $src}",
1700 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1702 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1703 "movbe{q}\t{$src, $dst|$dst, $src}",
1704 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1709 //===----------------------------------------------------------------------===//
1710 // RDRAND Instruction
1712 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1713 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1715 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1716 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1718 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1719 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1721 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1724 //===----------------------------------------------------------------------===//
1725 // RDSEED Instruction
1727 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1728 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1730 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1731 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1733 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;
1734 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1736 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1739 //===----------------------------------------------------------------------===//
1740 // LZCNT Instruction
1742 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1743 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1744 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1745 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1747 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1748 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1749 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1750 (implicit EFLAGS)]>, XS, OpSize;
1752 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1753 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1754 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1755 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1756 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1757 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1758 (implicit EFLAGS)]>, XS;
1760 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1761 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1762 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1764 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1765 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1766 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1767 (implicit EFLAGS)]>, XS;
1770 //===----------------------------------------------------------------------===//
1773 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1774 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1775 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1776 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1778 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1779 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1780 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1781 (implicit EFLAGS)]>, XS, OpSize;
1783 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1784 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1785 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1786 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1787 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1788 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1789 (implicit EFLAGS)]>, XS;
1791 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1792 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1793 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1795 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1796 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1797 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1798 (implicit EFLAGS)]>, XS;
1801 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1802 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1804 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1805 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1806 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1807 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1808 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1809 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1813 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1814 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1816 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1817 X86blsr, loadi64>, VEX_W;
1818 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1819 X86blsmsk, loadi32>;
1820 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1821 X86blsmsk, loadi64>, VEX_W;
1822 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1824 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1825 X86blsi, loadi64>, VEX_W;
1828 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1829 X86MemOperand x86memop, Intrinsic Int,
1831 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1832 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1833 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1835 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1836 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1837 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1838 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1841 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1842 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1843 int_x86_bmi_bextr_32, loadi32>;
1844 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1845 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1848 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1849 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1850 int_x86_bmi_bzhi_32, loadi32>;
1851 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1852 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1855 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1856 X86MemOperand x86memop, Intrinsic Int,
1858 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1859 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1860 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1862 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1863 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1864 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1867 let Predicates = [HasBMI2] in {
1868 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1869 int_x86_bmi_pdep_32, loadi32>, T8XD;
1870 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1871 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1872 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1873 int_x86_bmi_pext_32, loadi32>, T8XS;
1874 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1875 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1878 //===----------------------------------------------------------------------===//
1880 //===----------------------------------------------------------------------===//
1882 include "X86InstrArithmetic.td"
1883 include "X86InstrCMovSetCC.td"
1884 include "X86InstrExtension.td"
1885 include "X86InstrControl.td"
1886 include "X86InstrShiftRotate.td"
1888 // X87 Floating Point Stack.
1889 include "X86InstrFPStack.td"
1891 // SIMD support (SSE, MMX and AVX)
1892 include "X86InstrFragmentsSIMD.td"
1894 // FMA - Fused Multiply-Add support (requires FMA)
1895 include "X86InstrFMA.td"
1898 include "X86InstrXOP.td"
1900 // SSE, MMX and 3DNow! vector support.
1901 include "X86InstrSSE.td"
1902 include "X86InstrAVX512.td"
1903 include "X86InstrMMX.td"
1904 include "X86Instr3DNow.td"
1906 include "X86InstrVMX.td"
1907 include "X86InstrSVM.td"
1909 include "X86InstrTSX.td"
1911 // System instructions.
1912 include "X86InstrSystem.td"
1914 // Compiler Pseudo Instructions and Pat Patterns
1915 include "X86InstrCompiler.td"
1917 //===----------------------------------------------------------------------===//
1918 // Assembler Mnemonic Aliases
1919 //===----------------------------------------------------------------------===//
1921 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
1922 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
1924 def : MnemonicAlias<"cbw", "cbtw", "att">;
1925 def : MnemonicAlias<"cwde", "cwtl", "att">;
1926 def : MnemonicAlias<"cwd", "cwtd", "att">;
1927 def : MnemonicAlias<"cdq", "cltd", "att">;
1928 def : MnemonicAlias<"cdqe", "cltq", "att">;
1929 def : MnemonicAlias<"cqo", "cqto", "att">;
1931 // lret maps to lretl, it is not ambiguous with lretq.
1932 def : MnemonicAlias<"lret", "lretl", "att">;
1934 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[In32BitMode]>;
1935 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
1937 def : MnemonicAlias<"loopz", "loope", "att">;
1938 def : MnemonicAlias<"loopnz", "loopne", "att">;
1940 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
1941 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
1942 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
1943 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
1944 def : MnemonicAlias<"popfd", "popfl", "att">;
1946 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1947 // all modes. However: "push (addr)" and "push $42" should default to
1948 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1949 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
1950 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
1951 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
1952 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1953 def : MnemonicAlias<"pushfd", "pushfl", "att">;
1955 def : MnemonicAlias<"popad", "popa", "intel">, Requires<[In32BitMode]>;
1956 def : MnemonicAlias<"pushad", "pusha", "intel">, Requires<[In32BitMode]>;
1958 def : MnemonicAlias<"repe", "rep", "att">;
1959 def : MnemonicAlias<"repz", "rep", "att">;
1960 def : MnemonicAlias<"repnz", "repne", "att">;
1962 def : MnemonicAlias<"retl", "ret", "att">, Requires<[In32BitMode]>;
1963 def : MnemonicAlias<"retq", "ret", "att">, Requires<[In64BitMode]>;
1965 def : MnemonicAlias<"salb", "shlb", "att">;
1966 def : MnemonicAlias<"salw", "shlw", "att">;
1967 def : MnemonicAlias<"sall", "shll", "att">;
1968 def : MnemonicAlias<"salq", "shlq", "att">;
1970 def : MnemonicAlias<"smovb", "movsb", "att">;
1971 def : MnemonicAlias<"smovw", "movsw", "att">;
1972 def : MnemonicAlias<"smovl", "movsl", "att">;
1973 def : MnemonicAlias<"smovq", "movsq", "att">;
1975 def : MnemonicAlias<"ud2a", "ud2", "att">;
1976 def : MnemonicAlias<"verrw", "verr", "att">;
1978 // System instruction aliases.
1979 def : MnemonicAlias<"iret", "iretl", "att">;
1980 def : MnemonicAlias<"sysret", "sysretl", "att">;
1981 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
1983 def : MnemonicAlias<"lgdtl", "lgdt", "att">, Requires<[In32BitMode]>;
1984 def : MnemonicAlias<"lgdtq", "lgdt", "att">, Requires<[In64BitMode]>;
1985 def : MnemonicAlias<"lidtl", "lidt", "att">, Requires<[In32BitMode]>;
1986 def : MnemonicAlias<"lidtq", "lidt", "att">, Requires<[In64BitMode]>;
1987 def : MnemonicAlias<"sgdtl", "sgdt", "att">, Requires<[In32BitMode]>;
1988 def : MnemonicAlias<"sgdtq", "sgdt", "att">, Requires<[In64BitMode]>;
1989 def : MnemonicAlias<"sidtl", "sidt", "att">, Requires<[In32BitMode]>;
1990 def : MnemonicAlias<"sidtq", "sidt", "att">, Requires<[In64BitMode]>;
1993 // Floating point stack aliases.
1994 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
1995 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
1996 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
1997 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
1998 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
1999 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2000 def : MnemonicAlias<"fildq", "fildll", "att">;
2001 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2002 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2003 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2004 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2005 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2006 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2007 def : MnemonicAlias<"fwait", "wait", "att">;
2010 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2012 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2013 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2015 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2016 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2017 /// example "setz" -> "sete".
2018 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2020 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2021 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2022 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2023 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2024 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2025 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2026 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2027 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2028 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2029 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2031 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2032 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2033 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2034 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2037 // Aliases for set<CC>
2038 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2039 // Aliases for j<CC>
2040 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2041 // Aliases for cmov<CC>{w,l,q}
2042 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2043 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2044 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2045 // No size suffix for intel-style asm.
2046 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2049 //===----------------------------------------------------------------------===//
2050 // Assembler Instruction Aliases
2051 //===----------------------------------------------------------------------===//
2053 // aad/aam default to base 10 if no operand is specified.
2054 def : InstAlias<"aad", (AAD8i8 10)>;
2055 def : InstAlias<"aam", (AAM8i8 10)>;
2057 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2058 // Likewise for btc/btr/bts.
2059 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2060 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2061 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2062 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2063 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2064 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2065 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2066 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2069 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2070 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2071 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2072 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2074 // div and idiv aliases for explicit A register.
2075 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2076 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2077 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2078 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2079 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2080 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2081 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2082 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2083 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2084 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2085 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2086 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2087 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2088 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2089 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2090 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2094 // Various unary fpstack operations default to operating on on ST1.
2095 // For example, "fxch" -> "fxch %st(1)"
2096 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2097 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2098 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2099 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2100 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2101 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2102 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2103 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2104 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2105 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2106 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2107 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2108 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2109 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2110 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2112 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2113 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2114 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2116 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2117 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2118 (Inst RST:$op), EmitAlias>;
2119 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2120 (Inst ST0), EmitAlias>;
2123 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2124 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2125 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2126 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2127 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2128 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2129 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2130 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2131 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2132 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2133 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2134 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2135 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2136 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2137 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2138 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2141 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2142 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2143 // solely because gas supports it.
2144 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2145 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2146 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2147 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2148 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2149 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2151 // We accept "fnstsw %eax" even though it only writes %ax.
2152 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2153 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2154 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2156 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2157 // this is compatible with what GAS does.
2158 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2159 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2160 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
2161 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
2163 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2164 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2165 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2166 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2167 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2168 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2169 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2171 // inb %dx -> inb %al, %dx
2172 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2173 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2174 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2175 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2176 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2177 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2180 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2181 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2182 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2183 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2184 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2185 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2186 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2188 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2189 // the move. All segment/mem forms are equivalent, this has the shortest
2191 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2192 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2194 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2195 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2197 // Match 'movq GR64, MMX' as an alias for movd.
2198 def : InstAlias<"movq $src, $dst",
2199 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2200 def : InstAlias<"movq $src, $dst",
2201 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2203 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2204 // alias for movsl. (as in rep; movsd)
2205 def : InstAlias<"movsd", (MOVSD), 0>;
2208 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2209 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2210 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2211 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2212 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2213 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2214 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2217 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2218 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2219 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2220 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2221 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2222 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2223 // Note: No GR32->GR64 movzx form.
2225 // outb %dx -> outb %al, %dx
2226 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2227 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2228 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2229 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2230 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2231 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2233 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2234 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2235 // errors, since its encoding is the most compact.
2236 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2238 // shld/shrd op,op -> shld op, op, CL
2239 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2240 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2241 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2242 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2243 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2244 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2246 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2247 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2248 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2249 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2250 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2251 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2253 /* FIXME: This is disabled because the asm matcher is currently incapable of
2254 * matching a fixed immediate like $1.
2255 // "shl X, $1" is an alias for "shl X".
2256 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2257 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2258 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2259 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2260 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2261 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2262 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2263 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2264 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2265 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2266 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2267 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2268 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2269 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2270 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2271 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2272 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2275 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2276 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2277 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2278 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2281 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2282 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2283 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2284 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2285 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2287 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2288 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2289 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2290 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2291 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2293 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2294 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2295 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2296 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2297 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;