1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<2> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
45 // MemType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class MemType<bits<3> val> {
51 def NoMem : MemType<0>;
52 def Mem8 : MemType<1>;
53 def Mem16 : MemType<2>;
54 def Mem32 : MemType<3>;
55 def Mem64 : MemType<4>;
56 def Mem80 : MemType<5>;
57 def Mem128 : MemType<6>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def CondMovFP : FPFormat<5>;
70 def SpecialFP : FPFormat<6>;
73 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
74 let Namespace = "X86";
77 bits<8> Opcode = opcod;
79 bits<5> FormBits = Form.Value;
81 bits<3> MemTypeBits = MemT.Value;
83 bits<2> ImmTypeBits = ImmT.Value;
86 // Attributes specific to X86 instructions...
88 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
90 // Flag whether implicit register usage is printed before/after the
92 bit printImplicitUsesBefore = 0;
93 bit printImplicitUsesAfter = 0;
95 // Flag whether implicit register definitions are printed before/after the
97 bit printImplicitDefsBefore = 0;
98 bit printImplicitDefsAfter = 0;
100 bits<4> Prefix = 0; // Which prefix byte does this inst have?
101 FPFormat FPForm; // What flavor of FP instruction is this?
102 bits<3> FPFormBits = 0;
105 class Imp<list<Register> uses, list<Register> defs> {
106 list<Register> Uses = uses;
107 list<Register> Defs = defs;
110 class Pattern<dag P> {
115 // Prefix byte classes which are used to indicate to the ad-hoc machine code
116 // emitter that various prefix bytes are required.
117 class OpSize { bit hasOpSizePrefix = 1; }
118 class TB { bits<4> Prefix = 1; }
119 class REP { bits<4> Prefix = 2; }
120 class D8 { bits<4> Prefix = 3; }
121 class D9 { bits<4> Prefix = 4; }
122 class DA { bits<4> Prefix = 5; }
123 class DB { bits<4> Prefix = 6; }
124 class DC { bits<4> Prefix = 7; }
125 class DD { bits<4> Prefix = 8; }
126 class DE { bits<4> Prefix = 9; }
127 class DF { bits<4> Prefix = 10; }
130 //===----------------------------------------------------------------------===//
131 // Instruction templates...
133 class I<string n, bits<8> o, Format f> : X86Inst<n, o, f, NoMem, NoImm>;
135 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
136 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
137 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
138 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
140 class Ii<string n, bits<8> o, Format f, ImmType i> : X86Inst<n, o, f, NoMem, i>;
141 class Ii8 <string n, bits<8> o, Format f> : Ii<n, o, f, Imm8 >;
142 class Ii16<string n, bits<8> o, Format f> : Ii<n, o, f, Imm16>;
143 class Ii32<string n, bits<8> o, Format f> : Ii<n, o, f, Imm32>;
145 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
146 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
147 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
149 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
150 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
152 // Helper for shift instructions
153 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUsesAfter = 1; }
154 class PrintImpUsesAfter {bit printImplicitUsesAfter = 1;}
155 class PrintImpDefsAfter {bit printImplicitDefsAfter = 1;}
157 //===----------------------------------------------------------------------===//
158 // Instruction list...
161 def PHI : I<"PHI", 0, Pseudo>; // PHI node...
163 def NOOP : I<"nop", 0x90, RawFrm>; // nop
165 def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
166 def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
167 def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>;
168 def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>;
169 let isTerminator = 1 in
170 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
171 def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>;
172 //===----------------------------------------------------------------------===//
173 // Control Flow Instructions...
176 // Return instruction...
177 let isTerminator = 1, isReturn = 1 in
178 def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>;
180 // All branches are RawFrm, Void, Branch, and Terminators
181 let isBranch = 1, isTerminator = 1 in
182 class IBr<string name, bits<8> opcode> : I<name, opcode, RawFrm>;
184 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
185 def JB : IBr<"jb" , 0x82>, TB;
186 def JAE : IBr<"jae", 0x83>, TB;
187 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
188 def JNE : IBr<"jne", 0x85>, TB;
189 def JBE : IBr<"jbe", 0x86>, TB;
190 def JA : IBr<"ja" , 0x87>, TB;
191 def JS : IBr<"js" , 0x88>, TB;
192 def JNS : IBr<"jns", 0x89>, TB;
193 def JL : IBr<"jl" , 0x8C>, TB;
194 def JGE : IBr<"jge", 0x8D>, TB;
195 def JLE : IBr<"jle", 0x8E>, TB;
196 def JG : IBr<"jg" , 0x8F>, TB;
199 //===----------------------------------------------------------------------===//
200 // Call Instructions...
203 // All calls clobber the non-callee saved registers...
204 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
205 def CALLpcrel32 : I <"call", 0xE8, RawFrm>;
206 def CALL32r : I <"call", 0xFF, MRM2r>;
207 def CALL32m : Im32<"call", 0xFF, MRM2m>;
211 //===----------------------------------------------------------------------===//
212 // Miscellaneous Instructions...
214 def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>;
215 def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
217 let isTwoAddress = 1 in // R32 = bswap R32
218 def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB;
220 def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8
221 def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16
222 def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32
223 def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
224 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
225 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
226 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
227 def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
228 def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
230 def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
231 def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
234 def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
235 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
236 def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
237 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
238 def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
239 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
241 def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
242 Imp<[AL,ECX,EDI], [ECX,EDI]>;
243 def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
244 Imp<[AX,ECX,EDI], [ECX,EDI]>;
245 def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
246 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
248 //===----------------------------------------------------------------------===//
249 // Input/Output Instructions...
251 def IN8 : I<"in", 0xEC, RawFrm>, Imp<[DX],[AL]>, PrintImpUsesAfter, PrintImpDefsAfter; // in AL = I/O address DX
252 def IN16 : I<"in", 0xED, RawFrm>, Imp<[DX],[AX]>, OpSize, PrintImpUsesAfter, PrintImpDefsAfter; // in AX = I/O address DX
253 def IN32 : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, PrintImpUsesAfter, PrintImpDefsAfter; // in EAX = I/O address DX
255 def OUT8 : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, PrintImpUsesAfter;
256 def OUT16 : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, PrintImpUsesAfter;
257 def OUT32 : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, PrintImpUsesAfter;
259 //===----------------------------------------------------------------------===//
260 // Move Instructions...
262 def MOV8rr : I <"mov", 0x88, MRMDestReg>, Pattern<(set R8 , R8 )>;
263 def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, Pattern<(set R16, R16)>;
264 def MOV32rr : I <"mov", 0x89, MRMDestReg>, Pattern<(set R32, R32)>;
265 def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, Pattern<(set R8 , imm )>;
266 def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, Pattern<(set R16, imm)>;
267 def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, Pattern<(set R32, imm)>;
268 def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
269 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
270 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
272 def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
273 def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16]
274 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
275 def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>, // R32 = [mem32]
276 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
278 def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
279 def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
280 def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
282 //===----------------------------------------------------------------------===//
283 // Fixed-Register Multiplication and Division Instructions...
286 // Extra precision multiplication
287 def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8
288 def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
289 def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
290 def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
291 def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
292 def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
294 // unsigned division/remainder
295 def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
296 def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
297 def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
298 def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
299 def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
300 def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
302 // signed division/remainder
303 def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
304 def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
305 def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
306 def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
307 def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
308 def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
310 // Sign-extenders for division
311 def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL)
312 def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
313 def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
315 //===----------------------------------------------------------------------===//
316 // Two address Instructions...
318 let isTwoAddress = 1 in {
321 def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if <u, R16 = R16
322 def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
323 def CMOVB32rr : I <"cmovb", 0x42, MRMSrcReg>, TB; // if <u, R32 = R32
324 def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
326 def CMOVAE16rr: I <"cmovae", 0x43, MRMSrcReg>, TB, OpSize; // if >=u, R16 = R16
327 def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
328 def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32
329 def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
331 def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
332 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
333 def CMOVE32rr : I <"cmove", 0x44, MRMSrcReg>, TB; // if ==, R32 = R32
334 def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32]
336 def CMOVNE16rr: I <"cmovne",0x45, MRMSrcReg>, TB, OpSize; // if !=, R16 = R16
337 def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16]
338 def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
339 def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
341 def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16
342 def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
343 def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32
344 def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
346 def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16
347 def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
348 def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32
349 def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
351 def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16
352 def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
353 def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
354 def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
356 def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16
357 def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
358 def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32
359 def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
361 def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if <s, R16 = R16
362 def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
363 def CMOVL32rr : I <"cmovl", 0x4C, MRMSrcReg>, TB; // if <s, R32 = R32
364 def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
366 def CMOVGE16rr: I <"cmovge",0x4D, MRMSrcReg>, TB, OpSize; // if >=s, R16 = R16
367 def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
368 def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32
369 def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
371 def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16
372 def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
373 def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32
374 def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
376 def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16
377 def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
378 def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32
379 def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
381 // unary instructions
382 def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
383 def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16
384 def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32
385 def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
386 def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
387 def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
389 def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1
390 def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1
391 def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1
392 def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
393 def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
394 def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
396 def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8
397 def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16
398 def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32
399 def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
400 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
401 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
403 def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8
404 def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16
405 def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32
406 def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
407 def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
408 def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
410 // Logical operators...
411 def AND8rr : I <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
412 def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
413 def AND32rr : I <"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
414 def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
415 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
416 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
417 def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
418 def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
419 def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
421 def AND8ri : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>;
422 def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
423 def AND32ri : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>;
424 def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
425 def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
426 def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32
428 def AND16ri8 : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
429 def AND32ri8 : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8
430 def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
431 def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
434 def OR8rr : I <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
435 def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
436 def OR32rr : I <"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
437 def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
438 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
439 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
440 def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
441 def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
442 def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
444 def OR8ri : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>;
445 def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
446 def OR32ri : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>;
447 def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
448 def OR16mi : Im16i16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
449 def OR32mi : Im32i32<"or" , 0x81, MRM1m >; // [mem32] |= imm32
451 def OR16ri8 : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
452 def OR32ri8 : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8
453 def OR16mi8 : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
454 def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8
457 def XOR8rr : I <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
458 def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
459 def XOR32rr : I <"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
460 def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
461 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
462 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
463 def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
464 def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
465 def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
467 def XOR8ri : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>;
468 def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
469 def XOR32ri : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>;
470 def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
471 def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
472 def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
474 def XOR16ri8 : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
475 def XOR32ri8 : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
476 def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
477 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
479 // Shift instructions
480 // FIXME: provide shorter instructions when imm8 == 1
481 def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
482 def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
483 def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl
484 def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
485 def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
486 def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
488 def SHL8ri : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
489 def SHL16ri : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8
490 def SHL32ri : Ii8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8
491 def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
492 def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
493 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
495 def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
496 def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
497 def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl
498 def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
499 def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
500 def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
502 def SHR8ri : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
503 def SHR16ri : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8
504 def SHR32ri : Ii8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8
505 def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
506 def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
507 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
509 def SAR8rCL : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
510 def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
511 def SAR32rCL : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl
512 def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl
513 def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl
514 def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
516 def SAR8ri : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
517 def SAR16ri : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8
518 def SAR32ri : Ii8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8
519 def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
520 def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
521 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
523 def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
524 def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
525 def SHLD32rri8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
526 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
528 def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
529 def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
530 def SHRD32rri8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
531 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
535 def ADD8rr : I <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
536 def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
537 def ADD32rr : I <"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
538 def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
539 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
540 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
541 def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
542 def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
543 def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
545 def ADD8ri : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>;
546 def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
547 def ADD32ri : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>;
548 def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
549 def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
550 def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32
552 def ADD16ri8 : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
553 def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
554 def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
555 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
557 def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
558 def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry
559 def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry
560 def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry
561 def ADC32ri8 : Ii8 <"adc", 0x83, MRM2r >; // R32 += I8+Carry
562 def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
563 def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry
565 def SUB8rr : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
566 def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
567 def SUB32rr : I <"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
568 def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
569 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
570 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
571 def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
572 def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
573 def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
575 def SUB8ri : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>;
576 def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
577 def SUB32ri : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>;
578 def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
579 def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
580 def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32
582 def SUB16ri8 : Ii8 <"sub", 0x83, MRM5r >, OpSize;
583 def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
584 def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
585 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
587 def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
588 def SBB32mr : Im32 <"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry
589 def SBB32rm : Im32 <"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry
590 def SBB32ri : Ii32 <"sbb", 0x81, MRM3r >; // R32 -= I32+Carry
591 def SBB32ri8 : Ii8 <"sbb", 0x83, MRM3r >; // R32 -= I8+Carry
592 def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry
593 def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry
595 def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
596 def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
597 def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
598 def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
600 } // end Two Address instructions
602 // These are suprisingly enough not two address instructions!
603 def IMUL16rri : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16
604 def IMUL32rri : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32
605 def IMUL16rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8
606 def IMUL32rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8
607 def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
608 def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32
609 def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
610 def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
612 //===----------------------------------------------------------------------===//
613 // Test instructions are just like AND, except they don't generate a result.
614 def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8
615 def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16
616 def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32
617 def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
618 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
619 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
620 def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
621 def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
622 def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
624 def TEST8ri : Ii8 <"test", 0xF6, MRM0r >; // flags = R8 & imm8
625 def TEST16ri : Ii16 <"test", 0xF7, MRM0r >, OpSize; // flags = R16 & imm16
626 def TEST32ri : Ii32 <"test", 0xF7, MRM0r >; // flags = R32 & imm32
627 def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
628 def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
629 def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
633 // Condition code ops, incl. set if equal/not equal/...
634 def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH
635 def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>; // AH = flags
637 def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
638 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
639 def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign
640 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
641 def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = ==
642 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
643 def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = !=
644 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
645 def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign
646 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
647 def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed
648 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
649 def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = <sign bit>
650 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
651 def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = !<sign bit>
652 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
653 def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed
654 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
655 def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed
656 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
657 def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed
658 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
659 def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed
660 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
662 // Integer comparisons
663 def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8
664 def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16
665 def CMP32rr : I <"cmp", 0x39, MRMDestReg>, // compare R32, R32
666 Pattern<(isVoid (unspec2 R32, R32))>;
667 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
668 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
669 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
670 def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
671 def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
672 def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
673 def CMP8ri : Ii8 <"cmp", 0x80, MRM7r >; // compare R8, imm8
674 def CMP16ri : Ii16 <"cmp", 0x81, MRM7r >, OpSize; // compare R16, imm16
675 def CMP32ri : Ii32 <"cmp", 0x81, MRM7r >; // compare R32, imm32
676 def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
677 def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
678 def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
680 // Sign/Zero extenders
681 def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8)
682 def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8)
683 def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16)
684 def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
685 def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
686 def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
688 def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8)
689 def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8)
690 def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16)
691 def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
692 def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
693 def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
696 //===----------------------------------------------------------------------===//
697 // Floating point support
698 //===----------------------------------------------------------------------===//
700 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
702 // Floating point instruction templates
703 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
704 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
706 class FPI<string n, bits<8> o, Format F, FPFormat fp> : FPInst<n, o, F, fp, NoMem, NoImm>;
708 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
710 class FPI16m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
711 class FPI32m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
712 class FPI64m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
713 class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
715 // Pseudo instructions for floating point. We use these pseudo instructions
716 // because they can be expanded by the fp spackifier into one of many different
717 // forms of instructions for doing these operations. Until the stackifier runs,
718 // we prefer to be abstract.
719 def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2
720 def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
721 def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
722 def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
723 def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
725 def FpUCOM : FPI<"FUCOM", 0, Pseudo, TwoArgFP>; // FPSW = fucom f1, f2
726 def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
727 def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
730 // Floating point cmovs...
731 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0], printImplicitUsesBefore = 1 in {
732 def FCMOVB : FPI <"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA; // fcmovb ST(i) -> ST(0)
733 def FCMOVBE : FPI <"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA; // fcmovbe ST(i) -> ST(0)
734 def FCMOVE : FPI <"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA; // fcmove ST(i) -> ST(0)
735 def FCMOVAE : FPI <"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB; // fcmovae ST(i) -> ST(0)
736 def FCMOVA : FPI <"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB; // fcmova ST(i) -> ST(0)
737 def FCMOVNE : FPI <"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB; // fcmovne ST(i) -> ST(0)
740 // Floating point loads & stores...
741 def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
742 def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
743 def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
744 def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
745 def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
746 def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
747 def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
749 def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
750 def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
751 def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
752 def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
753 def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
754 def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
755 def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
757 def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
758 def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
759 def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
760 def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
761 def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
763 def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
765 // Floating point constant loads...
766 def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9;
767 def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9;
770 // Unary operations...
771 def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2
773 def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0)
775 // Binary arithmetic operations...
776 class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
777 list<Register> Uses = [ST0];
778 list<Register> Defs = [ST0];
780 class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
781 bit printImplicitUsesAfter = 1;
782 list<Register> Uses = [ST0];
784 class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
785 list<Register> Uses = [ST0];
788 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
789 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
790 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
792 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
793 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
794 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
796 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
797 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
798 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
800 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
801 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
802 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
804 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
805 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
806 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
808 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
809 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
810 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
812 // Floating point compares
813 def FUCOMr : I<"fucom" , 0xE0, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
814 def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
815 def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
817 // Floating point flag ops
818 def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags
819 def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
820 def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]
823 //===----------------------------------------------------------------------===//
824 // Instruction Expanders
827 def RET_R32 : Expander<(ret R32:$reg),
828 [(MOV32rr EAX, R32:$reg),
831 // FIXME: This should eventually just be implemented by defining a frameidx as a
832 // value address for a load.
833 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
834 [(MOV16rm R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
836 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
837 [(MOV32rm R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
840 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
841 [(MOV16rm R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
843 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
844 [(MOV32rm R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
846 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
847 basicblock:$d1, basicblock:$d2),
848 [(CMP32rr R32:$a1, R32:$a2),
850 (JMP basicblock:$d2)]>;