1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<2> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
45 // MemType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class MemType<bits<3> val> {
51 def NoMem : MemType<0>;
52 def Mem8 : MemType<1>;
53 def Mem16 : MemType<2>;
54 def Mem32 : MemType<3>;
55 def Mem64 : MemType<4>;
56 def Mem80 : MemType<5>;
57 def Mem128 : MemType<6>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def SpecialFP : FPFormat<5>;
72 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
73 let Namespace = "X86";
76 bits<8> Opcode = opcod;
78 bits<5> FormBits = Form.Value;
80 bits<3> MemTypeBits = MemT.Value;
82 bits<2> ImmTypeBits = ImmT.Value;
84 // Attributes specific to X86 instructions...
85 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
86 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
88 bits<4> Prefix = 0; // Which prefix byte does this inst have?
89 FPFormat FPForm; // What flavor of FP instruction is this?
90 bits<3> FPFormBits = 0;
93 class Imp<list<Register> uses, list<Register> defs> {
94 list<Register> Uses = uses;
95 list<Register> Defs = defs;
98 class Pattern<dag P> {
103 // Prefix byte classes which are used to indicate to the ad-hoc machine code
104 // emitter that various prefix bytes are required.
105 class OpSize { bit hasOpSizePrefix = 1; }
106 class TB { bits<4> Prefix = 1; }
107 class REP { bits<4> Prefix = 2; }
108 class D8 { bits<4> Prefix = 3; }
109 class D9 { bits<4> Prefix = 4; }
110 class DA { bits<4> Prefix = 5; }
111 class DB { bits<4> Prefix = 6; }
112 class DC { bits<4> Prefix = 7; }
113 class DD { bits<4> Prefix = 8; }
114 class DE { bits<4> Prefix = 9; }
115 class DF { bits<4> Prefix = 10; }
118 //===----------------------------------------------------------------------===//
119 // Instruction templates...
121 class I<string n, bits<8> o, Format f> : X86Inst<n, o, f, NoMem, NoImm>;
123 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
124 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
125 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
126 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
128 class Ii<string n, bits<8> o, Format f, ImmType i> : X86Inst<n, o, f, NoMem, i>;
129 class Ii8 <string n, bits<8> o, Format f> : Ii<n, o, f, Imm8 >;
130 class Ii16<string n, bits<8> o, Format f> : Ii<n, o, f, Imm16>;
131 class Ii32<string n, bits<8> o, Format f> : Ii<n, o, f, Imm32>;
133 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
134 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
135 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
137 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
138 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
140 // Helper for shift instructions
141 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
143 //===----------------------------------------------------------------------===//
144 // Instruction list...
147 def PHI : I<"PHI", 0, Pseudo>; // PHI node...
149 def NOOP : I<"nop", 0x90, RawFrm>; // nop
151 def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
152 def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
153 def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>;
154 def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>;
155 let isTerminator = 1 in
156 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
157 def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>;
158 //===----------------------------------------------------------------------===//
159 // Control Flow Instructions...
162 // Return instruction...
163 let isTerminator = 1, isReturn = 1 in
164 def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>;
166 // All branches are RawFrm, Void, Branch, and Terminators
167 let isBranch = 1, isTerminator = 1 in
168 class IBr<string name, bits<8> opcode> : I<name, opcode, RawFrm>;
170 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
171 def JB : IBr<"jb" , 0x82>, TB;
172 def JAE : IBr<"jae", 0x83>, TB;
173 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
174 def JNE : IBr<"jne", 0x85>, TB;
175 def JBE : IBr<"jbe", 0x86>, TB;
176 def JA : IBr<"ja" , 0x87>, TB;
177 def JS : IBr<"js" , 0x88>, TB;
178 def JNS : IBr<"jns", 0x89>, TB;
179 def JL : IBr<"jl" , 0x8C>, TB;
180 def JGE : IBr<"jge", 0x8D>, TB;
181 def JLE : IBr<"jle", 0x8E>, TB;
182 def JG : IBr<"jg" , 0x8F>, TB;
185 //===----------------------------------------------------------------------===//
186 // Call Instructions...
189 // All calls clobber the non-callee saved registers...
190 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
191 def CALLpcrel32 : I <"call", 0xE8, RawFrm>;
192 def CALL32r : I <"call", 0xFF, MRM2r>;
193 def CALL32m : Im32<"call", 0xFF, MRM2m>;
197 //===----------------------------------------------------------------------===//
198 // Miscellaneous Instructions...
200 def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>;
201 def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
203 let isTwoAddress = 1 in // R32 = bswap R32
204 def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB;
206 def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8
207 def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16
208 def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32
209 def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
210 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
211 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
212 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
213 def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
214 def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
216 def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
217 def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
220 def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
221 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
222 def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
223 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
224 def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
225 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
227 def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
228 Imp<[AL,ECX,EDI], [ECX,EDI]>;
229 def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
230 Imp<[AX,ECX,EDI], [ECX,EDI]>;
231 def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
232 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
234 //===----------------------------------------------------------------------===//
235 // Move Instructions...
237 def MOV8rr : I <"mov", 0x88, MRMDestReg>, Pattern<(set R8 , R8 )>;
238 def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, Pattern<(set R16, R16)>;
239 def MOV32rr : I <"mov", 0x89, MRMDestReg>, Pattern<(set R32, R32)>;
240 def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, Pattern<(set R8 , imm )>;
241 def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, Pattern<(set R16, imm)>;
242 def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, Pattern<(set R32, imm)>;
243 def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
244 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
245 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
247 def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
248 def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16]
249 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
250 def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>, // R32 = [mem32]
251 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
253 def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
254 def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
255 def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
257 //===----------------------------------------------------------------------===//
258 // Fixed-Register Multiplication and Division Instructions...
261 // Extra precision multiplication
262 def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8
263 def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
264 def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
265 def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
266 def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
267 def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
269 // unsigned division/remainder
270 def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
271 def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
272 def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
273 def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
274 def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
275 def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
277 // signed division/remainder
278 def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
279 def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
280 def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
281 def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
282 def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
283 def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
285 // Sign-extenders for division
286 def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL)
287 def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
288 def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
290 //===----------------------------------------------------------------------===//
291 // Two address Instructions...
293 let isTwoAddress = 1 in {
295 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
296 // register allocated to cmovXX XY, Z
297 def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
298 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
299 def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
300 def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
301 def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
302 def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
304 // unary instructions
305 def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
306 def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16
307 def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32
308 def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
309 def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
310 def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
312 def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1
313 def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1
314 def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1
315 def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
316 def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
317 def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
319 def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8
320 def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16
321 def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32
322 def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
323 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
324 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
326 def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8
327 def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16
328 def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32
329 def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
330 def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
331 def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
333 // Logical operators...
334 def AND8rr : I <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
335 def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
336 def AND32rr : I <"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
337 def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
338 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
339 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
340 def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
341 def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
342 def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
344 def AND8ri : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>;
345 def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
346 def AND32ri : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>;
347 def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
348 def AND16mi : Im16i16 <"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
349 def AND32mi : Im32i32 <"and", 0x81, MRM4m >; // [mem32] &= imm32
351 def AND16ri8 : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
352 def AND32ri8 : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8
353 def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
354 def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
357 def OR8rr : I <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
358 def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
359 def OR32rr : I <"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
360 def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
361 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
362 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
363 def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
364 def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
365 def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
367 def OR8ri : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>;
368 def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
369 def OR32ri : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>;
370 def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
371 def OR16mi : Im16i16 <"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
372 def OR32mi : Im32i32 <"or" , 0x81, MRM1m >; // [mem32] |= imm32
374 def OR16ri8 : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
375 def OR32ri8 : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8
376 def OR16mi8 : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
377 def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8
380 def XOR8rr : I <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
381 def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
382 def XOR32rr : I <"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
383 def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
384 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
385 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
386 def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
387 def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
388 def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
390 def XOR8ri : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>;
391 def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
392 def XOR32ri : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>;
393 def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
394 def XOR16mi : Im16i16 <"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
395 def XOR32mi : Im32i32 <"xor", 0x81, MRM6m >; // [mem32] ^= R32
397 def XOR16ri8 : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
398 def XOR32ri8 : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
399 def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
400 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
402 // Shift instructions
403 // FIXME: provide shorter instructions when imm8 == 1
404 def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
405 def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
406 def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl
407 def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
408 def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
409 def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
411 def SHL8ri : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
412 def SHL16ri : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8
413 def SHL32ri : Ii8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8
414 def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
415 def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
416 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
418 def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
419 def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
420 def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl
421 def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
422 def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
423 def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
425 def SHR8ri : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
426 def SHR16ri : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8
427 def SHR32ri : Ii8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8
428 def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
429 def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
430 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
432 def SAR8rCL : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
433 def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
434 def SAR32rCL : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl
435 def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl
436 def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl
437 def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
439 def SAR8ri : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
440 def SAR16ri : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8
441 def SAR32ri : Ii8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8
442 def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
443 def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
444 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
446 def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
447 def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
448 def SHLD32rri8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
449 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
451 def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
452 def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
453 def SHRD32rri8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
454 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
458 def ADD8rr : I <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
459 def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
460 def ADD32rr : I <"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
461 def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
462 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
463 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
464 def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
465 def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
466 def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
468 def ADD8ri : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>;
469 def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
470 def ADD32ri : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>;
471 def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
472 def ADD16mi : Im16i16 <"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
473 def ADD32mi : Im32i32 <"add", 0x81, MRM0m >; // [mem32] += I32
475 def ADD16ri8 : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
476 def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
477 def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
478 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
480 def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
481 def ADC32rm : Im32 <"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry
482 def ADC32mr : Im32 <"adc", 0x13, MRMDestMem>; // [mem32] += R32+Carry
485 def SUB8rr : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
486 def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
487 def SUB32rr : I <"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
488 def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
489 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
490 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
491 def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
492 def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
493 def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
495 def SUB8ri : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>;
496 def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
497 def SUB32ri : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>;
498 def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
499 def SUB16mi : Im16i16 <"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
500 def SUB32mi : Im32i32 <"sub", 0x81, MRM5m >; // [mem32] -= I32
502 def SUB16ri8 : Ii8 <"sub", 0x83, MRM5r >, OpSize;
503 def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
504 def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
505 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
507 def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow
508 def SBB32rm : Im32 <"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow
509 def SBB32mr : Im32 <"sbb", 0x1B, MRMDestMem>; // [mem32] -= R32+Borrow
511 def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
512 def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
513 def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
514 def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
516 } // end Two Address instructions
518 // These are suprisingly enough not two address instructions!
519 def IMUL16rri : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16
520 def IMUL32rri : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32
521 def IMUL16rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8
522 def IMUL32rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8
523 def IMUL16rmi : Im16i16 <"imul", 0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
524 def IMUL32rmi : Im32i32 <"imul", 0x69, MRMSrcMem>; // R32 = [mem32]*I32
525 def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
526 def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
528 //===----------------------------------------------------------------------===//
529 // Test instructions are just like AND, except they don't generate a result.
530 def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8
531 def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16
532 def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32
533 def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
534 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
535 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
536 def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
537 def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
538 def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
540 def TEST8ri : Ii8 <"test", 0xF6, MRM0r >; // flags = R8 & imm8
541 def TEST16ri : Ii16 <"test", 0xF7, MRM0r >, OpSize; // flags = R16 & imm16
542 def TEST32ri : Ii32 <"test", 0xF7, MRM0r >; // flags = R32 & imm32
543 def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
544 def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
545 def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
549 // Condition code ops, incl. set if equal/not equal/...
550 def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH
552 def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
553 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
554 def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign
555 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
556 def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = ==
557 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
558 def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = !=
559 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
560 def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign
561 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
562 def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed
563 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
564 def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = <sign bit>
565 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
566 def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = !<sign bit>
567 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
568 def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed
569 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
570 def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed
571 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
572 def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed
573 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
574 def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed
575 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
577 // Integer comparisons
578 def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8
579 def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16
580 def CMP32rr : I <"cmp", 0x39, MRMDestReg>, // compare R32, R32
581 Pattern<(isVoid (unspec2 R32, R32))>;
582 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
583 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
584 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
585 def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
586 def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
587 def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
588 def CMP8ri : Ii8 <"cmp", 0x80, MRM7r >; // compare R8, imm8
589 def CMP16ri : Ii16 <"cmp", 0x81, MRM7r >, OpSize; // compare R16, imm16
590 def CMP32ri : Ii32 <"cmp", 0x81, MRM7r >; // compare R32, imm32
591 def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
592 def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
593 def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
595 // Sign/Zero extenders
596 def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8)
597 def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8)
598 def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16)
599 def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
600 def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
601 def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
603 def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8)
604 def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8)
605 def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16)
606 def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
607 def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
608 def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
611 //===----------------------------------------------------------------------===//
612 // Floating point support
613 //===----------------------------------------------------------------------===//
615 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
617 // Floating point instruction templates
618 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
619 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
621 class FPI<string n, bits<8> o, Format F, FPFormat fp> : FPInst<n, o, F, fp, NoMem, NoImm>;
623 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
625 class FPI16m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
626 class FPI32m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
627 class FPI64m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
628 class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
630 // Pseudo instructions for floating point. We use these pseudo instructions
631 // because they can be expanded by the fp spackifier into one of many different
632 // forms of instructions for doing these operations. Until the stackifier runs,
633 // we prefer to be abstract.
634 def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2
635 def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
636 def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
637 def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
638 def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
640 def FpUCOM : FPI<"FUCOM", 0, Pseudo, TwoArgFP>; // FPSW = fucom f1, f2
641 def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
642 def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
644 // Floating point loads & stores...
645 def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
646 def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
647 def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
648 def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
649 def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
650 def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
651 def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
653 def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
654 def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
655 def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
656 def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
657 def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
658 def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
659 def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
661 def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
662 def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
663 def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
664 def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
665 def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
667 def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
669 // Floating point constant loads...
670 def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9;
671 def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9;
674 // Unary operations...
675 def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2
677 def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0)
679 // Binary arithmetic operations...
680 class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
681 list<Register> Uses = [ST0];
682 list<Register> Defs = [ST0];
684 class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
685 bit printImplicitUses = 1;
686 list<Register> Uses = [ST0];
688 class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
689 list<Register> Uses = [ST0];
692 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
693 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
694 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
696 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
697 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
698 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
700 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
701 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
702 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
704 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
705 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
706 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
708 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
709 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
710 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
712 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
713 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
714 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
716 // Floating point compares
717 def FUCOMr : I<"fucom" , 0xE0, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
718 def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
719 def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
721 // Floating point flag ops
722 def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags
723 def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
724 def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]
727 //===----------------------------------------------------------------------===//
728 // Instruction Expanders
731 def RET_R32 : Expander<(ret R32:$reg),
732 [(MOV32rr EAX, R32:$reg),
735 // FIXME: This should eventually just be implemented by defining a frameidx as a
736 // value address for a load.
737 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
738 [(MOV16rm R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
740 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
741 [(MOV32rm R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
744 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
745 [(MOV16rm R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
747 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
748 [(MOV32rm R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
750 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
751 basicblock:$d1, basicblock:$d2),
752 [(CMP32rr R32:$a1, R32:$a2),
754 (JMP basicblock:$d2)]>;