1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
146 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
155 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
156 [SDNPHasChain, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def X86vastart_save_xmm_regs :
180 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
181 SDT_X86VASTART_SAVE_XMM_REGS,
182 [SDNPHasChain, SDNPVariadic]>;
184 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
185 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
187 def X86callseq_start :
188 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
189 [SDNPHasChain, SDNPOutGlue]>;
191 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
195 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
198 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
199 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
200 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
201 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
204 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
205 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
207 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
208 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
210 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
211 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
213 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
219 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
220 SDTypeProfile<1, 1, [SDTCisInt<0>,
222 [SDNPHasChain, SDNPSideEffect]>;
223 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
224 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
225 [SDNPHasChain, SDNPSideEffect]>;
227 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
228 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
230 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
232 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
233 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
235 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
237 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
238 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
240 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
241 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
242 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
244 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
246 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
248 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
250 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
251 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
252 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
254 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
256 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
257 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
259 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
262 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
263 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
265 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
266 [SDNPHasChain, SDNPOutGlue]>;
268 //===----------------------------------------------------------------------===//
269 // X86 Operand Definitions.
272 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
273 // the index operand of an address, to conform to x86 encoding restrictions.
274 def ptr_rc_nosp : PointerLikeRegClass<1>;
276 // *mem - Operand definitions for the funky X86 addressing mode operands.
278 def X86MemAsmOperand : AsmOperandClass {
279 let Name = "Mem"; let PredicateMethod = "isMem";
281 def X86Mem8AsmOperand : AsmOperandClass {
282 let Name = "Mem8"; let PredicateMethod = "isMem8";
284 def X86Mem16AsmOperand : AsmOperandClass {
285 let Name = "Mem16"; let PredicateMethod = "isMem16";
287 def X86Mem32AsmOperand : AsmOperandClass {
288 let Name = "Mem32"; let PredicateMethod = "isMem32";
290 def X86Mem64AsmOperand : AsmOperandClass {
291 let Name = "Mem64"; let PredicateMethod = "isMem64";
293 def X86Mem80AsmOperand : AsmOperandClass {
294 let Name = "Mem80"; let PredicateMethod = "isMem80";
296 def X86Mem128AsmOperand : AsmOperandClass {
297 let Name = "Mem128"; let PredicateMethod = "isMem128";
299 def X86Mem256AsmOperand : AsmOperandClass {
300 let Name = "Mem256"; let PredicateMethod = "isMem256";
303 // Gather mem operands
304 def X86MemVX32Operand : AsmOperandClass {
305 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
307 def X86MemVY32Operand : AsmOperandClass {
308 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
310 def X86MemVX64Operand : AsmOperandClass {
311 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
313 def X86MemVY64Operand : AsmOperandClass {
314 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
317 def X86AbsMemAsmOperand : AsmOperandClass {
319 let SuperClasses = [X86MemAsmOperand];
321 class X86MemOperand<string printMethod> : Operand<iPTR> {
322 let PrintMethod = printMethod;
323 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
324 let ParserMatchClass = X86MemAsmOperand;
327 let OperandType = "OPERAND_MEMORY" in {
328 def opaque32mem : X86MemOperand<"printopaquemem">;
329 def opaque48mem : X86MemOperand<"printopaquemem">;
330 def opaque80mem : X86MemOperand<"printopaquemem">;
331 def opaque512mem : X86MemOperand<"printopaquemem">;
333 def i8mem : X86MemOperand<"printi8mem"> {
334 let ParserMatchClass = X86Mem8AsmOperand; }
335 def i16mem : X86MemOperand<"printi16mem"> {
336 let ParserMatchClass = X86Mem16AsmOperand; }
337 def i32mem : X86MemOperand<"printi32mem"> {
338 let ParserMatchClass = X86Mem32AsmOperand; }
339 def i64mem : X86MemOperand<"printi64mem"> {
340 let ParserMatchClass = X86Mem64AsmOperand; }
341 def i128mem : X86MemOperand<"printi128mem"> {
342 let ParserMatchClass = X86Mem128AsmOperand; }
343 def i256mem : X86MemOperand<"printi256mem"> {
344 let ParserMatchClass = X86Mem256AsmOperand; }
345 def f32mem : X86MemOperand<"printf32mem"> {
346 let ParserMatchClass = X86Mem32AsmOperand; }
347 def f64mem : X86MemOperand<"printf64mem"> {
348 let ParserMatchClass = X86Mem64AsmOperand; }
349 def f80mem : X86MemOperand<"printf80mem"> {
350 let ParserMatchClass = X86Mem80AsmOperand; }
351 def f128mem : X86MemOperand<"printf128mem"> {
352 let ParserMatchClass = X86Mem128AsmOperand; }
353 def f256mem : X86MemOperand<"printf256mem">{
354 let ParserMatchClass = X86Mem256AsmOperand; }
356 // Gather mem operands
357 def vx32mem : X86MemOperand<"printi32mem">{
358 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
359 let ParserMatchClass = X86MemVX32Operand; }
360 def vy32mem : X86MemOperand<"printi32mem">{
361 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
362 let ParserMatchClass = X86MemVY32Operand; }
363 def vx64mem : X86MemOperand<"printi64mem">{
364 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
365 let ParserMatchClass = X86MemVX64Operand; }
366 def vy64mem : X86MemOperand<"printi64mem">{
367 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
368 let ParserMatchClass = X86MemVY64Operand; }
371 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
372 // plain GR64, so that it doesn't potentially require a REX prefix.
373 def i8mem_NOREX : Operand<i64> {
374 let PrintMethod = "printi8mem";
375 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
376 let ParserMatchClass = X86Mem8AsmOperand;
377 let OperandType = "OPERAND_MEMORY";
380 // GPRs available for tailcall.
381 // It represents GR32_TC, GR64_TC or GR64_TCW64.
382 def ptr_rc_tailcall : PointerLikeRegClass<2>;
384 // Special i32mem for addresses of load folding tail calls. These are not
385 // allowed to use callee-saved registers since they must be scheduled
386 // after callee-saved register are popped.
387 def i32mem_TC : Operand<i32> {
388 let PrintMethod = "printi32mem";
389 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
391 let ParserMatchClass = X86Mem32AsmOperand;
392 let OperandType = "OPERAND_MEMORY";
395 // Special i64mem for addresses of load folding tail calls. These are not
396 // allowed to use callee-saved registers since they must be scheduled
397 // after callee-saved register are popped.
398 def i64mem_TC : Operand<i64> {
399 let PrintMethod = "printi64mem";
400 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
401 ptr_rc_tailcall, i32imm, i8imm);
402 let ParserMatchClass = X86Mem64AsmOperand;
403 let OperandType = "OPERAND_MEMORY";
406 let OperandType = "OPERAND_PCREL",
407 ParserMatchClass = X86AbsMemAsmOperand,
408 PrintMethod = "printPCRelImm" in {
409 def i32imm_pcrel : Operand<i32>;
410 def i16imm_pcrel : Operand<i16>;
412 def offset8 : Operand<i64>;
413 def offset16 : Operand<i64>;
414 def offset32 : Operand<i64>;
415 def offset64 : Operand<i64>;
417 // Branch targets have OtherVT type and print as pc-relative values.
418 def brtarget : Operand<OtherVT>;
419 def brtarget8 : Operand<OtherVT>;
423 def SSECC : Operand<i8> {
424 let PrintMethod = "printSSECC";
425 let OperandType = "OPERAND_IMMEDIATE";
428 def AVXCC : Operand<i8> {
429 let PrintMethod = "printAVXCC";
430 let OperandType = "OPERAND_IMMEDIATE";
433 class ImmSExtAsmOperandClass : AsmOperandClass {
434 let SuperClasses = [ImmAsmOperand];
435 let RenderMethod = "addImmOperands";
438 class ImmZExtAsmOperandClass : AsmOperandClass {
439 let SuperClasses = [ImmAsmOperand];
440 let RenderMethod = "addImmOperands";
443 // Sign-extended immediate classes. We don't need to define the full lattice
444 // here because there is no instruction with an ambiguity between ImmSExti64i32
447 // The strange ranges come from the fact that the assembler always works with
448 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
449 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
452 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
453 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
454 let Name = "ImmSExti64i32";
457 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
458 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
459 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
460 let Name = "ImmSExti16i8";
461 let SuperClasses = [ImmSExti64i32AsmOperand];
464 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
465 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
466 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
467 let Name = "ImmSExti32i8";
471 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
472 let Name = "ImmZExtu32u8";
477 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
478 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
479 let Name = "ImmSExti64i8";
480 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
481 ImmSExti64i32AsmOperand];
484 // A couple of more descriptive operand definitions.
485 // 16-bits but only 8 bits are significant.
486 def i16i8imm : Operand<i16> {
487 let ParserMatchClass = ImmSExti16i8AsmOperand;
488 let OperandType = "OPERAND_IMMEDIATE";
490 // 32-bits but only 8 bits are significant.
491 def i32i8imm : Operand<i32> {
492 let ParserMatchClass = ImmSExti32i8AsmOperand;
493 let OperandType = "OPERAND_IMMEDIATE";
495 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
496 def u32u8imm : Operand<i32> {
497 let ParserMatchClass = ImmZExtu32u8AsmOperand;
498 let OperandType = "OPERAND_IMMEDIATE";
501 // 64-bits but only 32 bits are significant.
502 def i64i32imm : Operand<i64> {
503 let ParserMatchClass = ImmSExti64i32AsmOperand;
504 let OperandType = "OPERAND_IMMEDIATE";
507 // 64-bits but only 32 bits are significant, and those bits are treated as being
509 def i64i32imm_pcrel : Operand<i64> {
510 let PrintMethod = "printPCRelImm";
511 let ParserMatchClass = X86AbsMemAsmOperand;
512 let OperandType = "OPERAND_PCREL";
515 // 64-bits but only 8 bits are significant.
516 def i64i8imm : Operand<i64> {
517 let ParserMatchClass = ImmSExti64i8AsmOperand;
518 let OperandType = "OPERAND_IMMEDIATE";
521 def lea64_32mem : Operand<i32> {
522 let PrintMethod = "printi32mem";
523 let AsmOperandLowerMethod = "lower_lea64_32mem";
524 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
525 let ParserMatchClass = X86MemAsmOperand;
528 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
529 def lea64mem : Operand<i64> {
530 let PrintMethod = "printi64mem";
531 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
532 let ParserMatchClass = X86MemAsmOperand;
536 //===----------------------------------------------------------------------===//
537 // X86 Complex Pattern Definitions.
540 // Define X86 specific addressing mode.
541 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
542 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
543 [add, sub, mul, X86mul_imm, shl, or, frameindex],
545 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
546 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
547 [add, sub, mul, X86mul_imm, shl, or,
548 frameindex, X86WrapperRIP],
551 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
552 [tglobaltlsaddr], []>;
554 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
555 [tglobaltlsaddr], []>;
557 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
558 [add, sub, mul, X86mul_imm, shl, or, frameindex,
561 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
562 [tglobaltlsaddr], []>;
564 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
565 [tglobaltlsaddr], []>;
567 //===----------------------------------------------------------------------===//
568 // X86 Instruction Predicate Definitions.
569 def HasCMov : Predicate<"Subtarget->hasCMov()">;
570 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
572 def HasMMX : Predicate<"Subtarget->hasMMX()">;
573 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
574 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
575 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
576 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
577 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
578 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
579 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
580 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
581 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
582 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
583 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
584 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
585 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
586 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
587 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
588 def HasAVX : Predicate<"Subtarget->hasAVX()">;
589 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
590 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
592 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
593 def HasAES : Predicate<"Subtarget->hasAES()">;
594 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
595 def HasFMA : Predicate<"Subtarget->hasFMA()">;
596 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
597 def HasXOP : Predicate<"Subtarget->hasXOP()">;
598 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
599 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
600 def HasF16C : Predicate<"Subtarget->hasF16C()">;
601 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
602 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
603 def HasBMI : Predicate<"Subtarget->hasBMI()">;
604 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
605 def HasRTM : Predicate<"Subtarget->hasRTM()">;
606 def HasADX : Predicate<"Subtarget->hasADX()">;
607 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
608 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
609 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
610 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
611 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
612 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
613 AssemblerPredicate<"!Mode64Bit", "32-bit mode">;
614 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
615 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
616 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
617 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
618 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
619 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
620 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
621 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
622 "TM.getCodeModel() != CodeModel::Kernel">;
623 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
624 "TM.getCodeModel() == CodeModel::Kernel">;
625 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
626 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
627 def OptForSize : Predicate<"OptForSize">;
628 def OptForSpeed : Predicate<"!OptForSize">;
629 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
630 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
632 //===----------------------------------------------------------------------===//
633 // X86 Instruction Format Definitions.
636 include "X86InstrFormats.td"
638 //===----------------------------------------------------------------------===//
639 // Pattern fragments.
642 // X86 specific condition code. These correspond to CondCode in
643 // X86InstrInfo.h. They must be kept in synch.
644 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
645 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
646 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
647 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
648 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
649 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
650 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
651 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
652 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
653 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
654 def X86_COND_NO : PatLeaf<(i8 10)>;
655 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
656 def X86_COND_NS : PatLeaf<(i8 12)>;
657 def X86_COND_O : PatLeaf<(i8 13)>;
658 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
659 def X86_COND_S : PatLeaf<(i8 15)>;
661 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
662 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
663 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
664 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
667 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
670 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
672 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
674 def i64immZExt32SExt8 : ImmLeaf<i64, [{
675 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
678 // Helper fragments for loads.
679 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
680 // known to be 32-bit aligned or better. Ditto for i8 to i16.
681 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
682 LoadSDNode *LD = cast<LoadSDNode>(N);
683 ISD::LoadExtType ExtType = LD->getExtensionType();
684 if (ExtType == ISD::NON_EXTLOAD)
686 if (ExtType == ISD::EXTLOAD)
687 return LD->getAlignment() >= 2 && !LD->isVolatile();
691 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
692 LoadSDNode *LD = cast<LoadSDNode>(N);
693 ISD::LoadExtType ExtType = LD->getExtensionType();
694 if (ExtType == ISD::EXTLOAD)
695 return LD->getAlignment() >= 2 && !LD->isVolatile();
699 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
700 LoadSDNode *LD = cast<LoadSDNode>(N);
701 ISD::LoadExtType ExtType = LD->getExtensionType();
702 if (ExtType == ISD::NON_EXTLOAD)
704 if (ExtType == ISD::EXTLOAD)
705 return LD->getAlignment() >= 4 && !LD->isVolatile();
709 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
710 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
711 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
712 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
713 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
715 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
716 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
717 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
718 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
719 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
720 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
722 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
723 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
724 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
725 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
726 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
727 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
728 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
729 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
730 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
731 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
733 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
734 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
735 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
736 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
737 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
738 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
739 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
740 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
741 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
742 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
745 // An 'and' node with a single use.
746 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
747 return N->hasOneUse();
749 // An 'srl' node with a single use.
750 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
751 return N->hasOneUse();
753 // An 'trunc' node with a single use.
754 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
755 return N->hasOneUse();
758 //===----------------------------------------------------------------------===//
763 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
764 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
765 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
766 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
767 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
768 "nop{l}\t$zero", [], IIC_NOP>, TB;
772 // Constructing a stack frame.
773 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
774 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
776 let SchedRW = [WriteALU] in {
777 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
778 def LEAVE : I<0xC9, RawFrm,
779 (outs), (ins), "leave", [], IIC_LEAVE>,
780 Requires<[In32BitMode]>;
782 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
783 def LEAVE64 : I<0xC9, RawFrm,
784 (outs), (ins), "leave", [], IIC_LEAVE>,
785 Requires<[In64BitMode]>;
788 //===----------------------------------------------------------------------===//
789 // Miscellaneous Instructions.
792 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
793 let mayLoad = 1, SchedRW = [WriteLoad] in {
794 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
795 IIC_POP_REG16>, OpSize;
796 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
798 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
799 IIC_POP_REG>, OpSize;
800 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
801 IIC_POP_MEM>, OpSize;
802 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
804 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
807 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
808 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
809 Requires<[In32BitMode]>;
810 } // mayLoad, SchedRW
812 let mayStore = 1, SchedRW = [WriteStore] in {
813 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
814 IIC_PUSH_REG>, OpSize;
815 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
817 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
818 IIC_PUSH_REG>, OpSize;
819 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
822 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
824 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
827 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
828 "push{l}\t$imm", [], IIC_PUSH_IMM>;
829 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
830 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
831 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
832 "push{l}\t$imm", [], IIC_PUSH_IMM>;
834 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
836 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
837 Requires<[In32BitMode]>;
839 } // mayStore, SchedRW
842 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
843 let mayLoad = 1, SchedRW = [WriteLoad] in {
844 def POP64r : I<0x58, AddRegFrm,
845 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
846 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
848 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
850 } // mayLoad, SchedRW
851 let mayStore = 1, SchedRW = [WriteStore] in {
852 def PUSH64r : I<0x50, AddRegFrm,
853 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
854 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
856 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
858 } // mayStore, SchedRW
861 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
862 SchedRW = [WriteStore] in {
863 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
864 "push{q}\t$imm", [], IIC_PUSH_IMM>;
865 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
866 "push{q}\t$imm", [], IIC_PUSH_IMM>;
867 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
868 "push{q}\t$imm", [], IIC_PUSH_IMM>;
871 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
872 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
873 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
874 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
875 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
876 Requires<[In64BitMode]>, Sched<[WriteStore]>;
878 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
879 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
880 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l|d}", [], IIC_POP_A>,
881 Requires<[In32BitMode]>;
883 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
884 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
885 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l|d}", [], IIC_PUSH_A>,
886 Requires<[In32BitMode]>;
889 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
891 def BSWAP32r : I<0xC8, AddRegFrm,
892 (outs GR32:$dst), (ins GR32:$src),
894 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
896 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
898 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
899 } // Constraints = "$src = $dst", SchedRW
901 // Bit scan instructions.
902 let Defs = [EFLAGS] in {
903 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
904 "bsf{w}\t{$src, $dst|$dst, $src}",
905 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
906 IIC_BSF>, TB, OpSize, Sched<[WriteShift]>;
907 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
908 "bsf{w}\t{$src, $dst|$dst, $src}",
909 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
910 IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>;
911 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
912 "bsf{l}\t{$src, $dst|$dst, $src}",
913 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB,
915 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
916 "bsf{l}\t{$src, $dst|$dst, $src}",
917 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
918 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
919 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
920 "bsf{q}\t{$src, $dst|$dst, $src}",
921 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
922 IIC_BSF>, TB, Sched<[WriteShift]>;
923 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
924 "bsf{q}\t{$src, $dst|$dst, $src}",
925 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
926 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
928 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
929 "bsr{w}\t{$src, $dst|$dst, $src}",
930 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
931 TB, OpSize, Sched<[WriteShift]>;
932 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
933 "bsr{w}\t{$src, $dst|$dst, $src}",
934 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
936 OpSize, Sched<[WriteShiftLd]>;
937 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
938 "bsr{l}\t{$src, $dst|$dst, $src}",
939 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB,
941 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
942 "bsr{l}\t{$src, $dst|$dst, $src}",
943 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
944 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
945 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
946 "bsr{q}\t{$src, $dst|$dst, $src}",
947 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB,
949 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
950 "bsr{q}\t{$src, $dst|$dst, $src}",
951 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
952 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
955 let SchedRW = [WriteMicrocoded] in {
956 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
957 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
958 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
959 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
960 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
961 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
964 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
965 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
966 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
967 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
968 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
969 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
970 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
971 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
972 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
974 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
975 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
976 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
977 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
979 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
980 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
981 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
982 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
985 //===----------------------------------------------------------------------===//
986 // Move Instructions.
988 let SchedRW = [WriteMove] in {
989 let neverHasSideEffects = 1 in {
990 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
991 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
992 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
993 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
994 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
995 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
996 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
997 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1000 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1001 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1002 "mov{b}\t{$src, $dst|$dst, $src}",
1003 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1004 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1005 "mov{w}\t{$src, $dst|$dst, $src}",
1006 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1007 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1008 "mov{l}\t{$src, $dst|$dst, $src}",
1009 [(set GR32:$dst, imm:$src)], IIC_MOV>;
1010 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1011 "movabs{q}\t{$src, $dst|$dst, $src}",
1012 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1013 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1014 "mov{q}\t{$src, $dst|$dst, $src}",
1015 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1019 let SchedRW = [WriteStore] in {
1020 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1021 "mov{b}\t{$src, $dst|$dst, $src}",
1022 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1023 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}",
1025 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1026 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1027 "mov{l}\t{$src, $dst|$dst, $src}",
1028 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1029 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1030 "mov{q}\t{$src, $dst|$dst, $src}",
1031 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1034 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1035 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1036 let SchedRW = [WriteALU] in {
1037 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1038 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1039 Requires<[In32BitMode]>;
1040 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1041 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1042 Requires<[In32BitMode]>;
1043 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1044 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1045 Requires<[In32BitMode]>;
1046 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1047 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1048 Requires<[In32BitMode]>;
1049 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1050 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1051 Requires<[In32BitMode]>;
1052 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1053 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1054 Requires<[In32BitMode]>;
1057 // FIXME: These definitions are utterly broken
1058 // Just leave them commented out for now because they're useless outside
1059 // of the large code model, and most compilers won't generate the instructions
1062 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1063 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1064 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1065 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1066 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1067 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1068 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1069 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1073 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
1074 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1075 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1076 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1077 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1078 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1079 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1080 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1081 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1084 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1085 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1086 "mov{b}\t{$src, $dst|$dst, $src}",
1087 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1088 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1089 "mov{w}\t{$src, $dst|$dst, $src}",
1090 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1091 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1092 "mov{l}\t{$src, $dst|$dst, $src}",
1093 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1094 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1095 "mov{q}\t{$src, $dst|$dst, $src}",
1096 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1099 let SchedRW = [WriteStore] in {
1100 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1101 "mov{b}\t{$src, $dst|$dst, $src}",
1102 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1103 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1104 "mov{w}\t{$src, $dst|$dst, $src}",
1105 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1106 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1107 "mov{l}\t{$src, $dst|$dst, $src}",
1108 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1109 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1110 "mov{q}\t{$src, $dst|$dst, $src}",
1111 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1114 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1115 // that they can be used for copying and storing h registers, which can't be
1116 // encoded when a REX prefix is present.
1117 let isCodeGenOnly = 1 in {
1118 let neverHasSideEffects = 1 in
1119 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1120 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1121 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1124 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1125 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1126 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1127 IIC_MOV_MEM>, Sched<[WriteStore]>;
1128 let mayLoad = 1, neverHasSideEffects = 1,
1129 canFoldAsLoad = 1, isReMaterializable = 1 in
1130 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1131 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1132 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1133 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1137 // Condition code ops, incl. set if equal/not equal/...
1138 let SchedRW = [WriteALU] in {
1139 let Defs = [EFLAGS], Uses = [AH] in
1140 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1141 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1142 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1143 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1144 IIC_AHF>; // AH = flags
1147 //===----------------------------------------------------------------------===//
1148 // Bit tests instructions: BT, BTS, BTR, BTC.
1150 let Defs = [EFLAGS] in {
1151 let SchedRW = [WriteALU] in {
1152 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1153 "bt{w}\t{$src2, $src1|$src1, $src2}",
1154 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1156 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1157 "bt{l}\t{$src2, $src1|$src1, $src2}",
1158 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1159 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1160 "bt{q}\t{$src2, $src1|$src1, $src2}",
1161 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1164 // Unlike with the register+register form, the memory+register form of the
1165 // bt instruction does not ignore the high bits of the index. From ISel's
1166 // perspective, this is pretty bizarre. Make these instructions disassembly
1169 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1170 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1171 "bt{w}\t{$src2, $src1|$src1, $src2}",
1172 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1173 // (implicit EFLAGS)]
1175 >, OpSize, TB, Requires<[FastBTMem]>;
1176 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1177 "bt{l}\t{$src2, $src1|$src1, $src2}",
1178 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1179 // (implicit EFLAGS)]
1181 >, TB, Requires<[FastBTMem]>;
1182 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1183 "bt{q}\t{$src2, $src1|$src1, $src2}",
1184 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1185 // (implicit EFLAGS)]
1190 let SchedRW = [WriteALU] in {
1191 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1192 "bt{w}\t{$src2, $src1|$src1, $src2}",
1193 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1194 IIC_BT_RI>, OpSize, TB;
1195 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1196 "bt{l}\t{$src2, $src1|$src1, $src2}",
1197 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1199 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1200 "bt{q}\t{$src2, $src1|$src1, $src2}",
1201 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1205 // Note that these instructions don't need FastBTMem because that
1206 // only applies when the other operand is in a register. When it's
1207 // an immediate, bt is still fast.
1208 let SchedRW = [WriteALU] in {
1209 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1210 "bt{w}\t{$src2, $src1|$src1, $src2}",
1211 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1212 ], IIC_BT_MI>, OpSize, TB;
1213 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1214 "bt{l}\t{$src2, $src1|$src1, $src2}",
1215 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1217 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1218 "bt{q}\t{$src2, $src1|$src1, $src2}",
1219 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1220 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1223 let hasSideEffects = 0 in {
1224 let SchedRW = [WriteALU] in {
1225 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1226 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1228 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1229 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1230 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1231 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1234 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1235 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1236 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1238 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1239 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1240 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1241 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1244 let SchedRW = [WriteALU] in {
1245 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1246 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1248 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1249 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1250 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1251 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1254 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1255 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1256 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1258 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1259 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1260 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1261 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1264 let SchedRW = [WriteALU] in {
1265 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1266 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1268 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1269 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1270 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1271 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1274 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1275 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1276 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1278 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1279 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1280 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1281 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1284 let SchedRW = [WriteALU] in {
1285 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1286 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1288 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1289 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1290 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1291 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1294 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1295 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1296 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1298 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1299 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1300 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1301 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1304 let SchedRW = [WriteALU] in {
1305 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1306 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1308 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1309 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1310 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1311 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1314 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1315 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1316 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1318 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1319 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1320 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1321 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1324 let SchedRW = [WriteALU] in {
1325 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1326 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1328 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1329 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1330 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1331 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1334 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1335 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1336 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1338 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1339 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1340 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1341 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1343 } // hasSideEffects = 0
1344 } // Defs = [EFLAGS]
1347 //===----------------------------------------------------------------------===//
1351 // Atomic swap. These are just normal xchg instructions. But since a memory
1352 // operand is referenced, the atomicity is ensured.
1353 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1354 InstrItinClass itin> {
1355 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1356 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1357 (ins GR8:$val, i8mem:$ptr),
1358 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1361 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1363 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1364 (ins GR16:$val, i16mem:$ptr),
1365 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1368 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1370 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1371 (ins GR32:$val, i32mem:$ptr),
1372 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1375 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1377 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1378 (ins GR64:$val, i64mem:$ptr),
1379 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1382 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1387 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1389 // Swap between registers.
1390 let SchedRW = [WriteALU] in {
1391 let Constraints = "$val = $dst" in {
1392 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1393 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1394 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1395 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1396 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1397 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1398 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1399 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1402 // Swap between EAX and other registers.
1403 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1404 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1405 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1406 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1407 Requires<[In32BitMode]>;
1408 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1409 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1410 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1411 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1412 Requires<[In64BitMode]>;
1413 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1414 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1417 let SchedRW = [WriteALU] in {
1418 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1419 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1420 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1421 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1423 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1424 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1425 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1426 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1429 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1430 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1431 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1432 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1433 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1435 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1436 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1437 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1438 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1442 let SchedRW = [WriteALU] in {
1443 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1444 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1445 IIC_CMPXCHG_REG8>, TB;
1446 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1447 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1448 IIC_CMPXCHG_REG>, TB, OpSize;
1449 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1450 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1451 IIC_CMPXCHG_REG>, TB;
1452 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1453 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1454 IIC_CMPXCHG_REG>, TB;
1457 let SchedRW = [WriteALULd, WriteRMW] in {
1458 let mayLoad = 1, mayStore = 1 in {
1459 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1460 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1461 IIC_CMPXCHG_MEM8>, TB;
1462 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1463 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1464 IIC_CMPXCHG_MEM>, TB, OpSize;
1465 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1466 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1467 IIC_CMPXCHG_MEM>, TB;
1468 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1469 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1470 IIC_CMPXCHG_MEM>, TB;
1473 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1474 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1475 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1477 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1478 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1479 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1480 TB, Requires<[HasCmpxchg16b]>;
1484 // Lock instruction prefix
1485 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1487 // Rex64 instruction prefix
1488 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1490 // Data16 instruction prefix
1491 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1493 // Repeat string operation instruction prefixes
1494 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1495 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1496 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1497 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1498 // Repeat while not equal (used with CMPS and SCAS)
1499 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1503 // String manipulation instructions
1504 let SchedRW = [WriteMicrocoded] in {
1505 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1506 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1507 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1508 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1511 let SchedRW = [WriteSystem] in {
1512 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1513 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1514 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1517 // Flag instructions
1518 let SchedRW = [WriteALU] in {
1519 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1520 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1521 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1522 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1523 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1524 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1525 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1527 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1530 // Table lookup instructions
1531 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1534 let SchedRW = [WriteMicrocoded] in {
1535 // ASCII Adjust After Addition
1536 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1537 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1538 Requires<[In32BitMode]>;
1540 // ASCII Adjust AX Before Division
1541 // sets AL, AH and EFLAGS and uses AL and AH
1542 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1543 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1545 // ASCII Adjust AX After Multiply
1546 // sets AL, AH and EFLAGS and uses AL
1547 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1548 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1550 // ASCII Adjust AL After Subtraction - sets
1551 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1552 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1553 Requires<[In32BitMode]>;
1555 // Decimal Adjust AL after Addition
1556 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1557 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1558 Requires<[In32BitMode]>;
1560 // Decimal Adjust AL after Subtraction
1561 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1562 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1563 Requires<[In32BitMode]>;
1566 let SchedRW = [WriteSystem] in {
1567 // Check Array Index Against Bounds
1568 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1569 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1570 Requires<[In32BitMode]>;
1571 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1572 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1573 Requires<[In32BitMode]>;
1575 // Adjust RPL Field of Segment Selector
1576 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1577 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1578 Requires<[In32BitMode]>;
1579 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1580 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1581 Requires<[In32BitMode]>;
1584 //===----------------------------------------------------------------------===//
1585 // MOVBE Instructions
1587 let Predicates = [HasMOVBE] in {
1588 let SchedRW = [WriteALULd] in {
1589 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1590 "movbe{w}\t{$src, $dst|$dst, $src}",
1591 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1593 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1594 "movbe{l}\t{$src, $dst|$dst, $src}",
1595 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1597 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1598 "movbe{q}\t{$src, $dst|$dst, $src}",
1599 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1602 let SchedRW = [WriteStore] in {
1603 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1604 "movbe{w}\t{$src, $dst|$dst, $src}",
1605 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1607 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1608 "movbe{l}\t{$src, $dst|$dst, $src}",
1609 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1611 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1612 "movbe{q}\t{$src, $dst|$dst, $src}",
1613 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1618 //===----------------------------------------------------------------------===//
1619 // RDRAND Instruction
1621 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1622 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1624 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1625 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1627 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1628 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1630 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1633 //===----------------------------------------------------------------------===//
1634 // LZCNT Instruction
1636 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1637 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1638 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1639 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1641 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1642 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1643 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1644 (implicit EFLAGS)]>, XS, OpSize;
1646 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1647 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1648 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1649 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1650 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1651 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1652 (implicit EFLAGS)]>, XS;
1654 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1655 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1656 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1658 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1659 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1660 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1661 (implicit EFLAGS)]>, XS;
1664 //===----------------------------------------------------------------------===//
1667 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1668 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1669 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1670 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1672 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1673 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1674 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1675 (implicit EFLAGS)]>, XS, OpSize;
1677 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1678 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1679 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1680 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1681 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1682 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1683 (implicit EFLAGS)]>, XS;
1685 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1686 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1687 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1689 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1690 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1691 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1692 (implicit EFLAGS)]>, XS;
1695 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1696 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1698 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1699 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1700 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1701 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1702 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1703 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1707 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1708 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1710 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1711 X86blsr, loadi64>, VEX_W;
1712 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1713 X86blsmsk, loadi32>;
1714 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1715 X86blsmsk, loadi64>, VEX_W;
1716 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1718 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1719 X86blsi, loadi64>, VEX_W;
1722 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1723 X86MemOperand x86memop, Intrinsic Int,
1725 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1726 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1727 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1729 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1730 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1731 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1732 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1735 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1736 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1737 int_x86_bmi_bextr_32, loadi32>;
1738 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1739 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1742 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1743 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1744 int_x86_bmi_bzhi_32, loadi32>;
1745 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1746 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1749 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1750 X86MemOperand x86memop, Intrinsic Int,
1752 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1753 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1754 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1756 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1757 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1758 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1761 let Predicates = [HasBMI2] in {
1762 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1763 int_x86_bmi_pdep_32, loadi32>, T8XD;
1764 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1765 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1766 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1767 int_x86_bmi_pext_32, loadi32>, T8XS;
1768 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1769 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1772 //===----------------------------------------------------------------------===//
1774 //===----------------------------------------------------------------------===//
1776 include "X86InstrArithmetic.td"
1777 include "X86InstrCMovSetCC.td"
1778 include "X86InstrExtension.td"
1779 include "X86InstrControl.td"
1780 include "X86InstrShiftRotate.td"
1782 // X87 Floating Point Stack.
1783 include "X86InstrFPStack.td"
1785 // SIMD support (SSE, MMX and AVX)
1786 include "X86InstrFragmentsSIMD.td"
1788 // FMA - Fused Multiply-Add support (requires FMA)
1789 include "X86InstrFMA.td"
1792 include "X86InstrXOP.td"
1794 // SSE, MMX and 3DNow! vector support.
1795 include "X86InstrSSE.td"
1796 include "X86InstrMMX.td"
1797 include "X86Instr3DNow.td"
1799 include "X86InstrVMX.td"
1800 include "X86InstrSVM.td"
1802 include "X86InstrTSX.td"
1804 // System instructions.
1805 include "X86InstrSystem.td"
1807 // Compiler Pseudo Instructions and Pat Patterns
1808 include "X86InstrCompiler.td"
1810 //===----------------------------------------------------------------------===//
1811 // Assembler Mnemonic Aliases
1812 //===----------------------------------------------------------------------===//
1814 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1815 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1817 def : MnemonicAlias<"cbw", "cbtw">;
1818 def : MnemonicAlias<"cwde", "cwtl">;
1819 def : MnemonicAlias<"cwd", "cwtd">;
1820 def : MnemonicAlias<"cdq", "cltd">;
1821 def : MnemonicAlias<"cdqe", "cltq">;
1822 def : MnemonicAlias<"cqo", "cqto">;
1824 // lret maps to lretl, it is not ambiguous with lretq.
1825 def : MnemonicAlias<"lret", "lretl">;
1827 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1828 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1830 def : MnemonicAlias<"loopz", "loope">;
1831 def : MnemonicAlias<"loopnz", "loopne">;
1833 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1834 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1835 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1836 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1837 def : MnemonicAlias<"popfd", "popfl">;
1839 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1840 // all modes. However: "push (addr)" and "push $42" should default to
1841 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1842 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1843 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1844 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1845 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1846 def : MnemonicAlias<"pushfd", "pushfl">;
1848 def : MnemonicAlias<"repe", "rep">;
1849 def : MnemonicAlias<"repz", "rep">;
1850 def : MnemonicAlias<"repnz", "repne">;
1852 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1853 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1855 def : MnemonicAlias<"salb", "shlb">;
1856 def : MnemonicAlias<"salw", "shlw">;
1857 def : MnemonicAlias<"sall", "shll">;
1858 def : MnemonicAlias<"salq", "shlq">;
1860 def : MnemonicAlias<"smovb", "movsb">;
1861 def : MnemonicAlias<"smovw", "movsw">;
1862 def : MnemonicAlias<"smovl", "movsl">;
1863 def : MnemonicAlias<"smovq", "movsq">;
1865 def : MnemonicAlias<"ud2a", "ud2">;
1866 def : MnemonicAlias<"verrw", "verr">;
1868 // System instruction aliases.
1869 def : MnemonicAlias<"iret", "iretl">;
1870 def : MnemonicAlias<"sysret", "sysretl">;
1871 def : MnemonicAlias<"sysexit", "sysexitl">;
1873 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1874 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1875 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1876 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1877 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1878 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1879 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1880 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1883 // Floating point stack aliases.
1884 def : MnemonicAlias<"fcmovz", "fcmove">;
1885 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1886 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1887 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1888 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1889 def : MnemonicAlias<"fcomip", "fcompi">;
1890 def : MnemonicAlias<"fildq", "fildll">;
1891 def : MnemonicAlias<"fistpq", "fistpll">;
1892 def : MnemonicAlias<"fisttpq", "fisttpll">;
1893 def : MnemonicAlias<"fldcww", "fldcw">;
1894 def : MnemonicAlias<"fnstcww", "fnstcw">;
1895 def : MnemonicAlias<"fnstsww", "fnstsw">;
1896 def : MnemonicAlias<"fucomip", "fucompi">;
1897 def : MnemonicAlias<"fwait", "wait">;
1900 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1901 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1902 !strconcat(Prefix, NewCond, Suffix)>;
1904 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1905 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1906 /// example "setz" -> "sete".
1907 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1908 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1909 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1910 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1911 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1912 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1913 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1914 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1915 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1916 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1917 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1919 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1920 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1921 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1922 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1925 // Aliases for set<CC>
1926 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1927 // Aliases for j<CC>
1928 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1929 // Aliases for cmov<CC>{w,l,q}
1930 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1931 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1932 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1935 //===----------------------------------------------------------------------===//
1936 // Assembler Instruction Aliases
1937 //===----------------------------------------------------------------------===//
1939 // aad/aam default to base 10 if no operand is specified.
1940 def : InstAlias<"aad", (AAD8i8 10)>;
1941 def : InstAlias<"aam", (AAM8i8 10)>;
1943 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1944 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1947 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1948 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1949 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1950 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1952 // div and idiv aliases for explicit A register.
1953 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1954 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1955 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1956 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1957 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1958 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1959 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1960 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1961 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1962 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1963 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1964 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1965 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1966 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1967 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1968 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1972 // Various unary fpstack operations default to operating on on ST1.
1973 // For example, "fxch" -> "fxch %st(1)"
1974 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1975 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1976 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1977 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1978 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1979 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1980 def : InstAlias<"fxch", (XCH_F ST1)>;
1981 def : InstAlias<"fcom", (COM_FST0r ST1)>;
1982 def : InstAlias<"fcomp", (COMP_FST0r ST1)>;
1983 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1984 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1985 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1986 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1987 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1988 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1990 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1991 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1992 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1994 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1995 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1996 (Inst RST:$op), EmitAlias>;
1997 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1998 (Inst ST0), EmitAlias>;
2001 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2002 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2003 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2004 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
2005 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2006 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
2007 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2008 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2009 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2010 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
2011 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2012 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
2013 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2014 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2015 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2016 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2019 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2020 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2021 // solely because gas supports it.
2022 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
2023 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
2024 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
2025 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
2026 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
2027 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
2029 // We accept "fnstsw %eax" even though it only writes %ax.
2030 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
2031 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
2032 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2034 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2035 // this is compatible with what GAS does.
2036 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2037 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2038 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
2039 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
2041 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2042 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2043 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2044 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2045 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2046 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2047 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2049 // inb %dx -> inb %al, %dx
2050 def : InstAlias<"inb %dx", (IN8rr)>;
2051 def : InstAlias<"inw %dx", (IN16rr)>;
2052 def : InstAlias<"inl %dx", (IN32rr)>;
2053 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
2054 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
2055 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
2058 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2059 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2060 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2061 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2062 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2063 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2064 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2066 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2067 // the move. All segment/mem forms are equivalent, this has the shortest
2069 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2070 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2072 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2073 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2075 // Match 'movq GR64, MMX' as an alias for movd.
2076 def : InstAlias<"movq $src, $dst",
2077 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2078 def : InstAlias<"movq $src, $dst",
2079 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2081 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2082 // alias for movsl. (as in rep; movsd)
2083 def : InstAlias<"movsd", (MOVSD)>;
2086 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2087 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2088 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2089 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2090 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2091 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2092 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2095 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2096 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2097 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2098 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2099 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2100 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2101 // Note: No GR32->GR64 movzx form.
2103 // outb %dx -> outb %al, %dx
2104 def : InstAlias<"outb %dx", (OUT8rr)>;
2105 def : InstAlias<"outw %dx", (OUT16rr)>;
2106 def : InstAlias<"outl %dx", (OUT32rr)>;
2107 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
2108 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
2109 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
2111 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2112 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2113 // errors, since its encoding is the most compact.
2114 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2116 // shld/shrd op,op -> shld op, op, CL
2117 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
2118 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
2119 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
2120 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
2121 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
2122 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
2124 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
2125 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
2126 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
2127 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
2128 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
2129 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2131 /* FIXME: This is disabled because the asm matcher is currently incapable of
2132 * matching a fixed immediate like $1.
2133 // "shl X, $1" is an alias for "shl X".
2134 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2135 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2136 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2137 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2138 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2139 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2140 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2141 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2142 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2143 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2144 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2145 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2146 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2147 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2148 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2149 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2150 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2153 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2154 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2155 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2156 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2159 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2160 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2161 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2162 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2163 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2165 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2166 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2167 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2168 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2169 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2171 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2172 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2173 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2174 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2175 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;