1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
84 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
85 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
86 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
88 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
89 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
91 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
92 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
94 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
95 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
97 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
100 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
103 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
125 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
127 def X86vastart_save_xmm_regs :
128 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
129 SDT_X86VASTART_SAVE_XMM_REGS,
130 [SDNPHasChain, SDNPVariadic]>;
132 def X86callseq_start :
133 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
134 [SDNPHasChain, SDNPOutFlag]>;
136 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
137 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
139 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
140 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
143 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
145 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
146 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
149 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
150 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
152 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
153 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
155 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
156 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
157 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
158 SDT_X86SegmentBaseAddress, []>;
160 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
163 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
164 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
166 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
168 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
169 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
171 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
174 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
175 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
176 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
178 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
180 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
183 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
185 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
186 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
188 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
191 //===----------------------------------------------------------------------===//
192 // X86 Operand Definitions.
195 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
196 // the index operand of an address, to conform to x86 encoding restrictions.
197 def ptr_rc_nosp : PointerLikeRegClass<1>;
199 // *mem - Operand definitions for the funky X86 addressing mode operands.
201 def X86MemAsmOperand : AsmOperandClass {
203 let SuperClasses = [];
205 def X86AbsMemAsmOperand : AsmOperandClass {
207 let SuperClasses = [X86MemAsmOperand];
209 class X86MemOperand<string printMethod> : Operand<iPTR> {
210 let PrintMethod = printMethod;
211 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
212 let ParserMatchClass = X86MemAsmOperand;
215 def opaque32mem : X86MemOperand<"printopaquemem">;
216 def opaque48mem : X86MemOperand<"printopaquemem">;
217 def opaque80mem : X86MemOperand<"printopaquemem">;
218 def opaque512mem : X86MemOperand<"printopaquemem">;
220 def i8mem : X86MemOperand<"printi8mem">;
221 def i16mem : X86MemOperand<"printi16mem">;
222 def i32mem : X86MemOperand<"printi32mem">;
223 def i64mem : X86MemOperand<"printi64mem">;
224 def i128mem : X86MemOperand<"printi128mem">;
225 //def i256mem : X86MemOperand<"printi256mem">;
226 def f32mem : X86MemOperand<"printf32mem">;
227 def f64mem : X86MemOperand<"printf64mem">;
228 def f80mem : X86MemOperand<"printf80mem">;
229 def f128mem : X86MemOperand<"printf128mem">;
230 def f256mem : X86MemOperand<"printf256mem">;
232 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
233 // plain GR64, so that it doesn't potentially require a REX prefix.
234 def i8mem_NOREX : Operand<i64> {
235 let PrintMethod = "printi8mem";
236 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
237 let ParserMatchClass = X86MemAsmOperand;
240 // Special i32mem for addresses of load folding tail calls. These are not
241 // allowed to use callee-saved registers since they must be scheduled
242 // after callee-saved register are popped.
243 def i32mem_TC : Operand<i32> {
244 let PrintMethod = "printi32mem";
245 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
246 let ParserMatchClass = X86MemAsmOperand;
250 let ParserMatchClass = X86AbsMemAsmOperand,
251 PrintMethod = "print_pcrel_imm" in {
252 def i32imm_pcrel : Operand<i32>;
253 def i16imm_pcrel : Operand<i16>;
255 def offset8 : Operand<i64>;
256 def offset16 : Operand<i64>;
257 def offset32 : Operand<i64>;
258 def offset64 : Operand<i64>;
260 // Branch targets have OtherVT type and print as pc-relative values.
261 def brtarget : Operand<OtherVT>;
262 def brtarget8 : Operand<OtherVT>;
266 def SSECC : Operand<i8> {
267 let PrintMethod = "printSSECC";
270 class ImmSExtAsmOperandClass : AsmOperandClass {
271 let SuperClasses = [ImmAsmOperand];
272 let RenderMethod = "addImmOperands";
275 // Sign-extended immediate classes. We don't need to define the full lattice
276 // here because there is no instruction with an ambiguity between ImmSExti64i32
279 // The strange ranges come from the fact that the assembler always works with
280 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
281 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
284 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
285 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
286 let Name = "ImmSExti64i32";
289 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
290 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
291 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
292 let Name = "ImmSExti16i8";
293 let SuperClasses = [ImmSExti64i32AsmOperand];
296 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
297 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
298 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
299 let Name = "ImmSExti32i8";
303 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
304 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
305 let Name = "ImmSExti64i8";
306 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
307 ImmSExti64i32AsmOperand];
310 // A couple of more descriptive operand definitions.
311 // 16-bits but only 8 bits are significant.
312 def i16i8imm : Operand<i16> {
313 let ParserMatchClass = ImmSExti16i8AsmOperand;
315 // 32-bits but only 8 bits are significant.
316 def i32i8imm : Operand<i32> {
317 let ParserMatchClass = ImmSExti32i8AsmOperand;
320 //===----------------------------------------------------------------------===//
321 // X86 Complex Pattern Definitions.
324 // Define X86 specific addressing mode.
325 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
326 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
327 [add, sub, mul, X86mul_imm, shl, or, frameindex],
329 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
330 [tglobaltlsaddr], []>;
332 //===----------------------------------------------------------------------===//
333 // X86 Instruction Predicate Definitions.
334 def HasCMov : Predicate<"Subtarget->hasCMov()">;
335 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
336 def HasMMX : Predicate<"Subtarget->hasMMX()">;
337 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
338 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
339 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
340 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
341 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
342 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
343 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
344 def HasAVX : Predicate<"Subtarget->hasAVX()">;
345 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
346 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
347 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
348 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
349 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
350 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
351 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
352 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
353 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
354 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
355 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
356 "TM.getCodeModel() != CodeModel::Kernel">;
357 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
358 "TM.getCodeModel() == CodeModel::Kernel">;
359 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
360 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
361 def OptForSize : Predicate<"OptForSize">;
362 def OptForSpeed : Predicate<"!OptForSize">;
363 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
364 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
365 def HasAES : Predicate<"Subtarget->hasAES()">;
367 //===----------------------------------------------------------------------===//
368 // X86 Instruction Format Definitions.
371 include "X86InstrFormats.td"
373 //===----------------------------------------------------------------------===//
374 // Pattern fragments...
377 // X86 specific condition code. These correspond to CondCode in
378 // X86InstrInfo.h. They must be kept in synch.
379 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
380 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
381 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
382 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
383 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
384 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
385 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
386 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
387 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
388 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
389 def X86_COND_NO : PatLeaf<(i8 10)>;
390 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
391 def X86_COND_NS : PatLeaf<(i8 12)>;
392 def X86_COND_O : PatLeaf<(i8 13)>;
393 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
394 def X86_COND_S : PatLeaf<(i8 15)>;
396 def immSext8 : PatLeaf<(imm), [{
397 return N->getSExtValue() == (int8_t)N->getSExtValue();
400 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
401 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
403 /// Load patterns: these constraint the match to the right address space.
404 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
405 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
406 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
407 if (PT->getAddressSpace() > 255)
412 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 return PT->getAddressSpace() == 256;
419 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 return PT->getAddressSpace() == 257;
427 // Helper fragments for loads.
428 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
429 // known to be 32-bit aligned or better. Ditto for i8 to i16.
430 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
431 LoadSDNode *LD = cast<LoadSDNode>(N);
432 if (const Value *Src = LD->getSrcValue())
433 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
434 if (PT->getAddressSpace() > 255)
436 ISD::LoadExtType ExtType = LD->getExtensionType();
437 if (ExtType == ISD::NON_EXTLOAD)
439 if (ExtType == ISD::EXTLOAD)
440 return LD->getAlignment() >= 2 && !LD->isVolatile();
444 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
445 LoadSDNode *LD = cast<LoadSDNode>(N);
446 if (const Value *Src = LD->getSrcValue())
447 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
448 if (PT->getAddressSpace() > 255)
450 ISD::LoadExtType ExtType = LD->getExtensionType();
451 if (ExtType == ISD::EXTLOAD)
452 return LD->getAlignment() >= 2 && !LD->isVolatile();
456 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
457 LoadSDNode *LD = cast<LoadSDNode>(N);
458 if (const Value *Src = LD->getSrcValue())
459 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
460 if (PT->getAddressSpace() > 255)
462 ISD::LoadExtType ExtType = LD->getExtensionType();
463 if (ExtType == ISD::NON_EXTLOAD)
465 if (ExtType == ISD::EXTLOAD)
466 return LD->getAlignment() >= 4 && !LD->isVolatile();
470 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
471 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
472 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
473 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
474 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
476 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
477 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
478 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
480 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
481 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
482 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
483 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
484 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
485 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
487 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
488 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
489 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
490 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
491 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
492 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
495 // An 'and' node with a single use.
496 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
497 return N->hasOneUse();
499 // An 'srl' node with a single use.
500 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
501 return N->hasOneUse();
503 // An 'trunc' node with a single use.
504 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
505 return N->hasOneUse();
508 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
509 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
510 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
511 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
513 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
514 APInt Mask = APInt::getAllOnesValue(BitWidth);
515 APInt KnownZero0, KnownOne0;
516 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
517 APInt KnownZero1, KnownOne1;
518 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
519 return (~KnownZero0 & ~KnownZero1) == 0;
522 //===----------------------------------------------------------------------===//
523 // Instruction list...
526 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
527 // a stack adjustment and the codegen must know that they may modify the stack
528 // pointer before prolog-epilog rewriting occurs.
529 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
530 // sub / add which can clobber EFLAGS.
531 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
532 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
534 [(X86callseq_start timm:$amt)]>,
535 Requires<[In32BitMode]>;
536 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
538 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
539 Requires<[In32BitMode]>;
542 // x86-64 va_start lowering magic.
543 let usesCustomInserter = 1 in {
544 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
547 i64imm:$regsavefi, i64imm:$offset,
549 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
550 [(X86vastart_save_xmm_regs GR8:$al,
554 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
555 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
556 // one go. Touching the stack at 4K increments is necessary to ensure that the
557 // guard pages used by the OS virtual memory manager are allocated in correct
559 // The main point of having separate instruction are extra unmodelled effects
560 // (compared to ordinary calls) like stack pointer change.
562 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
563 "# dynamic stack allocation",
568 let neverHasSideEffects = 1 in {
569 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
570 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
571 "nop{w}\t$zero", []>, TB, OpSize;
572 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
573 "nop{l}\t$zero", []>, TB;
577 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
578 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
579 // FIXME: need to make sure that "int $3" matches int3
580 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
581 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
582 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
584 // PIC base construction. This expands to code that looks like this:
587 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
588 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
591 //===----------------------------------------------------------------------===//
592 // Control Flow Instructions.
595 // Return instructions.
596 let isTerminator = 1, isReturn = 1, isBarrier = 1,
597 hasCtrlDep = 1, FPForm = SpecialFP in {
598 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
601 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
603 [(X86retflag timm:$amt)]>;
604 def LRET : I <0xCB, RawFrm, (outs), (ins),
606 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
610 // Unconditional branches.
611 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
612 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
613 "jmp\t$dst", [(br bb:$dst)]>;
614 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
618 // Conditional Branches.
619 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
620 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
621 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
622 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
623 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
627 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
628 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
629 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
630 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
631 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
632 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
633 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
634 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
635 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
636 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
637 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
638 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
639 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
640 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
641 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
642 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
644 // FIXME: What about the CX/RCX versions of this instruction?
645 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
646 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
651 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
652 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
653 [(brind GR32:$dst)]>;
654 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
655 [(brind (loadi32 addr:$dst))]>;
657 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
658 (ins i16imm:$seg, i16imm:$off),
659 "ljmp{w}\t$seg, $off", []>, OpSize;
660 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
661 (ins i16imm:$seg, i32imm:$off),
662 "ljmp{l}\t$seg, $off", []>;
664 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
665 "ljmp{w}\t{*}$dst", []>, OpSize;
666 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
667 "ljmp{l}\t{*}$dst", []>;
673 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
674 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
675 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
677 //===----------------------------------------------------------------------===//
678 // Call Instructions...
681 // All calls clobber the non-callee saved registers. ESP is marked as
682 // a use to prevent stack-pointer assignments that appear immediately
683 // before calls from potentially appearing dead. Uses for argument
684 // registers are added manually.
685 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
686 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
687 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
688 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
690 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
691 (outs), (ins i32imm_pcrel:$dst,variable_ops),
693 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
694 "call\t{*}$dst", [(X86call GR32:$dst)]>;
695 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
696 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
698 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
699 (ins i16imm:$seg, i16imm:$off),
700 "lcall{w}\t$seg, $off", []>, OpSize;
701 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
702 (ins i16imm:$seg, i32imm:$off),
703 "lcall{l}\t$seg, $off", []>;
705 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
706 "lcall{w}\t{*}$dst", []>, OpSize;
707 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
708 "lcall{l}\t{*}$dst", []>;
710 // callw for 16 bit code for the assembler.
711 let isAsmParserOnly = 1 in
712 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
713 (outs), (ins i16imm_pcrel:$dst, variable_ops),
714 "callw\t$dst", []>, OpSize;
717 // Constructing a stack frame.
719 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
720 "enter\t$len, $lvl", []>;
724 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
726 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
727 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
728 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
729 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
731 def TCRETURNdi : I<0, Pseudo, (outs),
732 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
733 "#TC_RETURN $dst $offset", []>;
734 def TCRETURNri : I<0, Pseudo, (outs),
735 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
736 "#TC_RETURN $dst $offset", []>;
738 def TCRETURNmi : I<0, Pseudo, (outs),
739 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
740 "#TC_RETURN $dst $offset", []>;
742 // FIXME: The should be pseudo instructions that are lowered when going to
744 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
745 (ins i32imm_pcrel:$dst, variable_ops),
746 "jmp\t$dst # TAILCALL",
748 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
749 "", []>; // FIXME: Remove encoding when JIT is dead.
751 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
752 "jmp{l}\t{*}$dst # TAILCALL", []>;
755 //===----------------------------------------------------------------------===//
756 // Miscellaneous Instructions...
758 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
759 def LEAVE : I<0xC9, RawFrm,
760 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
762 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
763 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
765 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
766 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
767 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
768 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
770 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
771 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
773 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
775 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
777 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
778 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
780 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
782 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
783 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
786 let mayStore = 1 in {
787 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
789 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
790 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
792 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
794 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
795 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
799 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
800 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
801 "push{l}\t$imm", []>;
802 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
803 "push{w}\t$imm", []>, OpSize;
804 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
805 "push{l}\t$imm", []>;
808 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
809 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
810 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
811 Requires<[In32BitMode]>;
813 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
814 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
815 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
816 Requires<[In32BitMode]>;
819 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
820 mayLoad=1, neverHasSideEffects=1 in {
821 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
822 Requires<[In32BitMode]>;
824 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
825 mayStore=1, neverHasSideEffects=1 in {
826 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
827 Requires<[In32BitMode]>;
830 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
831 def BSWAP32r : I<0xC8, AddRegFrm,
832 (outs GR32:$dst), (ins GR32:$src),
834 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
837 // Bit scan instructions.
838 let Defs = [EFLAGS] in {
839 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
840 "bsf{w}\t{$src, $dst|$dst, $src}",
841 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
842 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
843 "bsf{w}\t{$src, $dst|$dst, $src}",
844 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
846 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
847 "bsf{l}\t{$src, $dst|$dst, $src}",
848 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
849 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
850 "bsf{l}\t{$src, $dst|$dst, $src}",
851 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
853 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
854 "bsr{w}\t{$src, $dst|$dst, $src}",
855 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
856 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
857 "bsr{w}\t{$src, $dst|$dst, $src}",
858 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
860 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
861 "bsr{l}\t{$src, $dst|$dst, $src}",
862 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
863 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
864 "bsr{l}\t{$src, $dst|$dst, $src}",
865 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
868 let neverHasSideEffects = 1 in
869 def LEA16r : I<0x8D, MRMSrcMem,
870 (outs GR16:$dst), (ins i32mem:$src),
871 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
872 let isReMaterializable = 1 in
873 def LEA32r : I<0x8D, MRMSrcMem,
874 (outs GR32:$dst), (ins i32mem:$src),
875 "lea{l}\t{$src|$dst}, {$dst|$src}",
876 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
878 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
879 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
880 [(X86rep_movs i8)]>, REP;
881 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
882 [(X86rep_movs i16)]>, REP, OpSize;
883 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
884 [(X86rep_movs i32)]>, REP;
887 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
888 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
889 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
890 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
891 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
894 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
895 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
896 [(X86rep_stos i8)]>, REP;
897 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
898 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
899 [(X86rep_stos i16)]>, REP, OpSize;
900 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
901 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
902 [(X86rep_stos i32)]>, REP;
904 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
905 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
906 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
907 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
908 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
909 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
910 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
912 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
913 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
914 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
916 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
917 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
918 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
920 let Defs = [RAX, RDX] in
921 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
924 let Defs = [RAX, RCX, RDX] in
925 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
927 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
928 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
931 def SYSCALL : I<0x05, RawFrm,
932 (outs), (ins), "syscall", []>, TB;
933 def SYSRET : I<0x07, RawFrm,
934 (outs), (ins), "sysret", []>, TB;
935 def SYSENTER : I<0x34, RawFrm,
936 (outs), (ins), "sysenter", []>, TB;
937 def SYSEXIT : I<0x35, RawFrm,
938 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
940 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
943 //===----------------------------------------------------------------------===//
944 // Input/Output Instructions...
946 let Defs = [AL], Uses = [DX] in
947 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
948 "in{b}\t{%dx, %al|%AL, %DX}", []>;
949 let Defs = [AX], Uses = [DX] in
950 def IN16rr : I<0xED, RawFrm, (outs), (ins),
951 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
952 let Defs = [EAX], Uses = [DX] in
953 def IN32rr : I<0xED, RawFrm, (outs), (ins),
954 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
957 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
958 "in{b}\t{$port, %al|%AL, $port}", []>;
960 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
961 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
963 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
964 "in{l}\t{$port, %eax|%EAX, $port}", []>;
966 let Uses = [DX, AL] in
967 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
968 "out{b}\t{%al, %dx|%DX, %AL}", []>;
969 let Uses = [DX, AX] in
970 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
971 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
972 let Uses = [DX, EAX] in
973 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
974 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
977 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
978 "out{b}\t{%al, $port|$port, %AL}", []>;
980 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
981 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
983 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
984 "out{l}\t{%eax, $port|$port, %EAX}", []>;
986 def IN8 : I<0x6C, RawFrm, (outs), (ins),
988 def IN16 : I<0x6D, RawFrm, (outs), (ins),
989 "ins{w}", []>, OpSize;
990 def IN32 : I<0x6D, RawFrm, (outs), (ins),
993 //===----------------------------------------------------------------------===//
994 // Move Instructions...
996 let neverHasSideEffects = 1 in {
997 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
998 "mov{b}\t{$src, $dst|$dst, $src}", []>;
999 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1001 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1002 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1004 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1005 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1006 "mov{b}\t{$src, $dst|$dst, $src}",
1007 [(set GR8:$dst, imm:$src)]>;
1008 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1009 "mov{w}\t{$src, $dst|$dst, $src}",
1010 [(set GR16:$dst, imm:$src)]>, OpSize;
1011 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1012 "mov{l}\t{$src, $dst|$dst, $src}",
1013 [(set GR32:$dst, imm:$src)]>;
1016 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1017 "mov{b}\t{$src, $dst|$dst, $src}",
1018 [(store (i8 imm:$src), addr:$dst)]>;
1019 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1020 "mov{w}\t{$src, $dst|$dst, $src}",
1021 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1022 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1023 "mov{l}\t{$src, $dst|$dst, $src}",
1024 [(store (i32 imm:$src), addr:$dst)]>;
1026 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1027 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1028 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1029 "mov{b}\t{$src, %al|%al, $src}", []>,
1030 Requires<[In32BitMode]>;
1031 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1032 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1033 Requires<[In32BitMode]>;
1034 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1035 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1036 Requires<[In32BitMode]>;
1037 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1038 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1039 Requires<[In32BitMode]>;
1040 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1041 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1042 Requires<[In32BitMode]>;
1043 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1044 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1045 Requires<[In32BitMode]>;
1047 // Moves to and from segment registers
1048 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1049 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1050 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1051 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1052 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1053 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1054 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1055 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1056 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1057 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1058 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1059 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1060 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1061 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1062 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1063 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1065 let isCodeGenOnly = 1 in {
1066 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1067 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1068 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1069 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1070 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1071 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1074 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1075 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1076 "mov{b}\t{$src, $dst|$dst, $src}",
1077 [(set GR8:$dst, (loadi8 addr:$src))]>;
1078 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1079 "mov{w}\t{$src, $dst|$dst, $src}",
1080 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1081 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1082 "mov{l}\t{$src, $dst|$dst, $src}",
1083 [(set GR32:$dst, (loadi32 addr:$src))]>;
1086 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1087 "mov{b}\t{$src, $dst|$dst, $src}",
1088 [(store GR8:$src, addr:$dst)]>;
1089 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1090 "mov{w}\t{$src, $dst|$dst, $src}",
1091 [(store GR16:$src, addr:$dst)]>, OpSize;
1092 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1093 "mov{l}\t{$src, $dst|$dst, $src}",
1094 [(store GR32:$src, addr:$dst)]>;
1096 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1097 let isCodeGenOnly = 1 in {
1098 let neverHasSideEffects = 1 in
1099 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1100 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1103 canFoldAsLoad = 1, isReMaterializable = 1 in
1104 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1105 "mov{l}\t{$src, $dst|$dst, $src}",
1109 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1110 "mov{l}\t{$src, $dst|$dst, $src}",
1114 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1115 // that they can be used for copying and storing h registers, which can't be
1116 // encoded when a REX prefix is present.
1117 let isCodeGenOnly = 1 in {
1118 let neverHasSideEffects = 1 in
1119 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1120 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1121 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1123 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1124 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1125 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1127 canFoldAsLoad = 1, isReMaterializable = 1 in
1128 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1129 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1130 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1133 // Moves to and from debug registers
1134 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1135 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1136 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1137 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1139 // Moves to and from control registers
1140 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1141 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1142 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1143 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1145 //===----------------------------------------------------------------------===//
1146 // Fixed-Register Multiplication and Division Instructions...
1149 // Extra precision multiplication
1151 // AL is really implied by AX, by the registers in Defs must match the
1152 // SDNode results (i8, i32).
1153 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1154 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1155 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1156 // This probably ought to be moved to a def : Pat<> if the
1157 // syntax can be accepted.
1158 [(set AL, (mul AL, GR8:$src)),
1159 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1161 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1162 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1164 []>, OpSize; // AX,DX = AX*GR16
1166 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1167 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1169 []>; // EAX,EDX = EAX*GR32
1171 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1172 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1174 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1175 // This probably ought to be moved to a def : Pat<> if the
1176 // syntax can be accepted.
1177 [(set AL, (mul AL, (loadi8 addr:$src))),
1178 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1180 let mayLoad = 1, neverHasSideEffects = 1 in {
1181 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1182 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1184 []>, OpSize; // AX,DX = AX*[mem16]
1186 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1187 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1189 []>; // EAX,EDX = EAX*[mem32]
1192 let neverHasSideEffects = 1 in {
1193 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1194 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1196 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1197 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1198 OpSize; // AX,DX = AX*GR16
1199 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1200 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1201 // EAX,EDX = EAX*GR32
1202 let mayLoad = 1 in {
1203 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1204 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1205 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1206 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1207 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1208 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1209 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1210 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1211 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1213 } // neverHasSideEffects
1215 // unsigned division/remainder
1216 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1217 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1218 "div{b}\t$src", []>;
1219 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1220 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1221 "div{w}\t$src", []>, OpSize;
1222 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1223 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1224 "div{l}\t$src", []>;
1225 let mayLoad = 1 in {
1226 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1227 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1228 "div{b}\t$src", []>;
1229 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1230 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1231 "div{w}\t$src", []>, OpSize;
1232 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1233 // EDX:EAX/[mem32] = EAX,EDX
1234 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1235 "div{l}\t$src", []>;
1238 // Signed division/remainder.
1239 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1240 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1241 "idiv{b}\t$src", []>;
1242 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1243 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1244 "idiv{w}\t$src", []>, OpSize;
1245 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1246 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1247 "idiv{l}\t$src", []>;
1248 let mayLoad = 1, mayLoad = 1 in {
1249 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1250 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1251 "idiv{b}\t$src", []>;
1252 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1253 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1254 "idiv{w}\t$src", []>, OpSize;
1255 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1256 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1257 // EDX:EAX/[mem32] = EAX,EDX
1258 "idiv{l}\t$src", []>;
1261 //===----------------------------------------------------------------------===//
1262 // Two address Instructions.
1264 let Constraints = "$src1 = $dst" in {
1266 // Conditional moves
1267 let Uses = [EFLAGS] in {
1269 let Predicates = [HasCMov] in {
1270 let isCommutable = 1 in {
1271 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1272 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1273 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1275 X86_COND_B, EFLAGS))]>,
1277 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1278 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1279 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1281 X86_COND_B, EFLAGS))]>,
1283 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1284 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1285 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1287 X86_COND_AE, EFLAGS))]>,
1289 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1290 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1291 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1293 X86_COND_AE, EFLAGS))]>,
1295 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1296 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1297 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1299 X86_COND_E, EFLAGS))]>,
1301 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1302 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1303 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1305 X86_COND_E, EFLAGS))]>,
1307 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1308 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1309 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1311 X86_COND_NE, EFLAGS))]>,
1313 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1314 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1315 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1317 X86_COND_NE, EFLAGS))]>,
1319 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1320 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1321 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1323 X86_COND_BE, EFLAGS))]>,
1325 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1326 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1327 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1329 X86_COND_BE, EFLAGS))]>,
1331 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1332 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1333 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1335 X86_COND_A, EFLAGS))]>,
1337 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1338 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1339 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1341 X86_COND_A, EFLAGS))]>,
1343 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1344 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1345 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1347 X86_COND_L, EFLAGS))]>,
1349 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1350 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1351 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1353 X86_COND_L, EFLAGS))]>,
1355 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1356 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1357 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1359 X86_COND_GE, EFLAGS))]>,
1361 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1362 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1363 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1365 X86_COND_GE, EFLAGS))]>,
1367 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1368 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1369 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1371 X86_COND_LE, EFLAGS))]>,
1373 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1374 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1375 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1377 X86_COND_LE, EFLAGS))]>,
1379 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1380 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1381 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1383 X86_COND_G, EFLAGS))]>,
1385 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1386 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1387 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1389 X86_COND_G, EFLAGS))]>,
1391 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1392 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1393 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1395 X86_COND_S, EFLAGS))]>,
1397 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1398 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1399 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1401 X86_COND_S, EFLAGS))]>,
1403 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1404 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1405 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1407 X86_COND_NS, EFLAGS))]>,
1409 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1410 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1411 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1413 X86_COND_NS, EFLAGS))]>,
1415 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1416 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1417 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1418 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1419 X86_COND_P, EFLAGS))]>,
1421 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1422 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1423 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1424 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1425 X86_COND_P, EFLAGS))]>,
1427 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1428 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1429 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1431 X86_COND_NP, EFLAGS))]>,
1433 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1434 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1435 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1437 X86_COND_NP, EFLAGS))]>,
1439 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1440 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1441 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1443 X86_COND_O, EFLAGS))]>,
1445 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1446 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1447 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1449 X86_COND_O, EFLAGS))]>,
1451 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1452 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1453 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1455 X86_COND_NO, EFLAGS))]>,
1457 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1458 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1459 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1461 X86_COND_NO, EFLAGS))]>,
1463 } // isCommutable = 1
1465 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1466 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1467 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1469 X86_COND_B, EFLAGS))]>,
1471 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1472 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1473 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1475 X86_COND_B, EFLAGS))]>,
1477 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1478 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1479 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1481 X86_COND_AE, EFLAGS))]>,
1483 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1484 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1485 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1487 X86_COND_AE, EFLAGS))]>,
1489 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1490 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1491 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1493 X86_COND_E, EFLAGS))]>,
1495 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1496 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1497 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1499 X86_COND_E, EFLAGS))]>,
1501 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1502 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1503 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1505 X86_COND_NE, EFLAGS))]>,
1507 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1508 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1509 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1511 X86_COND_NE, EFLAGS))]>,
1513 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1514 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1515 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1517 X86_COND_BE, EFLAGS))]>,
1519 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1520 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1521 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1523 X86_COND_BE, EFLAGS))]>,
1525 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1526 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1527 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1529 X86_COND_A, EFLAGS))]>,
1531 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1532 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1533 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1534 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1535 X86_COND_A, EFLAGS))]>,
1537 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1538 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1539 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1541 X86_COND_L, EFLAGS))]>,
1543 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1544 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1545 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1547 X86_COND_L, EFLAGS))]>,
1549 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1550 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1551 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1553 X86_COND_GE, EFLAGS))]>,
1555 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1556 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1557 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1559 X86_COND_GE, EFLAGS))]>,
1561 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1562 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1563 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1565 X86_COND_LE, EFLAGS))]>,
1567 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1568 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1569 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1571 X86_COND_LE, EFLAGS))]>,
1573 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1574 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1575 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1577 X86_COND_G, EFLAGS))]>,
1579 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1580 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1581 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1583 X86_COND_G, EFLAGS))]>,
1585 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1586 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1587 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1589 X86_COND_S, EFLAGS))]>,
1591 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1592 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1593 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1594 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1595 X86_COND_S, EFLAGS))]>,
1597 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1598 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1599 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1601 X86_COND_NS, EFLAGS))]>,
1603 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1604 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1605 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1606 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1607 X86_COND_NS, EFLAGS))]>,
1609 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1610 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1611 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1612 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1613 X86_COND_P, EFLAGS))]>,
1615 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1616 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1617 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1618 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1619 X86_COND_P, EFLAGS))]>,
1621 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1622 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1623 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1624 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1625 X86_COND_NP, EFLAGS))]>,
1627 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1628 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1629 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1630 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1631 X86_COND_NP, EFLAGS))]>,
1633 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1634 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1635 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1636 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1637 X86_COND_O, EFLAGS))]>,
1639 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1640 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1641 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1642 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1643 X86_COND_O, EFLAGS))]>,
1645 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1646 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1647 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1648 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1649 X86_COND_NO, EFLAGS))]>,
1651 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1652 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1653 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1655 X86_COND_NO, EFLAGS))]>,
1657 } // Predicates = [HasCMov]
1659 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1660 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1661 // however that requires promoting the operands, and can induce additional
1662 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1663 // clobber EFLAGS, because if one of the operands is zero, the expansion
1664 // could involve an xor.
1665 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1666 def CMOV_GR8 : I<0, Pseudo,
1667 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1668 "#CMOV_GR8 PSEUDO!",
1669 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1670 imm:$cond, EFLAGS))]>;
1672 let Predicates = [NoCMov] in {
1673 def CMOV_GR32 : I<0, Pseudo,
1674 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1675 "#CMOV_GR32* PSEUDO!",
1677 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1678 def CMOV_GR16 : I<0, Pseudo,
1679 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1680 "#CMOV_GR16* PSEUDO!",
1682 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1683 def CMOV_RFP32 : I<0, Pseudo,
1685 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1686 "#CMOV_RFP32 PSEUDO!",
1688 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1690 def CMOV_RFP64 : I<0, Pseudo,
1692 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1693 "#CMOV_RFP64 PSEUDO!",
1695 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1697 def CMOV_RFP80 : I<0, Pseudo,
1699 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1700 "#CMOV_RFP80 PSEUDO!",
1702 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1704 } // Predicates = [NoCMov]
1705 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1706 } // Uses = [EFLAGS]
1709 // unary instructions
1710 let CodeSize = 2 in {
1711 let Defs = [EFLAGS] in {
1712 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1714 [(set GR8:$dst, (ineg GR8:$src1)),
1715 (implicit EFLAGS)]>;
1716 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1718 [(set GR16:$dst, (ineg GR16:$src1)),
1719 (implicit EFLAGS)]>, OpSize;
1720 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1722 [(set GR32:$dst, (ineg GR32:$src1)),
1723 (implicit EFLAGS)]>;
1725 let Constraints = "" in {
1726 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1728 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1729 (implicit EFLAGS)]>;
1730 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1732 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1733 (implicit EFLAGS)]>, OpSize;
1734 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1736 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1737 (implicit EFLAGS)]>;
1738 } // Constraints = ""
1739 } // Defs = [EFLAGS]
1741 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1742 let AddedComplexity = 15 in {
1743 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1745 [(set GR8:$dst, (not GR8:$src1))]>;
1746 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1748 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1749 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1751 [(set GR32:$dst, (not GR32:$src1))]>;
1753 let Constraints = "" in {
1754 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1756 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1757 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1759 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1760 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1762 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1763 } // Constraints = ""
1766 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1767 let Defs = [EFLAGS] in {
1769 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1771 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1773 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1774 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1776 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1777 OpSize, Requires<[In32BitMode]>;
1778 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1780 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1781 Requires<[In32BitMode]>;
1783 let Constraints = "", CodeSize = 2 in {
1784 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1785 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1786 (implicit EFLAGS)]>;
1787 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1788 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1789 (implicit EFLAGS)]>,
1790 OpSize, Requires<[In32BitMode]>;
1791 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1792 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1793 (implicit EFLAGS)]>,
1794 Requires<[In32BitMode]>;
1795 } // Constraints = "", CodeSize = 2
1798 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1800 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1801 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1802 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1804 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1805 OpSize, Requires<[In32BitMode]>;
1806 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1808 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1809 Requires<[In32BitMode]>;
1812 let Constraints = "", CodeSize = 2 in {
1813 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1814 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1815 (implicit EFLAGS)]>;
1816 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1817 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1818 (implicit EFLAGS)]>,
1819 OpSize, Requires<[In32BitMode]>;
1820 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1821 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1822 (implicit EFLAGS)]>,
1823 Requires<[In32BitMode]>;
1824 } // Constraints = "", CodeSize = 2
1825 } // Defs = [EFLAGS]
1827 // Logical operators...
1828 let Defs = [EFLAGS] in {
1829 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1830 def AND8rr : I<0x20, MRMDestReg,
1831 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1832 "and{b}\t{$src2, $dst|$dst, $src2}",
1833 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1834 def AND16rr : I<0x21, MRMDestReg,
1835 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1836 "and{w}\t{$src2, $dst|$dst, $src2}",
1837 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1838 GR16:$src2))]>, OpSize;
1839 def AND32rr : I<0x21, MRMDestReg,
1840 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1841 "and{l}\t{$src2, $dst|$dst, $src2}",
1842 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1846 // AND instructions with the destination register in REG and the source register
1847 // in R/M. Included for the disassembler.
1848 let isCodeGenOnly = 1 in {
1849 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1850 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1851 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1852 (ins GR16:$src1, GR16:$src2),
1853 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1854 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1855 (ins GR32:$src1, GR32:$src2),
1856 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1859 def AND8rm : I<0x22, MRMSrcMem,
1860 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1861 "and{b}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1863 (loadi8 addr:$src2)))]>;
1864 def AND16rm : I<0x23, MRMSrcMem,
1865 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1866 "and{w}\t{$src2, $dst|$dst, $src2}",
1867 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1868 (loadi16 addr:$src2)))]>,
1870 def AND32rm : I<0x23, MRMSrcMem,
1871 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1872 "and{l}\t{$src2, $dst|$dst, $src2}",
1873 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1874 (loadi32 addr:$src2)))]>;
1876 def AND8ri : Ii8<0x80, MRM4r,
1877 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1878 "and{b}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1881 def AND16ri : Ii16<0x81, MRM4r,
1882 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1883 "and{w}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1885 imm:$src2))]>, OpSize;
1886 def AND32ri : Ii32<0x81, MRM4r,
1887 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1888 "and{l}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1891 def AND16ri8 : Ii8<0x83, MRM4r,
1892 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1893 "and{w}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1895 i16immSExt8:$src2))]>,
1897 def AND32ri8 : Ii8<0x83, MRM4r,
1898 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1899 "and{l}\t{$src2, $dst|$dst, $src2}",
1900 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1901 i32immSExt8:$src2))]>;
1903 let Constraints = "" in {
1904 def AND8mr : I<0x20, MRMDestMem,
1905 (outs), (ins i8mem :$dst, GR8 :$src),
1906 "and{b}\t{$src, $dst|$dst, $src}",
1907 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1908 (implicit EFLAGS)]>;
1909 def AND16mr : I<0x21, MRMDestMem,
1910 (outs), (ins i16mem:$dst, GR16:$src),
1911 "and{w}\t{$src, $dst|$dst, $src}",
1912 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1913 (implicit EFLAGS)]>,
1915 def AND32mr : I<0x21, MRMDestMem,
1916 (outs), (ins i32mem:$dst, GR32:$src),
1917 "and{l}\t{$src, $dst|$dst, $src}",
1918 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1919 (implicit EFLAGS)]>;
1920 def AND8mi : Ii8<0x80, MRM4m,
1921 (outs), (ins i8mem :$dst, i8imm :$src),
1922 "and{b}\t{$src, $dst|$dst, $src}",
1923 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1924 (implicit EFLAGS)]>;
1925 def AND16mi : Ii16<0x81, MRM4m,
1926 (outs), (ins i16mem:$dst, i16imm:$src),
1927 "and{w}\t{$src, $dst|$dst, $src}",
1928 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1929 (implicit EFLAGS)]>,
1931 def AND32mi : Ii32<0x81, MRM4m,
1932 (outs), (ins i32mem:$dst, i32imm:$src),
1933 "and{l}\t{$src, $dst|$dst, $src}",
1934 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1935 (implicit EFLAGS)]>;
1936 def AND16mi8 : Ii8<0x83, MRM4m,
1937 (outs), (ins i16mem:$dst, i16i8imm :$src),
1938 "and{w}\t{$src, $dst|$dst, $src}",
1939 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1940 (implicit EFLAGS)]>,
1942 def AND32mi8 : Ii8<0x83, MRM4m,
1943 (outs), (ins i32mem:$dst, i32i8imm :$src),
1944 "and{l}\t{$src, $dst|$dst, $src}",
1945 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1946 (implicit EFLAGS)]>;
1948 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1949 "and{b}\t{$src, %al|%al, $src}", []>;
1950 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1951 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1952 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1953 "and{l}\t{$src, %eax|%eax, $src}", []>;
1955 } // Constraints = ""
1958 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1959 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1960 (ins GR8 :$src1, GR8 :$src2),
1961 "or{b}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1963 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1964 (ins GR16:$src1, GR16:$src2),
1965 "or{w}\t{$src2, $dst|$dst, $src2}",
1966 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1968 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1969 (ins GR32:$src1, GR32:$src2),
1970 "or{l}\t{$src2, $dst|$dst, $src2}",
1971 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1974 // OR instructions with the destination register in REG and the source register
1975 // in R/M. Included for the disassembler.
1976 let isCodeGenOnly = 1 in {
1977 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1978 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1979 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1980 (ins GR16:$src1, GR16:$src2),
1981 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1982 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1983 (ins GR32:$src1, GR32:$src2),
1984 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1987 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1988 (ins GR8 :$src1, i8mem :$src2),
1989 "or{b}\t{$src2, $dst|$dst, $src2}",
1990 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1991 (load addr:$src2)))]>;
1992 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1993 (ins GR16:$src1, i16mem:$src2),
1994 "or{w}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1996 (load addr:$src2)))]>,
1998 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1999 (ins GR32:$src1, i32mem:$src2),
2000 "or{l}\t{$src2, $dst|$dst, $src2}",
2001 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2002 (load addr:$src2)))]>;
2004 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2005 (ins GR8 :$src1, i8imm:$src2),
2006 "or{b}\t{$src2, $dst|$dst, $src2}",
2007 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2008 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2009 (ins GR16:$src1, i16imm:$src2),
2010 "or{w}\t{$src2, $dst|$dst, $src2}",
2011 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2012 imm:$src2))]>, OpSize;
2013 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2014 (ins GR32:$src1, i32imm:$src2),
2015 "or{l}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2019 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2020 (ins GR16:$src1, i16i8imm:$src2),
2021 "or{w}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2023 i16immSExt8:$src2))]>, OpSize;
2024 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2025 (ins GR32:$src1, i32i8imm:$src2),
2026 "or{l}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2028 i32immSExt8:$src2))]>;
2029 let Constraints = "" in {
2030 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2031 "or{b}\t{$src, $dst|$dst, $src}",
2032 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2033 (implicit EFLAGS)]>;
2034 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2035 "or{w}\t{$src, $dst|$dst, $src}",
2036 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2037 (implicit EFLAGS)]>, OpSize;
2038 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2039 "or{l}\t{$src, $dst|$dst, $src}",
2040 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2041 (implicit EFLAGS)]>;
2042 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2043 "or{b}\t{$src, $dst|$dst, $src}",
2044 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2045 (implicit EFLAGS)]>;
2046 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2047 "or{w}\t{$src, $dst|$dst, $src}",
2048 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2049 (implicit EFLAGS)]>,
2051 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2052 "or{l}\t{$src, $dst|$dst, $src}",
2053 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2054 (implicit EFLAGS)]>;
2055 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2056 "or{w}\t{$src, $dst|$dst, $src}",
2057 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2058 (implicit EFLAGS)]>,
2060 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2061 "or{l}\t{$src, $dst|$dst, $src}",
2062 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2063 (implicit EFLAGS)]>;
2065 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2066 "or{b}\t{$src, %al|%al, $src}", []>;
2067 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2068 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2069 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2070 "or{l}\t{$src, %eax|%eax, $src}", []>;
2071 } // Constraints = ""
2074 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2075 def XOR8rr : I<0x30, MRMDestReg,
2076 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2077 "xor{b}\t{$src2, $dst|$dst, $src2}",
2078 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2080 def XOR16rr : I<0x31, MRMDestReg,
2081 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2082 "xor{w}\t{$src2, $dst|$dst, $src2}",
2083 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2084 GR16:$src2))]>, OpSize;
2085 def XOR32rr : I<0x31, MRMDestReg,
2086 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2087 "xor{l}\t{$src2, $dst|$dst, $src2}",
2088 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2090 } // isCommutable = 1
2092 // XOR instructions with the destination register in REG and the source register
2093 // in R/M. Included for the disassembler.
2094 let isCodeGenOnly = 1 in {
2095 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2096 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2097 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2098 (ins GR16:$src1, GR16:$src2),
2099 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2100 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2101 (ins GR32:$src1, GR32:$src2),
2102 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2105 def XOR8rm : I<0x32, MRMSrcMem,
2106 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2107 "xor{b}\t{$src2, $dst|$dst, $src2}",
2108 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2109 (load addr:$src2)))]>;
2110 def XOR16rm : I<0x33, MRMSrcMem,
2111 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2112 "xor{w}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2114 (load addr:$src2)))]>,
2116 def XOR32rm : I<0x33, MRMSrcMem,
2117 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2118 "xor{l}\t{$src2, $dst|$dst, $src2}",
2119 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2120 (load addr:$src2)))]>;
2122 def XOR8ri : Ii8<0x80, MRM6r,
2123 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2124 "xor{b}\t{$src2, $dst|$dst, $src2}",
2125 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2126 def XOR16ri : Ii16<0x81, MRM6r,
2127 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2128 "xor{w}\t{$src2, $dst|$dst, $src2}",
2129 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2130 imm:$src2))]>, OpSize;
2131 def XOR32ri : Ii32<0x81, MRM6r,
2132 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2133 "xor{l}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2136 def XOR16ri8 : Ii8<0x83, MRM6r,
2137 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2138 "xor{w}\t{$src2, $dst|$dst, $src2}",
2139 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2140 i16immSExt8:$src2))]>,
2142 def XOR32ri8 : Ii8<0x83, MRM6r,
2143 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2144 "xor{l}\t{$src2, $dst|$dst, $src2}",
2145 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2146 i32immSExt8:$src2))]>;
2148 let Constraints = "" in {
2149 def XOR8mr : I<0x30, MRMDestMem,
2150 (outs), (ins i8mem :$dst, GR8 :$src),
2151 "xor{b}\t{$src, $dst|$dst, $src}",
2152 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2153 (implicit EFLAGS)]>;
2154 def XOR16mr : I<0x31, MRMDestMem,
2155 (outs), (ins i16mem:$dst, GR16:$src),
2156 "xor{w}\t{$src, $dst|$dst, $src}",
2157 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2158 (implicit EFLAGS)]>,
2160 def XOR32mr : I<0x31, MRMDestMem,
2161 (outs), (ins i32mem:$dst, GR32:$src),
2162 "xor{l}\t{$src, $dst|$dst, $src}",
2163 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2164 (implicit EFLAGS)]>;
2165 def XOR8mi : Ii8<0x80, MRM6m,
2166 (outs), (ins i8mem :$dst, i8imm :$src),
2167 "xor{b}\t{$src, $dst|$dst, $src}",
2168 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2169 (implicit EFLAGS)]>;
2170 def XOR16mi : Ii16<0x81, MRM6m,
2171 (outs), (ins i16mem:$dst, i16imm:$src),
2172 "xor{w}\t{$src, $dst|$dst, $src}",
2173 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2174 (implicit EFLAGS)]>,
2176 def XOR32mi : Ii32<0x81, MRM6m,
2177 (outs), (ins i32mem:$dst, i32imm:$src),
2178 "xor{l}\t{$src, $dst|$dst, $src}",
2179 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2180 (implicit EFLAGS)]>;
2181 def XOR16mi8 : Ii8<0x83, MRM6m,
2182 (outs), (ins i16mem:$dst, i16i8imm :$src),
2183 "xor{w}\t{$src, $dst|$dst, $src}",
2184 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2185 (implicit EFLAGS)]>,
2187 def XOR32mi8 : Ii8<0x83, MRM6m,
2188 (outs), (ins i32mem:$dst, i32i8imm :$src),
2189 "xor{l}\t{$src, $dst|$dst, $src}",
2190 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2191 (implicit EFLAGS)]>;
2193 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2194 "xor{b}\t{$src, %al|%al, $src}", []>;
2195 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2196 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2197 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2198 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2199 } // Constraints = ""
2200 } // Defs = [EFLAGS]
2202 // Shift instructions
2203 let Defs = [EFLAGS] in {
2204 let Uses = [CL] in {
2205 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2206 "shl{b}\t{%cl, $dst|$dst, CL}",
2207 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2208 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2209 "shl{w}\t{%cl, $dst|$dst, CL}",
2210 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2211 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2212 "shl{l}\t{%cl, $dst|$dst, CL}",
2213 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2216 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2217 "shl{b}\t{$src2, $dst|$dst, $src2}",
2218 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2220 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2221 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2222 "shl{w}\t{$src2, $dst|$dst, $src2}",
2223 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2224 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2225 "shl{l}\t{$src2, $dst|$dst, $src2}",
2226 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2228 // NOTE: We don't include patterns for shifts of a register by one, because
2229 // 'add reg,reg' is cheaper.
2231 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2232 "shl{b}\t$dst", []>;
2233 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2234 "shl{w}\t$dst", []>, OpSize;
2235 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2236 "shl{l}\t$dst", []>;
2238 } // isConvertibleToThreeAddress = 1
2240 let Constraints = "" in {
2241 let Uses = [CL] in {
2242 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2243 "shl{b}\t{%cl, $dst|$dst, CL}",
2244 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2245 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2246 "shl{w}\t{%cl, $dst|$dst, CL}",
2247 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2248 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2249 "shl{l}\t{%cl, $dst|$dst, CL}",
2250 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2252 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2253 "shl{b}\t{$src, $dst|$dst, $src}",
2254 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2255 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2256 "shl{w}\t{$src, $dst|$dst, $src}",
2257 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2259 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2260 "shl{l}\t{$src, $dst|$dst, $src}",
2261 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2264 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2266 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2267 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2269 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2271 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2273 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2274 } // Constraints = ""
2276 let Uses = [CL] in {
2277 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2278 "shr{b}\t{%cl, $dst|$dst, CL}",
2279 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2280 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2281 "shr{w}\t{%cl, $dst|$dst, CL}",
2282 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2283 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2284 "shr{l}\t{%cl, $dst|$dst, CL}",
2285 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2288 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2289 "shr{b}\t{$src2, $dst|$dst, $src2}",
2290 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2291 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2292 "shr{w}\t{$src2, $dst|$dst, $src2}",
2293 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2294 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2295 "shr{l}\t{$src2, $dst|$dst, $src2}",
2296 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2299 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2301 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2302 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2304 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2305 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2307 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2309 let Constraints = "" in {
2310 let Uses = [CL] in {
2311 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2312 "shr{b}\t{%cl, $dst|$dst, CL}",
2313 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2314 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2315 "shr{w}\t{%cl, $dst|$dst, CL}",
2316 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2318 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2319 "shr{l}\t{%cl, $dst|$dst, CL}",
2320 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2322 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2323 "shr{b}\t{$src, $dst|$dst, $src}",
2324 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2325 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2326 "shr{w}\t{$src, $dst|$dst, $src}",
2327 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2329 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2330 "shr{l}\t{$src, $dst|$dst, $src}",
2331 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2334 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2336 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2337 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2339 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2340 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2342 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2343 } // Constraints = ""
2345 let Uses = [CL] in {
2346 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2347 "sar{b}\t{%cl, $dst|$dst, CL}",
2348 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2349 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2350 "sar{w}\t{%cl, $dst|$dst, CL}",
2351 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2352 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2353 "sar{l}\t{%cl, $dst|$dst, CL}",
2354 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2357 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2358 "sar{b}\t{$src2, $dst|$dst, $src2}",
2359 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2360 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2361 "sar{w}\t{$src2, $dst|$dst, $src2}",
2362 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2364 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2365 "sar{l}\t{$src2, $dst|$dst, $src2}",
2366 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2369 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2371 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2372 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2374 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2375 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2377 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2379 let Constraints = "" in {
2380 let Uses = [CL] in {
2381 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2382 "sar{b}\t{%cl, $dst|$dst, CL}",
2383 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2384 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2385 "sar{w}\t{%cl, $dst|$dst, CL}",
2386 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2387 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2388 "sar{l}\t{%cl, $dst|$dst, CL}",
2389 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2391 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2392 "sar{b}\t{$src, $dst|$dst, $src}",
2393 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2394 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2395 "sar{w}\t{$src, $dst|$dst, $src}",
2396 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2398 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2399 "sar{l}\t{$src, $dst|$dst, $src}",
2400 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2403 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2405 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2406 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2408 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2410 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2412 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2413 } // Constraints = ""
2415 // Rotate instructions
2417 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2418 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2419 let Uses = [CL] in {
2420 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2421 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2423 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2424 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2426 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2427 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2428 let Uses = [CL] in {
2429 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2430 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2432 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2433 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2435 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2436 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2437 let Uses = [CL] in {
2438 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2439 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2441 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2442 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2444 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2445 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2446 let Uses = [CL] in {
2447 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2448 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2450 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2451 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2453 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2454 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2455 let Uses = [CL] in {
2456 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2457 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2459 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2460 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2462 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2463 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2464 let Uses = [CL] in {
2465 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2466 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2468 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2469 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2471 let Constraints = "" in {
2472 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2473 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2474 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2475 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2476 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2477 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2478 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2479 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2480 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2481 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2482 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2483 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2484 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2485 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2486 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2487 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2488 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2489 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2490 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2491 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2492 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2493 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2494 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2495 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2497 let Uses = [CL] in {
2498 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2499 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2500 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2501 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2502 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2503 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2504 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2505 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2506 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2507 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2508 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2509 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2511 } // Constraints = ""
2513 // FIXME: provide shorter instructions when imm8 == 1
2514 let Uses = [CL] in {
2515 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2516 "rol{b}\t{%cl, $dst|$dst, CL}",
2517 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2518 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2519 "rol{w}\t{%cl, $dst|$dst, CL}",
2520 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2521 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2522 "rol{l}\t{%cl, $dst|$dst, CL}",
2523 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2526 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2527 "rol{b}\t{$src2, $dst|$dst, $src2}",
2528 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2529 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2530 "rol{w}\t{$src2, $dst|$dst, $src2}",
2531 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2533 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2534 "rol{l}\t{$src2, $dst|$dst, $src2}",
2535 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2538 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2540 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2541 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2543 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2544 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2546 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2548 let Constraints = "" in {
2549 let Uses = [CL] in {
2550 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2551 "rol{b}\t{%cl, $dst|$dst, CL}",
2552 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2553 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2554 "rol{w}\t{%cl, $dst|$dst, CL}",
2555 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2556 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2557 "rol{l}\t{%cl, $dst|$dst, CL}",
2558 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2560 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2561 "rol{b}\t{$src, $dst|$dst, $src}",
2562 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2563 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2564 "rol{w}\t{$src, $dst|$dst, $src}",
2565 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2567 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2568 "rol{l}\t{$src, $dst|$dst, $src}",
2569 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2572 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2574 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2575 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2577 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2579 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2581 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2582 } // Constraints = ""
2584 let Uses = [CL] in {
2585 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2586 "ror{b}\t{%cl, $dst|$dst, CL}",
2587 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2588 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2589 "ror{w}\t{%cl, $dst|$dst, CL}",
2590 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2591 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2592 "ror{l}\t{%cl, $dst|$dst, CL}",
2593 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2596 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2597 "ror{b}\t{$src2, $dst|$dst, $src2}",
2598 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2599 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2600 "ror{w}\t{$src2, $dst|$dst, $src2}",
2601 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2603 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2604 "ror{l}\t{$src2, $dst|$dst, $src2}",
2605 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2608 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2610 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2611 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2613 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2614 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2616 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2618 let Constraints = "" in {
2619 let Uses = [CL] in {
2620 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2621 "ror{b}\t{%cl, $dst|$dst, CL}",
2622 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2623 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2624 "ror{w}\t{%cl, $dst|$dst, CL}",
2625 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2626 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2627 "ror{l}\t{%cl, $dst|$dst, CL}",
2628 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2630 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2631 "ror{b}\t{$src, $dst|$dst, $src}",
2632 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2633 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2634 "ror{w}\t{$src, $dst|$dst, $src}",
2635 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2637 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2638 "ror{l}\t{$src, $dst|$dst, $src}",
2639 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2642 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2644 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2645 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2647 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2649 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2651 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2652 } // Constraints = ""
2655 // Double shift instructions (generalizations of rotate)
2656 let Uses = [CL] in {
2657 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2658 (ins GR32:$src1, GR32:$src2),
2659 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2660 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2661 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2662 (ins GR32:$src1, GR32:$src2),
2663 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2664 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2665 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2666 (ins GR16:$src1, GR16:$src2),
2667 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2668 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2670 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2671 (ins GR16:$src1, GR16:$src2),
2672 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2673 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2677 let isCommutable = 1 in { // These instructions commute to each other.
2678 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2680 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2681 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2682 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2685 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2687 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2688 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2689 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2692 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2694 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2695 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2696 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2699 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2701 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2702 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2703 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2708 let Constraints = "" in {
2709 let Uses = [CL] in {
2710 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2711 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2712 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2714 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2715 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2716 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2719 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2720 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2721 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2722 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2723 (i8 imm:$src3)), addr:$dst)]>,
2725 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2726 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2727 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2728 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2729 (i8 imm:$src3)), addr:$dst)]>,
2732 let Uses = [CL] in {
2733 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2734 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2735 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2736 addr:$dst)]>, TB, OpSize;
2737 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2738 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2739 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2740 addr:$dst)]>, TB, OpSize;
2742 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2743 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2744 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2745 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2746 (i8 imm:$src3)), addr:$dst)]>,
2748 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2749 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2750 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2751 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2752 (i8 imm:$src3)), addr:$dst)]>,
2754 } // Constraints = ""
2755 } // Defs = [EFLAGS]
2759 let Defs = [EFLAGS] in {
2760 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2761 // Register-Register Addition
2762 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2763 (ins GR8 :$src1, GR8 :$src2),
2764 "add{b}\t{$src2, $dst|$dst, $src2}",
2765 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2767 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2768 // Register-Register Addition
2769 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2770 (ins GR16:$src1, GR16:$src2),
2771 "add{w}\t{$src2, $dst|$dst, $src2}",
2772 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2773 GR16:$src2))]>, OpSize;
2774 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2775 (ins GR32:$src1, GR32:$src2),
2776 "add{l}\t{$src2, $dst|$dst, $src2}",
2777 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2779 } // end isConvertibleToThreeAddress
2780 } // end isCommutable
2782 // These are alternate spellings for use by the disassembler, we mark them as
2783 // code gen only to ensure they aren't matched by the assembler.
2784 let isCodeGenOnly = 1 in {
2785 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2786 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2787 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2788 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2789 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2790 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2793 // Register-Memory Addition
2794 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2795 (ins GR8 :$src1, i8mem :$src2),
2796 "add{b}\t{$src2, $dst|$dst, $src2}",
2797 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2798 (load addr:$src2)))]>;
2799 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2800 (ins GR16:$src1, i16mem:$src2),
2801 "add{w}\t{$src2, $dst|$dst, $src2}",
2802 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2803 (load addr:$src2)))]>, OpSize;
2804 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2805 (ins GR32:$src1, i32mem:$src2),
2806 "add{l}\t{$src2, $dst|$dst, $src2}",
2807 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2808 (load addr:$src2)))]>;
2810 // Register-Integer Addition
2811 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2812 "add{b}\t{$src2, $dst|$dst, $src2}",
2813 [(set GR8:$dst, EFLAGS,
2814 (X86add_flag GR8:$src1, imm:$src2))]>;
2816 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2817 // Register-Integer Addition
2818 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2819 (ins GR16:$src1, i16imm:$src2),
2820 "add{w}\t{$src2, $dst|$dst, $src2}",
2821 [(set GR16:$dst, EFLAGS,
2822 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2823 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2824 (ins GR32:$src1, i32imm:$src2),
2825 "add{l}\t{$src2, $dst|$dst, $src2}",
2826 [(set GR32:$dst, EFLAGS,
2827 (X86add_flag GR32:$src1, imm:$src2))]>;
2828 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2829 (ins GR16:$src1, i16i8imm:$src2),
2830 "add{w}\t{$src2, $dst|$dst, $src2}",
2831 [(set GR16:$dst, EFLAGS,
2832 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2833 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2834 (ins GR32:$src1, i32i8imm:$src2),
2835 "add{l}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR32:$dst, EFLAGS,
2837 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2840 let Constraints = "" in {
2841 // Memory-Register Addition
2842 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2843 "add{b}\t{$src2, $dst|$dst, $src2}",
2844 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2845 (implicit EFLAGS)]>;
2846 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2847 "add{w}\t{$src2, $dst|$dst, $src2}",
2848 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2849 (implicit EFLAGS)]>, OpSize;
2850 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2851 "add{l}\t{$src2, $dst|$dst, $src2}",
2852 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2853 (implicit EFLAGS)]>;
2854 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2855 "add{b}\t{$src2, $dst|$dst, $src2}",
2856 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2857 (implicit EFLAGS)]>;
2858 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2859 "add{w}\t{$src2, $dst|$dst, $src2}",
2860 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2861 (implicit EFLAGS)]>, OpSize;
2862 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2863 "add{l}\t{$src2, $dst|$dst, $src2}",
2864 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2865 (implicit EFLAGS)]>;
2866 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2867 "add{w}\t{$src2, $dst|$dst, $src2}",
2868 [(store (add (load addr:$dst), i16immSExt8:$src2),
2870 (implicit EFLAGS)]>, OpSize;
2871 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2872 "add{l}\t{$src2, $dst|$dst, $src2}",
2873 [(store (add (load addr:$dst), i32immSExt8:$src2),
2875 (implicit EFLAGS)]>;
2878 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2879 "add{b}\t{$src, %al|%al, $src}", []>;
2880 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2881 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2882 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2883 "add{l}\t{$src, %eax|%eax, $src}", []>;
2884 } // Constraints = ""
2886 let Uses = [EFLAGS] in {
2887 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2888 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2889 "adc{b}\t{$src2, $dst|$dst, $src2}",
2890 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2891 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2892 (ins GR16:$src1, GR16:$src2),
2893 "adc{w}\t{$src2, $dst|$dst, $src2}",
2894 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2895 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2896 (ins GR32:$src1, GR32:$src2),
2897 "adc{l}\t{$src2, $dst|$dst, $src2}",
2898 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2901 let isCodeGenOnly = 1 in {
2902 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2903 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2904 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2905 (ins GR16:$src1, GR16:$src2),
2906 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2907 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2908 (ins GR32:$src1, GR32:$src2),
2909 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2912 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2913 (ins GR8:$src1, i8mem:$src2),
2914 "adc{b}\t{$src2, $dst|$dst, $src2}",
2915 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2916 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2917 (ins GR16:$src1, i16mem:$src2),
2918 "adc{w}\t{$src2, $dst|$dst, $src2}",
2919 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2921 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2922 (ins GR32:$src1, i32mem:$src2),
2923 "adc{l}\t{$src2, $dst|$dst, $src2}",
2924 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2925 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2926 "adc{b}\t{$src2, $dst|$dst, $src2}",
2927 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2928 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2929 (ins GR16:$src1, i16imm:$src2),
2930 "adc{w}\t{$src2, $dst|$dst, $src2}",
2931 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2932 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2933 (ins GR16:$src1, i16i8imm:$src2),
2934 "adc{w}\t{$src2, $dst|$dst, $src2}",
2935 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2937 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2938 (ins GR32:$src1, i32imm:$src2),
2939 "adc{l}\t{$src2, $dst|$dst, $src2}",
2940 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2941 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2942 (ins GR32:$src1, i32i8imm:$src2),
2943 "adc{l}\t{$src2, $dst|$dst, $src2}",
2944 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2946 let Constraints = "" in {
2947 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2948 "adc{b}\t{$src2, $dst|$dst, $src2}",
2949 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2950 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2951 "adc{w}\t{$src2, $dst|$dst, $src2}",
2952 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2954 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2955 "adc{l}\t{$src2, $dst|$dst, $src2}",
2956 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2957 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2958 "adc{b}\t{$src2, $dst|$dst, $src2}",
2959 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2960 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2961 "adc{w}\t{$src2, $dst|$dst, $src2}",
2962 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2964 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2965 "adc{w}\t{$src2, $dst|$dst, $src2}",
2966 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2968 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2969 "adc{l}\t{$src2, $dst|$dst, $src2}",
2970 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2971 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2972 "adc{l}\t{$src2, $dst|$dst, $src2}",
2973 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2975 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2976 "adc{b}\t{$src, %al|%al, $src}", []>;
2977 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2978 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2979 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2980 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2981 } // Constraints = ""
2982 } // Uses = [EFLAGS]
2984 // Register-Register Subtraction
2985 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2986 "sub{b}\t{$src2, $dst|$dst, $src2}",
2987 [(set GR8:$dst, EFLAGS,
2988 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2989 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2990 "sub{w}\t{$src2, $dst|$dst, $src2}",
2991 [(set GR16:$dst, EFLAGS,
2992 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2993 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2994 "sub{l}\t{$src2, $dst|$dst, $src2}",
2995 [(set GR32:$dst, EFLAGS,
2996 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2998 let isCodeGenOnly = 1 in {
2999 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3000 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3001 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3002 (ins GR16:$src1, GR16:$src2),
3003 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3004 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3005 (ins GR32:$src1, GR32:$src2),
3006 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3009 // Register-Memory Subtraction
3010 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3011 (ins GR8 :$src1, i8mem :$src2),
3012 "sub{b}\t{$src2, $dst|$dst, $src2}",
3013 [(set GR8:$dst, EFLAGS,
3014 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3015 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3016 (ins GR16:$src1, i16mem:$src2),
3017 "sub{w}\t{$src2, $dst|$dst, $src2}",
3018 [(set GR16:$dst, EFLAGS,
3019 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3020 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3021 (ins GR32:$src1, i32mem:$src2),
3022 "sub{l}\t{$src2, $dst|$dst, $src2}",
3023 [(set GR32:$dst, EFLAGS,
3024 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3026 // Register-Integer Subtraction
3027 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3028 (ins GR8:$src1, i8imm:$src2),
3029 "sub{b}\t{$src2, $dst|$dst, $src2}",
3030 [(set GR8:$dst, EFLAGS,
3031 (X86sub_flag GR8:$src1, imm:$src2))]>;
3032 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3033 (ins GR16:$src1, i16imm:$src2),
3034 "sub{w}\t{$src2, $dst|$dst, $src2}",
3035 [(set GR16:$dst, EFLAGS,
3036 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3037 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3038 (ins GR32:$src1, i32imm:$src2),
3039 "sub{l}\t{$src2, $dst|$dst, $src2}",
3040 [(set GR32:$dst, EFLAGS,
3041 (X86sub_flag GR32:$src1, imm:$src2))]>;
3042 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3043 (ins GR16:$src1, i16i8imm:$src2),
3044 "sub{w}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR16:$dst, EFLAGS,
3046 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3047 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3048 (ins GR32:$src1, i32i8imm:$src2),
3049 "sub{l}\t{$src2, $dst|$dst, $src2}",
3050 [(set GR32:$dst, EFLAGS,
3051 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3053 let Constraints = "" in {
3054 // Memory-Register Subtraction
3055 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3056 "sub{b}\t{$src2, $dst|$dst, $src2}",
3057 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3058 (implicit EFLAGS)]>;
3059 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3060 "sub{w}\t{$src2, $dst|$dst, $src2}",
3061 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3062 (implicit EFLAGS)]>, OpSize;
3063 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3064 "sub{l}\t{$src2, $dst|$dst, $src2}",
3065 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3066 (implicit EFLAGS)]>;
3068 // Memory-Integer Subtraction
3069 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3070 "sub{b}\t{$src2, $dst|$dst, $src2}",
3071 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3072 (implicit EFLAGS)]>;
3073 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3074 "sub{w}\t{$src2, $dst|$dst, $src2}",
3075 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3076 (implicit EFLAGS)]>, OpSize;
3077 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3078 "sub{l}\t{$src2, $dst|$dst, $src2}",
3079 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3080 (implicit EFLAGS)]>;
3081 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3082 "sub{w}\t{$src2, $dst|$dst, $src2}",
3083 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3085 (implicit EFLAGS)]>, OpSize;
3086 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3087 "sub{l}\t{$src2, $dst|$dst, $src2}",
3088 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3090 (implicit EFLAGS)]>;
3092 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3093 "sub{b}\t{$src, %al|%al, $src}", []>;
3094 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3095 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3096 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3097 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3098 } // Constraints = ""
3100 let Uses = [EFLAGS] in {
3101 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3102 (ins GR8:$src1, GR8:$src2),
3103 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3104 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3105 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3106 (ins GR16:$src1, GR16:$src2),
3107 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3108 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3109 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3110 (ins GR32:$src1, GR32:$src2),
3111 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3112 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3114 let Constraints = "" in {
3115 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3116 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3117 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3118 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3119 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3120 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3122 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3123 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3124 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3125 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3126 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3127 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3128 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3129 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3130 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3132 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3133 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3134 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3136 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3137 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3138 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3139 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3140 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3141 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3143 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3144 "sbb{b}\t{$src, %al|%al, $src}", []>;
3145 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3146 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3147 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3148 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3149 } // Constraints = ""
3151 let isCodeGenOnly = 1 in {
3152 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3153 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3154 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3155 (ins GR16:$src1, GR16:$src2),
3156 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3157 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3158 (ins GR32:$src1, GR32:$src2),
3159 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3162 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3163 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3164 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3165 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3166 (ins GR16:$src1, i16mem:$src2),
3167 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3168 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3170 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3171 (ins GR32:$src1, i32mem:$src2),
3172 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3173 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3174 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3175 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3176 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3177 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3178 (ins GR16:$src1, i16imm:$src2),
3179 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3180 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3181 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3182 (ins GR16:$src1, i16i8imm:$src2),
3183 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3184 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3186 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3187 (ins GR32:$src1, i32imm:$src2),
3188 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3189 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3190 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3191 (ins GR32:$src1, i32i8imm:$src2),
3192 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3193 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3194 } // Uses = [EFLAGS]
3195 } // Defs = [EFLAGS]
3197 let Defs = [EFLAGS] in {
3198 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3199 // Register-Register Signed Integer Multiply
3200 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3201 "imul{w}\t{$src2, $dst|$dst, $src2}",
3202 [(set GR16:$dst, EFLAGS,
3203 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3204 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3205 "imul{l}\t{$src2, $dst|$dst, $src2}",
3206 [(set GR32:$dst, EFLAGS,
3207 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3210 // Register-Memory Signed Integer Multiply
3211 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3212 (ins GR16:$src1, i16mem:$src2),
3213 "imul{w}\t{$src2, $dst|$dst, $src2}",
3214 [(set GR16:$dst, EFLAGS,
3215 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3217 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3218 (ins GR32:$src1, i32mem:$src2),
3219 "imul{l}\t{$src2, $dst|$dst, $src2}",
3220 [(set GR32:$dst, EFLAGS,
3221 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3222 } // Defs = [EFLAGS]
3223 } // end Two Address instructions
3225 // Suprisingly enough, these are not two address instructions!
3226 let Defs = [EFLAGS] in {
3227 // Register-Integer Signed Integer Multiply
3228 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3229 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3230 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3231 [(set GR16:$dst, EFLAGS,
3232 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3233 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3234 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3235 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3236 [(set GR32:$dst, EFLAGS,
3237 (X86smul_flag GR32:$src1, imm:$src2))]>;
3238 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3239 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3240 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3241 [(set GR16:$dst, EFLAGS,
3242 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3244 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3245 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3246 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3247 [(set GR32:$dst, EFLAGS,
3248 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3250 // Memory-Integer Signed Integer Multiply
3251 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3252 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3253 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3254 [(set GR16:$dst, EFLAGS,
3255 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3257 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3258 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3259 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3260 [(set GR32:$dst, EFLAGS,
3261 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3262 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3263 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3264 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3265 [(set GR16:$dst, EFLAGS,
3266 (X86smul_flag (load addr:$src1),
3267 i16immSExt8:$src2))]>, OpSize;
3268 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3269 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3270 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3271 [(set GR32:$dst, EFLAGS,
3272 (X86smul_flag (load addr:$src1),
3273 i32immSExt8:$src2))]>;
3274 } // Defs = [EFLAGS]
3276 //===----------------------------------------------------------------------===//
3277 // Test instructions are just like AND, except they don't generate a result.
3279 let Defs = [EFLAGS] in {
3280 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3281 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3282 "test{b}\t{$src2, $src1|$src1, $src2}",
3283 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3284 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3285 "test{w}\t{$src2, $src1|$src1, $src2}",
3286 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3289 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3290 "test{l}\t{$src2, $src1|$src1, $src2}",
3291 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3295 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3296 "test{b}\t{$src, %al|%al, $src}", []>;
3297 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3298 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3299 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3300 "test{l}\t{$src, %eax|%eax, $src}", []>;
3302 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3303 "test{b}\t{$src2, $src1|$src1, $src2}",
3304 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3306 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3307 "test{w}\t{$src2, $src1|$src1, $src2}",
3308 [(set EFLAGS, (X86cmp (and GR16:$src1,
3309 (loadi16 addr:$src2)), 0))]>, OpSize;
3310 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3311 "test{l}\t{$src2, $src1|$src1, $src2}",
3312 [(set EFLAGS, (X86cmp (and GR32:$src1,
3313 (loadi32 addr:$src2)), 0))]>;
3315 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3316 (outs), (ins GR8:$src1, i8imm:$src2),
3317 "test{b}\t{$src2, $src1|$src1, $src2}",
3318 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3319 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3320 (outs), (ins GR16:$src1, i16imm:$src2),
3321 "test{w}\t{$src2, $src1|$src1, $src2}",
3322 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3324 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3325 (outs), (ins GR32:$src1, i32imm:$src2),
3326 "test{l}\t{$src2, $src1|$src1, $src2}",
3327 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3329 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3330 (outs), (ins i8mem:$src1, i8imm:$src2),
3331 "test{b}\t{$src2, $src1|$src1, $src2}",
3332 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3334 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3335 (outs), (ins i16mem:$src1, i16imm:$src2),
3336 "test{w}\t{$src2, $src1|$src1, $src2}",
3337 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3339 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3340 (outs), (ins i32mem:$src1, i32imm:$src2),
3341 "test{l}\t{$src2, $src1|$src1, $src2}",
3342 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3344 } // Defs = [EFLAGS]
3347 // Condition code ops, incl. set if equal/not equal/...
3348 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3349 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3350 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3351 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3353 let Uses = [EFLAGS] in {
3354 // Use sbb to materialize carry bit.
3355 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3356 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3357 // However, Pat<> can't replicate the destination reg into the inputs of the
3359 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3361 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3362 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3363 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3364 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3366 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3367 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3370 def SETEr : I<0x94, MRM0r,
3371 (outs GR8 :$dst), (ins),
3373 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3375 def SETEm : I<0x94, MRM0m,
3376 (outs), (ins i8mem:$dst),
3378 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3381 def SETNEr : I<0x95, MRM0r,
3382 (outs GR8 :$dst), (ins),
3384 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3386 def SETNEm : I<0x95, MRM0m,
3387 (outs), (ins i8mem:$dst),
3389 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3392 def SETLr : I<0x9C, MRM0r,
3393 (outs GR8 :$dst), (ins),
3395 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3396 TB; // GR8 = < signed
3397 def SETLm : I<0x9C, MRM0m,
3398 (outs), (ins i8mem:$dst),
3400 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3401 TB; // [mem8] = < signed
3403 def SETGEr : I<0x9D, MRM0r,
3404 (outs GR8 :$dst), (ins),
3406 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3407 TB; // GR8 = >= signed
3408 def SETGEm : I<0x9D, MRM0m,
3409 (outs), (ins i8mem:$dst),
3411 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3412 TB; // [mem8] = >= signed
3414 def SETLEr : I<0x9E, MRM0r,
3415 (outs GR8 :$dst), (ins),
3417 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3418 TB; // GR8 = <= signed
3419 def SETLEm : I<0x9E, MRM0m,
3420 (outs), (ins i8mem:$dst),
3422 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3423 TB; // [mem8] = <= signed
3425 def SETGr : I<0x9F, MRM0r,
3426 (outs GR8 :$dst), (ins),
3428 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3429 TB; // GR8 = > signed
3430 def SETGm : I<0x9F, MRM0m,
3431 (outs), (ins i8mem:$dst),
3433 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3434 TB; // [mem8] = > signed
3436 def SETBr : I<0x92, MRM0r,
3437 (outs GR8 :$dst), (ins),
3439 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3440 TB; // GR8 = < unsign
3441 def SETBm : I<0x92, MRM0m,
3442 (outs), (ins i8mem:$dst),
3444 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3445 TB; // [mem8] = < unsign
3447 def SETAEr : I<0x93, MRM0r,
3448 (outs GR8 :$dst), (ins),
3450 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3451 TB; // GR8 = >= unsign
3452 def SETAEm : I<0x93, MRM0m,
3453 (outs), (ins i8mem:$dst),
3455 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3456 TB; // [mem8] = >= unsign
3458 def SETBEr : I<0x96, MRM0r,
3459 (outs GR8 :$dst), (ins),
3461 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3462 TB; // GR8 = <= unsign
3463 def SETBEm : I<0x96, MRM0m,
3464 (outs), (ins i8mem:$dst),
3466 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3467 TB; // [mem8] = <= unsign
3469 def SETAr : I<0x97, MRM0r,
3470 (outs GR8 :$dst), (ins),
3472 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3473 TB; // GR8 = > signed
3474 def SETAm : I<0x97, MRM0m,
3475 (outs), (ins i8mem:$dst),
3477 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3478 TB; // [mem8] = > signed
3480 def SETSr : I<0x98, MRM0r,
3481 (outs GR8 :$dst), (ins),
3483 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3484 TB; // GR8 = <sign bit>
3485 def SETSm : I<0x98, MRM0m,
3486 (outs), (ins i8mem:$dst),
3488 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3489 TB; // [mem8] = <sign bit>
3490 def SETNSr : I<0x99, MRM0r,
3491 (outs GR8 :$dst), (ins),
3493 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3494 TB; // GR8 = !<sign bit>
3495 def SETNSm : I<0x99, MRM0m,
3496 (outs), (ins i8mem:$dst),
3498 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3499 TB; // [mem8] = !<sign bit>
3501 def SETPr : I<0x9A, MRM0r,
3502 (outs GR8 :$dst), (ins),
3504 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3506 def SETPm : I<0x9A, MRM0m,
3507 (outs), (ins i8mem:$dst),
3509 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3510 TB; // [mem8] = parity
3511 def SETNPr : I<0x9B, MRM0r,
3512 (outs GR8 :$dst), (ins),
3514 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3515 TB; // GR8 = not parity
3516 def SETNPm : I<0x9B, MRM0m,
3517 (outs), (ins i8mem:$dst),
3519 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3520 TB; // [mem8] = not parity
3522 def SETOr : I<0x90, MRM0r,
3523 (outs GR8 :$dst), (ins),
3525 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3526 TB; // GR8 = overflow
3527 def SETOm : I<0x90, MRM0m,
3528 (outs), (ins i8mem:$dst),
3530 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3531 TB; // [mem8] = overflow
3532 def SETNOr : I<0x91, MRM0r,
3533 (outs GR8 :$dst), (ins),
3535 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3536 TB; // GR8 = not overflow
3537 def SETNOm : I<0x91, MRM0m,
3538 (outs), (ins i8mem:$dst),
3540 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3541 TB; // [mem8] = not overflow
3542 } // Uses = [EFLAGS]
3545 // Integer comparisons
3546 let Defs = [EFLAGS] in {
3547 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3548 "cmp{b}\t{$src, %al|%al, $src}", []>;
3549 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3550 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3551 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3552 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3554 def CMP8rr : I<0x38, MRMDestReg,
3555 (outs), (ins GR8 :$src1, GR8 :$src2),
3556 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3557 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3558 def CMP16rr : I<0x39, MRMDestReg,
3559 (outs), (ins GR16:$src1, GR16:$src2),
3560 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3561 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3562 def CMP32rr : I<0x39, MRMDestReg,
3563 (outs), (ins GR32:$src1, GR32:$src2),
3564 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3565 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3566 def CMP8mr : I<0x38, MRMDestMem,
3567 (outs), (ins i8mem :$src1, GR8 :$src2),
3568 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3569 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3570 def CMP16mr : I<0x39, MRMDestMem,
3571 (outs), (ins i16mem:$src1, GR16:$src2),
3572 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3573 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3575 def CMP32mr : I<0x39, MRMDestMem,
3576 (outs), (ins i32mem:$src1, GR32:$src2),
3577 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3578 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3579 def CMP8rm : I<0x3A, MRMSrcMem,
3580 (outs), (ins GR8 :$src1, i8mem :$src2),
3581 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3582 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3583 def CMP16rm : I<0x3B, MRMSrcMem,
3584 (outs), (ins GR16:$src1, i16mem:$src2),
3585 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3586 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3588 def CMP32rm : I<0x3B, MRMSrcMem,
3589 (outs), (ins GR32:$src1, i32mem:$src2),
3590 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3591 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3593 // These are alternate spellings for use by the disassembler, we mark them as
3594 // code gen only to ensure they aren't matched by the assembler.
3595 let isCodeGenOnly = 1 in {
3596 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3597 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3598 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3599 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3600 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3601 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3604 def CMP8ri : Ii8<0x80, MRM7r,
3605 (outs), (ins GR8:$src1, i8imm:$src2),
3606 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3607 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3608 def CMP16ri : Ii16<0x81, MRM7r,
3609 (outs), (ins GR16:$src1, i16imm:$src2),
3610 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3611 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3612 def CMP32ri : Ii32<0x81, MRM7r,
3613 (outs), (ins GR32:$src1, i32imm:$src2),
3614 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3615 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3616 def CMP8mi : Ii8 <0x80, MRM7m,
3617 (outs), (ins i8mem :$src1, i8imm :$src2),
3618 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3619 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3620 def CMP16mi : Ii16<0x81, MRM7m,
3621 (outs), (ins i16mem:$src1, i16imm:$src2),
3622 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3623 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3625 def CMP32mi : Ii32<0x81, MRM7m,
3626 (outs), (ins i32mem:$src1, i32imm:$src2),
3627 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3628 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3629 def CMP16ri8 : Ii8<0x83, MRM7r,
3630 (outs), (ins GR16:$src1, i16i8imm:$src2),
3631 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3632 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3634 def CMP16mi8 : Ii8<0x83, MRM7m,
3635 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3636 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3637 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3638 i16immSExt8:$src2))]>, OpSize;
3639 def CMP32mi8 : Ii8<0x83, MRM7m,
3640 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3641 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3642 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3643 i32immSExt8:$src2))]>;
3644 def CMP32ri8 : Ii8<0x83, MRM7r,
3645 (outs), (ins GR32:$src1, i32i8imm:$src2),
3646 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3647 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3648 } // Defs = [EFLAGS]
3651 // TODO: BTC, BTR, and BTS
3652 let Defs = [EFLAGS] in {
3653 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3654 "bt{w}\t{$src2, $src1|$src1, $src2}",
3655 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3656 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3657 "bt{l}\t{$src2, $src1|$src1, $src2}",
3658 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3660 // Unlike with the register+register form, the memory+register form of the
3661 // bt instruction does not ignore the high bits of the index. From ISel's
3662 // perspective, this is pretty bizarre. Make these instructions disassembly
3665 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3666 "bt{w}\t{$src2, $src1|$src1, $src2}",
3667 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3668 // (implicit EFLAGS)]
3670 >, OpSize, TB, Requires<[FastBTMem]>;
3671 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3672 "bt{l}\t{$src2, $src1|$src1, $src2}",
3673 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3674 // (implicit EFLAGS)]
3676 >, TB, Requires<[FastBTMem]>;
3678 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3679 "bt{w}\t{$src2, $src1|$src1, $src2}",
3680 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3682 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3683 "bt{l}\t{$src2, $src1|$src1, $src2}",
3684 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3685 // Note that these instructions don't need FastBTMem because that
3686 // only applies when the other operand is in a register. When it's
3687 // an immediate, bt is still fast.
3688 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3689 "bt{w}\t{$src2, $src1|$src1, $src2}",
3690 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3692 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3693 "bt{l}\t{$src2, $src1|$src1, $src2}",
3694 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3697 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3698 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3699 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3700 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3701 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3702 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3703 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3704 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3705 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3706 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3707 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3708 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3709 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3710 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3711 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3712 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3714 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3715 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3716 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3717 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3718 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3719 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3720 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3721 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3722 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3723 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3724 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3725 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3726 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3727 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3728 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3729 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3731 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3732 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3733 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3734 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3735 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3736 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3737 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3738 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3739 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3740 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3741 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3742 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3743 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3744 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3745 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3746 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3747 } // Defs = [EFLAGS]
3749 // Sign/Zero extenders
3750 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3751 // of the register here. This has a smaller encoding and avoids a
3752 // partial-register update. Actual movsbw included for the disassembler.
3753 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3754 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3755 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3756 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3757 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3758 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3759 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3760 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3761 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3762 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3763 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3764 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3765 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3766 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3767 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3768 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3769 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3770 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3771 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3772 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3774 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3775 // of the register here. This has a smaller encoding and avoids a
3776 // partial-register update. Actual movzbw included for the disassembler.
3777 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3778 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3779 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3780 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3781 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3782 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3783 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3784 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3785 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3786 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3787 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3788 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3789 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3790 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3791 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3792 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3793 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3794 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3795 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3796 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3798 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3799 // except that they use GR32_NOREX for the output operand register class
3800 // instead of GR32. This allows them to operate on h registers on x86-64.
3801 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3802 (outs GR32_NOREX:$dst), (ins GR8:$src),
3803 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3806 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3807 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3808 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3811 let neverHasSideEffects = 1 in {
3812 let Defs = [AX], Uses = [AL] in
3813 def CBW : I<0x98, RawFrm, (outs), (ins),
3814 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3815 let Defs = [EAX], Uses = [AX] in
3816 def CWDE : I<0x98, RawFrm, (outs), (ins),
3817 "{cwtl|cwde}", []>; // EAX = signext(AX)
3819 let Defs = [AX,DX], Uses = [AX] in
3820 def CWD : I<0x99, RawFrm, (outs), (ins),
3821 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3822 let Defs = [EAX,EDX], Uses = [EAX] in
3823 def CDQ : I<0x99, RawFrm, (outs), (ins),
3824 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3827 //===----------------------------------------------------------------------===//
3828 // Alias Instructions
3829 //===----------------------------------------------------------------------===//
3831 // Alias instructions that map movr0 to xor.
3832 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3833 // FIXME: Set encoding to pseudo.
3834 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3835 isCodeGenOnly = 1 in {
3836 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3837 [(set GR8:$dst, 0)]>;
3839 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3840 // encoding and avoids a partial-register update sometimes, but doing so
3841 // at isel time interferes with rematerialization in the current register
3842 // allocator. For now, this is rewritten when the instruction is lowered
3844 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3846 [(set GR16:$dst, 0)]>, OpSize;
3848 // FIXME: Set encoding to pseudo.
3849 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3850 [(set GR32:$dst, 0)]>;
3853 //===----------------------------------------------------------------------===//
3854 // Thread Local Storage Instructions
3858 // All calls clobber the non-callee saved registers. ESP is marked as
3859 // a use to prevent stack-pointer assignments that appear immediately
3860 // before calls from potentially appearing dead.
3861 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3862 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3863 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3864 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3866 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3867 "leal\t$sym, %eax; "
3868 "call\t___tls_get_addr@PLT",
3869 [(X86tlsaddr tls32addr:$sym)]>,
3870 Requires<[In32BitMode]>;
3872 // Darwin TLS Support
3873 // For i386, the address of the thunk is passed on the stack, on return the
3874 // address of the variable is in %eax. %ecx is trashed during the function
3875 // call. All other registers are preserved.
3876 let Defs = [EAX, ECX],
3878 usesCustomInserter = 1 in
3879 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3881 [(X86TLSCall addr:$sym)]>,
3882 Requires<[In32BitMode]>;
3884 let AddedComplexity = 5, isCodeGenOnly = 1 in
3885 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3886 "movl\t%gs:$src, $dst",
3887 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3889 let AddedComplexity = 5, isCodeGenOnly = 1 in
3890 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3891 "movl\t%fs:$src, $dst",
3892 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3894 //===----------------------------------------------------------------------===//
3895 // EH Pseudo Instructions
3897 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3898 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3899 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3900 "ret\t#eh_return, addr: $addr",
3901 [(X86ehret GR32:$addr)]>;
3905 //===----------------------------------------------------------------------===//
3909 // Atomic swap. These are just normal xchg instructions. But since a memory
3910 // operand is referenced, the atomicity is ensured.
3911 let Constraints = "$val = $dst" in {
3912 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3913 (ins GR32:$val, i32mem:$ptr),
3914 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3915 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3916 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3917 (ins GR16:$val, i16mem:$ptr),
3918 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3919 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3921 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3922 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3923 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3925 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3926 "xchg{l}\t{$val, $src|$src, $val}", []>;
3927 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3928 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3929 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3930 "xchg{b}\t{$val, $src|$src, $val}", []>;
3933 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3934 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3935 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3936 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3938 // Atomic compare and swap.
3939 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3940 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3942 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3943 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3945 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3946 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3949 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3952 let Defs = [AX, EFLAGS], Uses = [AX] in {
3953 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3955 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3956 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3958 let Defs = [AL, EFLAGS], Uses = [AL] in {
3959 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3961 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3962 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3965 // Atomic exchange and add
3966 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3967 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3969 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3970 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3972 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3974 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3975 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3977 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3979 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3980 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3984 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3985 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3986 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3987 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3988 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3989 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3991 let mayLoad = 1, mayStore = 1 in {
3992 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3993 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3994 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3995 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3996 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3997 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4000 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4001 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4002 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4003 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4004 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4005 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4007 let mayLoad = 1, mayStore = 1 in {
4008 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4009 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4010 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4011 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4012 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4013 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4016 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4017 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4018 "cmpxchg8b\t$dst", []>, TB;
4020 // Optimized codegen when the non-memory output is not used.
4021 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4022 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4023 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4025 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4026 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4028 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4029 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4031 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4032 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4034 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4035 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4037 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4038 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4040 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4041 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4043 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4044 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4046 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4048 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4050 "inc{b}\t$dst", []>, LOCK;
4051 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4053 "inc{w}\t$dst", []>, OpSize, LOCK;
4054 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4056 "inc{l}\t$dst", []>, LOCK;
4058 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4060 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4061 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4063 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4064 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4066 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4067 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4069 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4070 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4072 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4073 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4075 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4076 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4078 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4079 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4081 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4083 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4085 "dec{b}\t$dst", []>, LOCK;
4086 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4088 "dec{w}\t$dst", []>, OpSize, LOCK;
4089 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4091 "dec{l}\t$dst", []>, LOCK;
4094 // Atomic exchange, and, or, xor
4095 let Constraints = "$val = $dst", Defs = [EFLAGS],
4096 usesCustomInserter = 1 in {
4097 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4098 "#ATOMAND32 PSEUDO!",
4099 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4100 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4101 "#ATOMOR32 PSEUDO!",
4102 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4103 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4104 "#ATOMXOR32 PSEUDO!",
4105 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4106 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4107 "#ATOMNAND32 PSEUDO!",
4108 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4109 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4110 "#ATOMMIN32 PSEUDO!",
4111 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4112 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4113 "#ATOMMAX32 PSEUDO!",
4114 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4115 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4116 "#ATOMUMIN32 PSEUDO!",
4117 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4118 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4119 "#ATOMUMAX32 PSEUDO!",
4120 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4122 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4123 "#ATOMAND16 PSEUDO!",
4124 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4125 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4126 "#ATOMOR16 PSEUDO!",
4127 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4128 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4129 "#ATOMXOR16 PSEUDO!",
4130 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4131 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4132 "#ATOMNAND16 PSEUDO!",
4133 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4134 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4135 "#ATOMMIN16 PSEUDO!",
4136 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4137 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4138 "#ATOMMAX16 PSEUDO!",
4139 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4140 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4141 "#ATOMUMIN16 PSEUDO!",
4142 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4143 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4144 "#ATOMUMAX16 PSEUDO!",
4145 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4147 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4148 "#ATOMAND8 PSEUDO!",
4149 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4150 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4152 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4153 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4154 "#ATOMXOR8 PSEUDO!",
4155 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4156 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4157 "#ATOMNAND8 PSEUDO!",
4158 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4161 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4162 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4163 Uses = [EAX, EBX, ECX, EDX],
4164 mayLoad = 1, mayStore = 1,
4165 usesCustomInserter = 1 in {
4166 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4167 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4168 "#ATOMAND6432 PSEUDO!", []>;
4169 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4170 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4171 "#ATOMOR6432 PSEUDO!", []>;
4172 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4173 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4174 "#ATOMXOR6432 PSEUDO!", []>;
4175 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4176 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4177 "#ATOMNAND6432 PSEUDO!", []>;
4178 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4179 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4180 "#ATOMADD6432 PSEUDO!", []>;
4181 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4182 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4183 "#ATOMSUB6432 PSEUDO!", []>;
4184 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4185 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4186 "#ATOMSWAP6432 PSEUDO!", []>;
4189 // Segmentation support instructions.
4191 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4192 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4193 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4194 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4196 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4197 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4198 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4199 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4200 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4202 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4203 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4204 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4205 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4206 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4207 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4208 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4209 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4211 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4213 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4214 "str{w}\t{$dst}", []>, TB;
4215 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4216 "str{w}\t{$dst}", []>, TB;
4217 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4218 "ltr{w}\t{$src}", []>, TB;
4219 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4220 "ltr{w}\t{$src}", []>, TB;
4222 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4223 "push{w}\t%fs", []>, OpSize, TB;
4224 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4225 "push{l}\t%fs", []>, TB;
4226 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4227 "push{w}\t%gs", []>, OpSize, TB;
4228 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4229 "push{l}\t%gs", []>, TB;
4231 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4232 "pop{w}\t%fs", []>, OpSize, TB;
4233 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4234 "pop{l}\t%fs", []>, TB;
4235 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4236 "pop{w}\t%gs", []>, OpSize, TB;
4237 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4238 "pop{l}\t%gs", []>, TB;
4240 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4241 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4242 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4243 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4244 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4245 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4246 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4247 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4248 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4249 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4250 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4251 "les{l}\t{$src, $dst|$dst, $src}", []>;
4252 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4253 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4254 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4255 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4256 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4257 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4258 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4259 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4261 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4262 "verr\t$seg", []>, TB;
4263 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4264 "verr\t$seg", []>, TB;
4265 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4266 "verw\t$seg", []>, TB;
4267 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4268 "verw\t$seg", []>, TB;
4270 // Descriptor-table support instructions
4272 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4273 "sgdt\t$dst", []>, TB;
4274 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4275 "sidt\t$dst", []>, TB;
4276 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4277 "sldt{w}\t$dst", []>, TB;
4278 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4279 "sldt{w}\t$dst", []>, TB;
4280 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4281 "lgdt\t$src", []>, TB;
4282 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4283 "lidt\t$src", []>, TB;
4284 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4285 "lldt{w}\t$src", []>, TB;
4286 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4287 "lldt{w}\t$src", []>, TB;
4289 // Lock instruction prefix
4290 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4292 // Repeat string operation instruction prefixes
4293 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4294 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4295 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4296 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4297 // Repeat while not equal (used with CMPS and SCAS)
4298 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4301 // Segment override instruction prefixes
4302 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4303 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4304 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4305 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4306 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4307 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4309 // String manipulation instructions
4311 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4312 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4313 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4315 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4316 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4317 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4319 // CPU flow control instructions
4321 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4322 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4324 // FPU control instructions
4326 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4328 // Flag instructions
4330 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4331 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4332 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4333 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4334 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4335 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4336 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4338 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4340 // Table lookup instructions
4342 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4344 // Specialized register support
4346 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4347 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4348 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4350 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4351 "smsw{w}\t$dst", []>, OpSize, TB;
4352 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4353 "smsw{l}\t$dst", []>, TB;
4354 // For memory operands, there is only a 16-bit form
4355 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4356 "smsw{w}\t$dst", []>, TB;
4358 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4359 "lmsw{w}\t$src", []>, TB;
4360 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4361 "lmsw{w}\t$src", []>, TB;
4363 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4365 // Cache instructions
4367 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4368 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4373 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4375 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4377 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4378 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4379 "vmclear\t$vmcs", []>, OpSize, TB;
4381 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4383 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4384 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4385 "vmptrld\t$vmcs", []>, TB;
4386 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4387 "vmptrst\t$vmcs", []>, TB;
4388 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4389 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4390 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4391 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4392 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4393 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4394 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4395 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4396 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4397 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4398 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4399 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4400 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4401 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4402 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4403 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4405 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4406 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4407 "vmxon\t{$vmxon}", []>, XS;
4409 //===----------------------------------------------------------------------===//
4410 // Non-Instruction Patterns
4411 //===----------------------------------------------------------------------===//
4413 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4414 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4415 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4416 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4417 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4418 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4419 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4421 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4422 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4423 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4424 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4425 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4426 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4427 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4428 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4429 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4430 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4432 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4433 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4434 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4435 (MOV32mi addr:$dst, texternalsym:$src)>;
4436 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4437 (MOV32mi addr:$dst, tblockaddress:$src)>;
4441 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4442 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4443 Requires<[In32BitMode]>;
4445 // FIXME: This is disabled for 32-bit PIC mode because the global base
4446 // register which is part of the address mode may be assigned a
4447 // callee-saved register.
4448 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4449 (TCRETURNmi addr:$dst, imm:$off)>,
4450 Requires<[In32BitMode, IsNotPIC]>;
4452 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4453 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4454 Requires<[In32BitMode]>;
4456 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4457 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4458 Requires<[In32BitMode]>;
4460 // Normal calls, with various flavors of addresses.
4461 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4462 (CALLpcrel32 tglobaladdr:$dst)>;
4463 def : Pat<(X86call (i32 texternalsym:$dst)),
4464 (CALLpcrel32 texternalsym:$dst)>;
4465 def : Pat<(X86call (i32 imm:$dst)),
4466 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4468 // X86 specific add which produces a flag.
4469 def : Pat<(addc GR32:$src1, GR32:$src2),
4470 (ADD32rr GR32:$src1, GR32:$src2)>;
4471 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4472 (ADD32rm GR32:$src1, addr:$src2)>;
4473 def : Pat<(addc GR32:$src1, imm:$src2),
4474 (ADD32ri GR32:$src1, imm:$src2)>;
4475 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4476 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4478 def : Pat<(subc GR32:$src1, GR32:$src2),
4479 (SUB32rr GR32:$src1, GR32:$src2)>;
4480 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4481 (SUB32rm GR32:$src1, addr:$src2)>;
4482 def : Pat<(subc GR32:$src1, imm:$src2),
4483 (SUB32ri GR32:$src1, imm:$src2)>;
4484 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4485 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4489 // TEST R,R is smaller than CMP R,0
4490 def : Pat<(X86cmp GR8:$src1, 0),
4491 (TEST8rr GR8:$src1, GR8:$src1)>;
4492 def : Pat<(X86cmp GR16:$src1, 0),
4493 (TEST16rr GR16:$src1, GR16:$src1)>;
4494 def : Pat<(X86cmp GR32:$src1, 0),
4495 (TEST32rr GR32:$src1, GR32:$src1)>;
4497 // Conditional moves with folded loads with operands swapped and conditions
4499 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4500 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4501 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4502 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4503 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4504 (CMOVB16rm GR16:$src2, addr:$src1)>;
4505 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4506 (CMOVB32rm GR32:$src2, addr:$src1)>;
4507 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4508 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4509 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4510 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4511 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4512 (CMOVE16rm GR16:$src2, addr:$src1)>;
4513 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4514 (CMOVE32rm GR32:$src2, addr:$src1)>;
4515 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4516 (CMOVA16rm GR16:$src2, addr:$src1)>;
4517 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4518 (CMOVA32rm GR32:$src2, addr:$src1)>;
4519 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4520 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4521 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4522 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4523 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4524 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4525 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4526 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4527 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4528 (CMOVL16rm GR16:$src2, addr:$src1)>;
4529 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4530 (CMOVL32rm GR32:$src2, addr:$src1)>;
4531 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4532 (CMOVG16rm GR16:$src2, addr:$src1)>;
4533 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4534 (CMOVG32rm GR32:$src2, addr:$src1)>;
4535 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4536 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4537 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4538 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4539 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4540 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4541 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4542 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4543 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4544 (CMOVP16rm GR16:$src2, addr:$src1)>;
4545 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4546 (CMOVP32rm GR32:$src2, addr:$src1)>;
4547 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4548 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4549 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4550 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4551 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4552 (CMOVS16rm GR16:$src2, addr:$src1)>;
4553 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4554 (CMOVS32rm GR32:$src2, addr:$src1)>;
4555 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4556 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4557 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4558 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4559 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4560 (CMOVO16rm GR16:$src2, addr:$src1)>;
4561 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4562 (CMOVO32rm GR32:$src2, addr:$src1)>;
4564 // zextload bool -> zextload byte
4565 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4566 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4567 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4569 // extload bool -> extload byte
4570 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4571 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4572 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4573 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4574 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4575 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4577 // anyext. Define these to do an explicit zero-extend to
4578 // avoid partial-register updates.
4579 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4580 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4582 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4583 def : Pat<(i32 (anyext GR16:$src)),
4584 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4587 //===----------------------------------------------------------------------===//
4589 //===----------------------------------------------------------------------===//
4591 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4592 // +128 doesn't, so in this special case use a sub instead of an add.
4593 def : Pat<(add GR16:$src1, 128),
4594 (SUB16ri8 GR16:$src1, -128)>;
4595 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4596 (SUB16mi8 addr:$dst, -128)>;
4597 def : Pat<(add GR32:$src1, 128),
4598 (SUB32ri8 GR32:$src1, -128)>;
4599 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4600 (SUB32mi8 addr:$dst, -128)>;
4602 // r & (2^16-1) ==> movz
4603 def : Pat<(and GR32:$src1, 0xffff),
4604 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4605 // r & (2^8-1) ==> movz
4606 def : Pat<(and GR32:$src1, 0xff),
4607 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4610 Requires<[In32BitMode]>;
4611 // r & (2^8-1) ==> movz
4612 def : Pat<(and GR16:$src1, 0xff),
4613 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4616 Requires<[In32BitMode]>;
4618 // sext_inreg patterns
4619 def : Pat<(sext_inreg GR32:$src, i16),
4620 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4621 def : Pat<(sext_inreg GR32:$src, i8),
4622 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4625 Requires<[In32BitMode]>;
4626 def : Pat<(sext_inreg GR16:$src, i8),
4627 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4630 Requires<[In32BitMode]>;
4633 def : Pat<(i16 (trunc GR32:$src)),
4634 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4635 def : Pat<(i8 (trunc GR32:$src)),
4636 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4638 Requires<[In32BitMode]>;
4639 def : Pat<(i8 (trunc GR16:$src)),
4640 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4642 Requires<[In32BitMode]>;
4644 // h-register tricks
4645 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4646 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4648 Requires<[In32BitMode]>;
4649 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4650 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4652 Requires<[In32BitMode]>;
4653 def : Pat<(srl GR16:$src, (i8 8)),
4656 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4659 Requires<[In32BitMode]>;
4660 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4661 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4664 Requires<[In32BitMode]>;
4665 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4666 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4669 Requires<[In32BitMode]>;
4670 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4671 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4674 Requires<[In32BitMode]>;
4675 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4676 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4679 Requires<[In32BitMode]>;
4681 // (shl x, 1) ==> (add x, x)
4682 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4683 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4684 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4686 // (shl x (and y, 31)) ==> (shl x, y)
4687 def : Pat<(shl GR8:$src1, (and CL, 31)),
4688 (SHL8rCL GR8:$src1)>;
4689 def : Pat<(shl GR16:$src1, (and CL, 31)),
4690 (SHL16rCL GR16:$src1)>;
4691 def : Pat<(shl GR32:$src1, (and CL, 31)),
4692 (SHL32rCL GR32:$src1)>;
4693 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4694 (SHL8mCL addr:$dst)>;
4695 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4696 (SHL16mCL addr:$dst)>;
4697 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4698 (SHL32mCL addr:$dst)>;
4700 def : Pat<(srl GR8:$src1, (and CL, 31)),
4701 (SHR8rCL GR8:$src1)>;
4702 def : Pat<(srl GR16:$src1, (and CL, 31)),
4703 (SHR16rCL GR16:$src1)>;
4704 def : Pat<(srl GR32:$src1, (and CL, 31)),
4705 (SHR32rCL GR32:$src1)>;
4706 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4707 (SHR8mCL addr:$dst)>;
4708 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4709 (SHR16mCL addr:$dst)>;
4710 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4711 (SHR32mCL addr:$dst)>;
4713 def : Pat<(sra GR8:$src1, (and CL, 31)),
4714 (SAR8rCL GR8:$src1)>;
4715 def : Pat<(sra GR16:$src1, (and CL, 31)),
4716 (SAR16rCL GR16:$src1)>;
4717 def : Pat<(sra GR32:$src1, (and CL, 31)),
4718 (SAR32rCL GR32:$src1)>;
4719 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4720 (SAR8mCL addr:$dst)>;
4721 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4722 (SAR16mCL addr:$dst)>;
4723 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4724 (SAR32mCL addr:$dst)>;
4726 // (anyext (setcc_carry)) -> (setcc_carry)
4727 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4729 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4731 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4734 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4735 let AddedComplexity = 5 in { // Try this before the selecting to OR
4736 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4737 (ADD16ri GR16:$src1, imm:$src2)>;
4738 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4739 (ADD32ri GR32:$src1, imm:$src2)>;
4740 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4741 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4742 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4743 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4744 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4745 (ADD16rr GR16:$src1, GR16:$src2)>;
4746 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4747 (ADD32rr GR32:$src1, GR32:$src2)>;
4748 } // AddedComplexity
4750 //===----------------------------------------------------------------------===//
4751 // EFLAGS-defining Patterns
4752 //===----------------------------------------------------------------------===//
4755 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4756 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4757 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4760 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4761 (ADD8rm GR8:$src1, addr:$src2)>;
4762 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4763 (ADD16rm GR16:$src1, addr:$src2)>;
4764 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4765 (ADD32rm GR32:$src1, addr:$src2)>;
4768 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4769 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4770 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4771 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4772 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4773 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4774 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4777 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4778 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4779 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4782 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4783 (SUB8rm GR8:$src1, addr:$src2)>;
4784 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4785 (SUB16rm GR16:$src1, addr:$src2)>;
4786 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4787 (SUB32rm GR32:$src1, addr:$src2)>;
4790 def : Pat<(sub GR8:$src1, imm:$src2),
4791 (SUB8ri GR8:$src1, imm:$src2)>;
4792 def : Pat<(sub GR16:$src1, imm:$src2),
4793 (SUB16ri GR16:$src1, imm:$src2)>;
4794 def : Pat<(sub GR32:$src1, imm:$src2),
4795 (SUB32ri GR32:$src1, imm:$src2)>;
4796 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4797 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4798 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4799 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4802 def : Pat<(mul GR16:$src1, GR16:$src2),
4803 (IMUL16rr GR16:$src1, GR16:$src2)>;
4804 def : Pat<(mul GR32:$src1, GR32:$src2),
4805 (IMUL32rr GR32:$src1, GR32:$src2)>;
4808 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4809 (IMUL16rm GR16:$src1, addr:$src2)>;
4810 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4811 (IMUL32rm GR32:$src1, addr:$src2)>;
4814 def : Pat<(mul GR16:$src1, imm:$src2),
4815 (IMUL16rri GR16:$src1, imm:$src2)>;
4816 def : Pat<(mul GR32:$src1, imm:$src2),
4817 (IMUL32rri GR32:$src1, imm:$src2)>;
4818 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4819 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4820 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4821 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4823 // reg = mul mem, imm
4824 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4825 (IMUL16rmi addr:$src1, imm:$src2)>;
4826 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4827 (IMUL32rmi addr:$src1, imm:$src2)>;
4828 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4829 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4830 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4831 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4833 // Optimize multiply by 2 with EFLAGS result.
4834 let AddedComplexity = 2 in {
4835 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4836 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4839 // Patterns for nodes that do not produce flags, for instructions that do.
4842 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4843 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4844 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4847 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4848 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4849 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4852 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4853 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4854 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4857 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4858 (OR8rm GR8:$src1, addr:$src2)>;
4859 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4860 (OR16rm GR16:$src1, addr:$src2)>;
4861 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4862 (OR32rm GR32:$src1, addr:$src2)>;
4865 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4866 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4867 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4868 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4869 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4870 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4871 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4874 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4875 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4876 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4879 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4880 (XOR8rm GR8:$src1, addr:$src2)>;
4881 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4882 (XOR16rm GR16:$src1, addr:$src2)>;
4883 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4884 (XOR32rm GR32:$src1, addr:$src2)>;
4887 def : Pat<(xor GR8:$src1, imm:$src2),
4888 (XOR8ri GR8:$src1, imm:$src2)>;
4889 def : Pat<(xor GR16:$src1, imm:$src2),
4890 (XOR16ri GR16:$src1, imm:$src2)>;
4891 def : Pat<(xor GR32:$src1, imm:$src2),
4892 (XOR32ri GR32:$src1, imm:$src2)>;
4893 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4894 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4895 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4896 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4899 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4900 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4901 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4904 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4905 (AND8rm GR8:$src1, addr:$src2)>;
4906 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4907 (AND16rm GR16:$src1, addr:$src2)>;
4908 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4909 (AND32rm GR32:$src1, addr:$src2)>;
4912 def : Pat<(and GR8:$src1, imm:$src2),
4913 (AND8ri GR8:$src1, imm:$src2)>;
4914 def : Pat<(and GR16:$src1, imm:$src2),
4915 (AND16ri GR16:$src1, imm:$src2)>;
4916 def : Pat<(and GR32:$src1, imm:$src2),
4917 (AND32ri GR32:$src1, imm:$src2)>;
4918 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4919 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4920 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4921 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4923 //===----------------------------------------------------------------------===//
4924 // Floating Point Stack Support
4925 //===----------------------------------------------------------------------===//
4927 include "X86InstrFPStack.td"
4929 //===----------------------------------------------------------------------===//
4931 //===----------------------------------------------------------------------===//
4933 include "X86Instr64bit.td"
4935 //===----------------------------------------------------------------------===//
4936 // SIMD support (SSE, MMX and AVX)
4937 //===----------------------------------------------------------------------===//
4939 include "X86InstrFragmentsSIMD.td"
4941 //===----------------------------------------------------------------------===//
4942 // XMM Floating point support (requires SSE / SSE2)
4943 //===----------------------------------------------------------------------===//
4945 include "X86InstrSSE.td"
4947 //===----------------------------------------------------------------------===//
4948 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4949 //===----------------------------------------------------------------------===//
4951 include "X86InstrMMX.td"