1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
40 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
46 // RES1, RES2, FLAGS = op LHS, RHS
47 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
51 SDTCisInt<0>, SDTCisVT<1, i32>]>;
52 def SDTX86BrCond : SDTypeProfile<0, 3,
53 [SDTCisVT<0, OtherVT>,
54 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
56 def SDTX86SetCC : SDTypeProfile<1, 2,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC_C : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
65 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
68 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
69 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
71 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
72 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
75 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
77 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
81 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
87 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
89 def SDTX86Void : SDTypeProfile<0, 0, []>;
91 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
93 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
95 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
97 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
99 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
101 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
102 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
106 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
108 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
110 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
112 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
116 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
117 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
118 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
119 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
121 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
122 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
124 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
125 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
127 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
128 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
130 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
131 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
132 SDNPMayLoad, SDNPMemOperand]>;
133 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
134 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
135 SDNPMayLoad, SDNPMemOperand]>;
136 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
137 [SDNPHasChain, SDNPMayStore,
138 SDNPMayLoad, SDNPMemOperand]>;
139 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
140 [SDNPHasChain, SDNPMayStore,
141 SDNPMayLoad, SDNPMemOperand]>;
142 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
143 [SDNPHasChain, SDNPMayStore,
144 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
160 def X86vastart_save_xmm_regs :
161 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
162 SDT_X86VASTART_SAVE_XMM_REGS,
163 [SDNPHasChain, SDNPVariadic]>;
165 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
166 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
168 def X86callseq_start :
169 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
170 [SDNPHasChain, SDNPOutGlue]>;
172 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
175 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
176 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
179 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
180 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
181 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
185 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
186 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
188 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
189 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
191 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
197 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
198 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
200 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
202 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
203 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
205 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
207 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
208 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
210 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
211 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
212 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
214 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
216 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
219 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
221 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
222 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
224 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
225 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
227 //===----------------------------------------------------------------------===//
228 // X86 Operand Definitions.
231 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
232 // the index operand of an address, to conform to x86 encoding restrictions.
233 def ptr_rc_nosp : PointerLikeRegClass<1>;
235 // *mem - Operand definitions for the funky X86 addressing mode operands.
237 def X86MemAsmOperand : AsmOperandClass {
239 let SuperClasses = [];
241 def X86AbsMemAsmOperand : AsmOperandClass {
243 let SuperClasses = [X86MemAsmOperand];
245 class X86MemOperand<string printMethod> : Operand<iPTR> {
246 let PrintMethod = printMethod;
247 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
248 let ParserMatchClass = X86MemAsmOperand;
251 def opaque32mem : X86MemOperand<"printopaquemem">;
252 def opaque48mem : X86MemOperand<"printopaquemem">;
253 def opaque80mem : X86MemOperand<"printopaquemem">;
254 def opaque512mem : X86MemOperand<"printopaquemem">;
256 def i8mem : X86MemOperand<"printi8mem">;
257 def i16mem : X86MemOperand<"printi16mem">;
258 def i32mem : X86MemOperand<"printi32mem">;
259 def i64mem : X86MemOperand<"printi64mem">;
260 def i128mem : X86MemOperand<"printi128mem">;
261 def i256mem : X86MemOperand<"printi256mem">;
262 def f32mem : X86MemOperand<"printf32mem">;
263 def f64mem : X86MemOperand<"printf64mem">;
264 def f80mem : X86MemOperand<"printf80mem">;
265 def f128mem : X86MemOperand<"printf128mem">;
266 def f256mem : X86MemOperand<"printf256mem">;
268 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
269 // plain GR64, so that it doesn't potentially require a REX prefix.
270 def i8mem_NOREX : Operand<i64> {
271 let PrintMethod = "printi8mem";
272 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
273 let ParserMatchClass = X86MemAsmOperand;
276 // Special i32mem for addresses of load folding tail calls. These are not
277 // allowed to use callee-saved registers since they must be scheduled
278 // after callee-saved register are popped.
279 def i32mem_TC : Operand<i32> {
280 let PrintMethod = "printi32mem";
281 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
282 let ParserMatchClass = X86MemAsmOperand;
285 // Special i64mem for addresses of load folding tail calls. These are not
286 // allowed to use callee-saved registers since they must be scheduled
287 // after callee-saved register are popped.
288 def i64mem_TC : Operand<i64> {
289 let PrintMethod = "printi64mem";
290 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
291 let ParserMatchClass = X86MemAsmOperand;
294 let ParserMatchClass = X86AbsMemAsmOperand,
295 PrintMethod = "print_pcrel_imm" in {
296 def i32imm_pcrel : Operand<i32>;
297 def i16imm_pcrel : Operand<i16>;
299 def offset8 : Operand<i64>;
300 def offset16 : Operand<i64>;
301 def offset32 : Operand<i64>;
302 def offset64 : Operand<i64>;
304 // Branch targets have OtherVT type and print as pc-relative values.
305 def brtarget : Operand<OtherVT>;
306 def brtarget8 : Operand<OtherVT>;
310 def SSECC : Operand<i8> {
311 let PrintMethod = "printSSECC";
314 class ImmSExtAsmOperandClass : AsmOperandClass {
315 let SuperClasses = [ImmAsmOperand];
316 let RenderMethod = "addImmOperands";
319 // Sign-extended immediate classes. We don't need to define the full lattice
320 // here because there is no instruction with an ambiguity between ImmSExti64i32
323 // The strange ranges come from the fact that the assembler always works with
324 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
325 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
328 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
329 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
330 let Name = "ImmSExti64i32";
333 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
334 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
335 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
336 let Name = "ImmSExti16i8";
337 let SuperClasses = [ImmSExti64i32AsmOperand];
340 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
341 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
342 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
343 let Name = "ImmSExti32i8";
347 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
348 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
349 let Name = "ImmSExti64i8";
350 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
351 ImmSExti64i32AsmOperand];
354 // A couple of more descriptive operand definitions.
355 // 16-bits but only 8 bits are significant.
356 def i16i8imm : Operand<i16> {
357 let ParserMatchClass = ImmSExti16i8AsmOperand;
359 // 32-bits but only 8 bits are significant.
360 def i32i8imm : Operand<i32> {
361 let ParserMatchClass = ImmSExti32i8AsmOperand;
364 // 64-bits but only 32 bits are significant.
365 def i64i32imm : Operand<i64> {
366 let ParserMatchClass = ImmSExti64i32AsmOperand;
369 // 64-bits but only 32 bits are significant, and those bits are treated as being
371 def i64i32imm_pcrel : Operand<i64> {
372 let PrintMethod = "print_pcrel_imm";
373 let ParserMatchClass = X86AbsMemAsmOperand;
376 // 64-bits but only 8 bits are significant.
377 def i64i8imm : Operand<i64> {
378 let ParserMatchClass = ImmSExti64i8AsmOperand;
381 def lea64_32mem : Operand<i32> {
382 let PrintMethod = "printi32mem";
383 let AsmOperandLowerMethod = "lower_lea64_32mem";
384 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
385 let ParserMatchClass = X86MemAsmOperand;
389 //===----------------------------------------------------------------------===//
390 // X86 Complex Pattern Definitions.
393 // Define X86 specific addressing mode.
394 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
395 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
396 [add, sub, mul, X86mul_imm, shl, or, frameindex],
398 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
399 [tglobaltlsaddr], []>;
401 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
402 [add, sub, mul, X86mul_imm, shl, or, frameindex,
405 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
406 [tglobaltlsaddr], []>;
408 //===----------------------------------------------------------------------===//
409 // X86 Instruction Predicate Definitions.
410 def HasCMov : Predicate<"Subtarget->hasCMov()">;
411 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
413 def HasMMX : Predicate<"Subtarget->hasMMX()">;
414 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
415 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
416 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
417 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
418 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
419 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
420 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
421 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
422 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
424 def HasAVX : Predicate<"Subtarget->hasAVX()">;
425 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
427 def HasAES : Predicate<"Subtarget->hasAES()">;
428 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
429 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
430 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
431 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
432 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
433 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
434 def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
435 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
436 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
437 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
438 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
439 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
440 "TM.getCodeModel() != CodeModel::Kernel">;
441 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
442 "TM.getCodeModel() == CodeModel::Kernel">;
443 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
444 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
445 def OptForSize : Predicate<"OptForSize">;
446 def OptForSpeed : Predicate<"!OptForSize">;
447 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
448 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
450 //===----------------------------------------------------------------------===//
451 // X86 Instruction Format Definitions.
454 include "X86InstrFormats.td"
456 //===----------------------------------------------------------------------===//
457 // Pattern fragments...
460 // X86 specific condition code. These correspond to CondCode in
461 // X86InstrInfo.h. They must be kept in synch.
462 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
463 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
464 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
465 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
466 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
467 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
468 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
469 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
470 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
471 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
472 def X86_COND_NO : PatLeaf<(i8 10)>;
473 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
474 def X86_COND_NS : PatLeaf<(i8 12)>;
475 def X86_COND_O : PatLeaf<(i8 13)>;
476 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
477 def X86_COND_S : PatLeaf<(i8 15)>;
479 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
481 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
482 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
483 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
484 def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
485 def i64immZExt32 : PatLeaf<(i64 imm), [{
486 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
487 // unsignedsign extended field.
488 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
491 def i64immZExt32SExt8 : PatLeaf<(i64 imm), [{
492 uint64_t v = N->getZExtValue();
493 return v == (uint32_t)v && (int32_t)v == (int8_t)v;
496 // Helper fragments for loads.
497 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
498 // known to be 32-bit aligned or better. Ditto for i8 to i16.
499 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
500 LoadSDNode *LD = cast<LoadSDNode>(N);
501 ISD::LoadExtType ExtType = LD->getExtensionType();
502 if (ExtType == ISD::NON_EXTLOAD)
504 if (ExtType == ISD::EXTLOAD)
505 return LD->getAlignment() >= 2 && !LD->isVolatile();
509 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
510 LoadSDNode *LD = cast<LoadSDNode>(N);
511 ISD::LoadExtType ExtType = LD->getExtensionType();
512 if (ExtType == ISD::EXTLOAD)
513 return LD->getAlignment() >= 2 && !LD->isVolatile();
517 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
518 LoadSDNode *LD = cast<LoadSDNode>(N);
519 ISD::LoadExtType ExtType = LD->getExtensionType();
520 if (ExtType == ISD::NON_EXTLOAD)
522 if (ExtType == ISD::EXTLOAD)
523 return LD->getAlignment() >= 4 && !LD->isVolatile();
527 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
528 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
529 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
530 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
531 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
533 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
534 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
535 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
536 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
537 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
538 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
540 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
541 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
542 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
543 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
544 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
545 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
546 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
547 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
548 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
549 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
551 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
552 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
553 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
554 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
555 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
556 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
557 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
558 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
559 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
560 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
563 // An 'and' node with a single use.
564 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
565 return N->hasOneUse();
567 // An 'srl' node with a single use.
568 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
569 return N->hasOneUse();
571 // An 'trunc' node with a single use.
572 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
573 return N->hasOneUse();
576 //===----------------------------------------------------------------------===//
581 let neverHasSideEffects = 1 in {
582 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
583 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
584 "nop{w}\t$zero", []>, TB, OpSize;
585 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
586 "nop{l}\t$zero", []>, TB;
590 // Constructing a stack frame.
591 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
592 "enter\t$len, $lvl", []>;
594 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
595 def LEAVE : I<0xC9, RawFrm,
596 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
598 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
599 def LEAVE64 : I<0xC9, RawFrm,
600 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
602 //===----------------------------------------------------------------------===//
603 // Miscellaneous Instructions.
606 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
608 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
610 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
611 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
613 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
615 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
616 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
618 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
619 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
620 Requires<[In32BitMode]>;
623 let mayStore = 1 in {
624 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
626 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
627 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
629 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
631 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
632 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
634 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
635 "push{l}\t$imm", []>;
636 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
637 "push{w}\t$imm", []>, OpSize;
638 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
639 "push{l}\t$imm", []>;
641 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
642 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
643 Requires<[In32BitMode]>;
648 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
650 def POP64r : I<0x58, AddRegFrm,
651 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
652 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
653 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
655 let mayStore = 1 in {
656 def PUSH64r : I<0x50, AddRegFrm,
657 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
658 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
659 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
663 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
664 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
665 "push{q}\t$imm", []>;
666 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
667 "push{q}\t$imm", []>;
668 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
669 "push{q}\t$imm", []>;
672 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
673 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
674 Requires<[In64BitMode]>;
675 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
676 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
677 Requires<[In64BitMode]>;
681 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
682 mayLoad=1, neverHasSideEffects=1 in {
683 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
684 Requires<[In32BitMode]>;
686 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
687 mayStore=1, neverHasSideEffects=1 in {
688 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
689 Requires<[In32BitMode]>;
692 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
693 def BSWAP32r : I<0xC8, AddRegFrm,
694 (outs GR32:$dst), (ins GR32:$src),
696 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
698 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
700 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
701 } // Constraints = "$src = $dst"
703 // Bit scan instructions.
704 let Defs = [EFLAGS] in {
705 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
706 "bsf{w}\t{$src, $dst|$dst, $src}",
707 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
708 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
709 "bsf{w}\t{$src, $dst|$dst, $src}",
710 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
712 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
713 "bsf{l}\t{$src, $dst|$dst, $src}",
714 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
715 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
716 "bsf{l}\t{$src, $dst|$dst, $src}",
717 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
718 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
719 "bsf{q}\t{$src, $dst|$dst, $src}",
720 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
721 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
722 "bsf{q}\t{$src, $dst|$dst, $src}",
723 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
725 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
726 "bsr{w}\t{$src, $dst|$dst, $src}",
727 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
728 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
729 "bsr{w}\t{$src, $dst|$dst, $src}",
730 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
732 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
733 "bsr{l}\t{$src, $dst|$dst, $src}",
734 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
735 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
736 "bsr{l}\t{$src, $dst|$dst, $src}",
737 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
738 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
739 "bsr{q}\t{$src, $dst|$dst, $src}",
740 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
741 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
742 "bsr{q}\t{$src, $dst|$dst, $src}",
743 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
747 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
748 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
749 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
750 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
751 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
752 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
755 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
756 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
757 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
758 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
759 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
760 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
761 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
762 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
763 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
765 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
766 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
767 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
768 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
770 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
771 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
772 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
773 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
776 //===----------------------------------------------------------------------===//
777 // Move Instructions.
780 let neverHasSideEffects = 1 in {
781 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
782 "mov{b}\t{$src, $dst|$dst, $src}", []>;
783 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
784 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
785 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
786 "mov{l}\t{$src, $dst|$dst, $src}", []>;
787 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
788 "mov{q}\t{$src, $dst|$dst, $src}", []>;
790 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
791 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
792 "mov{b}\t{$src, $dst|$dst, $src}",
793 [(set GR8:$dst, imm:$src)]>;
794 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
795 "mov{w}\t{$src, $dst|$dst, $src}",
796 [(set GR16:$dst, imm:$src)]>, OpSize;
797 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
798 "mov{l}\t{$src, $dst|$dst, $src}",
799 [(set GR32:$dst, imm:$src)]>;
800 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
801 "movabs{q}\t{$src, $dst|$dst, $src}",
802 [(set GR64:$dst, imm:$src)]>;
803 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
804 "mov{q}\t{$src, $dst|$dst, $src}",
805 [(set GR64:$dst, i64immSExt32:$src)]>;
808 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
809 "mov{b}\t{$src, $dst|$dst, $src}",
810 [(store (i8 imm:$src), addr:$dst)]>;
811 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
812 "mov{w}\t{$src, $dst|$dst, $src}",
813 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
814 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
815 "mov{l}\t{$src, $dst|$dst, $src}",
816 [(store (i32 imm:$src), addr:$dst)]>;
817 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
818 "mov{q}\t{$src, $dst|$dst, $src}",
819 [(store i64immSExt32:$src, addr:$dst)]>;
821 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
822 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
823 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
824 "mov{b}\t{$src, %al|%al, $src}", []>,
825 Requires<[In32BitMode]>;
826 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
827 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
828 Requires<[In32BitMode]>;
829 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
830 "mov{l}\t{$src, %eax|%eax, $src}", []>,
831 Requires<[In32BitMode]>;
832 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
833 "mov{b}\t{%al, $dst|$dst, %al}", []>,
834 Requires<[In32BitMode]>;
835 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
836 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
837 Requires<[In32BitMode]>;
838 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
839 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
840 Requires<[In32BitMode]>;
842 // FIXME: These definitions are utterly broken
843 // Just leave them commented out for now because they're useless outside
844 // of the large code model, and most compilers won't generate the instructions
847 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
848 "mov{q}\t{$src, %rax|%rax, $src}", []>;
849 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
850 "mov{q}\t{$src, %rax|%rax, $src}", []>;
851 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
852 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
853 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
854 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
858 let isCodeGenOnly = 1 in {
859 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
860 "mov{b}\t{$src, $dst|$dst, $src}", []>;
861 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
862 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
863 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
864 "mov{l}\t{$src, $dst|$dst, $src}", []>;
865 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
866 "mov{q}\t{$src, $dst|$dst, $src}", []>;
869 let canFoldAsLoad = 1, isReMaterializable = 1 in {
870 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
871 "mov{b}\t{$src, $dst|$dst, $src}",
872 [(set GR8:$dst, (loadi8 addr:$src))]>;
873 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
874 "mov{w}\t{$src, $dst|$dst, $src}",
875 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
876 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
877 "mov{l}\t{$src, $dst|$dst, $src}",
878 [(set GR32:$dst, (loadi32 addr:$src))]>;
879 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
880 "mov{q}\t{$src, $dst|$dst, $src}",
881 [(set GR64:$dst, (load addr:$src))]>;
884 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
885 "mov{b}\t{$src, $dst|$dst, $src}",
886 [(store GR8:$src, addr:$dst)]>;
887 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
888 "mov{w}\t{$src, $dst|$dst, $src}",
889 [(store GR16:$src, addr:$dst)]>, OpSize;
890 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
891 "mov{l}\t{$src, $dst|$dst, $src}",
892 [(store GR32:$src, addr:$dst)]>;
893 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
894 "mov{q}\t{$src, $dst|$dst, $src}",
895 [(store GR64:$src, addr:$dst)]>;
897 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
898 // that they can be used for copying and storing h registers, which can't be
899 // encoded when a REX prefix is present.
900 let isCodeGenOnly = 1 in {
901 let neverHasSideEffects = 1 in
902 def MOV8rr_NOREX : I<0x88, MRMDestReg,
903 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
904 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
906 def MOV8mr_NOREX : I<0x88, MRMDestMem,
907 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
908 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
910 canFoldAsLoad = 1, isReMaterializable = 1 in
911 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
912 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
913 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
917 // Condition code ops, incl. set if equal/not equal/...
918 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
919 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
920 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
921 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
924 //===----------------------------------------------------------------------===//
925 // Bit tests instructions: BT, BTS, BTR, BTC.
927 let Defs = [EFLAGS] in {
928 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
929 "bt{w}\t{$src2, $src1|$src1, $src2}",
930 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
931 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
932 "bt{l}\t{$src2, $src1|$src1, $src2}",
933 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
934 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
935 "bt{q}\t{$src2, $src1|$src1, $src2}",
936 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
938 // Unlike with the register+register form, the memory+register form of the
939 // bt instruction does not ignore the high bits of the index. From ISel's
940 // perspective, this is pretty bizarre. Make these instructions disassembly
943 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
944 "bt{w}\t{$src2, $src1|$src1, $src2}",
945 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
946 // (implicit EFLAGS)]
948 >, OpSize, TB, Requires<[FastBTMem]>;
949 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
950 "bt{l}\t{$src2, $src1|$src1, $src2}",
951 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
952 // (implicit EFLAGS)]
954 >, TB, Requires<[FastBTMem]>;
955 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
956 "bt{q}\t{$src2, $src1|$src1, $src2}",
957 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
958 // (implicit EFLAGS)]
962 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
963 "bt{w}\t{$src2, $src1|$src1, $src2}",
964 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
966 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
967 "bt{l}\t{$src2, $src1|$src1, $src2}",
968 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
969 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
970 "bt{q}\t{$src2, $src1|$src1, $src2}",
971 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
973 // Note that these instructions don't need FastBTMem because that
974 // only applies when the other operand is in a register. When it's
975 // an immediate, bt is still fast.
976 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
977 "bt{w}\t{$src2, $src1|$src1, $src2}",
978 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
980 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
981 "bt{l}\t{$src2, $src1|$src1, $src2}",
982 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
984 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
985 "bt{q}\t{$src2, $src1|$src1, $src2}",
986 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
987 i64immSExt8:$src2))]>, TB;
990 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
991 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
992 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
993 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
994 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
995 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
996 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
997 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
998 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
999 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1000 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1001 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1002 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1003 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1004 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1005 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1006 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1007 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1008 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1009 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1010 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1011 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1012 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1013 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1015 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1016 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1017 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1018 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1019 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1020 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1021 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1022 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1023 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1024 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1025 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1026 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1027 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1028 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1029 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1030 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1031 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1032 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1033 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1034 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1035 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1036 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1037 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1038 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1040 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1041 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1042 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1043 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1044 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1045 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1046 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1047 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1048 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1049 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1050 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1051 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1052 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1053 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1054 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1055 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1056 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1057 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1058 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1059 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1060 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1061 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1062 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1063 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1064 } // Defs = [EFLAGS]
1067 //===----------------------------------------------------------------------===//
1072 // Atomic swap. These are just normal xchg instructions. But since a memory
1073 // operand is referenced, the atomicity is ensured.
1074 let Constraints = "$val = $dst" in {
1075 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1076 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1077 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1078 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1079 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1080 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1082 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1083 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1084 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1085 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1086 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1087 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1089 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1090 "xchg{b}\t{$val, $src|$src, $val}", []>;
1091 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1092 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1093 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1094 "xchg{l}\t{$val, $src|$src, $val}", []>;
1095 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1096 "xchg{q}\t{$val, $src|$src, $val}", []>;
1099 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1100 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1101 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1102 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1103 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1104 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1108 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1109 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1110 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1111 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1112 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1113 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1114 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1115 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1117 let mayLoad = 1, mayStore = 1 in {
1118 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1119 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1120 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1121 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1122 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1123 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1124 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1125 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1129 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1130 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1131 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1132 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1133 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1134 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1135 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1136 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1138 let mayLoad = 1, mayStore = 1 in {
1139 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1140 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1141 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1142 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1143 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1144 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1145 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1146 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1149 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1150 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1151 "cmpxchg8b\t$dst", []>, TB;
1153 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1154 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1155 "cmpxchg16b\t$dst", []>, TB;
1159 // Lock instruction prefix
1160 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1162 // Rex64 instruction prefix
1163 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1165 // Data16 instruction prefix
1166 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1168 // Repeat string operation instruction prefixes
1169 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1170 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1171 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1172 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1173 // Repeat while not equal (used with CMPS and SCAS)
1174 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1178 // String manipulation instructions
1179 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1180 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1181 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1182 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1184 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1185 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1186 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1189 // Flag instructions
1190 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1191 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1192 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1193 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1194 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1195 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1196 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1198 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1200 // Table lookup instructions
1201 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1203 // ASCII Adjust After Addition
1204 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1205 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1207 // ASCII Adjust AX Before Division
1208 // sets AL, AH and EFLAGS and uses AL and AH
1209 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1210 "aad\t$src", []>, Requires<[In32BitMode]>;
1212 // ASCII Adjust AX After Multiply
1213 // sets AL, AH and EFLAGS and uses AL
1214 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1215 "aam\t$src", []>, Requires<[In32BitMode]>;
1217 // ASCII Adjust AL After Subtraction - sets
1218 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1219 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1221 // Decimal Adjust AL after Addition
1222 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1223 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1225 // Decimal Adjust AL after Subtraction
1226 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1227 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1229 // Check Array Index Against Bounds
1230 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1231 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1232 Requires<[In32BitMode]>;
1233 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1234 "bound\t{$src, $dst|$dst, $src}", []>,
1235 Requires<[In32BitMode]>;
1237 // Adjust RPL Field of Segment Selector
1238 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1239 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1240 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1241 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1243 //===----------------------------------------------------------------------===//
1245 //===----------------------------------------------------------------------===//
1247 include "X86InstrArithmetic.td"
1248 include "X86InstrCMovSetCC.td"
1249 include "X86InstrExtension.td"
1250 include "X86InstrControl.td"
1251 include "X86InstrShiftRotate.td"
1253 // X87 Floating Point Stack.
1254 include "X86InstrFPStack.td"
1256 // SIMD support (SSE, MMX and AVX)
1257 include "X86InstrFragmentsSIMD.td"
1259 // FMA - Fused Multiply-Add support (requires FMA)
1260 include "X86InstrFMA.td"
1262 // SSE, MMX and 3DNow! vector support.
1263 include "X86InstrSSE.td"
1264 include "X86InstrMMX.td"
1265 include "X86Instr3DNow.td"
1267 include "X86InstrVMX.td"
1269 // System instructions.
1270 include "X86InstrSystem.td"
1272 // Compiler Pseudo Instructions and Pat Patterns
1273 include "X86InstrCompiler.td"
1275 //===----------------------------------------------------------------------===//
1276 // Assembler Mnemonic Aliases
1277 //===----------------------------------------------------------------------===//
1279 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1280 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1282 def : MnemonicAlias<"cbw", "cbtw">;
1283 def : MnemonicAlias<"cwd", "cwtd">;
1284 def : MnemonicAlias<"cdq", "cltd">;
1285 def : MnemonicAlias<"cwde", "cwtl">;
1286 def : MnemonicAlias<"cdqe", "cltq">;
1288 // lret maps to lretl, it is not ambiguous with lretq.
1289 def : MnemonicAlias<"lret", "lretl">;
1291 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1292 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1293 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1294 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1295 def : MnemonicAlias<"popfd", "popfl">;
1297 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1298 // all modes. However: "push (addr)" and "push $42" should default to
1299 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1300 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1301 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1302 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1303 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1304 def : MnemonicAlias<"pushfd", "pushfl">;
1306 def : MnemonicAlias<"repe", "rep">;
1307 def : MnemonicAlias<"repz", "rep">;
1308 def : MnemonicAlias<"repnz", "repne">;
1310 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1311 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1313 def : MnemonicAlias<"salb", "shlb">;
1314 def : MnemonicAlias<"salw", "shlw">;
1315 def : MnemonicAlias<"sall", "shll">;
1316 def : MnemonicAlias<"salq", "shlq">;
1318 def : MnemonicAlias<"smovb", "movsb">;
1319 def : MnemonicAlias<"smovw", "movsw">;
1320 def : MnemonicAlias<"smovl", "movsl">;
1321 def : MnemonicAlias<"smovq", "movsq">;
1323 def : MnemonicAlias<"ud2a", "ud2">;
1324 def : MnemonicAlias<"verrw", "verr">;
1326 // System instruction aliases.
1327 def : MnemonicAlias<"iret", "iretl">;
1328 def : MnemonicAlias<"sysret", "sysretl">;
1330 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1331 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1332 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1333 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1334 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1335 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1336 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1337 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1340 // Floating point stack aliases.
1341 def : MnemonicAlias<"fcmovz", "fcmove">;
1342 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1343 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1344 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1345 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1346 def : MnemonicAlias<"fcomip", "fcompi">;
1347 def : MnemonicAlias<"fildq", "fildll">;
1348 def : MnemonicAlias<"fldcww", "fldcw">;
1349 def : MnemonicAlias<"fnstcww", "fnstcw">;
1350 def : MnemonicAlias<"fnstsww", "fnstsw">;
1351 def : MnemonicAlias<"fucomip", "fucompi">;
1352 def : MnemonicAlias<"fwait", "wait">;
1355 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1356 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1357 !strconcat(Prefix, NewCond, Suffix)>;
1359 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1360 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1361 /// example "setz" -> "sete".
1362 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1363 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1364 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1365 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1366 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1367 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1368 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1369 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1370 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1371 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1372 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1374 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1375 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1376 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1377 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1380 // Aliases for set<CC>
1381 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1382 // Aliases for j<CC>
1383 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1384 // Aliases for cmov<CC>{w,l,q}
1385 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1386 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1387 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1390 //===----------------------------------------------------------------------===//
1391 // Assembler Instruction Aliases
1392 //===----------------------------------------------------------------------===//
1394 // aad/aam default to base 10 if no operand is specified.
1395 def : InstAlias<"aad", (AAD8i8 10)>;
1396 def : InstAlias<"aam", (AAM8i8 10)>;
1399 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1400 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1401 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1402 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1404 // div and idiv aliases for explicit A register.
1405 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1406 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1407 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1408 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1409 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1410 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1411 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1412 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1413 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1414 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1415 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1416 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1417 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1418 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1419 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1420 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1424 // Various unary fpstack operations default to operating on on ST1.
1425 // For example, "fxch" -> "fxch %st(1)"
1426 def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
1427 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1428 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1429 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1430 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1431 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1432 def : InstAlias<"fxch", (XCH_F ST1)>;
1433 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1434 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1435 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1436 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1437 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1438 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1440 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1441 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1442 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1444 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst> {
1445 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), (Inst RST:$op)>;
1446 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), (Inst ST0)>;
1449 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1450 defm : FpUnaryAlias<"faddp", ADD_FPrST0>;
1451 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1452 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1453 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1454 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1455 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1456 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1457 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1458 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1459 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1460 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1461 defm : FpUnaryAlias<"fcomi", COM_FIr>;
1462 defm : FpUnaryAlias<"fucomi", UCOM_FIr>;
1463 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1464 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1467 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1468 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1469 // solely because gas supports it.
1470 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op)>;
1471 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1472 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1473 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1474 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1476 // We accept "fnstsw %eax" even though it only writes %ax.
1477 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1478 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1479 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1481 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1482 // this is compatible with what GAS does.
1483 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1484 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1485 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1486 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1488 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1489 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1490 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1491 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1492 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1493 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1494 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1496 // inb %dx -> inb %al, %dx
1497 def : InstAlias<"inb %dx", (IN8rr)>;
1498 def : InstAlias<"inw %dx", (IN16rr)>;
1499 def : InstAlias<"inl %dx", (IN32rr)>;
1500 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1501 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1502 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1505 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1506 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1507 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1508 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1509 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1510 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1511 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1513 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1514 // the move. All segment/mem forms are equivalent, this has the shortest
1516 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1517 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1519 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1520 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1522 // Match 'movq GR64, MMX' as an alias for movd.
1523 def : InstAlias<"movq $src, $dst", (MMX_MOVD64to64rr VR64:$dst, GR64:$src)>;
1524 def : InstAlias<"movq $src, $dst", (MMX_MOVD64from64rr GR64:$dst, VR64:$src)>;
1526 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1527 // alias for movsl. (as in rep; movsd)
1528 def : InstAlias<"movsd", (MOVSD)>;
1531 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>;
1532 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
1533 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>;
1534 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>;
1535 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>;
1536 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>;
1537 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>;
1540 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>;
1541 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>;
1542 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>;
1543 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>;
1544 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
1545 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
1546 // Note: No GR32->GR64 movzx form.
1548 // outb %dx -> outb %al, %dx
1549 def : InstAlias<"outb %dx", (OUT8rr)>;
1550 def : InstAlias<"outw %dx", (OUT16rr)>;
1551 def : InstAlias<"outl %dx", (OUT32rr)>;
1552 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1553 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1554 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1556 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1557 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1558 // errors, since its encoding is the most compact.
1559 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1561 // shld/shrd op,op -> shld op, op, 1
1562 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1563 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1564 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1565 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1566 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1567 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1569 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1570 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1571 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1572 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1573 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1574 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1576 /* FIXME: This is disabled because the asm matcher is currently incapable of
1577 * matching a fixed immediate like $1.
1578 // "shl X, $1" is an alias for "shl X".
1579 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1580 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1581 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1582 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1583 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1584 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1585 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1586 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1587 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1588 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1589 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1590 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1591 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1592 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1593 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1594 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1595 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1598 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1599 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1600 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1601 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1604 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1605 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1606 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1607 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1608 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1610 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1611 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1612 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1613 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1614 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;