3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86Void : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
86 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
88 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
89 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
91 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
92 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
94 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
100 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
122 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
124 def X86vastart_save_xmm_regs :
125 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
126 SDT_X86VASTART_SAVE_XMM_REGS,
127 [SDNPHasChain, SDNPVariadic]>;
129 def X86callseq_start :
130 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
131 [SDNPHasChain, SDNPOutFlag]>;
133 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
134 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
136 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
137 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
182 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
184 //===----------------------------------------------------------------------===//
185 // X86 Operand Definitions.
188 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
189 // the index operand of an address, to conform to x86 encoding restrictions.
190 def ptr_rc_nosp : PointerLikeRegClass<1>;
192 // *mem - Operand definitions for the funky X86 addressing mode operands.
194 def X86MemAsmOperand : AsmOperandClass {
198 def X86AbsMemAsmOperand : AsmOperandClass {
200 let SuperClass = X86MemAsmOperand;
202 def X86NoSegMemAsmOperand : AsmOperandClass {
203 let Name = "NoSegMem";
204 let SuperClass = X86MemAsmOperand;
206 class X86MemOperand<string printMethod> : Operand<iPTR> {
207 let PrintMethod = printMethod;
208 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
209 let ParserMatchClass = X86MemAsmOperand;
212 def opaque32mem : X86MemOperand<"printopaquemem">;
213 def opaque48mem : X86MemOperand<"printopaquemem">;
214 def opaque80mem : X86MemOperand<"printopaquemem">;
215 def opaque512mem : X86MemOperand<"printopaquemem">;
217 def i8mem : X86MemOperand<"printi8mem">;
218 def i16mem : X86MemOperand<"printi16mem">;
219 def i32mem : X86MemOperand<"printi32mem">;
220 def i64mem : X86MemOperand<"printi64mem">;
221 def i128mem : X86MemOperand<"printi128mem">;
222 //def i256mem : X86MemOperand<"printi256mem">;
223 def f32mem : X86MemOperand<"printf32mem">;
224 def f64mem : X86MemOperand<"printf64mem">;
225 def f80mem : X86MemOperand<"printf80mem">;
226 def f128mem : X86MemOperand<"printf128mem">;
227 //def f256mem : X86MemOperand<"printf256mem">;
229 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
230 // plain GR64, so that it doesn't potentially require a REX prefix.
231 def i8mem_NOREX : Operand<i64> {
232 let PrintMethod = "printi8mem";
233 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
234 let ParserMatchClass = X86MemAsmOperand;
237 // Special i32mem for addresses of load folding tail calls. These are not
238 // allowed to use callee-saved registers since they must be scheduled
239 // after callee-saved register are popped.
240 def i32mem_TC : Operand<i32> {
241 let PrintMethod = "printi32mem";
242 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
243 let ParserMatchClass = X86MemAsmOperand;
246 def lea32mem : Operand<i32> {
247 let PrintMethod = "printlea32mem";
248 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
249 let ParserMatchClass = X86NoSegMemAsmOperand;
252 let ParserMatchClass = X86AbsMemAsmOperand,
253 PrintMethod = "print_pcrel_imm" in {
254 def i32imm_pcrel : Operand<i32>;
256 def offset8 : Operand<i64>;
257 def offset16 : Operand<i64>;
258 def offset32 : Operand<i64>;
259 def offset64 : Operand<i64>;
261 // Branch targets have OtherVT type and print as pc-relative values.
262 def brtarget : Operand<OtherVT>;
263 def brtarget8 : Operand<OtherVT>;
267 def SSECC : Operand<i8> {
268 let PrintMethod = "printSSECC";
271 def ImmSExt8AsmOperand : AsmOperandClass {
272 let Name = "ImmSExt8";
273 let SuperClass = ImmAsmOperand;
276 // A couple of more descriptive operand definitions.
277 // 16-bits but only 8 bits are significant.
278 def i16i8imm : Operand<i16> {
279 let ParserMatchClass = ImmSExt8AsmOperand;
281 // 32-bits but only 8 bits are significant.
282 def i32i8imm : Operand<i32> {
283 let ParserMatchClass = ImmSExt8AsmOperand;
286 //===----------------------------------------------------------------------===//
287 // X86 Complex Pattern Definitions.
290 // Define X86 specific addressing mode.
291 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
292 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
293 [add, sub, mul, X86mul_imm, shl, or, frameindex],
295 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
296 [tglobaltlsaddr], []>;
298 //===----------------------------------------------------------------------===//
299 // X86 Instruction Predicate Definitions.
300 def HasCMov : Predicate<"Subtarget->hasCMov()">;
301 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
302 def HasMMX : Predicate<"Subtarget->hasMMX()">;
303 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
304 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
305 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
306 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
307 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
308 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
309 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
310 def HasAVX : Predicate<"Subtarget->hasAVX()">;
311 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
312 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
313 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
314 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
315 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
316 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
317 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
318 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
319 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
320 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
321 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
322 "TM.getCodeModel() != CodeModel::Kernel">;
323 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
324 "TM.getCodeModel() == CodeModel::Kernel">;
325 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
326 def OptForSize : Predicate<"OptForSize">;
327 def OptForSpeed : Predicate<"!OptForSize">;
328 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
329 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
331 //===----------------------------------------------------------------------===//
332 // X86 Instruction Format Definitions.
335 include "X86InstrFormats.td"
337 //===----------------------------------------------------------------------===//
338 // Pattern fragments...
341 // X86 specific condition code. These correspond to CondCode in
342 // X86InstrInfo.h. They must be kept in synch.
343 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
344 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
345 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
346 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
347 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
348 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
349 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
350 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
351 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
352 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
353 def X86_COND_NO : PatLeaf<(i8 10)>;
354 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
355 def X86_COND_NS : PatLeaf<(i8 12)>;
356 def X86_COND_O : PatLeaf<(i8 13)>;
357 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
358 def X86_COND_S : PatLeaf<(i8 15)>;
360 def immSext8 : PatLeaf<(imm), [{
361 return N->getSExtValue() == (int8_t)N->getSExtValue();
364 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
365 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
367 /// Load patterns: these constraint the match to the right address space.
368 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
369 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
370 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
371 if (PT->getAddressSpace() > 255)
376 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
377 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
378 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
379 return PT->getAddressSpace() == 256;
383 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 return PT->getAddressSpace() == 257;
391 // Helper fragments for loads.
392 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
393 // known to be 32-bit aligned or better. Ditto for i8 to i16.
394 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
395 LoadSDNode *LD = cast<LoadSDNode>(N);
396 if (const Value *Src = LD->getSrcValue())
397 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
398 if (PT->getAddressSpace() > 255)
400 ISD::LoadExtType ExtType = LD->getExtensionType();
401 if (ExtType == ISD::NON_EXTLOAD)
403 if (ExtType == ISD::EXTLOAD)
404 return LD->getAlignment() >= 2 && !LD->isVolatile();
408 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
409 LoadSDNode *LD = cast<LoadSDNode>(N);
410 if (const Value *Src = LD->getSrcValue())
411 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
412 if (PT->getAddressSpace() > 255)
414 ISD::LoadExtType ExtType = LD->getExtensionType();
415 if (ExtType == ISD::EXTLOAD)
416 return LD->getAlignment() >= 2 && !LD->isVolatile();
420 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
421 LoadSDNode *LD = cast<LoadSDNode>(N);
422 if (const Value *Src = LD->getSrcValue())
423 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
424 if (PT->getAddressSpace() > 255)
426 ISD::LoadExtType ExtType = LD->getExtensionType();
427 if (ExtType == ISD::NON_EXTLOAD)
429 if (ExtType == ISD::EXTLOAD)
430 return LD->getAlignment() >= 4 && !LD->isVolatile();
434 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
435 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
436 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
437 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
438 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
440 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
441 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
442 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
444 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
445 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
446 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
447 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
448 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
449 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
451 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
452 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
453 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
454 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
455 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
456 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
459 // An 'and' node with a single use.
460 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
461 return N->hasOneUse();
463 // An 'srl' node with a single use.
464 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
465 return N->hasOneUse();
467 // An 'trunc' node with a single use.
468 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
469 return N->hasOneUse();
472 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
473 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
474 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
475 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
477 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
478 APInt Mask = APInt::getAllOnesValue(BitWidth);
479 APInt KnownZero0, KnownOne0;
480 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
481 APInt KnownZero1, KnownOne1;
482 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
483 return (~KnownZero0 & ~KnownZero1) == 0;
487 // 'shld' and 'shrd' instruction patterns. Note that even though these have
488 // the srl and shl in their patterns, the C++ code must still check for them,
489 // because predicates are tested before children nodes are explored.
491 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
492 (or (srl node:$src1, node:$amt1),
493 (shl node:$src2, node:$amt2)), [{
494 assert(N->getOpcode() == ISD::OR);
495 return N->getOperand(0).getOpcode() == ISD::SRL &&
496 N->getOperand(1).getOpcode() == ISD::SHL &&
497 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
498 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
499 N->getOperand(0).getConstantOperandVal(1) ==
500 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
503 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
504 (or (shl node:$src1, node:$amt1),
505 (srl node:$src2, node:$amt2)), [{
506 assert(N->getOpcode() == ISD::OR);
507 return N->getOperand(0).getOpcode() == ISD::SHL &&
508 N->getOperand(1).getOpcode() == ISD::SRL &&
509 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
510 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
511 N->getOperand(0).getConstantOperandVal(1) ==
512 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
515 //===----------------------------------------------------------------------===//
516 // Instruction list...
519 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
520 // a stack adjustment and the codegen must know that they may modify the stack
521 // pointer before prolog-epilog rewriting occurs.
522 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
523 // sub / add which can clobber EFLAGS.
524 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
525 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
527 [(X86callseq_start timm:$amt)]>,
528 Requires<[In32BitMode]>;
529 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
531 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
532 Requires<[In32BitMode]>;
535 // x86-64 va_start lowering magic.
536 let usesCustomInserter = 1 in {
537 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
540 i64imm:$regsavefi, i64imm:$offset,
542 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
543 [(X86vastart_save_xmm_regs GR8:$al,
547 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
548 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
549 // one go. Touching the stack at 4K increments is necessary to ensure that the
550 // guard pages used by the OS virtual memory manager are allocated in correct
552 // The main point of having separate instruction are extra unmodelled effects
553 // (compared to ordinary calls) like stack pointer change.
555 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
556 "# dynamic stack allocation",
561 let neverHasSideEffects = 1 in {
562 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
563 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
564 "nop{w}\t$zero", []>, TB, OpSize;
565 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
566 "nop{l}\t$zero", []>, TB;
570 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
571 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
572 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
573 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
575 // PIC base construction. This expands to code that looks like this:
578 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
579 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
582 //===----------------------------------------------------------------------===//
583 // Control Flow Instructions.
586 // Return instructions.
587 let isTerminator = 1, isReturn = 1, isBarrier = 1,
588 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
589 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
592 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
594 [(X86retflag timm:$amt)]>;
595 def LRET : I <0xCB, RawFrm, (outs), (ins),
597 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
601 // Unconditional branches.
602 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
603 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
604 "jmp\t$dst", [(br bb:$dst)]>;
605 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
609 // Conditional Branches.
610 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
611 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
612 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
613 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
614 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
618 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
619 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
620 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
621 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
622 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
623 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
624 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
625 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
626 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
627 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
628 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
629 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
630 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
631 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
632 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
633 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
635 // FIXME: What about the CX/RCX versions of this instruction?
636 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
637 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
642 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
643 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
644 [(brind GR32:$dst)]>;
645 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
646 [(brind (loadi32 addr:$dst))]>;
648 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
649 (ins i16imm:$seg, i16imm:$off),
650 "ljmp{w}\t$seg, $off", []>, OpSize;
651 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
652 (ins i16imm:$seg, i32imm:$off),
653 "ljmp{l}\t$seg, $off", []>;
655 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
656 "ljmp{w}\t{*}$dst", []>, OpSize;
657 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
658 "ljmp{l}\t{*}$dst", []>;
664 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
665 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
666 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
668 //===----------------------------------------------------------------------===//
669 // Call Instructions...
672 // All calls clobber the non-callee saved registers. ESP is marked as
673 // a use to prevent stack-pointer assignments that appear immediately
674 // before calls from potentially appearing dead. Uses for argument
675 // registers are added manually.
676 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
677 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
678 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
679 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
681 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
682 (outs), (ins i32imm_pcrel:$dst,variable_ops),
684 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
685 "call\t{*}$dst", [(X86call GR32:$dst)]>;
686 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
687 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
689 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
690 (ins i16imm:$seg, i16imm:$off),
691 "lcall{w}\t$seg, $off", []>, OpSize;
692 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
693 (ins i16imm:$seg, i32imm:$off),
694 "lcall{l}\t$seg, $off", []>;
696 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
697 "lcall{w}\t{*}$dst", []>, OpSize;
698 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
699 "lcall{l}\t{*}$dst", []>;
702 // Constructing a stack frame.
704 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
705 "enter\t$len, $lvl", []>;
709 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
710 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
711 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
712 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
713 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
715 def TCRETURNdi : I<0, Pseudo, (outs),
716 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
717 "#TC_RETURN $dst $offset", []>;
718 def TCRETURNri : I<0, Pseudo, (outs),
719 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
720 "#TC_RETURN $dst $offset", []>;
721 def TCRETURNmi : I<0, Pseudo, (outs),
722 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
723 "#TC_RETURN $dst $offset", []>;
725 // FIXME: The should be pseudo instructions that are lowered when going to
727 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
728 (ins i32imm_pcrel:$dst, variable_ops),
729 "jmp\t$dst # TAILCALL",
731 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
732 "jmp{l}\t{*}$dst # TAILCALL",
734 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
735 "jmp{l}\t{*}$dst # TAILCALL", []>;
738 //===----------------------------------------------------------------------===//
739 // Miscellaneous Instructions...
741 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
742 def LEAVE : I<0xC9, RawFrm,
743 (outs), (ins), "leave", []>;
745 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
746 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
747 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
748 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
749 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
750 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
751 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
752 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
754 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
756 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
758 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
759 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
761 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
763 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
764 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
767 let mayStore = 1 in {
768 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
770 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
771 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
773 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
775 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
776 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
780 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
781 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
782 "push{l}\t$imm", []>;
783 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
784 "push{l}\t$imm", []>;
785 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
786 "push{l}\t$imm", []>;
789 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
790 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
791 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
793 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
794 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
795 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
798 let isTwoAddress = 1 in // GR32 = bswap GR32
799 def BSWAP32r : I<0xC8, AddRegFrm,
800 (outs GR32:$dst), (ins GR32:$src),
802 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
805 // Bit scan instructions.
806 let Defs = [EFLAGS] in {
807 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
808 "bsf{w}\t{$src, $dst|$dst, $src}",
809 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
810 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
811 "bsf{w}\t{$src, $dst|$dst, $src}",
812 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
813 (implicit EFLAGS)]>, TB;
814 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
815 "bsf{l}\t{$src, $dst|$dst, $src}",
816 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
817 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
818 "bsf{l}\t{$src, $dst|$dst, $src}",
819 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
820 (implicit EFLAGS)]>, TB;
822 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
823 "bsr{w}\t{$src, $dst|$dst, $src}",
824 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
825 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
826 "bsr{w}\t{$src, $dst|$dst, $src}",
827 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
828 (implicit EFLAGS)]>, TB;
829 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
830 "bsr{l}\t{$src, $dst|$dst, $src}",
831 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
832 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
833 "bsr{l}\t{$src, $dst|$dst, $src}",
834 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
835 (implicit EFLAGS)]>, TB;
838 let neverHasSideEffects = 1 in
839 def LEA16r : I<0x8D, MRMSrcMem,
840 (outs GR16:$dst), (ins lea32mem:$src),
841 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
842 let isReMaterializable = 1 in
843 def LEA32r : I<0x8D, MRMSrcMem,
844 (outs GR32:$dst), (ins lea32mem:$src),
845 "lea{l}\t{$src|$dst}, {$dst|$src}",
846 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
848 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
849 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
850 [(X86rep_movs i8)]>, REP;
851 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
852 [(X86rep_movs i16)]>, REP, OpSize;
853 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
854 [(X86rep_movs i32)]>, REP;
857 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
858 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
859 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
860 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
861 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
864 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
865 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
866 [(X86rep_stos i8)]>, REP;
867 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
868 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
869 [(X86rep_stos i16)]>, REP, OpSize;
870 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
871 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
872 [(X86rep_stos i32)]>, REP;
874 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
875 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
876 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
877 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
878 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
879 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
880 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
882 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
883 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
884 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
886 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
887 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
888 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
890 let Defs = [RAX, RDX] in
891 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
894 let Defs = [RAX, RCX, RDX] in
895 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
897 let isBarrier = 1, hasCtrlDep = 1 in {
898 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
901 def SYSCALL : I<0x05, RawFrm,
902 (outs), (ins), "syscall", []>, TB;
903 def SYSRET : I<0x07, RawFrm,
904 (outs), (ins), "sysret", []>, TB;
905 def SYSENTER : I<0x34, RawFrm,
906 (outs), (ins), "sysenter", []>, TB;
907 def SYSEXIT : I<0x35, RawFrm,
908 (outs), (ins), "sysexit", []>, TB;
910 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
913 //===----------------------------------------------------------------------===//
914 // Input/Output Instructions...
916 let Defs = [AL], Uses = [DX] in
917 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
918 "in{b}\t{%dx, %al|%AL, %DX}", []>;
919 let Defs = [AX], Uses = [DX] in
920 def IN16rr : I<0xED, RawFrm, (outs), (ins),
921 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
922 let Defs = [EAX], Uses = [DX] in
923 def IN32rr : I<0xED, RawFrm, (outs), (ins),
924 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
927 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
928 "in{b}\t{$port, %al|%AL, $port}", []>;
930 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
931 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
933 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
934 "in{l}\t{$port, %eax|%EAX, $port}", []>;
936 let Uses = [DX, AL] in
937 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
938 "out{b}\t{%al, %dx|%DX, %AL}", []>;
939 let Uses = [DX, AX] in
940 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
941 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
942 let Uses = [DX, EAX] in
943 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
944 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
947 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
948 "out{b}\t{%al, $port|$port, %AL}", []>;
950 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
951 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
953 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
954 "out{l}\t{%eax, $port|$port, %EAX}", []>;
956 def IN8 : I<0x6C, RawFrm, (outs), (ins),
958 def IN16 : I<0x6D, RawFrm, (outs), (ins),
959 "ins{w}", []>, OpSize;
960 def IN32 : I<0x6D, RawFrm, (outs), (ins),
963 //===----------------------------------------------------------------------===//
964 // Move Instructions...
966 let neverHasSideEffects = 1 in {
967 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
968 "mov{b}\t{$src, $dst|$dst, $src}", []>;
969 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
970 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
971 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
972 "mov{l}\t{$src, $dst|$dst, $src}", []>;
974 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
975 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
976 "mov{b}\t{$src, $dst|$dst, $src}",
977 [(set GR8:$dst, imm:$src)]>;
978 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
979 "mov{w}\t{$src, $dst|$dst, $src}",
980 [(set GR16:$dst, imm:$src)]>, OpSize;
981 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
982 "mov{l}\t{$src, $dst|$dst, $src}",
983 [(set GR32:$dst, imm:$src)]>;
986 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
987 "mov{b}\t{$src, $dst|$dst, $src}",
988 [(store (i8 imm:$src), addr:$dst)]>;
989 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
990 "mov{w}\t{$src, $dst|$dst, $src}",
991 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
992 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
993 "mov{l}\t{$src, $dst|$dst, $src}",
994 [(store (i32 imm:$src), addr:$dst)]>;
996 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
997 "mov{b}\t{$src, %al|%al, $src}", []>;
998 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
999 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1000 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1001 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1003 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1004 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1005 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1006 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1007 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1008 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1010 // Moves to and from segment registers
1011 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1013 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1014 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1015 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1016 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1017 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1018 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1020 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1021 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1022 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1023 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1024 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1025 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1027 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1028 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1029 "mov{b}\t{$src, $dst|$dst, $src}",
1030 [(set GR8:$dst, (loadi8 addr:$src))]>;
1031 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1032 "mov{w}\t{$src, $dst|$dst, $src}",
1033 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1034 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1035 "mov{l}\t{$src, $dst|$dst, $src}",
1036 [(set GR32:$dst, (loadi32 addr:$src))]>;
1039 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1040 "mov{b}\t{$src, $dst|$dst, $src}",
1041 [(store GR8:$src, addr:$dst)]>;
1042 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1043 "mov{w}\t{$src, $dst|$dst, $src}",
1044 [(store GR16:$src, addr:$dst)]>, OpSize;
1045 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1046 "mov{l}\t{$src, $dst|$dst, $src}",
1047 [(store GR32:$src, addr:$dst)]>;
1049 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1050 let neverHasSideEffects = 1 in
1051 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1052 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1055 canFoldAsLoad = 1, isReMaterializable = 1 in
1056 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1057 "mov{l}\t{$src, $dst|$dst, $src}",
1061 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1062 "mov{l}\t{$src, $dst|$dst, $src}",
1065 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1066 // that they can be used for copying and storing h registers, which can't be
1067 // encoded when a REX prefix is present.
1068 let neverHasSideEffects = 1 in
1069 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1070 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1071 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1073 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1074 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1075 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1077 canFoldAsLoad = 1, isReMaterializable = 1 in
1078 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1079 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1080 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1082 // Moves to and from debug registers
1083 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1084 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1085 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1086 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1088 // Moves to and from control registers
1089 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1090 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1091 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1092 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1094 //===----------------------------------------------------------------------===//
1095 // Fixed-Register Multiplication and Division Instructions...
1098 // Extra precision multiplication
1100 // AL is really implied by AX, by the registers in Defs must match the
1101 // SDNode results (i8, i32).
1102 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1103 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1104 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1105 // This probably ought to be moved to a def : Pat<> if the
1106 // syntax can be accepted.
1107 [(set AL, (mul AL, GR8:$src)),
1108 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1110 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1111 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1113 []>, OpSize; // AX,DX = AX*GR16
1115 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1116 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1118 []>; // EAX,EDX = EAX*GR32
1120 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1121 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1123 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1124 // This probably ought to be moved to a def : Pat<> if the
1125 // syntax can be accepted.
1126 [(set AL, (mul AL, (loadi8 addr:$src))),
1127 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1129 let mayLoad = 1, neverHasSideEffects = 1 in {
1130 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1131 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1133 []>, OpSize; // AX,DX = AX*[mem16]
1135 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1136 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1138 []>; // EAX,EDX = EAX*[mem32]
1141 let neverHasSideEffects = 1 in {
1142 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1143 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1145 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1146 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1147 OpSize; // AX,DX = AX*GR16
1148 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1149 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1150 // EAX,EDX = EAX*GR32
1151 let mayLoad = 1 in {
1152 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1153 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1154 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1155 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1156 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1157 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1158 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1159 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1160 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1162 } // neverHasSideEffects
1164 // unsigned division/remainder
1165 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1166 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1167 "div{b}\t$src", []>;
1168 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1169 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1170 "div{w}\t$src", []>, OpSize;
1171 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1172 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1173 "div{l}\t$src", []>;
1174 let mayLoad = 1 in {
1175 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1176 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1177 "div{b}\t$src", []>;
1178 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1179 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1180 "div{w}\t$src", []>, OpSize;
1181 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1182 // EDX:EAX/[mem32] = EAX,EDX
1183 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1184 "div{l}\t$src", []>;
1187 // Signed division/remainder.
1188 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1189 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1190 "idiv{b}\t$src", []>;
1191 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1192 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1193 "idiv{w}\t$src", []>, OpSize;
1194 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1195 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1196 "idiv{l}\t$src", []>;
1197 let mayLoad = 1, mayLoad = 1 in {
1198 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1199 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1200 "idiv{b}\t$src", []>;
1201 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1202 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1203 "idiv{w}\t$src", []>, OpSize;
1204 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1205 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1206 // EDX:EAX/[mem32] = EAX,EDX
1207 "idiv{l}\t$src", []>;
1210 //===----------------------------------------------------------------------===//
1211 // Two address Instructions.
1213 let isTwoAddress = 1 in {
1215 // Conditional moves
1216 let Uses = [EFLAGS] in {
1218 let Predicates = [HasCMov] in {
1219 let isCommutable = 1 in {
1220 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1221 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1222 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1224 X86_COND_B, EFLAGS))]>,
1226 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1227 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1228 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1229 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1230 X86_COND_B, EFLAGS))]>,
1232 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1233 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1234 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1236 X86_COND_AE, EFLAGS))]>,
1238 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1239 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1240 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1242 X86_COND_AE, EFLAGS))]>,
1244 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1245 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1246 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1248 X86_COND_E, EFLAGS))]>,
1250 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1251 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1252 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1254 X86_COND_E, EFLAGS))]>,
1256 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1257 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1258 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1260 X86_COND_NE, EFLAGS))]>,
1262 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1263 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1264 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1266 X86_COND_NE, EFLAGS))]>,
1268 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1269 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1270 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1272 X86_COND_BE, EFLAGS))]>,
1274 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1275 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1276 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1278 X86_COND_BE, EFLAGS))]>,
1280 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1281 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1282 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1284 X86_COND_A, EFLAGS))]>,
1286 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1287 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1288 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1290 X86_COND_A, EFLAGS))]>,
1292 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1293 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1294 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1296 X86_COND_L, EFLAGS))]>,
1298 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1299 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1300 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1302 X86_COND_L, EFLAGS))]>,
1304 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1305 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1306 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1308 X86_COND_GE, EFLAGS))]>,
1310 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1311 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1312 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1314 X86_COND_GE, EFLAGS))]>,
1316 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1317 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1318 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1320 X86_COND_LE, EFLAGS))]>,
1322 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1323 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1324 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1326 X86_COND_LE, EFLAGS))]>,
1328 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1329 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1330 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1332 X86_COND_G, EFLAGS))]>,
1334 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1335 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1336 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1338 X86_COND_G, EFLAGS))]>,
1340 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1341 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1342 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1344 X86_COND_S, EFLAGS))]>,
1346 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1347 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1348 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1350 X86_COND_S, EFLAGS))]>,
1352 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1353 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1354 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1356 X86_COND_NS, EFLAGS))]>,
1358 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1359 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1360 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1362 X86_COND_NS, EFLAGS))]>,
1364 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1365 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1366 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1368 X86_COND_P, EFLAGS))]>,
1370 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1371 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1372 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1374 X86_COND_P, EFLAGS))]>,
1376 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1377 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1378 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1380 X86_COND_NP, EFLAGS))]>,
1382 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1383 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1384 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1386 X86_COND_NP, EFLAGS))]>,
1388 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1389 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1390 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1392 X86_COND_O, EFLAGS))]>,
1394 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1395 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1396 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1398 X86_COND_O, EFLAGS))]>,
1400 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1401 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1402 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1404 X86_COND_NO, EFLAGS))]>,
1406 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1407 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1408 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1410 X86_COND_NO, EFLAGS))]>,
1412 } // isCommutable = 1
1414 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1415 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1416 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1418 X86_COND_B, EFLAGS))]>,
1420 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1421 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1422 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1424 X86_COND_B, EFLAGS))]>,
1426 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1427 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1428 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1430 X86_COND_AE, EFLAGS))]>,
1432 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1433 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1434 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1436 X86_COND_AE, EFLAGS))]>,
1438 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1439 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1440 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1442 X86_COND_E, EFLAGS))]>,
1444 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1445 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1446 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1448 X86_COND_E, EFLAGS))]>,
1450 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1451 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1452 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1454 X86_COND_NE, EFLAGS))]>,
1456 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1457 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1458 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1460 X86_COND_NE, EFLAGS))]>,
1462 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1463 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1464 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1466 X86_COND_BE, EFLAGS))]>,
1468 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1469 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1470 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1472 X86_COND_BE, EFLAGS))]>,
1474 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1475 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1476 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1478 X86_COND_A, EFLAGS))]>,
1480 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1481 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1482 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1484 X86_COND_A, EFLAGS))]>,
1486 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1487 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1488 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1490 X86_COND_L, EFLAGS))]>,
1492 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1493 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1494 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1496 X86_COND_L, EFLAGS))]>,
1498 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1499 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1500 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1502 X86_COND_GE, EFLAGS))]>,
1504 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1505 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1506 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1508 X86_COND_GE, EFLAGS))]>,
1510 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1511 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1512 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1514 X86_COND_LE, EFLAGS))]>,
1516 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1517 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1518 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1520 X86_COND_LE, EFLAGS))]>,
1522 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1523 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1524 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1526 X86_COND_G, EFLAGS))]>,
1528 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1529 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1530 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1532 X86_COND_G, EFLAGS))]>,
1534 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1535 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1536 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1538 X86_COND_S, EFLAGS))]>,
1540 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1541 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1542 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1544 X86_COND_S, EFLAGS))]>,
1546 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1547 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1548 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1550 X86_COND_NS, EFLAGS))]>,
1552 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1553 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1554 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1556 X86_COND_NS, EFLAGS))]>,
1558 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1559 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1560 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1562 X86_COND_P, EFLAGS))]>,
1564 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1565 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1566 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1568 X86_COND_P, EFLAGS))]>,
1570 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1571 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1572 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1574 X86_COND_NP, EFLAGS))]>,
1576 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1577 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1578 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1580 X86_COND_NP, EFLAGS))]>,
1582 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1583 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1584 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1586 X86_COND_O, EFLAGS))]>,
1588 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1589 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1590 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1592 X86_COND_O, EFLAGS))]>,
1594 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1595 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1596 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1598 X86_COND_NO, EFLAGS))]>,
1600 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1601 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1602 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1604 X86_COND_NO, EFLAGS))]>,
1606 } // Predicates = [HasCMov]
1608 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1609 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1610 // however that requires promoting the operands, and can induce additional
1611 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1612 // clobber EFLAGS, because if one of the operands is zero, the expansion
1613 // could involve an xor.
1614 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1615 def CMOV_GR8 : I<0, Pseudo,
1616 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1617 "#CMOV_GR8 PSEUDO!",
1618 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1619 imm:$cond, EFLAGS))]>;
1621 let Predicates = [NoCMov] in {
1622 def CMOV_GR32 : I<0, Pseudo,
1623 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1624 "#CMOV_GR32* PSEUDO!",
1626 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1627 def CMOV_GR16 : I<0, Pseudo,
1628 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1629 "#CMOV_GR16* PSEUDO!",
1631 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1632 def CMOV_RFP32 : I<0, Pseudo,
1633 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1634 "#CMOV_RFP32 PSEUDO!",
1635 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1637 def CMOV_RFP64 : I<0, Pseudo,
1638 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1639 "#CMOV_RFP64 PSEUDO!",
1640 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1642 def CMOV_RFP80 : I<0, Pseudo,
1643 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1644 "#CMOV_RFP80 PSEUDO!",
1645 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1647 } // Predicates = [NoCMov]
1648 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1649 } // Uses = [EFLAGS]
1652 // unary instructions
1653 let CodeSize = 2 in {
1654 let Defs = [EFLAGS] in {
1655 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1656 [(set GR8:$dst, (ineg GR8:$src)),
1657 (implicit EFLAGS)]>;
1658 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1659 [(set GR16:$dst, (ineg GR16:$src)),
1660 (implicit EFLAGS)]>, OpSize;
1661 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1662 [(set GR32:$dst, (ineg GR32:$src)),
1663 (implicit EFLAGS)]>;
1664 let isTwoAddress = 0 in {
1665 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1666 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1667 (implicit EFLAGS)]>;
1668 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1669 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1670 (implicit EFLAGS)]>, OpSize;
1671 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1672 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1673 (implicit EFLAGS)]>;
1675 } // Defs = [EFLAGS]
1677 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1678 let AddedComplexity = 15 in {
1679 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1680 [(set GR8:$dst, (not GR8:$src))]>;
1681 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1682 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1683 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1684 [(set GR32:$dst, (not GR32:$src))]>;
1686 let isTwoAddress = 0 in {
1687 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1688 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1689 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1690 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1691 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1692 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1696 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1697 let Defs = [EFLAGS] in {
1699 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1700 [(set GR8:$dst, (add GR8:$src, 1)),
1701 (implicit EFLAGS)]>;
1702 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1703 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1705 [(set GR16:$dst, (add GR16:$src, 1)),
1706 (implicit EFLAGS)]>,
1707 OpSize, Requires<[In32BitMode]>;
1708 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1710 [(set GR32:$dst, (add GR32:$src, 1)),
1711 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1713 let isTwoAddress = 0, CodeSize = 2 in {
1714 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1715 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1716 (implicit EFLAGS)]>;
1717 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1718 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1719 (implicit EFLAGS)]>,
1720 OpSize, Requires<[In32BitMode]>;
1721 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1722 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1723 (implicit EFLAGS)]>,
1724 Requires<[In32BitMode]>;
1728 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1729 [(set GR8:$dst, (add GR8:$src, -1)),
1730 (implicit EFLAGS)]>;
1731 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1732 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1734 [(set GR16:$dst, (add GR16:$src, -1)),
1735 (implicit EFLAGS)]>,
1736 OpSize, Requires<[In32BitMode]>;
1737 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1739 [(set GR32:$dst, (add GR32:$src, -1)),
1740 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1743 let isTwoAddress = 0, CodeSize = 2 in {
1744 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1745 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1746 (implicit EFLAGS)]>;
1747 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1748 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1749 (implicit EFLAGS)]>,
1750 OpSize, Requires<[In32BitMode]>;
1751 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1752 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1753 (implicit EFLAGS)]>,
1754 Requires<[In32BitMode]>;
1756 } // Defs = [EFLAGS]
1758 // Logical operators...
1759 let Defs = [EFLAGS] in {
1760 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1761 def AND8rr : I<0x20, MRMDestReg,
1762 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1763 "and{b}\t{$src2, $dst|$dst, $src2}",
1764 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1765 (implicit EFLAGS)]>;
1766 def AND16rr : I<0x21, MRMDestReg,
1767 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1768 "and{w}\t{$src2, $dst|$dst, $src2}",
1769 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1770 (implicit EFLAGS)]>, OpSize;
1771 def AND32rr : I<0x21, MRMDestReg,
1772 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1773 "and{l}\t{$src2, $dst|$dst, $src2}",
1774 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1775 (implicit EFLAGS)]>;
1778 // AND instructions with the destination register in REG and the source register
1779 // in R/M. Included for the disassembler.
1780 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1781 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1782 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1783 (ins GR16:$src1, GR16:$src2),
1784 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1785 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1786 (ins GR32:$src1, GR32:$src2),
1787 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1789 def AND8rm : I<0x22, MRMSrcMem,
1790 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1791 "and{b}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1793 (implicit EFLAGS)]>;
1794 def AND16rm : I<0x23, MRMSrcMem,
1795 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1796 "and{w}\t{$src2, $dst|$dst, $src2}",
1797 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1798 (implicit EFLAGS)]>, OpSize;
1799 def AND32rm : I<0x23, MRMSrcMem,
1800 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1801 "and{l}\t{$src2, $dst|$dst, $src2}",
1802 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1803 (implicit EFLAGS)]>;
1805 def AND8ri : Ii8<0x80, MRM4r,
1806 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1807 "and{b}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1809 (implicit EFLAGS)]>;
1810 def AND16ri : Ii16<0x81, MRM4r,
1811 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1812 "and{w}\t{$src2, $dst|$dst, $src2}",
1813 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1814 (implicit EFLAGS)]>, OpSize;
1815 def AND32ri : Ii32<0x81, MRM4r,
1816 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1817 "and{l}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1819 (implicit EFLAGS)]>;
1820 def AND16ri8 : Ii8<0x83, MRM4r,
1821 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1822 "and{w}\t{$src2, $dst|$dst, $src2}",
1823 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1824 (implicit EFLAGS)]>,
1826 def AND32ri8 : Ii8<0x83, MRM4r,
1827 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1828 "and{l}\t{$src2, $dst|$dst, $src2}",
1829 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1830 (implicit EFLAGS)]>;
1832 let isTwoAddress = 0 in {
1833 def AND8mr : I<0x20, MRMDestMem,
1834 (outs), (ins i8mem :$dst, GR8 :$src),
1835 "and{b}\t{$src, $dst|$dst, $src}",
1836 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1837 (implicit EFLAGS)]>;
1838 def AND16mr : I<0x21, MRMDestMem,
1839 (outs), (ins i16mem:$dst, GR16:$src),
1840 "and{w}\t{$src, $dst|$dst, $src}",
1841 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1842 (implicit EFLAGS)]>,
1844 def AND32mr : I<0x21, MRMDestMem,
1845 (outs), (ins i32mem:$dst, GR32:$src),
1846 "and{l}\t{$src, $dst|$dst, $src}",
1847 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1848 (implicit EFLAGS)]>;
1849 def AND8mi : Ii8<0x80, MRM4m,
1850 (outs), (ins i8mem :$dst, i8imm :$src),
1851 "and{b}\t{$src, $dst|$dst, $src}",
1852 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1853 (implicit EFLAGS)]>;
1854 def AND16mi : Ii16<0x81, MRM4m,
1855 (outs), (ins i16mem:$dst, i16imm:$src),
1856 "and{w}\t{$src, $dst|$dst, $src}",
1857 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1858 (implicit EFLAGS)]>,
1860 def AND32mi : Ii32<0x81, MRM4m,
1861 (outs), (ins i32mem:$dst, i32imm:$src),
1862 "and{l}\t{$src, $dst|$dst, $src}",
1863 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1864 (implicit EFLAGS)]>;
1865 def AND16mi8 : Ii8<0x83, MRM4m,
1866 (outs), (ins i16mem:$dst, i16i8imm :$src),
1867 "and{w}\t{$src, $dst|$dst, $src}",
1868 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1869 (implicit EFLAGS)]>,
1871 def AND32mi8 : Ii8<0x83, MRM4m,
1872 (outs), (ins i32mem:$dst, i32i8imm :$src),
1873 "and{l}\t{$src, $dst|$dst, $src}",
1874 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1875 (implicit EFLAGS)]>;
1877 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1878 "and{b}\t{$src, %al|%al, $src}", []>;
1879 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1880 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1881 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1882 "and{l}\t{$src, %eax|%eax, $src}", []>;
1887 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1888 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1889 (ins GR8 :$src1, GR8 :$src2),
1890 "or{b}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1892 (implicit EFLAGS)]>;
1893 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1894 (ins GR16:$src1, GR16:$src2),
1895 "or{w}\t{$src2, $dst|$dst, $src2}",
1896 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1897 (implicit EFLAGS)]>, OpSize;
1898 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1899 (ins GR32:$src1, GR32:$src2),
1900 "or{l}\t{$src2, $dst|$dst, $src2}",
1901 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1902 (implicit EFLAGS)]>;
1905 // OR instructions with the destination register in REG and the source register
1906 // in R/M. Included for the disassembler.
1907 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1908 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1909 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1910 (ins GR16:$src1, GR16:$src2),
1911 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1912 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1913 (ins GR32:$src1, GR32:$src2),
1914 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1916 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1917 (ins GR8 :$src1, i8mem :$src2),
1918 "or{b}\t{$src2, $dst|$dst, $src2}",
1919 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1920 (implicit EFLAGS)]>;
1921 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1922 (ins GR16:$src1, i16mem:$src2),
1923 "or{w}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1925 (implicit EFLAGS)]>, OpSize;
1926 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1927 (ins GR32:$src1, i32mem:$src2),
1928 "or{l}\t{$src2, $dst|$dst, $src2}",
1929 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1930 (implicit EFLAGS)]>;
1932 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1933 (ins GR8 :$src1, i8imm:$src2),
1934 "or{b}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1936 (implicit EFLAGS)]>;
1937 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1938 (ins GR16:$src1, i16imm:$src2),
1939 "or{w}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1941 (implicit EFLAGS)]>, OpSize;
1942 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1943 (ins GR32:$src1, i32imm:$src2),
1944 "or{l}\t{$src2, $dst|$dst, $src2}",
1945 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1946 (implicit EFLAGS)]>;
1948 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1949 (ins GR16:$src1, i16i8imm:$src2),
1950 "or{w}\t{$src2, $dst|$dst, $src2}",
1951 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1952 (implicit EFLAGS)]>, OpSize;
1953 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1954 (ins GR32:$src1, i32i8imm:$src2),
1955 "or{l}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1957 (implicit EFLAGS)]>;
1958 let isTwoAddress = 0 in {
1959 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1960 "or{b}\t{$src, $dst|$dst, $src}",
1961 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1962 (implicit EFLAGS)]>;
1963 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1964 "or{w}\t{$src, $dst|$dst, $src}",
1965 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1966 (implicit EFLAGS)]>, OpSize;
1967 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1968 "or{l}\t{$src, $dst|$dst, $src}",
1969 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1970 (implicit EFLAGS)]>;
1971 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1972 "or{b}\t{$src, $dst|$dst, $src}",
1973 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1974 (implicit EFLAGS)]>;
1975 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1976 "or{w}\t{$src, $dst|$dst, $src}",
1977 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1978 (implicit EFLAGS)]>,
1980 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1981 "or{l}\t{$src, $dst|$dst, $src}",
1982 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1983 (implicit EFLAGS)]>;
1984 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1985 "or{w}\t{$src, $dst|$dst, $src}",
1986 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1987 (implicit EFLAGS)]>,
1989 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1990 "or{l}\t{$src, $dst|$dst, $src}",
1991 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1992 (implicit EFLAGS)]>;
1994 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1995 "or{b}\t{$src, %al|%al, $src}", []>;
1996 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1997 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1998 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1999 "or{l}\t{$src, %eax|%eax, $src}", []>;
2000 } // isTwoAddress = 0
2003 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2004 def XOR8rr : I<0x30, MRMDestReg,
2005 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2006 "xor{b}\t{$src2, $dst|$dst, $src2}",
2007 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
2008 (implicit EFLAGS)]>;
2009 def XOR16rr : I<0x31, MRMDestReg,
2010 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2011 "xor{w}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
2013 (implicit EFLAGS)]>, OpSize;
2014 def XOR32rr : I<0x31, MRMDestReg,
2015 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2016 "xor{l}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
2018 (implicit EFLAGS)]>;
2019 } // isCommutable = 1
2021 // XOR instructions with the destination register in REG and the source register
2022 // in R/M. Included for the disassembler.
2023 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2024 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2025 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2026 (ins GR16:$src1, GR16:$src2),
2027 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2028 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2029 (ins GR32:$src1, GR32:$src2),
2030 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2032 def XOR8rm : I<0x32, MRMSrcMem ,
2033 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2034 "xor{b}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
2036 (implicit EFLAGS)]>;
2037 def XOR16rm : I<0x33, MRMSrcMem ,
2038 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2039 "xor{w}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2041 (implicit EFLAGS)]>,
2043 def XOR32rm : I<0x33, MRMSrcMem ,
2044 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2045 "xor{l}\t{$src2, $dst|$dst, $src2}",
2046 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2047 (implicit EFLAGS)]>;
2049 def XOR8ri : Ii8<0x80, MRM6r,
2050 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2051 "xor{b}\t{$src2, $dst|$dst, $src2}",
2052 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2053 (implicit EFLAGS)]>;
2054 def XOR16ri : Ii16<0x81, MRM6r,
2055 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2056 "xor{w}\t{$src2, $dst|$dst, $src2}",
2057 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2058 (implicit EFLAGS)]>, OpSize;
2059 def XOR32ri : Ii32<0x81, MRM6r,
2060 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2061 "xor{l}\t{$src2, $dst|$dst, $src2}",
2062 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2063 (implicit EFLAGS)]>;
2064 def XOR16ri8 : Ii8<0x83, MRM6r,
2065 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2066 "xor{w}\t{$src2, $dst|$dst, $src2}",
2067 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2068 (implicit EFLAGS)]>,
2070 def XOR32ri8 : Ii8<0x83, MRM6r,
2071 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2072 "xor{l}\t{$src2, $dst|$dst, $src2}",
2073 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2074 (implicit EFLAGS)]>;
2076 let isTwoAddress = 0 in {
2077 def XOR8mr : I<0x30, MRMDestMem,
2078 (outs), (ins i8mem :$dst, GR8 :$src),
2079 "xor{b}\t{$src, $dst|$dst, $src}",
2080 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2081 (implicit EFLAGS)]>;
2082 def XOR16mr : I<0x31, MRMDestMem,
2083 (outs), (ins i16mem:$dst, GR16:$src),
2084 "xor{w}\t{$src, $dst|$dst, $src}",
2085 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2086 (implicit EFLAGS)]>,
2088 def XOR32mr : I<0x31, MRMDestMem,
2089 (outs), (ins i32mem:$dst, GR32:$src),
2090 "xor{l}\t{$src, $dst|$dst, $src}",
2091 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2092 (implicit EFLAGS)]>;
2093 def XOR8mi : Ii8<0x80, MRM6m,
2094 (outs), (ins i8mem :$dst, i8imm :$src),
2095 "xor{b}\t{$src, $dst|$dst, $src}",
2096 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2097 (implicit EFLAGS)]>;
2098 def XOR16mi : Ii16<0x81, MRM6m,
2099 (outs), (ins i16mem:$dst, i16imm:$src),
2100 "xor{w}\t{$src, $dst|$dst, $src}",
2101 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2102 (implicit EFLAGS)]>,
2104 def XOR32mi : Ii32<0x81, MRM6m,
2105 (outs), (ins i32mem:$dst, i32imm:$src),
2106 "xor{l}\t{$src, $dst|$dst, $src}",
2107 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2108 (implicit EFLAGS)]>;
2109 def XOR16mi8 : Ii8<0x83, MRM6m,
2110 (outs), (ins i16mem:$dst, i16i8imm :$src),
2111 "xor{w}\t{$src, $dst|$dst, $src}",
2112 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2113 (implicit EFLAGS)]>,
2115 def XOR32mi8 : Ii8<0x83, MRM6m,
2116 (outs), (ins i32mem:$dst, i32i8imm :$src),
2117 "xor{l}\t{$src, $dst|$dst, $src}",
2118 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2119 (implicit EFLAGS)]>;
2121 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2122 "xor{b}\t{$src, %al|%al, $src}", []>;
2123 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2124 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2125 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2126 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2127 } // isTwoAddress = 0
2128 } // Defs = [EFLAGS]
2130 // Shift instructions
2131 let Defs = [EFLAGS] in {
2132 let Uses = [CL] in {
2133 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2134 "shl{b}\t{%cl, $dst|$dst, CL}",
2135 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2136 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2137 "shl{w}\t{%cl, $dst|$dst, CL}",
2138 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2139 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2140 "shl{l}\t{%cl, $dst|$dst, CL}",
2141 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2144 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2145 "shl{b}\t{$src2, $dst|$dst, $src2}",
2146 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2147 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2148 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2149 "shl{w}\t{$src2, $dst|$dst, $src2}",
2150 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2151 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2152 "shl{l}\t{$src2, $dst|$dst, $src2}",
2153 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2155 // NOTE: We don't include patterns for shifts of a register by one, because
2156 // 'add reg,reg' is cheaper.
2158 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2159 "shl{b}\t$dst", []>;
2160 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2161 "shl{w}\t$dst", []>, OpSize;
2162 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2163 "shl{l}\t$dst", []>;
2165 } // isConvertibleToThreeAddress = 1
2167 let isTwoAddress = 0 in {
2168 let Uses = [CL] in {
2169 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2170 "shl{b}\t{%cl, $dst|$dst, CL}",
2171 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2172 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2173 "shl{w}\t{%cl, $dst|$dst, CL}",
2174 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2175 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2176 "shl{l}\t{%cl, $dst|$dst, CL}",
2177 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2179 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2180 "shl{b}\t{$src, $dst|$dst, $src}",
2181 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2182 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2183 "shl{w}\t{$src, $dst|$dst, $src}",
2184 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2186 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2187 "shl{l}\t{$src, $dst|$dst, $src}",
2188 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2191 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2193 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2194 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2196 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2198 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2200 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2203 let Uses = [CL] in {
2204 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2205 "shr{b}\t{%cl, $dst|$dst, CL}",
2206 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2207 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2208 "shr{w}\t{%cl, $dst|$dst, CL}",
2209 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2210 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2211 "shr{l}\t{%cl, $dst|$dst, CL}",
2212 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2215 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2216 "shr{b}\t{$src2, $dst|$dst, $src2}",
2217 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2218 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2219 "shr{w}\t{$src2, $dst|$dst, $src2}",
2220 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2221 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2222 "shr{l}\t{$src2, $dst|$dst, $src2}",
2223 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2226 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2228 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2229 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2231 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2232 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2234 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2236 let isTwoAddress = 0 in {
2237 let Uses = [CL] in {
2238 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2239 "shr{b}\t{%cl, $dst|$dst, CL}",
2240 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2241 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2242 "shr{w}\t{%cl, $dst|$dst, CL}",
2243 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2245 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2246 "shr{l}\t{%cl, $dst|$dst, CL}",
2247 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2249 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2250 "shr{b}\t{$src, $dst|$dst, $src}",
2251 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2252 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2253 "shr{w}\t{$src, $dst|$dst, $src}",
2254 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2256 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2257 "shr{l}\t{$src, $dst|$dst, $src}",
2258 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2261 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2263 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2264 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2266 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2267 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2269 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2272 let Uses = [CL] in {
2273 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2274 "sar{b}\t{%cl, $dst|$dst, CL}",
2275 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2276 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2277 "sar{w}\t{%cl, $dst|$dst, CL}",
2278 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2279 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2280 "sar{l}\t{%cl, $dst|$dst, CL}",
2281 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2284 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2285 "sar{b}\t{$src2, $dst|$dst, $src2}",
2286 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2287 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2288 "sar{w}\t{$src2, $dst|$dst, $src2}",
2289 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2291 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2292 "sar{l}\t{$src2, $dst|$dst, $src2}",
2293 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2296 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2298 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2299 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2301 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2302 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2304 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2306 let isTwoAddress = 0 in {
2307 let Uses = [CL] in {
2308 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2309 "sar{b}\t{%cl, $dst|$dst, CL}",
2310 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2311 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2312 "sar{w}\t{%cl, $dst|$dst, CL}",
2313 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2314 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2315 "sar{l}\t{%cl, $dst|$dst, CL}",
2316 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2318 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2319 "sar{b}\t{$src, $dst|$dst, $src}",
2320 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2321 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2322 "sar{w}\t{$src, $dst|$dst, $src}",
2323 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2325 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2326 "sar{l}\t{$src, $dst|$dst, $src}",
2327 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2330 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2332 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2333 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2335 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2337 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2339 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2342 // Rotate instructions
2344 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2345 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2346 let Uses = [CL] in {
2347 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2348 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2350 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2351 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2353 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2354 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2355 let Uses = [CL] in {
2356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2357 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2359 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2360 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2362 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2363 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2364 let Uses = [CL] in {
2365 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2366 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2368 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2369 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2371 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2372 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2373 let Uses = [CL] in {
2374 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2375 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2377 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2378 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2380 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2381 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2382 let Uses = [CL] in {
2383 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2384 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2386 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2387 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2389 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2390 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2391 let Uses = [CL] in {
2392 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2393 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2398 let isTwoAddress = 0 in {
2399 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2400 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2401 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2402 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2403 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2404 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2405 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2406 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2407 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2408 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2409 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2410 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2411 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2412 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2413 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2414 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2415 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2416 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2417 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2418 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2419 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2420 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2421 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2422 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2424 let Uses = [CL] in {
2425 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2426 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2427 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2428 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2429 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2430 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2431 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2432 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2433 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2434 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2435 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2436 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2440 // FIXME: provide shorter instructions when imm8 == 1
2441 let Uses = [CL] in {
2442 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2443 "rol{b}\t{%cl, $dst|$dst, CL}",
2444 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2445 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2446 "rol{w}\t{%cl, $dst|$dst, CL}",
2447 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2448 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2449 "rol{l}\t{%cl, $dst|$dst, CL}",
2450 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2453 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2454 "rol{b}\t{$src2, $dst|$dst, $src2}",
2455 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2456 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2457 "rol{w}\t{$src2, $dst|$dst, $src2}",
2458 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2460 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2461 "rol{l}\t{$src2, $dst|$dst, $src2}",
2462 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2465 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2467 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2468 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2470 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2471 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2473 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2475 let isTwoAddress = 0 in {
2476 let Uses = [CL] in {
2477 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2478 "rol{b}\t{%cl, $dst|$dst, CL}",
2479 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2480 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2481 "rol{w}\t{%cl, $dst|$dst, CL}",
2482 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2483 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2484 "rol{l}\t{%cl, $dst|$dst, CL}",
2485 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2487 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2488 "rol{b}\t{$src, $dst|$dst, $src}",
2489 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2490 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2491 "rol{w}\t{$src, $dst|$dst, $src}",
2492 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2494 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2495 "rol{l}\t{$src, $dst|$dst, $src}",
2496 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2499 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2501 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2502 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2504 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2506 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2508 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2511 let Uses = [CL] in {
2512 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2513 "ror{b}\t{%cl, $dst|$dst, CL}",
2514 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2515 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2516 "ror{w}\t{%cl, $dst|$dst, CL}",
2517 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2518 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2519 "ror{l}\t{%cl, $dst|$dst, CL}",
2520 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2523 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2524 "ror{b}\t{$src2, $dst|$dst, $src2}",
2525 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2526 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2527 "ror{w}\t{$src2, $dst|$dst, $src2}",
2528 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2530 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2531 "ror{l}\t{$src2, $dst|$dst, $src2}",
2532 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2535 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2537 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2538 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2540 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2541 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2543 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2545 let isTwoAddress = 0 in {
2546 let Uses = [CL] in {
2547 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2548 "ror{b}\t{%cl, $dst|$dst, CL}",
2549 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2550 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2551 "ror{w}\t{%cl, $dst|$dst, CL}",
2552 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2553 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2554 "ror{l}\t{%cl, $dst|$dst, CL}",
2555 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2557 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2558 "ror{b}\t{$src, $dst|$dst, $src}",
2559 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2560 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2561 "ror{w}\t{$src, $dst|$dst, $src}",
2562 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2564 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2565 "ror{l}\t{$src, $dst|$dst, $src}",
2566 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2569 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2571 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2572 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2574 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2576 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2578 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2583 // Double shift instructions (generalizations of rotate)
2584 let Uses = [CL] in {
2585 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2586 (ins GR32:$src1, GR32:$src2),
2587 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2588 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2589 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2590 (ins GR32:$src1, GR32:$src2),
2591 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2592 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2593 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2594 (ins GR16:$src1, GR16:$src2),
2595 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2596 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2598 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2599 (ins GR16:$src1, GR16:$src2),
2600 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2601 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2605 let isCommutable = 1 in { // These instructions commute to each other.
2606 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2608 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2609 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2610 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2613 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2615 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2616 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2617 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2620 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2622 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2623 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2624 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2627 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2629 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2630 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2636 let isTwoAddress = 0 in {
2637 let Uses = [CL] in {
2638 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2639 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2640 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2642 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2643 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2644 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2647 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2648 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2649 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2650 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2651 (i8 imm:$src3)), addr:$dst)]>,
2653 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2654 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2655 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2656 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2657 (i8 imm:$src3)), addr:$dst)]>,
2660 let Uses = [CL] in {
2661 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2662 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2663 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2664 addr:$dst)]>, TB, OpSize;
2665 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2666 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2667 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2668 addr:$dst)]>, TB, OpSize;
2670 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2671 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2672 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2673 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2674 (i8 imm:$src3)), addr:$dst)]>,
2676 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2677 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2678 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2679 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2680 (i8 imm:$src3)), addr:$dst)]>,
2683 } // Defs = [EFLAGS]
2687 let Defs = [EFLAGS] in {
2688 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2689 // Register-Register Addition
2690 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2691 (ins GR8 :$src1, GR8 :$src2),
2692 "add{b}\t{$src2, $dst|$dst, $src2}",
2693 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2694 (implicit EFLAGS)]>;
2696 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2697 // Register-Register Addition
2698 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2699 (ins GR16:$src1, GR16:$src2),
2700 "add{w}\t{$src2, $dst|$dst, $src2}",
2701 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2702 (implicit EFLAGS)]>, OpSize;
2703 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2704 (ins GR32:$src1, GR32:$src2),
2705 "add{l}\t{$src2, $dst|$dst, $src2}",
2706 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2707 (implicit EFLAGS)]>;
2708 } // end isConvertibleToThreeAddress
2709 } // end isCommutable
2711 // These are alternate spellings for use by the disassembler, we mark them as
2712 // code gen only to ensure they aren't matched by the assembler.
2713 let isCodeGenOnly = 1 in {
2714 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2715 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2716 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2717 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2718 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2719 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2722 // Register-Memory Addition
2723 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2724 (ins GR8 :$src1, i8mem :$src2),
2725 "add{b}\t{$src2, $dst|$dst, $src2}",
2726 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2727 (implicit EFLAGS)]>;
2728 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2729 (ins GR16:$src1, i16mem:$src2),
2730 "add{w}\t{$src2, $dst|$dst, $src2}",
2731 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2732 (implicit EFLAGS)]>, OpSize;
2733 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2734 (ins GR32:$src1, i32mem:$src2),
2735 "add{l}\t{$src2, $dst|$dst, $src2}",
2736 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2737 (implicit EFLAGS)]>;
2739 // Register-Integer Addition
2740 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2741 "add{b}\t{$src2, $dst|$dst, $src2}",
2742 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2743 (implicit EFLAGS)]>;
2745 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2746 // Register-Integer Addition
2747 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2748 (ins GR16:$src1, i16imm:$src2),
2749 "add{w}\t{$src2, $dst|$dst, $src2}",
2750 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2751 (implicit EFLAGS)]>, OpSize;
2752 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2753 (ins GR32:$src1, i32imm:$src2),
2754 "add{l}\t{$src2, $dst|$dst, $src2}",
2755 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2756 (implicit EFLAGS)]>;
2757 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2758 (ins GR16:$src1, i16i8imm:$src2),
2759 "add{w}\t{$src2, $dst|$dst, $src2}",
2760 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2761 (implicit EFLAGS)]>, OpSize;
2762 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2763 (ins GR32:$src1, i32i8imm:$src2),
2764 "add{l}\t{$src2, $dst|$dst, $src2}",
2765 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2766 (implicit EFLAGS)]>;
2769 let isTwoAddress = 0 in {
2770 // Memory-Register Addition
2771 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2772 "add{b}\t{$src2, $dst|$dst, $src2}",
2773 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2774 (implicit EFLAGS)]>;
2775 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2776 "add{w}\t{$src2, $dst|$dst, $src2}",
2777 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2778 (implicit EFLAGS)]>, OpSize;
2779 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2780 "add{l}\t{$src2, $dst|$dst, $src2}",
2781 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2782 (implicit EFLAGS)]>;
2783 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2784 "add{b}\t{$src2, $dst|$dst, $src2}",
2785 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2786 (implicit EFLAGS)]>;
2787 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2788 "add{w}\t{$src2, $dst|$dst, $src2}",
2789 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2790 (implicit EFLAGS)]>, OpSize;
2791 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2792 "add{l}\t{$src2, $dst|$dst, $src2}",
2793 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2794 (implicit EFLAGS)]>;
2795 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2796 "add{w}\t{$src2, $dst|$dst, $src2}",
2797 [(store (add (load addr:$dst), i16immSExt8:$src2),
2799 (implicit EFLAGS)]>, OpSize;
2800 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2801 "add{l}\t{$src2, $dst|$dst, $src2}",
2802 [(store (add (load addr:$dst), i32immSExt8:$src2),
2804 (implicit EFLAGS)]>;
2807 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2808 "add{b}\t{$src, %al|%al, $src}", []>;
2809 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2810 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2811 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2812 "add{l}\t{$src, %eax|%eax, $src}", []>;
2815 let Uses = [EFLAGS] in {
2816 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2817 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2818 "adc{b}\t{$src2, $dst|$dst, $src2}",
2819 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2820 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2821 (ins GR16:$src1, GR16:$src2),
2822 "adc{w}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2824 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2825 (ins GR32:$src1, GR32:$src2),
2826 "adc{l}\t{$src2, $dst|$dst, $src2}",
2827 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2830 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2831 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2832 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2833 (ins GR16:$src1, GR16:$src2),
2834 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2835 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2836 (ins GR32:$src1, GR32:$src2),
2837 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2839 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2840 (ins GR8:$src1, i8mem:$src2),
2841 "adc{b}\t{$src2, $dst|$dst, $src2}",
2842 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2843 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2844 (ins GR16:$src1, i16mem:$src2),
2845 "adc{w}\t{$src2, $dst|$dst, $src2}",
2846 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2848 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2849 (ins GR32:$src1, i32mem:$src2),
2850 "adc{l}\t{$src2, $dst|$dst, $src2}",
2851 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2852 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2853 "adc{b}\t{$src2, $dst|$dst, $src2}",
2854 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2855 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2856 (ins GR16:$src1, i16imm:$src2),
2857 "adc{w}\t{$src2, $dst|$dst, $src2}",
2858 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2859 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2860 (ins GR16:$src1, i16i8imm:$src2),
2861 "adc{w}\t{$src2, $dst|$dst, $src2}",
2862 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2864 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2865 (ins GR32:$src1, i32imm:$src2),
2866 "adc{l}\t{$src2, $dst|$dst, $src2}",
2867 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2868 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2869 (ins GR32:$src1, i32i8imm:$src2),
2870 "adc{l}\t{$src2, $dst|$dst, $src2}",
2871 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2873 let isTwoAddress = 0 in {
2874 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2875 "adc{b}\t{$src2, $dst|$dst, $src2}",
2876 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2877 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2878 "adc{w}\t{$src2, $dst|$dst, $src2}",
2879 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2881 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2882 "adc{l}\t{$src2, $dst|$dst, $src2}",
2883 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2884 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2885 "adc{b}\t{$src2, $dst|$dst, $src2}",
2886 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2887 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2888 "adc{w}\t{$src2, $dst|$dst, $src2}",
2889 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2891 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2892 "adc{w}\t{$src2, $dst|$dst, $src2}",
2893 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2895 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2896 "adc{l}\t{$src2, $dst|$dst, $src2}",
2897 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2898 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2899 "adc{l}\t{$src2, $dst|$dst, $src2}",
2900 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2902 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2903 "adc{b}\t{$src, %al|%al, $src}", []>;
2904 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2905 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2906 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2907 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2909 } // Uses = [EFLAGS]
2911 // Register-Register Subtraction
2912 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2913 "sub{b}\t{$src2, $dst|$dst, $src2}",
2914 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2915 (implicit EFLAGS)]>;
2916 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2917 "sub{w}\t{$src2, $dst|$dst, $src2}",
2918 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2919 (implicit EFLAGS)]>, OpSize;
2920 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2921 "sub{l}\t{$src2, $dst|$dst, $src2}",
2922 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2923 (implicit EFLAGS)]>;
2925 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2926 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2927 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2928 (ins GR16:$src1, GR16:$src2),
2929 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2930 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2931 (ins GR32:$src1, GR32:$src2),
2932 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2934 // Register-Memory Subtraction
2935 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2936 (ins GR8 :$src1, i8mem :$src2),
2937 "sub{b}\t{$src2, $dst|$dst, $src2}",
2938 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2939 (implicit EFLAGS)]>;
2940 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2941 (ins GR16:$src1, i16mem:$src2),
2942 "sub{w}\t{$src2, $dst|$dst, $src2}",
2943 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2944 (implicit EFLAGS)]>, OpSize;
2945 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2946 (ins GR32:$src1, i32mem:$src2),
2947 "sub{l}\t{$src2, $dst|$dst, $src2}",
2948 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2949 (implicit EFLAGS)]>;
2951 // Register-Integer Subtraction
2952 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2953 (ins GR8:$src1, i8imm:$src2),
2954 "sub{b}\t{$src2, $dst|$dst, $src2}",
2955 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2956 (implicit EFLAGS)]>;
2957 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2958 (ins GR16:$src1, i16imm:$src2),
2959 "sub{w}\t{$src2, $dst|$dst, $src2}",
2960 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2961 (implicit EFLAGS)]>, OpSize;
2962 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2963 (ins GR32:$src1, i32imm:$src2),
2964 "sub{l}\t{$src2, $dst|$dst, $src2}",
2965 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2966 (implicit EFLAGS)]>;
2967 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2968 (ins GR16:$src1, i16i8imm:$src2),
2969 "sub{w}\t{$src2, $dst|$dst, $src2}",
2970 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2971 (implicit EFLAGS)]>, OpSize;
2972 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2973 (ins GR32:$src1, i32i8imm:$src2),
2974 "sub{l}\t{$src2, $dst|$dst, $src2}",
2975 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2976 (implicit EFLAGS)]>;
2978 let isTwoAddress = 0 in {
2979 // Memory-Register Subtraction
2980 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2981 "sub{b}\t{$src2, $dst|$dst, $src2}",
2982 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2983 (implicit EFLAGS)]>;
2984 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2985 "sub{w}\t{$src2, $dst|$dst, $src2}",
2986 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2987 (implicit EFLAGS)]>, OpSize;
2988 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2989 "sub{l}\t{$src2, $dst|$dst, $src2}",
2990 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2991 (implicit EFLAGS)]>;
2993 // Memory-Integer Subtraction
2994 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2995 "sub{b}\t{$src2, $dst|$dst, $src2}",
2996 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2997 (implicit EFLAGS)]>;
2998 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2999 "sub{w}\t{$src2, $dst|$dst, $src2}",
3000 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3001 (implicit EFLAGS)]>, OpSize;
3002 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3003 "sub{l}\t{$src2, $dst|$dst, $src2}",
3004 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3005 (implicit EFLAGS)]>;
3006 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3007 "sub{w}\t{$src2, $dst|$dst, $src2}",
3008 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3010 (implicit EFLAGS)]>, OpSize;
3011 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3012 "sub{l}\t{$src2, $dst|$dst, $src2}",
3013 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3015 (implicit EFLAGS)]>;
3017 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3018 "sub{b}\t{$src, %al|%al, $src}", []>;
3019 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3020 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3021 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3022 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3025 let Uses = [EFLAGS] in {
3026 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3027 (ins GR8:$src1, GR8:$src2),
3028 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3029 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3030 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3031 (ins GR16:$src1, GR16:$src2),
3032 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3034 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3035 (ins GR32:$src1, GR32:$src2),
3036 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3037 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3039 let isTwoAddress = 0 in {
3040 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3041 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3042 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3043 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3044 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3045 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3047 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3048 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3049 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3050 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3051 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3052 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3053 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3054 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3055 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3057 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3058 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3059 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3061 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3062 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3063 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3064 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3065 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3066 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3068 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3069 "sbb{b}\t{$src, %al|%al, $src}", []>;
3070 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3071 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3072 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3073 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3076 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3077 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3078 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3079 (ins GR16:$src1, GR16:$src2),
3080 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3081 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3082 (ins GR32:$src1, GR32:$src2),
3083 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3085 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3086 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3087 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3088 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3089 (ins GR16:$src1, i16mem:$src2),
3090 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3091 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3093 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3094 (ins GR32:$src1, i32mem:$src2),
3095 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3096 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3097 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3098 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3099 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3100 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3101 (ins GR16:$src1, i16imm:$src2),
3102 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3104 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3105 (ins GR16:$src1, i16i8imm:$src2),
3106 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3109 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3110 (ins GR32:$src1, i32imm:$src2),
3111 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3112 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3113 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3114 (ins GR32:$src1, i32i8imm:$src2),
3115 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3116 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3117 } // Uses = [EFLAGS]
3118 } // Defs = [EFLAGS]
3120 let Defs = [EFLAGS] in {
3121 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3122 // Register-Register Signed Integer Multiply
3123 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3124 "imul{w}\t{$src2, $dst|$dst, $src2}",
3125 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3126 (implicit EFLAGS)]>, TB, OpSize;
3127 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3128 "imul{l}\t{$src2, $dst|$dst, $src2}",
3129 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3130 (implicit EFLAGS)]>, TB;
3133 // Register-Memory Signed Integer Multiply
3134 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3135 (ins GR16:$src1, i16mem:$src2),
3136 "imul{w}\t{$src2, $dst|$dst, $src2}",
3137 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3138 (implicit EFLAGS)]>, TB, OpSize;
3139 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3140 (ins GR32:$src1, i32mem:$src2),
3141 "imul{l}\t{$src2, $dst|$dst, $src2}",
3142 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3143 (implicit EFLAGS)]>, TB;
3144 } // Defs = [EFLAGS]
3145 } // end Two Address instructions
3147 // Suprisingly enough, these are not two address instructions!
3148 let Defs = [EFLAGS] in {
3149 // Register-Integer Signed Integer Multiply
3150 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3151 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3152 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3153 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3154 (implicit EFLAGS)]>, OpSize;
3155 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3156 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3157 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3158 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3159 (implicit EFLAGS)]>;
3160 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3161 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3162 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3163 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3164 (implicit EFLAGS)]>, OpSize;
3165 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3166 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3167 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3168 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3169 (implicit EFLAGS)]>;
3171 // Memory-Integer Signed Integer Multiply
3172 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3173 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3174 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3175 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3176 (implicit EFLAGS)]>, OpSize;
3177 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3178 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3179 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3180 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3181 (implicit EFLAGS)]>;
3182 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3183 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3184 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3185 [(set GR16:$dst, (mul (load addr:$src1),
3186 i16immSExt8:$src2)),
3187 (implicit EFLAGS)]>, OpSize;
3188 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3189 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3190 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3191 [(set GR32:$dst, (mul (load addr:$src1),
3192 i32immSExt8:$src2)),
3193 (implicit EFLAGS)]>;
3194 } // Defs = [EFLAGS]
3196 //===----------------------------------------------------------------------===//
3197 // Test instructions are just like AND, except they don't generate a result.
3199 let Defs = [EFLAGS] in {
3200 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3201 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3202 "test{b}\t{$src2, $src1|$src1, $src2}",
3203 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3204 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3205 "test{w}\t{$src2, $src1|$src1, $src2}",
3206 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3209 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3210 "test{l}\t{$src2, $src1|$src1, $src2}",
3211 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3215 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3216 "test{b}\t{$src, %al|%al, $src}", []>;
3217 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3218 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3219 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3220 "test{l}\t{$src, %eax|%eax, $src}", []>;
3222 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3223 "test{b}\t{$src2, $src1|$src1, $src2}",
3224 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3226 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3227 "test{w}\t{$src2, $src1|$src1, $src2}",
3228 [(set EFLAGS, (X86cmp (and GR16:$src1,
3229 (loadi16 addr:$src2)), 0))]>, OpSize;
3230 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3231 "test{l}\t{$src2, $src1|$src1, $src2}",
3232 [(set EFLAGS, (X86cmp (and GR32:$src1,
3233 (loadi32 addr:$src2)), 0))]>;
3235 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3236 (outs), (ins GR8:$src1, i8imm:$src2),
3237 "test{b}\t{$src2, $src1|$src1, $src2}",
3238 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3239 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3240 (outs), (ins GR16:$src1, i16imm:$src2),
3241 "test{w}\t{$src2, $src1|$src1, $src2}",
3242 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3244 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3245 (outs), (ins GR32:$src1, i32imm:$src2),
3246 "test{l}\t{$src2, $src1|$src1, $src2}",
3247 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3249 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3250 (outs), (ins i8mem:$src1, i8imm:$src2),
3251 "test{b}\t{$src2, $src1|$src1, $src2}",
3252 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3254 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3255 (outs), (ins i16mem:$src1, i16imm:$src2),
3256 "test{w}\t{$src2, $src1|$src1, $src2}",
3257 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3259 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3260 (outs), (ins i32mem:$src1, i32imm:$src2),
3261 "test{l}\t{$src2, $src1|$src1, $src2}",
3262 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3264 } // Defs = [EFLAGS]
3267 // Condition code ops, incl. set if equal/not equal/...
3268 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3269 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3270 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3271 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3273 let Uses = [EFLAGS] in {
3274 // Use sbb to materialize carry bit.
3275 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3276 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3277 // However, Pat<> can't replicate the destination reg into the inputs of the
3279 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3281 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3282 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3283 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3284 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3286 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3287 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3290 def SETEr : I<0x94, MRM0r,
3291 (outs GR8 :$dst), (ins),
3293 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3295 def SETEm : I<0x94, MRM0m,
3296 (outs), (ins i8mem:$dst),
3298 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3301 def SETNEr : I<0x95, MRM0r,
3302 (outs GR8 :$dst), (ins),
3304 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3306 def SETNEm : I<0x95, MRM0m,
3307 (outs), (ins i8mem:$dst),
3309 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3312 def SETLr : I<0x9C, MRM0r,
3313 (outs GR8 :$dst), (ins),
3315 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3316 TB; // GR8 = < signed
3317 def SETLm : I<0x9C, MRM0m,
3318 (outs), (ins i8mem:$dst),
3320 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3321 TB; // [mem8] = < signed
3323 def SETGEr : I<0x9D, MRM0r,
3324 (outs GR8 :$dst), (ins),
3326 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3327 TB; // GR8 = >= signed
3328 def SETGEm : I<0x9D, MRM0m,
3329 (outs), (ins i8mem:$dst),
3331 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3332 TB; // [mem8] = >= signed
3334 def SETLEr : I<0x9E, MRM0r,
3335 (outs GR8 :$dst), (ins),
3337 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3338 TB; // GR8 = <= signed
3339 def SETLEm : I<0x9E, MRM0m,
3340 (outs), (ins i8mem:$dst),
3342 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3343 TB; // [mem8] = <= signed
3345 def SETGr : I<0x9F, MRM0r,
3346 (outs GR8 :$dst), (ins),
3348 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3349 TB; // GR8 = > signed
3350 def SETGm : I<0x9F, MRM0m,
3351 (outs), (ins i8mem:$dst),
3353 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3354 TB; // [mem8] = > signed
3356 def SETBr : I<0x92, MRM0r,
3357 (outs GR8 :$dst), (ins),
3359 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3360 TB; // GR8 = < unsign
3361 def SETBm : I<0x92, MRM0m,
3362 (outs), (ins i8mem:$dst),
3364 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3365 TB; // [mem8] = < unsign
3367 def SETAEr : I<0x93, MRM0r,
3368 (outs GR8 :$dst), (ins),
3370 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3371 TB; // GR8 = >= unsign
3372 def SETAEm : I<0x93, MRM0m,
3373 (outs), (ins i8mem:$dst),
3375 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3376 TB; // [mem8] = >= unsign
3378 def SETBEr : I<0x96, MRM0r,
3379 (outs GR8 :$dst), (ins),
3381 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3382 TB; // GR8 = <= unsign
3383 def SETBEm : I<0x96, MRM0m,
3384 (outs), (ins i8mem:$dst),
3386 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3387 TB; // [mem8] = <= unsign
3389 def SETAr : I<0x97, MRM0r,
3390 (outs GR8 :$dst), (ins),
3392 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3393 TB; // GR8 = > signed
3394 def SETAm : I<0x97, MRM0m,
3395 (outs), (ins i8mem:$dst),
3397 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3398 TB; // [mem8] = > signed
3400 def SETSr : I<0x98, MRM0r,
3401 (outs GR8 :$dst), (ins),
3403 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3404 TB; // GR8 = <sign bit>
3405 def SETSm : I<0x98, MRM0m,
3406 (outs), (ins i8mem:$dst),
3408 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3409 TB; // [mem8] = <sign bit>
3410 def SETNSr : I<0x99, MRM0r,
3411 (outs GR8 :$dst), (ins),
3413 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3414 TB; // GR8 = !<sign bit>
3415 def SETNSm : I<0x99, MRM0m,
3416 (outs), (ins i8mem:$dst),
3418 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3419 TB; // [mem8] = !<sign bit>
3421 def SETPr : I<0x9A, MRM0r,
3422 (outs GR8 :$dst), (ins),
3424 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3426 def SETPm : I<0x9A, MRM0m,
3427 (outs), (ins i8mem:$dst),
3429 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3430 TB; // [mem8] = parity
3431 def SETNPr : I<0x9B, MRM0r,
3432 (outs GR8 :$dst), (ins),
3434 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3435 TB; // GR8 = not parity
3436 def SETNPm : I<0x9B, MRM0m,
3437 (outs), (ins i8mem:$dst),
3439 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3440 TB; // [mem8] = not parity
3442 def SETOr : I<0x90, MRM0r,
3443 (outs GR8 :$dst), (ins),
3445 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3446 TB; // GR8 = overflow
3447 def SETOm : I<0x90, MRM0m,
3448 (outs), (ins i8mem:$dst),
3450 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3451 TB; // [mem8] = overflow
3452 def SETNOr : I<0x91, MRM0r,
3453 (outs GR8 :$dst), (ins),
3455 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3456 TB; // GR8 = not overflow
3457 def SETNOm : I<0x91, MRM0m,
3458 (outs), (ins i8mem:$dst),
3460 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3461 TB; // [mem8] = not overflow
3462 } // Uses = [EFLAGS]
3465 // Integer comparisons
3466 let Defs = [EFLAGS] in {
3467 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3468 "cmp{b}\t{$src, %al|%al, $src}", []>;
3469 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3470 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3471 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3472 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3474 def CMP8rr : I<0x38, MRMDestReg,
3475 (outs), (ins GR8 :$src1, GR8 :$src2),
3476 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3477 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3478 def CMP16rr : I<0x39, MRMDestReg,
3479 (outs), (ins GR16:$src1, GR16:$src2),
3480 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3481 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3482 def CMP32rr : I<0x39, MRMDestReg,
3483 (outs), (ins GR32:$src1, GR32:$src2),
3484 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3485 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3486 def CMP8mr : I<0x38, MRMDestMem,
3487 (outs), (ins i8mem :$src1, GR8 :$src2),
3488 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3489 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3490 def CMP16mr : I<0x39, MRMDestMem,
3491 (outs), (ins i16mem:$src1, GR16:$src2),
3492 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3493 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3495 def CMP32mr : I<0x39, MRMDestMem,
3496 (outs), (ins i32mem:$src1, GR32:$src2),
3497 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3498 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3499 def CMP8rm : I<0x3A, MRMSrcMem,
3500 (outs), (ins GR8 :$src1, i8mem :$src2),
3501 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3502 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3503 def CMP16rm : I<0x3B, MRMSrcMem,
3504 (outs), (ins GR16:$src1, i16mem:$src2),
3505 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3506 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3508 def CMP32rm : I<0x3B, MRMSrcMem,
3509 (outs), (ins GR32:$src1, i32mem:$src2),
3510 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3511 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3513 // These are alternate spellings for use by the disassembler, we mark them as
3514 // code gen only to ensure they aren't matched by the assembler.
3515 let isCodeGenOnly = 1 in {
3516 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3517 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3518 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3519 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3520 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3521 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3524 def CMP8ri : Ii8<0x80, MRM7r,
3525 (outs), (ins GR8:$src1, i8imm:$src2),
3526 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3527 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3528 def CMP16ri : Ii16<0x81, MRM7r,
3529 (outs), (ins GR16:$src1, i16imm:$src2),
3530 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3531 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3532 def CMP32ri : Ii32<0x81, MRM7r,
3533 (outs), (ins GR32:$src1, i32imm:$src2),
3534 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3535 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3536 def CMP8mi : Ii8 <0x80, MRM7m,
3537 (outs), (ins i8mem :$src1, i8imm :$src2),
3538 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3539 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3540 def CMP16mi : Ii16<0x81, MRM7m,
3541 (outs), (ins i16mem:$src1, i16imm:$src2),
3542 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3543 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3545 def CMP32mi : Ii32<0x81, MRM7m,
3546 (outs), (ins i32mem:$src1, i32imm:$src2),
3547 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3548 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3549 def CMP16ri8 : Ii8<0x83, MRM7r,
3550 (outs), (ins GR16:$src1, i16i8imm:$src2),
3551 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3552 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3554 def CMP16mi8 : Ii8<0x83, MRM7m,
3555 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3556 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3557 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3558 i16immSExt8:$src2))]>, OpSize;
3559 def CMP32mi8 : Ii8<0x83, MRM7m,
3560 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3561 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3562 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3563 i32immSExt8:$src2))]>;
3564 def CMP32ri8 : Ii8<0x83, MRM7r,
3565 (outs), (ins GR32:$src1, i32i8imm:$src2),
3566 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3567 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3568 } // Defs = [EFLAGS]
3571 // TODO: BTC, BTR, and BTS
3572 let Defs = [EFLAGS] in {
3573 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3574 "bt{w}\t{$src2, $src1|$src1, $src2}",
3575 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3576 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3577 "bt{l}\t{$src2, $src1|$src1, $src2}",
3578 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3580 // Unlike with the register+register form, the memory+register form of the
3581 // bt instruction does not ignore the high bits of the index. From ISel's
3582 // perspective, this is pretty bizarre. Make these instructions disassembly
3585 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3586 "bt{w}\t{$src2, $src1|$src1, $src2}",
3587 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3588 // (implicit EFLAGS)]
3590 >, OpSize, TB, Requires<[FastBTMem]>;
3591 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3592 "bt{l}\t{$src2, $src1|$src1, $src2}",
3593 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3594 // (implicit EFLAGS)]
3596 >, TB, Requires<[FastBTMem]>;
3598 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3599 "bt{w}\t{$src2, $src1|$src1, $src2}",
3600 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3602 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3603 "bt{l}\t{$src2, $src1|$src1, $src2}",
3604 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3605 // Note that these instructions don't need FastBTMem because that
3606 // only applies when the other operand is in a register. When it's
3607 // an immediate, bt is still fast.
3608 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3609 "bt{w}\t{$src2, $src1|$src1, $src2}",
3610 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3612 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3613 "bt{l}\t{$src2, $src1|$src1, $src2}",
3614 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3617 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3618 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3619 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3620 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3621 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3622 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3623 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3624 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3625 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3626 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3627 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3628 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3629 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3630 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3631 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3632 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3634 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3635 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3636 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3637 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3638 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3639 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3640 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3641 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3642 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3643 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3644 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3645 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3646 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3647 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3648 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3649 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3651 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3652 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3653 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3654 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3655 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3656 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3657 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3658 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3659 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3660 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3661 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3662 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3663 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3664 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3665 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3666 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3667 } // Defs = [EFLAGS]
3669 // Sign/Zero extenders
3670 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3671 // of the register here. This has a smaller encoding and avoids a
3672 // partial-register update. Actual movsbw included for the disassembler.
3673 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3674 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3675 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3676 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3677 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3678 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3679 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3680 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3681 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3682 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3683 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3684 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3685 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3686 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3687 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3688 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3689 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3690 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3691 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3692 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3694 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3695 // of the register here. This has a smaller encoding and avoids a
3696 // partial-register update. Actual movzbw included for the disassembler.
3697 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3698 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3699 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3700 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3701 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3702 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3703 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3704 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3705 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3706 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3707 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3708 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3709 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3710 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3711 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3712 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3713 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3714 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3715 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3716 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3718 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3719 // except that they use GR32_NOREX for the output operand register class
3720 // instead of GR32. This allows them to operate on h registers on x86-64.
3721 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3722 (outs GR32_NOREX:$dst), (ins GR8:$src),
3723 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3726 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3727 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3728 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3731 let neverHasSideEffects = 1 in {
3732 let Defs = [AX], Uses = [AL] in
3733 def CBW : I<0x98, RawFrm, (outs), (ins),
3734 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3735 let Defs = [EAX], Uses = [AX] in
3736 def CWDE : I<0x98, RawFrm, (outs), (ins),
3737 "{cwtl|cwde}", []>; // EAX = signext(AX)
3739 let Defs = [AX,DX], Uses = [AX] in
3740 def CWD : I<0x99, RawFrm, (outs), (ins),
3741 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3742 let Defs = [EAX,EDX], Uses = [EAX] in
3743 def CDQ : I<0x99, RawFrm, (outs), (ins),
3744 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3747 //===----------------------------------------------------------------------===//
3748 // Alias Instructions
3749 //===----------------------------------------------------------------------===//
3751 // Alias instructions that map movr0 to xor.
3752 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3753 // FIXME: Set encoding to pseudo.
3754 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3755 isCodeGenOnly = 1 in {
3756 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3757 [(set GR8:$dst, 0)]>;
3759 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3760 // encoding and avoids a partial-register update sometimes, but doing so
3761 // at isel time interferes with rematerialization in the current register
3762 // allocator. For now, this is rewritten when the instruction is lowered
3764 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3766 [(set GR16:$dst, 0)]>, OpSize;
3768 // FIXME: Set encoding to pseudo.
3769 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3770 [(set GR32:$dst, 0)]>;
3773 //===----------------------------------------------------------------------===//
3774 // Thread Local Storage Instructions
3777 // All calls clobber the non-callee saved registers. ESP is marked as
3778 // a use to prevent stack-pointer assignments that appear immediately
3779 // before calls from potentially appearing dead.
3780 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3781 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3782 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3783 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3785 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3786 "leal\t$sym, %eax; "
3787 "call\t___tls_get_addr@PLT",
3788 [(X86tlsaddr tls32addr:$sym)]>,
3789 Requires<[In32BitMode]>;
3791 let AddedComplexity = 5, isCodeGenOnly = 1 in
3792 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3793 "movl\t%gs:$src, $dst",
3794 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3796 let AddedComplexity = 5, isCodeGenOnly = 1 in
3797 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3798 "movl\t%fs:$src, $dst",
3799 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3801 //===----------------------------------------------------------------------===//
3802 // EH Pseudo Instructions
3804 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3805 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3806 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3807 "ret\t#eh_return, addr: $addr",
3808 [(X86ehret GR32:$addr)]>;
3812 //===----------------------------------------------------------------------===//
3816 // Atomic swap. These are just normal xchg instructions. But since a memory
3817 // operand is referenced, the atomicity is ensured.
3818 let Constraints = "$val = $dst" in {
3819 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3820 (ins GR32:$val, i32mem:$ptr),
3821 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3822 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3823 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3824 (ins GR16:$val, i16mem:$ptr),
3825 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3826 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3828 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3829 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3830 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3832 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3833 "xchg{l}\t{$val, $src|$src, $val}", []>;
3834 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3835 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3836 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3837 "xchg{b}\t{$val, $src|$src, $val}", []>;
3840 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3841 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3842 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3843 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3845 // Atomic compare and swap.
3846 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3847 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3849 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3850 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3852 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3853 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3856 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3859 let Defs = [AX, EFLAGS], Uses = [AX] in {
3860 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3862 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3863 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3865 let Defs = [AL, EFLAGS], Uses = [AL] in {
3866 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3868 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3869 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3872 // Atomic exchange and add
3873 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3874 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3876 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3877 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3879 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3881 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3882 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3884 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3886 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3887 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3891 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3892 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3893 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3894 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3895 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3896 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3898 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3899 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3900 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3901 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3902 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3903 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3905 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3906 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3907 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3908 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3909 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3910 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3912 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3913 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3914 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3915 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3916 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3917 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3919 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3920 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3921 "cmpxchg8b\t$dst", []>, TB;
3923 // Optimized codegen when the non-memory output is not used.
3924 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3925 let Defs = [EFLAGS] in {
3926 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3928 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3929 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3931 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3932 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3934 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3935 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3937 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3938 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3940 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3941 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3943 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3944 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3946 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3947 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3949 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3951 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3953 "inc{b}\t$dst", []>, LOCK;
3954 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3956 "inc{w}\t$dst", []>, OpSize, LOCK;
3957 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3959 "inc{l}\t$dst", []>, LOCK;
3961 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3963 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3964 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3966 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3967 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3969 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3970 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3972 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3973 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3975 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3976 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3978 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3979 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3981 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3982 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3984 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3986 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3988 "dec{b}\t$dst", []>, LOCK;
3989 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3991 "dec{w}\t$dst", []>, OpSize, LOCK;
3992 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3994 "dec{l}\t$dst", []>, LOCK;
3997 // Atomic exchange, and, or, xor
3998 let Constraints = "$val = $dst", Defs = [EFLAGS],
3999 usesCustomInserter = 1 in {
4000 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4001 "#ATOMAND32 PSEUDO!",
4002 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4003 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4004 "#ATOMOR32 PSEUDO!",
4005 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4006 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4007 "#ATOMXOR32 PSEUDO!",
4008 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4009 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4010 "#ATOMNAND32 PSEUDO!",
4011 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4012 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4013 "#ATOMMIN32 PSEUDO!",
4014 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4015 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4016 "#ATOMMAX32 PSEUDO!",
4017 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4018 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4019 "#ATOMUMIN32 PSEUDO!",
4020 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4021 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4022 "#ATOMUMAX32 PSEUDO!",
4023 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4025 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4026 "#ATOMAND16 PSEUDO!",
4027 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4028 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4029 "#ATOMOR16 PSEUDO!",
4030 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4031 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4032 "#ATOMXOR16 PSEUDO!",
4033 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4034 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4035 "#ATOMNAND16 PSEUDO!",
4036 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4037 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4038 "#ATOMMIN16 PSEUDO!",
4039 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4040 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4041 "#ATOMMAX16 PSEUDO!",
4042 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4043 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4044 "#ATOMUMIN16 PSEUDO!",
4045 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4046 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4047 "#ATOMUMAX16 PSEUDO!",
4048 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4050 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4051 "#ATOMAND8 PSEUDO!",
4052 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4053 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4055 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4056 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4057 "#ATOMXOR8 PSEUDO!",
4058 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4059 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4060 "#ATOMNAND8 PSEUDO!",
4061 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4064 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4065 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4066 Uses = [EAX, EBX, ECX, EDX],
4067 mayLoad = 1, mayStore = 1,
4068 usesCustomInserter = 1 in {
4069 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4070 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4071 "#ATOMAND6432 PSEUDO!", []>;
4072 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4073 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4074 "#ATOMOR6432 PSEUDO!", []>;
4075 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4076 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4077 "#ATOMXOR6432 PSEUDO!", []>;
4078 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4079 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4080 "#ATOMNAND6432 PSEUDO!", []>;
4081 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4082 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4083 "#ATOMADD6432 PSEUDO!", []>;
4084 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4085 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4086 "#ATOMSUB6432 PSEUDO!", []>;
4087 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4088 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4089 "#ATOMSWAP6432 PSEUDO!", []>;
4092 // Segmentation support instructions.
4094 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4095 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4096 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4097 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4099 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4100 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4101 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4102 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4103 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4105 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4106 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4107 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4108 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4109 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4110 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4111 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4112 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4114 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4116 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4117 "str{w}\t{$dst}", []>, TB;
4118 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4119 "str{w}\t{$dst}", []>, TB;
4120 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4121 "ltr{w}\t{$src}", []>, TB;
4122 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4123 "ltr{w}\t{$src}", []>, TB;
4125 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4126 "push{w}\t%fs", []>, OpSize, TB;
4127 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4128 "push{l}\t%fs", []>, TB;
4129 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4130 "push{w}\t%gs", []>, OpSize, TB;
4131 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4132 "push{l}\t%gs", []>, TB;
4134 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4135 "pop{w}\t%fs", []>, OpSize, TB;
4136 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4137 "pop{l}\t%fs", []>, TB;
4138 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4139 "pop{w}\t%gs", []>, OpSize, TB;
4140 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4141 "pop{l}\t%gs", []>, TB;
4143 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4144 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4145 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4146 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4147 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4148 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4149 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4150 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4151 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4152 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4153 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4154 "les{l}\t{$src, $dst|$dst, $src}", []>;
4155 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4156 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4157 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4158 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4159 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4160 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4161 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4162 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4164 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4165 "verr\t$seg", []>, TB;
4166 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4167 "verr\t$seg", []>, TB;
4168 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4169 "verw\t$seg", []>, TB;
4170 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4171 "verw\t$seg", []>, TB;
4173 // Descriptor-table support instructions
4175 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4176 "sgdt\t$dst", []>, TB;
4177 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4178 "sidt\t$dst", []>, TB;
4179 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4180 "sldt{w}\t$dst", []>, TB;
4181 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4182 "sldt{w}\t$dst", []>, TB;
4183 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4184 "lgdt\t$src", []>, TB;
4185 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4186 "lidt\t$src", []>, TB;
4187 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4188 "lldt{w}\t$src", []>, TB;
4189 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4190 "lldt{w}\t$src", []>, TB;
4192 // Lock instruction prefix
4193 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4195 // Repeat string operation instruction prefixes
4196 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4197 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4198 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4199 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4200 // Repeat while not equal (used with CMPS and SCAS)
4201 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4204 // Segment override instruction prefixes
4205 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4206 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4207 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4208 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4209 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4210 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4212 // String manipulation instructions
4214 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4215 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4216 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4218 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4219 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4220 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4222 // CPU flow control instructions
4224 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4225 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4227 // FPU control instructions
4229 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4231 // Flag instructions
4233 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4234 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4235 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4236 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4237 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4238 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4239 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4241 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4243 // Table lookup instructions
4245 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4247 // Specialized register support
4249 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4250 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4251 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4253 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4254 "smsw{w}\t$dst", []>, OpSize, TB;
4255 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4256 "smsw{l}\t$dst", []>, TB;
4257 // For memory operands, there is only a 16-bit form
4258 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4259 "smsw{w}\t$dst", []>, TB;
4261 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4262 "lmsw{w}\t$src", []>, TB;
4263 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4264 "lmsw{w}\t$src", []>, TB;
4266 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4268 // Cache instructions
4270 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4271 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4276 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4278 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4280 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4281 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4282 "vmclear\t$vmcs", []>, OpSize, TB;
4284 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4286 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4287 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4288 "vmptrld\t$vmcs", []>, TB;
4289 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4290 "vmptrst\t$vmcs", []>, TB;
4291 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4292 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4293 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4294 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4295 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4296 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4297 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4298 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4299 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4300 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4301 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4302 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4303 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4304 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4305 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4306 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4308 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4309 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4310 "vmxon\t{$vmxon}", []>, XS;
4312 //===----------------------------------------------------------------------===//
4313 // Non-Instruction Patterns
4314 //===----------------------------------------------------------------------===//
4316 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4317 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4318 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4319 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4320 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4321 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4322 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4324 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4325 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4326 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4327 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4328 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4329 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4330 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4331 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4332 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4333 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4335 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4336 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4337 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4338 (MOV32mi addr:$dst, texternalsym:$src)>;
4339 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4340 (MOV32mi addr:$dst, tblockaddress:$src)>;
4344 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4345 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4346 Requires<[In32BitMode]>;
4348 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4349 (TCRETURNmi addr:$dst, imm:$off)>,
4350 Requires<[In32BitMode]>;
4352 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4353 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4354 Requires<[In32BitMode]>;
4356 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4357 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4358 Requires<[In32BitMode]>;
4360 // Normal calls, with various flavors of addresses.
4361 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4362 (CALLpcrel32 tglobaladdr:$dst)>;
4363 def : Pat<(X86call (i32 texternalsym:$dst)),
4364 (CALLpcrel32 texternalsym:$dst)>;
4365 def : Pat<(X86call (i32 imm:$dst)),
4366 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4368 // X86 specific add which produces a flag.
4369 def : Pat<(addc GR32:$src1, GR32:$src2),
4370 (ADD32rr GR32:$src1, GR32:$src2)>;
4371 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4372 (ADD32rm GR32:$src1, addr:$src2)>;
4373 def : Pat<(addc GR32:$src1, imm:$src2),
4374 (ADD32ri GR32:$src1, imm:$src2)>;
4375 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4376 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4378 def : Pat<(subc GR32:$src1, GR32:$src2),
4379 (SUB32rr GR32:$src1, GR32:$src2)>;
4380 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4381 (SUB32rm GR32:$src1, addr:$src2)>;
4382 def : Pat<(subc GR32:$src1, imm:$src2),
4383 (SUB32ri GR32:$src1, imm:$src2)>;
4384 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4385 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4389 // TEST R,R is smaller than CMP R,0
4390 def : Pat<(X86cmp GR8:$src1, 0),
4391 (TEST8rr GR8:$src1, GR8:$src1)>;
4392 def : Pat<(X86cmp GR16:$src1, 0),
4393 (TEST16rr GR16:$src1, GR16:$src1)>;
4394 def : Pat<(X86cmp GR32:$src1, 0),
4395 (TEST32rr GR32:$src1, GR32:$src1)>;
4397 // Conditional moves with folded loads with operands swapped and conditions
4399 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4400 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4402 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4404 (CMOVB16rm GR16:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4406 (CMOVB32rm GR32:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4408 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4410 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4412 (CMOVE16rm GR16:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4414 (CMOVE32rm GR32:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4416 (CMOVA16rm GR16:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4418 (CMOVA32rm GR32:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4420 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4422 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4424 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4426 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4428 (CMOVL16rm GR16:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4430 (CMOVL32rm GR32:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4432 (CMOVG16rm GR16:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4434 (CMOVG32rm GR32:$src2, addr:$src1)>;
4435 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4436 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4437 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4438 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4439 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4440 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4441 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4442 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4443 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4444 (CMOVP16rm GR16:$src2, addr:$src1)>;
4445 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4446 (CMOVP32rm GR32:$src2, addr:$src1)>;
4447 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4448 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4449 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4450 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4451 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4452 (CMOVS16rm GR16:$src2, addr:$src1)>;
4453 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4454 (CMOVS32rm GR32:$src2, addr:$src1)>;
4455 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4456 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4457 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4458 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4459 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4460 (CMOVO16rm GR16:$src2, addr:$src1)>;
4461 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4462 (CMOVO32rm GR32:$src2, addr:$src1)>;
4464 // zextload bool -> zextload byte
4465 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4466 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4467 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4469 // extload bool -> extload byte
4470 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4471 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4472 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4473 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4474 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4475 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4477 // anyext. Define these to do an explicit zero-extend to
4478 // avoid partial-register updates.
4479 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4480 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4481 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4483 //===----------------------------------------------------------------------===//
4485 //===----------------------------------------------------------------------===//
4487 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4488 // +128 doesn't, so in this special case use a sub instead of an add.
4489 def : Pat<(add GR16:$src1, 128),
4490 (SUB16ri8 GR16:$src1, -128)>;
4491 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4492 (SUB16mi8 addr:$dst, -128)>;
4493 def : Pat<(add GR32:$src1, 128),
4494 (SUB32ri8 GR32:$src1, -128)>;
4495 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4496 (SUB32mi8 addr:$dst, -128)>;
4498 // r & (2^16-1) ==> movz
4499 def : Pat<(and GR32:$src1, 0xffff),
4500 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4501 // r & (2^8-1) ==> movz
4502 def : Pat<(and GR32:$src1, 0xff),
4503 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4506 Requires<[In32BitMode]>;
4507 // r & (2^8-1) ==> movz
4508 def : Pat<(and GR16:$src1, 0xff),
4509 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4512 Requires<[In32BitMode]>;
4514 // sext_inreg patterns
4515 def : Pat<(sext_inreg GR32:$src, i16),
4516 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4517 def : Pat<(sext_inreg GR32:$src, i8),
4518 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4521 Requires<[In32BitMode]>;
4522 def : Pat<(sext_inreg GR16:$src, i8),
4523 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4526 Requires<[In32BitMode]>;
4529 def : Pat<(i16 (trunc GR32:$src)),
4530 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4531 def : Pat<(i8 (trunc GR32:$src)),
4532 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4534 Requires<[In32BitMode]>;
4535 def : Pat<(i8 (trunc GR16:$src)),
4536 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4538 Requires<[In32BitMode]>;
4540 // h-register tricks
4541 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4542 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4543 x86_subreg_8bit_hi)>,
4544 Requires<[In32BitMode]>;
4545 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4546 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4547 x86_subreg_8bit_hi)>,
4548 Requires<[In32BitMode]>;
4549 def : Pat<(srl GR16:$src, (i8 8)),
4552 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4553 x86_subreg_8bit_hi)),
4555 Requires<[In32BitMode]>;
4556 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4557 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4559 x86_subreg_8bit_hi))>,
4560 Requires<[In32BitMode]>;
4561 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4562 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4564 x86_subreg_8bit_hi))>,
4565 Requires<[In32BitMode]>;
4566 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4567 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4569 x86_subreg_8bit_hi))>,
4570 Requires<[In32BitMode]>;
4572 // (shl x, 1) ==> (add x, x)
4573 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4574 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4575 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4577 // (shl x (and y, 31)) ==> (shl x, y)
4578 def : Pat<(shl GR8:$src1, (and CL, 31)),
4579 (SHL8rCL GR8:$src1)>;
4580 def : Pat<(shl GR16:$src1, (and CL, 31)),
4581 (SHL16rCL GR16:$src1)>;
4582 def : Pat<(shl GR32:$src1, (and CL, 31)),
4583 (SHL32rCL GR32:$src1)>;
4584 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4585 (SHL8mCL addr:$dst)>;
4586 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4587 (SHL16mCL addr:$dst)>;
4588 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4589 (SHL32mCL addr:$dst)>;
4591 def : Pat<(srl GR8:$src1, (and CL, 31)),
4592 (SHR8rCL GR8:$src1)>;
4593 def : Pat<(srl GR16:$src1, (and CL, 31)),
4594 (SHR16rCL GR16:$src1)>;
4595 def : Pat<(srl GR32:$src1, (and CL, 31)),
4596 (SHR32rCL GR32:$src1)>;
4597 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4598 (SHR8mCL addr:$dst)>;
4599 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4600 (SHR16mCL addr:$dst)>;
4601 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4602 (SHR32mCL addr:$dst)>;
4604 def : Pat<(sra GR8:$src1, (and CL, 31)),
4605 (SAR8rCL GR8:$src1)>;
4606 def : Pat<(sra GR16:$src1, (and CL, 31)),
4607 (SAR16rCL GR16:$src1)>;
4608 def : Pat<(sra GR32:$src1, (and CL, 31)),
4609 (SAR32rCL GR32:$src1)>;
4610 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4611 (SAR8mCL addr:$dst)>;
4612 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4613 (SAR16mCL addr:$dst)>;
4614 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4615 (SAR32mCL addr:$dst)>;
4617 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4618 def : Pat<(or (srl GR32:$src1, CL:$amt),
4619 (shl GR32:$src2, (sub 32, CL:$amt))),
4620 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4622 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4623 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4624 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4626 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4627 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4628 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4630 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4631 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4633 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4635 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4636 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4638 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4639 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4640 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4642 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4643 def : Pat<(or (shl GR32:$src1, CL:$amt),
4644 (srl GR32:$src2, (sub 32, CL:$amt))),
4645 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4647 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4648 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4649 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4651 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4652 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4653 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4655 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4656 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4658 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4660 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4661 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4663 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4664 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4665 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4667 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4668 def : Pat<(or (srl GR16:$src1, CL:$amt),
4669 (shl GR16:$src2, (sub 16, CL:$amt))),
4670 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4672 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4673 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4674 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4676 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4677 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4678 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4680 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4681 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4683 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4685 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4686 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4688 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4689 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4690 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4692 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4693 def : Pat<(or (shl GR16:$src1, CL:$amt),
4694 (srl GR16:$src2, (sub 16, CL:$amt))),
4695 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4697 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4698 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4699 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4701 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4702 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4703 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4705 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4706 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4708 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4710 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4711 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4713 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4714 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4715 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4717 // (anyext (setcc_carry)) -> (setcc_carry)
4718 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4720 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4723 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4724 let AddedComplexity = 5 in { // Try this before the selecting to OR
4725 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4727 (ADD16ri GR16:$src1, imm:$src2)>;
4728 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4730 (ADD32ri GR32:$src1, imm:$src2)>;
4731 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4733 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4734 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4736 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4737 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4739 (ADD16rr GR16:$src1, GR16:$src2)>;
4740 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4742 (ADD32rr GR32:$src1, GR32:$src2)>;
4743 } // AddedComplexity
4745 //===----------------------------------------------------------------------===//
4746 // EFLAGS-defining Patterns
4747 //===----------------------------------------------------------------------===//
4749 // Register-Register Addition with EFLAGS result
4750 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4752 (ADD8rr GR8:$src1, GR8:$src2)>;
4753 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4755 (ADD16rr GR16:$src1, GR16:$src2)>;
4756 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4758 (ADD32rr GR32:$src1, GR32:$src2)>;
4760 // Register-Memory Addition with EFLAGS result
4761 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4763 (ADD8rm GR8:$src1, addr:$src2)>;
4764 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4766 (ADD16rm GR16:$src1, addr:$src2)>;
4767 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4769 (ADD32rm GR32:$src1, addr:$src2)>;
4771 // Register-Integer Addition with EFLAGS result
4772 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4774 (ADD8ri GR8:$src1, imm:$src2)>;
4775 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4777 (ADD16ri GR16:$src1, imm:$src2)>;
4778 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4780 (ADD32ri GR32:$src1, imm:$src2)>;
4781 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4783 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4784 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4786 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4789 // Memory-Register Addition with EFLAGS result
4790 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4793 (ADD8mr addr:$dst, GR8:$src2)>;
4794 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4797 (ADD16mr addr:$dst, GR16:$src2)>;
4798 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4801 (ADD32mr addr:$dst, GR32:$src2)>;
4803 // Memory-Integer Addition with EFLAGS result
4804 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4807 (ADD8mi addr:$dst, imm:$src2)>;
4808 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4811 (ADD16mi addr:$dst, imm:$src2)>;
4812 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4815 (ADD32mi addr:$dst, imm:$src2)>;
4816 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4819 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4820 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4823 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4826 // Register-Register Subtraction with EFLAGS result
4827 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4829 (SUB8rr GR8:$src1, GR8:$src2)>;
4830 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4832 (SUB16rr GR16:$src1, GR16:$src2)>;
4833 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4835 (SUB32rr GR32:$src1, GR32:$src2)>;
4837 // Register-Memory Subtraction with EFLAGS result
4838 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4840 (SUB8rm GR8:$src1, addr:$src2)>;
4841 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4843 (SUB16rm GR16:$src1, addr:$src2)>;
4844 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4846 (SUB32rm GR32:$src1, addr:$src2)>;
4848 // Register-Integer Subtraction with EFLAGS result
4849 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4851 (SUB8ri GR8:$src1, imm:$src2)>;
4852 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4854 (SUB16ri GR16:$src1, imm:$src2)>;
4855 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4857 (SUB32ri GR32:$src1, imm:$src2)>;
4858 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4860 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4861 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4863 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4866 // Memory-Register Subtraction with EFLAGS result
4867 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4870 (SUB8mr addr:$dst, GR8:$src2)>;
4871 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4874 (SUB16mr addr:$dst, GR16:$src2)>;
4875 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4878 (SUB32mr addr:$dst, GR32:$src2)>;
4880 // Memory-Integer Subtraction with EFLAGS result
4881 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4884 (SUB8mi addr:$dst, imm:$src2)>;
4885 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4888 (SUB16mi addr:$dst, imm:$src2)>;
4889 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4892 (SUB32mi addr:$dst, imm:$src2)>;
4893 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4896 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4897 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4900 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4903 // Register-Register Signed Integer Multiply with EFLAGS result
4904 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4906 (IMUL16rr GR16:$src1, GR16:$src2)>;
4907 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4909 (IMUL32rr GR32:$src1, GR32:$src2)>;
4911 // Register-Memory Signed Integer Multiply with EFLAGS result
4912 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4914 (IMUL16rm GR16:$src1, addr:$src2)>;
4915 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4917 (IMUL32rm GR32:$src1, addr:$src2)>;
4919 // Register-Integer Signed Integer Multiply with EFLAGS result
4920 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4922 (IMUL16rri GR16:$src1, imm:$src2)>;
4923 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4925 (IMUL32rri GR32:$src1, imm:$src2)>;
4926 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4928 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4929 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4931 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4933 // Memory-Integer Signed Integer Multiply with EFLAGS result
4934 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4936 (IMUL16rmi addr:$src1, imm:$src2)>;
4937 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4939 (IMUL32rmi addr:$src1, imm:$src2)>;
4940 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4942 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4943 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4945 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4947 // Optimize multiply by 2 with EFLAGS result.
4948 let AddedComplexity = 2 in {
4949 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4951 (ADD16rr GR16:$src1, GR16:$src1)>;
4953 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4955 (ADD32rr GR32:$src1, GR32:$src1)>;
4958 // INC and DEC with EFLAGS result. Note that these do not set CF.
4959 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4962 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4966 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4968 /*def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4970 (DEC8m addr:$dst)>;*/
4972 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4973 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4975 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4977 (INC16m addr:$dst)>, Requires<[In32BitMode]>;*/
4978 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4979 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4981 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4983 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;*/
4985 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4986 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4987 /*def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4989 (INC32m addr:$dst)>, Requires<[In32BitMode]>;*/
4990 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4991 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4992 /*def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4994 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;*/
4996 // Register-Register Or with EFLAGS result
4997 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4999 (OR8rr GR8:$src1, GR8:$src2)>;
5000 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
5002 (OR16rr GR16:$src1, GR16:$src2)>;
5003 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
5005 (OR32rr GR32:$src1, GR32:$src2)>;
5007 // Register-Memory Or with EFLAGS result
5008 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
5010 (OR8rm GR8:$src1, addr:$src2)>;
5011 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
5013 (OR16rm GR16:$src1, addr:$src2)>;
5014 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
5016 (OR32rm GR32:$src1, addr:$src2)>;
5018 // Register-Integer Or with EFLAGS result
5019 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
5021 (OR8ri GR8:$src1, imm:$src2)>;
5022 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
5024 (OR16ri GR16:$src1, imm:$src2)>;
5025 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
5027 (OR32ri GR32:$src1, imm:$src2)>;
5028 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
5030 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5031 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
5033 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5035 // Memory-Register Or with EFLAGS result
5036 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
5039 (OR8mr addr:$dst, GR8:$src2)>;
5040 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
5043 (OR16mr addr:$dst, GR16:$src2)>;
5044 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
5047 (OR32mr addr:$dst, GR32:$src2)>;
5049 // Memory-Integer Or with EFLAGS result
5050 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
5053 (OR8mi addr:$dst, imm:$src2)>;
5054 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
5057 (OR16mi addr:$dst, imm:$src2)>;
5058 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
5061 (OR32mi addr:$dst, imm:$src2)>;
5062 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5065 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
5066 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5069 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5072 // Register-Register XOr with EFLAGS result
5073 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5075 (XOR8rr GR8:$src1, GR8:$src2)>;
5076 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5078 (XOR16rr GR16:$src1, GR16:$src2)>;
5079 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5081 (XOR32rr GR32:$src1, GR32:$src2)>;
5083 // Register-Memory XOr with EFLAGS result
5084 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5086 (XOR8rm GR8:$src1, addr:$src2)>;
5087 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5089 (XOR16rm GR16:$src1, addr:$src2)>;
5090 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5092 (XOR32rm GR32:$src1, addr:$src2)>;
5094 // Register-Integer XOr with EFLAGS result
5095 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5097 (XOR8ri GR8:$src1, imm:$src2)>;
5098 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5100 (XOR16ri GR16:$src1, imm:$src2)>;
5101 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5103 (XOR32ri GR32:$src1, imm:$src2)>;
5104 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5106 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5107 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5109 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5112 // Memory-Register XOr with EFLAGS result
5113 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5116 (XOR8mr addr:$dst, GR8:$src2)>;
5117 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5120 (XOR16mr addr:$dst, GR16:$src2)>;
5121 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5124 (XOR32mr addr:$dst, GR32:$src2)>;
5126 // Memory-Integer XOr with EFLAGS result
5127 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5130 (XOR8mi addr:$dst, imm:$src2)>;
5131 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5134 (XOR16mi addr:$dst, imm:$src2)>;
5135 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5138 (XOR32mi addr:$dst, imm:$src2)>;
5139 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5142 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5143 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5146 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5149 // Register-Register And with EFLAGS result
5150 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5152 (AND8rr GR8:$src1, GR8:$src2)>;
5153 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5155 (AND16rr GR16:$src1, GR16:$src2)>;
5156 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5158 (AND32rr GR32:$src1, GR32:$src2)>;
5160 // Register-Memory And with EFLAGS result
5161 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5163 (AND8rm GR8:$src1, addr:$src2)>;
5164 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5166 (AND16rm GR16:$src1, addr:$src2)>;
5167 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5169 (AND32rm GR32:$src1, addr:$src2)>;
5171 // Register-Integer And with EFLAGS result
5172 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5174 (AND8ri GR8:$src1, imm:$src2)>;
5175 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5177 (AND16ri GR16:$src1, imm:$src2)>;
5178 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5180 (AND32ri GR32:$src1, imm:$src2)>;
5181 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5183 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5184 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5186 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5189 // Memory-Register And with EFLAGS result
5190 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5193 (AND8mr addr:$dst, GR8:$src2)>;
5194 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5197 (AND16mr addr:$dst, GR16:$src2)>;
5198 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5201 (AND32mr addr:$dst, GR32:$src2)>;
5203 // Memory-Integer And with EFLAGS result
5204 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5207 (AND8mi addr:$dst, imm:$src2)>;
5208 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5211 (AND16mi addr:$dst, imm:$src2)>;
5212 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5215 (AND32mi addr:$dst, imm:$src2)>;
5216 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5219 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5220 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5223 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5226 // -disable-16bit support.
5227 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
5228 (MOV16mi addr:$dst, imm:$src)>;
5229 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5230 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5231 def : Pat<(i32 (sextloadi16 addr:$dst)),
5232 (MOVSX32rm16 addr:$dst)>;
5233 def : Pat<(i32 (zextloadi16 addr:$dst)),
5234 (MOVZX32rm16 addr:$dst)>;
5235 def : Pat<(i32 (extloadi16 addr:$dst)),
5236 (MOVZX32rm16 addr:$dst)>;
5238 //===----------------------------------------------------------------------===//
5239 // Floating Point Stack Support
5240 //===----------------------------------------------------------------------===//
5242 include "X86InstrFPStack.td"
5244 //===----------------------------------------------------------------------===//
5246 //===----------------------------------------------------------------------===//
5248 include "X86Instr64bit.td"
5250 //===----------------------------------------------------------------------===//
5251 // SIMD support (SSE, MMX and AVX)
5252 //===----------------------------------------------------------------------===//
5254 include "X86InstrFragmentsSIMD.td"
5256 //===----------------------------------------------------------------------===//
5257 // XMM Floating point support (requires SSE / SSE2)
5258 //===----------------------------------------------------------------------===//
5260 include "X86InstrSSE.td"
5262 //===----------------------------------------------------------------------===//
5263 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5264 //===----------------------------------------------------------------------===//
5266 include "X86InstrMMX.td"