1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
19 class X86MemOperand<ValueType Ty> : Operand<Ty> {
20 let PrintMethod = "printMemoryOperand";
21 let NumMIOperands = 4;
22 let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
24 def SSECC : Operand<i8> {
25 let PrintMethod = "printSSECC";
28 def i8mem : X86MemOperand<i8>;
29 def i16mem : X86MemOperand<i16>;
30 def i32mem : X86MemOperand<i32>;
31 def i64mem : X86MemOperand<i64>;
32 def f32mem : X86MemOperand<f32>;
33 def f64mem : X86MemOperand<f64>;
34 def f80mem : X86MemOperand<f80>;
36 // A couple of more descriptive operand definitions.
37 // 16-bits but only 8 bits are significant.
38 def i16i8imm : Operand<i16>;
39 // 32-bits but only 8 bits are significant.
40 def i32i8imm : Operand<i32>;
42 // PCRelative calls need special operand formatting.
43 let PrintMethod = "printCallOperand" in
44 def calltarget : Operand<i32>;
46 // Format specifies the encoding used by the instruction. This is part of the
47 // ad-hoc solution used to emit machine instruction encodings by our machine
49 class Format<bits<5> val> {
53 def Pseudo : Format<0>; def RawFrm : Format<1>;
54 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
55 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
56 def MRMSrcMem : Format<6>;
57 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
58 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
59 def MRM6r : Format<22>; def MRM7r : Format<23>;
60 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
61 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
62 def MRM6m : Format<30>; def MRM7m : Format<31>;
64 // ImmType - This specifies the immediate type used by an instruction. This is
65 // part of the ad-hoc solution used to emit machine instruction encodings by our
66 // machine code emitter.
67 class ImmType<bits<2> val> {
70 def NoImm : ImmType<0>;
71 def Imm8 : ImmType<1>;
72 def Imm16 : ImmType<2>;
73 def Imm32 : ImmType<3>;
75 // FPFormat - This specifies what form this FP instruction has. This is used by
76 // the Floating-Point stackifier pass.
77 class FPFormat<bits<3> val> {
80 def NotFP : FPFormat<0>;
81 def ZeroArgFP : FPFormat<1>;
82 def OneArgFP : FPFormat<2>;
83 def OneArgFPRW : FPFormat<3>;
84 def TwoArgFP : FPFormat<4>;
85 def CompareFP : FPFormat<5>;
86 def CondMovFP : FPFormat<6>;
87 def SpecialFP : FPFormat<7>;
90 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
92 let Namespace = "X86";
94 bits<8> Opcode = opcod;
96 bits<5> FormBits = Form.Value;
98 bits<2> ImmTypeBits = ImmT.Value;
100 dag OperandList = ops;
101 string AsmString = AsmStr;
104 // Attributes specific to X86 instructions...
106 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
108 bits<4> Prefix = 0; // Which prefix byte does this inst have?
109 FPFormat FPForm; // What flavor of FP instruction is this?
110 bits<3> FPFormBits = 0;
113 class Imp<list<Register> uses, list<Register> defs> {
114 list<Register> Uses = uses;
115 list<Register> Defs = defs;
119 // Prefix byte classes which are used to indicate to the ad-hoc machine code
120 // emitter that various prefix bytes are required.
121 class OpSize { bit hasOpSizePrefix = 1; }
122 class TB { bits<4> Prefix = 1; }
123 class REP { bits<4> Prefix = 2; }
124 class D8 { bits<4> Prefix = 3; }
125 class D9 { bits<4> Prefix = 4; }
126 class DA { bits<4> Prefix = 5; }
127 class DB { bits<4> Prefix = 6; }
128 class DC { bits<4> Prefix = 7; }
129 class DD { bits<4> Prefix = 8; }
130 class DE { bits<4> Prefix = 9; }
131 class DF { bits<4> Prefix = 10; }
132 class XD { bits<4> Prefix = 11; }
133 class XS { bits<4> Prefix = 12; }
136 //===----------------------------------------------------------------------===//
137 // Pattern fragments...
139 def immSExt8 : PatLeaf<(imm), [{
140 // immSExt8 predicate - True if the immediate fits in a 8-bit sign extended
142 return (int)N->getValue() == (signed char)N->getValue();
145 //===----------------------------------------------------------------------===//
146 // Instruction templates...
148 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
149 : X86Inst<o, f, NoImm, ops, asm> {
150 let Pattern = pattern;
152 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
153 : X86Inst<o, f, Imm8 , ops, asm> {
154 let Pattern = pattern;
156 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
157 : X86Inst<o, f, Imm16, ops, asm> {
158 let Pattern = pattern;
160 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
161 : X86Inst<o, f, Imm32, ops, asm> {
162 let Pattern = pattern;
165 //===----------------------------------------------------------------------===//
166 // Instruction list...
169 def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node.
170 def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop
172 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>;
173 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
174 "#ADJCALLSTACKUP", []>;
175 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
176 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
177 let isTerminator = 1 in
178 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
179 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
181 //===----------------------------------------------------------------------===//
182 // Control Flow Instructions...
185 // Return instructions.
186 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
187 def RET : I<0xC3, RawFrm, (ops), "ret", []>;
188 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
189 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
191 // All branches are RawFrm, Void, Branch, and Terminators
192 let isBranch = 1, isTerminator = 1 in
193 class IBr<bits<8> opcode, dag ops, string asm> :
194 I<opcode, RawFrm, ops, asm, []>;
197 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
198 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
199 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
200 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
201 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
202 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
203 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
204 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
205 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
206 def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB;
207 def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB;
208 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
209 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
210 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
211 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
214 //===----------------------------------------------------------------------===//
215 // Call Instructions...
218 // All calls clobber the non-callee saved registers...
219 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
220 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
221 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>;
222 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>;
223 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>;
227 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
228 def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">;
229 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
230 def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>;
231 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
232 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
233 "jmp {*}$dst # TAIL CALL", []>;
235 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
236 // way, except that it is marked as being a terminator. This causes the epilog
237 // inserter to insert reloads of callee saved registers BEFORE this. We need
238 // this until we have a more accurate way of tracking where the stack pointer is
239 // within a function.
240 let isTerminator = 1, isTwoAddress = 1 in
241 def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
242 "add{l} {$src2, $dst|$dst, $src2}", []>;
244 //===----------------------------------------------------------------------===//
245 // Miscellaneous Instructions...
247 def LEAVE : I<0xC9, RawFrm,
248 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
249 def POP32r : I<0x58, AddRegFrm,
250 (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
252 let isTwoAddress = 1 in // R32 = bswap R32
253 def BSWAP32r : I<0xC8, AddRegFrm,
254 (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB;
256 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
257 (ops R8:$src1, R8:$src2),
258 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
259 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
260 (ops R16:$src1, R16:$src2),
261 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
262 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
263 (ops R32:$src1, R32:$src2),
264 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
266 def XCHG8mr : I<0x86, MRMDestMem,
267 (ops i8mem:$src1, R8:$src2),
268 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
269 def XCHG16mr : I<0x87, MRMDestMem,
270 (ops i16mem:$src1, R16:$src2),
271 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
272 def XCHG32mr : I<0x87, MRMDestMem,
273 (ops i32mem:$src1, R32:$src2),
274 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
275 def XCHG8rm : I<0x86, MRMSrcMem,
276 (ops R8:$src1, i8mem:$src2),
277 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
278 def XCHG16rm : I<0x87, MRMSrcMem,
279 (ops R16:$src1, i16mem:$src2),
280 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
281 def XCHG32rm : I<0x87, MRMSrcMem,
282 (ops R32:$src1, i32mem:$src2),
283 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
285 def LEA16r : I<0x8D, MRMSrcMem,
286 (ops R16:$dst, i32mem:$src),
287 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
288 def LEA32r : I<0x8D, MRMSrcMem,
289 (ops R32:$dst, i32mem:$src),
290 "lea{l} {$src|$dst}, {$dst|$src}", []>;
293 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>,
294 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
295 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>,
296 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
297 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>,
298 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
300 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>,
301 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
302 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>,
303 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
304 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
305 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
308 //===----------------------------------------------------------------------===//
309 // Input/Output Instructions...
311 def IN8rr : I<0xEC, RawFrm, (ops),
312 "in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>;
313 def IN16rr : I<0xED, RawFrm, (ops),
314 "in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize;
315 def IN32rr : I<0xED, RawFrm, (ops),
316 "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
318 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
319 "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>;
320 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
321 "in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize;
322 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
323 "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
325 def OUT8rr : I<0xEE, RawFrm, (ops),
326 "out{b} {%al, %dx|%DX, %AL}", []>, Imp<[DX, AL], []>;
327 def OUT16rr : I<0xEF, RawFrm, (ops),
328 "out{w} {%ax, %dx|%DX, %AX}", []>, Imp<[DX, AX], []>, OpSize;
329 def OUT32rr : I<0xEF, RawFrm, (ops),
330 "out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>;
332 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
333 "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>;
334 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
335 "out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize;
336 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
337 "out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>;
339 //===----------------------------------------------------------------------===//
340 // Move Instructions...
342 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
343 "mov{b} {$src, $dst|$dst, $src}", []>;
344 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
345 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
346 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
347 "mov{l} {$src, $dst|$dst, $src}", []>;
348 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
349 "mov{b} {$src, $dst|$dst, $src}",
350 [(set R8:$dst, imm:$src)]>;
351 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
352 "mov{w} {$src, $dst|$dst, $src}",
353 [(set R16:$dst, imm:$src)]>, OpSize;
354 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
355 "mov{l} {$src, $dst|$dst, $src}",
356 [(set R32:$dst, imm:$src)]>;
357 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
358 "mov{b} {$src, $dst|$dst, $src}", []>;
359 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
360 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
361 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
362 "mov{l} {$src, $dst|$dst, $src}", []>;
364 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
365 "mov{b} {$src, $dst|$dst, $src}", []>;
366 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
367 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
368 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
369 "mov{l} {$src, $dst|$dst, $src}", []>;
371 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
372 "mov{b} {$src, $dst|$dst, $src}", []>;
373 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
374 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
375 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
376 "mov{l} {$src, $dst|$dst, $src}", []>;
378 //===----------------------------------------------------------------------===//
379 // Fixed-Register Multiplication and Division Instructions...
382 // Extra precision multiplication
383 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>,
384 Imp<[AL],[AX]>; // AL,AH = AL*R8
385 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>,
386 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
387 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>,
388 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
389 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
390 "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
391 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
392 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
393 OpSize; // AX,DX = AX*[mem16]
394 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
395 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
397 def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>,
398 Imp<[AL],[AX]>; // AL,AH = AL*R8
399 def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>,
400 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
401 def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>,
402 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
403 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
404 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
405 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
406 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
407 OpSize; // AX,DX = AX*[mem16]
408 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
410 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
412 // unsigned division/remainder
413 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
414 "div{b} $src", []>, Imp<[AX],[AX]>;
415 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
416 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
417 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
418 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
419 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
420 "div{b} $src", []>, Imp<[AX],[AX]>;
421 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
422 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
423 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
424 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
426 // Signed division/remainder.
427 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
428 "idiv{b} $src", []>, Imp<[AX],[AX]>;
429 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
430 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
431 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
432 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
433 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
434 "idiv{b} $src", []>, Imp<[AX],[AX]>;
435 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
436 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
437 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
438 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
440 // Sign-extenders for division.
441 def CBW : I<0x98, RawFrm, (ops),
442 "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL)
443 def CWD : I<0x99, RawFrm, (ops),
444 "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX)
445 def CDQ : I<0x99, RawFrm, (ops),
446 "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
449 //===----------------------------------------------------------------------===//
450 // Two address Instructions...
452 let isTwoAddress = 1 in {
455 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
456 (ops R16:$dst, R16:$src1, R16:$src2),
457 "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
458 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
459 (ops R16:$dst, R16:$src1, i16mem:$src2),
460 "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
461 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
462 (ops R32:$dst, R32:$src1, R32:$src2),
463 "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
464 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
465 (ops R32:$dst, R32:$src1, i32mem:$src2),
466 "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
468 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
469 (ops R16:$dst, R16:$src1, R16:$src2),
470 "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
471 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
472 (ops R16:$dst, R16:$src1, i16mem:$src2),
473 "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
474 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
475 (ops R32:$dst, R32:$src1, R32:$src2),
476 "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
477 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
478 (ops R32:$dst, R32:$src1, i32mem:$src2),
479 "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
481 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
482 (ops R16:$dst, R16:$src1, R16:$src2),
483 "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
484 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
485 (ops R16:$dst, R16:$src1, i16mem:$src2),
486 "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
487 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
488 (ops R32:$dst, R32:$src1, R32:$src2),
489 "cmove {$src2, $dst|$dst, $src2}", []>, TB;
490 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
491 (ops R32:$dst, R32:$src1, i32mem:$src2),
492 "cmove {$src2, $dst|$dst, $src2}", []>, TB;
494 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
495 (ops R16:$dst, R16:$src1, R16:$src2),
496 "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
497 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
498 (ops R16:$dst, R16:$src1, i16mem:$src2),
499 "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
500 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
501 (ops R32:$dst, R32:$src1, R32:$src2),
502 "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
503 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
504 (ops R32:$dst, R32:$src1, i32mem:$src2),
505 "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
507 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
508 (ops R16:$dst, R16:$src1, R16:$src2),
509 "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
510 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
511 (ops R16:$dst, R16:$src1, i16mem:$src2),
512 "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
513 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
514 (ops R32:$dst, R32:$src1, R32:$src2),
515 "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
516 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
517 (ops R32:$dst, R32:$src1, i32mem:$src2),
518 "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
520 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
521 (ops R16:$dst, R16:$src1, R16:$src2),
522 "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
523 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
524 (ops R16:$dst, R16:$src1, i16mem:$src2),
525 "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
526 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
527 (ops R32:$dst, R32:$src1, R32:$src2),
528 "cmova {$src2, $dst|$dst, $src2}", []>, TB;
529 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
530 (ops R32:$dst, R32:$src1, i32mem:$src2),
531 "cmova {$src2, $dst|$dst, $src2}", []>, TB;
533 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
534 (ops R16:$dst, R16:$src1, R16:$src2),
535 "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
536 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
537 (ops R16:$dst, R16:$src1, i16mem:$src2),
538 "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
539 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
540 (ops R32:$dst, R32:$src1, R32:$src2),
541 "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
542 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
543 (ops R32:$dst, R32:$src1, i32mem:$src2),
544 "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
546 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
547 (ops R16:$dst, R16:$src1, R16:$src2),
548 "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
549 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
550 (ops R16:$dst, R16:$src1, i16mem:$src2),
551 "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
552 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
553 (ops R32:$dst, R32:$src1, R32:$src2),
554 "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
555 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
556 (ops R32:$dst, R32:$src1, i32mem:$src2),
557 "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
559 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
560 (ops R16:$dst, R16:$src1, R16:$src2),
561 "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
562 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
563 (ops R16:$dst, R16:$src1, i16mem:$src2),
564 "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
565 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
566 (ops R32:$dst, R32:$src1, R32:$src2),
567 "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
568 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
569 (ops R32:$dst, R32:$src1, i32mem:$src2),
570 "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
573 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
574 (ops R16:$dst, R16:$src1, R16:$src2),
575 "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
576 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
577 (ops R16:$dst, R16:$src1, i16mem:$src2),
578 "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
579 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
580 (ops R32:$dst, R32:$src1, R32:$src2),
581 "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
582 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
583 (ops R32:$dst, R32:$src1, i32mem:$src2),
584 "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
587 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
588 (ops R16:$dst, R16:$src1, R16:$src2),
589 "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
590 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
591 (ops R16:$dst, R16:$src1, i16mem:$src2),
592 "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
593 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
594 (ops R32:$dst, R32:$src1, R32:$src2),
595 "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
596 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
597 (ops R32:$dst, R32:$src1, i32mem:$src2),
598 "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
600 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
601 (ops R16:$dst, R16:$src1, R16:$src2),
602 "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
603 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
604 (ops R16:$dst, R16:$src1, i16mem:$src2),
605 "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
606 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
607 (ops R32:$dst, R32:$src1, R32:$src2),
608 "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
609 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
610 (ops R32:$dst, R32:$src1, i32mem:$src2),
611 "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
613 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
614 (ops R16:$dst, R16:$src1, R16:$src2),
615 "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
616 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
617 (ops R16:$dst, R16:$src1, i16mem:$src2),
618 "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
619 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
620 (ops R32:$dst, R32:$src1, R32:$src2),
621 "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
622 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
623 (ops R32:$dst, R32:$src1, i32mem:$src2),
624 "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
626 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
627 (ops R16:$dst, R16:$src1, R16:$src2),
628 "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
629 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
630 (ops R16:$dst, R16:$src1, i16mem:$src2),
631 "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
632 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
633 (ops R32:$dst, R32:$src1, R32:$src2),
634 "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
635 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
636 (ops R32:$dst, R32:$src1, i32mem:$src2),
637 "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
639 // unary instructions
640 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst",
641 [(set R8:$dst, (ineg R8:$src))]>;
642 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst",
643 [(set R16:$dst, (ineg R16:$src))]>, OpSize;
644 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst",
645 [(set R32:$dst, (ineg R32:$src))]>;
646 let isTwoAddress = 0 in {
647 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", []>;
648 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", []>, OpSize;
649 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", []>;
652 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst",
653 [(set R8:$dst, (not R8:$src))]>;
654 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst",
655 [(set R16:$dst, (not R16:$src))]>, OpSize;
656 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst",
657 [(set R32:$dst, (not R32:$src))]>;
658 let isTwoAddress = 0 in {
659 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", []>;
660 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", []>, OpSize;
661 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", []>;
664 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
665 [(set R8:$dst, (add R8:$src, 1))]>;
666 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
667 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst",
668 [(set R16:$dst, (add R16:$src, 1))]>, OpSize;
669 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst",
670 [(set R32:$dst, (add R32:$src, 1))]>;
672 let isTwoAddress = 0 in {
673 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", []>;
674 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", []>, OpSize;
675 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>;
678 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", []>;
679 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
680 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", []>,
682 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", []>;
685 let isTwoAddress = 0 in {
686 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", []>;
687 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", []>, OpSize;
688 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", []>;
691 // Logical operators...
692 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
693 def AND8rr : I<0x20, MRMDestReg,
694 (ops R8 :$dst, R8 :$src1, R8 :$src2),
695 "and{b} {$src2, $dst|$dst, $src2}",
696 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
697 def AND16rr : I<0x21, MRMDestReg,
698 (ops R16:$dst, R16:$src1, R16:$src2),
699 "and{w} {$src2, $dst|$dst, $src2}",
700 [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize;
701 def AND32rr : I<0x21, MRMDestReg,
702 (ops R32:$dst, R32:$src1, R32:$src2),
703 "and{l} {$src2, $dst|$dst, $src2}",
704 [(set R32:$dst, (and R32:$src1, R32:$src2))]>;
707 def AND8rm : I<0x22, MRMSrcMem,
708 (ops R8 :$dst, R8 :$src1, i8mem :$src2),
709 "and{b} {$src2, $dst|$dst, $src2}",[]>;
710 def AND16rm : I<0x23, MRMSrcMem,
711 (ops R16:$dst, R16:$src1, i16mem:$src2),
712 "and{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
713 def AND32rm : I<0x23, MRMSrcMem,
714 (ops R32:$dst, R32:$src1, i32mem:$src2),
715 "and{l} {$src2, $dst|$dst, $src2}", []>;
717 def AND8ri : Ii8<0x80, MRM4r,
718 (ops R8 :$dst, R8 :$src1, i8imm :$src2),
719 "and{b} {$src2, $dst|$dst, $src2}",
720 [(set R8:$dst, (and R8:$src1, imm:$src2))]>;
721 def AND16ri : Ii16<0x81, MRM4r,
722 (ops R16:$dst, R16:$src1, i16imm:$src2),
723 "and{w} {$src2, $dst|$dst, $src2}",
724 [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize;
725 def AND32ri : Ii32<0x81, MRM4r,
726 (ops R32:$dst, R32:$src1, i32imm:$src2),
727 "and{l} {$src2, $dst|$dst, $src2}",
728 [(set R32:$dst, (and R32:$src1, imm:$src2))]>;
729 def AND16ri8 : Ii8<0x83, MRM4r,
730 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
731 "and{w} {$src2, $dst|$dst, $src2}",
732 [(set R16:$dst, (and R16:$src1, immSExt8:$src2))]>, OpSize;
733 def AND32ri8 : Ii8<0x83, MRM4r,
734 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
735 "and{l} {$src2, $dst|$dst, $src2}",
736 [(set R32:$dst, (and R32:$src1, immSExt8:$src2))]>;
738 let isTwoAddress = 0 in {
739 def AND8mr : I<0x20, MRMDestMem,
740 (ops i8mem :$dst, R8 :$src),
741 "and{b} {$src, $dst|$dst, $src}", []>;
742 def AND16mr : I<0x21, MRMDestMem,
743 (ops i16mem:$dst, R16:$src),
744 "and{w} {$src, $dst|$dst, $src}", []>, OpSize;
745 def AND32mr : I<0x21, MRMDestMem,
746 (ops i32mem:$dst, R32:$src),
747 "and{l} {$src, $dst|$dst, $src}", []>;
748 def AND8mi : Ii8<0x80, MRM4m,
749 (ops i8mem :$dst, i8imm :$src),
750 "and{b} {$src, $dst|$dst, $src}", []>;
751 def AND16mi : Ii16<0x81, MRM4m,
752 (ops i16mem:$dst, i16imm:$src),
753 "and{w} {$src, $dst|$dst, $src}", []>, OpSize;
754 def AND32mi : Ii32<0x81, MRM4m,
755 (ops i32mem:$dst, i32imm:$src),
756 "and{l} {$src, $dst|$dst, $src}", []>;
757 def AND16mi8 : Ii8<0x83, MRM4m,
758 (ops i16mem:$dst, i8imm :$src),
759 "and{w} {$src, $dst|$dst, $src}", []>, OpSize;
760 def AND32mi8 : Ii8<0x83, MRM4m,
761 (ops i32mem:$dst, i8imm :$src),
762 "and{l} {$src, $dst|$dst, $src}", []>;
766 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
767 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
768 "or{b} {$src2, $dst|$dst, $src2}",
769 [(set R8:$dst, (or R8:$src1, R8:$src2))]>;
770 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
771 "or{w} {$src2, $dst|$dst, $src2}",
772 [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize;
773 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
774 "or{l} {$src2, $dst|$dst, $src2}",
775 [(set R32:$dst, (or R32:$src1, R32:$src2))]>;
777 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
778 "or{b} {$src2, $dst|$dst, $src2}", []>;
779 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
780 "or{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
781 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
782 "or{l} {$src2, $dst|$dst, $src2}", []>;
784 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
785 "or{b} {$src2, $dst|$dst, $src2}",
786 [(set R8:$dst, (or R8:$src1, imm:$src2))]>;
787 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
788 "or{w} {$src2, $dst|$dst, $src2}",
789 [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize;
790 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
791 "or{l} {$src2, $dst|$dst, $src2}",
792 [(set R32:$dst, (or R32:$src1, imm:$src2))]>;
794 def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
795 "or{w} {$src2, $dst|$dst, $src2}",
796 [(set R16:$dst, (or R16:$src1, immSExt8:$src2))]>, OpSize;
797 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
798 "or{l} {$src2, $dst|$dst, $src2}",
799 [(set R32:$dst, (or R32:$src1, immSExt8:$src2))]>;
800 let isTwoAddress = 0 in {
801 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
802 "or{b} {$src, $dst|$dst, $src}", []>;
803 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
804 "or{w} {$src, $dst|$dst, $src}", []>, OpSize;
805 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
806 "or{l} {$src, $dst|$dst, $src}", []>;
807 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
808 "or{b} {$src, $dst|$dst, $src}", []>;
809 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
810 "or{w} {$src, $dst|$dst, $src}", []>, OpSize;
811 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
812 "or{l} {$src, $dst|$dst, $src}", []>;
813 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
814 "or{w} {$src, $dst|$dst, $src}", []>, OpSize;
815 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
816 "or{l} {$src, $dst|$dst, $src}", []>;
820 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
821 def XOR8rr : I<0x30, MRMDestReg,
822 (ops R8 :$dst, R8 :$src1, R8 :$src2),
823 "xor{b} {$src2, $dst|$dst, $src2}",
824 [(set R8:$dst, (xor R8:$src1, R8:$src2))]>;
825 def XOR16rr : I<0x31, MRMDestReg,
826 (ops R16:$dst, R16:$src1, R16:$src2),
827 "xor{w} {$src2, $dst|$dst, $src2}",
828 [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize;
829 def XOR32rr : I<0x31, MRMDestReg,
830 (ops R32:$dst, R32:$src1, R32:$src2),
831 "xor{l} {$src2, $dst|$dst, $src2}",
832 [(set R32:$dst, (xor R32:$src1, R32:$src2))]>;
835 def XOR8rm : I<0x32, MRMSrcMem ,
836 (ops R8 :$dst, R8:$src1, i8mem :$src2),
837 "xor{b} {$src2, $dst|$dst, $src2}", []>;
838 def XOR16rm : I<0x33, MRMSrcMem ,
839 (ops R16:$dst, R8:$src1, i16mem:$src2),
840 "xor{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
841 def XOR32rm : I<0x33, MRMSrcMem ,
842 (ops R32:$dst, R8:$src1, i32mem:$src2),
843 "xor{l} {$src2, $dst|$dst, $src2}", []>;
845 def XOR8ri : Ii8<0x80, MRM6r,
846 (ops R8:$dst, R8:$src1, i8imm:$src2),
847 "xor{b} {$src2, $dst|$dst, $src2}",
848 [(set R8:$dst, (xor R8:$src1, imm:$src2))]>;
849 def XOR16ri : Ii16<0x81, MRM6r,
850 (ops R16:$dst, R16:$src1, i16imm:$src2),
851 "xor{w} {$src2, $dst|$dst, $src2}",
852 [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize;
853 def XOR32ri : Ii32<0x81, MRM6r,
854 (ops R32:$dst, R32:$src1, i32imm:$src2),
855 "xor{l} {$src2, $dst|$dst, $src2}",
856 [(set R32:$dst, (xor R32:$src1, imm:$src2))]>;
857 def XOR16ri8 : Ii8<0x83, MRM6r,
858 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
859 "xor{w} {$src2, $dst|$dst, $src2}",
860 [(set R16:$dst, (xor R16:$src1, immSExt8:$src2))]>, OpSize;
861 def XOR32ri8 : Ii8<0x83, MRM6r,
862 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
863 "xor{l} {$src2, $dst|$dst, $src2}",
864 [(set R32:$dst, (xor R32:$src1, immSExt8:$src2))]>;
865 let isTwoAddress = 0 in {
866 def XOR8mr : I<0x30, MRMDestMem,
867 (ops i8mem :$dst, R8 :$src),
868 "xor{b} {$src, $dst|$dst, $src}", []>;
869 def XOR16mr : I<0x31, MRMDestMem,
870 (ops i16mem:$dst, R16:$src),
871 "xor{w} {$src, $dst|$dst, $src}", []>, OpSize;
872 def XOR32mr : I<0x31, MRMDestMem,
873 (ops i32mem:$dst, R32:$src),
874 "xor{l} {$src, $dst|$dst, $src}", []>;
875 def XOR8mi : Ii8<0x80, MRM6m,
876 (ops i8mem :$dst, i8imm :$src),
877 "xor{b} {$src, $dst|$dst, $src}", []>;
878 def XOR16mi : Ii16<0x81, MRM6m,
879 (ops i16mem:$dst, i16imm:$src),
880 "xor{w} {$src, $dst|$dst, $src}", []>, OpSize;
881 def XOR32mi : Ii32<0x81, MRM6m,
882 (ops i32mem:$dst, i32imm:$src),
883 "xor{l} {$src, $dst|$dst, $src}", []>;
884 def XOR16mi8 : Ii8<0x83, MRM6m,
885 (ops i16mem:$dst, i8imm :$src),
886 "xor{w} {$src, $dst|$dst, $src}", []>, OpSize;
887 def XOR32mi8 : Ii8<0x83, MRM6m,
888 (ops i32mem:$dst, i8imm :$src),
889 "xor{l} {$src, $dst|$dst, $src}", []>;
892 // Shift instructions
893 // FIXME: provide shorter instructions when imm8 == 1
894 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
895 "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
896 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
897 "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
898 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
899 "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
901 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
902 "shl{b} {$src2, $dst|$dst, $src2}",
903 [(set R8:$dst, (shl R8:$src1, imm:$src2))]>;
904 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
905 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
906 "shl{w} {$src2, $dst|$dst, $src2}",
907 [(set R16:$dst, (shl R16:$src1, immSExt8:$src2))]>, OpSize;
908 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
909 "shl{l} {$src2, $dst|$dst, $src2}",
910 [(set R32:$dst, (shl R32:$src1, immSExt8:$src2))]>;
913 let isTwoAddress = 0 in {
914 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
915 "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
916 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
917 "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
918 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
919 "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
920 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
921 "shl{b} {$src, $dst|$dst, $src}, []", []>;
922 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
923 "shl{w} {$src, $dst|$dst, $src}, []", []>, OpSize;
924 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
925 "shl{l} {$src, $dst|$dst, $src}, []", []>;
928 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
929 "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
930 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
931 "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
932 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
933 "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
935 def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
936 "shr{b} {$src2, $dst|$dst, $src2}",
937 [(set R8:$dst, (srl R8:$src1, imm:$src2))]>;
938 def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
939 "shr{w} {$src2, $dst|$dst, $src2}",
940 [(set R16:$dst, (srl R16:$src1, immSExt8:$src2))]>, OpSize;
941 def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
942 "shr{l} {$src2, $dst|$dst, $src2}",
943 [(set R32:$dst, (srl R32:$src1, immSExt8:$src2))]>;
945 let isTwoAddress = 0 in {
946 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
947 "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
948 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
949 "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
950 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
951 "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
952 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
953 "shr{b} {$src, $dst|$dst, $src}", []>;
954 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
955 "shr{w} {$src, $dst|$dst, $src}", []>, OpSize;
956 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
957 "shr{l} {$src, $dst|$dst, $src}", []>;
960 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
961 "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
962 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
963 "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
964 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
965 "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
967 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
968 "sar{b} {$src2, $dst|$dst, $src2}",
969 [(set R8:$dst, (sra R8:$src1, imm:$src2))]>;
970 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
971 "sar{w} {$src2, $dst|$dst, $src2}",
972 [(set R16:$dst, (sra R16:$src1, immSExt8:$src2))]>, OpSize;
973 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
974 "sar{l} {$src2, $dst|$dst, $src2}",
975 [(set R32:$dst, (sra R32:$src1, immSExt8:$src2))]>;
976 let isTwoAddress = 0 in {
977 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
978 "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
979 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
980 "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
981 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
982 "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
983 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
984 "sar{b} {$src, $dst|$dst, $src}", []>;
985 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
986 "sar{w} {$src, $dst|$dst, $src}", []>, OpSize;
987 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
988 "sar{l} {$src, $dst|$dst, $src}", []>;
991 // Rotate instructions
992 // FIXME: provide shorter instructions when imm8 == 1
993 def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
994 "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
995 def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
996 "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
997 def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
998 "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1000 def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1001 "rol{b} {$src2, $dst|$dst, $src2}", []>;
1002 def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1003 "rol{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1004 def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1005 "rol{l} {$src2, $dst|$dst, $src2}", []>;
1007 let isTwoAddress = 0 in {
1008 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1009 "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1010 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1011 "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
1012 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1013 "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1014 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1015 "rol{b} {$src, $dst|$dst, $src}", []>;
1016 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1017 "rol{w} {$src, $dst|$dst, $src}", []>, OpSize;
1018 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1019 "rol{l} {$src, $dst|$dst, $src}", []>;
1022 def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
1023 "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1024 def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
1025 "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
1026 def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
1027 "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1029 def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1030 "ror{b} {$src2, $dst|$dst, $src2}", []>;
1031 def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1032 "ror{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1033 def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1034 "ror{l} {$src2, $dst|$dst, $src2}", []>;
1035 let isTwoAddress = 0 in {
1036 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1037 "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1038 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1039 "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
1040 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1041 "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
1042 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1043 "ror{b} {$src, $dst|$dst, $src}", []>;
1044 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1045 "ror{w} {$src, $dst|$dst, $src}", []>, OpSize;
1046 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1047 "ror{l} {$src, $dst|$dst, $src}", []>;
1052 // Double shift instructions (generalizations of rotate)
1054 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1055 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1057 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1058 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1060 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1061 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1062 Imp<[CL],[]>, TB, OpSize;
1063 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1064 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1065 Imp<[CL],[]>, TB, OpSize;
1067 let isCommutable = 1 in { // These instructions commute to each other.
1068 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1069 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
1070 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
1071 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1072 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
1073 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
1074 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1075 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1076 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1078 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1079 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1080 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1084 let isTwoAddress = 0 in {
1085 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1086 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1088 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1089 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1091 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1092 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1093 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1095 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1096 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1097 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1100 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1101 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1102 Imp<[CL],[]>, TB, OpSize;
1103 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1104 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
1105 Imp<[CL],[]>, TB, OpSize;
1106 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1107 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1108 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1110 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1111 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1112 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
1118 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1119 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1120 "add{b} {$src2, $dst|$dst, $src2}",
1121 [(set R8:$dst, (add R8:$src1, R8:$src2))]>;
1122 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1123 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1124 "add{w} {$src2, $dst|$dst, $src2}",
1125 [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize;
1126 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1127 "add{l} {$src2, $dst|$dst, $src2}",
1128 [(set R32:$dst, (add R32:$src1, R32:$src2))]>;
1129 } // end isConvertibleToThreeAddress
1130 } // end isCommutable
1131 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1132 "add{b} {$src2, $dst|$dst, $src2}", []>;
1133 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1134 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1135 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1136 "add{l} {$src2, $dst|$dst, $src2}", []>;
1138 def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1139 "add{b} {$src2, $dst|$dst, $src2}",
1140 [(set R8:$dst, (add R8:$src1, imm:$src2))]>;
1142 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1143 def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1144 "add{w} {$src2, $dst|$dst, $src2}",
1145 [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize;
1146 def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1147 "add{l} {$src2, $dst|$dst, $src2}",
1148 [(set R32:$dst, (add R32:$src1, imm:$src2))]>;
1151 // FIXME: move ADD16ri8 above ADD16ri to optimize for space.
1152 def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1153 "add{w} {$src2, $dst|$dst, $src2}",
1154 [(set R16:$dst, (add R16:$src1, immSExt8:$src2))]>, OpSize;
1155 def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1156 "add{l} {$src2, $dst|$dst, $src2}",
1157 [(set R32:$dst, (add R32:$src1, immSExt8:$src2))]>;
1159 let isTwoAddress = 0 in {
1160 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1161 "add{b} {$src2, $dst|$dst, $src2}", []>;
1162 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1163 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1164 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1165 "add{l} {$src2, $dst|$dst, $src2}", []>;
1166 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1167 "add{b} {$src2, $dst|$dst, $src2}", []>;
1168 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1169 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1170 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1171 "add{l} {$src2, $dst|$dst, $src2}", []>;
1172 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
1173 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1174 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2),
1175 "add{l} {$src2, $dst|$dst, $src2}", []>;
1178 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1179 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1180 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1182 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
1183 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1184 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1185 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1186 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1187 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1189 let isTwoAddress = 0 in {
1190 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1191 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1192 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1193 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1194 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
1195 "adc{l} {$src2, $dst|$dst, $src2}", []>;
1198 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1199 "sub{b} {$src2, $dst|$dst, $src2}",
1200 [(set R8:$dst, (sub R8:$src1, R8:$src2))]>;
1201 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1202 "sub{w} {$src2, $dst|$dst, $src2}",
1203 [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize;
1204 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1205 "sub{l} {$src2, $dst|$dst, $src2}",
1206 [(set R32:$dst, (sub R32:$src1, R32:$src2))]>;
1207 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1208 "sub{b} {$src2, $dst|$dst, $src2}", []>;
1209 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1210 "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1211 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1212 "sub{l} {$src2, $dst|$dst, $src2}", []>;
1214 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1215 "sub{b} {$src2, $dst|$dst, $src2}",
1216 [(set R8:$dst, (sub R8:$src1, imm:$src2))]>;
1217 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1218 "sub{w} {$src2, $dst|$dst, $src2}",
1219 [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize;
1220 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1221 "sub{l} {$src2, $dst|$dst, $src2}",
1222 [(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
1223 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1224 "sub{w} {$src2, $dst|$dst, $src2}",
1225 [(set R16:$dst, (sub R16:$src1, immSExt8:$src2))]>, OpSize;
1226 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1227 "sub{l} {$src2, $dst|$dst, $src2}",
1228 [(set R32:$dst, (sub R32:$src1, immSExt8:$src2))]>;
1229 let isTwoAddress = 0 in {
1230 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1231 "sub{b} {$src2, $dst|$dst, $src2}", []>;
1232 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1233 "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1234 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1235 "sub{l} {$src2, $dst|$dst, $src2}", []>;
1236 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1237 "sub{b} {$src2, $dst|$dst, $src2}", []>;
1238 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1239 "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1240 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1241 "sub{l} {$src2, $dst|$dst, $src2}", []>;
1242 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2),
1243 "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1244 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2),
1245 "sub{l} {$src2, $dst|$dst, $src2}", []>;
1248 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1249 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1251 let isTwoAddress = 0 in {
1252 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1253 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1254 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1255 "sbb{b} {$src2, $dst|$dst, $src2}", []>;
1256 def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
1257 "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1258 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
1259 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1260 def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
1261 "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1262 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
1263 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1265 def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1266 "sbb{b} {$src2, $dst|$dst, $src2}", []>;
1267 def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1268 "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1270 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1271 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1272 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1273 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1275 def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1276 "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
1277 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1278 "sbb{l} {$src2, $dst|$dst, $src2}", []>;
1280 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
1281 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
1282 "imul{w} {$src2, $dst|$dst, $src2}",
1283 [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize;
1284 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
1285 "imul{l} {$src2, $dst|$dst, $src2}",
1286 [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB;
1288 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1289 "imul{w} {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
1290 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1291 "imul{l} {$src2, $dst|$dst, $src2}", []>, TB;
1293 } // end Two Address instructions
1295 // Suprisingly enough, these are not two address instructions!
1296 def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
1297 (ops R16:$dst, R16:$src1, i16imm:$src2),
1298 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1299 [(set R16:$dst, (mul R16:$src1, imm:$src2))]>,
1301 def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
1302 (ops R32:$dst, R32:$src1, i32imm:$src2),
1303 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1304 [(set R32:$dst, (mul R32:$src1, imm:$src2))]>;
1305 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
1306 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1307 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1308 [(set R16:$dst, (mul R16:$src1, immSExt8:$src2))]>, OpSize;
1309 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
1310 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1311 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1312 [(set R32:$dst, (mul R32:$src1, immSExt8:$src2))]>;
1314 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
1315 (ops R32:$dst, i16mem:$src1, i16imm:$src2),
1316 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize;
1317 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
1318 (ops R32:$dst, i32mem:$src1, i32imm:$src2),
1319 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
1320 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
1321 (ops R32:$dst, i16mem:$src1, i8imm :$src2),
1322 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize;
1323 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
1324 (ops R32:$dst, i32mem:$src1, i8imm: $src2),
1325 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
1327 //===----------------------------------------------------------------------===//
1328 // Test instructions are just like AND, except they don't generate a result.
1330 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1331 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
1332 "test{b} {$src2, $src1|$src1, $src2}", []>;
1333 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
1334 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1335 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
1336 "test{l} {$src2, $src1|$src1, $src2}", []>;
1338 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
1339 "test{b} {$src2, $src1|$src1, $src2}", []>;
1340 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
1341 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1342 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
1343 "test{l} {$src2, $src1|$src1, $src2}", []>;
1344 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
1345 "test{b} {$src2, $src1|$src1, $src2}", []>;
1346 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
1347 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1348 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
1349 "test{l} {$src2, $src1|$src1, $src2}", []>;
1351 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
1352 (ops R8:$src1, i8imm:$src2),
1353 "test{b} {$src2, $src1|$src1, $src2}", []>;
1354 def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
1355 (ops R16:$src1, i16imm:$src2),
1356 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1357 def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
1358 (ops R32:$src1, i32imm:$src2),
1359 "test{l} {$src2, $src1|$src1, $src2}", []>;
1360 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1361 (ops i32mem:$src1, i8imm:$src2),
1362 "test{b} {$src2, $src1|$src1, $src2}", []>;
1363 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1364 (ops i16mem:$src1, i16imm:$src2),
1365 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1366 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1367 (ops i32mem:$src1, i32imm:$src2),
1368 "test{l} {$src2, $src1|$src1, $src2}", []>;
1372 // Condition code ops, incl. set if equal/not equal/...
1373 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
1374 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
1376 def SETBr : I<0x92, MRM0r,
1377 (ops R8 :$dst), "setb $dst", []>, TB; // R8 = < unsign
1378 def SETBm : I<0x92, MRM0m,
1379 (ops i8mem:$dst), "setb $dst", []>, TB; // [mem8] = < unsign
1380 def SETAEr : I<0x93, MRM0r,
1381 (ops R8 :$dst), "setae $dst", []>, TB; // R8 = >= unsign
1382 def SETAEm : I<0x93, MRM0m,
1383 (ops i8mem:$dst), "setae $dst", []>, TB; // [mem8] = >= unsign
1384 def SETEr : I<0x94, MRM0r,
1385 (ops R8 :$dst), "sete $dst", []>, TB; // R8 = ==
1386 def SETEm : I<0x94, MRM0m,
1387 (ops i8mem:$dst), "sete $dst", []>, TB; // [mem8] = ==
1388 def SETNEr : I<0x95, MRM0r,
1389 (ops R8 :$dst), "setne $dst", []>, TB; // R8 = !=
1390 def SETNEm : I<0x95, MRM0m,
1391 (ops i8mem:$dst), "setne $dst", []>, TB; // [mem8] = !=
1392 def SETBEr : I<0x96, MRM0r,
1393 (ops R8 :$dst), "setbe $dst", []>, TB; // R8 = <= unsign
1394 def SETBEm : I<0x96, MRM0m,
1395 (ops i8mem:$dst), "setbe $dst", []>, TB; // [mem8] = <= unsign
1396 def SETAr : I<0x97, MRM0r,
1397 (ops R8 :$dst), "seta $dst", []>, TB; // R8 = > signed
1398 def SETAm : I<0x97, MRM0m,
1399 (ops i8mem:$dst), "seta $dst", []>, TB; // [mem8] = > signed
1400 def SETSr : I<0x98, MRM0r,
1401 (ops R8 :$dst), "sets $dst", []>, TB; // R8 = <sign bit>
1402 def SETSm : I<0x98, MRM0m,
1403 (ops i8mem:$dst), "sets $dst", []>, TB; // [mem8] = <sign bit>
1404 def SETNSr : I<0x99, MRM0r,
1405 (ops R8 :$dst), "setns $dst", []>, TB; // R8 = !<sign bit>
1406 def SETNSm : I<0x99, MRM0m,
1407 (ops i8mem:$dst), "setns $dst", []>, TB; // [mem8] = !<sign bit>
1408 def SETPr : I<0x9A, MRM0r,
1409 (ops R8 :$dst), "setp $dst", []>, TB; // R8 = parity
1410 def SETPm : I<0x9A, MRM0m,
1411 (ops i8mem:$dst), "setp $dst", []>, TB; // [mem8] = parity
1412 def SETNPr : I<0x9B, MRM0r,
1413 (ops R8 :$dst), "setnp $dst", []>, TB; // R8 = not parity
1414 def SETNPm : I<0x9B, MRM0m,
1415 (ops i8mem:$dst), "setnp $dst", []>, TB; // [mem8] = not parity
1416 def SETLr : I<0x9C, MRM0r,
1417 (ops R8 :$dst), "setl $dst", []>, TB; // R8 = < signed
1418 def SETLm : I<0x9C, MRM0m,
1419 (ops i8mem:$dst), "setl $dst", []>, TB; // [mem8] = < signed
1420 def SETGEr : I<0x9D, MRM0r,
1421 (ops R8 :$dst), "setge $dst", []>, TB; // R8 = >= signed
1422 def SETGEm : I<0x9D, MRM0m,
1423 (ops i8mem:$dst), "setge $dst", []>, TB; // [mem8] = >= signed
1424 def SETLEr : I<0x9E, MRM0r,
1425 (ops R8 :$dst), "setle $dst", []>, TB; // R8 = <= signed
1426 def SETLEm : I<0x9E, MRM0m,
1427 (ops i8mem:$dst), "setle $dst", []>, TB; // [mem8] = <= signed
1428 def SETGr : I<0x9F, MRM0r,
1429 (ops R8 :$dst), "setg $dst", []>, TB; // R8 = < signed
1430 def SETGm : I<0x9F, MRM0m,
1431 (ops i8mem:$dst), "setg $dst", []>, TB; // [mem8] = < signed
1433 // Integer comparisons
1434 def CMP8rr : I<0x38, MRMDestReg,
1435 (ops R8 :$src1, R8 :$src2),
1436 "cmp{b} {$src2, $src1|$src1, $src2}", []>;
1437 def CMP16rr : I<0x39, MRMDestReg,
1438 (ops R16:$src1, R16:$src2),
1439 "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1440 def CMP32rr : I<0x39, MRMDestReg,
1441 (ops R32:$src1, R32:$src2),
1442 "cmp{l} {$src2, $src1|$src1, $src2}", []>;
1443 def CMP8mr : I<0x38, MRMDestMem,
1444 (ops i8mem :$src1, R8 :$src2),
1445 "cmp{b} {$src2, $src1|$src1, $src2}", []>;
1446 def CMP16mr : I<0x39, MRMDestMem,
1447 (ops i16mem:$src1, R16:$src2),
1448 "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1449 def CMP32mr : I<0x39, MRMDestMem,
1450 (ops i32mem:$src1, R32:$src2),
1451 "cmp{l} {$src2, $src1|$src1, $src2}", []>;
1452 def CMP8rm : I<0x3A, MRMSrcMem,
1453 (ops R8 :$src1, i8mem :$src2),
1454 "cmp{b} {$src2, $src1|$src1, $src2}", []>;
1455 def CMP16rm : I<0x3B, MRMSrcMem,
1456 (ops R16:$src1, i16mem:$src2),
1457 "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1458 def CMP32rm : I<0x3B, MRMSrcMem,
1459 (ops R32:$src1, i32mem:$src2),
1460 "cmp{l} {$src2, $src1|$src1, $src2}", []>;
1461 def CMP8ri : Ii8<0x80, MRM7r,
1462 (ops R16:$src1, i8imm:$src2),
1463 "cmp{b} {$src2, $src1|$src1, $src2}", []>;
1464 def CMP16ri : Ii16<0x81, MRM7r,
1465 (ops R16:$src1, i16imm:$src2),
1466 "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1467 def CMP32ri : Ii32<0x81, MRM7r,
1468 (ops R32:$src1, i32imm:$src2),
1469 "cmp{l} {$src2, $src1|$src1, $src2}", []>;
1470 def CMP8mi : Ii8 <0x80, MRM7m,
1471 (ops i8mem :$src1, i8imm :$src2),
1472 "cmp{b} {$src2, $src1|$src1, $src2}", []>;
1473 def CMP16mi : Ii16<0x81, MRM7m,
1474 (ops i16mem:$src1, i16imm:$src2),
1475 "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
1476 def CMP32mi : Ii32<0x81, MRM7m,
1477 (ops i32mem:$src1, i32imm:$src2),
1478 "cmp{l} {$src2, $src1|$src1, $src2}", []>;
1480 // Sign/Zero extenders
1481 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
1482 "movs{bw|x} {$src, $dst|$dst, $src}",
1483 [(set R16:$dst, (sext R8:$src))]>, TB, OpSize;
1484 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1485 "movs{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize;
1486 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
1487 "movs{bl|x} {$src, $dst|$dst, $src}",
1488 [(set R32:$dst, (sext R8:$src))]>, TB;
1489 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1490 "movs{bl|x} {$src, $dst|$dst, $src}", []>, TB;
1491 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
1492 "movs{wl|x} {$src, $dst|$dst, $src}",
1493 [(set R32:$dst, (sext R16:$src))]>, TB;
1494 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1495 "movs{wl|x} {$src, $dst|$dst, $src}", []>, TB;
1497 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
1498 "movz{bw|x} {$src, $dst|$dst, $src}",
1499 [(set R16:$dst, (zext R8:$src))]>, TB, OpSize;
1500 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1501 "movz{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize;
1502 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
1503 "movz{bl|x} {$src, $dst|$dst, $src}",
1504 [(set R32:$dst, (zext R8:$src))]>, TB;
1505 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1506 "movz{bl|x} {$src, $dst|$dst, $src}", []>, TB;
1507 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
1508 "movz{wl|x} {$src, $dst|$dst, $src}",
1509 [(set R32:$dst, (zext R16:$src))]>, TB;
1510 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1511 "movz{wl|x} {$src, $dst|$dst, $src}", []>, TB;
1513 //===----------------------------------------------------------------------===//
1514 // XMM Floating point support (requires SSE2)
1515 //===----------------------------------------------------------------------===//
1517 def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
1518 "movss {$src, $dst|$dst, $src}", []>, XS;
1519 def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
1520 "movss {$src, $dst|$dst, $src}", []>, XS;
1521 def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src),
1522 "movss {$src, $dst|$dst, $src}", []>, XS;
1523 def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
1524 "movsd {$src, $dst|$dst, $src}", []>, XD;
1525 def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
1526 "movsd {$src, $dst|$dst, $src}", []>, XD;
1527 def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src),
1528 "movsd {$src, $dst|$dst, $src}", []>, XD;
1530 def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src),
1531 "cvttsd2si {$src, $dst|$dst, $src}",
1532 [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD;
1533 def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
1534 "cvttsd2si {$src, $dst|$dst, $src}", []>, XD;
1535 def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src),
1536 "cvttss2si {$src, $dst|$dst, $src}",
1537 [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS;
1538 def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1539 "cvttss2si {$src, $dst|$dst, $src}", []>, XS;
1540 def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src),
1541 "cvtsd2ss {$src, $dst|$dst, $src}",
1542 [(set V4F4:$dst, (fround V2F8:$src))]>, XS;
1543 def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src),
1544 "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS;
1545 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src),
1546 "cvtss2sd {$src, $dst|$dst, $src}",
1547 [(set V2F8:$dst, (fextend V4F4:$src))]>, XD;
1548 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src),
1549 "cvtss2sd {$src, $dst|$dst, $src}", []>, XD;
1550 def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src),
1551 "cvtsi2ss {$src, $dst|$dst, $src}",
1552 [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS;
1553 def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src),
1554 "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS;
1555 def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src),
1556 "cvtsi2sd {$src, $dst|$dst, $src}",
1557 [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD;
1558 def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src),
1559 "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD;
1561 def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
1562 "sqrtss {$src, $dst|$dst, $src}", []>, XS;
1563 def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
1564 "sqrtss {$src, $dst|$dst, $src}",
1565 [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS;
1566 def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
1567 "sqrtsd {$src, $dst|$dst, $src}", []>, XD;
1568 def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
1569 "sqrtsd {$src, $dst|$dst, $src}",
1570 [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD;
1572 def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
1573 "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
1574 def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
1575 "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
1576 def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
1577 "ucomiss {$src, $dst|$dst, $src}", []>, TB;
1578 def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
1579 "ucomiss {$src, $dst|$dst, $src}", []>, TB;
1581 // Pseudo-instructions that map fld0 to xorps/xorpd for sse.
1582 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1583 def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst),
1584 "xorps $dst, $dst", []>, TB;
1585 def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst),
1586 "xorpd $dst, $dst", []>, TB, OpSize;
1588 let isTwoAddress = 1 in {
1589 let isCommutable = 1 in {
1590 def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1591 "addss {$src2, $dst|$dst, $src2}",
1592 [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS;
1593 def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1594 "addsd {$src2, $dst|$dst, $src2}",
1595 [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD;
1596 def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1597 "andps {$src2, $dst|$dst, $src2}", []>, TB;
1598 def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1599 "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
1600 def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1601 "mulss {$src2, $dst|$dst, $src2}",
1602 [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS;
1603 def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1604 "mulsd {$src2, $dst|$dst, $src2}",
1605 [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD;
1606 def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1607 "orps {$src2, $dst|$dst, $src2}", []>, TB;
1608 def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1609 "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
1610 def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1611 "xorps {$src2, $dst|$dst, $src2}", []>, TB;
1612 def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1613 "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
1615 def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1616 "andnps {$src2, $dst|$dst, $src2}", []>, TB;
1617 def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1618 "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
1619 def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
1620 "addss {$src2, $dst|$dst, $src2}", []>, XS;
1621 def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
1622 "addsd {$src2, $dst|$dst, $src2}", []>, XD;
1623 def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
1624 "mulss {$src2, $dst|$dst, $src2}", []>, XS;
1625 def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
1626 "mulsd {$src2, $dst|$dst, $src2}", []>, XD;
1628 def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
1629 "divss {$src2, $dst|$dst, $src2}", []>, XS;
1630 def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1631 "divss {$src2, $dst|$dst, $src2}",
1632 [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS;
1633 def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
1634 "divsd {$src2, $dst|$dst, $src2}", []>, XD;
1635 def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1636 "divsd {$src2, $dst|$dst, $src2}",
1637 [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD;
1639 def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
1640 "subss {$src2, $dst|$dst, $src2}", []>, XS;
1641 def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
1642 "subss {$src2, $dst|$dst, $src2}",
1643 [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS;
1644 def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
1645 "subsd {$src2, $dst|$dst, $src2}", []>, XD;
1646 def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
1647 "subsd {$src2, $dst|$dst, $src2}",
1648 [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD;
1650 def CMPSSrr : I<0xC2, MRMSrcReg,
1651 (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc),
1652 "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
1653 def CMPSSrm : I<0xC2, MRMSrcMem,
1654 (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc),
1655 "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
1656 def CMPSDrr : I<0xC2, MRMSrcReg,
1657 (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc),
1658 "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
1659 def CMPSDrm : I<0xC2, MRMSrcMem,
1660 (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc),
1661 "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
1664 //===----------------------------------------------------------------------===//
1665 // Miscellaneous Instructions
1666 //===----------------------------------------------------------------------===//
1668 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>;
1671 //===----------------------------------------------------------------------===//
1672 // Stack-based Floating point support
1673 //===----------------------------------------------------------------------===//
1675 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
1677 // Floating point instruction template
1678 class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
1679 : X86Inst<o, F, NoImm, ops, asm> {
1680 let FPForm = fp; let FPFormBits = FPForm.Value;
1683 // Pseudo instructions for floating point. We use these pseudo instructions
1684 // because they can be expanded by the fp spackifier into one of many different
1685 // forms of instructions for doing these operations. Until the stackifier runs,
1686 // we prefer to be abstract.
1687 def FpMOV : FPI<0, Pseudo, SpecialFP,
1688 (ops RFP:$dst, RFP:$src), "">; // f1 = fmov f2
1689 def FpADD : FPI<0, Pseudo, TwoArgFP ,
1690 (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fadd f2, f3
1691 def FpSUB : FPI<0, Pseudo, TwoArgFP ,
1692 (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fsub f2, f3
1693 def FpMUL : FPI<0, Pseudo, TwoArgFP ,
1694 (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fmul f2, f3
1695 def FpDIV : FPI<0, Pseudo, TwoArgFP ,
1696 (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fdiv f2, f3
1698 def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$dst), "">,
1699 Imp<[ST0], []>; // FPR = ST(0)
1701 def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$src), "">,
1702 Imp<[], [ST0]>; // ST(0) = FPR
1704 // FADD reg, mem: Before stackification, these are represented by:
1705 // R1 = FADD* R2, [mem]
1706 def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
1707 (ops f32mem:$src, variable_ops),
1709 def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
1710 (ops f64mem:$src, variable_ops),
1712 //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
1713 //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
1715 // FMUL reg, mem: Before stackification, these are represented by:
1716 // R1 = FMUL* R2, [mem]
1717 def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
1718 (ops f32mem:$src, variable_ops),
1720 def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
1721 (ops f64mem:$src, variable_ops),
1723 // ST(0) = ST(0) * [mem16int]
1724 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
1725 // ST(0) = ST(0) * [mem32int]
1726 //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
1728 // FSUB reg, mem: Before stackification, these are represented by:
1729 // R1 = FSUB* R2, [mem]
1730 def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
1731 (ops f32mem:$src, variable_ops),
1733 def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
1734 (ops f64mem:$src, variable_ops),
1736 // ST(0) = ST(0) - [mem16int]
1737 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
1738 // ST(0) = ST(0) - [mem32int]
1739 //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
1741 // FSUBR reg, mem: Before stackification, these are represented by:
1742 // R1 = FSUBR* R2, [mem]
1744 // Note that the order of operands does not reflect the operation being
1746 def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
1747 (ops f32mem:$src, variable_ops),
1749 def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
1750 (ops f64mem:$src, variable_ops),
1752 // ST(0) = [mem16int] - ST(0)
1753 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
1754 // ST(0) = [mem32int] - ST(0)
1755 //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
1757 // FDIV reg, mem: Before stackification, these are represented by:
1758 // R1 = FDIV* R2, [mem]
1759 def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
1760 (ops f32mem:$src, variable_ops),
1762 def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
1763 (ops f64mem:$src, variable_ops),
1765 // ST(0) = ST(0) / [mem16int]
1766 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
1767 // ST(0) = ST(0) / [mem32int]
1768 //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
1770 // FDIVR reg, mem: Before stackification, these are represented by:
1771 // R1 = FDIVR* R2, [mem]
1772 // Note that the order of operands does not reflect the operation being
1774 def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
1775 (ops f32mem:$src, variable_ops),
1777 def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
1778 (ops f64mem:$src, variable_ops),
1780 // ST(0) = [mem16int] / ST(0)
1781 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
1782 // ST(0) = [mem32int] / ST(0)
1783 //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
1786 // Floating point cmovs...
1787 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
1788 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
1789 (ops RST:$op, variable_ops),
1790 "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
1791 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
1792 (ops RST:$op, variable_ops),
1793 "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
1794 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
1795 (ops RST:$op, variable_ops),
1796 "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
1797 def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP,
1798 (ops RST:$op, variable_ops),
1799 "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
1800 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
1801 (ops RST:$op, variable_ops),
1802 "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
1803 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
1804 (ops RST:$op, variable_ops),
1805 "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
1806 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
1807 (ops RST:$op, variable_ops),
1808 "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
1809 def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
1810 (ops RST:$op, variable_ops),
1811 "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
1814 // Floating point loads & stores...
1815 // FIXME: these are all marked variable_ops because they have an implicit
1816 // destination. Instructions like FILD* that are generated by the instruction
1817 // selector (not the fp stackifier) need more accurate operand accounting.
1818 def FLDrr : FPI<0xC0, AddRegFrm, NotFP,
1819 (ops RST:$src, variable_ops),
1821 def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP,
1822 (ops f32mem:$src, variable_ops),
1824 def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP,
1825 (ops f64mem:$src, variable_ops),
1827 def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP,
1828 (ops f80mem:$src, variable_ops),
1830 def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
1831 (ops i16mem:$src, variable_ops),
1833 def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
1834 (ops i32mem:$src, variable_ops),
1836 def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
1837 (ops i64mem:$src, variable_ops),
1840 def FSTrr : FPI<0xD0, AddRegFrm, NotFP,
1841 (ops RST:$op, variable_ops),
1843 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP,
1844 (ops RST:$op, variable_ops),
1846 def FST32m : FPI<0xD9, MRM2m, OneArgFP,
1847 (ops f32mem:$op, variable_ops),
1849 def FST64m : FPI<0xDD, MRM2m, OneArgFP,
1850 (ops f64mem:$op, variable_ops),
1852 def FSTP32m : FPI<0xD9, MRM3m, OneArgFP,
1853 (ops f32mem:$op, variable_ops),
1855 def FSTP64m : FPI<0xDD, MRM3m, OneArgFP,
1856 (ops f64mem:$op, variable_ops),
1858 def FSTP80m : FPI<0xDB, MRM7m, OneArgFP,
1859 (ops f80mem:$op, variable_ops),
1862 def FIST16m : FPI<0xDF, MRM2m , OneArgFP,
1863 (ops i16mem:$op, variable_ops),
1865 def FIST32m : FPI<0xDB, MRM2m , OneArgFP,
1866 (ops i32mem:$op, variable_ops),
1868 def FISTP16m : FPI<0xDF, MRM3m , NotFP ,
1869 (ops i16mem:$op, variable_ops),
1871 def FISTP32m : FPI<0xDB, MRM3m , NotFP ,
1872 (ops i32mem:$op, variable_ops),
1874 def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
1875 (ops i64mem:$op, variable_ops),
1878 def FXCH : FPI<0xC8, AddRegFrm, NotFP,
1879 (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
1881 // Floating point constant loads...
1882 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
1883 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;
1886 // Unary operations...
1887 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, // f1 = fchs f2
1890 def FABS : FPI<0xE1, RawFrm, OneArgFPRW, // f1 = fabs f2
1893 def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, // fsqrt ST(0)
1896 def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, // fsin ST(0)
1899 def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, // fcos ST(0)
1902 def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0)
1906 // Binary arithmetic operations...
1907 class FPST0rInst<bits<8> o, dag ops, string asm>
1908 : I<o, AddRegFrm, ops, asm, []>, D8 {
1909 list<Register> Uses = [ST0];
1910 list<Register> Defs = [ST0];
1912 class FPrST0Inst<bits<8> o, dag ops, string asm>
1913 : I<o, AddRegFrm, ops, asm, []>, DC {
1914 list<Register> Uses = [ST0];
1916 class FPrST0PInst<bits<8> o, dag ops, string asm>
1917 : I<o, AddRegFrm, ops, asm, []>, DE {
1918 list<Register> Uses = [ST0];
1921 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
1923 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
1924 "fadd {%ST(0), $op|$op, %ST(0)}">;
1925 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
1928 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
1929 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
1930 // we have to put some 'r's in and take them out of weird places.
1931 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
1933 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
1934 "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
1935 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
1938 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
1940 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
1941 "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
1942 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
1945 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
1947 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
1948 "fmul {%ST(0), $op|$op, %ST(0)}">;
1949 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
1952 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
1954 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
1955 "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
1956 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
1959 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
1961 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
1962 "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
1963 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
1966 // Floating point compares
1967 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
1968 (ops RST:$reg, variable_ops),
1969 "fucom $reg">, DD, Imp<[ST0],[]>;
1970 def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
1971 (ops RST:$reg, variable_ops),
1972 "fucomp $reg", []>, DD, Imp<[ST0],[]>;
1973 def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
1975 "fucompp", []>, DA, Imp<[ST0],[]>;
1977 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
1978 (ops RST:$reg, variable_ops),
1979 "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
1980 def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
1981 (ops RST:$reg, variable_ops),
1982 "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>;
1985 // Floating point flag ops
1986 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
1987 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
1989 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
1990 (ops i16mem:$dst), "fnstcw $dst", []>;
1991 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
1992 (ops i16mem:$dst), "fldcw $dst", []>;