1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
254 [SDNPHasChain, SDNPOutGlue]>;
256 //===----------------------------------------------------------------------===//
257 // X86 Operand Definitions.
260 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
261 // the index operand of an address, to conform to x86 encoding restrictions.
262 def ptr_rc_nosp : PointerLikeRegClass<1>;
264 // *mem - Operand definitions for the funky X86 addressing mode operands.
266 def X86MemAsmOperand : AsmOperandClass {
269 let RenderMethod = "addMemOperands" in {
270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
278 // Gather mem operands
279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
287 def X86AbsMemAsmOperand : AsmOperandClass {
289 let SuperClasses = [X86MemAsmOperand];
292 class X86MemOperand<string printMethod,
293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
294 let PrintMethod = printMethod;
295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
296 let ParserMatchClass = parserMatchClass;
297 let OperandType = "OPERAND_MEMORY";
300 // Gather mem operands
301 class X86VMemOperand<RegisterClass RC, string printMethod,
302 AsmOperandClass parserMatchClass>
303 : X86MemOperand<printMethod, parserMatchClass> {
304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
307 def anymem : X86MemOperand<"printanymem">;
309 def opaque32mem : X86MemOperand<"printopaquemem">;
310 def opaque48mem : X86MemOperand<"printopaquemem">;
311 def opaque80mem : X86MemOperand<"printopaquemem">;
312 def opaque512mem : X86MemOperand<"printopaquemem">;
314 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
315 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
316 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
317 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
318 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
319 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
320 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
321 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
322 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
323 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
324 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
325 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
326 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
328 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
330 // Gather mem operands
331 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
332 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
333 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
334 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
336 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
337 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
339 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
340 // plain GR64, so that it doesn't potentially require a REX prefix.
341 def i8mem_NOREX : Operand<i64> {
342 let PrintMethod = "printi8mem";
343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
344 let ParserMatchClass = X86Mem8AsmOperand;
345 let OperandType = "OPERAND_MEMORY";
348 // GPRs available for tailcall.
349 // It represents GR32_TC, GR64_TC or GR64_TCW64.
350 def ptr_rc_tailcall : PointerLikeRegClass<2>;
352 // Special i32mem for addresses of load folding tail calls. These are not
353 // allowed to use callee-saved registers since they must be scheduled
354 // after callee-saved register are popped.
355 def i32mem_TC : Operand<i32> {
356 let PrintMethod = "printi32mem";
357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
359 let ParserMatchClass = X86Mem32AsmOperand;
360 let OperandType = "OPERAND_MEMORY";
363 // Special i64mem for addresses of load folding tail calls. These are not
364 // allowed to use callee-saved registers since they must be scheduled
365 // after callee-saved register are popped.
366 def i64mem_TC : Operand<i64> {
367 let PrintMethod = "printi64mem";
368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
369 ptr_rc_tailcall, i32imm, i8imm);
370 let ParserMatchClass = X86Mem64AsmOperand;
371 let OperandType = "OPERAND_MEMORY";
374 let OperandType = "OPERAND_PCREL",
375 ParserMatchClass = X86AbsMemAsmOperand,
376 PrintMethod = "printPCRelImm" in {
377 def i32imm_pcrel : Operand<i32>;
378 def i16imm_pcrel : Operand<i16>;
380 // Branch targets have OtherVT type and print as pc-relative values.
381 def brtarget : Operand<OtherVT>;
382 def brtarget8 : Operand<OtherVT>;
386 // Special parsers to detect mode to disambiguate.
387 def X86AbsMem16AsmOperand : AsmOperandClass {
388 let Name = "AbsMem16";
389 let RenderMethod = "addAbsMemOperands";
390 let SuperClasses = [X86AbsMemAsmOperand];
393 def X86AbsMem32AsmOperand : AsmOperandClass {
394 let Name = "AbsMem32";
395 let RenderMethod = "addAbsMemOperands";
396 let SuperClasses = [X86AbsMemAsmOperand];
399 // Branch targets have OtherVT type and print as pc-relative values.
400 let OperandType = "OPERAND_PCREL",
401 PrintMethod = "printPCRelImm" in {
402 let ParserMatchClass = X86AbsMem16AsmOperand in
403 def brtarget16 : Operand<OtherVT>;
404 let ParserMatchClass = X86AbsMem32AsmOperand in
405 def brtarget32 : Operand<OtherVT>;
408 let RenderMethod = "addSrcIdxOperands" in {
409 def X86SrcIdx8Operand : AsmOperandClass {
410 let Name = "SrcIdx8";
411 let SuperClasses = [X86Mem8AsmOperand];
413 def X86SrcIdx16Operand : AsmOperandClass {
414 let Name = "SrcIdx16";
415 let SuperClasses = [X86Mem16AsmOperand];
417 def X86SrcIdx32Operand : AsmOperandClass {
418 let Name = "SrcIdx32";
419 let SuperClasses = [X86Mem32AsmOperand];
421 def X86SrcIdx64Operand : AsmOperandClass {
422 let Name = "SrcIdx64";
423 let SuperClasses = [X86Mem64AsmOperand];
425 } // RenderMethod = "addSrcIdxOperands"
427 let RenderMethod = "addDstIdxOperands" in {
428 def X86DstIdx8Operand : AsmOperandClass {
429 let Name = "DstIdx8";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86DstIdx16Operand : AsmOperandClass {
433 let Name = "DstIdx16";
434 let SuperClasses = [X86Mem16AsmOperand];
436 def X86DstIdx32Operand : AsmOperandClass {
437 let Name = "DstIdx32";
438 let SuperClasses = [X86Mem32AsmOperand];
440 def X86DstIdx64Operand : AsmOperandClass {
441 let Name = "DstIdx64";
442 let SuperClasses = [X86Mem64AsmOperand];
444 } // RenderMethod = "addDstIdxOperands"
446 let RenderMethod = "addMemOffsOperands" in {
447 def X86MemOffs16_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs16_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs16_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs16_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs32_8AsmOperand : AsmOperandClass {
460 let Name = "MemOffs32_8";
461 let SuperClasses = [X86Mem8AsmOperand];
463 def X86MemOffs32_16AsmOperand : AsmOperandClass {
464 let Name = "MemOffs32_16";
465 let SuperClasses = [X86Mem16AsmOperand];
467 def X86MemOffs32_32AsmOperand : AsmOperandClass {
468 let Name = "MemOffs32_32";
469 let SuperClasses = [X86Mem32AsmOperand];
471 def X86MemOffs32_64AsmOperand : AsmOperandClass {
472 let Name = "MemOffs32_64";
473 let SuperClasses = [X86Mem64AsmOperand];
475 def X86MemOffs64_8AsmOperand : AsmOperandClass {
476 let Name = "MemOffs64_8";
477 let SuperClasses = [X86Mem8AsmOperand];
479 def X86MemOffs64_16AsmOperand : AsmOperandClass {
480 let Name = "MemOffs64_16";
481 let SuperClasses = [X86Mem16AsmOperand];
483 def X86MemOffs64_32AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64_32";
485 let SuperClasses = [X86Mem32AsmOperand];
487 def X86MemOffs64_64AsmOperand : AsmOperandClass {
488 let Name = "MemOffs64_64";
489 let SuperClasses = [X86Mem64AsmOperand];
491 } // RenderMethod = "addMemOffsOperands"
493 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
494 : X86MemOperand<printMethod, parserMatchClass> {
495 let MIOperandInfo = (ops ptr_rc, i8imm);
498 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
499 : X86MemOperand<printMethod, parserMatchClass> {
500 let MIOperandInfo = (ops ptr_rc);
503 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
504 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
505 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
506 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
507 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
508 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
509 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
510 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
512 class X86MemOffsOperand<Operand immOperand, string printMethod,
513 AsmOperandClass parserMatchClass>
514 : X86MemOperand<printMethod, parserMatchClass> {
515 let MIOperandInfo = (ops immOperand, i8imm);
518 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
519 X86MemOffs16_8AsmOperand>;
520 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
521 X86MemOffs16_16AsmOperand>;
522 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
523 X86MemOffs16_32AsmOperand>;
524 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
525 X86MemOffs32_8AsmOperand>;
526 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
527 X86MemOffs32_16AsmOperand>;
528 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
529 X86MemOffs32_32AsmOperand>;
530 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
531 X86MemOffs32_64AsmOperand>;
532 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
533 X86MemOffs64_8AsmOperand>;
534 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
535 X86MemOffs64_16AsmOperand>;
536 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
537 X86MemOffs64_32AsmOperand>;
538 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
539 X86MemOffs64_64AsmOperand>;
541 def SSECC : Operand<i8> {
542 let PrintMethod = "printSSEAVXCC";
543 let OperandType = "OPERAND_IMMEDIATE";
546 def i8immZExt3 : ImmLeaf<i8, [{
547 return Imm >= 0 && Imm < 8;
550 def AVXCC : Operand<i8> {
551 let PrintMethod = "printSSEAVXCC";
552 let OperandType = "OPERAND_IMMEDIATE";
555 def i8immZExt5 : ImmLeaf<i8, [{
556 return Imm >= 0 && Imm < 32;
559 def AVX512ICC : Operand<i8> {
560 let PrintMethod = "printSSEAVXCC";
561 let OperandType = "OPERAND_IMMEDIATE";
564 def XOPCC : Operand<i8> {
565 let PrintMethod = "printXOPCC";
566 let OperandType = "OPERAND_IMMEDIATE";
569 class ImmSExtAsmOperandClass : AsmOperandClass {
570 let SuperClasses = [ImmAsmOperand];
571 let RenderMethod = "addImmOperands";
574 def X86GR32orGR64AsmOperand : AsmOperandClass {
575 let Name = "GR32orGR64";
578 def GR32orGR64 : RegisterOperand<GR32> {
579 let ParserMatchClass = X86GR32orGR64AsmOperand;
582 def AVX512RC : Operand<i32> {
583 let PrintMethod = "printRoundingControl";
584 let OperandType = "OPERAND_IMMEDIATE";
587 // Sign-extended immediate classes. We don't need to define the full lattice
588 // here because there is no instruction with an ambiguity between ImmSExti64i32
591 // The strange ranges come from the fact that the assembler always works with
592 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
593 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
596 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
597 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
598 let Name = "ImmSExti64i32";
601 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
602 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
603 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
604 let Name = "ImmSExti16i8";
605 let SuperClasses = [ImmSExti64i32AsmOperand];
608 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
609 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
610 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
611 let Name = "ImmSExti32i8";
615 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
616 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
617 let Name = "ImmSExti64i8";
618 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
619 ImmSExti64i32AsmOperand];
622 // Unsigned immediate used by SSE/AVX instructions
624 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
625 def ImmUnsignedi8AsmOperand : AsmOperandClass {
626 let Name = "ImmUnsignedi8";
627 let RenderMethod = "addImmOperands";
630 // A couple of more descriptive operand definitions.
631 // 16-bits but only 8 bits are significant.
632 def i16i8imm : Operand<i16> {
633 let ParserMatchClass = ImmSExti16i8AsmOperand;
634 let OperandType = "OPERAND_IMMEDIATE";
636 // 32-bits but only 8 bits are significant.
637 def i32i8imm : Operand<i32> {
638 let ParserMatchClass = ImmSExti32i8AsmOperand;
639 let OperandType = "OPERAND_IMMEDIATE";
642 // 64-bits but only 32 bits are significant.
643 def i64i32imm : Operand<i64> {
644 let ParserMatchClass = ImmSExti64i32AsmOperand;
645 let OperandType = "OPERAND_IMMEDIATE";
648 // 64-bits but only 8 bits are significant.
649 def i64i8imm : Operand<i64> {
650 let ParserMatchClass = ImmSExti64i8AsmOperand;
651 let OperandType = "OPERAND_IMMEDIATE";
654 // Unsigned 8-bit immediate used by SSE/AVX instructions.
655 def u8imm : Operand<i8> {
656 let PrintMethod = "printU8Imm";
657 let ParserMatchClass = ImmUnsignedi8AsmOperand;
658 let OperandType = "OPERAND_IMMEDIATE";
661 // 32-bit immediate but only 8-bits are significant and they are unsigned.
662 // Used by some SSE/AVX instructions that use intrinsics.
663 def i32u8imm : Operand<i32> {
664 let PrintMethod = "printU8Imm";
665 let ParserMatchClass = ImmUnsignedi8AsmOperand;
666 let OperandType = "OPERAND_IMMEDIATE";
669 // 64-bits but only 32 bits are significant, and those bits are treated as being
671 def i64i32imm_pcrel : Operand<i64> {
672 let PrintMethod = "printPCRelImm";
673 let ParserMatchClass = X86AbsMemAsmOperand;
674 let OperandType = "OPERAND_PCREL";
677 def lea64_32mem : Operand<i32> {
678 let PrintMethod = "printanymem";
679 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
680 let ParserMatchClass = X86MemAsmOperand;
683 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
684 def lea64mem : Operand<i64> {
685 let PrintMethod = "printanymem";
686 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
687 let ParserMatchClass = X86MemAsmOperand;
691 //===----------------------------------------------------------------------===//
692 // X86 Complex Pattern Definitions.
695 // Define X86 specific addressing mode.
696 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
697 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
698 [add, sub, mul, X86mul_imm, shl, or, frameindex],
700 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
701 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
702 [add, sub, mul, X86mul_imm, shl, or,
703 frameindex, X86WrapperRIP],
706 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
707 [tglobaltlsaddr], []>;
709 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
710 [tglobaltlsaddr], []>;
712 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
713 [add, sub, mul, X86mul_imm, shl, or, frameindex,
716 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
717 [tglobaltlsaddr], []>;
719 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
720 [tglobaltlsaddr], []>;
722 //===----------------------------------------------------------------------===//
723 // X86 Instruction Predicate Definitions.
724 def HasCMov : Predicate<"Subtarget->hasCMov()">;
725 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
727 def HasMMX : Predicate<"Subtarget->hasMMX()">;
728 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
729 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
730 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
731 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
732 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
733 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
734 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
735 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
736 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
737 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
738 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
739 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
740 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
741 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
742 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
743 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
744 def HasAVX : Predicate<"Subtarget->hasAVX()">;
745 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
746 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
747 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
748 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
749 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
750 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
751 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
752 def HasCDI : Predicate<"Subtarget->hasCDI()">;
753 def HasPFI : Predicate<"Subtarget->hasPFI()">;
754 def HasERI : Predicate<"Subtarget->hasERI()">;
755 def HasDQI : Predicate<"Subtarget->hasDQI()">;
756 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
757 def HasBWI : Predicate<"Subtarget->hasBWI()">;
758 def HasVLX : Predicate<"Subtarget->hasVLX()">,
759 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
760 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
762 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
763 def HasAES : Predicate<"Subtarget->hasAES()">;
764 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
765 def HasFMA : Predicate<"Subtarget->hasFMA()">;
766 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
767 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
768 def HasXOP : Predicate<"Subtarget->hasXOP()">;
769 def HasTBM : Predicate<"Subtarget->hasTBM()">;
770 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
771 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
772 def HasF16C : Predicate<"Subtarget->hasF16C()">;
773 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
774 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
775 def HasBMI : Predicate<"Subtarget->hasBMI()">;
776 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
777 def HasRTM : Predicate<"Subtarget->hasRTM()">;
778 def HasHLE : Predicate<"Subtarget->hasHLE()">;
779 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
780 def HasADX : Predicate<"Subtarget->hasADX()">;
781 def HasSHA : Predicate<"Subtarget->hasSHA()">;
782 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
783 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
784 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
785 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
786 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
787 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
788 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
789 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
790 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
791 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
792 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
793 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
794 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
795 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
796 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
797 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
798 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
799 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
800 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
801 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
802 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
803 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
804 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
805 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
806 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
807 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
808 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
809 "TM.getCodeModel() != CodeModel::Kernel">;
810 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
811 "TM.getCodeModel() == CodeModel::Kernel">;
812 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
813 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
814 def OptForSize : Predicate<"OptForSize">;
815 def OptForSpeed : Predicate<"!OptForSize">;
816 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
817 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
818 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
819 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
820 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
822 //===----------------------------------------------------------------------===//
823 // X86 Instruction Format Definitions.
826 include "X86InstrFormats.td"
828 //===----------------------------------------------------------------------===//
829 // Pattern fragments.
832 // X86 specific condition code. These correspond to CondCode in
833 // X86InstrInfo.h. They must be kept in synch.
834 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
835 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
836 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
837 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
838 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
839 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
840 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
841 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
842 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
843 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
844 def X86_COND_NO : PatLeaf<(i8 10)>;
845 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
846 def X86_COND_NS : PatLeaf<(i8 12)>;
847 def X86_COND_O : PatLeaf<(i8 13)>;
848 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
849 def X86_COND_S : PatLeaf<(i8 15)>;
851 // Predicate used to help when pattern matching LZCNT/TZCNT.
852 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
853 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
856 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
857 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
858 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
859 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
862 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
865 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
867 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
869 def i64immZExt32SExt8 : ImmLeaf<i64, [{
870 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
873 // Helper fragments for loads.
874 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
875 // known to be 32-bit aligned or better. Ditto for i8 to i16.
876 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
877 LoadSDNode *LD = cast<LoadSDNode>(N);
878 ISD::LoadExtType ExtType = LD->getExtensionType();
879 if (ExtType == ISD::NON_EXTLOAD)
881 if (ExtType == ISD::EXTLOAD)
882 return LD->getAlignment() >= 2 && !LD->isVolatile();
886 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
887 LoadSDNode *LD = cast<LoadSDNode>(N);
888 ISD::LoadExtType ExtType = LD->getExtensionType();
889 if (ExtType == ISD::EXTLOAD)
890 return LD->getAlignment() >= 2 && !LD->isVolatile();
894 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
895 LoadSDNode *LD = cast<LoadSDNode>(N);
896 ISD::LoadExtType ExtType = LD->getExtensionType();
897 if (ExtType == ISD::NON_EXTLOAD)
899 if (ExtType == ISD::EXTLOAD)
900 return LD->getAlignment() >= 4 && !LD->isVolatile();
904 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
905 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
906 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
907 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
908 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
910 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
911 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
912 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
913 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
914 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
915 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
917 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
918 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
919 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
920 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
921 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
922 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
923 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
924 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
925 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
926 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
928 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
929 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
930 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
931 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
932 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
933 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
934 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
935 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
936 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
937 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
940 // An 'and' node with a single use.
941 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
942 return N->hasOneUse();
944 // An 'srl' node with a single use.
945 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
946 return N->hasOneUse();
948 // An 'trunc' node with a single use.
949 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
950 return N->hasOneUse();
953 //===----------------------------------------------------------------------===//
958 let hasSideEffects = 0, SchedRW = [WriteZero] in {
959 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
960 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
961 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
962 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
963 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
967 // Constructing a stack frame.
968 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
969 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
971 let SchedRW = [WriteALU] in {
972 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
973 def LEAVE : I<0xC9, RawFrm,
974 (outs), (ins), "leave", [], IIC_LEAVE>,
975 Requires<[Not64BitMode]>;
977 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
978 def LEAVE64 : I<0xC9, RawFrm,
979 (outs), (ins), "leave", [], IIC_LEAVE>,
980 Requires<[In64BitMode]>;
983 //===----------------------------------------------------------------------===//
984 // Miscellaneous Instructions.
987 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
988 let mayLoad = 1, SchedRW = [WriteLoad] in {
989 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
990 IIC_POP_REG16>, OpSize16;
991 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
992 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
993 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
994 IIC_POP_REG>, OpSize16;
995 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
996 IIC_POP_MEM>, OpSize16;
997 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
998 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
999 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1000 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1001 } // mayLoad, SchedRW
1003 let mayStore = 1, SchedRW = [WriteStore] in {
1004 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1005 IIC_PUSH_REG>, OpSize16;
1006 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1007 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1008 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1009 IIC_PUSH_REG>, OpSize16;
1010 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1011 IIC_PUSH_MEM>, OpSize16;
1012 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1013 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1014 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1015 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1017 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1018 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1019 Requires<[Not64BitMode]>;
1020 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1021 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1022 Requires<[Not64BitMode]>;
1023 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1024 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1025 Requires<[Not64BitMode]>;
1026 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1027 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1028 Requires<[Not64BitMode]>;
1029 } // mayStore, SchedRW
1032 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1033 SchedRW = [WriteLoad] in {
1034 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1036 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1037 OpSize32, Requires<[Not64BitMode]>;
1040 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1041 SchedRW = [WriteStore] in {
1042 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1044 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1045 OpSize32, Requires<[Not64BitMode]>;
1048 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1049 let mayLoad = 1, SchedRW = [WriteLoad] in {
1050 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1051 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1052 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1053 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1054 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1055 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1056 } // mayLoad, SchedRW
1057 let mayStore = 1, SchedRW = [WriteStore] in {
1058 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1059 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1060 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1061 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1062 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1063 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1064 } // mayStore, SchedRW
1067 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1068 SchedRW = [WriteStore] in {
1069 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1070 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1071 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1072 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1073 Requires<[In64BitMode]>;
1074 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1075 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1076 Requires<[In64BitMode]>;
1079 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1080 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1081 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1082 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1083 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1084 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1086 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1087 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1088 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1089 OpSize32, Requires<[Not64BitMode]>;
1090 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1091 OpSize16, Requires<[Not64BitMode]>;
1093 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1094 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1095 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1096 OpSize32, Requires<[Not64BitMode]>;
1097 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1098 OpSize16, Requires<[Not64BitMode]>;
1101 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1102 // GR32 = bswap GR32
1103 def BSWAP32r : I<0xC8, AddRegFrm,
1104 (outs GR32:$dst), (ins GR32:$src),
1106 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1108 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1110 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1111 } // Constraints = "$src = $dst", SchedRW
1113 // Bit scan instructions.
1114 let Defs = [EFLAGS] in {
1115 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1116 "bsf{w}\t{$src, $dst|$dst, $src}",
1117 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1118 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1119 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1120 "bsf{w}\t{$src, $dst|$dst, $src}",
1121 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1122 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1123 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1124 "bsf{l}\t{$src, $dst|$dst, $src}",
1125 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1126 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1127 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1128 "bsf{l}\t{$src, $dst|$dst, $src}",
1129 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1130 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1131 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1132 "bsf{q}\t{$src, $dst|$dst, $src}",
1133 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1134 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1135 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1136 "bsf{q}\t{$src, $dst|$dst, $src}",
1137 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1138 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1140 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1141 "bsr{w}\t{$src, $dst|$dst, $src}",
1142 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1143 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1144 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1145 "bsr{w}\t{$src, $dst|$dst, $src}",
1146 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1147 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1148 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1149 "bsr{l}\t{$src, $dst|$dst, $src}",
1150 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1151 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1152 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1153 "bsr{l}\t{$src, $dst|$dst, $src}",
1154 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1155 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1156 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1157 "bsr{q}\t{$src, $dst|$dst, $src}",
1158 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1159 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1160 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1161 "bsr{q}\t{$src, $dst|$dst, $src}",
1162 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1163 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1164 } // Defs = [EFLAGS]
1166 let SchedRW = [WriteMicrocoded] in {
1167 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1168 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1169 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1170 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1171 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1172 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1173 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1174 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1175 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1176 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1179 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1180 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1181 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1182 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1183 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1184 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1185 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1186 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1187 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1188 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1189 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1190 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1191 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1193 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1194 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1195 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1196 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1197 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1198 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1199 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1200 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1201 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1202 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1203 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1204 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1205 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1207 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1208 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1209 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1210 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1211 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1212 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1213 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1214 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1215 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1216 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1220 //===----------------------------------------------------------------------===//
1221 // Move Instructions.
1223 let SchedRW = [WriteMove] in {
1224 let hasSideEffects = 0 in {
1225 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1226 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1227 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1228 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1229 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1230 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1231 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1232 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1235 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1236 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1237 "mov{b}\t{$src, $dst|$dst, $src}",
1238 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1239 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1240 "mov{w}\t{$src, $dst|$dst, $src}",
1241 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1242 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1243 "mov{l}\t{$src, $dst|$dst, $src}",
1244 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1245 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1246 "mov{q}\t{$src, $dst|$dst, $src}",
1247 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1249 let isReMaterializable = 1 in {
1250 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1251 "movabs{q}\t{$src, $dst|$dst, $src}",
1252 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1255 // Longer forms that use a ModR/M byte. Needed for disassembler
1256 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1257 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1258 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1259 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1260 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1261 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1262 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1266 let SchedRW = [WriteStore] in {
1267 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1268 "mov{b}\t{$src, $dst|$dst, $src}",
1269 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1270 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1271 "mov{w}\t{$src, $dst|$dst, $src}",
1272 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1273 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1274 "mov{l}\t{$src, $dst|$dst, $src}",
1275 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1276 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1277 "mov{q}\t{$src, $dst|$dst, $src}",
1278 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1281 let hasSideEffects = 0 in {
1283 /// Memory offset versions of moves. The immediate is an address mode sized
1284 /// offset from the segment base.
1285 let SchedRW = [WriteALU] in {
1286 let mayLoad = 1 in {
1288 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1289 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1292 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1293 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1296 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1297 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1300 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1301 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1305 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1306 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1308 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1309 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1312 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1313 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1316 let mayStore = 1 in {
1318 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1319 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1321 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1322 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1325 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1326 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1329 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1330 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1334 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1335 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1337 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1338 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1341 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1342 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1347 // These forms all have full 64-bit absolute addresses in their instructions
1348 // and use the movabs mnemonic to indicate this specific form.
1349 let mayLoad = 1 in {
1351 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1352 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1354 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1355 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1357 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1358 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1361 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1362 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1365 let mayStore = 1 in {
1367 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1368 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1370 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1371 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1373 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1374 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1377 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1378 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1380 } // hasSideEffects = 0
1382 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1383 SchedRW = [WriteMove] in {
1384 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1385 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1386 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1387 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1388 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1389 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1390 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1391 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1394 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1395 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1396 "mov{b}\t{$src, $dst|$dst, $src}",
1397 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1398 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1399 "mov{w}\t{$src, $dst|$dst, $src}",
1400 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1401 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1402 "mov{l}\t{$src, $dst|$dst, $src}",
1403 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1404 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1405 "mov{q}\t{$src, $dst|$dst, $src}",
1406 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1409 let SchedRW = [WriteStore] in {
1410 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1411 "mov{b}\t{$src, $dst|$dst, $src}",
1412 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1413 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1414 "mov{w}\t{$src, $dst|$dst, $src}",
1415 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1416 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1417 "mov{l}\t{$src, $dst|$dst, $src}",
1418 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1419 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1420 "mov{q}\t{$src, $dst|$dst, $src}",
1421 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1424 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1425 // that they can be used for copying and storing h registers, which can't be
1426 // encoded when a REX prefix is present.
1427 let isCodeGenOnly = 1 in {
1428 let hasSideEffects = 0 in
1429 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1430 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1431 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1433 let mayStore = 1, hasSideEffects = 0 in
1434 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1435 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1436 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1437 IIC_MOV_MEM>, Sched<[WriteStore]>;
1438 let mayLoad = 1, hasSideEffects = 0,
1439 canFoldAsLoad = 1, isReMaterializable = 1 in
1440 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1441 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1442 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1443 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1447 // Condition code ops, incl. set if equal/not equal/...
1448 let SchedRW = [WriteALU] in {
1449 let Defs = [EFLAGS], Uses = [AH] in
1450 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1451 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1452 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1453 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1454 IIC_AHF>; // AH = flags
1457 //===----------------------------------------------------------------------===//
1458 // Bit tests instructions: BT, BTS, BTR, BTC.
1460 let Defs = [EFLAGS] in {
1461 let SchedRW = [WriteALU] in {
1462 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1463 "bt{w}\t{$src2, $src1|$src1, $src2}",
1464 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1466 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1467 "bt{l}\t{$src2, $src1|$src1, $src2}",
1468 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1470 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1471 "bt{q}\t{$src2, $src1|$src1, $src2}",
1472 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1475 // Unlike with the register+register form, the memory+register form of the
1476 // bt instruction does not ignore the high bits of the index. From ISel's
1477 // perspective, this is pretty bizarre. Make these instructions disassembly
1480 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1481 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1482 "bt{w}\t{$src2, $src1|$src1, $src2}",
1483 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1484 // (implicit EFLAGS)]
1486 >, OpSize16, TB, Requires<[FastBTMem]>;
1487 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1488 "bt{l}\t{$src2, $src1|$src1, $src2}",
1489 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1490 // (implicit EFLAGS)]
1492 >, OpSize32, TB, Requires<[FastBTMem]>;
1493 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1494 "bt{q}\t{$src2, $src1|$src1, $src2}",
1495 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1496 // (implicit EFLAGS)]
1501 let SchedRW = [WriteALU] in {
1502 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1503 "bt{w}\t{$src2, $src1|$src1, $src2}",
1504 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1505 IIC_BT_RI>, OpSize16, TB;
1506 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1507 "bt{l}\t{$src2, $src1|$src1, $src2}",
1508 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1509 IIC_BT_RI>, OpSize32, TB;
1510 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1511 "bt{q}\t{$src2, $src1|$src1, $src2}",
1512 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1516 // Note that these instructions don't need FastBTMem because that
1517 // only applies when the other operand is in a register. When it's
1518 // an immediate, bt is still fast.
1519 let SchedRW = [WriteALU] in {
1520 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1521 "bt{w}\t{$src2, $src1|$src1, $src2}",
1522 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1523 ], IIC_BT_MI>, OpSize16, TB;
1524 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1525 "bt{l}\t{$src2, $src1|$src1, $src2}",
1526 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1527 ], IIC_BT_MI>, OpSize32, TB;
1528 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1529 "bt{q}\t{$src2, $src1|$src1, $src2}",
1530 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1531 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1534 let hasSideEffects = 0 in {
1535 let SchedRW = [WriteALU] in {
1536 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1537 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1539 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1540 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1542 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1543 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1546 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1547 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1548 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1550 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1551 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1553 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1554 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1557 let SchedRW = [WriteALU] in {
1558 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1559 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1561 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1562 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1564 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1565 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1568 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1569 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1570 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1572 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1573 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1575 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1576 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1579 let SchedRW = [WriteALU] in {
1580 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1581 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1583 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1584 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1586 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1587 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1590 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1591 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1592 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1594 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1595 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1597 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1598 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1601 let SchedRW = [WriteALU] in {
1602 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1603 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1605 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1606 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1608 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1609 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1612 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1613 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1614 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1616 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1617 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1619 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1620 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1623 let SchedRW = [WriteALU] in {
1624 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1625 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1627 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1628 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1630 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1631 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1634 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1635 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1636 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1638 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1639 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1641 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1642 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1645 let SchedRW = [WriteALU] in {
1646 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1647 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1649 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1650 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1652 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1653 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1656 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1657 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1658 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1660 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1661 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1663 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1664 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1666 } // hasSideEffects = 0
1667 } // Defs = [EFLAGS]
1670 //===----------------------------------------------------------------------===//
1674 // Atomic swap. These are just normal xchg instructions. But since a memory
1675 // operand is referenced, the atomicity is ensured.
1676 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1677 InstrItinClass itin> {
1678 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1679 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1680 (ins GR8:$val, i8mem:$ptr),
1681 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1684 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1686 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1687 (ins GR16:$val, i16mem:$ptr),
1688 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1691 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1693 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1694 (ins GR32:$val, i32mem:$ptr),
1695 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1698 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1700 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1701 (ins GR64:$val, i64mem:$ptr),
1702 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1705 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1710 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1712 // Swap between registers.
1713 let SchedRW = [WriteALU] in {
1714 let Constraints = "$val = $dst" in {
1715 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1716 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1717 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1718 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1720 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1721 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1723 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1724 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1727 // Swap between EAX and other registers.
1728 let Uses = [AX], Defs = [AX] in
1729 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1730 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1731 let Uses = [EAX], Defs = [EAX] in
1732 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1733 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1734 OpSize32, Requires<[Not64BitMode]>;
1735 let Uses = [EAX], Defs = [EAX] in
1736 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1737 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1738 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1739 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1740 OpSize32, Requires<[In64BitMode]>;
1741 let Uses = [RAX], Defs = [RAX] in
1742 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1743 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1746 let SchedRW = [WriteALU] in {
1747 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1748 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1749 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1750 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1752 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1753 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1755 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1756 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1759 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1760 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1761 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1762 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1763 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1765 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1766 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1768 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1769 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1773 let SchedRW = [WriteALU] in {
1774 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1775 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1776 IIC_CMPXCHG_REG8>, TB;
1777 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1778 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1779 IIC_CMPXCHG_REG>, TB, OpSize16;
1780 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1781 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1782 IIC_CMPXCHG_REG>, TB, OpSize32;
1783 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1784 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1785 IIC_CMPXCHG_REG>, TB;
1788 let SchedRW = [WriteALULd, WriteRMW] in {
1789 let mayLoad = 1, mayStore = 1 in {
1790 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1791 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1792 IIC_CMPXCHG_MEM8>, TB;
1793 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1794 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1795 IIC_CMPXCHG_MEM>, TB, OpSize16;
1796 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1797 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1798 IIC_CMPXCHG_MEM>, TB, OpSize32;
1799 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1800 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1801 IIC_CMPXCHG_MEM>, TB;
1804 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1805 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1806 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1808 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1809 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1810 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1811 TB, Requires<[HasCmpxchg16b]>;
1815 // Lock instruction prefix
1816 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1818 // Rex64 instruction prefix
1819 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1820 Requires<[In64BitMode]>;
1822 // Data16 instruction prefix
1823 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1825 // Repeat string operation instruction prefixes
1826 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1827 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1828 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1829 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1830 // Repeat while not equal (used with CMPS and SCAS)
1831 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1835 // String manipulation instructions
1836 let SchedRW = [WriteMicrocoded] in {
1837 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1838 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1839 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1840 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1841 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1842 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1843 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1844 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1845 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1846 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1847 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1848 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1849 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1852 let SchedRW = [WriteSystem] in {
1853 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1854 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1855 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1856 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1857 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1858 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1859 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1860 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1863 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1864 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1865 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1866 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1867 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1868 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1869 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1870 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1874 // Flag instructions
1875 let SchedRW = [WriteALU] in {
1876 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1877 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1878 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1879 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1880 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1881 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1882 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1884 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1887 // Table lookup instructions
1888 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1891 let SchedRW = [WriteMicrocoded] in {
1892 // ASCII Adjust After Addition
1893 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1894 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1895 Requires<[Not64BitMode]>;
1897 // ASCII Adjust AX Before Division
1898 // sets AL, AH and EFLAGS and uses AL and AH
1899 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1900 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1902 // ASCII Adjust AX After Multiply
1903 // sets AL, AH and EFLAGS and uses AL
1904 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1905 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1907 // ASCII Adjust AL After Subtraction - sets
1908 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1909 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1910 Requires<[Not64BitMode]>;
1912 // Decimal Adjust AL after Addition
1913 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1914 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1915 Requires<[Not64BitMode]>;
1917 // Decimal Adjust AL after Subtraction
1918 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1919 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1920 Requires<[Not64BitMode]>;
1923 let SchedRW = [WriteSystem] in {
1924 // Check Array Index Against Bounds
1925 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1926 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1927 Requires<[Not64BitMode]>;
1928 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1929 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1930 Requires<[Not64BitMode]>;
1932 // Adjust RPL Field of Segment Selector
1933 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1934 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1935 Requires<[Not64BitMode]>;
1936 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1937 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1938 Requires<[Not64BitMode]>;
1941 //===----------------------------------------------------------------------===//
1942 // MOVBE Instructions
1944 let Predicates = [HasMOVBE] in {
1945 let SchedRW = [WriteALULd] in {
1946 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1947 "movbe{w}\t{$src, $dst|$dst, $src}",
1948 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1950 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1951 "movbe{l}\t{$src, $dst|$dst, $src}",
1952 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1954 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1955 "movbe{q}\t{$src, $dst|$dst, $src}",
1956 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1959 let SchedRW = [WriteStore] in {
1960 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1961 "movbe{w}\t{$src, $dst|$dst, $src}",
1962 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1964 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1965 "movbe{l}\t{$src, $dst|$dst, $src}",
1966 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1968 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1969 "movbe{q}\t{$src, $dst|$dst, $src}",
1970 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1975 //===----------------------------------------------------------------------===//
1976 // RDRAND Instruction
1978 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1979 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1981 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1982 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1984 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1985 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1987 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1990 //===----------------------------------------------------------------------===//
1991 // RDSEED Instruction
1993 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1994 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1996 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1997 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1999 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2000 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2002 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2005 //===----------------------------------------------------------------------===//
2006 // LZCNT Instruction
2008 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2009 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2010 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2011 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2013 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2014 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2015 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2016 (implicit EFLAGS)]>, XS, OpSize16;
2018 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2019 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2020 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2022 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2023 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2024 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2025 (implicit EFLAGS)]>, XS, OpSize32;
2027 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2028 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2029 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2031 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2032 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2033 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2034 (implicit EFLAGS)]>, XS;
2037 let Predicates = [HasLZCNT] in {
2038 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2039 (X86cmp GR16:$src, (i16 0))),
2040 (LZCNT16rr GR16:$src)>;
2041 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2042 (X86cmp GR32:$src, (i32 0))),
2043 (LZCNT32rr GR32:$src)>;
2044 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2045 (X86cmp GR64:$src, (i64 0))),
2046 (LZCNT64rr GR64:$src)>;
2047 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2048 (X86cmp GR16:$src, (i16 0))),
2049 (LZCNT16rr GR16:$src)>;
2050 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2051 (X86cmp GR32:$src, (i32 0))),
2052 (LZCNT32rr GR32:$src)>;
2053 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2054 (X86cmp GR64:$src, (i64 0))),
2055 (LZCNT64rr GR64:$src)>;
2057 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2058 (X86cmp (loadi16 addr:$src), (i16 0))),
2059 (LZCNT16rm addr:$src)>;
2060 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2061 (X86cmp (loadi32 addr:$src), (i32 0))),
2062 (LZCNT32rm addr:$src)>;
2063 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2064 (X86cmp (loadi64 addr:$src), (i64 0))),
2065 (LZCNT64rm addr:$src)>;
2066 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2067 (X86cmp (loadi16 addr:$src), (i16 0))),
2068 (LZCNT16rm addr:$src)>;
2069 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2070 (X86cmp (loadi32 addr:$src), (i32 0))),
2071 (LZCNT32rm addr:$src)>;
2072 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2073 (X86cmp (loadi64 addr:$src), (i64 0))),
2074 (LZCNT64rm addr:$src)>;
2077 //===----------------------------------------------------------------------===//
2080 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2081 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2082 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2083 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2085 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2086 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2087 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2088 (implicit EFLAGS)]>, XS, OpSize16;
2090 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2091 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2092 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2094 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2095 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2096 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2097 (implicit EFLAGS)]>, XS, OpSize32;
2099 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2100 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2101 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2103 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2104 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2105 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2106 (implicit EFLAGS)]>, XS;
2109 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2110 RegisterClass RC, X86MemOperand x86memop> {
2111 let hasSideEffects = 0 in {
2112 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2113 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2116 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2117 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2122 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2123 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2124 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2125 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2126 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2127 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2128 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2131 //===----------------------------------------------------------------------===//
2132 // Pattern fragments to auto generate BMI instructions.
2133 //===----------------------------------------------------------------------===//
2135 let Predicates = [HasBMI] in {
2136 // FIXME: patterns for the load versions are not implemented
2137 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2138 (BLSR32rr GR32:$src)>;
2139 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2140 (BLSR64rr GR64:$src)>;
2142 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2143 (BLSMSK32rr GR32:$src)>;
2144 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2145 (BLSMSK64rr GR64:$src)>;
2147 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2148 (BLSI32rr GR32:$src)>;
2149 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2150 (BLSI64rr GR64:$src)>;
2153 let Predicates = [HasBMI] in {
2154 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2155 (X86cmp GR16:$src, (i16 0))),
2156 (TZCNT16rr GR16:$src)>;
2157 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2158 (X86cmp GR32:$src, (i32 0))),
2159 (TZCNT32rr GR32:$src)>;
2160 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2161 (X86cmp GR64:$src, (i64 0))),
2162 (TZCNT64rr GR64:$src)>;
2163 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2164 (X86cmp GR16:$src, (i16 0))),
2165 (TZCNT16rr GR16:$src)>;
2166 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2167 (X86cmp GR32:$src, (i32 0))),
2168 (TZCNT32rr GR32:$src)>;
2169 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2170 (X86cmp GR64:$src, (i64 0))),
2171 (TZCNT64rr GR64:$src)>;
2173 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2174 (X86cmp (loadi16 addr:$src), (i16 0))),
2175 (TZCNT16rm addr:$src)>;
2176 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2177 (X86cmp (loadi32 addr:$src), (i32 0))),
2178 (TZCNT32rm addr:$src)>;
2179 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2180 (X86cmp (loadi64 addr:$src), (i64 0))),
2181 (TZCNT64rm addr:$src)>;
2182 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2183 (X86cmp (loadi16 addr:$src), (i16 0))),
2184 (TZCNT16rm addr:$src)>;
2185 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2186 (X86cmp (loadi32 addr:$src), (i32 0))),
2187 (TZCNT32rm addr:$src)>;
2188 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2189 (X86cmp (loadi64 addr:$src), (i64 0))),
2190 (TZCNT64rm addr:$src)>;
2194 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2195 X86MemOperand x86memop, Intrinsic Int,
2197 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2198 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2201 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2202 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2203 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2204 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2207 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2208 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2209 int_x86_bmi_bextr_32, loadi32>;
2210 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2211 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2214 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2215 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2216 int_x86_bmi_bzhi_32, loadi32>;
2217 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2218 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2222 def CountTrailingOnes : SDNodeXForm<imm, [{
2223 // Count the trailing ones in the immediate.
2224 return getI8Imm(countTrailingOnes(N->getZExtValue()));
2227 def BZHIMask : ImmLeaf<i64, [{
2228 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2231 let Predicates = [HasBMI2] in {
2232 def : Pat<(and GR64:$src, BZHIMask:$mask),
2233 (BZHI64rr GR64:$src,
2234 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2235 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2237 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2238 (BZHI32rr GR32:$src,
2239 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2241 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2242 (BZHI32rm addr:$src,
2243 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2245 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2246 (BZHI64rr GR64:$src,
2247 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2249 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2250 (BZHI64rm addr:$src,
2251 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2254 let Predicates = [HasBMI] in {
2255 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2256 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2257 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2258 (BEXTR32rm addr:$src1, GR32:$src2)>;
2259 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2260 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2261 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2262 (BEXTR64rm addr:$src1, GR64:$src2)>;
2265 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2266 X86MemOperand x86memop, Intrinsic Int,
2268 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2269 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2270 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2272 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2273 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2274 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2277 let Predicates = [HasBMI2] in {
2278 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2279 int_x86_bmi_pdep_32, loadi32>, T8XD;
2280 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2281 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2282 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2283 int_x86_bmi_pext_32, loadi32>, T8XS;
2284 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2285 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2288 //===----------------------------------------------------------------------===//
2291 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2293 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2294 X86MemOperand x86memop, PatFrag ld_frag,
2295 Intrinsic Int, Operand immtype,
2296 SDPatternOperator immoperator> {
2297 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2298 !strconcat(OpcodeStr,
2299 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2300 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2302 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2303 (ins x86memop:$src1, immtype:$cntl),
2304 !strconcat(OpcodeStr,
2305 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2306 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2310 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2311 int_x86_tbm_bextri_u32, i32imm, imm>;
2312 let ImmT = Imm32S in
2313 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2314 int_x86_tbm_bextri_u64, i64i32imm,
2315 i64immSExt32>, VEX_W;
2317 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2318 RegisterClass RC, string OpcodeStr,
2319 X86MemOperand x86memop, PatFrag ld_frag> {
2320 let hasSideEffects = 0 in {
2321 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2322 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2325 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2326 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2331 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2332 Format FormReg, Format FormMem> {
2333 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2335 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2339 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2340 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2341 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2342 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2343 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2344 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2345 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2346 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2347 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2350 //===----------------------------------------------------------------------===//
2351 // Pattern fragments to auto generate TBM instructions.
2352 //===----------------------------------------------------------------------===//
2354 let Predicates = [HasTBM] in {
2355 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2356 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2357 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2358 (BEXTRI32mi addr:$src1, imm:$src2)>;
2359 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2360 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2361 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2362 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2364 // FIXME: patterns for the load versions are not implemented
2365 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2366 (BLCFILL32rr GR32:$src)>;
2367 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2368 (BLCFILL64rr GR64:$src)>;
2370 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2371 (BLCI32rr GR32:$src)>;
2372 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2373 (BLCI64rr GR64:$src)>;
2375 // Extra patterns because opt can optimize the above patterns to this.
2376 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2377 (BLCI32rr GR32:$src)>;
2378 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2379 (BLCI64rr GR64:$src)>;
2381 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2382 (BLCIC32rr GR32:$src)>;
2383 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2384 (BLCIC64rr GR64:$src)>;
2386 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2387 (BLCMSK32rr GR32:$src)>;
2388 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2389 (BLCMSK64rr GR64:$src)>;
2391 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2392 (BLCS32rr GR32:$src)>;
2393 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2394 (BLCS64rr GR64:$src)>;
2396 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2397 (BLSFILL32rr GR32:$src)>;
2398 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2399 (BLSFILL64rr GR64:$src)>;
2401 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2402 (BLSIC32rr GR32:$src)>;
2403 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2404 (BLSIC64rr GR64:$src)>;
2406 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2407 (T1MSKC32rr GR32:$src)>;
2408 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2409 (T1MSKC64rr GR64:$src)>;
2411 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2412 (TZMSK32rr GR32:$src)>;
2413 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2414 (TZMSK64rr GR64:$src)>;
2417 //===----------------------------------------------------------------------===//
2418 // Memory Instructions
2421 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2422 "clflushopt\t$src", []>, PD;
2423 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2424 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2427 //===----------------------------------------------------------------------===//
2429 //===----------------------------------------------------------------------===//
2431 include "X86InstrArithmetic.td"
2432 include "X86InstrCMovSetCC.td"
2433 include "X86InstrExtension.td"
2434 include "X86InstrControl.td"
2435 include "X86InstrShiftRotate.td"
2437 // X87 Floating Point Stack.
2438 include "X86InstrFPStack.td"
2440 // SIMD support (SSE, MMX and AVX)
2441 include "X86InstrFragmentsSIMD.td"
2443 // FMA - Fused Multiply-Add support (requires FMA)
2444 include "X86InstrFMA.td"
2447 include "X86InstrXOP.td"
2449 // SSE, MMX and 3DNow! vector support.
2450 include "X86InstrSSE.td"
2451 include "X86InstrAVX512.td"
2452 include "X86InstrMMX.td"
2453 include "X86Instr3DNow.td"
2455 include "X86InstrVMX.td"
2456 include "X86InstrSVM.td"
2458 include "X86InstrTSX.td"
2459 include "X86InstrSGX.td"
2461 // System instructions.
2462 include "X86InstrSystem.td"
2464 // Compiler Pseudo Instructions and Pat Patterns
2465 include "X86InstrCompiler.td"
2467 //===----------------------------------------------------------------------===//
2468 // Assembler Mnemonic Aliases
2469 //===----------------------------------------------------------------------===//
2471 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2472 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2473 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2475 def : MnemonicAlias<"cbw", "cbtw", "att">;
2476 def : MnemonicAlias<"cwde", "cwtl", "att">;
2477 def : MnemonicAlias<"cwd", "cwtd", "att">;
2478 def : MnemonicAlias<"cdq", "cltd", "att">;
2479 def : MnemonicAlias<"cdqe", "cltq", "att">;
2480 def : MnemonicAlias<"cqo", "cqto", "att">;
2482 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2483 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2484 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2486 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2487 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2489 def : MnemonicAlias<"loopz", "loope", "att">;
2490 def : MnemonicAlias<"loopnz", "loopne", "att">;
2492 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2493 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2494 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2495 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2496 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2497 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2498 def : MnemonicAlias<"popfd", "popfl", "att">;
2500 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2501 // all modes. However: "push (addr)" and "push $42" should default to
2502 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2503 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2504 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2505 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2506 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2507 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2508 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2509 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2511 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2512 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2513 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2514 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2515 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2516 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2518 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2519 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2520 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2521 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2523 def : MnemonicAlias<"repe", "rep", "att">;
2524 def : MnemonicAlias<"repz", "rep", "att">;
2525 def : MnemonicAlias<"repnz", "repne", "att">;
2527 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2528 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2529 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2531 def : MnemonicAlias<"salb", "shlb", "att">;
2532 def : MnemonicAlias<"salw", "shlw", "att">;
2533 def : MnemonicAlias<"sall", "shll", "att">;
2534 def : MnemonicAlias<"salq", "shlq", "att">;
2536 def : MnemonicAlias<"smovb", "movsb", "att">;
2537 def : MnemonicAlias<"smovw", "movsw", "att">;
2538 def : MnemonicAlias<"smovl", "movsl", "att">;
2539 def : MnemonicAlias<"smovq", "movsq", "att">;
2541 def : MnemonicAlias<"ud2a", "ud2", "att">;
2542 def : MnemonicAlias<"verrw", "verr", "att">;
2544 // System instruction aliases.
2545 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2546 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2547 def : MnemonicAlias<"sysret", "sysretl", "att">;
2548 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2550 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2551 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2552 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2553 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2554 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2555 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2556 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2557 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2558 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2559 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2560 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2561 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2564 // Floating point stack aliases.
2565 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2566 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2567 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2568 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2569 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2570 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2571 def : MnemonicAlias<"fildq", "fildll", "att">;
2572 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2573 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2574 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2575 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2576 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2577 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2578 def : MnemonicAlias<"fwait", "wait">;
2580 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2581 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2582 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2583 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2584 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2587 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2589 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2590 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2592 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2593 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2594 /// example "setz" -> "sete".
2595 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2597 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2598 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2599 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2600 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2601 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2602 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2603 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2604 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2605 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2606 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2608 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2609 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2610 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2611 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2614 // Aliases for set<CC>
2615 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2616 // Aliases for j<CC>
2617 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2618 // Aliases for cmov<CC>{w,l,q}
2619 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2620 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2621 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2622 // No size suffix for intel-style asm.
2623 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2626 //===----------------------------------------------------------------------===//
2627 // Assembler Instruction Aliases
2628 //===----------------------------------------------------------------------===//
2630 // aad/aam default to base 10 if no operand is specified.
2631 def : InstAlias<"aad", (AAD8i8 10)>;
2632 def : InstAlias<"aam", (AAM8i8 10)>;
2634 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2635 // Likewise for btc/btr/bts.
2636 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2637 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2638 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2639 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2640 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2641 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2642 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2643 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2646 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2647 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2648 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2649 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2651 // lods aliases. Accept the destination being omitted because it's implicit
2652 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2653 // in the destination.
2654 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2655 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2656 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2657 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2658 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2659 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2660 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2661 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2663 // stos aliases. Accept the source being omitted because it's implicit in
2664 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2666 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2667 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2668 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2669 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2670 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2671 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2672 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2673 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2675 // scas aliases. Accept the destination being omitted because it's implicit
2676 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2677 // in the destination.
2678 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2679 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2680 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2681 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2682 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2683 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2684 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2685 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2687 // div and idiv aliases for explicit A register.
2688 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2689 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2690 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2691 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2692 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2693 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2694 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2695 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2696 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2697 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2698 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2699 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2700 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2701 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2702 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2703 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2707 // Various unary fpstack operations default to operating on on ST1.
2708 // For example, "fxch" -> "fxch %st(1)"
2709 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2710 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2711 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2712 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2713 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2714 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2715 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2716 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2717 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2718 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2719 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2720 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2721 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2722 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2723 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2725 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2726 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2727 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2729 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2730 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2731 (Inst RST:$op), EmitAlias>;
2732 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2733 (Inst ST0), EmitAlias>;
2736 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2737 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2738 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2739 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2740 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2741 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2742 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2743 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2744 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2745 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2746 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2747 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2748 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2749 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2750 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2751 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2754 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2755 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2756 // solely because gas supports it.
2757 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2758 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2759 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2760 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2761 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2762 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2764 // We accept "fnstsw %eax" even though it only writes %ax.
2765 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2766 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2767 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2769 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2770 // this is compatible with what GAS does.
2771 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2772 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2773 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2774 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2775 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2776 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2777 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2778 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2780 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2781 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2782 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2783 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2784 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2785 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2788 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2789 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2790 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2791 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2792 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2793 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2794 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2796 // inb %dx -> inb %al, %dx
2797 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2798 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2799 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2800 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2801 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2802 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2805 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2806 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2807 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2808 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2809 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2810 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2811 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2812 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2813 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2815 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2816 // the move. All segment/mem forms are equivalent, this has the shortest
2818 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2819 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2821 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2822 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2824 // Match 'movq GR64, MMX' as an alias for movd.
2825 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2826 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2827 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2828 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2831 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2832 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2833 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2834 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2835 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2836 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2837 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2840 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2841 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2842 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2843 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2844 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2845 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2846 // Note: No GR32->GR64 movzx form.
2848 // outb %dx -> outb %al, %dx
2849 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2850 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2851 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2852 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2853 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2854 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2856 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2857 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2858 // errors, since its encoding is the most compact.
2859 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2861 // shld/shrd op,op -> shld op, op, CL
2862 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2863 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2864 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2865 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2866 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2867 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2869 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2870 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2871 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2872 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2873 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2874 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2876 /* FIXME: This is disabled because the asm matcher is currently incapable of
2877 * matching a fixed immediate like $1.
2878 // "shl X, $1" is an alias for "shl X".
2879 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2880 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2881 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2882 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2883 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2884 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2885 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2886 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2887 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2888 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2889 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2890 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2891 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2892 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2893 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2894 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2895 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2898 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2899 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2900 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2901 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2904 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2905 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2906 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2907 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2908 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2909 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2910 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2911 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2912 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2914 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2915 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2916 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2917 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2918 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2919 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2920 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2921 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2922 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2924 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2925 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2926 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2927 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2928 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2929 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2930 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;