1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
254 [SDNPHasChain, SDNPOutGlue]>;
256 //===----------------------------------------------------------------------===//
257 // X86 Operand Definitions.
260 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
261 // the index operand of an address, to conform to x86 encoding restrictions.
262 def ptr_rc_nosp : PointerLikeRegClass<1>;
264 // *mem - Operand definitions for the funky X86 addressing mode operands.
266 def X86MemAsmOperand : AsmOperandClass {
269 let RenderMethod = "addMemOperands" in {
270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
278 // Gather mem operands
279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
287 def X86AbsMemAsmOperand : AsmOperandClass {
289 let SuperClasses = [X86MemAsmOperand];
292 class X86MemOperand<string printMethod,
293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
294 let PrintMethod = printMethod;
295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
296 let ParserMatchClass = parserMatchClass;
297 let OperandType = "OPERAND_MEMORY";
300 // Gather mem operands
301 class X86VMemOperand<RegisterClass RC, string printMethod,
302 AsmOperandClass parserMatchClass>
303 : X86MemOperand<printMethod, parserMatchClass> {
304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
307 def anymem : X86MemOperand<"printanymem">;
309 def opaque32mem : X86MemOperand<"printopaquemem">;
310 def opaque48mem : X86MemOperand<"printopaquemem">;
311 def opaque80mem : X86MemOperand<"printopaquemem">;
312 def opaque512mem : X86MemOperand<"printopaquemem">;
314 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
315 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
316 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
317 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
318 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
319 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
320 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
321 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
322 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
323 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
324 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
325 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
326 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
328 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
330 // Gather mem operands
331 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
332 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
333 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
334 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
336 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
337 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
339 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
340 // plain GR64, so that it doesn't potentially require a REX prefix.
341 def i8mem_NOREX : Operand<i64> {
342 let PrintMethod = "printi8mem";
343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
344 let ParserMatchClass = X86Mem8AsmOperand;
345 let OperandType = "OPERAND_MEMORY";
348 // GPRs available for tailcall.
349 // It represents GR32_TC, GR64_TC or GR64_TCW64.
350 def ptr_rc_tailcall : PointerLikeRegClass<2>;
352 // Special i32mem for addresses of load folding tail calls. These are not
353 // allowed to use callee-saved registers since they must be scheduled
354 // after callee-saved register are popped.
355 def i32mem_TC : Operand<i32> {
356 let PrintMethod = "printi32mem";
357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
359 let ParserMatchClass = X86Mem32AsmOperand;
360 let OperandType = "OPERAND_MEMORY";
363 // Special i64mem for addresses of load folding tail calls. These are not
364 // allowed to use callee-saved registers since they must be scheduled
365 // after callee-saved register are popped.
366 def i64mem_TC : Operand<i64> {
367 let PrintMethod = "printi64mem";
368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
369 ptr_rc_tailcall, i32imm, i8imm);
370 let ParserMatchClass = X86Mem64AsmOperand;
371 let OperandType = "OPERAND_MEMORY";
374 let OperandType = "OPERAND_PCREL",
375 ParserMatchClass = X86AbsMemAsmOperand,
376 PrintMethod = "printPCRelImm" in {
377 def i32imm_pcrel : Operand<i32>;
378 def i16imm_pcrel : Operand<i16>;
380 // Branch targets have OtherVT type and print as pc-relative values.
381 def brtarget : Operand<OtherVT>;
382 def brtarget8 : Operand<OtherVT>;
386 // Special parsers to detect mode to disambiguate.
387 def X86AbsMem16AsmOperand : AsmOperandClass {
388 let Name = "AbsMem16";
389 let RenderMethod = "addAbsMemOperands";
390 let SuperClasses = [X86AbsMemAsmOperand];
393 def X86AbsMem32AsmOperand : AsmOperandClass {
394 let Name = "AbsMem32";
395 let RenderMethod = "addAbsMemOperands";
396 let SuperClasses = [X86AbsMemAsmOperand];
399 // Branch targets have OtherVT type and print as pc-relative values.
400 let OperandType = "OPERAND_PCREL",
401 PrintMethod = "printPCRelImm" in {
402 let ParserMatchClass = X86AbsMem16AsmOperand in
403 def brtarget16 : Operand<OtherVT>;
404 let ParserMatchClass = X86AbsMem32AsmOperand in
405 def brtarget32 : Operand<OtherVT>;
408 let RenderMethod = "addSrcIdxOperands" in {
409 def X86SrcIdx8Operand : AsmOperandClass {
410 let Name = "SrcIdx8";
411 let SuperClasses = [X86Mem8AsmOperand];
413 def X86SrcIdx16Operand : AsmOperandClass {
414 let Name = "SrcIdx16";
415 let SuperClasses = [X86Mem16AsmOperand];
417 def X86SrcIdx32Operand : AsmOperandClass {
418 let Name = "SrcIdx32";
419 let SuperClasses = [X86Mem32AsmOperand];
421 def X86SrcIdx64Operand : AsmOperandClass {
422 let Name = "SrcIdx64";
423 let SuperClasses = [X86Mem64AsmOperand];
425 } // RenderMethod = "addSrcIdxOperands"
427 let RenderMethod = "addDstIdxOperands" in {
428 def X86DstIdx8Operand : AsmOperandClass {
429 let Name = "DstIdx8";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86DstIdx16Operand : AsmOperandClass {
433 let Name = "DstIdx16";
434 let SuperClasses = [X86Mem16AsmOperand];
436 def X86DstIdx32Operand : AsmOperandClass {
437 let Name = "DstIdx32";
438 let SuperClasses = [X86Mem32AsmOperand];
440 def X86DstIdx64Operand : AsmOperandClass {
441 let Name = "DstIdx64";
442 let SuperClasses = [X86Mem64AsmOperand];
444 } // RenderMethod = "addDstIdxOperands"
446 let RenderMethod = "addMemOffsOperands" in {
447 def X86MemOffs16_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs16_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs16_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs16_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs32_8AsmOperand : AsmOperandClass {
460 let Name = "MemOffs32_8";
461 let SuperClasses = [X86Mem8AsmOperand];
463 def X86MemOffs32_16AsmOperand : AsmOperandClass {
464 let Name = "MemOffs32_16";
465 let SuperClasses = [X86Mem16AsmOperand];
467 def X86MemOffs32_32AsmOperand : AsmOperandClass {
468 let Name = "MemOffs32_32";
469 let SuperClasses = [X86Mem32AsmOperand];
471 def X86MemOffs32_64AsmOperand : AsmOperandClass {
472 let Name = "MemOffs32_64";
473 let SuperClasses = [X86Mem64AsmOperand];
475 def X86MemOffs64_8AsmOperand : AsmOperandClass {
476 let Name = "MemOffs64_8";
477 let SuperClasses = [X86Mem8AsmOperand];
479 def X86MemOffs64_16AsmOperand : AsmOperandClass {
480 let Name = "MemOffs64_16";
481 let SuperClasses = [X86Mem16AsmOperand];
483 def X86MemOffs64_32AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64_32";
485 let SuperClasses = [X86Mem32AsmOperand];
487 def X86MemOffs64_64AsmOperand : AsmOperandClass {
488 let Name = "MemOffs64_64";
489 let SuperClasses = [X86Mem64AsmOperand];
491 } // RenderMethod = "addMemOffsOperands"
493 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
494 : X86MemOperand<printMethod, parserMatchClass> {
495 let MIOperandInfo = (ops ptr_rc, i8imm);
498 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
499 : X86MemOperand<printMethod, parserMatchClass> {
500 let MIOperandInfo = (ops ptr_rc);
503 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
504 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
505 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
506 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
507 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
508 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
509 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
510 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
512 class X86MemOffsOperand<Operand immOperand, string printMethod,
513 AsmOperandClass parserMatchClass>
514 : X86MemOperand<printMethod, parserMatchClass> {
515 let MIOperandInfo = (ops immOperand, i8imm);
518 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
519 X86MemOffs16_8AsmOperand>;
520 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
521 X86MemOffs16_16AsmOperand>;
522 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
523 X86MemOffs16_32AsmOperand>;
524 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
525 X86MemOffs32_8AsmOperand>;
526 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
527 X86MemOffs32_16AsmOperand>;
528 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
529 X86MemOffs32_32AsmOperand>;
530 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
531 X86MemOffs32_64AsmOperand>;
532 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
533 X86MemOffs64_8AsmOperand>;
534 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
535 X86MemOffs64_16AsmOperand>;
536 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
537 X86MemOffs64_32AsmOperand>;
538 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
539 X86MemOffs64_64AsmOperand>;
541 def SSECC : Operand<i8> {
542 let PrintMethod = "printSSECC";
543 let OperandType = "OPERAND_IMMEDIATE";
546 def i8immZExt3 : ImmLeaf<i8, [{
547 return Imm >= 0 && Imm < 8;
550 def AVXCC : Operand<i8> {
551 let PrintMethod = "printAVXCC";
552 let OperandType = "OPERAND_IMMEDIATE";
555 def i8immZExt5 : ImmLeaf<i8, [{
556 return Imm >= 0 && Imm < 32;
559 class ImmSExtAsmOperandClass : AsmOperandClass {
560 let SuperClasses = [ImmAsmOperand];
561 let RenderMethod = "addImmOperands";
564 def X86GR32orGR64AsmOperand : AsmOperandClass {
565 let Name = "GR32orGR64";
568 def GR32orGR64 : RegisterOperand<GR32> {
569 let ParserMatchClass = X86GR32orGR64AsmOperand;
572 def AVX512RC : Operand<i32> {
573 let PrintMethod = "printRoundingControl";
574 let OperandType = "OPERAND_IMMEDIATE";
577 // Sign-extended immediate classes. We don't need to define the full lattice
578 // here because there is no instruction with an ambiguity between ImmSExti64i32
581 // The strange ranges come from the fact that the assembler always works with
582 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
583 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
586 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
587 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
588 let Name = "ImmSExti64i32";
591 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
592 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
593 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
594 let Name = "ImmSExti16i8";
595 let SuperClasses = [ImmSExti64i32AsmOperand];
598 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
599 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
600 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
601 let Name = "ImmSExti32i8";
605 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
606 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
607 let Name = "ImmSExti64i8";
608 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
609 ImmSExti64i32AsmOperand];
612 // Unsigned immediate used by SSE/AVX instructions
614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
615 def ImmUnsignedi8AsmOperand : AsmOperandClass {
616 let Name = "ImmUnsignedi8";
617 let RenderMethod = "addImmOperands";
620 // A couple of more descriptive operand definitions.
621 // 16-bits but only 8 bits are significant.
622 def i16i8imm : Operand<i16> {
623 let ParserMatchClass = ImmSExti16i8AsmOperand;
624 let OperandType = "OPERAND_IMMEDIATE";
626 // 32-bits but only 8 bits are significant.
627 def i32i8imm : Operand<i32> {
628 let ParserMatchClass = ImmSExti32i8AsmOperand;
629 let OperandType = "OPERAND_IMMEDIATE";
632 // 64-bits but only 32 bits are significant.
633 def i64i32imm : Operand<i64> {
634 let ParserMatchClass = ImmSExti64i32AsmOperand;
635 let OperandType = "OPERAND_IMMEDIATE";
638 // 64-bits but only 8 bits are significant.
639 def i64i8imm : Operand<i64> {
640 let ParserMatchClass = ImmSExti64i8AsmOperand;
641 let OperandType = "OPERAND_IMMEDIATE";
644 // Unsigned 8-bit immediate used by SSE/AVX instructions.
645 def u8imm : Operand<i8> {
646 let ParserMatchClass = ImmUnsignedi8AsmOperand;
647 let OperandType = "OPERAND_IMMEDIATE";
650 // 64-bits but only 32 bits are significant, and those bits are treated as being
652 def i64i32imm_pcrel : Operand<i64> {
653 let PrintMethod = "printPCRelImm";
654 let ParserMatchClass = X86AbsMemAsmOperand;
655 let OperandType = "OPERAND_PCREL";
658 def lea64_32mem : Operand<i32> {
659 let PrintMethod = "printanymem";
660 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
661 let ParserMatchClass = X86MemAsmOperand;
664 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
665 def lea64mem : Operand<i64> {
666 let PrintMethod = "printanymem";
667 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
668 let ParserMatchClass = X86MemAsmOperand;
672 //===----------------------------------------------------------------------===//
673 // X86 Complex Pattern Definitions.
676 // Define X86 specific addressing mode.
677 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
678 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
679 [add, sub, mul, X86mul_imm, shl, or, frameindex],
681 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
682 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
683 [add, sub, mul, X86mul_imm, shl, or,
684 frameindex, X86WrapperRIP],
687 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
688 [tglobaltlsaddr], []>;
690 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
691 [tglobaltlsaddr], []>;
693 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
694 [add, sub, mul, X86mul_imm, shl, or, frameindex,
697 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
698 [tglobaltlsaddr], []>;
700 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
701 [tglobaltlsaddr], []>;
703 //===----------------------------------------------------------------------===//
704 // X86 Instruction Predicate Definitions.
705 def HasCMov : Predicate<"Subtarget->hasCMov()">;
706 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
708 def HasMMX : Predicate<"Subtarget->hasMMX()">;
709 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
710 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
711 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
712 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
713 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
714 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
715 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
716 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
717 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
718 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
719 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
720 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
721 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
722 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
723 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
724 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
725 def HasAVX : Predicate<"Subtarget->hasAVX()">;
726 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
727 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
728 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
729 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
730 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
731 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
732 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
733 def HasCDI : Predicate<"Subtarget->hasCDI()">;
734 def HasPFI : Predicate<"Subtarget->hasPFI()">;
735 def HasERI : Predicate<"Subtarget->hasERI()">;
736 def HasDQI : Predicate<"Subtarget->hasDQI()">;
737 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
738 def HasBWI : Predicate<"Subtarget->hasBWI()">;
739 def HasVLX : Predicate<"Subtarget->hasVLX()">,
740 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
741 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
743 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
744 def HasAES : Predicate<"Subtarget->hasAES()">;
745 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
746 def HasFMA : Predicate<"Subtarget->hasFMA()">;
747 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
748 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
749 def HasXOP : Predicate<"Subtarget->hasXOP()">;
750 def HasTBM : Predicate<"Subtarget->hasTBM()">;
751 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
752 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
753 def HasF16C : Predicate<"Subtarget->hasF16C()">;
754 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
755 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
756 def HasBMI : Predicate<"Subtarget->hasBMI()">;
757 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
758 def HasRTM : Predicate<"Subtarget->hasRTM()">;
759 def HasHLE : Predicate<"Subtarget->hasHLE()">;
760 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
761 def HasADX : Predicate<"Subtarget->hasADX()">;
762 def HasSHA : Predicate<"Subtarget->hasSHA()">;
763 def HasSGX : Predicate<"Subtarget->hasSGX()">;
764 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
765 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
766 def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
767 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
768 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
769 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
770 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
771 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
772 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
773 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
774 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
775 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
776 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
777 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
778 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
779 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
780 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
781 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
782 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
783 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
784 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
785 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
786 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
787 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
788 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
789 "TM.getCodeModel() != CodeModel::Kernel">;
790 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
791 "TM.getCodeModel() == CodeModel::Kernel">;
792 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
793 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
794 def OptForSize : Predicate<"OptForSize">;
795 def OptForSpeed : Predicate<"!OptForSize">;
796 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
797 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
798 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
799 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
800 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
802 //===----------------------------------------------------------------------===//
803 // X86 Instruction Format Definitions.
806 include "X86InstrFormats.td"
808 //===----------------------------------------------------------------------===//
809 // Pattern fragments.
812 // X86 specific condition code. These correspond to CondCode in
813 // X86InstrInfo.h. They must be kept in synch.
814 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
815 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
816 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
817 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
818 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
819 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
820 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
821 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
822 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
823 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
824 def X86_COND_NO : PatLeaf<(i8 10)>;
825 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
826 def X86_COND_NS : PatLeaf<(i8 12)>;
827 def X86_COND_O : PatLeaf<(i8 13)>;
828 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
829 def X86_COND_S : PatLeaf<(i8 15)>;
831 // Predicate used to help when pattern matching LZCNT/TZCNT.
832 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
833 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
836 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
837 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
838 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
839 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
842 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
845 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
847 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
849 def i64immZExt32SExt8 : ImmLeaf<i64, [{
850 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
853 // Helper fragments for loads.
854 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
855 // known to be 32-bit aligned or better. Ditto for i8 to i16.
856 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
857 LoadSDNode *LD = cast<LoadSDNode>(N);
858 ISD::LoadExtType ExtType = LD->getExtensionType();
859 if (ExtType == ISD::NON_EXTLOAD)
861 if (ExtType == ISD::EXTLOAD)
862 return LD->getAlignment() >= 2 && !LD->isVolatile();
866 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
867 LoadSDNode *LD = cast<LoadSDNode>(N);
868 ISD::LoadExtType ExtType = LD->getExtensionType();
869 if (ExtType == ISD::EXTLOAD)
870 return LD->getAlignment() >= 2 && !LD->isVolatile();
874 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
875 LoadSDNode *LD = cast<LoadSDNode>(N);
876 ISD::LoadExtType ExtType = LD->getExtensionType();
877 if (ExtType == ISD::NON_EXTLOAD)
879 if (ExtType == ISD::EXTLOAD)
880 return LD->getAlignment() >= 4 && !LD->isVolatile();
884 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
885 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
886 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
887 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
888 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
890 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
891 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
892 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
893 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
894 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
895 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
897 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
898 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
899 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
900 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
901 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
902 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
903 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
904 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
905 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
906 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
908 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
909 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
910 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
911 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
912 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
913 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
914 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
915 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
916 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
917 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
920 // An 'and' node with a single use.
921 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
922 return N->hasOneUse();
924 // An 'srl' node with a single use.
925 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
926 return N->hasOneUse();
928 // An 'trunc' node with a single use.
929 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
930 return N->hasOneUse();
933 //===----------------------------------------------------------------------===//
938 let hasSideEffects = 0, SchedRW = [WriteZero] in {
939 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
940 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
941 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
942 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
943 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
947 // Constructing a stack frame.
948 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
949 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
951 let SchedRW = [WriteALU] in {
952 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
953 def LEAVE : I<0xC9, RawFrm,
954 (outs), (ins), "leave", [], IIC_LEAVE>,
955 Requires<[Not64BitMode]>;
957 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
958 def LEAVE64 : I<0xC9, RawFrm,
959 (outs), (ins), "leave", [], IIC_LEAVE>,
960 Requires<[In64BitMode]>;
963 //===----------------------------------------------------------------------===//
964 // Miscellaneous Instructions.
967 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
968 let mayLoad = 1, SchedRW = [WriteLoad] in {
969 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
970 IIC_POP_REG16>, OpSize16;
971 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
972 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
973 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
974 IIC_POP_REG>, OpSize16;
975 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
976 IIC_POP_MEM>, OpSize16;
977 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
978 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
979 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
980 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
981 } // mayLoad, SchedRW
983 let mayStore = 1, SchedRW = [WriteStore] in {
984 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
985 IIC_PUSH_REG>, OpSize16;
986 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
987 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
988 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
989 IIC_PUSH_REG>, OpSize16;
990 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
991 IIC_PUSH_MEM>, OpSize16;
992 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
993 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
994 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
995 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
997 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
998 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
999 Requires<[Not64BitMode]>;
1000 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1001 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1002 Requires<[Not64BitMode]>;
1003 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1004 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1005 Requires<[Not64BitMode]>;
1006 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1007 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1008 Requires<[Not64BitMode]>;
1009 } // mayStore, SchedRW
1012 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1013 SchedRW = [WriteLoad] in {
1014 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1016 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1017 OpSize32, Requires<[Not64BitMode]>;
1020 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1021 SchedRW = [WriteStore] in {
1022 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1024 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1025 OpSize32, Requires<[Not64BitMode]>;
1028 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1029 let mayLoad = 1, SchedRW = [WriteLoad] in {
1030 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1031 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1032 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1033 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1034 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1035 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1036 } // mayLoad, SchedRW
1037 let mayStore = 1, SchedRW = [WriteStore] in {
1038 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1039 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1040 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1041 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1042 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1043 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1044 } // mayStore, SchedRW
1047 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1048 SchedRW = [WriteStore] in {
1049 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1050 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1051 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1052 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1053 Requires<[In64BitMode]>;
1054 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1055 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1056 Requires<[In64BitMode]>;
1059 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1060 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1061 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1062 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1063 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1064 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1066 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1067 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1068 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1069 OpSize32, Requires<[Not64BitMode]>;
1070 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1071 OpSize16, Requires<[Not64BitMode]>;
1073 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1074 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1075 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1076 OpSize32, Requires<[Not64BitMode]>;
1077 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1078 OpSize16, Requires<[Not64BitMode]>;
1081 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1082 // GR32 = bswap GR32
1083 def BSWAP32r : I<0xC8, AddRegFrm,
1084 (outs GR32:$dst), (ins GR32:$src),
1086 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1088 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1090 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1091 } // Constraints = "$src = $dst", SchedRW
1093 // Bit scan instructions.
1094 let Defs = [EFLAGS] in {
1095 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1096 "bsf{w}\t{$src, $dst|$dst, $src}",
1097 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1098 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1099 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1100 "bsf{w}\t{$src, $dst|$dst, $src}",
1101 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1102 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1103 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1104 "bsf{l}\t{$src, $dst|$dst, $src}",
1105 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1106 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1107 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1108 "bsf{l}\t{$src, $dst|$dst, $src}",
1109 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1110 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1111 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1112 "bsf{q}\t{$src, $dst|$dst, $src}",
1113 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1114 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1115 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1116 "bsf{q}\t{$src, $dst|$dst, $src}",
1117 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1118 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1120 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1121 "bsr{w}\t{$src, $dst|$dst, $src}",
1122 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1123 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1124 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1125 "bsr{w}\t{$src, $dst|$dst, $src}",
1126 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1127 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1128 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1129 "bsr{l}\t{$src, $dst|$dst, $src}",
1130 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1131 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1132 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1133 "bsr{l}\t{$src, $dst|$dst, $src}",
1134 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1135 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1136 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1137 "bsr{q}\t{$src, $dst|$dst, $src}",
1138 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1139 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1140 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1141 "bsr{q}\t{$src, $dst|$dst, $src}",
1142 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1143 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1144 } // Defs = [EFLAGS]
1146 let SchedRW = [WriteMicrocoded] in {
1147 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1148 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1149 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1150 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1151 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1152 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1153 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1154 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1155 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1156 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1159 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1160 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1161 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1162 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1163 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1164 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1165 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1166 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1167 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1168 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1169 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1170 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1171 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1173 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1174 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1175 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1176 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1177 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1178 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1179 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1180 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1181 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1182 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1183 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1184 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1185 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1187 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1188 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1189 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1190 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1191 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1192 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1193 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1194 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1195 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1196 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1200 //===----------------------------------------------------------------------===//
1201 // Move Instructions.
1203 let SchedRW = [WriteMove] in {
1204 let hasSideEffects = 0 in {
1205 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1206 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1207 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1208 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1209 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1210 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1211 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1212 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1215 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1216 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1217 "mov{b}\t{$src, $dst|$dst, $src}",
1218 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1219 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1220 "mov{w}\t{$src, $dst|$dst, $src}",
1221 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1222 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1223 "mov{l}\t{$src, $dst|$dst, $src}",
1224 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1225 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1226 "mov{q}\t{$src, $dst|$dst, $src}",
1227 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1229 let isReMaterializable = 1 in {
1230 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1231 "movabs{q}\t{$src, $dst|$dst, $src}",
1232 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1235 // Longer forms that use a ModR/M byte. Needed for disassembler
1236 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1237 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1238 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1239 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1240 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1241 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1242 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1246 let SchedRW = [WriteStore] in {
1247 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1248 "mov{b}\t{$src, $dst|$dst, $src}",
1249 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1250 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1251 "mov{w}\t{$src, $dst|$dst, $src}",
1252 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1253 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1254 "mov{l}\t{$src, $dst|$dst, $src}",
1255 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1256 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1257 "mov{q}\t{$src, $dst|$dst, $src}",
1258 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1261 let hasSideEffects = 0 in {
1263 /// Memory offset versions of moves. The immediate is an address mode sized
1264 /// offset from the segment base.
1265 let SchedRW = [WriteALU] in {
1266 let mayLoad = 1 in {
1268 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1269 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1272 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1273 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1276 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1277 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1280 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1281 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1285 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1286 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1288 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1289 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1292 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1293 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1296 let mayStore = 1 in {
1298 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1299 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1301 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1302 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1305 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1306 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1309 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1310 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1314 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1315 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1317 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1318 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1321 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1322 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1327 // These forms all have full 64-bit absolute addresses in their instructions
1328 // and use the movabs mnemonic to indicate this specific form.
1329 let mayLoad = 1 in {
1331 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1332 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1334 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1335 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1337 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1338 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1341 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1342 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1345 let mayStore = 1 in {
1347 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1348 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1350 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1351 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1353 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1354 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1357 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1358 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1360 } // hasSideEffects = 0
1362 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1363 SchedRW = [WriteMove] in {
1364 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1365 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1366 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1367 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1368 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1369 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1370 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1371 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1374 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1375 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1376 "mov{b}\t{$src, $dst|$dst, $src}",
1377 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1378 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1379 "mov{w}\t{$src, $dst|$dst, $src}",
1380 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1381 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1382 "mov{l}\t{$src, $dst|$dst, $src}",
1383 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1384 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1385 "mov{q}\t{$src, $dst|$dst, $src}",
1386 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1389 let SchedRW = [WriteStore] in {
1390 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1391 "mov{b}\t{$src, $dst|$dst, $src}",
1392 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1393 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1394 "mov{w}\t{$src, $dst|$dst, $src}",
1395 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1396 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1397 "mov{l}\t{$src, $dst|$dst, $src}",
1398 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1399 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1400 "mov{q}\t{$src, $dst|$dst, $src}",
1401 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1404 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1405 // that they can be used for copying and storing h registers, which can't be
1406 // encoded when a REX prefix is present.
1407 let isCodeGenOnly = 1 in {
1408 let hasSideEffects = 0 in
1409 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1410 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1411 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1413 let mayStore = 1, hasSideEffects = 0 in
1414 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1415 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1416 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1417 IIC_MOV_MEM>, Sched<[WriteStore]>;
1418 let mayLoad = 1, hasSideEffects = 0,
1419 canFoldAsLoad = 1, isReMaterializable = 1 in
1420 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1421 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1422 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1423 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1427 // Condition code ops, incl. set if equal/not equal/...
1428 let SchedRW = [WriteALU] in {
1429 let Defs = [EFLAGS], Uses = [AH] in
1430 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1431 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1432 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1433 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1434 IIC_AHF>; // AH = flags
1437 //===----------------------------------------------------------------------===//
1438 // Bit tests instructions: BT, BTS, BTR, BTC.
1440 let Defs = [EFLAGS] in {
1441 let SchedRW = [WriteALU] in {
1442 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1443 "bt{w}\t{$src2, $src1|$src1, $src2}",
1444 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1446 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1447 "bt{l}\t{$src2, $src1|$src1, $src2}",
1448 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1450 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1451 "bt{q}\t{$src2, $src1|$src1, $src2}",
1452 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1455 // Unlike with the register+register form, the memory+register form of the
1456 // bt instruction does not ignore the high bits of the index. From ISel's
1457 // perspective, this is pretty bizarre. Make these instructions disassembly
1460 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1461 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1462 "bt{w}\t{$src2, $src1|$src1, $src2}",
1463 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1464 // (implicit EFLAGS)]
1466 >, OpSize16, TB, Requires<[FastBTMem]>;
1467 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1468 "bt{l}\t{$src2, $src1|$src1, $src2}",
1469 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1470 // (implicit EFLAGS)]
1472 >, OpSize32, TB, Requires<[FastBTMem]>;
1473 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1474 "bt{q}\t{$src2, $src1|$src1, $src2}",
1475 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1476 // (implicit EFLAGS)]
1481 let SchedRW = [WriteALU] in {
1482 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1483 "bt{w}\t{$src2, $src1|$src1, $src2}",
1484 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1485 IIC_BT_RI>, OpSize16, TB;
1486 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1487 "bt{l}\t{$src2, $src1|$src1, $src2}",
1488 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1489 IIC_BT_RI>, OpSize32, TB;
1490 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1491 "bt{q}\t{$src2, $src1|$src1, $src2}",
1492 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1496 // Note that these instructions don't need FastBTMem because that
1497 // only applies when the other operand is in a register. When it's
1498 // an immediate, bt is still fast.
1499 let SchedRW = [WriteALU] in {
1500 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1501 "bt{w}\t{$src2, $src1|$src1, $src2}",
1502 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1503 ], IIC_BT_MI>, OpSize16, TB;
1504 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1505 "bt{l}\t{$src2, $src1|$src1, $src2}",
1506 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1507 ], IIC_BT_MI>, OpSize32, TB;
1508 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1509 "bt{q}\t{$src2, $src1|$src1, $src2}",
1510 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1511 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1514 let hasSideEffects = 0 in {
1515 let SchedRW = [WriteALU] in {
1516 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1517 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1519 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1520 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1522 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1523 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1526 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1527 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1528 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1530 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1531 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1533 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1534 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1537 let SchedRW = [WriteALU] in {
1538 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1539 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1541 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1542 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1544 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1545 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1548 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1549 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1550 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1552 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1553 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1555 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1556 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1559 let SchedRW = [WriteALU] in {
1560 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1561 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1563 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1564 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1566 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1567 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1570 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1571 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1572 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1574 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1575 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1577 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1578 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1581 let SchedRW = [WriteALU] in {
1582 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1583 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1585 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1586 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1588 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1589 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1592 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1593 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1594 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1596 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1597 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1599 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1600 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1603 let SchedRW = [WriteALU] in {
1604 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1605 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1607 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1608 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1610 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1611 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1614 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1615 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1616 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1618 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1619 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1621 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1622 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1625 let SchedRW = [WriteALU] in {
1626 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1627 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1629 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1630 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1632 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1633 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1636 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1637 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1638 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1640 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1641 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1643 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1644 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1646 } // hasSideEffects = 0
1647 } // Defs = [EFLAGS]
1650 //===----------------------------------------------------------------------===//
1654 // Atomic swap. These are just normal xchg instructions. But since a memory
1655 // operand is referenced, the atomicity is ensured.
1656 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1657 InstrItinClass itin> {
1658 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1659 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1660 (ins GR8:$val, i8mem:$ptr),
1661 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1664 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1666 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1667 (ins GR16:$val, i16mem:$ptr),
1668 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1671 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1673 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1674 (ins GR32:$val, i32mem:$ptr),
1675 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1678 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1680 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1681 (ins GR64:$val, i64mem:$ptr),
1682 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1685 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1690 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1692 // Swap between registers.
1693 let SchedRW = [WriteALU] in {
1694 let Constraints = "$val = $dst" in {
1695 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1696 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1697 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1698 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1700 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1701 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1703 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1704 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1707 // Swap between EAX and other registers.
1708 let Uses = [AX], Defs = [AX] in
1709 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1710 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1711 let Uses = [EAX], Defs = [EAX] in
1712 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1713 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1714 OpSize32, Requires<[Not64BitMode]>;
1715 let Uses = [EAX], Defs = [EAX] in
1716 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1717 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1718 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1719 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1720 OpSize32, Requires<[In64BitMode]>;
1721 let Uses = [RAX], Defs = [RAX] in
1722 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1723 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1726 let SchedRW = [WriteALU] in {
1727 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1728 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1729 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1730 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1732 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1733 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1735 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1736 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1739 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1740 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1741 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1742 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1743 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1745 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1746 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1748 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1749 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1753 let SchedRW = [WriteALU] in {
1754 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1755 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1756 IIC_CMPXCHG_REG8>, TB;
1757 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1758 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1759 IIC_CMPXCHG_REG>, TB, OpSize16;
1760 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1761 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1762 IIC_CMPXCHG_REG>, TB, OpSize32;
1763 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1764 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1765 IIC_CMPXCHG_REG>, TB;
1768 let SchedRW = [WriteALULd, WriteRMW] in {
1769 let mayLoad = 1, mayStore = 1 in {
1770 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1771 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1772 IIC_CMPXCHG_MEM8>, TB;
1773 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1774 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1775 IIC_CMPXCHG_MEM>, TB, OpSize16;
1776 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1777 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1778 IIC_CMPXCHG_MEM>, TB, OpSize32;
1779 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1780 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1781 IIC_CMPXCHG_MEM>, TB;
1784 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1785 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1786 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1788 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1789 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1790 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1791 TB, Requires<[HasCmpxchg16b]>;
1795 // Lock instruction prefix
1796 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1798 // Rex64 instruction prefix
1799 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1800 Requires<[In64BitMode]>;
1802 // Data16 instruction prefix
1803 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1805 // Repeat string operation instruction prefixes
1806 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1807 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1808 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1809 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1810 // Repeat while not equal (used with CMPS and SCAS)
1811 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1815 // String manipulation instructions
1816 let SchedRW = [WriteMicrocoded] in {
1817 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1818 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1819 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1820 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1821 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1822 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1823 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1824 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1825 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1826 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1827 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1828 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1829 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1832 let SchedRW = [WriteSystem] in {
1833 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1834 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1835 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1836 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1837 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1838 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1839 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1840 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1843 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1844 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1845 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1846 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1847 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1848 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1849 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1850 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1854 // Flag instructions
1855 let SchedRW = [WriteALU] in {
1856 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1857 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1858 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1859 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1860 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1861 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1862 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1864 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1867 // Table lookup instructions
1868 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1871 let SchedRW = [WriteMicrocoded] in {
1872 // ASCII Adjust After Addition
1873 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1874 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1875 Requires<[Not64BitMode]>;
1877 // ASCII Adjust AX Before Division
1878 // sets AL, AH and EFLAGS and uses AL and AH
1879 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1880 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1882 // ASCII Adjust AX After Multiply
1883 // sets AL, AH and EFLAGS and uses AL
1884 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1885 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1887 // ASCII Adjust AL After Subtraction - sets
1888 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1889 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1890 Requires<[Not64BitMode]>;
1892 // Decimal Adjust AL after Addition
1893 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1894 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1895 Requires<[Not64BitMode]>;
1897 // Decimal Adjust AL after Subtraction
1898 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1899 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1900 Requires<[Not64BitMode]>;
1903 let SchedRW = [WriteSystem] in {
1904 // Check Array Index Against Bounds
1905 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1906 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1907 Requires<[Not64BitMode]>;
1908 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1909 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1910 Requires<[Not64BitMode]>;
1912 // Adjust RPL Field of Segment Selector
1913 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1914 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1915 Requires<[Not64BitMode]>;
1916 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1917 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1918 Requires<[Not64BitMode]>;
1921 //===----------------------------------------------------------------------===//
1922 // MOVBE Instructions
1924 let Predicates = [HasMOVBE] in {
1925 let SchedRW = [WriteALULd] in {
1926 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1927 "movbe{w}\t{$src, $dst|$dst, $src}",
1928 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1930 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1931 "movbe{l}\t{$src, $dst|$dst, $src}",
1932 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1934 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1935 "movbe{q}\t{$src, $dst|$dst, $src}",
1936 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1939 let SchedRW = [WriteStore] in {
1940 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1941 "movbe{w}\t{$src, $dst|$dst, $src}",
1942 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1944 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1945 "movbe{l}\t{$src, $dst|$dst, $src}",
1946 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1948 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1949 "movbe{q}\t{$src, $dst|$dst, $src}",
1950 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1955 //===----------------------------------------------------------------------===//
1956 // RDRAND Instruction
1958 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1959 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1961 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1962 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1964 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1965 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1967 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1970 //===----------------------------------------------------------------------===//
1971 // RDSEED Instruction
1973 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1974 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1976 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1977 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1979 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1980 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1982 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1985 //===----------------------------------------------------------------------===//
1986 // LZCNT Instruction
1988 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1989 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1990 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1991 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1993 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1994 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1995 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1996 (implicit EFLAGS)]>, XS, OpSize16;
1998 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1999 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2000 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2002 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2003 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2004 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2005 (implicit EFLAGS)]>, XS, OpSize32;
2007 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2008 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2009 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2011 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2012 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2013 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2014 (implicit EFLAGS)]>, XS;
2017 let Predicates = [HasLZCNT] in {
2018 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2019 (X86cmp GR16:$src, (i16 0))),
2020 (LZCNT16rr GR16:$src)>;
2021 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2022 (X86cmp GR32:$src, (i32 0))),
2023 (LZCNT32rr GR32:$src)>;
2024 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2025 (X86cmp GR64:$src, (i64 0))),
2026 (LZCNT64rr GR64:$src)>;
2027 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2028 (X86cmp GR16:$src, (i16 0))),
2029 (LZCNT16rr GR16:$src)>;
2030 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2031 (X86cmp GR32:$src, (i32 0))),
2032 (LZCNT32rr GR32:$src)>;
2033 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2034 (X86cmp GR64:$src, (i64 0))),
2035 (LZCNT64rr GR64:$src)>;
2037 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2038 (X86cmp (loadi16 addr:$src), (i16 0))),
2039 (LZCNT16rm addr:$src)>;
2040 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2041 (X86cmp (loadi32 addr:$src), (i32 0))),
2042 (LZCNT32rm addr:$src)>;
2043 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2044 (X86cmp (loadi64 addr:$src), (i64 0))),
2045 (LZCNT64rm addr:$src)>;
2046 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2047 (X86cmp (loadi16 addr:$src), (i16 0))),
2048 (LZCNT16rm addr:$src)>;
2049 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2050 (X86cmp (loadi32 addr:$src), (i32 0))),
2051 (LZCNT32rm addr:$src)>;
2052 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2053 (X86cmp (loadi64 addr:$src), (i64 0))),
2054 (LZCNT64rm addr:$src)>;
2057 //===----------------------------------------------------------------------===//
2060 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2061 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2062 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2063 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2065 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2066 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2067 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2068 (implicit EFLAGS)]>, XS, OpSize16;
2070 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2071 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2072 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2074 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2075 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2076 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2077 (implicit EFLAGS)]>, XS, OpSize32;
2079 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2080 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2081 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2083 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2084 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2085 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2086 (implicit EFLAGS)]>, XS;
2089 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2090 RegisterClass RC, X86MemOperand x86memop> {
2091 let hasSideEffects = 0 in {
2092 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2093 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2096 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2097 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2102 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2103 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2104 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2105 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2106 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2107 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2108 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2111 //===----------------------------------------------------------------------===//
2112 // Pattern fragments to auto generate BMI instructions.
2113 //===----------------------------------------------------------------------===//
2115 let Predicates = [HasBMI] in {
2116 // FIXME: patterns for the load versions are not implemented
2117 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2118 (BLSR32rr GR32:$src)>;
2119 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2120 (BLSR64rr GR64:$src)>;
2122 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2123 (BLSMSK32rr GR32:$src)>;
2124 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2125 (BLSMSK64rr GR64:$src)>;
2127 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2128 (BLSI32rr GR32:$src)>;
2129 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2130 (BLSI64rr GR64:$src)>;
2133 let Predicates = [HasBMI] in {
2134 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2135 (X86cmp GR16:$src, (i16 0))),
2136 (TZCNT16rr GR16:$src)>;
2137 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2138 (X86cmp GR32:$src, (i32 0))),
2139 (TZCNT32rr GR32:$src)>;
2140 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2141 (X86cmp GR64:$src, (i64 0))),
2142 (TZCNT64rr GR64:$src)>;
2143 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2144 (X86cmp GR16:$src, (i16 0))),
2145 (TZCNT16rr GR16:$src)>;
2146 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2147 (X86cmp GR32:$src, (i32 0))),
2148 (TZCNT32rr GR32:$src)>;
2149 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2150 (X86cmp GR64:$src, (i64 0))),
2151 (TZCNT64rr GR64:$src)>;
2153 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2154 (X86cmp (loadi16 addr:$src), (i16 0))),
2155 (TZCNT16rm addr:$src)>;
2156 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2157 (X86cmp (loadi32 addr:$src), (i32 0))),
2158 (TZCNT32rm addr:$src)>;
2159 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2160 (X86cmp (loadi64 addr:$src), (i64 0))),
2161 (TZCNT64rm addr:$src)>;
2162 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2163 (X86cmp (loadi16 addr:$src), (i16 0))),
2164 (TZCNT16rm addr:$src)>;
2165 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2166 (X86cmp (loadi32 addr:$src), (i32 0))),
2167 (TZCNT32rm addr:$src)>;
2168 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2169 (X86cmp (loadi64 addr:$src), (i64 0))),
2170 (TZCNT64rm addr:$src)>;
2174 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2175 X86MemOperand x86memop, Intrinsic Int,
2177 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2178 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2179 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2181 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2182 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2183 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2184 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2187 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2188 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2189 int_x86_bmi_bextr_32, loadi32>;
2190 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2191 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2194 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2195 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2196 int_x86_bmi_bzhi_32, loadi32>;
2197 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2198 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2202 def CountTrailingOnes : SDNodeXForm<imm, [{
2203 // Count the trailing ones in the immediate.
2204 return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
2207 def BZHIMask : ImmLeaf<i64, [{
2208 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
2211 let Predicates = [HasBMI2] in {
2212 def : Pat<(and GR64:$src, BZHIMask:$mask),
2213 (BZHI64rr GR64:$src,
2214 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2215 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2217 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2218 (BZHI32rr GR32:$src,
2219 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2221 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2222 (BZHI32rm addr:$src,
2223 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2225 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2226 (BZHI64rr GR64:$src,
2227 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2229 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2230 (BZHI64rm addr:$src,
2231 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2234 let Predicates = [HasBMI] in {
2235 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2236 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2237 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2238 (BEXTR32rm addr:$src1, GR32:$src2)>;
2239 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2240 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2241 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2242 (BEXTR64rm addr:$src1, GR64:$src2)>;
2245 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2246 X86MemOperand x86memop, Intrinsic Int,
2248 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2249 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2250 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2252 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2253 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2254 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2257 let Predicates = [HasBMI2] in {
2258 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2259 int_x86_bmi_pdep_32, loadi32>, T8XD;
2260 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2261 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2262 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2263 int_x86_bmi_pext_32, loadi32>, T8XS;
2264 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2265 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2268 //===----------------------------------------------------------------------===//
2271 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2273 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2274 X86MemOperand x86memop, PatFrag ld_frag,
2275 Intrinsic Int, Operand immtype,
2276 SDPatternOperator immoperator> {
2277 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2278 !strconcat(OpcodeStr,
2279 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2280 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2282 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2283 (ins x86memop:$src1, immtype:$cntl),
2284 !strconcat(OpcodeStr,
2285 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2286 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2290 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2291 int_x86_tbm_bextri_u32, i32imm, imm>;
2292 let ImmT = Imm32S in
2293 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2294 int_x86_tbm_bextri_u64, i64i32imm,
2295 i64immSExt32>, VEX_W;
2297 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2298 RegisterClass RC, string OpcodeStr,
2299 X86MemOperand x86memop, PatFrag ld_frag> {
2300 let hasSideEffects = 0 in {
2301 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2302 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2305 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2306 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2311 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2312 Format FormReg, Format FormMem> {
2313 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2315 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2319 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2320 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2321 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2322 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2323 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2324 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2325 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2326 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2327 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2330 //===----------------------------------------------------------------------===//
2331 // Pattern fragments to auto generate TBM instructions.
2332 //===----------------------------------------------------------------------===//
2334 let Predicates = [HasTBM] in {
2335 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2336 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2337 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2338 (BEXTRI32mi addr:$src1, imm:$src2)>;
2339 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2340 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2341 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2342 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2344 // FIXME: patterns for the load versions are not implemented
2345 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2346 (BLCFILL32rr GR32:$src)>;
2347 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2348 (BLCFILL64rr GR64:$src)>;
2350 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2351 (BLCI32rr GR32:$src)>;
2352 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2353 (BLCI64rr GR64:$src)>;
2355 // Extra patterns because opt can optimize the above patterns to this.
2356 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2357 (BLCI32rr GR32:$src)>;
2358 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2359 (BLCI64rr GR64:$src)>;
2361 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2362 (BLCIC32rr GR32:$src)>;
2363 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2364 (BLCIC64rr GR64:$src)>;
2366 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2367 (BLCMSK32rr GR32:$src)>;
2368 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2369 (BLCMSK64rr GR64:$src)>;
2371 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2372 (BLCS32rr GR32:$src)>;
2373 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2374 (BLCS64rr GR64:$src)>;
2376 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2377 (BLSFILL32rr GR32:$src)>;
2378 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2379 (BLSFILL64rr GR64:$src)>;
2381 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2382 (BLSIC32rr GR32:$src)>;
2383 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2384 (BLSIC64rr GR64:$src)>;
2386 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2387 (T1MSKC32rr GR32:$src)>;
2388 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2389 (T1MSKC64rr GR64:$src)>;
2391 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2392 (TZMSK32rr GR32:$src)>;
2393 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2394 (TZMSK64rr GR64:$src)>;
2397 //===----------------------------------------------------------------------===//
2399 //===----------------------------------------------------------------------===//
2401 include "X86InstrArithmetic.td"
2402 include "X86InstrCMovSetCC.td"
2403 include "X86InstrExtension.td"
2404 include "X86InstrControl.td"
2405 include "X86InstrShiftRotate.td"
2407 // X87 Floating Point Stack.
2408 include "X86InstrFPStack.td"
2410 // SIMD support (SSE, MMX and AVX)
2411 include "X86InstrFragmentsSIMD.td"
2413 // FMA - Fused Multiply-Add support (requires FMA)
2414 include "X86InstrFMA.td"
2417 include "X86InstrXOP.td"
2419 // SSE, MMX and 3DNow! vector support.
2420 include "X86InstrSSE.td"
2421 include "X86InstrAVX512.td"
2422 include "X86InstrMMX.td"
2423 include "X86Instr3DNow.td"
2425 include "X86InstrVMX.td"
2426 include "X86InstrSVM.td"
2428 include "X86InstrTSX.td"
2429 include "X86InstrSGX.td"
2431 // System instructions.
2432 include "X86InstrSystem.td"
2434 // Compiler Pseudo Instructions and Pat Patterns
2435 include "X86InstrCompiler.td"
2437 //===----------------------------------------------------------------------===//
2438 // Assembler Mnemonic Aliases
2439 //===----------------------------------------------------------------------===//
2441 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2442 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2443 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2445 def : MnemonicAlias<"cbw", "cbtw", "att">;
2446 def : MnemonicAlias<"cwde", "cwtl", "att">;
2447 def : MnemonicAlias<"cwd", "cwtd", "att">;
2448 def : MnemonicAlias<"cdq", "cltd", "att">;
2449 def : MnemonicAlias<"cdqe", "cltq", "att">;
2450 def : MnemonicAlias<"cqo", "cqto", "att">;
2452 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2453 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2454 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2456 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2457 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2459 def : MnemonicAlias<"loopz", "loope", "att">;
2460 def : MnemonicAlias<"loopnz", "loopne", "att">;
2462 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2463 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2464 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2465 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2466 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2467 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2468 def : MnemonicAlias<"popfd", "popfl", "att">;
2470 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2471 // all modes. However: "push (addr)" and "push $42" should default to
2472 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2473 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2474 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2475 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2476 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2477 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2478 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2479 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2481 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2482 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2483 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2484 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2485 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2486 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2488 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2489 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2490 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2491 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2493 def : MnemonicAlias<"repe", "rep", "att">;
2494 def : MnemonicAlias<"repz", "rep", "att">;
2495 def : MnemonicAlias<"repnz", "repne", "att">;
2497 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2498 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2499 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2501 def : MnemonicAlias<"salb", "shlb", "att">;
2502 def : MnemonicAlias<"salw", "shlw", "att">;
2503 def : MnemonicAlias<"sall", "shll", "att">;
2504 def : MnemonicAlias<"salq", "shlq", "att">;
2506 def : MnemonicAlias<"smovb", "movsb", "att">;
2507 def : MnemonicAlias<"smovw", "movsw", "att">;
2508 def : MnemonicAlias<"smovl", "movsl", "att">;
2509 def : MnemonicAlias<"smovq", "movsq", "att">;
2511 def : MnemonicAlias<"ud2a", "ud2", "att">;
2512 def : MnemonicAlias<"verrw", "verr", "att">;
2514 // System instruction aliases.
2515 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2516 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2517 def : MnemonicAlias<"sysret", "sysretl", "att">;
2518 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2520 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2521 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2522 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2523 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2524 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2525 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2526 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2527 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2528 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2529 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2530 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2531 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2534 // Floating point stack aliases.
2535 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2536 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2537 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2538 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2539 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2540 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2541 def : MnemonicAlias<"fildq", "fildll", "att">;
2542 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2543 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2544 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2545 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2546 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2547 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2548 def : MnemonicAlias<"fwait", "wait">;
2551 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2553 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2554 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2556 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2557 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2558 /// example "setz" -> "sete".
2559 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2561 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2562 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2563 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2564 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2565 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2566 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2567 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2568 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2569 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2570 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2572 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2573 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2574 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2575 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2578 // Aliases for set<CC>
2579 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2580 // Aliases for j<CC>
2581 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2582 // Aliases for cmov<CC>{w,l,q}
2583 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2584 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2585 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2586 // No size suffix for intel-style asm.
2587 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2590 //===----------------------------------------------------------------------===//
2591 // Assembler Instruction Aliases
2592 //===----------------------------------------------------------------------===//
2594 // aad/aam default to base 10 if no operand is specified.
2595 def : InstAlias<"aad", (AAD8i8 10)>;
2596 def : InstAlias<"aam", (AAM8i8 10)>;
2598 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2599 // Likewise for btc/btr/bts.
2600 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2601 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2602 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2603 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2604 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2605 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2606 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2607 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2610 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2611 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2612 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2613 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2615 // lods aliases. Accept the destination being omitted because it's implicit
2616 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2617 // in the destination.
2618 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2619 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2620 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2621 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2622 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2623 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2624 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2625 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2627 // stos aliases. Accept the source being omitted because it's implicit in
2628 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2630 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2631 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2632 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2633 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2634 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2635 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2636 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2637 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2639 // scas aliases. Accept the destination being omitted because it's implicit
2640 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2641 // in the destination.
2642 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2643 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2644 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2645 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2646 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2647 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2648 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2649 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2651 // div and idiv aliases for explicit A register.
2652 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2653 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2654 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2655 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2656 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2657 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2658 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2659 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2660 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2661 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2662 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2663 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2664 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2665 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2666 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2667 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2671 // Various unary fpstack operations default to operating on on ST1.
2672 // For example, "fxch" -> "fxch %st(1)"
2673 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2674 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2675 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2676 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2677 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2678 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2679 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2680 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2681 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2682 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2683 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2684 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2685 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2686 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2687 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2689 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2690 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2691 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2693 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2694 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2695 (Inst RST:$op), EmitAlias>;
2696 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2697 (Inst ST0), EmitAlias>;
2700 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2701 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2702 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2703 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2704 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2705 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2706 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2707 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2708 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2709 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2710 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2711 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2712 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2713 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2714 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2715 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2718 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2719 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2720 // solely because gas supports it.
2721 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2722 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2723 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2724 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2725 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2726 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2728 // We accept "fnstsw %eax" even though it only writes %ax.
2729 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2730 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2731 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2733 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2734 // this is compatible with what GAS does.
2735 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2736 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2737 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2738 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2739 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2740 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2741 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2742 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2744 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2745 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2746 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2747 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2748 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2749 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2752 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2753 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2754 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2755 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2756 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2757 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2758 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2760 // inb %dx -> inb %al, %dx
2761 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2762 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2763 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2764 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2765 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2766 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2769 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2770 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2771 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2772 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2773 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2774 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2775 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2776 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2777 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2779 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2780 // the move. All segment/mem forms are equivalent, this has the shortest
2782 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2783 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2785 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2786 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2788 // Match 'movq GR64, MMX' as an alias for movd.
2789 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2790 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2791 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2792 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2795 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2796 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2797 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2798 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2799 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2800 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2801 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2804 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2805 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2806 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2807 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2808 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2809 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2810 // Note: No GR32->GR64 movzx form.
2812 // outb %dx -> outb %al, %dx
2813 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2814 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2815 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2816 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2817 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2818 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2820 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2821 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2822 // errors, since its encoding is the most compact.
2823 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2825 // shld/shrd op,op -> shld op, op, CL
2826 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2827 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2828 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2829 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2830 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2831 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2833 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2834 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2835 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2836 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2837 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2838 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2840 /* FIXME: This is disabled because the asm matcher is currently incapable of
2841 * matching a fixed immediate like $1.
2842 // "shl X, $1" is an alias for "shl X".
2843 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2844 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2845 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2846 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2847 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2848 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2849 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2850 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2851 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2852 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2853 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2854 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2855 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2856 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2857 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2858 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2859 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2862 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2863 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2864 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2865 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2868 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2869 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2870 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2871 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2872 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2873 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2874 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2875 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2876 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2878 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2879 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2880 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2881 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2882 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2883 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2884 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2885 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2886 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2888 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2889 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2890 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2891 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2892 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2893 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2894 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;