1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // MMX Pattern Fragments
18 //===----------------------------------------------------------------------===//
20 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
22 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
23 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
24 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
25 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
27 //===----------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
31 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
33 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
34 return getI8Imm(X86::getShuffleSHUFImmediate(N));
37 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
38 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
39 return X86::isUNPCKHMask(N);
42 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
43 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
44 return X86::isUNPCKLMask(N);
47 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
48 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
49 return X86::isUNPCKH_v_undef_Mask(N);
52 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
53 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
54 return X86::isUNPCKL_v_undef_Mask(N);
57 // Patterns for shuffling.
58 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
59 return X86::isPSHUFDMask(N);
60 }], MMX_SHUFFLE_get_shuf_imm>;
62 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
63 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
64 return X86::isMOVLMask(N);
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 let isTwoAddress = 1 in {
72 // MMXI_binop_rm - Simple MMX binary operator.
73 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
74 ValueType OpVT, bit Commutable = 0> {
75 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
76 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
77 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
78 let isCommutable = Commutable;
80 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
82 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
84 (load_mmx addr:$src2)))))]>;
87 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
89 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
91 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
92 let isCommutable = Commutable;
94 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
96 [(set VR64:$dst, (IntId VR64:$src1,
97 (bitconvert (load_mmx addr:$src2))))]>;
100 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
102 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
103 // to collapse (bitconvert VT to VT) into its operand.
105 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
106 bit Commutable = 0> {
107 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
108 (ins VR64:$src1, VR64:$src2),
109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
110 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
111 let isCommutable = Commutable;
113 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
114 (ins VR64:$src1, i64mem:$src2),
115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
117 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
120 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
121 string OpcodeStr, Intrinsic IntId,
123 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
124 (ins VR64:$src1, VR64:$src2),
125 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
126 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
127 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
128 (ins VR64:$src1, i64mem:$src2),
129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
130 [(set VR64:$dst, (IntId VR64:$src1,
131 (bitconvert (load_mmx addr:$src2))))]>;
132 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
133 (ins VR64:$src1, i32i8imm:$src2),
134 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
135 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
139 //===----------------------------------------------------------------------===//
140 // MMX EMMS & FEMMS Instructions
141 //===----------------------------------------------------------------------===//
143 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
144 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
146 //===----------------------------------------------------------------------===//
147 // MMX Scalar Instructions
148 //===----------------------------------------------------------------------===//
150 // Data Transfer Instructions
151 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
152 "movd\t{$src, $dst|$dst, $src}",
153 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
154 let isSimpleLoad = 1, isReMaterializable = 1 in
155 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
156 "movd\t{$src, $dst|$dst, $src}",
157 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
159 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
160 "movd\t{$src, $dst|$dst, $src}", []>;
162 let neverHasSideEffects = 1 in
163 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
164 "movd\t{$src, $dst|$dst, $src}", []>;
166 let neverHasSideEffects = 1 in
167 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg, (outs GR64:$dst), (ins VR64:$src),
168 "movd\t{$src, $dst|$dst, $src}", []>;
170 let neverHasSideEffects = 1 in
171 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
172 "movq\t{$src, $dst|$dst, $src}", []>;
173 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
174 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
175 "movq\t{$src, $dst|$dst, $src}",
176 [(set VR64:$dst, (load_mmx addr:$src))]>;
177 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
178 "movq\t{$src, $dst|$dst, $src}",
179 [(store (v1i64 VR64:$src), addr:$dst)]>;
181 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
182 "movdq2q\t{$src, $dst|$dst, $src}",
185 (i64 (vector_extract (v2i64 VR128:$src),
188 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
189 "movq2dq\t{$src, $dst|$dst, $src}",
191 (v2i64 (vector_shuffle immAllZerosV,
192 (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
193 MOVL_shuffle_mask)))]>;
195 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
196 "movntq\t{$src, $dst|$dst, $src}",
197 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
199 let AddedComplexity = 15 in
200 // movd to MMX register zero-extends
201 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
202 "movd\t{$src, $dst|$dst, $src}",
204 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
205 let AddedComplexity = 20 in
206 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
207 "movd\t{$src, $dst|$dst, $src}",
209 (v2i32 (X86vzmovl (v2i32
210 (scalar_to_vector (loadi32 addr:$src))))))]>;
212 // Arithmetic Instructions
215 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
216 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
217 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
218 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
220 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
221 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
223 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
224 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
227 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
228 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
229 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
230 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
232 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
233 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
235 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
236 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
239 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
241 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
242 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
243 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
246 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
248 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
249 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
251 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
252 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
254 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
255 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
257 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
259 // Logical Instructions
260 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
261 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
262 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
264 let isTwoAddress = 1 in {
265 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
266 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
267 "pandn\t{$src2, $dst|$dst, $src2}",
268 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
270 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
271 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
272 "pandn\t{$src2, $dst|$dst, $src2}",
273 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
274 (load addr:$src2))))]>;
277 // Shift Instructions
278 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
279 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
280 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
281 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
282 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
283 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
285 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
286 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
287 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
288 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
289 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
290 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
292 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
293 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
294 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
295 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
297 // Comparison Instructions
298 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
299 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
300 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
302 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
303 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
304 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
306 // Conversion Instructions
308 // -- Unpack Instructions
309 let isTwoAddress = 1 in {
310 // Unpack High Packed Data Instructions
311 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
312 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
313 "punpckhbw\t{$src2, $dst|$dst, $src2}",
315 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
316 MMX_UNPCKH_shuffle_mask)))]>;
317 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
318 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
319 "punpckhbw\t{$src2, $dst|$dst, $src2}",
321 (v8i8 (vector_shuffle VR64:$src1,
322 (bc_v8i8 (load_mmx addr:$src2)),
323 MMX_UNPCKH_shuffle_mask)))]>;
325 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
326 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
327 "punpckhwd\t{$src2, $dst|$dst, $src2}",
329 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
330 MMX_UNPCKH_shuffle_mask)))]>;
331 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
332 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
333 "punpckhwd\t{$src2, $dst|$dst, $src2}",
335 (v4i16 (vector_shuffle VR64:$src1,
336 (bc_v4i16 (load_mmx addr:$src2)),
337 MMX_UNPCKH_shuffle_mask)))]>;
339 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
340 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
341 "punpckhdq\t{$src2, $dst|$dst, $src2}",
343 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
344 MMX_UNPCKH_shuffle_mask)))]>;
345 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
346 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
347 "punpckhdq\t{$src2, $dst|$dst, $src2}",
349 (v2i32 (vector_shuffle VR64:$src1,
350 (bc_v2i32 (load_mmx addr:$src2)),
351 MMX_UNPCKH_shuffle_mask)))]>;
353 // Unpack Low Packed Data Instructions
354 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
355 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
356 "punpcklbw\t{$src2, $dst|$dst, $src2}",
358 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
359 MMX_UNPCKL_shuffle_mask)))]>;
360 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
361 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
362 "punpcklbw\t{$src2, $dst|$dst, $src2}",
364 (v8i8 (vector_shuffle VR64:$src1,
365 (bc_v8i8 (load_mmx addr:$src2)),
366 MMX_UNPCKL_shuffle_mask)))]>;
368 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
369 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
370 "punpcklwd\t{$src2, $dst|$dst, $src2}",
372 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
373 MMX_UNPCKL_shuffle_mask)))]>;
374 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
375 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
376 "punpcklwd\t{$src2, $dst|$dst, $src2}",
378 (v4i16 (vector_shuffle VR64:$src1,
379 (bc_v4i16 (load_mmx addr:$src2)),
380 MMX_UNPCKL_shuffle_mask)))]>;
382 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
383 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
384 "punpckldq\t{$src2, $dst|$dst, $src2}",
386 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
387 MMX_UNPCKL_shuffle_mask)))]>;
388 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
389 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
390 "punpckldq\t{$src2, $dst|$dst, $src2}",
392 (v2i32 (vector_shuffle VR64:$src1,
393 (bc_v2i32 (load_mmx addr:$src2)),
394 MMX_UNPCKL_shuffle_mask)))]>;
397 // -- Pack Instructions
398 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
399 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
400 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
402 // -- Shuffle Instructions
403 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
404 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
405 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
407 (v4i16 (vector_shuffle
409 MMX_PSHUFW_shuffle_mask:$src2)))]>;
410 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
411 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
412 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
414 (v4i16 (vector_shuffle
415 (bc_v4i16 (load_mmx addr:$src1)),
417 MMX_PSHUFW_shuffle_mask:$src2)))]>;
419 // -- Conversion Instructions
420 let neverHasSideEffects = 1 in {
421 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
422 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
424 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
425 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
427 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
428 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
430 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
431 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
433 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
434 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
436 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
437 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
439 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
440 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
442 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
443 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
445 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
446 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
448 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
449 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
451 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
452 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
454 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
455 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
456 } // end neverHasSideEffects
460 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
461 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
463 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
464 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
465 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
466 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
467 (iPTR imm:$src2)))]>;
468 let isTwoAddress = 1 in {
469 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
470 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
471 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
472 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
473 GR32:$src2, (iPTR imm:$src3))))]>;
474 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
475 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
476 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
478 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
479 (i32 (anyext (loadi16 addr:$src2))),
480 (iPTR imm:$src3))))]>;
484 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
485 "pmovmskb\t{$src, $dst|$dst, $src}",
486 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
490 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
491 "maskmovq\t{$mask, $src|$src, $mask}",
492 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
494 //===----------------------------------------------------------------------===//
495 // Alias Instructions
496 //===----------------------------------------------------------------------===//
498 // Alias instructions that map zero vector to pxor.
499 let isReMaterializable = 1 in {
500 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
502 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
503 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
504 "pcmpeqd\t$dst, $dst",
505 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
508 let Predicates = [HasMMX] in {
509 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
510 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
511 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
514 //===----------------------------------------------------------------------===//
515 // Non-Instruction Patterns
516 //===----------------------------------------------------------------------===//
518 // Store 64-bit integer vector values.
519 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
520 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
522 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
523 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
524 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
525 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
526 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
529 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
530 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
531 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
532 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
533 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
534 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
535 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
536 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
537 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
538 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
539 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
540 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
542 // 64-bit bit convert.
543 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
544 (MMX_MOVD64to64rr GR64:$src)>;
545 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
546 (MMX_MOVD64to64rr GR64:$src)>;
547 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
548 (MMX_MOVD64to64rr GR64:$src)>;
549 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
550 (MMX_MOVD64to64rr GR64:$src)>;
551 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
552 (MMX_MOVD64from64rr VR64:$src)>;
553 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
554 (MMX_MOVD64from64rr VR64:$src)>;
555 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
556 (MMX_MOVD64from64rr VR64:$src)>;
557 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
558 (MMX_MOVD64from64rr VR64:$src)>;
560 // Move scalar to XMM zero-extended
561 // movd to XMM register zero-extends
562 let AddedComplexity = 15 in {
563 def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))))),
564 (MMX_MOVZDI2PDIrr GR32:$src)>;
565 def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))))),
566 (MMX_MOVZDI2PDIrr GR32:$src)>;
569 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
570 // 8 or 16-bits matter.
571 def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
572 (MMX_MOVD64rr GR32:$src)>;
573 def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
574 (MMX_MOVD64rr GR32:$src)>;
576 // Patterns to perform canonical versions of vector shuffling.
577 let AddedComplexity = 10 in {
578 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
579 MMX_UNPCKL_v_undef_shuffle_mask)),
580 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
581 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
582 MMX_UNPCKL_v_undef_shuffle_mask)),
583 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
584 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
585 MMX_UNPCKL_v_undef_shuffle_mask)),
586 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
589 let AddedComplexity = 10 in {
590 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
591 MMX_UNPCKH_v_undef_shuffle_mask)),
592 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
593 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
594 MMX_UNPCKH_v_undef_shuffle_mask)),
595 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
596 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
597 MMX_UNPCKH_v_undef_shuffle_mask)),
598 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
601 // Patterns to perform vector shuffling with a zeroed out vector.
602 let AddedComplexity = 20 in {
603 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
604 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
605 MMX_UNPCKL_shuffle_mask)),
606 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
609 // Some special case PANDN patterns.
610 // FIXME: Get rid of these.
611 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
613 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
614 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
616 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
617 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
619 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
621 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
623 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
624 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
626 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
627 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
629 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
631 // Move MMX to lower 64-bit of XMM
632 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
633 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
635 // Move lower 64-bit of XMM to MMX.
636 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
638 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
639 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
641 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
642 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
644 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;