1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 // All instructions that use MMX should be in this file, even if they also use
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 let Sched = WriteVecALU in {
24 def MMX_INTALU_ITINS : OpndItins<
25 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
28 def MMX_INTALUQ_ITINS : OpndItins<
29 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM
32 def MMX_PHADDSUBW : OpndItins<
33 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM
36 def MMX_PHADDSUBD : OpndItins<
37 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM
41 let Sched = WriteVecIMul in
42 def MMX_PMUL_ITINS : OpndItins<
43 IIC_MMX_PMUL, IIC_MMX_PMUL
46 let Sched = WriteVecALU in {
47 def MMX_PSADBW_ITINS : OpndItins<
48 IIC_MMX_PSADBW, IIC_MMX_PSADBW
51 def MMX_MISC_FUNC_ITINS : OpndItins<
52 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG
56 def MMX_SHIFT_ITINS : ShiftOpndItins<
57 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI
60 let Sched = WriteShuffle in {
61 def MMX_UNPCK_H_ITINS : OpndItins<
62 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM
65 def MMX_UNPCK_L_ITINS : OpndItins<
66 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L
69 def MMX_PCK_ITINS : OpndItins<
70 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM
73 def MMX_PSHUF_ITINS : OpndItins<
74 IIC_MMX_PSHUF, IIC_MMX_PSHUF
78 let Sched = WriteCvtF2I in {
79 def MMX_CVT_PD_ITINS : OpndItins<
80 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM
83 def MMX_CVT_PS_ITINS : OpndItins<
84 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM
88 let Constraints = "$src1 = $dst" in {
89 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
90 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
91 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
92 OpndItins itins, bit Commutable = 0> {
93 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
94 (ins VR64:$src1, VR64:$src2),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
96 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
97 Sched<[itins.Sched]> {
98 let isCommutable = Commutable;
100 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
101 (ins VR64:$src1, i64mem:$src2),
102 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
103 [(set VR64:$dst, (IntId VR64:$src1,
104 (bitconvert (load_mmx addr:$src2))))],
105 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
108 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
109 string OpcodeStr, Intrinsic IntId,
110 Intrinsic IntId2, ShiftOpndItins itins> {
111 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
112 (ins VR64:$src1, VR64:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
115 Sched<[WriteVecShift]>;
116 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
117 (ins VR64:$src1, i64mem:$src2),
118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
119 [(set VR64:$dst, (IntId VR64:$src1,
120 (bitconvert (load_mmx addr:$src2))))],
121 itins.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>;
122 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
123 (ins VR64:$src1, i32i8imm:$src2),
124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
125 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))], itins.ri>,
126 Sched<[WriteVecShift]>;
130 /// Unary MMX instructions requiring SSSE3.
131 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
132 Intrinsic IntId64, OpndItins itins> {
133 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
134 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
135 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>,
136 Sched<[itins.Sched]>;
138 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
141 (IntId64 (bitconvert (memopmmx addr:$src))))],
142 itins.rm>, Sched<[itins.Sched.Folded]>;
145 /// Binary MMX instructions requiring SSSE3.
146 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
147 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
148 Intrinsic IntId64, OpndItins itins> {
149 let isCommutable = 0 in
150 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
151 (ins VR64:$src1, VR64:$src2),
152 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
153 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>,
154 Sched<[itins.Sched]>;
155 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
156 (ins VR64:$src1, i64mem:$src2),
157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
160 (bitconvert (memopmmx addr:$src2))))], itins.rm>,
161 Sched<[itins.Sched.Folded, ReadAfterLd]>;
165 /// PALIGN MMX instructions (require SSSE3).
166 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
167 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
168 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
169 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
170 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
171 def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
172 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
173 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
174 [(set VR64:$dst, (IntId VR64:$src1,
175 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
178 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
179 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
180 string asm, OpndItins itins, Domain d> {
181 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
182 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
183 Sched<[itins.Sched]>;
184 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
185 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>,
186 Sched<[itins.Sched.Folded]>;
189 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
190 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
191 PatFrag ld_frag, string asm, Domain d> {
192 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
193 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
195 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
196 (ins DstRC:$src1, x86memop:$src2), asm,
197 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
201 //===----------------------------------------------------------------------===//
202 // MMX EMMS Instruction
203 //===----------------------------------------------------------------------===//
205 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
206 [(int_x86_mmx_emms)]>;
208 //===----------------------------------------------------------------------===//
209 // MMX Scalar Instructions
210 //===----------------------------------------------------------------------===//
212 // Data Transfer Instructions
213 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
214 "movd\t{$src, $dst|$dst, $src}",
216 (x86mmx (scalar_to_vector GR32:$src)))],
217 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
218 let canFoldAsLoad = 1 in
219 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
220 "movd\t{$src, $dst|$dst, $src}",
222 (x86mmx (scalar_to_vector (loadi32 addr:$src))))],
223 IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>;
225 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
226 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>,
229 // Low word of MMX to GPR.
230 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
231 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
232 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
233 "movd\t{$src, $dst|$dst, $src}",
235 (MMX_X86movd2w (x86mmx VR64:$src)))],
236 IIC_MMX_MOV_REG_MM>, Sched<[WriteMove]>;
238 let neverHasSideEffects = 1 in
239 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
240 "movd\t{$src, $dst|$dst, $src}",
241 [], IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
243 // These are 64 bit moves, but since the OS X assembler doesn't
244 // recognize a register-register movq, we write them as
246 let SchedRW = [WriteMove] in {
247 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
248 (outs GR64:$dst), (ins VR64:$src),
249 "movd\t{$src, $dst|$dst, $src}",
251 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>;
252 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
253 "movd\t{$src, $dst|$dst, $src}",
255 (bitconvert GR64:$src))], IIC_MMX_MOV_MM_RM>;
256 let neverHasSideEffects = 1 in
257 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
258 "movq\t{$src, $dst|$dst, $src}", [],
262 let SchedRW = [WriteLoad] in {
263 let canFoldAsLoad = 1 in
264 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
265 "movq\t{$src, $dst|$dst, $src}",
266 [(set VR64:$dst, (load_mmx addr:$src))],
268 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
269 "movq\t{$src, $dst|$dst, $src}",
270 [(store (x86mmx VR64:$src), addr:$dst)],
274 let SchedRW = [WriteMove] in {
275 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
276 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
279 (i64 (vector_extract (v2i64 VR128:$src),
283 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
284 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
288 (i64 (bitconvert (x86mmx VR64:$src))))))],
291 let neverHasSideEffects = 1 in
292 def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
293 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
294 [], IIC_MMX_MOVQ_RR>;
296 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
297 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
298 [], IIC_MMX_MOVQ_RR>;
301 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
302 "movntq\t{$src, $dst|$dst, $src}",
303 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)],
304 IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>;
306 let AddedComplexity = 15 in
307 // movd to MMX register zero-extends
308 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
309 "movd\t{$src, $dst|$dst, $src}",
311 (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))],
312 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
313 let AddedComplexity = 20 in
314 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
316 "movd\t{$src, $dst|$dst, $src}",
318 (x86mmx (X86vzmovl (x86mmx
319 (scalar_to_vector (loadi32 addr:$src))))))],
320 IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>;
322 // Arithmetic Instructions
323 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
325 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
327 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
330 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
331 MMX_INTALU_ITINS, 1>;
332 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
333 MMX_INTALU_ITINS, 1>;
334 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
335 MMX_INTALU_ITINS, 1>;
336 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
337 MMX_INTALUQ_ITINS, 1>;
338 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
339 MMX_INTALU_ITINS, 1>;
340 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
341 MMX_INTALU_ITINS, 1>;
343 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
344 MMX_INTALU_ITINS, 1>;
345 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
346 MMX_INTALU_ITINS, 1>;
348 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
350 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
352 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
357 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
359 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
360 MMX_INTALU_ITINS, 1>;
361 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
362 MMX_INTALU_ITINS, 1>;
363 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
364 MMX_INTALUQ_ITINS, 1>;
366 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
367 MMX_INTALU_ITINS, 1>;
368 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
369 MMX_INTALU_ITINS, 1>;
371 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
372 MMX_INTALU_ITINS, 1>;
373 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
374 MMX_INTALU_ITINS, 1>;
376 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
378 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
380 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
384 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
387 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
389 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
391 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
393 let isCommutable = 1 in
394 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
395 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>;
398 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
401 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
402 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>;
403 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
404 MMX_MISC_FUNC_ITINS, 1>;
405 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
406 MMX_MISC_FUNC_ITINS, 1>;
408 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
409 MMX_MISC_FUNC_ITINS, 1>;
410 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
411 MMX_MISC_FUNC_ITINS, 1>;
413 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
414 MMX_MISC_FUNC_ITINS, 1>;
415 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
416 MMX_MISC_FUNC_ITINS, 1>;
418 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
419 MMX_PSADBW_ITINS, 1>;
421 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
422 MMX_MISC_FUNC_ITINS>;
423 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
424 MMX_MISC_FUNC_ITINS>;
425 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
426 MMX_MISC_FUNC_ITINS>;
427 let Constraints = "$src1 = $dst" in
428 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
430 // Logical Instructions
431 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
432 MMX_INTALU_ITINS, 1>;
433 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
434 MMX_INTALU_ITINS, 1>;
435 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
436 MMX_INTALU_ITINS, 1>;
437 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
440 // Shift Instructions
441 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
442 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
444 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
445 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
447 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
448 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
451 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
452 int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
454 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
455 int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
457 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
458 int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
461 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
462 int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
464 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
465 int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
468 // Comparison Instructions
469 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
471 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
473 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
476 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
478 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
480 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
483 // -- Unpack Instructions
484 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
485 int_x86_mmx_punpckhbw,
487 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
488 int_x86_mmx_punpckhwd,
490 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
491 int_x86_mmx_punpckhdq,
493 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
494 int_x86_mmx_punpcklbw,
496 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
497 int_x86_mmx_punpcklwd,
499 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
500 int_x86_mmx_punpckldq,
503 // -- Pack Instructions
504 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
506 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
508 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
511 // -- Shuffle Instructions
512 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
515 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
516 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
517 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
519 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))],
520 IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
521 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
522 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
523 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
525 (int_x86_sse_pshuf_w (load_mmx addr:$src1),
527 IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>;
532 // -- Conversion Instructions
533 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
534 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
535 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
536 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
537 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
538 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
539 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
540 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
541 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
542 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
543 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
544 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
545 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
546 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
547 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
548 let Constraints = "$src1 = $dst" in {
549 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
550 int_x86_sse_cvtpi2ps,
551 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
552 SSEPackedSingle>, TB;
556 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
557 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
558 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
559 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
561 IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
562 let Constraints = "$src1 = $dst" in {
563 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
565 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
566 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
567 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
568 GR32:$src2, (iPTR imm:$src3)))],
569 IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
571 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
573 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
574 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
575 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
576 (i32 (anyext (loadi16 addr:$src2))),
578 IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
582 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
583 "pmovmskb\t{$src, $dst|$dst, $src}",
585 (int_x86_mmx_pmovmskb VR64:$src))]>;
588 // Low word of XMM to MMX.
589 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
590 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
592 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
593 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
595 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
596 (x86mmx (MMX_MOVQ64rm addr:$src))>;
599 let SchedRW = [WriteShuffle] in {
601 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
602 "maskmovq\t{$mask, $src|$src, $mask}",
603 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)],
606 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
607 "maskmovq\t{$mask, $src|$src, $mask}",
608 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)],
612 // 64-bit bit convert.
613 let Predicates = [HasSSE2] in {
614 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
615 (MMX_MOVD64to64rr GR64:$src)>;
616 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
617 (MMX_MOVD64from64rr VR64:$src)>;
618 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
619 (MMX_MOVQ2FR64rr VR64:$src)>;
620 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
621 (MMX_MOVFR642Qrr FR64:$src)>;