1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 let Constraints = "$src1 = $dst" in {
21 // MMXI_binop_rm - Simple MMX binary operator based on llvm operator.
22 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 ValueType OpVT, bit Commutable = 0> {
24 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
25 (ins VR64:$src1, VR64:$src2),
26 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
27 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
28 let isCommutable = Commutable;
30 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
31 (ins VR64:$src1, i64mem:$src2),
32 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
33 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
35 (load_mmx addr:$src2)))))]>;
38 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic, with a
39 // different name for the generated instructions than MMXI_binop_rm uses.
40 // Thus int and rm can coexist for different implementations of the same
41 // instruction. This is temporary during transition to intrinsic-only
42 // implementation; eventually the non-intrinsic forms will go away. When
43 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
44 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
46 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
47 (ins VR64:$src1, VR64:$src2),
48 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
49 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
50 let isCommutable = Commutable;
52 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
53 (ins VR64:$src1, i64mem:$src2),
54 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
55 [(set VR64:$dst, (IntId VR64:$src1,
56 (bitconvert (load_mmx addr:$src2))))]>;
59 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
61 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
62 // to collapse (bitconvert VT to VT) into its operand.
64 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
66 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
67 (ins VR64:$src1, VR64:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
70 let isCommutable = Commutable;
72 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
73 (ins VR64:$src1, i64mem:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
76 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
79 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
80 string OpcodeStr, Intrinsic IntId,
82 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
83 (ins VR64:$src1, VR64:$src2),
84 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
85 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
86 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
87 (ins VR64:$src1, i64mem:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
89 [(set VR64:$dst, (IntId VR64:$src1,
90 (bitconvert (load_mmx addr:$src2))))]>;
91 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
92 (ins VR64:$src1, i32i8imm:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
94 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
98 //===----------------------------------------------------------------------===//
99 // MMX EMMS & FEMMS Instructions
100 //===----------------------------------------------------------------------===//
102 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
103 [(int_x86_mmx_emms)]>;
104 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
105 [(int_x86_mmx_femms)]>;
107 //===----------------------------------------------------------------------===//
108 // MMX Scalar Instructions
109 //===----------------------------------------------------------------------===//
111 // Data Transfer Instructions
112 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
113 "movd\t{$src, $dst|$dst, $src}",
115 (v2i32 (scalar_to_vector GR32:$src)))]>;
116 let canFoldAsLoad = 1, isReMaterializable = 1 in
117 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
118 "movd\t{$src, $dst|$dst, $src}",
120 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
122 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
123 "movd\t{$src, $dst|$dst, $src}", []>;
124 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
125 "movd\t{$src, $dst|$dst, $src}", []>;
127 let neverHasSideEffects = 1 in
128 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
129 "movd\t{$src, $dst|$dst, $src}",
132 let neverHasSideEffects = 1 in
133 // These are 64 bit moves, but since the OS X assembler doesn't
134 // recognize a register-register movq, we write them as
136 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
137 (outs GR64:$dst), (ins VR64:$src),
138 "movd\t{$src, $dst|$dst, $src}", []>;
139 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
140 "movd\t{$src, $dst|$dst, $src}",
142 (v1i64 (scalar_to_vector GR64:$src)))]>;
144 let neverHasSideEffects = 1 in
145 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
146 "movq\t{$src, $dst|$dst, $src}", []>;
147 let canFoldAsLoad = 1, isReMaterializable = 1 in
148 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
149 "movq\t{$src, $dst|$dst, $src}",
150 [(set VR64:$dst, (load_mmx addr:$src))]>;
151 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
152 "movq\t{$src, $dst|$dst, $src}",
153 [(store (v1i64 VR64:$src), addr:$dst)]>;
155 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
156 "movdq2q\t{$src, $dst|$dst, $src}",
159 (i64 (vector_extract (v2i64 VR128:$src),
162 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
163 "movq2dq\t{$src, $dst|$dst, $src}",
166 (v2i64 (scalar_to_vector
167 (i64 (bitconvert (v1i64 VR64:$src)))))))]>;
169 let neverHasSideEffects = 1 in
170 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
171 "movq2dq\t{$src, $dst|$dst, $src}", []>;
173 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
174 "movdq2q\t{$src, $dst|$dst, $src}", []>;
176 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
177 "movntq\t{$src, $dst|$dst, $src}",
178 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
180 let AddedComplexity = 15 in
181 // movd to MMX register zero-extends
182 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
183 "movd\t{$src, $dst|$dst, $src}",
185 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
186 let AddedComplexity = 20 in
187 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
189 "movd\t{$src, $dst|$dst, $src}",
191 (v2i32 (X86vzmovl (v2i32
192 (scalar_to_vector (loadi32 addr:$src))))))]>;
194 // Arithmetic Instructions
197 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>,
198 MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
199 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>,
200 MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
201 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>,
202 MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
203 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>,
204 MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
205 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
206 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
208 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
209 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
212 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>,
213 MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
214 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>,
215 MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>;
216 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>,
217 MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>;
218 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>,
219 MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>;
221 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
222 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
224 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
225 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
228 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
229 MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
231 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
232 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
233 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
236 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
238 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
239 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
241 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
242 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
244 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
245 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
247 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
249 // Logical Instructions
250 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>,
251 MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
252 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>,
253 MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>;
254 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>,
255 MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>;
256 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 1>;
258 let Constraints = "$src1 = $dst" in {
259 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
260 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
261 "pandn\t{$src2, $dst|$dst, $src2}",
262 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
264 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
265 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
266 "pandn\t{$src2, $dst|$dst, $src2}",
267 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
268 (load addr:$src2))))]>;
271 // Shift Instructions
272 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
273 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
274 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
275 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
276 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
277 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
279 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
280 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
281 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
282 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
283 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
284 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
286 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
287 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
288 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
289 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
291 // Shift up / down and insert zero's.
292 def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
293 (MMX_PSLLQri VR64:$src, (GetLo32XForm imm:$amt))>;
294 def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
295 (MMX_PSRLQri VR64:$src, (GetLo32XForm imm:$amt))>;
297 // Comparison Instructions
298 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
299 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
300 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
302 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
303 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
304 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
306 // Conversion Instructions
308 // -- Unpack Instructions
309 let Constraints = "$src1 = $dst" in {
310 // Unpack High Packed Data Instructions
311 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
312 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
313 "punpckhbw\t{$src2, $dst|$dst, $src2}",
315 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
316 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
317 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
318 "punpckhbw\t{$src2, $dst|$dst, $src2}",
320 (v8i8 (mmx_unpckh VR64:$src1,
321 (bc_v8i8 (load_mmx addr:$src2)))))]>;
323 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
324 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
325 "punpckhwd\t{$src2, $dst|$dst, $src2}",
327 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
328 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
329 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
330 "punpckhwd\t{$src2, $dst|$dst, $src2}",
332 (v4i16 (mmx_unpckh VR64:$src1,
333 (bc_v4i16 (load_mmx addr:$src2)))))]>;
335 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
336 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
337 "punpckhdq\t{$src2, $dst|$dst, $src2}",
339 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
340 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
341 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
342 "punpckhdq\t{$src2, $dst|$dst, $src2}",
344 (v2i32 (mmx_unpckh VR64:$src1,
345 (bc_v2i32 (load_mmx addr:$src2)))))]>;
347 // Unpack Low Packed Data Instructions
348 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
349 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
350 "punpcklbw\t{$src2, $dst|$dst, $src2}",
352 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
353 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
354 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
355 "punpcklbw\t{$src2, $dst|$dst, $src2}",
357 (v8i8 (mmx_unpckl VR64:$src1,
358 (bc_v8i8 (load_mmx addr:$src2)))))]>;
360 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
361 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
362 "punpcklwd\t{$src2, $dst|$dst, $src2}",
364 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
365 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
366 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
367 "punpcklwd\t{$src2, $dst|$dst, $src2}",
369 (v4i16 (mmx_unpckl VR64:$src1,
370 (bc_v4i16 (load_mmx addr:$src2)))))]>;
372 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
373 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
374 "punpckldq\t{$src2, $dst|$dst, $src2}",
376 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
377 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
378 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
379 "punpckldq\t{$src2, $dst|$dst, $src2}",
381 (v2i32 (mmx_unpckl VR64:$src1,
382 (bc_v2i32 (load_mmx addr:$src2)))))]>;
384 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
385 int_x86_mmx_punpckhbw>;
386 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
387 int_x86_mmx_punpckhwd>;
388 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
389 int_x86_mmx_punpckhdq>;
390 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
391 int_x86_mmx_punpcklbw>;
392 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
393 int_x86_mmx_punpcklwd>;
394 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
395 int_x86_mmx_punpckldq>;
397 // -- Pack Instructions
398 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
399 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
400 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
402 // -- Shuffle Instructions
403 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
404 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
405 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
407 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
408 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
409 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
410 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
412 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
415 // -- Conversion Instructions
416 let neverHasSideEffects = 1 in {
417 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
418 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
420 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
422 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
424 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
425 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
427 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
429 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
431 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
432 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
434 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
436 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
438 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
439 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
441 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
442 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
444 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
445 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
447 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
449 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
451 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
452 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
454 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
455 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
456 } // end neverHasSideEffects
458 // Intrinsic versions.
459 def MMX_CVTPD2PIirr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
460 "cvtpd2pi\t{$src, $dst|$dst, $src}",
461 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
462 def MMX_CVTPD2PIirm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
464 "cvtpd2pi\t{$src, $dst|$dst, $src}",
466 (int_x86_sse_cvtpd2pi
467 (bitconvert (loadv2i64 addr:$src))))]>;
468 def MMX_CVTPI2PDirr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
469 "cvtpi2pd\t{$src, $dst|$dst, $src}",
470 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
471 let Constraints = "$src1 = $dst" in {
472 def MMX_CVTPI2PSirr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst),
473 (ins VR128:$src1, VR64:$src2),
474 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 (int_x86_sse_cvtpi2ps VR128:$src1, VR64:$src2))]>;
477 def MMX_CVTPI2PSirm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
478 (ins VR128:$src1, i64mem:$src2),
479 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
481 (int_x86_sse_cvtpi2ps VR128:$src1,
482 (bitconvert (load_mmx addr:$src2))))]>;
484 def MMX_CVTPS2PIirr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
485 "cvtps2pi\t{$src, $dst|$dst, $src}",
486 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
487 def MMX_CVTPS2PIirm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
488 "cvtps2pi\t{$src, $dst|$dst, $src}",
490 (int_x86_sse_cvtps2pi
491 (bitconvert (load_mmx addr:$src))))]>;
492 def MMX_CVTTPD2PIirr: MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
493 "cvttpd2pi\t{$src, $dst|$dst, $src}",
494 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
495 def MMX_CVTTPD2PIirm: MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
497 "cvttpd2pi\t{$src, $dst|$dst, $src}",
499 (int_x86_sse_cvtpd2pi
500 (bitconvert (loadv2i64 addr:$src))))]>;
501 def MMX_CVTTPS2PIirr: MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
502 "cvttps2pi\t{$src, $dst|$dst, $src}",
503 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
504 def MMX_CVTTPS2PIirm: MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
505 "cvttps2pi\t{$src, $dst|$dst, $src}",
507 (int_x86_sse_cvtpd2pi
508 (bitconvert (load_mmx addr:$src))))]>;
511 def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW",
512 SDTypeProfile<1, 3, [SDTCisVT<0, v4i16>, SDTCisSameAs<0,1>,
513 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
516 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
517 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
518 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
519 [(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1),
520 (iPTR imm:$src2)))]>;
521 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
522 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
523 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
524 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
525 (iPTR imm:$src2)))]>;
526 let Constraints = "$src1 = $dst" in {
527 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
529 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
530 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
531 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
532 GR32:$src2,(iPTR imm:$src3))))]>;
533 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
535 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
536 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
538 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
539 (i32 (anyext (loadi16 addr:$src2))),
540 (iPTR imm:$src3))))]>;
541 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
543 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
544 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
545 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
546 GR32:$src2, (iPTR imm:$src3)))]>;
548 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
550 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
551 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
552 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
553 (i32 (anyext (loadi16 addr:$src2))),
554 (iPTR imm:$src3)))]>;
557 // MMX to XMM for vector types
558 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
559 [SDTCisVT<0, v2i64>, SDTCisVT<1, v1i64>]>>;
561 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
562 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
564 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
565 (v2i64 (MOVQI2PQIrm addr:$src))>;
567 def : Pat<(v2i64 (MMX_X86movq2dq (v1i64 (bitconvert
568 (v2i32 (scalar_to_vector (loadi32 addr:$src))))))),
569 (v2i64 (MOVDI2PDIrm addr:$src))>;
572 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
573 "pmovmskb\t{$src, $dst|$dst, $src}",
574 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
578 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
579 "maskmovq\t{$mask, $src|$src, $mask}",
580 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
582 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
583 "maskmovq\t{$mask, $src|$src, $mask}",
584 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
586 //===----------------------------------------------------------------------===//
587 // Alias Instructions
588 //===----------------------------------------------------------------------===//
590 // Alias instructions that map zero vector to pxor.
591 let isReMaterializable = 1, isCodeGenOnly = 1 in {
592 // FIXME: Change encoding to pseudo.
593 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "",
594 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
595 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "",
596 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
599 let Predicates = [HasMMX] in {
600 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
601 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
602 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
605 //===----------------------------------------------------------------------===//
606 // Non-Instruction Patterns
607 //===----------------------------------------------------------------------===//
609 // Store 64-bit integer vector values.
610 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
611 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
612 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
613 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
614 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
615 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
616 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
617 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
620 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
621 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
622 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
623 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
624 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
625 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
626 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
627 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
628 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
629 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
630 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
631 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
633 // 64-bit bit convert.
634 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
635 (MMX_MOVD64to64rr GR64:$src)>;
636 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
637 (MMX_MOVD64to64rr GR64:$src)>;
638 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
639 (MMX_MOVD64to64rr GR64:$src)>;
640 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
641 (MMX_MOVD64to64rr GR64:$src)>;
642 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
643 (MMX_MOVD64from64rr VR64:$src)>;
644 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
645 (MMX_MOVD64from64rr VR64:$src)>;
646 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
647 (MMX_MOVD64from64rr VR64:$src)>;
648 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
649 (MMX_MOVD64from64rr VR64:$src)>;
650 def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
651 (MMX_MOVQ2FR64rr VR64:$src)>;
652 def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
653 (MMX_MOVQ2FR64rr VR64:$src)>;
654 def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
655 (MMX_MOVQ2FR64rr VR64:$src)>;
656 def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
657 (MMX_MOVQ2FR64rr VR64:$src)>;
658 def : Pat<(v1i64 (bitconvert (f64 FR64:$src))),
659 (MMX_MOVFR642Qrr FR64:$src)>;
660 def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
661 (MMX_MOVFR642Qrr FR64:$src)>;
662 def : Pat<(v4i16 (bitconvert (f64 FR64:$src))),
663 (MMX_MOVFR642Qrr FR64:$src)>;
664 def : Pat<(v8i8 (bitconvert (f64 FR64:$src))),
665 (MMX_MOVFR642Qrr FR64:$src)>;
667 let AddedComplexity = 20 in {
668 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
669 (MMX_MOVZDI2PDIrm addr:$src)>;
673 let AddedComplexity = 15 in {
674 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
675 (MMX_PUNPCKLDQrr VR64:$src, (v2i32 (MMX_V_SET0)))>;
678 // Patterns to perform canonical versions of vector shuffling.
679 let AddedComplexity = 10 in {
680 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
681 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
682 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
683 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
684 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
685 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
688 let AddedComplexity = 10 in {
689 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
690 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
691 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
692 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
693 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
694 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
697 // Some special case PANDN patterns.
698 // FIXME: Get rid of these.
699 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
701 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
702 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
704 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
706 // Move MMX to lower 64-bit of XMM
707 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
708 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
709 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
710 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
711 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
712 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
713 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
714 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
716 // Move lower 64-bit of XMM to MMX.
717 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
719 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
720 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
722 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
723 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
725 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
727 // Patterns for vector comparisons
728 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
729 (MMX_PCMPEQBirr VR64:$src1, VR64:$src2)>;
730 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
731 (MMX_PCMPEQBirm VR64:$src1, addr:$src2)>;
732 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
733 (MMX_PCMPEQWirr VR64:$src1, VR64:$src2)>;
734 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
735 (MMX_PCMPEQWirm VR64:$src1, addr:$src2)>;
736 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
737 (MMX_PCMPEQDirr VR64:$src1, VR64:$src2)>;
738 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
739 (MMX_PCMPEQDirm VR64:$src1, addr:$src2)>;
741 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
742 (MMX_PCMPGTBirr VR64:$src1, VR64:$src2)>;
743 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
744 (MMX_PCMPGTBirm VR64:$src1, addr:$src2)>;
745 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
746 (MMX_PCMPGTWirr VR64:$src1, VR64:$src2)>;
747 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
748 (MMX_PCMPGTWirm VR64:$src1, addr:$src2)>;
749 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
750 (MMX_PCMPGTDirr VR64:$src1, VR64:$src2)>;
751 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
752 (MMX_PCMPGTDirm VR64:$src1, addr:$src2)>;
754 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
755 // instruction selection into a branch sequence.
756 let Uses = [EFLAGS], usesCustomInserter = 1 in {
757 def CMOV_V1I64 : I<0, Pseudo,
758 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
759 "#CMOV_V1I64 PSEUDO!",
761 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,