1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 // All instructions that use MMX should be in this file, even if they also use
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 let Constraints = "$src1 = $dst" in {
24 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
25 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
26 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
28 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
29 (ins VR64:$src1, VR64:$src2),
30 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
31 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
32 let isCommutable = Commutable;
34 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
35 (ins VR64:$src1, i64mem:$src2),
36 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
37 [(set VR64:$dst, (IntId VR64:$src1,
38 (bitconvert (load_mmx addr:$src2))))]>;
41 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
42 string OpcodeStr, Intrinsic IntId,
44 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
45 (ins VR64:$src1, VR64:$src2),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
48 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
49 (ins VR64:$src1, i64mem:$src2),
50 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
51 [(set VR64:$dst, (IntId VR64:$src1,
52 (bitconvert (load_mmx addr:$src2))))]>;
53 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
54 (ins VR64:$src1, i32i8imm:$src2),
55 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
56 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
60 /// Unary MMX instructions requiring SSSE3.
61 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
63 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
64 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
65 [(set VR64:$dst, (IntId64 VR64:$src))]>;
67 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
70 (IntId64 (bitconvert (memopmmx addr:$src))))]>;
73 /// Binary MMX instructions requiring SSSE3.
74 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
75 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
77 let isCommutable = 0 in
78 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
79 (ins VR64:$src1, VR64:$src2),
80 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
82 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
83 (ins VR64:$src1, i64mem:$src2),
84 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
87 (bitconvert (memopmmx addr:$src2))))]>;
91 /// PALIGN MMX instructions (require SSSE3).
92 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
93 def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
94 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
95 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
96 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
97 def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
98 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
99 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
100 [(set VR64:$dst, (IntId VR64:$src1,
101 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
104 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
105 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
106 string asm, Domain d> {
107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
108 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
109 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
110 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
113 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
114 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
115 PatFrag ld_frag, string asm, Domain d> {
116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
117 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
118 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
119 (ins DstRC:$src1, x86memop:$src2), asm,
120 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
123 //===----------------------------------------------------------------------===//
124 // MMX EMMS & FEMMS Instructions
125 //===----------------------------------------------------------------------===//
127 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
128 [(int_x86_mmx_emms)]>;
129 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
130 [(int_x86_mmx_femms)]>;
132 //===----------------------------------------------------------------------===//
133 // MMX Scalar Instructions
134 //===----------------------------------------------------------------------===//
136 // Data Transfer Instructions
137 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
138 "movd\t{$src, $dst|$dst, $src}",
140 (x86mmx (scalar_to_vector GR32:$src)))]>;
141 let canFoldAsLoad = 1 in
142 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
143 "movd\t{$src, $dst|$dst, $src}",
145 (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>;
147 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
148 "movd\t{$src, $dst|$dst, $src}", []>;
149 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
150 "movd\t{$src, $dst|$dst, $src}", []>;
152 let neverHasSideEffects = 1 in
153 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
154 "movd\t{$src, $dst|$dst, $src}",
157 // These are 64 bit moves, but since the OS X assembler doesn't
158 // recognize a register-register movq, we write them as
160 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
161 (outs GR64:$dst), (ins VR64:$src),
162 "movd\t{$src, $dst|$dst, $src}",
164 (bitconvert VR64:$src))]>;
165 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
166 "movd\t{$src, $dst|$dst, $src}",
168 (bitconvert GR64:$src))]>;
169 let neverHasSideEffects = 1 in
170 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
171 "movq\t{$src, $dst|$dst, $src}", []>;
172 let canFoldAsLoad = 1 in
173 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
174 "movq\t{$src, $dst|$dst, $src}",
175 [(set VR64:$dst, (load_mmx addr:$src))]>;
176 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
177 "movq\t{$src, $dst|$dst, $src}",
178 [(store (x86mmx VR64:$src), addr:$dst)]>;
180 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
181 "movdq2q\t{$src, $dst|$dst, $src}",
184 (i64 (vector_extract (v2i64 VR128:$src),
187 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
188 "movq2dq\t{$src, $dst|$dst, $src}",
190 (v2i64 (scalar_to_vector
191 (i64 (bitconvert (x86mmx VR64:$src))))))]>;
193 let neverHasSideEffects = 1 in
194 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
195 "movq2dq\t{$src, $dst|$dst, $src}", []>;
197 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
198 "movdq2q\t{$src, $dst|$dst, $src}", []>;
200 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
201 "movntq\t{$src, $dst|$dst, $src}",
202 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
204 let AddedComplexity = 15 in
205 // movd to MMX register zero-extends
206 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
207 "movd\t{$src, $dst|$dst, $src}",
209 (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))]>;
210 let AddedComplexity = 20 in
211 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
213 "movd\t{$src, $dst|$dst, $src}",
215 (x86mmx (X86vzmovl (x86mmx
216 (scalar_to_vector (loadi32 addr:$src))))))]>;
218 // Arithmetic Instructions
219 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b>;
220 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w>;
221 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d>;
223 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
224 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
225 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
226 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
227 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
228 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
230 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
231 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
233 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w>;
234 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d>;
235 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw>;
239 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
240 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>;
241 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>;
242 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>;
244 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
245 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
247 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
248 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
250 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w>;
251 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d>;
252 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw>;
255 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
257 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
258 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
259 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
260 let isCommutable = 1 in
261 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
262 int_x86_ssse3_pmul_hr_sw>;
265 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
267 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
268 int_x86_ssse3_pmadd_ub_sw>;
269 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
270 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
272 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
273 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
275 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
276 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
278 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
280 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b>;
281 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w>;
282 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d>;
283 let Constraints = "$src1 = $dst" in
284 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
286 // Logical Instructions
287 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
288 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>;
289 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>;
290 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 1>;
292 // Shift Instructions
293 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
294 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
295 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
296 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
297 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
298 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
300 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
301 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
302 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
303 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
304 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
305 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
307 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
308 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
309 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
310 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
312 // Comparison Instructions
313 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
314 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
315 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
317 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
318 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
319 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
321 // -- Unpack Instructions
322 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
323 int_x86_mmx_punpckhbw>;
324 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
325 int_x86_mmx_punpckhwd>;
326 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
327 int_x86_mmx_punpckhdq>;
328 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
329 int_x86_mmx_punpcklbw>;
330 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
331 int_x86_mmx_punpcklwd>;
332 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
333 int_x86_mmx_punpckldq>;
335 // -- Pack Instructions
336 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
337 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
338 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
340 // -- Shuffle Instructions
341 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b>;
343 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
344 (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
345 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
347 (int_x86_ssse3_pshuf_w VR64:$src1, imm:$src2))]>;
348 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
349 (outs VR64:$dst), (ins i64mem:$src1, i32i8imm:$src2),
350 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
352 (int_x86_ssse3_pshuf_w (load_mmx addr:$src1),
359 // -- Conversion Instructions
360 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
361 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
362 SSEPackedSingle>, TB;
363 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
364 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
365 SSEPackedDouble>, TB, OpSize;
366 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
367 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
368 SSEPackedSingle>, TB;
369 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
370 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
371 SSEPackedDouble>, TB, OpSize;
372 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
373 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
374 SSEPackedDouble>, TB, OpSize;
375 let Constraints = "$src1 = $dst" in {
376 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
377 int_x86_sse_cvtpi2ps,
378 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
379 SSEPackedSingle>, TB;
383 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
384 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
385 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
386 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
387 (iPTR imm:$src2)))]>;
388 let Constraints = "$src1 = $dst" in {
389 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
391 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
392 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
393 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
394 GR32:$src2, (iPTR imm:$src3)))]>;
396 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
398 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
399 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
400 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
401 (i32 (anyext (loadi16 addr:$src2))),
402 (iPTR imm:$src3)))]>;
406 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
407 "pmovmskb\t{$src, $dst|$dst, $src}",
409 (int_x86_mmx_pmovmskb VR64:$src))]>;
412 // MMX to XMM for vector types
413 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
414 [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
416 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
417 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
419 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
420 (v2i64 (MOVQI2PQIrm addr:$src))>;
422 def : Pat<(v2i64 (MMX_X86movq2dq
423 (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
424 (v2i64 (MOVDI2PDIrm addr:$src))>;
426 // Low word of XMM to MMX.
427 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
428 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
430 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
431 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
433 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
434 (x86mmx (MMX_MOVQ64rm addr:$src))>;
438 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
439 "maskmovq\t{$mask, $src|$src, $mask}",
440 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
442 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
443 "maskmovq\t{$mask, $src|$src, $mask}",
444 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
446 // 64-bit bit convert.
447 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
448 (MMX_MOVD64to64rr GR64:$src)>;
449 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
450 (MMX_MOVD64from64rr VR64:$src)>;
451 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
452 (MMX_MOVQ2FR64rr VR64:$src)>;
453 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
454 (MMX_MOVFR642Qrr FR64:$src)>;