1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 let Constraints = "$src1 = $dst" in {
21 // MMXI_binop_rm - Simple MMX binary operator.
22 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 ValueType OpVT, bit Commutable = 0> {
24 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
25 (ins VR64:$src1, VR64:$src2),
26 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
27 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
28 let isCommutable = Commutable;
30 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
31 (ins VR64:$src1, i64mem:$src2),
32 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
33 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
35 (load_mmx addr:$src2)))))]>;
38 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
40 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
41 (ins VR64:$src1, VR64:$src2),
42 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
43 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
44 let isCommutable = Commutable;
46 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
47 (ins VR64:$src1, i64mem:$src2),
48 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
49 [(set VR64:$dst, (IntId VR64:$src1,
50 (bitconvert (load_mmx addr:$src2))))]>;
53 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
55 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
56 // to collapse (bitconvert VT to VT) into its operand.
58 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
61 (ins VR64:$src1, VR64:$src2),
62 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
63 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
64 let isCommutable = Commutable;
66 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
67 (ins VR64:$src1, i64mem:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
70 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
73 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
74 string OpcodeStr, Intrinsic IntId,
76 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
77 (ins VR64:$src1, VR64:$src2),
78 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
79 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
80 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
81 (ins VR64:$src1, i64mem:$src2),
82 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
83 [(set VR64:$dst, (IntId VR64:$src1,
84 (bitconvert (load_mmx addr:$src2))))]>;
85 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
86 (ins VR64:$src1, i32i8imm:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
92 //===----------------------------------------------------------------------===//
93 // MMX EMMS & FEMMS Instructions
94 //===----------------------------------------------------------------------===//
96 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
97 [(int_x86_mmx_emms)]>;
98 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
99 [(int_x86_mmx_femms)]>;
101 //===----------------------------------------------------------------------===//
102 // MMX Scalar Instructions
103 //===----------------------------------------------------------------------===//
105 // Data Transfer Instructions
106 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
107 "movd\t{$src, $dst|$dst, $src}",
109 (v2i32 (scalar_to_vector GR32:$src)))]>;
110 let canFoldAsLoad = 1, isReMaterializable = 1 in
111 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
112 "movd\t{$src, $dst|$dst, $src}",
114 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
116 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
117 "movd\t{$src, $dst|$dst, $src}", []>;
118 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
119 "movd\t{$src, $dst|$dst, $src}", []>;
120 def MMX_MOVQ64gmr : MMXRI<0x7F, MRMDestMem, (outs),
121 (ins i64mem:$dst, VR64:$src),
122 "movq\t{$src, $dst|$dst, $src}", []>;
124 let neverHasSideEffects = 1 in
125 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
126 "movd\t{$src, $dst|$dst, $src}",
129 let neverHasSideEffects = 1 in
130 // These are 64 bit moves, but since the OS X assembler doesn't
131 // recognize a register-register movq, we write them as
133 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
134 (outs GR64:$dst), (ins VR64:$src),
135 "movd\t{$src, $dst|$dst, $src}", []>;
136 def MMX_MOVD64rrv164 : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
137 "movd\t{$src, $dst|$dst, $src}",
139 (v1i64 (scalar_to_vector GR64:$src)))]>;
141 let neverHasSideEffects = 1 in
142 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
143 "movq\t{$src, $dst|$dst, $src}", []>;
144 let canFoldAsLoad = 1, isReMaterializable = 1 in
145 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
146 "movq\t{$src, $dst|$dst, $src}",
147 [(set VR64:$dst, (load_mmx addr:$src))]>;
148 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
149 "movq\t{$src, $dst|$dst, $src}",
150 [(store (v1i64 VR64:$src), addr:$dst)]>;
152 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
153 "movdq2q\t{$src, $dst|$dst, $src}",
156 (i64 (vector_extract (v2i64 VR128:$src),
159 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
160 "movq2dq\t{$src, $dst|$dst, $src}",
163 (v2i64 (scalar_to_vector
164 (i64 (bitconvert (v1i64 VR64:$src)))))))]>;
166 let neverHasSideEffects = 1 in
167 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
168 "movq2dq\t{$src, $dst|$dst, $src}", []>;
170 def MMX_MOVFR642Qrr: SSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
171 "movdq2q\t{$src, $dst|$dst, $src}", []>;
173 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
174 "movntq\t{$src, $dst|$dst, $src}",
175 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
177 let AddedComplexity = 15 in
178 // movd to MMX register zero-extends
179 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
180 "movd\t{$src, $dst|$dst, $src}",
182 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
183 let AddedComplexity = 20 in
184 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
186 "movd\t{$src, $dst|$dst, $src}",
188 (v2i32 (X86vzmovl (v2i32
189 (scalar_to_vector (loadi32 addr:$src))))))]>;
191 // Arithmetic Instructions
194 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
195 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
196 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
197 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
199 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
200 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
202 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
203 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
206 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
207 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
208 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
209 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
211 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
212 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
214 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
215 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
218 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
220 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
221 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
222 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
225 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
227 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
228 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
230 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
231 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
233 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
234 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
236 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
238 // Logical Instructions
239 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
240 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
241 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
243 let Constraints = "$src1 = $dst" in {
244 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
245 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
246 "pandn\t{$src2, $dst|$dst, $src2}",
247 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
249 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
250 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
251 "pandn\t{$src2, $dst|$dst, $src2}",
252 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
253 (load addr:$src2))))]>;
256 // Shift Instructions
257 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
258 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
259 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
260 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
261 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
262 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
264 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
265 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
266 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
267 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
268 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
269 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
271 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
272 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
273 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
274 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
276 // Shift up / down and insert zero's.
277 def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
278 (MMX_PSLLQri VR64:$src, (GetLo32XForm imm:$amt))>;
279 def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
280 (MMX_PSRLQri VR64:$src, (GetLo32XForm imm:$amt))>;
282 // Comparison Instructions
283 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
284 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
285 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
287 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
288 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
289 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
291 // Conversion Instructions
293 // -- Unpack Instructions
294 let Constraints = "$src1 = $dst" in {
295 // Unpack High Packed Data Instructions
296 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
297 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
298 "punpckhbw\t{$src2, $dst|$dst, $src2}",
300 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
301 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
302 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
303 "punpckhbw\t{$src2, $dst|$dst, $src2}",
305 (v8i8 (mmx_unpckh VR64:$src1,
306 (bc_v8i8 (load_mmx addr:$src2)))))]>;
308 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
309 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
310 "punpckhwd\t{$src2, $dst|$dst, $src2}",
312 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
313 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
314 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
315 "punpckhwd\t{$src2, $dst|$dst, $src2}",
317 (v4i16 (mmx_unpckh VR64:$src1,
318 (bc_v4i16 (load_mmx addr:$src2)))))]>;
320 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
321 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
322 "punpckhdq\t{$src2, $dst|$dst, $src2}",
324 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
325 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
326 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
327 "punpckhdq\t{$src2, $dst|$dst, $src2}",
329 (v2i32 (mmx_unpckh VR64:$src1,
330 (bc_v2i32 (load_mmx addr:$src2)))))]>;
332 // Unpack Low Packed Data Instructions
333 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
334 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
335 "punpcklbw\t{$src2, $dst|$dst, $src2}",
337 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
338 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
339 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
340 "punpcklbw\t{$src2, $dst|$dst, $src2}",
342 (v8i8 (mmx_unpckl VR64:$src1,
343 (bc_v8i8 (load_mmx addr:$src2)))))]>;
345 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
346 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
347 "punpcklwd\t{$src2, $dst|$dst, $src2}",
349 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
350 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
351 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
352 "punpcklwd\t{$src2, $dst|$dst, $src2}",
354 (v4i16 (mmx_unpckl VR64:$src1,
355 (bc_v4i16 (load_mmx addr:$src2)))))]>;
357 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
358 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
359 "punpckldq\t{$src2, $dst|$dst, $src2}",
361 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
362 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
363 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
364 "punpckldq\t{$src2, $dst|$dst, $src2}",
366 (v2i32 (mmx_unpckl VR64:$src1,
367 (bc_v2i32 (load_mmx addr:$src2)))))]>;
370 // -- Pack Instructions
371 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
372 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
373 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
375 // -- Shuffle Instructions
376 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
377 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
378 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
380 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
381 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
382 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
383 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
385 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
388 // -- Conversion Instructions
389 let neverHasSideEffects = 1 in {
390 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
391 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
393 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
395 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
397 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
398 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
400 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
402 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
404 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
405 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
407 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
409 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
411 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
412 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
414 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
415 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
417 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
418 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
420 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
422 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
424 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
425 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
427 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
428 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
429 } // end neverHasSideEffects
433 def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW",
434 SDTypeProfile<1, 3, [SDTCisVT<0, v4i16>, SDTCisSameAs<0,1>,
435 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
438 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
439 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
440 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
441 [(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1),
442 (iPTR imm:$src2)))]>;
443 let Constraints = "$src1 = $dst" in {
444 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
446 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
447 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
448 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
449 GR32:$src2,(iPTR imm:$src3))))]>;
450 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
452 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
453 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
455 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
456 (i32 (anyext (loadi16 addr:$src2))),
457 (iPTR imm:$src3))))]>;
460 // MMX to XMM for vector types
461 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
462 [SDTCisVT<0, v2i64>, SDTCisVT<1, v1i64>]>>;
464 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
465 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
467 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
468 (v2i64 (MOVQI2PQIrm addr:$src))>;
470 def : Pat<(v2i64 (MMX_X86movq2dq (v1i64 (bitconvert
471 (v2i32 (scalar_to_vector (loadi32 addr:$src))))))),
472 (v2i64 (MOVDI2PDIrm addr:$src))>;
475 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
476 "pmovmskb\t{$src, $dst|$dst, $src}",
477 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
481 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
482 "maskmovq\t{$mask, $src|$src, $mask}",
483 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
485 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
486 "maskmovq\t{$mask, $src|$src, $mask}",
487 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
489 //===----------------------------------------------------------------------===//
490 // Alias Instructions
491 //===----------------------------------------------------------------------===//
493 // Alias instructions that map zero vector to pxor.
494 let isReMaterializable = 1, isCodeGenOnly = 1 in {
495 // FIXME: Change encoding to pseudo.
496 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "",
497 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
498 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "",
499 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
502 let Predicates = [HasMMX] in {
503 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
504 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
505 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
508 //===----------------------------------------------------------------------===//
509 // Non-Instruction Patterns
510 //===----------------------------------------------------------------------===//
512 // Store 64-bit integer vector values.
513 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
514 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
515 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
516 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
517 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
518 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
519 def : Pat<(store (v2f32 VR64:$src), addr:$dst),
520 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
522 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
525 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
526 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
527 def : Pat<(v8i8 (bitconvert (v2f32 VR64:$src))), (v8i8 VR64:$src)>;
528 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
529 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
530 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
531 def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16 VR64:$src)>;
532 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
533 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
534 def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32 VR64:$src)>;
535 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
536 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
537 def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32 VR64:$src)>;
538 def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32 VR64:$src)>;
539 def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32 VR64:$src)>;
540 def : Pat<(v2f32 (bitconvert (v8i8 VR64:$src))), (v2f32 VR64:$src)>;
541 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
542 def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64 VR64:$src)>;
543 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
544 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
546 // 64-bit bit convert.
547 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
548 (MMX_MOVD64to64rr GR64:$src)>;
549 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
550 (MMX_MOVD64to64rr GR64:$src)>;
551 def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
552 (MMX_MOVD64to64rr GR64:$src)>;
553 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
554 (MMX_MOVD64to64rr GR64:$src)>;
555 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
556 (MMX_MOVD64to64rr GR64:$src)>;
557 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
558 (MMX_MOVD64from64rr VR64:$src)>;
559 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
560 (MMX_MOVD64from64rr VR64:$src)>;
561 def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
562 (MMX_MOVD64from64rr VR64:$src)>;
563 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
564 (MMX_MOVD64from64rr VR64:$src)>;
565 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
566 (MMX_MOVD64from64rr VR64:$src)>;
567 def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
568 (MMX_MOVQ2FR64rr VR64:$src)>;
569 def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
570 (MMX_MOVQ2FR64rr VR64:$src)>;
571 def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
572 (MMX_MOVQ2FR64rr VR64:$src)>;
573 def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
574 (MMX_MOVQ2FR64rr VR64:$src)>;
575 def : Pat<(v1i64 (bitconvert (f64 FR64:$src))),
576 (MMX_MOVFR642Qrr FR64:$src)>;
577 def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
578 (MMX_MOVFR642Qrr FR64:$src)>;
579 def : Pat<(v4i16 (bitconvert (f64 FR64:$src))),
580 (MMX_MOVFR642Qrr FR64:$src)>;
581 def : Pat<(v8i8 (bitconvert (f64 FR64:$src))),
582 (MMX_MOVFR642Qrr FR64:$src)>;
584 let AddedComplexity = 20 in {
585 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
586 (MMX_MOVZDI2PDIrm addr:$src)>;
590 let AddedComplexity = 15 in {
591 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
592 (MMX_PUNPCKLDQrr VR64:$src, (v2i32 (MMX_V_SET0)))>;
595 // Patterns to perform canonical versions of vector shuffling.
596 let AddedComplexity = 10 in {
597 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
598 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
599 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
600 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
601 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
602 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
605 let AddedComplexity = 10 in {
606 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
607 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
608 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
609 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
610 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
611 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
614 // Some special case PANDN patterns.
615 // FIXME: Get rid of these.
616 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
618 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
619 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
621 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
623 // Move MMX to lower 64-bit of XMM
624 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
625 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
626 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
627 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
628 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
629 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
630 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
631 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
633 // Move lower 64-bit of XMM to MMX.
634 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
636 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
637 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
639 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
640 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
642 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
644 // Patterns for vector comparisons
645 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
646 (MMX_PCMPEQBrr VR64:$src1, VR64:$src2)>;
647 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
648 (MMX_PCMPEQBrm VR64:$src1, addr:$src2)>;
649 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
650 (MMX_PCMPEQWrr VR64:$src1, VR64:$src2)>;
651 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
652 (MMX_PCMPEQWrm VR64:$src1, addr:$src2)>;
653 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
654 (MMX_PCMPEQDrr VR64:$src1, VR64:$src2)>;
655 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
656 (MMX_PCMPEQDrm VR64:$src1, addr:$src2)>;
658 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
659 (MMX_PCMPGTBrr VR64:$src1, VR64:$src2)>;
660 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
661 (MMX_PCMPGTBrm VR64:$src1, addr:$src2)>;
662 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
663 (MMX_PCMPGTWrr VR64:$src1, VR64:$src2)>;
664 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
665 (MMX_PCMPGTWrm VR64:$src1, addr:$src2)>;
666 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
667 (MMX_PCMPGTDrr VR64:$src1, VR64:$src2)>;
668 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
669 (MMX_PCMPGTDrm VR64:$src1, addr:$src2)>;
671 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
672 // instruction selection into a branch sequence.
673 let Uses = [EFLAGS], usesCustomInserter = 1 in {
674 def CMOV_V1I64 : I<0, Pseudo,
675 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
676 "#CMOV_V1I64 PSEUDO!",
678 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,