1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Some 'special' instructions
17 let isImplicitDef = 1 in
18 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
20 [(set VR64:$dst, (v8i8 (undef)))]>,
23 // 64-bit vector undef's.
24 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
25 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
26 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
27 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
29 //===----------------------------------------------------------------------===//
30 // MMX Pattern Fragments
31 //===----------------------------------------------------------------------===//
33 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
35 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
36 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
37 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
38 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
46 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
47 return getI8Imm(X86::getShuffleSHUFImmediate(N));
50 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
51 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
52 return X86::isUNPCKHMask(N);
55 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
56 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
57 return X86::isUNPCKLMask(N);
60 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
61 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
62 return X86::isUNPCKH_v_undef_Mask(N);
65 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
66 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
67 return X86::isUNPCKL_v_undef_Mask(N);
70 // Patterns for shuffling.
71 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
72 return X86::isPSHUFDMask(N);
73 }], MMX_SHUFFLE_get_shuf_imm>;
75 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
76 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
77 return X86::isMOVLMask(N);
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 let isTwoAddress = 1 in {
85 // MMXI_binop_rm - Simple MMX binary operator.
86 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
87 ValueType OpVT, bit Commutable = 0> {
88 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
91 let isCommutable = Commutable;
93 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
97 (load_mmx addr:$src2)))))]>;
100 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
101 bit Commutable = 0> {
102 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
103 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
105 let isCommutable = Commutable;
107 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 [(set VR64:$dst, (IntId VR64:$src1,
110 (bitconvert (load_mmx addr:$src2))))]>;
113 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
115 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
116 // to collapse (bitconvert VT to VT) into its operand.
118 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
119 bit Commutable = 0> {
120 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
122 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
123 let isCommutable = Commutable;
125 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
128 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
131 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
132 string OpcodeStr, Intrinsic IntId> {
133 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
134 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
135 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
136 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
137 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
138 [(set VR64:$dst, (IntId VR64:$src1,
139 (bitconvert (load_mmx addr:$src2))))]>;
140 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
141 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
142 [(set VR64:$dst, (IntId VR64:$src1,
143 (scalar_to_vector (i32 imm:$src2))))]>;
147 //===----------------------------------------------------------------------===//
148 // MMX EMMS & FEMMS Instructions
149 //===----------------------------------------------------------------------===//
151 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
152 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
154 //===----------------------------------------------------------------------===//
155 // MMX Scalar Instructions
156 //===----------------------------------------------------------------------===//
158 // Data Transfer Instructions
159 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
160 "movd\t{$src, $dst|$dst, $src}",
161 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
162 let isSimpleLoad = 1, isReMaterializable = 1 in
163 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
164 "movd\t{$src, $dst|$dst, $src}",
165 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
167 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
168 "movd\t{$src, $dst|$dst, $src}", []>;
170 let neverHasSideEffects = 1 in
171 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
172 "movd\t{$src, $dst|$dst, $src}", []>;
174 let neverHasSideEffects = 1 in
175 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
176 "movq\t{$src, $dst|$dst, $src}", []>;
177 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
178 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
179 "movq\t{$src, $dst|$dst, $src}",
180 [(set VR64:$dst, (load_mmx addr:$src))]>;
181 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
182 "movq\t{$src, $dst|$dst, $src}",
183 [(store (v1i64 VR64:$src), addr:$dst)]>;
185 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
186 "movdq2q\t{$src, $dst|$dst, $src}",
188 (v1i64 (vector_extract (v2i64 VR128:$src),
191 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
192 "movq2dq\t{$src, $dst|$dst, $src}",
194 (bitconvert (v1i64 VR64:$src)))]>;
196 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
197 "movntq\t{$src, $dst|$dst, $src}",
198 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
200 let AddedComplexity = 15 in
201 // movd to MMX register zero-extends
202 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
203 "movd\t{$src, $dst|$dst, $src}",
205 (v2i32 (vector_shuffle immAllZerosV,
206 (v2i32 (scalar_to_vector GR32:$src)),
207 MMX_MOVL_shuffle_mask)))]>;
208 let AddedComplexity = 20 in
209 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
210 "movd\t{$src, $dst|$dst, $src}",
212 (v2i32 (vector_shuffle immAllZerosV,
213 (v2i32 (scalar_to_vector
214 (loadi32 addr:$src))),
215 MMX_MOVL_shuffle_mask)))]>;
217 // Arithmetic Instructions
220 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
221 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
222 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
223 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
225 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
226 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
228 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
229 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
232 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
233 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
234 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
235 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
237 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
238 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
240 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
241 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
244 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
246 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
247 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
248 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
251 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
253 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
254 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
256 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
257 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
259 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
260 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
262 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
264 // Logical Instructions
265 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
266 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
267 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
269 let isTwoAddress = 1 in {
270 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
271 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
272 "pandn\t{$src2, $dst|$dst, $src2}",
273 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
275 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
276 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
277 "pandn\t{$src2, $dst|$dst, $src2}",
278 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
279 (load addr:$src2))))]>;
282 // Shift Instructions
283 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
285 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
287 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
290 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
292 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
294 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
297 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
299 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
302 // Comparison Instructions
303 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
304 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
305 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
307 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
308 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
309 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
311 // Conversion Instructions
313 // -- Unpack Instructions
314 let isTwoAddress = 1 in {
315 // Unpack High Packed Data Instructions
316 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
317 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
318 "punpckhbw\t{$src2, $dst|$dst, $src2}",
320 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
321 MMX_UNPCKH_shuffle_mask)))]>;
322 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
323 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
324 "punpckhbw\t{$src2, $dst|$dst, $src2}",
326 (v8i8 (vector_shuffle VR64:$src1,
327 (bc_v8i8 (load_mmx addr:$src2)),
328 MMX_UNPCKH_shuffle_mask)))]>;
330 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
331 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
332 "punpckhwd\t{$src2, $dst|$dst, $src2}",
334 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
335 MMX_UNPCKH_shuffle_mask)))]>;
336 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
337 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
338 "punpckhwd\t{$src2, $dst|$dst, $src2}",
340 (v4i16 (vector_shuffle VR64:$src1,
341 (bc_v4i16 (load_mmx addr:$src2)),
342 MMX_UNPCKH_shuffle_mask)))]>;
344 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
345 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
346 "punpckhdq\t{$src2, $dst|$dst, $src2}",
348 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
349 MMX_UNPCKH_shuffle_mask)))]>;
350 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
351 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
352 "punpckhdq\t{$src2, $dst|$dst, $src2}",
354 (v2i32 (vector_shuffle VR64:$src1,
355 (bc_v2i32 (load_mmx addr:$src2)),
356 MMX_UNPCKH_shuffle_mask)))]>;
358 // Unpack Low Packed Data Instructions
359 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
360 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
361 "punpcklbw\t{$src2, $dst|$dst, $src2}",
363 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
364 MMX_UNPCKL_shuffle_mask)))]>;
365 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
366 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
367 "punpcklbw\t{$src2, $dst|$dst, $src2}",
369 (v8i8 (vector_shuffle VR64:$src1,
370 (bc_v8i8 (load_mmx addr:$src2)),
371 MMX_UNPCKL_shuffle_mask)))]>;
373 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
374 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
375 "punpcklwd\t{$src2, $dst|$dst, $src2}",
377 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
378 MMX_UNPCKL_shuffle_mask)))]>;
379 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
380 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
381 "punpcklwd\t{$src2, $dst|$dst, $src2}",
383 (v4i16 (vector_shuffle VR64:$src1,
384 (bc_v4i16 (load_mmx addr:$src2)),
385 MMX_UNPCKL_shuffle_mask)))]>;
387 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
388 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
389 "punpckldq\t{$src2, $dst|$dst, $src2}",
391 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
392 MMX_UNPCKL_shuffle_mask)))]>;
393 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
394 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
395 "punpckldq\t{$src2, $dst|$dst, $src2}",
397 (v2i32 (vector_shuffle VR64:$src1,
398 (bc_v2i32 (load_mmx addr:$src2)),
399 MMX_UNPCKL_shuffle_mask)))]>;
402 // -- Pack Instructions
403 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
404 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
405 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
407 // -- Shuffle Instructions
408 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
409 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
410 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
412 (v4i16 (vector_shuffle
414 MMX_PSHUFW_shuffle_mask:$src2)))]>;
415 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
416 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
417 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4i16 (vector_shuffle
420 (bc_v4i16 (load_mmx addr:$src1)),
422 MMX_PSHUFW_shuffle_mask:$src2)))]>;
424 // -- Conversion Instructions
425 let neverHasSideEffects = 1 in {
426 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
427 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
429 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
430 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
432 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
433 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
435 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
436 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
438 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
439 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
441 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
442 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
444 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
445 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
447 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
448 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
450 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
451 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
453 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
454 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
456 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
457 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
459 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
460 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
461 } // end neverHasSideEffects
465 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
466 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
468 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
469 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
470 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
471 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
472 (iPTR imm:$src2)))]>;
473 let isTwoAddress = 1 in {
474 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
475 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
476 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
477 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
478 GR32:$src2, (iPTR imm:$src3))))]>;
479 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
480 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
481 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
483 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
484 (i32 (anyext (loadi16 addr:$src2))),
485 (iPTR imm:$src3))))]>;
489 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
490 "pmovmskb\t{$src, $dst|$dst, $src}",
491 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
495 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
496 "maskmovq\t{$mask, $src|$src, $mask}",
497 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
499 //===----------------------------------------------------------------------===//
500 // Alias Instructions
501 //===----------------------------------------------------------------------===//
503 // Alias instructions that map zero vector to pxor.
504 let isReMaterializable = 1 in {
505 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
507 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
508 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
509 "pcmpeqd\t$dst, $dst",
510 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
513 //===----------------------------------------------------------------------===//
514 // Non-Instruction Patterns
515 //===----------------------------------------------------------------------===//
517 // Store 64-bit integer vector values.
518 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
519 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
520 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
521 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
522 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
523 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
524 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
525 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
528 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
529 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
530 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
531 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
532 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
533 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
534 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
535 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
536 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
537 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
538 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
539 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
541 // 64-bit bit convert.
542 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
543 (MMX_MOVD64to64rr GR64:$src)>;
544 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
545 (MMX_MOVD64to64rr GR64:$src)>;
546 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
547 (MMX_MOVD64to64rr GR64:$src)>;
548 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
549 (MMX_MOVD64to64rr GR64:$src)>;
551 // Move scalar to XMM zero-extended
552 // movd to XMM register zero-extends
553 let AddedComplexity = 15 in {
554 def : Pat<(v8i8 (vector_shuffle immAllZerosV_bc,
555 (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
556 MMX_MOVL_shuffle_mask)),
557 (MMX_MOVZDI2PDIrr GR32:$src)>;
558 def : Pat<(v4i16 (vector_shuffle immAllZerosV_bc,
559 (bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
560 MMX_MOVL_shuffle_mask)),
561 (MMX_MOVZDI2PDIrr GR32:$src)>;
564 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
565 // 8 or 16-bits matter.
566 def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
567 (MMX_MOVD64rr GR32:$src)>;
568 def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
569 (MMX_MOVD64rr GR32:$src)>;
571 // Patterns to perform canonical versions of vector shuffling.
572 let AddedComplexity = 10 in {
573 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
574 MMX_UNPCKL_v_undef_shuffle_mask)),
575 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
576 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
577 MMX_UNPCKL_v_undef_shuffle_mask)),
578 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
579 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
580 MMX_UNPCKL_v_undef_shuffle_mask)),
581 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
584 let AddedComplexity = 10 in {
585 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
586 MMX_UNPCKH_v_undef_shuffle_mask)),
587 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
588 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
589 MMX_UNPCKH_v_undef_shuffle_mask)),
590 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
591 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
592 MMX_UNPCKH_v_undef_shuffle_mask)),
593 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
596 // Patterns to perform vector shuffling with a zeroed out vector.
597 let AddedComplexity = 20 in {
598 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
599 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
600 MMX_UNPCKL_shuffle_mask)),
601 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
604 // Some special case PANDN patterns.
605 // FIXME: Get rid of these.
606 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
608 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
609 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
611 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
612 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
614 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
616 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
618 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
619 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
621 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
622 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
624 (MMX_PANDNrm VR64:$src1, addr:$src2)>;