1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // MMX Pattern Fragments
18 //===----------------------------------------------------------------------===//
20 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
22 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
23 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
24 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
25 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
27 //===----------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
31 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
33 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
34 return getI8Imm(X86::getShuffleSHUFImmediate(N));
37 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
38 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
39 return X86::isUNPCKHMask(N);
42 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
43 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
44 return X86::isUNPCKLMask(N);
47 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
48 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
49 return X86::isUNPCKH_v_undef_Mask(N);
52 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
53 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
54 return X86::isUNPCKL_v_undef_Mask(N);
57 // Patterns for shuffling.
58 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
59 return X86::isPSHUFDMask(N);
60 }], MMX_SHUFFLE_get_shuf_imm>;
62 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
63 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
64 return X86::isMOVLMask(N);
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 let isTwoAddress = 1 in {
72 // MMXI_binop_rm - Simple MMX binary operator.
73 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
74 ValueType OpVT, bit Commutable = 0> {
75 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
76 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
77 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
78 let isCommutable = Commutable;
80 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
82 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
84 (load_mmx addr:$src2)))))]>;
87 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
89 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
91 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
92 let isCommutable = Commutable;
94 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
96 [(set VR64:$dst, (IntId VR64:$src1,
97 (bitconvert (load_mmx addr:$src2))))]>;
100 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
102 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
103 // to collapse (bitconvert VT to VT) into its operand.
105 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
106 bit Commutable = 0> {
107 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
108 (ins VR64:$src1, VR64:$src2),
109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
110 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
111 let isCommutable = Commutable;
113 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
114 (ins VR64:$src1, i64mem:$src2),
115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
117 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
120 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
121 string OpcodeStr, Intrinsic IntId> {
122 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
123 (ins VR64:$src1, VR64:$src2),
124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
125 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
126 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
127 (ins VR64:$src1, i64mem:$src2),
128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
129 [(set VR64:$dst, (IntId VR64:$src1,
130 (bitconvert (load_mmx addr:$src2))))]>;
131 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
132 (ins VR64:$src1, i32i8imm:$src2),
133 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
134 [(set VR64:$dst, (IntId VR64:$src1,
136 (v2i32 (vector_shuffle immAllZerosV,
137 (v2i32 (scalar_to_vector (i32 imm:$src2))),
138 MMX_MOVL_shuffle_mask))))))]>;
142 //===----------------------------------------------------------------------===//
143 // MMX EMMS & FEMMS Instructions
144 //===----------------------------------------------------------------------===//
146 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
147 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
149 //===----------------------------------------------------------------------===//
150 // MMX Scalar Instructions
151 //===----------------------------------------------------------------------===//
153 // Data Transfer Instructions
154 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
155 "movd\t{$src, $dst|$dst, $src}",
156 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
157 let isSimpleLoad = 1, isReMaterializable = 1 in
158 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
159 "movd\t{$src, $dst|$dst, $src}",
160 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
162 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
163 "movd\t{$src, $dst|$dst, $src}", []>;
165 let neverHasSideEffects = 1 in
166 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
167 "movd\t{$src, $dst|$dst, $src}", []>;
169 let neverHasSideEffects = 1 in
170 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg, (outs GR64:$dst), (ins VR64:$src),
171 "movd\t{$src, $dst|$dst, $src}", []>;
173 let neverHasSideEffects = 1 in
174 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
175 "movq\t{$src, $dst|$dst, $src}", []>;
176 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
177 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
178 "movq\t{$src, $dst|$dst, $src}",
179 [(set VR64:$dst, (load_mmx addr:$src))]>;
180 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
181 "movq\t{$src, $dst|$dst, $src}",
182 [(store (v1i64 VR64:$src), addr:$dst)]>;
184 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
185 "movdq2q\t{$src, $dst|$dst, $src}",
188 (i64 (vector_extract (v2i64 VR128:$src),
191 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
192 "movq2dq\t{$src, $dst|$dst, $src}",
194 (v2i64 (vector_shuffle immAllZerosV,
195 (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
196 MOVL_shuffle_mask)))]>;
198 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
199 "movntq\t{$src, $dst|$dst, $src}",
200 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
202 let AddedComplexity = 15 in
203 // movd to MMX register zero-extends
204 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
205 "movd\t{$src, $dst|$dst, $src}",
207 (v2i32 (vector_shuffle immAllZerosV,
208 (v2i32 (scalar_to_vector GR32:$src)),
209 MMX_MOVL_shuffle_mask)))]>;
210 let AddedComplexity = 20 in
211 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
212 "movd\t{$src, $dst|$dst, $src}",
214 (v2i32 (vector_shuffle immAllZerosV,
215 (v2i32 (scalar_to_vector
216 (loadi32 addr:$src))),
217 MMX_MOVL_shuffle_mask)))]>;
219 // Arithmetic Instructions
222 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
223 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
224 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
225 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
227 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
228 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
230 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
231 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
234 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
235 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
236 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
237 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
239 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
240 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
242 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
243 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
246 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
248 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
249 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
250 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
253 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
255 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
256 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
258 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
259 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
261 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
262 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
264 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
266 // Logical Instructions
267 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
268 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
269 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
271 let isTwoAddress = 1 in {
272 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
273 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
274 "pandn\t{$src2, $dst|$dst, $src2}",
275 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
277 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
278 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
279 "pandn\t{$src2, $dst|$dst, $src2}",
280 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
281 (load addr:$src2))))]>;
284 // Shift Instructions
285 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
287 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
289 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
292 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
294 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
296 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
299 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
301 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
304 // Comparison Instructions
305 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
306 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
307 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
309 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
310 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
311 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
313 // Conversion Instructions
315 // -- Unpack Instructions
316 let isTwoAddress = 1 in {
317 // Unpack High Packed Data Instructions
318 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
319 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
320 "punpckhbw\t{$src2, $dst|$dst, $src2}",
322 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
323 MMX_UNPCKH_shuffle_mask)))]>;
324 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
325 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
326 "punpckhbw\t{$src2, $dst|$dst, $src2}",
328 (v8i8 (vector_shuffle VR64:$src1,
329 (bc_v8i8 (load_mmx addr:$src2)),
330 MMX_UNPCKH_shuffle_mask)))]>;
332 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
333 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
334 "punpckhwd\t{$src2, $dst|$dst, $src2}",
336 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
337 MMX_UNPCKH_shuffle_mask)))]>;
338 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
339 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
340 "punpckhwd\t{$src2, $dst|$dst, $src2}",
342 (v4i16 (vector_shuffle VR64:$src1,
343 (bc_v4i16 (load_mmx addr:$src2)),
344 MMX_UNPCKH_shuffle_mask)))]>;
346 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
347 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
348 "punpckhdq\t{$src2, $dst|$dst, $src2}",
350 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
351 MMX_UNPCKH_shuffle_mask)))]>;
352 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
353 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
354 "punpckhdq\t{$src2, $dst|$dst, $src2}",
356 (v2i32 (vector_shuffle VR64:$src1,
357 (bc_v2i32 (load_mmx addr:$src2)),
358 MMX_UNPCKH_shuffle_mask)))]>;
360 // Unpack Low Packed Data Instructions
361 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
362 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
363 "punpcklbw\t{$src2, $dst|$dst, $src2}",
365 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
366 MMX_UNPCKL_shuffle_mask)))]>;
367 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
368 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
369 "punpcklbw\t{$src2, $dst|$dst, $src2}",
371 (v8i8 (vector_shuffle VR64:$src1,
372 (bc_v8i8 (load_mmx addr:$src2)),
373 MMX_UNPCKL_shuffle_mask)))]>;
375 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
376 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
377 "punpcklwd\t{$src2, $dst|$dst, $src2}",
379 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
380 MMX_UNPCKL_shuffle_mask)))]>;
381 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
382 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
383 "punpcklwd\t{$src2, $dst|$dst, $src2}",
385 (v4i16 (vector_shuffle VR64:$src1,
386 (bc_v4i16 (load_mmx addr:$src2)),
387 MMX_UNPCKL_shuffle_mask)))]>;
389 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
390 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
391 "punpckldq\t{$src2, $dst|$dst, $src2}",
393 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
394 MMX_UNPCKL_shuffle_mask)))]>;
395 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
396 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
397 "punpckldq\t{$src2, $dst|$dst, $src2}",
399 (v2i32 (vector_shuffle VR64:$src1,
400 (bc_v2i32 (load_mmx addr:$src2)),
401 MMX_UNPCKL_shuffle_mask)))]>;
404 // -- Pack Instructions
405 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
406 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
407 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
409 // -- Shuffle Instructions
410 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
411 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
412 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
414 (v4i16 (vector_shuffle
416 MMX_PSHUFW_shuffle_mask:$src2)))]>;
417 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
418 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
419 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
421 (v4i16 (vector_shuffle
422 (bc_v4i16 (load_mmx addr:$src1)),
424 MMX_PSHUFW_shuffle_mask:$src2)))]>;
426 // -- Conversion Instructions
427 let neverHasSideEffects = 1 in {
428 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
429 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
431 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
432 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
434 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
435 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
437 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
438 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
440 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
441 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
443 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
444 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
446 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
447 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
449 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
450 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
452 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
453 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
455 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
456 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
458 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
459 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
461 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
462 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
463 } // end neverHasSideEffects
467 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
468 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
470 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
471 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
472 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
473 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
474 (iPTR imm:$src2)))]>;
475 let isTwoAddress = 1 in {
476 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
477 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
478 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
479 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
480 GR32:$src2, (iPTR imm:$src3))))]>;
481 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
482 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
483 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
485 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
486 (i32 (anyext (loadi16 addr:$src2))),
487 (iPTR imm:$src3))))]>;
491 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
492 "pmovmskb\t{$src, $dst|$dst, $src}",
493 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
497 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
498 "maskmovq\t{$mask, $src|$src, $mask}",
499 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
501 //===----------------------------------------------------------------------===//
502 // Alias Instructions
503 //===----------------------------------------------------------------------===//
505 // Alias instructions that map zero vector to pxor.
506 let isReMaterializable = 1 in {
507 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
509 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
510 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
511 "pcmpeqd\t$dst, $dst",
512 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
515 let Predicates = [HasMMX] in {
516 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
517 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
518 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
521 //===----------------------------------------------------------------------===//
522 // Non-Instruction Patterns
523 //===----------------------------------------------------------------------===//
525 // Store 64-bit integer vector values.
526 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
527 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
528 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
529 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
530 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
531 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
532 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
533 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
536 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
537 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
538 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
539 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
540 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
541 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
542 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
543 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
544 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
545 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
546 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
547 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
549 // 64-bit bit convert.
550 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
551 (MMX_MOVD64to64rr GR64:$src)>;
552 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
553 (MMX_MOVD64to64rr GR64:$src)>;
554 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
555 (MMX_MOVD64to64rr GR64:$src)>;
556 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
557 (MMX_MOVD64to64rr GR64:$src)>;
558 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
559 (MMX_MOVD64from64rr VR64:$src)>;
560 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
561 (MMX_MOVD64from64rr VR64:$src)>;
562 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
563 (MMX_MOVD64from64rr VR64:$src)>;
564 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
565 (MMX_MOVD64from64rr VR64:$src)>;
567 // Move scalar to XMM zero-extended
568 // movd to XMM register zero-extends
569 let AddedComplexity = 15 in {
570 def : Pat<(v8i8 (vector_shuffle immAllZerosV_bc,
571 (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
572 MMX_MOVL_shuffle_mask)),
573 (MMX_MOVZDI2PDIrr GR32:$src)>;
574 def : Pat<(v4i16 (vector_shuffle immAllZerosV_bc,
575 (bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
576 MMX_MOVL_shuffle_mask)),
577 (MMX_MOVZDI2PDIrr GR32:$src)>;
580 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
581 // 8 or 16-bits matter.
582 def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
583 (MMX_MOVD64rr GR32:$src)>;
584 def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
585 (MMX_MOVD64rr GR32:$src)>;
587 // Patterns to perform canonical versions of vector shuffling.
588 let AddedComplexity = 10 in {
589 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
590 MMX_UNPCKL_v_undef_shuffle_mask)),
591 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
592 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
593 MMX_UNPCKL_v_undef_shuffle_mask)),
594 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
595 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
596 MMX_UNPCKL_v_undef_shuffle_mask)),
597 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
600 let AddedComplexity = 10 in {
601 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
602 MMX_UNPCKH_v_undef_shuffle_mask)),
603 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
604 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
605 MMX_UNPCKH_v_undef_shuffle_mask)),
606 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
607 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
608 MMX_UNPCKH_v_undef_shuffle_mask)),
609 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
612 // Patterns to perform vector shuffling with a zeroed out vector.
613 let AddedComplexity = 20 in {
614 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
615 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
616 MMX_UNPCKL_shuffle_mask)),
617 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
620 // Some special case PANDN patterns.
621 // FIXME: Get rid of these.
622 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
624 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
625 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
627 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
628 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
630 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
632 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
634 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
635 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
637 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
638 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
640 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
642 // Move MMX to lower 64-bit of XMM
643 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
644 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
646 // Move lower 64-bit of XMM to MMX.
647 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
649 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
650 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
652 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
653 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
655 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;