1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 // All instructions that use MMX should be in this file, even if they also use
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 def MMX_INTALU_ITINS : OpndItins<
24 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
27 def MMX_INTALUQ_ITINS : OpndItins<
28 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM
31 def MMX_PHADDSUBW : OpndItins<
32 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM
35 def MMX_PHADDSUBD : OpndItins<
36 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM
39 def MMX_PMUL_ITINS : OpndItins<
40 IIC_MMX_PMUL, IIC_MMX_PMUL
43 def MMX_PSADBW_ITINS : OpndItins<
44 IIC_MMX_PSADBW, IIC_MMX_PSADBW
47 def MMX_MISC_FUNC_ITINS : OpndItins<
48 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG
51 def MMX_SHIFT_ITINS : ShiftOpndItins<
52 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI
55 def MMX_UNPCK_H_ITINS : OpndItins<
56 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM
59 def MMX_UNPCK_L_ITINS : OpndItins<
60 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L
63 def MMX_PCK_ITINS : OpndItins<
64 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM
67 def MMX_PSHUF_ITINS : OpndItins<
68 IIC_MMX_PSHUF, IIC_MMX_PSHUF
71 def MMX_CVT_PD_ITINS : OpndItins<
72 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM
75 def MMX_CVT_PS_ITINS : OpndItins<
76 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM
79 let Constraints = "$src1 = $dst" in {
80 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
81 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
82 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
83 OpndItins itins, bit Commutable = 0> {
84 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
85 (ins VR64:$src1, VR64:$src2),
86 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
87 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr> {
88 let isCommutable = Commutable;
90 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
91 (ins VR64:$src1, i64mem:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 [(set VR64:$dst, (IntId VR64:$src1,
94 (bitconvert (load_mmx addr:$src2))))],
98 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
99 string OpcodeStr, Intrinsic IntId,
100 Intrinsic IntId2, ShiftOpndItins itins> {
101 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
102 (ins VR64:$src1, VR64:$src2),
103 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>;
105 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
106 (ins VR64:$src1, i64mem:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 [(set VR64:$dst, (IntId VR64:$src1,
109 (bitconvert (load_mmx addr:$src2))))],
111 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
112 (ins VR64:$src1, i32i8imm:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))], itins.ri>;
118 /// Unary MMX instructions requiring SSSE3.
119 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
120 Intrinsic IntId64, OpndItins itins> {
121 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
122 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
123 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>;
125 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
128 (IntId64 (bitconvert (memopmmx addr:$src))))],
132 /// Binary MMX instructions requiring SSSE3.
133 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
134 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
135 Intrinsic IntId64, OpndItins itins> {
136 let isCommutable = 0 in
137 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
138 (ins VR64:$src1, VR64:$src2),
139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
140 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>;
141 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
142 (ins VR64:$src1, i64mem:$src2),
143 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
146 (bitconvert (memopmmx addr:$src2))))], itins.rm>;
150 /// PALIGN MMX instructions (require SSSE3).
151 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
152 def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
153 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
154 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
155 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
156 def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
157 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
158 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
159 [(set VR64:$dst, (IntId VR64:$src1,
160 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
163 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
164 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
165 string asm, OpndItins itins, Domain d> {
166 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
167 [(set DstRC:$dst, (Int SrcRC:$src))],
169 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
170 [(set DstRC:$dst, (Int (ld_frag addr:$src)))],
174 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
175 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
176 PatFrag ld_frag, string asm, Domain d> {
177 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
178 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
180 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
181 (ins DstRC:$src1, x86memop:$src2), asm,
182 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
186 //===----------------------------------------------------------------------===//
187 // MMX EMMS Instruction
188 //===----------------------------------------------------------------------===//
190 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
191 [(int_x86_mmx_emms)]>;
193 //===----------------------------------------------------------------------===//
194 // MMX Scalar Instructions
195 //===----------------------------------------------------------------------===//
197 // Data Transfer Instructions
198 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
199 "movd\t{$src, $dst|$dst, $src}",
201 (x86mmx (scalar_to_vector GR32:$src)))],
203 let canFoldAsLoad = 1 in
204 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
205 "movd\t{$src, $dst|$dst, $src}",
207 (x86mmx (scalar_to_vector (loadi32 addr:$src))))],
210 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
211 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>;
212 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
213 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_REG_MM>;
215 let neverHasSideEffects = 1 in
216 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
217 "movd\t{$src, $dst|$dst, $src}",
218 [], IIC_MMX_MOV_MM_RM>;
220 // These are 64 bit moves, but since the OS X assembler doesn't
221 // recognize a register-register movq, we write them as
223 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
224 (outs GR64:$dst), (ins VR64:$src),
225 "movd\t{$src, $dst|$dst, $src}",
227 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>;
228 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
229 "movd\t{$src, $dst|$dst, $src}",
231 (bitconvert GR64:$src))], IIC_MMX_MOV_MM_RM>;
232 let neverHasSideEffects = 1 in
233 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
234 "movq\t{$src, $dst|$dst, $src}", [],
236 let canFoldAsLoad = 1 in
237 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
238 "movq\t{$src, $dst|$dst, $src}",
239 [(set VR64:$dst, (load_mmx addr:$src))],
241 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
242 "movq\t{$src, $dst|$dst, $src}",
243 [(store (x86mmx VR64:$src), addr:$dst)],
246 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
247 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
250 (i64 (vector_extract (v2i64 VR128:$src),
254 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
255 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
257 (v2i64 (scalar_to_vector
258 (i64 (bitconvert (x86mmx VR64:$src))))))],
261 let neverHasSideEffects = 1 in
262 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
263 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", [],
266 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
267 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", [],
270 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
271 "movntq\t{$src, $dst|$dst, $src}",
272 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)],
275 let AddedComplexity = 15 in
276 // movd to MMX register zero-extends
277 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
278 "movd\t{$src, $dst|$dst, $src}",
280 (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))],
282 let AddedComplexity = 20 in
283 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
285 "movd\t{$src, $dst|$dst, $src}",
287 (x86mmx (X86vzmovl (x86mmx
288 (scalar_to_vector (loadi32 addr:$src))))))],
291 // Arithmetic Instructions
292 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
294 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
296 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
299 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
300 MMX_INTALU_ITINS, 1>;
301 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
302 MMX_INTALU_ITINS, 1>;
303 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
304 MMX_INTALU_ITINS, 1>;
305 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
306 MMX_INTALUQ_ITINS, 1>;
307 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
308 MMX_INTALU_ITINS, 1>;
309 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
310 MMX_INTALU_ITINS, 1>;
312 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
313 MMX_INTALU_ITINS, 1>;
314 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
315 MMX_INTALU_ITINS, 1>;
317 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
319 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
321 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
326 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
328 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
329 MMX_INTALU_ITINS, 1>;
330 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
331 MMX_INTALU_ITINS, 1>;
332 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
333 MMX_INTALUQ_ITINS, 1>;
335 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
336 MMX_INTALU_ITINS, 1>;
337 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
338 MMX_INTALU_ITINS, 1>;
340 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
341 MMX_INTALU_ITINS, 1>;
342 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
343 MMX_INTALU_ITINS, 1>;
345 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
347 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
349 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
353 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
356 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
358 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
360 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
362 let isCommutable = 1 in
363 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
364 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>;
367 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
370 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
371 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>;
372 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
373 MMX_MISC_FUNC_ITINS, 1>;
374 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
375 MMX_MISC_FUNC_ITINS, 1>;
377 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
378 MMX_MISC_FUNC_ITINS, 1>;
379 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
380 MMX_MISC_FUNC_ITINS, 1>;
382 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
383 MMX_MISC_FUNC_ITINS, 1>;
384 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
385 MMX_MISC_FUNC_ITINS, 1>;
387 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
388 MMX_PSADBW_ITINS, 1>;
390 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
391 MMX_MISC_FUNC_ITINS>;
392 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
393 MMX_MISC_FUNC_ITINS>;
394 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
395 MMX_MISC_FUNC_ITINS>;
396 let Constraints = "$src1 = $dst" in
397 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
399 // Logical Instructions
400 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
401 MMX_INTALU_ITINS, 1>;
402 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
403 MMX_INTALU_ITINS, 1>;
404 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
405 MMX_INTALU_ITINS, 1>;
406 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
409 // Shift Instructions
410 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
411 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
413 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
414 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
416 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
417 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
420 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
421 int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
423 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
424 int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
426 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
427 int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
430 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
431 int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
433 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
434 int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
437 // Comparison Instructions
438 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
440 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
442 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
445 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
447 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
449 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
452 // -- Unpack Instructions
453 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
454 int_x86_mmx_punpckhbw,
456 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
457 int_x86_mmx_punpckhwd,
459 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
460 int_x86_mmx_punpckhdq,
462 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
463 int_x86_mmx_punpcklbw,
465 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
466 int_x86_mmx_punpcklwd,
468 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
469 int_x86_mmx_punpckldq,
472 // -- Pack Instructions
473 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
475 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
477 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
480 // -- Shuffle Instructions
481 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
484 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
485 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
486 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
488 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))],
490 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
491 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
492 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
494 (int_x86_sse_pshuf_w (load_mmx addr:$src1),
501 // -- Conversion Instructions
502 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
503 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
504 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
505 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
506 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
507 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
508 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
509 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
510 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
511 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
512 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
513 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
514 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
515 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
516 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
517 let Constraints = "$src1 = $dst" in {
518 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
519 int_x86_sse_cvtpi2ps,
520 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
521 SSEPackedSingle>, TB;
525 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
526 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
527 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
528 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
531 let Constraints = "$src1 = $dst" in {
532 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
534 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
535 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
536 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
537 GR32:$src2, (iPTR imm:$src3)))],
540 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
542 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
543 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
544 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
545 (i32 (anyext (loadi16 addr:$src2))),
551 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
552 "pmovmskb\t{$src, $dst|$dst, $src}",
554 (int_x86_mmx_pmovmskb VR64:$src))]>;
557 // MMX to XMM for vector types
558 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
559 [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
561 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
562 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
564 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
565 (v2i64 (MOVQI2PQIrm addr:$src))>;
567 def : Pat<(v2i64 (MMX_X86movq2dq
568 (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
569 (v2i64 (MOVDI2PDIrm addr:$src))>;
571 // Low word of XMM to MMX.
572 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
573 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
575 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
576 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
578 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
579 (x86mmx (MMX_MOVQ64rm addr:$src))>;
583 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
584 "maskmovq\t{$mask, $src|$src, $mask}",
585 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)],
588 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
589 "maskmovq\t{$mask, $src|$src, $mask}",
590 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)],
593 // 64-bit bit convert.
594 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
595 (MMX_MOVD64to64rr GR64:$src)>;
596 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
597 (MMX_MOVD64from64rr VR64:$src)>;
598 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
599 (MMX_MOVQ2FR64rr VR64:$src)>;
600 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
601 (MMX_MOVFR642Qrr FR64:$src)>;