1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Instruction templates
18 //===----------------------------------------------------------------------===//
20 // MMXI - MMX instructions with TB prefix.
21 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
22 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
23 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
24 // MMXID - MMX instructions with XD prefix.
25 // MMXIS - MMX instructions with XS prefix.
26 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
27 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
28 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
29 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
30 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
31 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
32 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
33 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
34 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
35 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
36 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
37 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
39 // Some 'special' instructions
40 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
42 [(set VR64:$dst, (v8i8 (undef)))]>,
45 // 64-bit vector undef's.
46 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
47 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
48 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
49 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
51 //===----------------------------------------------------------------------===//
52 // MMX Pattern Fragments
53 //===----------------------------------------------------------------------===//
55 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
57 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
58 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
59 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
60 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
68 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
69 return getI8Imm(X86::getShuffleSHUFImmediate(N));
72 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
73 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
74 return X86::isUNPCKHMask(N);
77 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
78 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
79 return X86::isUNPCKLMask(N);
82 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
83 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
84 return X86::isUNPCKH_v_undef_Mask(N);
87 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
88 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
89 return X86::isUNPCKL_v_undef_Mask(N);
92 // Patterns for shuffling.
93 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
94 return X86::isPSHUFDMask(N);
95 }], MMX_SHUFFLE_get_shuf_imm>;
97 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
98 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
99 return X86::isMOVLMask(N);
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 let isTwoAddress = 1 in {
107 // MMXI_binop_rm - Simple MMX binary operator.
108 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
109 ValueType OpVT, bit Commutable = 0> {
110 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
111 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
112 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
113 let isCommutable = Commutable;
115 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
116 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
117 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
119 (load_mmx addr:$src2)))))]>;
122 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
123 bit Commutable = 0> {
124 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
125 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
126 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
127 let isCommutable = Commutable;
129 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
130 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
131 [(set VR64:$dst, (IntId VR64:$src1,
132 (bitconvert (load_mmx addr:$src2))))]>;
135 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
137 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
138 // to collapse (bitconvert VT to VT) into its operand.
140 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
141 bit Commutable = 0> {
142 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
143 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
144 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
145 let isCommutable = Commutable;
147 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
148 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
150 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
153 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
154 string OpcodeStr, Intrinsic IntId> {
155 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
156 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
157 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
158 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
159 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
160 [(set VR64:$dst, (IntId VR64:$src1,
161 (bitconvert (load_mmx addr:$src2))))]>;
162 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
163 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
164 [(set VR64:$dst, (IntId VR64:$src1,
165 (scalar_to_vector (i32 imm:$src2))))]>;
169 //===----------------------------------------------------------------------===//
170 // MMX EMMS & FEMMS Instructions
171 //===----------------------------------------------------------------------===//
173 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
174 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
176 //===----------------------------------------------------------------------===//
177 // MMX Scalar Instructions
178 //===----------------------------------------------------------------------===//
180 // Data Transfer Instructions
181 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
182 "movd {$src, $dst|$dst, $src}", []>;
183 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
184 "movd {$src, $dst|$dst, $src}", []>;
185 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
186 "movd {$src, $dst|$dst, $src}", []>;
188 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
189 "movd {$src, $dst|$dst, $src}", []>;
191 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
192 "movq {$src, $dst|$dst, $src}", []>;
193 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
194 "movq {$src, $dst|$dst, $src}",
195 [(set VR64:$dst, (load_mmx addr:$src))]>;
196 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
197 "movq {$src, $dst|$dst, $src}",
198 [(store (v1i64 VR64:$src), addr:$dst)]>;
200 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
201 "movdq2q {$src, $dst|$dst, $src}",
203 (v1i64 (vector_extract (v2i64 VR128:$src),
206 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
207 "movq2dq {$src, $dst|$dst, $src}",
209 (bitconvert (v1i64 VR64:$src)))]>;
211 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
212 "movntq {$src, $dst|$dst, $src}",
213 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
215 let AddedComplexity = 15 in
216 // movd to MMX register zero-extends
217 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
218 "movd {$src, $dst|$dst, $src}",
220 (v2i32 (vector_shuffle immAllZerosV,
221 (v2i32 (scalar_to_vector GR32:$src)),
222 MMX_MOVL_shuffle_mask)))]>;
223 let AddedComplexity = 20 in
224 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
225 "movd {$src, $dst|$dst, $src}",
227 (v2i32 (vector_shuffle immAllZerosV,
228 (v2i32 (scalar_to_vector
229 (loadi32 addr:$src))),
230 MMX_MOVL_shuffle_mask)))]>;
232 // Arithmetic Instructions
235 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
236 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
237 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
238 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
240 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
241 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
243 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
244 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
247 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
248 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
249 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
250 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
252 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
253 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
255 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
256 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
259 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
261 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
262 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
263 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
266 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
268 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
269 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
271 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
272 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
274 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
275 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
277 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
279 // Logical Instructions
280 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
281 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
282 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
284 let isTwoAddress = 1 in {
285 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
286 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
287 "pandn {$src2, $dst|$dst, $src2}",
288 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
290 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
291 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
292 "pandn {$src2, $dst|$dst, $src2}",
293 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
294 (load addr:$src2))))]>;
297 // Shift Instructions
298 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
300 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
302 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
305 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
307 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
309 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
312 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
314 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
317 // Comparison Instructions
318 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
319 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
320 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
322 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
323 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
324 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
326 // Conversion Instructions
328 // -- Unpack Instructions
329 let isTwoAddress = 1 in {
330 // Unpack High Packed Data Instructions
331 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
332 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
333 "punpckhbw {$src2, $dst|$dst, $src2}",
335 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
336 MMX_UNPCKH_shuffle_mask)))]>;
337 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
338 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
339 "punpckhbw {$src2, $dst|$dst, $src2}",
341 (v8i8 (vector_shuffle VR64:$src1,
342 (bc_v8i8 (load_mmx addr:$src2)),
343 MMX_UNPCKH_shuffle_mask)))]>;
345 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
346 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
347 "punpckhwd {$src2, $dst|$dst, $src2}",
349 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
350 MMX_UNPCKH_shuffle_mask)))]>;
351 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
352 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
353 "punpckhwd {$src2, $dst|$dst, $src2}",
355 (v4i16 (vector_shuffle VR64:$src1,
356 (bc_v4i16 (load_mmx addr:$src2)),
357 MMX_UNPCKH_shuffle_mask)))]>;
359 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
360 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
361 "punpckhdq {$src2, $dst|$dst, $src2}",
363 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
364 MMX_UNPCKH_shuffle_mask)))]>;
365 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
366 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
367 "punpckhdq {$src2, $dst|$dst, $src2}",
369 (v2i32 (vector_shuffle VR64:$src1,
370 (bc_v2i32 (load_mmx addr:$src2)),
371 MMX_UNPCKH_shuffle_mask)))]>;
373 // Unpack Low Packed Data Instructions
374 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
375 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
376 "punpcklbw {$src2, $dst|$dst, $src2}",
378 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
379 MMX_UNPCKL_shuffle_mask)))]>;
380 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
381 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
382 "punpcklbw {$src2, $dst|$dst, $src2}",
384 (v8i8 (vector_shuffle VR64:$src1,
385 (bc_v8i8 (load_mmx addr:$src2)),
386 MMX_UNPCKL_shuffle_mask)))]>;
388 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
389 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
390 "punpcklwd {$src2, $dst|$dst, $src2}",
392 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
393 MMX_UNPCKL_shuffle_mask)))]>;
394 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
395 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
396 "punpcklwd {$src2, $dst|$dst, $src2}",
398 (v4i16 (vector_shuffle VR64:$src1,
399 (bc_v4i16 (load_mmx addr:$src2)),
400 MMX_UNPCKL_shuffle_mask)))]>;
402 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
403 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
404 "punpckldq {$src2, $dst|$dst, $src2}",
406 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
407 MMX_UNPCKL_shuffle_mask)))]>;
408 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
409 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
410 "punpckldq {$src2, $dst|$dst, $src2}",
412 (v2i32 (vector_shuffle VR64:$src1,
413 (bc_v2i32 (load_mmx addr:$src2)),
414 MMX_UNPCKL_shuffle_mask)))]>;
417 // -- Pack Instructions
418 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
419 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
420 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
422 // -- Shuffle Instructions
423 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
424 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
425 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
427 (v4i16 (vector_shuffle
429 MMX_PSHUFW_shuffle_mask:$src2)))]>;
430 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
431 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
432 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
434 (v4i16 (vector_shuffle
435 (bc_v4i16 (load_mmx addr:$src1)),
437 MMX_PSHUFW_shuffle_mask:$src2)))]>;
439 // -- Conversion Instructions
440 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
441 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
442 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
443 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
445 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
446 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
447 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
448 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
450 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
451 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
452 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
453 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
455 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
456 "cvtps2pi {$src, $dst|$dst, $src}", []>;
457 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
458 "cvtps2pi {$src, $dst|$dst, $src}", []>;
460 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
462 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
463 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
465 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
466 "cvttps2pi {$src, $dst|$dst, $src}", []>;
467 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
468 "cvttps2pi {$src, $dst|$dst, $src}", []>;
471 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
472 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
474 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
475 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
476 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
477 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
478 (iPTR imm:$src2)))]>;
479 let isTwoAddress = 1 in {
480 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
481 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
482 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
483 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
484 GR32:$src2, (iPTR imm:$src3))))]>;
485 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
486 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
487 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
489 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
490 (i32 (anyext (loadi16 addr:$src2))),
491 (iPTR imm:$src3))))]>;
495 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
496 "pmovmskb {$src, $dst|$dst, $src}",
497 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
500 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
501 "maskmovq {$mask, $src|$src, $mask}",
502 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
505 //===----------------------------------------------------------------------===//
506 // Alias Instructions
507 //===----------------------------------------------------------------------===//
509 // Alias instructions that map zero vector to pxor.
510 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
511 let isReMaterializable = 1 in {
512 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
514 [(set VR64:$dst, (v1i64 immAllZerosV))]>;
515 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
516 "pcmpeqd $dst, $dst",
517 [(set VR64:$dst, (v1i64 immAllOnesV))]>;
520 //===----------------------------------------------------------------------===//
521 // Non-Instruction Patterns
522 //===----------------------------------------------------------------------===//
524 // Store 64-bit integer vector values.
525 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
526 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
528 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
529 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
530 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
531 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
532 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
534 // 64-bit vector all zero's.
535 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
536 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
537 def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
538 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
540 // 64-bit vector all one's.
541 def : Pat<(v8i8 immAllOnesV), (MMX_V_SETALLONES)>;
542 def : Pat<(v4i16 immAllOnesV), (MMX_V_SETALLONES)>;
543 def : Pat<(v2i32 immAllOnesV), (MMX_V_SETALLONES)>;
544 def : Pat<(v1i64 immAllOnesV), (MMX_V_SETALLONES)>;
547 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
548 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
549 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
550 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
551 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
552 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
553 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
554 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
555 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
556 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
557 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
558 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
560 // 64-bit bit convert.
561 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
562 (MMX_MOVD64to64rr GR64:$src)>;
563 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
564 (MMX_MOVD64to64rr GR64:$src)>;
565 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
566 (MMX_MOVD64to64rr GR64:$src)>;
567 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
568 (MMX_MOVD64to64rr GR64:$src)>;
570 def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
572 // Move scalar to XMM zero-extended
573 // movd to XMM register zero-extends
574 let AddedComplexity = 15 in {
575 def : Pat<(v8i8 (vector_shuffle immAllZerosV,
576 (v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
577 (MMX_MOVZDI2PDIrr GR32:$src)>;
578 def : Pat<(v4i16 (vector_shuffle immAllZerosV,
579 (v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
580 (MMX_MOVZDI2PDIrr GR32:$src)>;
581 def : Pat<(v2i32 (vector_shuffle immAllZerosV,
582 (v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
583 (MMX_MOVZDI2PDIrr GR32:$src)>;
586 // Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
587 // 8 or 16-bits matter.
588 def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
589 def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
590 def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
592 // Patterns to perform canonical versions of vector shuffling.
593 let AddedComplexity = 10 in {
594 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
595 MMX_UNPCKL_v_undef_shuffle_mask)),
596 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
597 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
598 MMX_UNPCKL_v_undef_shuffle_mask)),
599 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
600 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
601 MMX_UNPCKL_v_undef_shuffle_mask)),
602 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
605 let AddedComplexity = 10 in {
606 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
607 MMX_UNPCKH_v_undef_shuffle_mask)),
608 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
609 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
610 MMX_UNPCKH_v_undef_shuffle_mask)),
611 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
612 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
613 MMX_UNPCKH_v_undef_shuffle_mask)),
614 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
617 // Patterns to perform vector shuffling with a zeroed out vector.
618 let AddedComplexity = 20 in {
619 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
620 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
621 MMX_UNPCKL_shuffle_mask)),
622 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
625 // Some special case PANDN patterns.
626 // FIXME: Get rid of these.
627 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
629 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
630 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
632 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
633 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
635 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
637 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
639 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
640 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
642 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
643 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
645 (MMX_PANDNrm VR64:$src1, addr:$src2)>;