1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 let Constraints = "$src1 = $dst" in {
21 // MMXI_binop_rm - Simple MMX binary operator based on llvm operator.
22 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 ValueType OpVT, bit Commutable = 0> {
24 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
25 (ins VR64:$src1, VR64:$src2),
26 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
27 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
28 let isCommutable = Commutable;
30 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
31 (ins VR64:$src1, i64mem:$src2),
32 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
33 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
35 (load_mmx addr:$src2)))))]>;
38 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
39 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
41 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
42 (ins VR64:$src1, VR64:$src2),
43 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
44 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
45 let isCommutable = Commutable;
47 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
48 (ins VR64:$src1, i64mem:$src2),
49 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
50 [(set VR64:$dst, (IntId VR64:$src1,
51 (bitconvert (load_mmx addr:$src2))))]>;
54 // MMXI_binop_rm_int2 - Simple MMX binary operator based on intrinsic, with a
55 // different name for the generated instructions than MMXI_binop_rm uses.
56 // Thus int2 and rm can coexist for different implementations of the same
57 // instruction, while int and rm cannot. This is temporary during transition
58 // to intrinsic-only implementation. When it is removed, remove the FIXME
59 // from X86RecognizableInstr.cpp.
60 multiclass MMXI_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
62 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
63 (ins VR64:$src1, VR64:$src2),
64 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
65 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
66 let isCommutable = Commutable;
68 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
69 (ins VR64:$src1, i64mem:$src2),
70 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
71 [(set VR64:$dst, (IntId VR64:$src1,
72 (bitconvert (load_mmx addr:$src2))))]>;
75 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
77 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
78 // to collapse (bitconvert VT to VT) into its operand.
80 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
82 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
83 (ins VR64:$src1, VR64:$src2),
84 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
85 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
86 let isCommutable = Commutable;
88 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
89 (ins VR64:$src1, i64mem:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
92 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
95 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
96 string OpcodeStr, Intrinsic IntId,
98 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
99 (ins VR64:$src1, VR64:$src2),
100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
101 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
102 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
103 (ins VR64:$src1, i64mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
105 [(set VR64:$dst, (IntId VR64:$src1,
106 (bitconvert (load_mmx addr:$src2))))]>;
107 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
108 (ins VR64:$src1, i32i8imm:$src2),
109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
110 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
114 //===----------------------------------------------------------------------===//
115 // MMX EMMS & FEMMS Instructions
116 //===----------------------------------------------------------------------===//
118 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
119 [(int_x86_mmx_emms)]>;
120 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
121 [(int_x86_mmx_femms)]>;
123 //===----------------------------------------------------------------------===//
124 // MMX Scalar Instructions
125 //===----------------------------------------------------------------------===//
127 // Data Transfer Instructions
128 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
129 "movd\t{$src, $dst|$dst, $src}",
131 (v2i32 (scalar_to_vector GR32:$src)))]>;
132 let canFoldAsLoad = 1, isReMaterializable = 1 in
133 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
134 "movd\t{$src, $dst|$dst, $src}",
136 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
138 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
139 "movd\t{$src, $dst|$dst, $src}", []>;
140 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
141 "movd\t{$src, $dst|$dst, $src}", []>;
143 let neverHasSideEffects = 1 in
144 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
145 "movd\t{$src, $dst|$dst, $src}",
148 let neverHasSideEffects = 1 in
149 // These are 64 bit moves, but since the OS X assembler doesn't
150 // recognize a register-register movq, we write them as
152 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
153 (outs GR64:$dst), (ins VR64:$src),
154 "movd\t{$src, $dst|$dst, $src}", []>;
155 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
156 "movd\t{$src, $dst|$dst, $src}",
158 (v1i64 (scalar_to_vector GR64:$src)))]>;
160 let neverHasSideEffects = 1 in
161 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
162 "movq\t{$src, $dst|$dst, $src}", []>;
163 let canFoldAsLoad = 1, isReMaterializable = 1 in
164 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
165 "movq\t{$src, $dst|$dst, $src}",
166 [(set VR64:$dst, (load_mmx addr:$src))]>;
167 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
168 "movq\t{$src, $dst|$dst, $src}",
169 [(store (v1i64 VR64:$src), addr:$dst)]>;
171 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
172 "movdq2q\t{$src, $dst|$dst, $src}",
175 (i64 (vector_extract (v2i64 VR128:$src),
178 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
179 "movq2dq\t{$src, $dst|$dst, $src}",
182 (v2i64 (scalar_to_vector
183 (i64 (bitconvert (v1i64 VR64:$src)))))))]>;
185 let neverHasSideEffects = 1 in
186 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
187 "movq2dq\t{$src, $dst|$dst, $src}", []>;
189 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
190 "movdq2q\t{$src, $dst|$dst, $src}", []>;
192 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
193 "movntq\t{$src, $dst|$dst, $src}",
194 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
196 let AddedComplexity = 15 in
197 // movd to MMX register zero-extends
198 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
199 "movd\t{$src, $dst|$dst, $src}",
201 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
202 let AddedComplexity = 20 in
203 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
205 "movd\t{$src, $dst|$dst, $src}",
207 (v2i32 (X86vzmovl (v2i32
208 (scalar_to_vector (loadi32 addr:$src))))))]>;
210 // Arithmetic Instructions
213 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>,
214 MMXI_binop_rm_int2<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
215 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>,
216 MMXI_binop_rm_int2<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
217 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>,
218 MMXI_binop_rm_int2<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
219 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>,
220 MMXI_binop_rm_int2<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
221 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
222 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
224 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
225 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
228 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>,
229 MMXI_binop_rm_int2<0xF8, "psubb", int_x86_mmx_psub_b>;
230 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>,
231 MMXI_binop_rm_int2<0xF9, "psubw", int_x86_mmx_psub_w>;
232 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>,
233 MMXI_binop_rm_int2<0xFA, "psubd", int_x86_mmx_psub_d>;
234 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>,
235 MMXI_binop_rm_int2<0xFB, "psubq", int_x86_mmx_psub_q>;
237 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
238 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
240 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
241 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
244 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
245 MMXI_binop_rm_int2<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
247 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
248 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
249 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
252 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
254 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
255 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
257 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
258 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
260 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
261 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
263 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
265 // Logical Instructions
266 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>,
267 MMXI_binop_rm_int2<0xDB, "pand", int_x86_mmx_pand, 1>;
268 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>,
269 MMXI_binop_rm_int2<0xEB, "por" , int_x86_mmx_por, 1>;
270 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>,
271 MMXI_binop_rm_int2<0xEF, "pxor", int_x86_mmx_pxor, 1>;
272 defm MMX_PANDN : MMXI_binop_rm_int2<0xDF, "pandn", int_x86_mmx_pandn, 1>;
274 let Constraints = "$src1 = $dst" in {
275 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
276 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
277 "pandn\t{$src2, $dst|$dst, $src2}",
278 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
280 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
281 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
282 "pandn\t{$src2, $dst|$dst, $src2}",
283 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
284 (load addr:$src2))))]>;
287 // Shift Instructions
288 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
289 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
290 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
291 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
292 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
293 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
295 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
296 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
297 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
298 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
299 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
300 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
302 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
303 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
304 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
305 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
307 // Shift up / down and insert zero's.
308 def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
309 (MMX_PSLLQri VR64:$src, (GetLo32XForm imm:$amt))>;
310 def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
311 (MMX_PSRLQri VR64:$src, (GetLo32XForm imm:$amt))>;
313 // Comparison Instructions
314 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
315 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
316 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
318 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
319 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
320 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
322 // Conversion Instructions
324 // -- Unpack Instructions
325 let Constraints = "$src1 = $dst" in {
326 // Unpack High Packed Data Instructions
327 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
328 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
329 "punpckhbw\t{$src2, $dst|$dst, $src2}",
331 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
332 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
333 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
334 "punpckhbw\t{$src2, $dst|$dst, $src2}",
336 (v8i8 (mmx_unpckh VR64:$src1,
337 (bc_v8i8 (load_mmx addr:$src2)))))]>;
339 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
340 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
341 "punpckhwd\t{$src2, $dst|$dst, $src2}",
343 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
344 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
345 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
346 "punpckhwd\t{$src2, $dst|$dst, $src2}",
348 (v4i16 (mmx_unpckh VR64:$src1,
349 (bc_v4i16 (load_mmx addr:$src2)))))]>;
351 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
352 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
353 "punpckhdq\t{$src2, $dst|$dst, $src2}",
355 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
356 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
357 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
358 "punpckhdq\t{$src2, $dst|$dst, $src2}",
360 (v2i32 (mmx_unpckh VR64:$src1,
361 (bc_v2i32 (load_mmx addr:$src2)))))]>;
363 // Unpack Low Packed Data Instructions
364 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
365 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
366 "punpcklbw\t{$src2, $dst|$dst, $src2}",
368 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
369 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
370 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
371 "punpcklbw\t{$src2, $dst|$dst, $src2}",
373 (v8i8 (mmx_unpckl VR64:$src1,
374 (bc_v8i8 (load_mmx addr:$src2)))))]>;
376 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
377 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
378 "punpcklwd\t{$src2, $dst|$dst, $src2}",
380 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
381 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
382 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
383 "punpcklwd\t{$src2, $dst|$dst, $src2}",
385 (v4i16 (mmx_unpckl VR64:$src1,
386 (bc_v4i16 (load_mmx addr:$src2)))))]>;
388 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
389 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
390 "punpckldq\t{$src2, $dst|$dst, $src2}",
392 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
393 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
394 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
395 "punpckldq\t{$src2, $dst|$dst, $src2}",
397 (v2i32 (mmx_unpckl VR64:$src1,
398 (bc_v2i32 (load_mmx addr:$src2)))))]>;
400 defm MMX_PUNPCKHBW : MMXI_binop_rm_int2<0x68, "punpckhbw",
401 int_x86_mmx_punpckhbw>;
402 defm MMX_PUNPCKHWD : MMXI_binop_rm_int2<0x69, "punpckhwd",
403 int_x86_mmx_punpckhwd>;
404 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int2<0x6A, "punpckhdq",
405 int_x86_mmx_punpckhdq>;
406 defm MMX_PUNPCKLBW : MMXI_binop_rm_int2<0x60, "punpcklbw",
407 int_x86_mmx_punpcklbw>;
408 defm MMX_PUNPCKLWD : MMXI_binop_rm_int2<0x61, "punpcklwd",
409 int_x86_mmx_punpcklwd>;
410 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int2<0x62, "punpckldq",
411 int_x86_mmx_punpckldq>;
413 // -- Pack Instructions
414 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
415 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
416 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
418 // -- Shuffle Instructions
419 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
420 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
421 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
423 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
424 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
425 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
426 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
428 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
431 // -- Conversion Instructions
432 let neverHasSideEffects = 1 in {
433 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
434 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
436 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
438 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
440 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
441 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
443 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
445 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
447 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
448 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
450 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
452 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
454 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
455 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
457 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
458 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
460 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
463 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
465 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
467 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
468 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
470 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
471 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
472 } // end neverHasSideEffects
474 // Intrinsic versions.
475 def MMX_CVTPD2PIirr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
476 "cvtpd2pi\t{$src, $dst|$dst, $src}",
477 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
478 def MMX_CVTPD2PIirm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
480 "cvtpd2pi\t{$src, $dst|$dst, $src}",
482 (int_x86_sse_cvtpd2pi
483 (bitconvert (loadv2i64 addr:$src))))]>;
484 def MMX_CVTPI2PDirr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
485 "cvtpi2pd\t{$src, $dst|$dst, $src}",
486 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
487 let Constraints = "$src1 = $dst" in {
488 def MMX_CVTPI2PSirr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst),
489 (ins VR128:$src1, VR64:$src2),
490 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
492 (int_x86_sse_cvtpi2ps VR128:$src1, VR64:$src2))]>;
493 def MMX_CVTPI2PSirm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
494 (ins VR128:$src1, i64mem:$src2),
495 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
497 (int_x86_sse_cvtpi2ps VR128:$src1,
498 (bitconvert (load_mmx addr:$src2))))]>;
500 def MMX_CVTPS2PIirr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
501 "cvtps2pi\t{$src, $dst|$dst, $src}",
502 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
503 def MMX_CVTPS2PIirm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
504 "cvtps2pi\t{$src, $dst|$dst, $src}",
506 (int_x86_sse_cvtps2pi
507 (bitconvert (load_mmx addr:$src))))]>;
508 def MMX_CVTTPD2PIirr: MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
509 "cvttpd2pi\t{$src, $dst|$dst, $src}",
510 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
511 def MMX_CVTTPD2PIirm: MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
513 "cvttpd2pi\t{$src, $dst|$dst, $src}",
515 (int_x86_sse_cvtpd2pi
516 (bitconvert (loadv2i64 addr:$src))))]>;
517 def MMX_CVTTPS2PIirr: MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
518 "cvttps2pi\t{$src, $dst|$dst, $src}",
519 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
520 def MMX_CVTTPS2PIirm: MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
521 "cvttps2pi\t{$src, $dst|$dst, $src}",
523 (int_x86_sse_cvtpd2pi
524 (bitconvert (load_mmx addr:$src))))]>;
527 def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW",
528 SDTypeProfile<1, 3, [SDTCisVT<0, v4i16>, SDTCisSameAs<0,1>,
529 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
532 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
533 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
534 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
535 [(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1),
536 (iPTR imm:$src2)))]>;
537 let Constraints = "$src1 = $dst" in {
538 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
540 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
541 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
542 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
543 GR32:$src2,(iPTR imm:$src3))))]>;
544 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
546 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
547 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
549 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
550 (i32 (anyext (loadi16 addr:$src2))),
551 (iPTR imm:$src3))))]>;
554 // MMX to XMM for vector types
555 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
556 [SDTCisVT<0, v2i64>, SDTCisVT<1, v1i64>]>>;
558 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
559 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
561 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
562 (v2i64 (MOVQI2PQIrm addr:$src))>;
564 def : Pat<(v2i64 (MMX_X86movq2dq (v1i64 (bitconvert
565 (v2i32 (scalar_to_vector (loadi32 addr:$src))))))),
566 (v2i64 (MOVDI2PDIrm addr:$src))>;
569 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
570 "pmovmskb\t{$src, $dst|$dst, $src}",
571 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
575 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
576 "maskmovq\t{$mask, $src|$src, $mask}",
577 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
579 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
580 "maskmovq\t{$mask, $src|$src, $mask}",
581 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
583 //===----------------------------------------------------------------------===//
584 // Alias Instructions
585 //===----------------------------------------------------------------------===//
587 // Alias instructions that map zero vector to pxor.
588 let isReMaterializable = 1, isCodeGenOnly = 1 in {
589 // FIXME: Change encoding to pseudo.
590 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "",
591 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
592 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "",
593 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
596 let Predicates = [HasMMX] in {
597 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
598 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
599 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
602 //===----------------------------------------------------------------------===//
603 // Non-Instruction Patterns
604 //===----------------------------------------------------------------------===//
606 // Store 64-bit integer vector values.
607 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
608 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
609 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
610 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
611 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
612 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
613 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
614 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
617 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
618 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
619 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
620 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
621 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
622 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
623 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
624 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
625 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
626 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
627 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
628 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
630 // 64-bit bit convert.
631 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
632 (MMX_MOVD64to64rr GR64:$src)>;
633 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
634 (MMX_MOVD64to64rr GR64:$src)>;
635 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
636 (MMX_MOVD64to64rr GR64:$src)>;
637 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
638 (MMX_MOVD64to64rr GR64:$src)>;
639 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
640 (MMX_MOVD64from64rr VR64:$src)>;
641 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
642 (MMX_MOVD64from64rr VR64:$src)>;
643 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
644 (MMX_MOVD64from64rr VR64:$src)>;
645 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
646 (MMX_MOVD64from64rr VR64:$src)>;
647 def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
648 (MMX_MOVQ2FR64rr VR64:$src)>;
649 def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
650 (MMX_MOVQ2FR64rr VR64:$src)>;
651 def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
652 (MMX_MOVQ2FR64rr VR64:$src)>;
653 def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
654 (MMX_MOVQ2FR64rr VR64:$src)>;
655 def : Pat<(v1i64 (bitconvert (f64 FR64:$src))),
656 (MMX_MOVFR642Qrr FR64:$src)>;
657 def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
658 (MMX_MOVFR642Qrr FR64:$src)>;
659 def : Pat<(v4i16 (bitconvert (f64 FR64:$src))),
660 (MMX_MOVFR642Qrr FR64:$src)>;
661 def : Pat<(v8i8 (bitconvert (f64 FR64:$src))),
662 (MMX_MOVFR642Qrr FR64:$src)>;
664 let AddedComplexity = 20 in {
665 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
666 (MMX_MOVZDI2PDIrm addr:$src)>;
670 let AddedComplexity = 15 in {
671 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
672 (MMX_PUNPCKLDQrr VR64:$src, (v2i32 (MMX_V_SET0)))>;
675 // Patterns to perform canonical versions of vector shuffling.
676 let AddedComplexity = 10 in {
677 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
678 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
679 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
680 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
681 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
682 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
685 let AddedComplexity = 10 in {
686 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
687 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
688 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
689 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
690 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
691 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
694 // Some special case PANDN patterns.
695 // FIXME: Get rid of these.
696 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
698 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
699 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
701 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
703 // Move MMX to lower 64-bit of XMM
704 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
705 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
706 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
707 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
708 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
709 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
710 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
711 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
713 // Move lower 64-bit of XMM to MMX.
714 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
716 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
717 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
719 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
720 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
722 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
724 // Patterns for vector comparisons
725 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
726 (MMX_PCMPEQBrr VR64:$src1, VR64:$src2)>;
727 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
728 (MMX_PCMPEQBrm VR64:$src1, addr:$src2)>;
729 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
730 (MMX_PCMPEQWrr VR64:$src1, VR64:$src2)>;
731 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
732 (MMX_PCMPEQWrm VR64:$src1, addr:$src2)>;
733 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
734 (MMX_PCMPEQDrr VR64:$src1, VR64:$src2)>;
735 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
736 (MMX_PCMPEQDrm VR64:$src1, addr:$src2)>;
738 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
739 (MMX_PCMPGTBrr VR64:$src1, VR64:$src2)>;
740 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
741 (MMX_PCMPGTBrm VR64:$src1, addr:$src2)>;
742 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
743 (MMX_PCMPGTWrr VR64:$src1, VR64:$src2)>;
744 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
745 (MMX_PCMPGTWrm VR64:$src1, addr:$src2)>;
746 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
747 (MMX_PCMPGTDrr VR64:$src1, VR64:$src2)>;
748 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
749 (MMX_PCMPGTDrm VR64:$src1, addr:$src2)>;
751 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
752 // instruction selection into a branch sequence.
753 let Uses = [EFLAGS], usesCustomInserter = 1 in {
754 def CMOV_V1I64 : I<0, Pseudo,
755 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
756 "#CMOV_V1I64 PSEUDO!",
758 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,