1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Instruction templates
18 //===----------------------------------------------------------------------===//
20 // MMXI - MMX instructions with TB prefix.
21 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
22 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
23 class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
24 : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
25 class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
26 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
27 class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
28 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
30 // Some 'special' instructions
31 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
33 [(set VR64:$dst, (v8i8 (undef)))]>,
36 // 64-bit vector undef's.
37 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
38 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
39 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
41 //===----------------------------------------------------------------------===//
42 // MMX Pattern Fragments
43 //===----------------------------------------------------------------------===//
45 def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
47 //===----------------------------------------------------------------------===//
48 // MMX EMMS Instruction
49 //===----------------------------------------------------------------------===//
51 def EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
53 //===----------------------------------------------------------------------===//
54 // MMX Scalar Instructions
55 //===----------------------------------------------------------------------===//
58 def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
59 "movd {$src, $dst|$dst, $src}", []>;
60 def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
61 "movd {$src, $dst|$dst, $src}", []>;
62 def MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
63 "movd {$src, $dst|$dst, $src}", []>;
65 def MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
66 "movq {$src, $dst|$dst, $src}", []>;
67 def MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
68 "movq {$src, $dst|$dst, $src}",
69 [(set VR64:$dst, (loadv2i32 addr:$src))]>;
70 def MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
71 "movq {$src, $dst|$dst, $src}",
72 [(store (v2i32 VR64:$src), addr:$dst)]>;
74 // Conversion instructions
75 def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
76 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
77 def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
78 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
79 def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
80 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
81 def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
82 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
83 def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
84 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
86 def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
87 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
89 def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
90 "cvtps2pi {$src, $dst|$dst, $src}", []>;
91 def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
92 "cvtps2pi {$src, $dst|$dst, $src}", []>;
93 def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
94 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
95 def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
96 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
98 // Shuffle and unpack instructions
99 def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
100 (ops VR64:$dst, VR64:$src1, i8imm:$src2),
101 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
102 def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
103 (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
104 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
107 def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
108 "movntq {$src, $dst|$dst, $src}", []>, TB,
111 def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
112 "maskmovq {$mask, $src|$src, $mask}", []>, TB,
115 //===----------------------------------------------------------------------===//
116 // Non-Instruction Patterns
117 //===----------------------------------------------------------------------===//
119 // Store 64-bit integer vector values.
120 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
121 (MOVQ64mr addr:$dst, VR64:$src)>;
122 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
123 (MOVQ64mr addr:$dst, VR64:$src)>;
126 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
127 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
128 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
129 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
130 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
131 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;