1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad,
24 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
29 [SDNPHasChain, SDNPOutFlag]>;
30 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
31 [SDNPHasChain, SDNPOutFlag]>;
32 def X86s2vec : SDNode<"X86ISD::S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
92 return X86::isSplatMask(N);
95 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVHLPSMask(N);
99 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHPMask(N);
103 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVLPMask(N);
107 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVLMask(N);
111 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVSHDUPMask(N);
115 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVSLDUPMask(N);
119 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isUNPCKLMask(N);
123 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isUNPCKHMask(N);
127 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isUNPCKL_v_undef_Mask(N);
131 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isPSHUFDMask(N);
133 }], SHUFFLE_get_shuf_imm>;
135 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFHWMask(N);
137 }], SHUFFLE_get_pshufhw_imm>;
139 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isPSHUFLWMask(N);
141 }], SHUFFLE_get_pshuflw_imm>;
143 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isPSHUFDMask(N);
145 }], SHUFFLE_get_shuf_imm>;
147 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isSHUFPMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isSHUFPMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 //===----------------------------------------------------------------------===//
156 // SSE scalar FP Instructions
157 //===----------------------------------------------------------------------===//
159 // Instruction templates
160 // SSI - SSE1 instructions with XS prefix.
161 // SDI - SSE2 instructions with XD prefix.
162 // PSI - SSE1 instructions with TB prefix.
163 // PDI - SSE2 instructions with TB and OpSize prefixes.
164 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
165 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
166 // S3I - SSE3 instructions with TB and OpSize prefixes.
167 // S3SI - SSE3 instructions with XS prefix.
168 // S3DI - SSE3 instructions with XD prefix.
169 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
170 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
171 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
172 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
173 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
175 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
177 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
179 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
180 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
182 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
183 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
184 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
185 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
186 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
187 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
189 //===----------------------------------------------------------------------===//
190 // Helpers for defining instructions that directly correspond to intrinsics.
192 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
193 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
194 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
195 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
196 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
197 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
198 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
201 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
202 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
203 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
204 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
205 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
206 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
207 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
210 class SS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
211 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
212 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
213 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
214 class SS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
215 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
216 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
217 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
218 class SD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
219 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
220 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
221 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
222 class SD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
223 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
224 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
225 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
227 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
228 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
229 [(set VR128:$dst, (IntId VR128:$src))]>;
230 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
231 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
232 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
233 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
234 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
235 [(set VR128:$dst, (IntId VR128:$src))]>;
236 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
237 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
238 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
240 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
241 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
242 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
243 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
244 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
245 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
246 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
247 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
248 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
249 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
250 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
251 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
253 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
254 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
255 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
256 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
257 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
258 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
259 (loadv4f32 addr:$src2))))]>;
260 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
261 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
262 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
263 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
264 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
265 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
266 (loadv2f64 addr:$src2))))]>;
268 // Some 'special' instructions
269 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
270 "#IMPLICIT_DEF $dst",
271 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
272 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
273 "#IMPLICIT_DEF $dst",
274 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
276 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
277 // scheduler into a branch sequence.
278 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
279 def CMOV_FR32 : I<0, Pseudo,
280 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
281 "#CMOV_FR32 PSEUDO!",
282 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
283 def CMOV_FR64 : I<0, Pseudo,
284 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
285 "#CMOV_FR64 PSEUDO!",
286 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
287 def CMOV_V4F32 : I<0, Pseudo,
288 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
289 "#CMOV_V4F32 PSEUDO!",
291 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
292 def CMOV_V2F64 : I<0, Pseudo,
293 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
294 "#CMOV_V2F64 PSEUDO!",
296 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
297 def CMOV_V2I64 : I<0, Pseudo,
298 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
299 "#CMOV_V2I64 PSEUDO!",
301 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
305 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
306 "movss {$src, $dst|$dst, $src}", []>;
307 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
308 "movss {$src, $dst|$dst, $src}",
309 [(set FR32:$dst, (loadf32 addr:$src))]>;
310 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
311 "movsd {$src, $dst|$dst, $src}", []>;
312 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
313 "movsd {$src, $dst|$dst, $src}",
314 [(set FR64:$dst, (loadf64 addr:$src))]>;
316 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
317 "movss {$src, $dst|$dst, $src}",
318 [(store FR32:$src, addr:$dst)]>;
319 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
320 "movsd {$src, $dst|$dst, $src}",
321 [(store FR64:$src, addr:$dst)]>;
323 // Arithmetic instructions
324 let isTwoAddress = 1 in {
325 let isCommutable = 1 in {
326 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
327 "addss {$src2, $dst|$dst, $src2}",
328 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
329 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
330 "addsd {$src2, $dst|$dst, $src2}",
331 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
332 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
333 "mulss {$src2, $dst|$dst, $src2}",
334 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
335 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
336 "mulsd {$src2, $dst|$dst, $src2}",
337 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
340 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
341 "addss {$src2, $dst|$dst, $src2}",
342 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
343 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
344 "addsd {$src2, $dst|$dst, $src2}",
345 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
346 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
347 "mulss {$src2, $dst|$dst, $src2}",
348 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
349 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
350 "mulsd {$src2, $dst|$dst, $src2}",
351 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
353 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
354 "divss {$src2, $dst|$dst, $src2}",
355 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
356 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
357 "divss {$src2, $dst|$dst, $src2}",
358 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
359 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
360 "divsd {$src2, $dst|$dst, $src2}",
361 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
362 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
363 "divsd {$src2, $dst|$dst, $src2}",
364 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
366 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
367 "subss {$src2, $dst|$dst, $src2}",
368 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
369 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
370 "subss {$src2, $dst|$dst, $src2}",
371 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
372 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
373 "subsd {$src2, $dst|$dst, $src2}",
374 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
375 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
376 "subsd {$src2, $dst|$dst, $src2}",
377 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
380 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
381 "sqrtss {$src, $dst|$dst, $src}",
382 [(set FR32:$dst, (fsqrt FR32:$src))]>;
383 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
384 "sqrtss {$src, $dst|$dst, $src}",
385 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
386 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
387 "sqrtsd {$src, $dst|$dst, $src}",
388 [(set FR64:$dst, (fsqrt FR64:$src))]>;
389 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
390 "sqrtsd {$src, $dst|$dst, $src}",
391 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
393 // Aliases to match intrinsics which expect XMM operand(s).
394 let isTwoAddress = 1 in {
395 let isCommutable = 1 in {
396 def Int_ADDSSrr : SS_Intrr<0x58, "addss", int_x86_sse_add_ss>;
397 def Int_ADDSDrr : SD_Intrr<0x58, "addsd", int_x86_sse2_add_sd>;
398 def Int_MULSSrr : SS_Intrr<0x59, "mulss", int_x86_sse_mul_ss>;
399 def Int_MULSDrr : SD_Intrr<0x59, "mulsd", int_x86_sse2_mul_sd>;
402 def Int_ADDSSrm : SS_Intrm<0x58, "addss", int_x86_sse_add_ss>;
403 def Int_ADDSDrm : SD_Intrm<0x58, "addsd", int_x86_sse2_add_sd>;
404 def Int_MULSSrm : SS_Intrm<0x59, "mulss", int_x86_sse_mul_ss>;
405 def Int_MULSDrm : SD_Intrm<0x59, "mulsd", int_x86_sse2_mul_sd>;
407 def Int_DIVSSrr : SS_Intrr<0x5E, "divss", int_x86_sse_div_ss>;
408 def Int_DIVSSrm : SS_Intrm<0x5E, "divss", int_x86_sse_div_ss>;
409 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd", int_x86_sse2_div_sd>;
410 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd", int_x86_sse2_div_sd>;
412 def Int_SUBSSrr : SS_Intrr<0x5C, "subss", int_x86_sse_sub_ss>;
413 def Int_SUBSSrm : SS_Intrm<0x5C, "subss", int_x86_sse_sub_ss>;
414 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd", int_x86_sse2_sub_sd>;
415 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd", int_x86_sse2_sub_sd>;
418 defm Int_SQRTSS : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
419 defm Int_SQRTSD : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
420 defm Int_RSQRTSS : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
421 defm Int_RCPSS : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
423 let isTwoAddress = 1 in {
424 let isCommutable = 1 in {
425 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss", int_x86_sse_max_ss>;
426 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd", int_x86_sse2_max_sd>;
427 def Int_MINSSrr : SS_Intrr<0x5D, "minss", int_x86_sse_min_ss>;
428 def Int_MINSDrr : SD_Intrr<0x5D, "minsd", int_x86_sse2_min_sd>;
430 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss", int_x86_sse_max_ss>;
431 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd", int_x86_sse2_max_sd>;
432 def Int_MINSSrm : SS_Intrm<0x5D, "minss", int_x86_sse_min_ss>;
433 def Int_MINSDrm : SD_Intrm<0x5D, "minsd", int_x86_sse2_min_sd>;
436 // Conversion instructions
437 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
438 "cvttss2si {$src, $dst|$dst, $src}",
439 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
440 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
441 "cvttss2si {$src, $dst|$dst, $src}",
442 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
443 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
444 "cvttsd2si {$src, $dst|$dst, $src}",
445 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
446 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
447 "cvttsd2si {$src, $dst|$dst, $src}",
448 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
449 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
450 "cvtsd2ss {$src, $dst|$dst, $src}",
451 [(set FR32:$dst, (fround FR64:$src))]>;
452 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
453 "cvtsd2ss {$src, $dst|$dst, $src}",
454 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
455 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
456 "cvtsi2ss {$src, $dst|$dst, $src}",
457 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
458 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
459 "cvtsi2ss {$src, $dst|$dst, $src}",
460 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
461 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
462 "cvtsi2sd {$src, $dst|$dst, $src}",
463 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
464 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
465 "cvtsi2sd {$src, $dst|$dst, $src}",
466 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
468 // SSE2 instructions with XS prefix
469 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
470 "cvtss2sd {$src, $dst|$dst, $src}",
471 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
473 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
474 "cvtss2sd {$src, $dst|$dst, $src}",
475 [(set FR64:$dst, (extload addr:$src, f32))]>, XS,
478 // Match intrinsics which expect XMM operand(s).
479 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
480 "cvtss2si {$src, $dst|$dst, $src}",
481 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
482 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
483 "cvtss2si {$src, $dst|$dst, $src}",
484 [(set GR32:$dst, (int_x86_sse_cvtss2si
485 (loadv4f32 addr:$src)))]>;
486 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
487 "cvtsd2si {$src, $dst|$dst, $src}",
488 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
489 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
490 "cvtsd2si {$src, $dst|$dst, $src}",
491 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
492 (loadv2f64 addr:$src)))]>;
494 // Aliases for intrinsics
495 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
496 "cvttss2si {$src, $dst|$dst, $src}",
497 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
498 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
499 "cvttss2si {$src, $dst|$dst, $src}",
500 [(set GR32:$dst, (int_x86_sse_cvttss2si
501 (loadv4f32 addr:$src)))]>;
502 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
503 "cvttsd2si {$src, $dst|$dst, $src}",
504 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
505 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
506 "cvttsd2si {$src, $dst|$dst, $src}",
507 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
508 (loadv2f64 addr:$src)))]>;
510 let isTwoAddress = 1 in {
511 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
512 (ops VR128:$dst, VR128:$src1, GR32:$src2),
513 "cvtsi2ss {$src2, $dst|$dst, $src2}",
514 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
516 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
517 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
518 "cvtsi2ss {$src2, $dst|$dst, $src2}",
519 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
520 (loadi32 addr:$src2)))]>;
523 // Comparison instructions
524 let isTwoAddress = 1 in {
525 def CMPSSrr : SSI<0xC2, MRMSrcReg,
526 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
527 "cmp${cc}ss {$src, $dst|$dst, $src}",
529 def CMPSSrm : SSI<0xC2, MRMSrcMem,
530 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
531 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
532 def CMPSDrr : SDI<0xC2, MRMSrcReg,
533 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
534 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
535 def CMPSDrm : SDI<0xC2, MRMSrcMem,
536 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
537 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
540 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
541 "ucomiss {$src2, $src1|$src1, $src2}",
542 [(X86cmp FR32:$src1, FR32:$src2)]>;
543 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
544 "ucomiss {$src2, $src1|$src1, $src2}",
545 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
546 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
547 "ucomisd {$src2, $src1|$src1, $src2}",
548 [(X86cmp FR64:$src1, FR64:$src2)]>;
549 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
550 "ucomisd {$src2, $src1|$src1, $src2}",
551 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
553 // Aliases to match intrinsics which expect XMM operand(s).
554 let isTwoAddress = 1 in {
555 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
556 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
557 "cmp${cc}ss {$src, $dst|$dst, $src}",
558 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
559 VR128:$src, imm:$cc))]>;
560 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
561 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
562 "cmp${cc}ss {$src, $dst|$dst, $src}",
563 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
564 (load addr:$src), imm:$cc))]>;
565 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
566 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
567 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
568 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
569 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
570 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
573 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
574 "ucomiss {$src2, $src1|$src1, $src2}",
575 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
576 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
577 "ucomiss {$src2, $src1|$src1, $src2}",
578 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
579 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
580 "ucomisd {$src2, $src1|$src1, $src2}",
581 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
582 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
583 "ucomisd {$src2, $src1|$src1, $src2}",
584 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
586 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
587 "comiss {$src2, $src1|$src1, $src2}",
588 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
589 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
590 "comiss {$src2, $src1|$src1, $src2}",
591 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
592 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
593 "comisd {$src2, $src1|$src1, $src2}",
594 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
595 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
596 "comisd {$src2, $src1|$src1, $src2}",
597 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
599 // Aliases of packed instructions for scalar use. These all have names that
602 // Alias instructions that map fld0 to pxor for sse.
603 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
604 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
605 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
606 Requires<[HasSSE1]>, TB, OpSize;
607 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
608 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
609 Requires<[HasSSE2]>, TB, OpSize;
611 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
612 // Upper bits are disregarded.
613 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
614 "movaps {$src, $dst|$dst, $src}", []>;
615 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
616 "movapd {$src, $dst|$dst, $src}", []>;
618 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
619 // Upper bits are disregarded.
620 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
621 "movaps {$src, $dst|$dst, $src}",
622 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
623 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
624 "movapd {$src, $dst|$dst, $src}",
625 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
627 // Alias bitwise logical operations using SSE logical ops on packed FP values.
628 let isTwoAddress = 1 in {
629 let isCommutable = 1 in {
630 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
631 "andps {$src2, $dst|$dst, $src2}",
632 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
633 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
634 "andpd {$src2, $dst|$dst, $src2}",
635 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
636 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
637 "orps {$src2, $dst|$dst, $src2}", []>;
638 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
639 "orpd {$src2, $dst|$dst, $src2}", []>;
640 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
641 "xorps {$src2, $dst|$dst, $src2}",
642 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
643 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
644 "xorpd {$src2, $dst|$dst, $src2}",
645 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
647 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
648 "andps {$src2, $dst|$dst, $src2}",
649 [(set FR32:$dst, (X86fand FR32:$src1,
650 (X86loadpf32 addr:$src2)))]>;
651 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
652 "andpd {$src2, $dst|$dst, $src2}",
653 [(set FR64:$dst, (X86fand FR64:$src1,
654 (X86loadpf64 addr:$src2)))]>;
655 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
656 "orps {$src2, $dst|$dst, $src2}", []>;
657 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
658 "orpd {$src2, $dst|$dst, $src2}", []>;
659 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
660 "xorps {$src2, $dst|$dst, $src2}",
661 [(set FR32:$dst, (X86fxor FR32:$src1,
662 (X86loadpf32 addr:$src2)))]>;
663 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
664 "xorpd {$src2, $dst|$dst, $src2}",
665 [(set FR64:$dst, (X86fxor FR64:$src1,
666 (X86loadpf64 addr:$src2)))]>;
668 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
669 "andnps {$src2, $dst|$dst, $src2}", []>;
670 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
671 "andnps {$src2, $dst|$dst, $src2}", []>;
672 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
673 "andnpd {$src2, $dst|$dst, $src2}", []>;
674 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
675 "andnpd {$src2, $dst|$dst, $src2}", []>;
678 //===----------------------------------------------------------------------===//
679 // SSE packed FP Instructions
680 //===----------------------------------------------------------------------===//
682 // Some 'special' instructions
683 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
684 "#IMPLICIT_DEF $dst",
685 [(set VR128:$dst, (v4f32 (undef)))]>,
689 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
690 "movaps {$src, $dst|$dst, $src}", []>;
691 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
692 "movaps {$src, $dst|$dst, $src}",
693 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
694 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
695 "movapd {$src, $dst|$dst, $src}", []>;
696 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
697 "movapd {$src, $dst|$dst, $src}",
698 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
700 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
701 "movaps {$src, $dst|$dst, $src}",
702 [(store (v4f32 VR128:$src), addr:$dst)]>;
703 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
704 "movapd {$src, $dst|$dst, $src}",
705 [(store (v2f64 VR128:$src), addr:$dst)]>;
707 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
708 "movups {$src, $dst|$dst, $src}", []>;
709 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
710 "movups {$src, $dst|$dst, $src}",
711 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
712 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
713 "movups {$src, $dst|$dst, $src}",
714 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
715 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
716 "movupd {$src, $dst|$dst, $src}", []>;
717 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
718 "movupd {$src, $dst|$dst, $src}",
719 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
720 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
721 "movupd {$src, $dst|$dst, $src}",
722 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
724 let isTwoAddress = 1 in {
725 let AddedComplexity = 20 in {
726 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
727 "movlps {$src2, $dst|$dst, $src2}",
729 (v4f32 (vector_shuffle VR128:$src1,
730 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
731 MOVLP_shuffle_mask)))]>;
732 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
733 "movlpd {$src2, $dst|$dst, $src2}",
735 (v2f64 (vector_shuffle VR128:$src1,
736 (scalar_to_vector (loadf64 addr:$src2)),
737 MOVLP_shuffle_mask)))]>;
738 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
739 "movhps {$src2, $dst|$dst, $src2}",
741 (v4f32 (vector_shuffle VR128:$src1,
742 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
743 MOVHP_shuffle_mask)))]>;
744 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
745 "movhpd {$src2, $dst|$dst, $src2}",
747 (v2f64 (vector_shuffle VR128:$src1,
748 (scalar_to_vector (loadf64 addr:$src2)),
749 MOVHP_shuffle_mask)))]>;
753 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
754 "movlps {$src, $dst|$dst, $src}",
755 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
756 (iPTR 0))), addr:$dst)]>;
757 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
758 "movlpd {$src, $dst|$dst, $src}",
759 [(store (f64 (vector_extract (v2f64 VR128:$src),
760 (iPTR 0))), addr:$dst)]>;
762 // v2f64 extract element 1 is always custom lowered to unpack high to low
763 // and extract element 0 so the non-store version isn't too horrible.
764 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
765 "movhps {$src, $dst|$dst, $src}",
766 [(store (f64 (vector_extract
767 (v2f64 (vector_shuffle
768 (bc_v2f64 (v4f32 VR128:$src)), (undef),
769 UNPCKH_shuffle_mask)), (iPTR 0))),
771 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
772 "movhpd {$src, $dst|$dst, $src}",
773 [(store (f64 (vector_extract
774 (v2f64 (vector_shuffle VR128:$src, (undef),
775 UNPCKH_shuffle_mask)), (iPTR 0))),
778 let isTwoAddress = 1 in {
779 let AddedComplexity = 20 in {
780 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
781 "movlhps {$src2, $dst|$dst, $src2}",
783 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
784 MOVHP_shuffle_mask)))]>;
786 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
787 "movhlps {$src2, $dst|$dst, $src2}",
789 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
790 MOVHLPS_shuffle_mask)))]>;
794 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
795 "movshdup {$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (v4f32 (vector_shuffle
798 MOVSHDUP_shuffle_mask)))]>;
799 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
800 "movshdup {$src, $dst|$dst, $src}",
801 [(set VR128:$dst, (v4f32 (vector_shuffle
802 (loadv4f32 addr:$src), (undef),
803 MOVSHDUP_shuffle_mask)))]>;
805 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
806 "movsldup {$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (v4f32 (vector_shuffle
809 MOVSLDUP_shuffle_mask)))]>;
810 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
811 "movsldup {$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (v4f32 (vector_shuffle
813 (loadv4f32 addr:$src), (undef),
814 MOVSLDUP_shuffle_mask)))]>;
816 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
817 "movddup {$src, $dst|$dst, $src}",
818 [(set VR128:$dst, (v2f64 (vector_shuffle
820 SSE_splat_v2_mask)))]>;
821 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
822 "movddup {$src, $dst|$dst, $src}",
823 [(set VR128:$dst, (v2f64 (vector_shuffle
824 (scalar_to_vector (loadf64 addr:$src)),
826 SSE_splat_v2_mask)))]>;
828 // SSE2 instructions without OpSize prefix
829 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
830 "cvtdq2ps {$src, $dst|$dst, $src}",
831 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
832 TB, Requires<[HasSSE2]>;
833 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
834 "cvtdq2ps {$src, $dst|$dst, $src}",
835 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
836 (bc_v4i32 (loadv2i64 addr:$src))))]>,
837 TB, Requires<[HasSSE2]>;
839 // SSE2 instructions with XS prefix
840 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
841 "cvtdq2pd {$src, $dst|$dst, $src}",
842 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
843 XS, Requires<[HasSSE2]>;
844 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
845 "cvtdq2pd {$src, $dst|$dst, $src}",
846 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
847 (bc_v4i32 (loadv2i64 addr:$src))))]>,
848 XS, Requires<[HasSSE2]>;
850 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
851 "cvtps2dq {$src, $dst|$dst, $src}",
852 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
853 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
854 "cvtps2dq {$src, $dst|$dst, $src}",
855 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
856 (loadv4f32 addr:$src)))]>;
857 // SSE2 packed instructions with XS prefix
858 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
859 "cvttps2dq {$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
861 XS, Requires<[HasSSE2]>;
862 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
863 "cvttps2dq {$src, $dst|$dst, $src}",
864 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
865 (loadv4f32 addr:$src)))]>,
866 XS, Requires<[HasSSE2]>;
868 // SSE2 packed instructions with XD prefix
869 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
870 "cvtpd2dq {$src, $dst|$dst, $src}",
871 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
872 XD, Requires<[HasSSE2]>;
873 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
874 "cvtpd2dq {$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
876 (loadv2f64 addr:$src)))]>,
877 XD, Requires<[HasSSE2]>;
878 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
879 "cvttpd2dq {$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
881 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
882 "cvttpd2dq {$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
884 (loadv2f64 addr:$src)))]>;
886 // SSE2 instructions without OpSize prefix
887 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
888 "cvtps2pd {$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
890 TB, Requires<[HasSSE2]>;
891 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
892 "cvtps2pd {$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
894 (loadv4f32 addr:$src)))]>,
895 TB, Requires<[HasSSE2]>;
897 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
898 "cvtpd2ps {$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
900 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
901 "cvtpd2ps {$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
903 (loadv2f64 addr:$src)))]>;
905 // Match intrinsics which expect XMM operand(s).
906 // Aliases for intrinsics
907 let isTwoAddress = 1 in {
908 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
909 (ops VR128:$dst, VR128:$src1, GR32:$src2),
910 "cvtsi2sd {$src2, $dst|$dst, $src2}",
911 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
913 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
914 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
915 "cvtsi2sd {$src2, $dst|$dst, $src2}",
916 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
917 (loadi32 addr:$src2)))]>;
918 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
919 (ops VR128:$dst, VR128:$src1, VR128:$src2),
920 "cvtsd2ss {$src2, $dst|$dst, $src2}",
921 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
923 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
924 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
925 "cvtsd2ss {$src2, $dst|$dst, $src2}",
926 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
927 (loadv2f64 addr:$src2)))]>;
928 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
929 (ops VR128:$dst, VR128:$src1, VR128:$src2),
930 "cvtss2sd {$src2, $dst|$dst, $src2}",
931 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
934 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
935 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
936 "cvtss2sd {$src2, $dst|$dst, $src2}",
937 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
938 (loadv4f32 addr:$src2)))]>, XS,
943 let isTwoAddress = 1 in {
944 let isCommutable = 1 in {
945 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
946 "addps {$src2, $dst|$dst, $src2}",
947 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
948 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
949 "addpd {$src2, $dst|$dst, $src2}",
950 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
951 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
952 "mulps {$src2, $dst|$dst, $src2}",
953 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
954 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
955 "mulpd {$src2, $dst|$dst, $src2}",
956 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
959 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
960 "addps {$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
962 (load addr:$src2))))]>;
963 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
964 "addpd {$src2, $dst|$dst, $src2}",
965 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
966 (load addr:$src2))))]>;
967 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
968 "mulps {$src2, $dst|$dst, $src2}",
969 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
970 (load addr:$src2))))]>;
971 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
972 "mulpd {$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
974 (load addr:$src2))))]>;
976 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
977 "divps {$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
979 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
980 "divps {$src2, $dst|$dst, $src2}",
981 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
982 (load addr:$src2))))]>;
983 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
984 "divpd {$src2, $dst|$dst, $src2}",
985 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
986 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
987 "divpd {$src2, $dst|$dst, $src2}",
988 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
989 (load addr:$src2))))]>;
991 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
992 "subps {$src2, $dst|$dst, $src2}",
993 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
994 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
995 "subps {$src2, $dst|$dst, $src2}",
996 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
997 (load addr:$src2))))]>;
998 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
999 "subpd {$src2, $dst|$dst, $src2}",
1000 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1001 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1002 "subpd {$src2, $dst|$dst, $src2}",
1003 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1004 (load addr:$src2))))]>;
1006 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1007 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1008 "addsubps {$src2, $dst|$dst, $src2}",
1009 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1011 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1012 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1013 "addsubps {$src2, $dst|$dst, $src2}",
1014 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1015 (loadv4f32 addr:$src2)))]>;
1016 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1017 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1018 "addsubpd {$src2, $dst|$dst, $src2}",
1019 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1021 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1022 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1023 "addsubpd {$src2, $dst|$dst, $src2}",
1024 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1025 (loadv2f64 addr:$src2)))]>;
1028 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1029 int_x86_sse_sqrt_ps>;
1030 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1031 int_x86_sse_sqrt_ps>;
1032 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1033 int_x86_sse2_sqrt_pd>;
1034 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1035 int_x86_sse2_sqrt_pd>;
1037 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1038 int_x86_sse_rsqrt_ps>;
1039 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1040 int_x86_sse_rsqrt_ps>;
1041 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1042 int_x86_sse_rcp_ps>;
1043 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1044 int_x86_sse_rcp_ps>;
1046 let isTwoAddress = 1 in {
1047 let isCommutable = 1 in {
1048 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1049 int_x86_sse_max_ps>;
1050 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1051 int_x86_sse2_max_pd>;
1052 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1053 int_x86_sse_min_ps>;
1054 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1055 int_x86_sse2_min_pd>;
1057 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1058 int_x86_sse_max_ps>;
1059 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1060 int_x86_sse2_max_pd>;
1061 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1062 int_x86_sse_min_ps>;
1063 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1064 int_x86_sse2_min_pd>;
1068 let isTwoAddress = 1 in {
1069 let isCommutable = 1 in {
1070 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1071 "andps {$src2, $dst|$dst, $src2}",
1072 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1073 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1074 "andpd {$src2, $dst|$dst, $src2}",
1076 (and (bc_v2i64 (v2f64 VR128:$src1)),
1077 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1078 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1079 "orps {$src2, $dst|$dst, $src2}",
1080 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1081 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1082 "orpd {$src2, $dst|$dst, $src2}",
1084 (or (bc_v2i64 (v2f64 VR128:$src1)),
1085 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1086 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1087 "xorps {$src2, $dst|$dst, $src2}",
1088 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1089 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1090 "xorpd {$src2, $dst|$dst, $src2}",
1092 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1093 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1095 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1096 "andps {$src2, $dst|$dst, $src2}",
1097 [(set VR128:$dst, (and VR128:$src1,
1098 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1099 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1100 "andpd {$src2, $dst|$dst, $src2}",
1102 (and (bc_v2i64 (v2f64 VR128:$src1)),
1103 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1104 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1105 "orps {$src2, $dst|$dst, $src2}",
1106 [(set VR128:$dst, (or VR128:$src1,
1107 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1108 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1109 "orpd {$src2, $dst|$dst, $src2}",
1111 (or (bc_v2i64 (v2f64 VR128:$src1)),
1112 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1113 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1114 "xorps {$src2, $dst|$dst, $src2}",
1115 [(set VR128:$dst, (xor VR128:$src1,
1116 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1117 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1118 "xorpd {$src2, $dst|$dst, $src2}",
1120 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1121 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1122 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1123 "andnps {$src2, $dst|$dst, $src2}",
1124 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1125 (bc_v2i64 (v4i32 immAllOnesV))),
1127 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1128 "andnps {$src2, $dst|$dst, $src2}",
1129 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1130 (bc_v2i64 (v4i32 immAllOnesV))),
1131 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1132 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1133 "andnpd {$src2, $dst|$dst, $src2}",
1135 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1136 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1137 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1138 "andnpd {$src2, $dst|$dst, $src2}",
1140 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1141 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1144 let isTwoAddress = 1 in {
1145 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1146 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1147 "cmp${cc}ps {$src, $dst|$dst, $src}",
1148 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1149 VR128:$src, imm:$cc))]>;
1150 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1151 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1152 "cmp${cc}ps {$src, $dst|$dst, $src}",
1153 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1154 (load addr:$src), imm:$cc))]>;
1155 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1156 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1157 "cmp${cc}pd {$src, $dst|$dst, $src}",
1158 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1159 VR128:$src, imm:$cc))]>;
1160 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1161 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1162 "cmp${cc}pd {$src, $dst|$dst, $src}",
1163 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1164 (load addr:$src), imm:$cc))]>;
1167 // Shuffle and unpack instructions
1168 let isTwoAddress = 1 in {
1169 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1170 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1171 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1172 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1173 [(set VR128:$dst, (v4f32 (vector_shuffle
1174 VR128:$src1, VR128:$src2,
1175 SHUFP_shuffle_mask:$src3)))]>;
1176 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1177 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1178 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1179 [(set VR128:$dst, (v4f32 (vector_shuffle
1180 VR128:$src1, (load addr:$src2),
1181 SHUFP_shuffle_mask:$src3)))]>;
1182 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1183 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1184 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1185 [(set VR128:$dst, (v2f64 (vector_shuffle
1186 VR128:$src1, VR128:$src2,
1187 SHUFP_shuffle_mask:$src3)))]>;
1188 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1189 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1190 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1191 [(set VR128:$dst, (v2f64 (vector_shuffle
1192 VR128:$src1, (load addr:$src2),
1193 SHUFP_shuffle_mask:$src3)))]>;
1195 let AddedComplexity = 10 in {
1196 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1197 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1198 "unpckhps {$src2, $dst|$dst, $src2}",
1199 [(set VR128:$dst, (v4f32 (vector_shuffle
1200 VR128:$src1, VR128:$src2,
1201 UNPCKH_shuffle_mask)))]>;
1202 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1203 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1204 "unpckhps {$src2, $dst|$dst, $src2}",
1205 [(set VR128:$dst, (v4f32 (vector_shuffle
1206 VR128:$src1, (load addr:$src2),
1207 UNPCKH_shuffle_mask)))]>;
1208 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1209 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1210 "unpckhpd {$src2, $dst|$dst, $src2}",
1211 [(set VR128:$dst, (v2f64 (vector_shuffle
1212 VR128:$src1, VR128:$src2,
1213 UNPCKH_shuffle_mask)))]>;
1214 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1215 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1216 "unpckhpd {$src2, $dst|$dst, $src2}",
1217 [(set VR128:$dst, (v2f64 (vector_shuffle
1218 VR128:$src1, (load addr:$src2),
1219 UNPCKH_shuffle_mask)))]>;
1221 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1222 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1223 "unpcklps {$src2, $dst|$dst, $src2}",
1224 [(set VR128:$dst, (v4f32 (vector_shuffle
1225 VR128:$src1, VR128:$src2,
1226 UNPCKL_shuffle_mask)))]>;
1227 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1228 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1229 "unpcklps {$src2, $dst|$dst, $src2}",
1230 [(set VR128:$dst, (v4f32 (vector_shuffle
1231 VR128:$src1, (load addr:$src2),
1232 UNPCKL_shuffle_mask)))]>;
1233 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1234 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1235 "unpcklpd {$src2, $dst|$dst, $src2}",
1236 [(set VR128:$dst, (v2f64 (vector_shuffle
1237 VR128:$src1, VR128:$src2,
1238 UNPCKL_shuffle_mask)))]>;
1239 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1240 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1241 "unpcklpd {$src2, $dst|$dst, $src2}",
1242 [(set VR128:$dst, (v2f64 (vector_shuffle
1243 VR128:$src1, (load addr:$src2),
1244 UNPCKL_shuffle_mask)))]>;
1245 } // AddedComplexity
1249 let isTwoAddress = 1 in {
1250 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1251 int_x86_sse3_hadd_ps>;
1252 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1253 int_x86_sse3_hadd_ps>;
1254 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1255 int_x86_sse3_hadd_pd>;
1256 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1257 int_x86_sse3_hadd_pd>;
1258 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1259 int_x86_sse3_hsub_ps>;
1260 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1261 int_x86_sse3_hsub_ps>;
1262 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1263 int_x86_sse3_hsub_pd>;
1264 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1265 int_x86_sse3_hsub_pd>;
1268 //===----------------------------------------------------------------------===//
1269 // SSE integer instructions
1270 //===----------------------------------------------------------------------===//
1272 // Move Instructions
1273 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1274 "movdqa {$src, $dst|$dst, $src}", []>;
1275 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1276 "movdqa {$src, $dst|$dst, $src}",
1277 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1278 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1279 "movdqa {$src, $dst|$dst, $src}",
1280 [(store (v2i64 VR128:$src), addr:$dst)]>;
1281 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1282 "movdqu {$src, $dst|$dst, $src}",
1283 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1284 XS, Requires<[HasSSE2]>;
1285 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1286 "movdqu {$src, $dst|$dst, $src}",
1287 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1288 XS, Requires<[HasSSE2]>;
1289 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1290 "lddqu {$src, $dst|$dst, $src}",
1291 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1293 // 128-bit Integer Arithmetic
1294 let isTwoAddress = 1 in {
1295 let isCommutable = 1 in {
1296 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1297 "paddb {$src2, $dst|$dst, $src2}",
1298 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1299 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1300 "paddw {$src2, $dst|$dst, $src2}",
1301 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1302 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1303 "paddd {$src2, $dst|$dst, $src2}",
1304 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1306 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1307 "paddq {$src2, $dst|$dst, $src2}",
1308 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1310 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1311 "paddb {$src2, $dst|$dst, $src2}",
1312 [(set VR128:$dst, (add VR128:$src1,
1313 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1314 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1315 "paddw {$src2, $dst|$dst, $src2}",
1316 [(set VR128:$dst, (add VR128:$src1,
1317 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1318 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1319 "paddd {$src2, $dst|$dst, $src2}",
1320 [(set VR128:$dst, (add VR128:$src1,
1321 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1322 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1323 "paddd {$src2, $dst|$dst, $src2}",
1324 [(set VR128:$dst, (add VR128:$src1,
1325 (loadv2i64 addr:$src2)))]>;
1327 let isCommutable = 1 in {
1328 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1329 "paddsb {$src2, $dst|$dst, $src2}",
1330 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1332 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1333 "paddsw {$src2, $dst|$dst, $src2}",
1334 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1336 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1337 "paddusb {$src2, $dst|$dst, $src2}",
1338 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1340 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1341 "paddusw {$src2, $dst|$dst, $src2}",
1342 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1345 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1346 "paddsb {$src2, $dst|$dst, $src2}",
1347 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1348 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1349 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1350 "paddsw {$src2, $dst|$dst, $src2}",
1351 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1352 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1353 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1354 "paddusb {$src2, $dst|$dst, $src2}",
1355 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1356 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1357 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1358 "paddusw {$src2, $dst|$dst, $src2}",
1359 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1360 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1363 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1364 "psubb {$src2, $dst|$dst, $src2}",
1365 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1366 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1367 "psubw {$src2, $dst|$dst, $src2}",
1368 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1369 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1370 "psubd {$src2, $dst|$dst, $src2}",
1371 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1372 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1373 "psubq {$src2, $dst|$dst, $src2}",
1374 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1376 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1377 "psubb {$src2, $dst|$dst, $src2}",
1378 [(set VR128:$dst, (sub VR128:$src1,
1379 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1380 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1381 "psubw {$src2, $dst|$dst, $src2}",
1382 [(set VR128:$dst, (sub VR128:$src1,
1383 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1384 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1385 "psubd {$src2, $dst|$dst, $src2}",
1386 [(set VR128:$dst, (sub VR128:$src1,
1387 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1388 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1389 "psubd {$src2, $dst|$dst, $src2}",
1390 [(set VR128:$dst, (sub VR128:$src1,
1391 (loadv2i64 addr:$src2)))]>;
1393 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1394 "psubsb {$src2, $dst|$dst, $src2}",
1395 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1397 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1398 "psubsw {$src2, $dst|$dst, $src2}",
1399 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1401 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1402 "psubusb {$src2, $dst|$dst, $src2}",
1403 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1405 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1406 "psubusw {$src2, $dst|$dst, $src2}",
1407 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1410 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1411 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1412 "psubsb {$src2, $dst|$dst, $src2}",
1413 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1414 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1415 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1416 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1417 "psubsw {$src2, $dst|$dst, $src2}",
1418 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1419 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1420 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1421 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1422 "psubusb {$src2, $dst|$dst, $src2}",
1423 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1424 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1425 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1426 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1427 "psubusw {$src2, $dst|$dst, $src2}",
1428 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1429 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1431 let isCommutable = 1 in {
1432 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1433 "pmulhuw {$src2, $dst|$dst, $src2}",
1434 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1436 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1437 "pmulhw {$src2, $dst|$dst, $src2}",
1438 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1440 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1441 "pmullw {$src2, $dst|$dst, $src2}",
1442 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1443 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1444 "pmuludq {$src2, $dst|$dst, $src2}",
1445 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1448 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1449 "pmulhuw {$src2, $dst|$dst, $src2}",
1450 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1451 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1452 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1453 "pmulhw {$src2, $dst|$dst, $src2}",
1454 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1455 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1456 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1457 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1458 "pmullw {$src2, $dst|$dst, $src2}",
1459 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1460 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1461 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1462 "pmuludq {$src2, $dst|$dst, $src2}",
1463 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1464 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1466 let isCommutable = 1 in {
1467 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1468 "pmaddwd {$src2, $dst|$dst, $src2}",
1469 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1472 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1473 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1474 "pmaddwd {$src2, $dst|$dst, $src2}",
1475 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1476 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1478 let isCommutable = 1 in {
1479 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1480 "pavgb {$src2, $dst|$dst, $src2}",
1481 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1483 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1484 "pavgw {$src2, $dst|$dst, $src2}",
1485 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1488 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1489 "pavgb {$src2, $dst|$dst, $src2}",
1490 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1491 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1492 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1493 "pavgw {$src2, $dst|$dst, $src2}",
1494 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1495 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1497 let isCommutable = 1 in {
1498 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1499 "pmaxub {$src2, $dst|$dst, $src2}",
1500 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1502 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1503 "pmaxsw {$src2, $dst|$dst, $src2}",
1504 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1507 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1508 "pmaxub {$src2, $dst|$dst, $src2}",
1509 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1510 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1511 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1512 "pmaxsw {$src2, $dst|$dst, $src2}",
1513 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1514 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1516 let isCommutable = 1 in {
1517 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1518 "pminub {$src2, $dst|$dst, $src2}",
1519 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1521 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1522 "pminsw {$src2, $dst|$dst, $src2}",
1523 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1526 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1527 "pminub {$src2, $dst|$dst, $src2}",
1528 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1529 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1530 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1531 "pminsw {$src2, $dst|$dst, $src2}",
1532 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1533 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1536 let isCommutable = 1 in {
1537 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1538 "psadbw {$src2, $dst|$dst, $src2}",
1539 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1542 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1543 "psadbw {$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1545 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1548 let isTwoAddress = 1 in {
1549 def PSLLWrr : PDI<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1550 "psllw {$src2, $dst|$dst, $src2}",
1551 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1553 def PSLLWrm : PDI<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1554 "psllw {$src2, $dst|$dst, $src2}",
1555 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1556 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1557 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1558 "psllw {$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1560 (scalar_to_vector (i32 imm:$src2))))]>;
1561 def PSLLDrr : PDI<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1562 "pslld {$src2, $dst|$dst, $src2}",
1563 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1565 def PSLLDrm : PDI<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1566 "pslld {$src2, $dst|$dst, $src2}",
1567 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1568 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1569 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1570 "pslld {$src2, $dst|$dst, $src2}",
1571 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1572 (scalar_to_vector (i32 imm:$src2))))]>;
1573 def PSLLQrr : PDI<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1574 "psllq {$src2, $dst|$dst, $src2}",
1575 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1577 def PSLLQrm : PDI<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1578 "psllq {$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1580 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1581 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1582 "psllq {$src2, $dst|$dst, $src2}",
1583 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1584 (scalar_to_vector (i32 imm:$src2))))]>;
1585 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1586 "pslldq {$src2, $dst|$dst, $src2}", []>;
1588 def PSRLWrr : PDI<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1589 "psrlw {$src2, $dst|$dst, $src2}",
1590 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1592 def PSRLWrm : PDI<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1593 "psrlw {$src2, $dst|$dst, $src2}",
1594 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1595 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1596 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1597 "psrlw {$src2, $dst|$dst, $src2}",
1598 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1599 (scalar_to_vector (i32 imm:$src2))))]>;
1600 def PSRLDrr : PDI<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1601 "psrld {$src2, $dst|$dst, $src2}",
1602 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1604 def PSRLDrm : PDI<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1605 "psrld {$src2, $dst|$dst, $src2}",
1606 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1607 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1608 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1609 "psrld {$src2, $dst|$dst, $src2}",
1610 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1611 (scalar_to_vector (i32 imm:$src2))))]>;
1612 def PSRLQrr : PDI<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1613 "psrlq {$src2, $dst|$dst, $src2}",
1614 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1616 def PSRLQrm : PDI<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1617 "psrlq {$src2, $dst|$dst, $src2}",
1618 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1619 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1620 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1621 "psrlq {$src2, $dst|$dst, $src2}",
1622 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1623 (scalar_to_vector (i32 imm:$src2))))]>;
1624 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1625 "psrldq {$src2, $dst|$dst, $src2}", []>;
1627 def PSRAWrr : PDI<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1628 "psraw {$src2, $dst|$dst, $src2}",
1629 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1631 def PSRAWrm : PDI<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1632 "psraw {$src2, $dst|$dst, $src2}",
1633 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1634 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1635 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1636 "psraw {$src2, $dst|$dst, $src2}",
1637 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1638 (scalar_to_vector (i32 imm:$src2))))]>;
1639 def PSRADrr : PDI<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1640 "psrad {$src2, $dst|$dst, $src2}",
1641 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1643 def PSRADrm : PDI<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1644 "psrad {$src2, $dst|$dst, $src2}",
1645 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1646 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1647 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1648 "psrad {$src2, $dst|$dst, $src2}",
1649 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1650 (scalar_to_vector (i32 imm:$src2))))]>;
1654 let isTwoAddress = 1 in {
1655 let isCommutable = 1 in {
1656 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1657 "pand {$src2, $dst|$dst, $src2}",
1658 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1659 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1660 "por {$src2, $dst|$dst, $src2}",
1661 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1662 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1663 "pxor {$src2, $dst|$dst, $src2}",
1664 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1667 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1668 "pand {$src2, $dst|$dst, $src2}",
1669 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1670 (load addr:$src2))))]>;
1671 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1672 "por {$src2, $dst|$dst, $src2}",
1673 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1674 (load addr:$src2))))]>;
1675 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1676 "pxor {$src2, $dst|$dst, $src2}",
1677 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1678 (load addr:$src2))))]>;
1680 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1681 "pandn {$src2, $dst|$dst, $src2}",
1682 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1685 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1686 "pandn {$src2, $dst|$dst, $src2}",
1687 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1688 (load addr:$src2))))]>;
1691 // SSE2 Integer comparison
1692 let isTwoAddress = 1 in {
1693 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1694 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1695 "pcmpeqb {$src2, $dst|$dst, $src2}",
1696 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1698 def PCMPEQBrm : PDI<0x74, MRMSrcMem,
1699 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1700 "pcmpeqb {$src2, $dst|$dst, $src2}",
1701 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1702 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1703 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1704 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1705 "pcmpeqw {$src2, $dst|$dst, $src2}",
1706 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1708 def PCMPEQWrm : PDI<0x75, MRMSrcMem,
1709 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1710 "pcmpeqw {$src2, $dst|$dst, $src2}",
1711 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1712 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1713 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1714 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1715 "pcmpeqd {$src2, $dst|$dst, $src2}",
1716 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1718 def PCMPEQDrm : PDI<0x76, MRMSrcMem,
1719 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1720 "pcmpeqd {$src2, $dst|$dst, $src2}",
1721 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1722 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1724 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1725 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1726 "pcmpgtb {$src2, $dst|$dst, $src2}",
1727 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1729 def PCMPGTBrm : PDI<0x64, MRMSrcMem,
1730 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1731 "pcmpgtb {$src2, $dst|$dst, $src2}",
1732 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1733 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1734 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1735 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1736 "pcmpgtw {$src2, $dst|$dst, $src2}",
1737 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1739 def PCMPGTWrm : PDI<0x65, MRMSrcMem,
1740 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1741 "pcmpgtw {$src2, $dst|$dst, $src2}",
1742 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1743 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1744 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1745 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1746 "pcmpgtd {$src2, $dst|$dst, $src2}",
1747 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1749 def PCMPGTDrm : PDI<0x66, MRMSrcMem,
1750 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1751 "pcmpgtd {$src2, $dst|$dst, $src2}",
1752 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1753 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1756 // Pack instructions
1757 let isTwoAddress = 1 in {
1758 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1760 "packsswb {$src2, $dst|$dst, $src2}",
1761 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1764 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1766 "packsswb {$src2, $dst|$dst, $src2}",
1767 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1769 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1770 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1772 "packssdw {$src2, $dst|$dst, $src2}",
1773 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1776 def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1778 "packssdw {$src2, $dst|$dst, $src2}",
1779 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1781 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1782 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1784 "packuswb {$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1788 def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1790 "packuswb {$src2, $dst|$dst, $src2}",
1791 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1793 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1796 // Shuffle and unpack instructions
1797 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1798 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1799 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1800 [(set VR128:$dst, (v4i32 (vector_shuffle
1801 VR128:$src1, (undef),
1802 PSHUFD_shuffle_mask:$src2)))]>;
1803 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1804 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1805 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1806 [(set VR128:$dst, (v4i32 (vector_shuffle
1807 (bc_v4i32 (loadv2i64 addr:$src1)),
1809 PSHUFD_shuffle_mask:$src2)))]>;
1811 // SSE2 with ImmT == Imm8 and XS prefix.
1812 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1813 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1814 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1815 [(set VR128:$dst, (v8i16 (vector_shuffle
1816 VR128:$src1, (undef),
1817 PSHUFHW_shuffle_mask:$src2)))]>,
1818 XS, Requires<[HasSSE2]>;
1819 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1820 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1821 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1822 [(set VR128:$dst, (v8i16 (vector_shuffle
1823 (bc_v8i16 (loadv2i64 addr:$src1)),
1825 PSHUFHW_shuffle_mask:$src2)))]>,
1826 XS, Requires<[HasSSE2]>;
1828 // SSE2 with ImmT == Imm8 and XD prefix.
1829 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1830 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1831 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1832 [(set VR128:$dst, (v8i16 (vector_shuffle
1833 VR128:$src1, (undef),
1834 PSHUFLW_shuffle_mask:$src2)))]>,
1835 XD, Requires<[HasSSE2]>;
1836 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1837 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1838 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1839 [(set VR128:$dst, (v8i16 (vector_shuffle
1840 (bc_v8i16 (loadv2i64 addr:$src1)),
1842 PSHUFLW_shuffle_mask:$src2)))]>,
1843 XD, Requires<[HasSSE2]>;
1845 let isTwoAddress = 1 in {
1846 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1847 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1848 "punpcklbw {$src2, $dst|$dst, $src2}",
1850 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1851 UNPCKL_shuffle_mask)))]>;
1852 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1853 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1854 "punpcklbw {$src2, $dst|$dst, $src2}",
1856 (v16i8 (vector_shuffle VR128:$src1,
1857 (bc_v16i8 (loadv2i64 addr:$src2)),
1858 UNPCKL_shuffle_mask)))]>;
1859 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1860 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1861 "punpcklwd {$src2, $dst|$dst, $src2}",
1863 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1864 UNPCKL_shuffle_mask)))]>;
1865 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1866 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1867 "punpcklwd {$src2, $dst|$dst, $src2}",
1869 (v8i16 (vector_shuffle VR128:$src1,
1870 (bc_v8i16 (loadv2i64 addr:$src2)),
1871 UNPCKL_shuffle_mask)))]>;
1872 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1873 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1874 "punpckldq {$src2, $dst|$dst, $src2}",
1876 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1877 UNPCKL_shuffle_mask)))]>;
1878 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1879 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1880 "punpckldq {$src2, $dst|$dst, $src2}",
1882 (v4i32 (vector_shuffle VR128:$src1,
1883 (bc_v4i32 (loadv2i64 addr:$src2)),
1884 UNPCKL_shuffle_mask)))]>;
1885 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1886 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1887 "punpcklqdq {$src2, $dst|$dst, $src2}",
1889 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1890 UNPCKL_shuffle_mask)))]>;
1891 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1892 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1893 "punpcklqdq {$src2, $dst|$dst, $src2}",
1895 (v2i64 (vector_shuffle VR128:$src1,
1896 (loadv2i64 addr:$src2),
1897 UNPCKL_shuffle_mask)))]>;
1899 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1900 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1901 "punpckhbw {$src2, $dst|$dst, $src2}",
1903 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1904 UNPCKH_shuffle_mask)))]>;
1905 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1906 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1907 "punpckhbw {$src2, $dst|$dst, $src2}",
1909 (v16i8 (vector_shuffle VR128:$src1,
1910 (bc_v16i8 (loadv2i64 addr:$src2)),
1911 UNPCKH_shuffle_mask)))]>;
1912 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1913 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1914 "punpckhwd {$src2, $dst|$dst, $src2}",
1916 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1917 UNPCKH_shuffle_mask)))]>;
1918 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1919 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1920 "punpckhwd {$src2, $dst|$dst, $src2}",
1922 (v8i16 (vector_shuffle VR128:$src1,
1923 (bc_v8i16 (loadv2i64 addr:$src2)),
1924 UNPCKH_shuffle_mask)))]>;
1925 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1926 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1927 "punpckhdq {$src2, $dst|$dst, $src2}",
1929 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1930 UNPCKH_shuffle_mask)))]>;
1931 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1932 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1933 "punpckhdq {$src2, $dst|$dst, $src2}",
1935 (v4i32 (vector_shuffle VR128:$src1,
1936 (bc_v4i32 (loadv2i64 addr:$src2)),
1937 UNPCKH_shuffle_mask)))]>;
1938 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1939 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1940 "punpckhqdq {$src2, $dst|$dst, $src2}",
1942 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1943 UNPCKH_shuffle_mask)))]>;
1944 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1945 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1946 "punpckhqdq {$src2, $dst|$dst, $src2}",
1948 (v2i64 (vector_shuffle VR128:$src1,
1949 (loadv2i64 addr:$src2),
1950 UNPCKH_shuffle_mask)))]>;
1954 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1955 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1956 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1957 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1958 (i32 imm:$src2)))]>;
1959 let isTwoAddress = 1 in {
1960 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1961 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
1962 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1963 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1964 GR32:$src2, (iPTR imm:$src3))))]>;
1965 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1966 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1967 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1969 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1970 (i32 (anyext (loadi16 addr:$src2))),
1971 (iPTR imm:$src3))))]>;
1974 //===----------------------------------------------------------------------===//
1975 // Miscellaneous Instructions
1976 //===----------------------------------------------------------------------===//
1979 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1980 "movmskps {$src, $dst|$dst, $src}",
1981 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1982 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1983 "movmskpd {$src, $dst|$dst, $src}",
1984 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1986 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1987 "pmovmskb {$src, $dst|$dst, $src}",
1988 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1990 // Conditional store
1991 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1992 "maskmovdqu {$mask, $src|$src, $mask}",
1993 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1996 // Prefetching loads
1997 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
1998 "prefetcht0 $src", []>;
1999 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2000 "prefetcht1 $src", []>;
2001 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2002 "prefetcht2 $src", []>;
2003 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2004 "prefetchtnta $src", []>;
2006 // Non-temporal stores
2007 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2008 "movntps {$src, $dst|$dst, $src}",
2009 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2010 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2011 "movntpd {$src, $dst|$dst, $src}",
2012 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2013 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2014 "movntdq {$src, $dst|$dst, $src}",
2015 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2016 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
2017 "movnti {$src, $dst|$dst, $src}",
2018 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2019 TB, Requires<[HasSSE2]>;
2022 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2023 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2024 TB, Requires<[HasSSE2]>;
2026 // Load, store, and memory fence
2027 def SFENCE : I<0xAE, MRM7m, (ops),
2028 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2029 def LFENCE : I<0xAE, MRM5m, (ops),
2030 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2031 def MFENCE : I<0xAE, MRM6m, (ops),
2032 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2035 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2037 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2038 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2040 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2042 // Thread synchronization
2043 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2044 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2045 TB, Requires<[HasSSE3]>;
2046 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2047 [(int_x86_sse3_mwait ECX, EAX)]>,
2048 TB, Requires<[HasSSE3]>;
2050 //===----------------------------------------------------------------------===//
2051 // Alias Instructions
2052 //===----------------------------------------------------------------------===//
2054 // Alias instructions that map zero vector to pxor / xorp* for sse.
2055 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2056 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2058 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2060 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2061 "pcmpeqd $dst, $dst",
2062 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2064 // FR32 / FR64 to 128-bit vector conversion.
2065 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2066 "movss {$src, $dst|$dst, $src}",
2068 (v4f32 (scalar_to_vector FR32:$src)))]>;
2069 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2070 "movss {$src, $dst|$dst, $src}",
2072 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2073 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2074 "movsd {$src, $dst|$dst, $src}",
2076 (v2f64 (scalar_to_vector FR64:$src)))]>;
2077 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2078 "movsd {$src, $dst|$dst, $src}",
2080 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2082 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2083 "movd {$src, $dst|$dst, $src}",
2085 (v4i32 (scalar_to_vector GR32:$src)))]>;
2086 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2087 "movd {$src, $dst|$dst, $src}",
2089 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2090 // SSE2 instructions with XS prefix
2091 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2092 "movq {$src, $dst|$dst, $src}",
2094 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2095 Requires<[HasSSE2]>;
2096 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2097 "movq {$src, $dst|$dst, $src}",
2099 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2100 Requires<[HasSSE2]>;
2101 // FIXME: may not be able to eliminate this movss with coalescing the src and
2102 // dest register classes are different. We really want to write this pattern
2104 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2105 // (f32 FR32:$src)>;
2106 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2107 "movss {$src, $dst|$dst, $src}",
2108 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2110 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2111 "movss {$src, $dst|$dst, $src}",
2112 [(store (f32 (vector_extract (v4f32 VR128:$src),
2113 (iPTR 0))), addr:$dst)]>;
2114 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2115 "movsd {$src, $dst|$dst, $src}",
2116 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2118 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2119 "movsd {$src, $dst|$dst, $src}",
2120 [(store (f64 (vector_extract (v2f64 VR128:$src),
2121 (iPTR 0))), addr:$dst)]>;
2122 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
2123 "movd {$src, $dst|$dst, $src}",
2124 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2126 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2127 "movd {$src, $dst|$dst, $src}",
2128 [(store (i32 (vector_extract (v4i32 VR128:$src),
2129 (iPTR 0))), addr:$dst)]>;
2131 // Move to lower bits of a VR128, leaving upper bits alone.
2132 // Three operand (but two address) aliases.
2133 let isTwoAddress = 1 in {
2134 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2135 "movss {$src2, $dst|$dst, $src2}", []>;
2136 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2137 "movsd {$src2, $dst|$dst, $src2}", []>;
2139 let AddedComplexity = 20 in {
2140 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2141 "movss {$src2, $dst|$dst, $src2}",
2143 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2144 MOVL_shuffle_mask)))]>;
2145 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2146 "movsd {$src2, $dst|$dst, $src2}",
2148 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2149 MOVL_shuffle_mask)))]>;
2153 // Store / copy lower 64-bits of a XMM register.
2154 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2155 "movq {$src, $dst|$dst, $src}",
2156 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2158 // Move to lower bits of a VR128 and zeroing upper bits.
2159 // Loading from memory automatically zeroing upper bits.
2160 let AddedComplexity = 20 in {
2161 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2162 "movss {$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
2164 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
2165 MOVL_shuffle_mask)))]>;
2166 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2167 "movsd {$src, $dst|$dst, $src}",
2168 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
2169 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2170 MOVL_shuffle_mask)))]>;
2171 // movd / movq to XMM register zero-extends
2172 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2173 "movd {$src, $dst|$dst, $src}",
2174 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
2175 (v4i32 (scalar_to_vector GR32:$src)),
2176 MOVL_shuffle_mask)))]>;
2177 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2178 "movd {$src, $dst|$dst, $src}",
2179 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
2180 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2181 MOVL_shuffle_mask)))]>;
2182 // Moving from XMM to XMM but still clear upper 64 bits.
2183 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2184 "movq {$src, $dst|$dst, $src}",
2185 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2186 XS, Requires<[HasSSE2]>;
2187 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2188 "movq {$src, $dst|$dst, $src}",
2189 [(set VR128:$dst, (int_x86_sse2_movl_dq
2190 (bc_v4i32 (loadv2i64 addr:$src))))]>,
2191 XS, Requires<[HasSSE2]>;
2194 //===----------------------------------------------------------------------===//
2195 // Non-Instruction Patterns
2196 //===----------------------------------------------------------------------===//
2198 // 128-bit vector undef's.
2199 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2200 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2201 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2202 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2203 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2205 // 128-bit vector all zero's.
2206 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2207 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2208 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2209 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2210 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2212 // 128-bit vector all one's.
2213 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2214 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2215 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2216 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2217 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2219 // Store 128-bit integer vector values.
2220 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2221 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2222 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2223 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2224 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2225 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2227 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2229 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2230 Requires<[HasSSE2]>;
2231 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2232 Requires<[HasSSE2]>;
2235 let Predicates = [HasSSE2] in {
2236 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2237 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2238 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2239 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2240 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2241 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2242 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2243 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2244 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2245 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2246 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2247 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2248 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2249 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2250 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2251 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2252 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2253 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2254 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2255 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2256 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2257 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2258 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2259 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2260 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2261 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2262 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2263 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2264 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2265 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2268 // Move scalar to XMM zero-extended
2269 // movd to XMM register zero-extends
2270 let AddedComplexity = 20 in {
2271 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2272 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2273 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2274 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2275 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2276 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2277 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2278 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2279 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2280 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2281 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2282 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2283 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2286 // Splat v2f64 / v2i64
2287 let AddedComplexity = 10 in {
2288 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2289 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2290 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2291 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2295 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2296 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2297 Requires<[HasSSE1]>;
2299 // Special unary SHUFPSrri case.
2300 // FIXME: when we want non two-address code, then we should use PSHUFD?
2301 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2302 SHUFP_unary_shuffle_mask:$sm),
2303 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2304 Requires<[HasSSE1]>;
2305 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2306 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2307 SHUFP_unary_shuffle_mask:$sm),
2308 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2309 Requires<[HasSSE2]>;
2310 // Special binary v4i32 shuffle cases with SHUFPS.
2311 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2312 PSHUFD_binary_shuffle_mask:$sm),
2313 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2314 Requires<[HasSSE2]>;
2315 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2316 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2317 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2318 Requires<[HasSSE2]>;
2320 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2321 let AddedComplexity = 10 in {
2322 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2323 UNPCKL_v_undef_shuffle_mask)),
2324 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2325 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2326 UNPCKL_v_undef_shuffle_mask)),
2327 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2328 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2329 UNPCKL_v_undef_shuffle_mask)),
2330 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2331 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2332 UNPCKL_v_undef_shuffle_mask)),
2333 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2336 let AddedComplexity = 20 in {
2337 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2338 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2339 MOVSHDUP_shuffle_mask)),
2340 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2341 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2342 MOVSHDUP_shuffle_mask)),
2343 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2345 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2346 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2347 MOVSLDUP_shuffle_mask)),
2348 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2349 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2350 MOVSLDUP_shuffle_mask)),
2351 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2354 let AddedComplexity = 20 in {
2355 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2356 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2357 MOVHP_shuffle_mask)),
2358 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2360 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2361 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2362 MOVHLPS_shuffle_mask)),
2363 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2365 // vector_shuffle v1, undef <2, 3, ?, ?> using MOVHLPS
2366 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2367 UNPCKH_shuffle_mask)),
2368 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2369 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2370 UNPCKH_shuffle_mask)),
2371 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2373 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2374 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2375 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2376 MOVLP_shuffle_mask)),
2377 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2378 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2379 MOVLP_shuffle_mask)),
2380 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2381 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2382 MOVHP_shuffle_mask)),
2383 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2384 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2385 MOVHP_shuffle_mask)),
2386 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2388 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2389 MOVLP_shuffle_mask)),
2390 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2391 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2392 MOVLP_shuffle_mask)),
2393 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2394 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2395 MOVHP_shuffle_mask)),
2396 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2397 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2398 MOVLP_shuffle_mask)),
2399 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2401 // Setting the lowest element in the vector.
2402 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2403 MOVL_shuffle_mask)),
2404 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2405 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2406 MOVL_shuffle_mask)),
2407 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2409 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2410 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2411 MOVLP_shuffle_mask)),
2412 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2413 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2414 MOVLP_shuffle_mask)),
2415 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2417 // Set lowest element and zero upper elements.
2418 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2419 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2420 MOVL_shuffle_mask)),
2421 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2424 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2425 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2426 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2427 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2428 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2429 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2430 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2431 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2432 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2433 Requires<[HasSSE2]>;
2434 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2435 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2436 Requires<[HasSSE2]>;
2437 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2438 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2439 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2440 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2441 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2442 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2443 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2444 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2445 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2446 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2447 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2448 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2449 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2450 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2451 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2452 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2454 // 128-bit logical shifts
2455 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2456 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2457 Requires<[HasSSE2]>;
2458 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2459 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2460 Requires<[HasSSE2]>;
2462 // Some special case pandn patterns.
2463 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2465 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2466 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2468 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2469 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2471 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2473 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2474 (load addr:$src2))),
2475 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2476 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2477 (load addr:$src2))),
2478 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2479 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2480 (load addr:$src2))),
2481 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2484 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2485 Requires<[HasSSE1]>;