1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand x86memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memopr, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand x86memop, PatFrag mem_frag,
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
447 //===----------------------------------------------------------------------===//
448 // SSE 1 & 2 - Move Instructions
449 //===----------------------------------------------------------------------===//
451 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
452 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
453 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
455 // Loading from memory automatically zeroing upper bits.
456 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
457 PatFrag mem_pat, string OpcodeStr> :
458 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
459 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
460 [(set RC:$dst, (mem_pat addr:$src))]>;
462 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
463 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
464 // is used instead. Register-to-register movss/movsd is not modeled as an
465 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
466 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
467 let isAsmParserOnly = 1 in {
468 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
469 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
470 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
471 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
473 let canFoldAsLoad = 1, isReMaterializable = 1 in {
474 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
476 let AddedComplexity = 20 in
477 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
481 let Constraints = "$src1 = $dst" in {
482 def MOVSSrr : sse12_move_rr<FR32, v4f32,
483 "movss\t{$src2, $dst|$dst, $src2}">, XS;
484 def MOVSDrr : sse12_move_rr<FR64, v2f64,
485 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
488 let canFoldAsLoad = 1, isReMaterializable = 1 in {
489 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
491 let AddedComplexity = 20 in
492 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
495 let AddedComplexity = 15 in {
496 // Extract the low 32-bit value from one vector and insert it into another.
497 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
498 (MOVSSrr (v4f32 VR128:$src1),
499 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
500 // Extract the low 64-bit value from one vector and insert it into another.
501 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
502 (MOVSDrr (v2f64 VR128:$src1),
503 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
506 // Implicitly promote a 32-bit scalar to a vector.
507 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
508 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
509 // Implicitly promote a 64-bit scalar to a vector.
510 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
511 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
513 let AddedComplexity = 20 in {
514 // MOVSSrm zeros the high parts of the register; represent this
515 // with SUBREG_TO_REG.
516 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
517 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
518 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
519 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
520 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
521 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
522 // MOVSDrm zeros the high parts of the register; represent this
523 // with SUBREG_TO_REG.
524 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
525 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
526 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
527 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
528 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
529 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
530 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
531 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
532 def : Pat<(v2f64 (X86vzload addr:$src)),
533 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
536 // Store scalar value to memory.
537 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
538 "movss\t{$src, $dst|$dst, $src}",
539 [(store FR32:$src, addr:$dst)]>;
540 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
541 "movsd\t{$src, $dst|$dst, $src}",
542 [(store FR64:$src, addr:$dst)]>;
544 let isAsmParserOnly = 1 in {
545 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
546 "movss\t{$src, $dst|$dst, $src}",
547 [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
548 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
549 "movsd\t{$src, $dst|$dst, $src}",
550 [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
553 // Extract and store.
554 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
557 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
558 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
561 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
563 // Move Aligned/Unaligned floating point values
564 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
565 X86MemOperand x86memop, PatFrag ld_frag,
566 string asm, Domain d,
567 bit IsReMaterializable = 1> {
568 let neverHasSideEffects = 1 in
569 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
570 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
571 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
572 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
573 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
574 [(set RC:$dst, (ld_frag addr:$src))], d>;
577 let isAsmParserOnly = 1 in {
578 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
579 "movaps", SSEPackedSingle>, VEX;
580 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
581 "movapd", SSEPackedDouble>, OpSize, VEX;
582 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
583 "movups", SSEPackedSingle>, VEX;
584 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
585 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
587 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
588 "movaps", SSEPackedSingle>, TB;
589 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
590 "movapd", SSEPackedDouble>, TB, OpSize;
591 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
592 "movups", SSEPackedSingle>, TB;
593 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
594 "movupd", SSEPackedDouble, 0>, TB, OpSize;
596 let isAsmParserOnly = 1 in {
597 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
600 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
601 "movapd\t{$src, $dst|$dst, $src}",
602 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
603 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
604 "movups\t{$src, $dst|$dst, $src}",
605 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
606 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
607 "movupd\t{$src, $dst|$dst, $src}",
608 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
610 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
611 "movaps\t{$src, $dst|$dst, $src}",
612 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
613 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
614 "movapd\t{$src, $dst|$dst, $src}",
615 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
616 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
617 "movups\t{$src, $dst|$dst, $src}",
618 [(store (v4f32 VR128:$src), addr:$dst)]>;
619 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
620 "movupd\t{$src, $dst|$dst, $src}",
621 [(store (v2f64 VR128:$src), addr:$dst)]>;
623 // Intrinsic forms of MOVUPS/D load and store
624 let isAsmParserOnly = 1 in {
625 let canFoldAsLoad = 1, isReMaterializable = 1 in
626 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
628 "movups\t{$src, $dst|$dst, $src}",
629 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
630 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
632 "movupd\t{$src, $dst|$dst, $src}",
633 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
634 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
635 (ins f128mem:$dst, VR128:$src),
636 "movups\t{$src, $dst|$dst, $src}",
637 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
638 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
639 (ins f128mem:$dst, VR128:$src),
640 "movupd\t{$src, $dst|$dst, $src}",
641 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
643 let canFoldAsLoad = 1, isReMaterializable = 1 in
644 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
645 "movups\t{$src, $dst|$dst, $src}",
646 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
647 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
648 "movupd\t{$src, $dst|$dst, $src}",
649 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
651 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
652 "movups\t{$src, $dst|$dst, $src}",
653 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
654 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
655 "movupd\t{$src, $dst|$dst, $src}",
656 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
658 // Move Low/High packed floating point values
659 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
660 PatFrag mov_frag, string base_opc,
662 def PSrm : PI<opc, MRMSrcMem,
663 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
664 !strconcat(!strconcat(base_opc,"s"), asm_opr),
667 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
668 SSEPackedSingle>, TB;
670 def PDrm : PI<opc, MRMSrcMem,
671 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
672 !strconcat(!strconcat(base_opc,"d"), asm_opr),
673 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
674 (scalar_to_vector (loadf64 addr:$src2)))))],
675 SSEPackedDouble>, TB, OpSize;
678 let isAsmParserOnly = 1, AddedComplexity = 20 in {
679 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
681 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
682 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
684 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
685 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
686 "\t{$src2, $dst|$dst, $src2}">;
687 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
688 "\t{$src2, $dst|$dst, $src2}">;
691 let isAsmParserOnly = 1 in {
692 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
693 "movlps\t{$src, $dst|$dst, $src}",
694 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
695 (iPTR 0))), addr:$dst)]>, VEX;
696 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
697 "movlpd\t{$src, $dst|$dst, $src}",
698 [(store (f64 (vector_extract (v2f64 VR128:$src),
699 (iPTR 0))), addr:$dst)]>, VEX;
701 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
702 "movlps\t{$src, $dst|$dst, $src}",
703 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
704 (iPTR 0))), addr:$dst)]>;
705 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
706 "movlpd\t{$src, $dst|$dst, $src}",
707 [(store (f64 (vector_extract (v2f64 VR128:$src),
708 (iPTR 0))), addr:$dst)]>;
710 // v2f64 extract element 1 is always custom lowered to unpack high to low
711 // and extract element 0 so the non-store version isn't too horrible.
712 let isAsmParserOnly = 1 in {
713 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
714 "movhps\t{$src, $dst|$dst, $src}",
715 [(store (f64 (vector_extract
716 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
717 (undef)), (iPTR 0))), addr:$dst)]>,
719 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
720 "movhpd\t{$src, $dst|$dst, $src}",
721 [(store (f64 (vector_extract
722 (v2f64 (unpckh VR128:$src, (undef))),
723 (iPTR 0))), addr:$dst)]>,
726 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
727 "movhps\t{$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract
729 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
730 (undef)), (iPTR 0))), addr:$dst)]>;
731 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movhpd\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract
734 (v2f64 (unpckh VR128:$src, (undef))),
735 (iPTR 0))), addr:$dst)]>;
737 let isAsmParserOnly = 1, AddedComplexity = 20 in {
738 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
739 (ins VR128:$src1, VR128:$src2),
740 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
742 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
744 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
745 (ins VR128:$src1, VR128:$src2),
746 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
751 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
752 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
753 (ins VR128:$src1, VR128:$src2),
754 "movlhps\t{$src2, $dst|$dst, $src2}",
756 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
757 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
758 (ins VR128:$src1, VR128:$src2),
759 "movhlps\t{$src2, $dst|$dst, $src2}",
761 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
764 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
765 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
766 let AddedComplexity = 20 in {
767 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
768 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
769 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
770 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
773 //===----------------------------------------------------------------------===//
774 // SSE 1 & 2 - Conversion Instructions
775 //===----------------------------------------------------------------------===//
777 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
778 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
780 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
781 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
782 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
783 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
786 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
787 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
788 string asm, Domain d> {
789 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
790 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
791 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
792 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
795 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
796 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
798 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
800 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
801 (ins DstRC:$src1, x86memop:$src), asm, []>;
804 let isAsmParserOnly = 1 in {
805 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
806 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
807 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
808 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
809 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
810 "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
812 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
813 "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
817 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
818 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
819 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
820 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
821 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
822 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
823 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
824 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
826 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
827 // and/or XMM operand(s).
828 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
829 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
830 string asm, Domain d> {
831 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
832 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
833 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
834 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
837 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
838 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
840 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
841 [(set DstRC:$dst, (Int SrcRC:$src))]>;
842 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
843 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
846 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
847 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
848 PatFrag ld_frag, string asm, Domain d> {
849 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
850 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
851 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
852 (ins DstRC:$src1, x86memop:$src2), asm,
853 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
856 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
857 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
858 PatFrag ld_frag, string asm> {
859 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
860 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
861 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
862 (ins DstRC:$src1, x86memop:$src2), asm,
863 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
866 let isAsmParserOnly = 1 in {
867 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
868 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
870 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
871 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
874 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
875 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
876 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
877 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
880 let Constraints = "$src1 = $dst" in {
881 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
882 int_x86_sse_cvtsi2ss, i32mem, loadi32,
883 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
884 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
885 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
886 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
889 // Instructions below don't have an AVX form.
890 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
891 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
892 SSEPackedSingle>, TB;
893 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
894 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
895 SSEPackedDouble>, TB, OpSize;
896 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
897 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
898 SSEPackedSingle>, TB;
899 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
900 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
901 SSEPackedDouble>, TB, OpSize;
902 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
903 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
904 SSEPackedDouble>, TB, OpSize;
905 let Constraints = "$src1 = $dst" in {
906 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
907 int_x86_sse_cvtpi2ps,
908 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
909 SSEPackedSingle>, TB;
914 // Aliases for intrinsics
915 let isAsmParserOnly = 1, Pattern = []<dag> in {
916 defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
917 int_x86_sse_cvttss2si, f32mem, load,
918 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
919 defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
920 int_x86_sse2_cvttsd2si, f128mem, load,
921 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
923 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
924 f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
926 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
927 f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
930 let isAsmParserOnly = 1, Pattern = []<dag> in {
931 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
932 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
933 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
934 "cvtdq2ps\t{$src, $dst|$dst, $src}",
935 SSEPackedSingle>, TB, VEX;
937 let Pattern = []<dag> in {
938 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
939 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
940 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
941 "cvtdq2ps\t{$src, $dst|$dst, $src}",
942 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
947 // Convert scalar double to scalar single
948 let isAsmParserOnly = 1 in {
949 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
950 (ins FR64:$src1, FR64:$src2),
951 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
953 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
954 (ins FR64:$src1, f64mem:$src2),
955 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
956 []>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V;
958 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
959 "cvtsd2ss\t{$src, $dst|$dst, $src}",
960 [(set FR32:$dst, (fround FR64:$src))]>;
961 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
962 "cvtsd2ss\t{$src, $dst|$dst, $src}",
963 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
964 Requires<[HasSSE2, OptForSize]>;
966 let isAsmParserOnly = 1 in
967 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
968 int_x86_sse2_cvtsd2ss, f64mem, load,
969 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
971 let Constraints = "$src1 = $dst" in
972 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
973 int_x86_sse2_cvtsd2ss, f64mem, load,
974 "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
976 // Convert scalar single to scalar double
977 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
978 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
979 (ins FR32:$src1, FR32:$src2),
980 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
981 []>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V;
982 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
983 (ins FR32:$src1, f32mem:$src2),
984 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
985 []>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>;
987 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
988 "cvtss2sd\t{$src, $dst|$dst, $src}",
989 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
991 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
992 "cvtss2sd\t{$src, $dst|$dst, $src}",
993 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
994 Requires<[HasSSE2, OptForSize]>;
996 let isAsmParserOnly = 1 in {
997 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
998 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
999 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1000 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1001 VR128:$src2))]>, XS, VEX_4V,
1002 Requires<[HasAVX, HasSSE2]>;
1003 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1004 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1005 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1006 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1007 (load addr:$src2)))]>, XS, VEX_4V,
1008 Requires<[HasAVX, HasSSE2]>;
1010 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1011 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1012 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1013 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1014 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1015 VR128:$src2))]>, XS,
1016 Requires<[HasSSE2]>;
1017 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1018 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1019 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1021 (load addr:$src2)))]>, XS,
1022 Requires<[HasSSE2]>;
1025 def : Pat<(extloadf32 addr:$src),
1026 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1027 Requires<[HasSSE2, OptForSpeed]>;
1029 // Convert doubleword to packed single/double fp
1030 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1031 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1033 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1034 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1035 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1036 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1037 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1038 (bitconvert (memopv2i64 addr:$src))))]>,
1039 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1041 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1042 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1043 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1044 TB, Requires<[HasSSE2]>;
1045 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1046 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1047 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1048 (bitconvert (memopv2i64 addr:$src))))]>,
1049 TB, Requires<[HasSSE2]>;
1051 // FIXME: why the non-intrinsic version is described as SSE3?
1052 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
1053 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1054 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1056 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1057 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1058 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1059 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1060 (bitconvert (memopv2i64 addr:$src))))]>,
1061 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1063 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1064 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1065 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1066 XS, Requires<[HasSSE2]>;
1067 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1068 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1069 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1070 (bitconvert (memopv2i64 addr:$src))))]>,
1071 XS, Requires<[HasSSE2]>;
1073 // Convert packed single/double fp to doubleword
1074 let isAsmParserOnly = 1 in {
1075 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1076 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1077 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1078 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1080 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1081 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1082 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1083 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1085 let isAsmParserOnly = 1 in {
1086 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1087 "cvtps2dq\t{$src, $dst|$dst, $src}",
1088 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1090 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1092 "cvtps2dq\t{$src, $dst|$dst, $src}",
1093 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1094 (memop addr:$src)))]>, VEX;
1096 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1097 "cvtps2dq\t{$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1099 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1100 "cvtps2dq\t{$src, $dst|$dst, $src}",
1101 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1102 (memop addr:$src)))]>;
1104 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
1105 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1106 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1107 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1108 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1109 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1110 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1111 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1112 (memop addr:$src)))]>,
1113 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1115 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1116 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1118 XD, Requires<[HasSSE2]>;
1119 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1120 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1121 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1122 (memop addr:$src)))]>,
1123 XD, Requires<[HasSSE2]>;
1126 // Convert with truncation packed single/double fp to doubleword
1127 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
1128 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1129 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1130 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1131 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1133 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1134 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1135 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1136 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1139 let isAsmParserOnly = 1 in {
1140 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1141 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1143 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1144 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1145 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1146 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1147 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1148 (memop addr:$src)))]>,
1149 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1151 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1152 "cvttps2dq\t{$src, $dst|$dst, $src}",
1154 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1155 XS, Requires<[HasSSE2]>;
1156 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1157 "cvttps2dq\t{$src, $dst|$dst, $src}",
1158 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1159 (memop addr:$src)))]>,
1160 XS, Requires<[HasSSE2]>;
1162 let isAsmParserOnly = 1 in {
1163 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1165 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1166 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1168 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1170 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1171 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1172 (memop addr:$src)))]>, VEX;
1174 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1175 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1176 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1177 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1178 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1179 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1180 (memop addr:$src)))]>;
1182 // Convert packed single to packed double
1183 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1184 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1185 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1187 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1188 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1191 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1192 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1193 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1194 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1196 let isAsmParserOnly = 1 in {
1197 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1198 "cvtps2pd\t{$src, $dst|$dst, $src}",
1199 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1200 VEX, Requires<[HasAVX, HasSSE2]>;
1201 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1202 "cvtps2pd\t{$src, $dst|$dst, $src}",
1203 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1204 (load addr:$src)))]>,
1205 VEX, Requires<[HasAVX, HasSSE2]>;
1207 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1208 "cvtps2pd\t{$src, $dst|$dst, $src}",
1209 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1210 TB, Requires<[HasSSE2]>;
1211 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1212 "cvtps2pd\t{$src, $dst|$dst, $src}",
1213 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1214 (load addr:$src)))]>,
1215 TB, Requires<[HasSSE2]>;
1217 // Convert packed double to packed single
1218 let isAsmParserOnly = 1 in {
1219 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1220 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1221 // FIXME: the memory form of this instruction should described using
1222 // use extra asm syntax
1224 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1225 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1226 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1227 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1230 let isAsmParserOnly = 1 in {
1231 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1232 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1233 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1234 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1236 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1238 (memop addr:$src)))]>;
1240 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1241 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1242 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1243 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1244 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1245 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1246 (memop addr:$src)))]>;
1248 //===----------------------------------------------------------------------===//
1249 // SSE 1 & 2 - Compare Instructions
1250 //===----------------------------------------------------------------------===//
1252 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1253 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1254 string asm, string asm_alt> {
1255 def rr : SIi8<0xC2, MRMSrcReg,
1256 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1259 def rm : SIi8<0xC2, MRMSrcMem,
1260 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1262 // Accept explicit immediate argument form instead of comparison code.
1263 let isAsmParserOnly = 1 in {
1264 def rr_alt : SIi8<0xC2, MRMSrcReg,
1265 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1268 def rm_alt : SIi8<0xC2, MRMSrcMem,
1269 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1274 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1275 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1276 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1277 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1279 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1280 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1281 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1285 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1286 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1287 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1288 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1289 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1290 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1291 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1294 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1295 Intrinsic Int, string asm> {
1296 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1297 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1298 [(set VR128:$dst, (Int VR128:$src1,
1299 VR128:$src, imm:$cc))]>;
1300 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1301 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1302 [(set VR128:$dst, (Int VR128:$src1,
1303 (load addr:$src), imm:$cc))]>;
1306 // Aliases to match intrinsics which expect XMM operand(s).
1307 let isAsmParserOnly = 1 in {
1308 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1309 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1311 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1312 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1315 let Constraints = "$src1 = $dst" in {
1316 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1317 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1318 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1319 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1323 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1324 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1325 ValueType vt, X86MemOperand x86memop,
1326 PatFrag ld_frag, string OpcodeStr, Domain d> {
1327 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1328 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1329 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1330 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1332 [(set EFLAGS, (OpNode (vt RC:$src1),
1333 (ld_frag addr:$src2)))], d>;
1336 let Defs = [EFLAGS] in {
1337 let isAsmParserOnly = 1 in {
1338 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1339 "ucomiss", SSEPackedSingle>, VEX;
1340 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1341 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1342 let Pattern = []<dag> in {
1343 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1344 "comiss", SSEPackedSingle>, VEX;
1345 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1346 "comisd", SSEPackedDouble>, OpSize, VEX;
1349 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1350 load, "ucomiss", SSEPackedSingle>, VEX;
1351 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1352 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1354 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1355 load, "comiss", SSEPackedSingle>, VEX;
1356 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1357 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1359 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1360 "ucomiss", SSEPackedSingle>, TB;
1361 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1362 "ucomisd", SSEPackedDouble>, TB, OpSize;
1364 let Pattern = []<dag> in {
1365 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1366 "comiss", SSEPackedSingle>, TB;
1367 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1368 "comisd", SSEPackedDouble>, TB, OpSize;
1371 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1372 load, "ucomiss", SSEPackedSingle>, TB;
1373 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1374 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1376 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1377 "comiss", SSEPackedSingle>, TB;
1378 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1379 "comisd", SSEPackedDouble>, TB, OpSize;
1380 } // Defs = [EFLAGS]
1382 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1383 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1384 Intrinsic Int, string asm, string asm_alt,
1386 def rri : PIi8<0xC2, MRMSrcReg,
1387 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1388 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1389 def rmi : PIi8<0xC2, MRMSrcMem,
1390 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1391 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1392 // Accept explicit immediate argument form instead of comparison code.
1393 let isAsmParserOnly = 1 in {
1394 def rri_alt : PIi8<0xC2, MRMSrcReg,
1395 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1397 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1398 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1403 let isAsmParserOnly = 1 in {
1404 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1405 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1406 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1407 SSEPackedSingle>, VEX_4V;
1408 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1409 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1410 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1411 SSEPackedDouble>, OpSize, VEX_4V;
1413 let Constraints = "$src1 = $dst" in {
1414 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1415 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1416 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1417 SSEPackedSingle>, TB;
1418 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1419 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1420 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1421 SSEPackedDouble>, TB, OpSize;
1424 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1425 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1426 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1427 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1428 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1429 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1430 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1431 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1433 //===----------------------------------------------------------------------===//
1434 // SSE 1 & 2 - Shuffle Instructions
1435 //===----------------------------------------------------------------------===//
1437 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1438 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1439 ValueType vt, string asm, PatFrag mem_frag,
1440 Domain d, bit IsConvertibleToThreeAddress = 0> {
1441 def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
1442 (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
1443 [(set VR128:$dst, (vt (shufp:$src3
1444 VR128:$src1, (mem_frag addr:$src2))))], d>;
1445 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1446 def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
1447 (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
1449 (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
1452 let isAsmParserOnly = 1 in {
1453 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1454 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1455 memopv4f32, SSEPackedSingle>, VEX_4V;
1456 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1457 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1458 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1461 let Constraints = "$src1 = $dst" in {
1462 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1463 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1464 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1466 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1467 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1468 memopv2f64, SSEPackedDouble>, TB, OpSize;
1471 //===----------------------------------------------------------------------===//
1472 // SSE 1 & 2 - Unpack Instructions
1473 //===----------------------------------------------------------------------===//
1475 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1476 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1477 PatFrag mem_frag, RegisterClass RC,
1478 X86MemOperand x86memop, string asm,
1480 def rr : PI<opc, MRMSrcReg,
1481 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1483 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1484 def rm : PI<opc, MRMSrcMem,
1485 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1487 (vt (OpNode RC:$src1,
1488 (mem_frag addr:$src2))))], d>;
1491 let AddedComplexity = 10 in {
1492 let isAsmParserOnly = 1 in {
1493 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1494 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1495 SSEPackedSingle>, VEX_4V;
1496 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1497 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1498 SSEPackedDouble>, OpSize, VEX_4V;
1499 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1500 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1501 SSEPackedSingle>, VEX_4V;
1502 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1503 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1504 SSEPackedDouble>, OpSize, VEX_4V;
1507 let Constraints = "$src1 = $dst" in {
1508 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1509 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1510 SSEPackedSingle>, TB;
1511 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1512 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1513 SSEPackedDouble>, TB, OpSize;
1514 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1515 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1516 SSEPackedSingle>, TB;
1517 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1518 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1519 SSEPackedDouble>, TB, OpSize;
1520 } // Constraints = "$src1 = $dst"
1521 } // AddedComplexity
1523 //===----------------------------------------------------------------------===//
1524 // SSE 1 & 2 - Extract Floating-Point Sign mask
1525 //===----------------------------------------------------------------------===//
1527 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1528 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1530 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1531 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1532 [(set GR32:$dst, (Int RC:$src))], d>;
1536 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1537 SSEPackedSingle>, TB;
1538 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1539 SSEPackedDouble>, TB, OpSize;
1541 let isAsmParserOnly = 1 in {
1542 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1543 "movmskps", SSEPackedSingle>, VEX;
1544 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1545 "movmskpd", SSEPackedDouble>, OpSize,
1549 //===----------------------------------------------------------------------===//
1550 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1551 //===----------------------------------------------------------------------===//
1553 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1554 // names that start with 'Fs'.
1556 // Alias instructions that map fld0 to pxor for sse.
1557 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1558 canFoldAsLoad = 1 in {
1559 // FIXME: Set encoding to pseudo!
1560 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1561 [(set FR32:$dst, fp32imm0)]>,
1562 Requires<[HasSSE1]>, TB, OpSize;
1563 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1564 [(set FR64:$dst, fpimm0)]>,
1565 Requires<[HasSSE2]>, TB, OpSize;
1568 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1569 // bits are disregarded.
1570 let neverHasSideEffects = 1 in {
1571 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1572 "movaps\t{$src, $dst|$dst, $src}", []>;
1573 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1574 "movapd\t{$src, $dst|$dst, $src}", []>;
1577 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1578 // bits are disregarded.
1579 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1580 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1581 "movaps\t{$src, $dst|$dst, $src}",
1582 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1583 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1584 "movapd\t{$src, $dst|$dst, $src}",
1585 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1588 //===----------------------------------------------------------------------===//
1589 // SSE 1 & 2 - Logical Instructions
1590 //===----------------------------------------------------------------------===//
1592 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1594 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1595 SDNode OpNode, bit MayLoad = 0> {
1596 let isAsmParserOnly = 1 in {
1597 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1598 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
1599 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
1601 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1602 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
1603 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
1607 let Constraints = "$src1 = $dst" in {
1608 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1609 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
1610 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
1612 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1613 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
1614 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
1618 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1619 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1620 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1621 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1623 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1624 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
1626 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1628 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1629 SDNode OpNode, int HasPat = 0,
1630 list<list<dag>> Pattern = []> {
1631 let isAsmParserOnly = 1 in {
1632 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1633 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1635 !if(HasPat, Pattern[0], // rr
1636 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1638 !if(HasPat, Pattern[2], // rm
1639 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1640 (memopv2i64 addr:$src2)))])>,
1643 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1644 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1646 !if(HasPat, Pattern[1], // rr
1647 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1650 !if(HasPat, Pattern[3], // rm
1651 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1652 (memopv2i64 addr:$src2)))])>,
1655 let Constraints = "$src1 = $dst" in {
1656 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1657 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
1658 !if(HasPat, Pattern[0], // rr
1659 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1661 !if(HasPat, Pattern[2], // rm
1662 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1663 (memopv2i64 addr:$src2)))])>, TB;
1665 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1666 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
1667 !if(HasPat, Pattern[1], // rr
1668 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1671 !if(HasPat, Pattern[3], // rm
1672 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1673 (memopv2i64 addr:$src2)))])>,
1678 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1679 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1680 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1681 let isCommutable = 0 in
1682 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1684 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1685 (bc_v2i64 (v4i32 immAllOnesV))),
1688 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1689 (bc_v2i64 (v2f64 VR128:$src2))))],
1691 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1692 (bc_v2i64 (v4i32 immAllOnesV))),
1693 (memopv2i64 addr:$src2))))],
1695 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1696 (memopv2i64 addr:$src2)))]]>;
1698 //===----------------------------------------------------------------------===//
1699 // SSE 1 & 2 - Arithmetic Instructions
1700 //===----------------------------------------------------------------------===//
1702 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
1705 /// In addition, we also have a special variant of the scalar form here to
1706 /// represent the associated intrinsic operation. This form is unlike the
1707 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1708 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1710 /// These three forms can each be reg+reg or reg+mem.
1712 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1715 let isAsmParserOnly = 1 in {
1716 defm V#NAME#SS : sse12_fp_scalar<opc,
1717 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1718 OpNode, FR32, f32mem>, XS, VEX_4V;
1720 defm V#NAME#SD : sse12_fp_scalar<opc,
1721 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1722 OpNode, FR64, f64mem>, XD, VEX_4V;
1724 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1725 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1726 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1729 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1730 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1731 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1734 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1735 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1736 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1738 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1739 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1740 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1743 let Constraints = "$src1 = $dst" in {
1744 defm SS : sse12_fp_scalar<opc,
1745 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1746 OpNode, FR32, f32mem>, XS;
1748 defm SD : sse12_fp_scalar<opc,
1749 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1750 OpNode, FR64, f64mem>, XD;
1752 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1753 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1754 f128mem, memopv4f32, SSEPackedSingle>, TB;
1756 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1757 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1758 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1760 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1761 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1762 "", "_ss", ssmem, sse_load_f32>, XS;
1764 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1765 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1766 "2", "_sd", sdmem, sse_load_f64>, XD;
1770 // Arithmetic instructions
1771 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
1772 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
1774 let isCommutable = 0 in {
1775 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
1776 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
1779 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
1781 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
1782 /// instructions for a full-vector intrinsic form. Operations that map
1783 /// onto C operators don't use this form since they just use the plain
1784 /// vector form instead of having a separate vector intrinsic form.
1786 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1789 let isAsmParserOnly = 1 in {
1790 // Scalar operation, reg+reg.
1791 defm V#NAME#SS : sse12_fp_scalar<opc,
1792 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1793 OpNode, FR32, f32mem>, XS, VEX_4V;
1795 defm V#NAME#SD : sse12_fp_scalar<opc,
1796 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1797 OpNode, FR64, f64mem>, XD, VEX_4V;
1799 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1800 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1801 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1804 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1805 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1806 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1809 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1810 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1813 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1814 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1815 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1817 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1818 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1819 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
1821 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1822 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1823 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
1827 let Constraints = "$src1 = $dst" in {
1828 // Scalar operation, reg+reg.
1829 defm SS : sse12_fp_scalar<opc,
1830 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1831 OpNode, FR32, f32mem>, XS;
1832 defm SD : sse12_fp_scalar<opc,
1833 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1834 OpNode, FR64, f64mem>, XD;
1835 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1836 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1837 f128mem, memopv4f32, SSEPackedSingle>, TB;
1839 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1840 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1841 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1843 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1844 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1845 "", "_ss", ssmem, sse_load_f32>, XS;
1847 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1848 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1849 "2", "_sd", sdmem, sse_load_f64>, XD;
1851 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1852 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1853 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
1855 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1856 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1857 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1861 let isCommutable = 0 in {
1862 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
1863 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
1867 /// In addition, we also have a special variant of the scalar form here to
1868 /// represent the associated intrinsic operation. This form is unlike the
1869 /// plain scalar form, in that it takes an entire vector (instead of a
1870 /// scalar) and leaves the top elements undefined.
1872 /// And, we have a special variant form for a full-vector intrinsic form.
1874 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1875 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1876 SDNode OpNode, Intrinsic F32Int> {
1877 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1878 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1879 [(set FR32:$dst, (OpNode FR32:$src))]>;
1880 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1881 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1882 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1883 Requires<[HasSSE1, OptForSize]>;
1884 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (F32Int VR128:$src))]>;
1887 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1888 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1889 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1892 /// sse1_fp_unop_p - SSE1 unops in scalar form.
1893 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
1894 SDNode OpNode, Intrinsic V4F32Int> {
1895 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1896 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1897 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1898 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1900 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1901 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1902 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1903 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1904 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1905 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1906 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1909 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1910 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1911 SDNode OpNode, Intrinsic F32Int> {
1912 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1913 !strconcat(!strconcat("v", OpcodeStr),
1914 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1915 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1916 !strconcat(!strconcat("v", OpcodeStr),
1917 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1918 []>, XS, Requires<[HasAVX, HasSSE1, OptForSize]>;
1919 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
1920 (ins VR128:$src1, VR128:$src2),
1921 !strconcat(!strconcat("v", OpcodeStr),
1922 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1923 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1924 (ins VR128:$src1, ssmem:$src2),
1925 !strconcat(!strconcat("v", OpcodeStr),
1926 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1929 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1930 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1931 SDNode OpNode, Intrinsic F64Int> {
1932 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1933 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1934 [(set FR64:$dst, (OpNode FR64:$src))]>;
1935 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1936 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1937 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1938 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1940 [(set VR128:$dst, (F64Int VR128:$src))]>;
1941 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1942 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1943 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1946 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1947 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1948 SDNode OpNode, Intrinsic V2F64Int> {
1949 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1951 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1952 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1953 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1954 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1955 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1956 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1957 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1958 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1960 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1963 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1964 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1965 SDNode OpNode, Intrinsic F64Int> {
1966 def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1967 !strconcat(OpcodeStr,
1968 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1969 def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
1970 (ins FR64:$src1, f64mem:$src2),
1971 !strconcat(OpcodeStr,
1972 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1973 def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
1974 (ins VR128:$src1, VR128:$src2),
1975 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1977 def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
1978 (ins VR128:$src1, sdmem:$src2),
1979 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1983 let isAsmParserOnly = 1 in {
1985 let Predicates = [HasAVX, HasSSE2] in {
1986 defm VSQRT : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1989 defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX;
1992 let Predicates = [HasAVX, HasSSE1] in {
1993 defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1995 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX;
1996 // Reciprocal approximations. Note that these typically require refinement
1997 // in order to obtain suitable precision.
1998 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
1999 int_x86_sse_rsqrt_ss>, VEX_4V;
2000 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>,
2002 defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2004 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>,
2010 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2011 sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>,
2012 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2013 sse2_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_pd>;
2015 // Reciprocal approximations. Note that these typically require refinement
2016 // in order to obtain suitable precision.
2017 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2018 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>;
2019 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2020 sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
2022 // There is no f64 version of the reciprocal approximation instructions.
2024 //===----------------------------------------------------------------------===//
2025 // SSE 1 & 2 - Non-temporal stores
2026 //===----------------------------------------------------------------------===//
2028 let isAsmParserOnly = 1 in {
2029 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
2030 (ins i128mem:$dst, VR128:$src),
2031 "movntps\t{$src, $dst|$dst, $src}",
2032 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2033 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2034 (ins i128mem:$dst, VR128:$src),
2035 "movntpd\t{$src, $dst|$dst, $src}",
2036 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2038 let ExeDomain = SSEPackedInt in
2039 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2040 (ins f128mem:$dst, VR128:$src),
2041 "movntdq\t{$src, $dst|$dst, $src}",
2042 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2044 let AddedComplexity = 400 in { // Prefer non-temporal versions
2045 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2046 (ins f128mem:$dst, VR128:$src),
2047 "movntps\t{$src, $dst|$dst, $src}",
2048 [(alignednontemporalstore (v4f32 VR128:$src),
2050 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2051 (ins f128mem:$dst, VR128:$src),
2052 "movntpd\t{$src, $dst|$dst, $src}",
2053 [(alignednontemporalstore (v2f64 VR128:$src),
2055 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2056 (ins f128mem:$dst, VR128:$src),
2057 "movntdq\t{$src, $dst|$dst, $src}",
2058 [(alignednontemporalstore (v2f64 VR128:$src),
2060 let ExeDomain = SSEPackedInt in
2061 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2062 (ins f128mem:$dst, VR128:$src),
2063 "movntdq\t{$src, $dst|$dst, $src}",
2064 [(alignednontemporalstore (v4f32 VR128:$src),
2069 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2070 "movntps\t{$src, $dst|$dst, $src}",
2071 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2072 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2073 "movntpd\t{$src, $dst|$dst, $src}",
2074 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2076 let ExeDomain = SSEPackedInt in
2077 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2078 "movntdq\t{$src, $dst|$dst, $src}",
2079 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2081 let AddedComplexity = 400 in { // Prefer non-temporal versions
2082 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2083 "movntps\t{$src, $dst|$dst, $src}",
2084 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2085 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2086 "movntpd\t{$src, $dst|$dst, $src}",
2087 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2090 "movntdq\t{$src, $dst|$dst, $src}",
2091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2093 let ExeDomain = SSEPackedInt in
2094 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2095 "movntdq\t{$src, $dst|$dst, $src}",
2096 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2098 // There is no AVX form for instructions below this point
2099 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2100 "movnti\t{$src, $dst|$dst, $src}",
2101 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2102 TB, Requires<[HasSSE2]>;
2104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2105 "movnti\t{$src, $dst|$dst, $src}",
2106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2107 TB, Requires<[HasSSE2]>;
2110 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2111 "movnti\t{$src, $dst|$dst, $src}",
2112 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2113 TB, Requires<[HasSSE2]>;
2115 //===----------------------------------------------------------------------===//
2116 // SSE 1 & 2 - Misc Instructions (No AVX form)
2117 //===----------------------------------------------------------------------===//
2119 // Prefetch intrinsic.
2120 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2121 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2122 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2123 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2124 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2125 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2126 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2127 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2129 // Load, store, and memory fence
2130 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2131 TB, Requires<[HasSSE1]>;
2133 // Alias instructions that map zero vector to pxor / xorp* for sse.
2134 // We set canFoldAsLoad because this can be converted to a constant-pool
2135 // load of an all-zeros value if folding it would be beneficial.
2136 // FIXME: Change encoding to pseudo!
2137 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2138 isCodeGenOnly = 1 in {
2139 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2140 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2141 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2142 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2143 let ExeDomain = SSEPackedInt in
2144 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2145 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2148 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2149 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2150 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2152 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2153 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE 1 & 2 - Load/Store XCSR register
2157 //===----------------------------------------------------------------------===//
2159 let isAsmParserOnly = 1 in {
2160 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2161 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2162 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2163 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2166 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2167 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2168 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2169 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2171 //===---------------------------------------------------------------------===//
2172 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2173 //===---------------------------------------------------------------------===//
2174 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2176 let isAsmParserOnly = 1 in {
2177 let neverHasSideEffects = 1 in
2178 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2179 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2180 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2181 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2183 let canFoldAsLoad = 1, mayLoad = 1 in {
2184 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2185 "movdqa\t{$src, $dst|$dst, $src}",
2186 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
2188 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2189 "vmovdqu\t{$src, $dst|$dst, $src}",
2190 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2191 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2194 let mayStore = 1 in {
2195 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2196 (ins i128mem:$dst, VR128:$src),
2197 "movdqa\t{$src, $dst|$dst, $src}",
2198 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
2199 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2200 "vmovdqu\t{$src, $dst|$dst, $src}",
2201 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2202 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2206 let neverHasSideEffects = 1 in
2207 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2208 "movdqa\t{$src, $dst|$dst, $src}", []>;
2210 let canFoldAsLoad = 1, mayLoad = 1 in {
2211 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2212 "movdqa\t{$src, $dst|$dst, $src}",
2213 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2214 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2215 "movdqu\t{$src, $dst|$dst, $src}",
2216 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2217 XS, Requires<[HasSSE2]>;
2220 let mayStore = 1 in {
2221 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2222 "movdqa\t{$src, $dst|$dst, $src}",
2223 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2224 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2225 "movdqu\t{$src, $dst|$dst, $src}",
2226 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2227 XS, Requires<[HasSSE2]>;
2230 // Intrinsic forms of MOVDQU load and store
2231 let isAsmParserOnly = 1 in {
2232 let canFoldAsLoad = 1 in
2233 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2234 "vmovdqu\t{$src, $dst|$dst, $src}",
2235 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2236 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2237 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2238 "vmovdqu\t{$src, $dst|$dst, $src}",
2239 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2240 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2243 let canFoldAsLoad = 1 in
2244 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2245 "movdqu\t{$src, $dst|$dst, $src}",
2246 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2247 XS, Requires<[HasSSE2]>;
2248 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2249 "movdqu\t{$src, $dst|$dst, $src}",
2250 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2251 XS, Requires<[HasSSE2]>;
2253 } // ExeDomain = SSEPackedInt
2255 //===---------------------------------------------------------------------===//
2256 // SSE2 - Packed Integer Arithmetic Instructions
2257 //===---------------------------------------------------------------------===//
2259 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2261 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2263 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2264 (ins VR128:$src1, VR128:$src2),
2266 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2267 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2268 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2269 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2270 (ins VR128:$src1, i128mem:$src2),
2272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2273 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2274 [(set VR128:$dst, (IntId VR128:$src1,
2275 (bitconvert (memopv2i64 addr:$src2))))]>;
2278 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2279 string OpcodeStr, Intrinsic IntId,
2280 Intrinsic IntId2, bit Is2Addr = 1> {
2281 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2282 (ins VR128:$src1, VR128:$src2),
2284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2285 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2286 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2287 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2288 (ins VR128:$src1, i128mem:$src2),
2290 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2292 [(set VR128:$dst, (IntId VR128:$src1,
2293 (bitconvert (memopv2i64 addr:$src2))))]>;
2294 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2295 (ins VR128:$src1, i32i8imm:$src2),
2297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2299 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2302 /// PDI_binop_rm - Simple SSE2 binary operator.
2303 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2304 ValueType OpVT, bit Is2Addr = 1> {
2305 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2306 (ins VR128:$src1, VR128:$src2),
2308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2310 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2311 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2312 (ins VR128:$src1, i128mem:$src2),
2314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2316 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2317 (bitconvert (memopv2i64 addr:$src2)))))]>;
2320 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2322 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2323 /// to collapse (bitconvert VT to VT) into its operand.
2325 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2327 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src2),
2330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2332 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2333 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, i128mem:$src2),
2336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2338 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2341 } // ExeDomain = SSEPackedInt
2343 // 128-bit Integer Arithmetic
2345 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2346 let isCommutable = 1 in {
2347 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 0 /* 3 addr */>, VEX_4V;
2348 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 0>, VEX_4V;
2349 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 0>, VEX_4V;
2350 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 0>, VEX_4V;
2351 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 0>, VEX_4V;
2353 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0>, VEX_4V;
2354 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0>, VEX_4V;
2355 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0>, VEX_4V;
2356 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
2359 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0>,
2361 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0>,
2363 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0>,
2365 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0>,
2367 let isCommutable = 1 in {
2368 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 0>,
2370 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 0>,
2372 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 0>,
2374 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 0>,
2376 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 0>,
2378 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 0>,
2380 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 0>,
2382 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 0>,
2384 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 0>,
2386 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 0>,
2388 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 0>,
2390 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 0>,
2392 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 0>,
2394 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 0>,
2396 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 0>,
2401 let Constraints = "$src1 = $dst" in {
2402 let isCommutable = 1 in {
2403 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8>;
2404 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16>;
2405 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32>;
2406 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add>;
2407 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16>;
2409 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2410 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2411 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2412 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2415 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2416 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2417 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2418 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2419 let isCommutable = 1 in {
2420 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b>;
2421 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w>;
2422 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b>;
2423 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w>;
2424 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w>;
2425 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w>;
2426 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq>;
2427 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd>;
2428 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b>;
2429 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w>;
2430 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b>;
2431 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w>;
2432 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b>;
2433 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w>;
2434 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw>;
2437 } // Constraints = "$src1 = $dst"
2439 //===---------------------------------------------------------------------===//
2440 // SSE2 - Packed Integer Logical Instructions
2441 //===---------------------------------------------------------------------===//
2443 let Constraints = "$src1 = $dst" in {
2444 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2445 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2446 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2447 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2448 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2449 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2451 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2452 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2453 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2454 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2455 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2456 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2458 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2459 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2460 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2461 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2463 let isCommutable = 1 in {
2464 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and>;
2465 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or>;
2466 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor>;
2469 let ExeDomain = SSEPackedInt in {
2470 let neverHasSideEffects = 1 in {
2471 // 128-bit logical shifts.
2472 def PSLLDQri : PDIi8<0x73, MRM7r,
2473 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2474 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2475 def PSRLDQri : PDIi8<0x73, MRM3r,
2476 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2477 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2478 // PSRADQri doesn't exist in SSE[1-3].
2480 def PANDNrr : PDI<0xDF, MRMSrcReg,
2481 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2482 "pandn\t{$src2, $dst|$dst, $src2}",
2483 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2486 def PANDNrm : PDI<0xDF, MRMSrcMem,
2487 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2488 "pandn\t{$src2, $dst|$dst, $src2}",
2489 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2490 (memopv2i64 addr:$src2))))]>;
2492 } // Constraints = "$src1 = $dst"
2494 let Predicates = [HasSSE2] in {
2495 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2496 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2497 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2498 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2499 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2500 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2501 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2502 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2503 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2504 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2506 // Shift up / down and insert zero's.
2507 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2508 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2509 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2510 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2513 //===---------------------------------------------------------------------===//
2514 // SSE2 - Packed Integer Comparison Instructions
2515 //===---------------------------------------------------------------------===//
2517 let Constraints = "$src1 = $dst" in {
2518 let isCommutable = 1 in {
2519 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2520 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2521 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2523 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2524 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2525 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2526 } // Constraints = "$src1 = $dst"
2528 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2529 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2530 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2531 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2532 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2533 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2534 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2535 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2536 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2537 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2538 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2539 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2541 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2542 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2543 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2544 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2545 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2546 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2547 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2548 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2549 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2550 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2551 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2552 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2554 //===---------------------------------------------------------------------===//
2555 // SSE2 - Packed Integer Pack Instructions
2556 //===---------------------------------------------------------------------===//
2558 let Constraints = "$src1 = $dst" in {
2559 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2560 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2561 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2562 } // Constraints = "$src1 = $dst"
2564 //===---------------------------------------------------------------------===//
2565 // SSE2 - Packed Integer Shuffle Instructions
2566 //===---------------------------------------------------------------------===//
2568 let ExeDomain = SSEPackedInt in {
2570 // Shuffle and unpack instructions
2571 let AddedComplexity = 5 in {
2572 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2573 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2574 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2575 [(set VR128:$dst, (v4i32 (pshufd:$src2
2576 VR128:$src1, (undef))))]>;
2577 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2578 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2579 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2580 [(set VR128:$dst, (v4i32 (pshufd:$src2
2581 (bc_v4i32 (memopv2i64 addr:$src1)),
2585 // SSE2 with ImmT == Imm8 and XS prefix.
2586 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2587 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2588 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2589 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2591 XS, Requires<[HasSSE2]>;
2592 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2593 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2594 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2595 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2596 (bc_v8i16 (memopv2i64 addr:$src1)),
2598 XS, Requires<[HasSSE2]>;
2600 // SSE2 with ImmT == Imm8 and XD prefix.
2601 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2602 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2603 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2604 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2606 XD, Requires<[HasSSE2]>;
2607 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2608 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2609 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2610 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2611 (bc_v8i16 (memopv2i64 addr:$src1)),
2613 XD, Requires<[HasSSE2]>;
2615 } // ExeDomain = SSEPackedInt
2617 //===---------------------------------------------------------------------===//
2618 // SSE2 - Packed Integer Unpack Instructions
2619 //===---------------------------------------------------------------------===//
2621 let ExeDomain = SSEPackedInt in {
2623 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2624 PatFrag unp_frag, PatFrag bc_frag> {
2625 def rr : PDI<opc, MRMSrcReg,
2626 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2627 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2628 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2629 def rm : PDI<opc, MRMSrcMem,
2630 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2631 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2632 [(set VR128:$dst, (unp_frag VR128:$src1,
2633 (bc_frag (memopv2i64
2637 let Constraints = "$src1 = $dst" in {
2638 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2639 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2640 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2642 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2643 /// knew to collapse (bitconvert VT to VT) into its operand.
2644 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2645 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2646 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2648 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2649 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2650 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2651 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2653 (v2i64 (unpckl VR128:$src1,
2654 (memopv2i64 addr:$src2))))]>;
2656 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2657 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2658 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2660 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2661 /// knew to collapse (bitconvert VT to VT) into its operand.
2662 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2663 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2664 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2666 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2667 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2668 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2669 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2671 (v2i64 (unpckh VR128:$src1,
2672 (memopv2i64 addr:$src2))))]>;
2675 } // ExeDomain = SSEPackedInt
2677 //===---------------------------------------------------------------------===//
2678 // SSE2 - Packed Misc Integer Instructions
2679 //===---------------------------------------------------------------------===//
2681 let ExeDomain = SSEPackedInt in {
2684 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2685 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2686 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2687 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2689 let Constraints = "$src1 = $dst" in {
2690 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2691 (outs VR128:$dst), (ins VR128:$src1,
2692 GR32:$src2, i32i8imm:$src3),
2693 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2695 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2696 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2697 (outs VR128:$dst), (ins VR128:$src1,
2698 i16mem:$src2, i32i8imm:$src3),
2699 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2701 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2706 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2707 "pmovmskb\t{$src, $dst|$dst, $src}",
2708 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2710 // Conditional store
2712 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2713 "maskmovdqu\t{$mask, $src|$src, $mask}",
2714 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2717 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2718 "maskmovdqu\t{$mask, $src|$src, $mask}",
2719 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2721 } // ExeDomain = SSEPackedInt
2724 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2725 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2726 TB, Requires<[HasSSE2]>;
2728 // Load, store, and memory fence
2729 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2730 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2731 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2732 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2734 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2735 // was introduced with SSE2, it's backward compatible.
2736 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2738 //TODO: custom lower this so as to never even generate the noop
2739 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2741 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2742 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2743 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2746 // Alias instructions that map zero vector to pxor / xorp* for sse.
2747 // We set canFoldAsLoad because this can be converted to a constant-pool
2748 // load of an all-ones value if folding it would be beneficial.
2749 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2750 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2751 // FIXME: Change encoding to pseudo.
2752 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2753 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2755 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2756 "movd\t{$src, $dst|$dst, $src}",
2758 (v4i32 (scalar_to_vector GR32:$src)))]>;
2759 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2760 "movd\t{$src, $dst|$dst, $src}",
2762 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2764 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2765 "movd\t{$src, $dst|$dst, $src}",
2766 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2768 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2769 "movd\t{$src, $dst|$dst, $src}",
2770 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2772 // SSE2 instructions with XS prefix
2773 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2774 "movq\t{$src, $dst|$dst, $src}",
2776 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2777 Requires<[HasSSE2]>;
2778 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2779 "movq\t{$src, $dst|$dst, $src}",
2780 [(store (i64 (vector_extract (v2i64 VR128:$src),
2781 (iPTR 0))), addr:$dst)]>;
2783 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2784 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2786 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2787 "movd\t{$src, $dst|$dst, $src}",
2788 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2790 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2791 "movd\t{$src, $dst|$dst, $src}",
2792 [(store (i32 (vector_extract (v4i32 VR128:$src),
2793 (iPTR 0))), addr:$dst)]>;
2795 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2796 "movd\t{$src, $dst|$dst, $src}",
2797 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2798 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2799 "movd\t{$src, $dst|$dst, $src}",
2800 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2802 // Store / copy lower 64-bits of a XMM register.
2803 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2804 "movq\t{$src, $dst|$dst, $src}",
2805 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2807 // movd / movq to XMM register zero-extends
2808 let AddedComplexity = 15 in {
2809 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2810 "movd\t{$src, $dst|$dst, $src}",
2811 [(set VR128:$dst, (v4i32 (X86vzmovl
2812 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2813 // This is X86-64 only.
2814 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2815 "mov{d|q}\t{$src, $dst|$dst, $src}",
2816 [(set VR128:$dst, (v2i64 (X86vzmovl
2817 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2820 let AddedComplexity = 20 in {
2821 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2822 "movd\t{$src, $dst|$dst, $src}",
2824 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2825 (loadi32 addr:$src))))))]>;
2827 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2828 (MOVZDI2PDIrm addr:$src)>;
2829 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2830 (MOVZDI2PDIrm addr:$src)>;
2831 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2832 (MOVZDI2PDIrm addr:$src)>;
2834 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2835 "movq\t{$src, $dst|$dst, $src}",
2837 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2838 (loadi64 addr:$src))))))]>, XS,
2839 Requires<[HasSSE2]>;
2841 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2842 (MOVZQI2PQIrm addr:$src)>;
2843 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2844 (MOVZQI2PQIrm addr:$src)>;
2845 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2848 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2849 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2850 let AddedComplexity = 15 in
2851 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2852 "movq\t{$src, $dst|$dst, $src}",
2853 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2854 XS, Requires<[HasSSE2]>;
2856 let AddedComplexity = 20 in {
2857 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2858 "movq\t{$src, $dst|$dst, $src}",
2859 [(set VR128:$dst, (v2i64 (X86vzmovl
2860 (loadv2i64 addr:$src))))]>,
2861 XS, Requires<[HasSSE2]>;
2863 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2864 (MOVZPQILo2PQIrm addr:$src)>;
2867 // Instructions for the disassembler
2868 // xr = XMM register
2871 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2872 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2874 //===---------------------------------------------------------------------===//
2875 // SSE3 Instructions
2876 //===---------------------------------------------------------------------===//
2878 // Conversion Instructions
2879 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2880 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2881 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2882 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2883 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2884 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2885 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2886 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2888 // Move Instructions
2889 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2890 "movshdup\t{$src, $dst|$dst, $src}",
2891 [(set VR128:$dst, (v4f32 (movshdup
2892 VR128:$src, (undef))))]>;
2893 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2894 "movshdup\t{$src, $dst|$dst, $src}",
2895 [(set VR128:$dst, (movshdup
2896 (memopv4f32 addr:$src), (undef)))]>;
2898 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2899 "movsldup\t{$src, $dst|$dst, $src}",
2900 [(set VR128:$dst, (v4f32 (movsldup
2901 VR128:$src, (undef))))]>;
2902 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2903 "movsldup\t{$src, $dst|$dst, $src}",
2904 [(set VR128:$dst, (movsldup
2905 (memopv4f32 addr:$src), (undef)))]>;
2907 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2908 "movddup\t{$src, $dst|$dst, $src}",
2909 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2910 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2911 "movddup\t{$src, $dst|$dst, $src}",
2913 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2916 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2918 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2920 let AddedComplexity = 5 in {
2921 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2922 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2923 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2924 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2925 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2926 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2927 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2928 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2932 let Constraints = "$src1 = $dst" in {
2933 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2934 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2935 "addsubps\t{$src2, $dst|$dst, $src2}",
2936 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2938 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2939 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2940 "addsubps\t{$src2, $dst|$dst, $src2}",
2941 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2942 (memop addr:$src2)))]>;
2943 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2944 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2945 "addsubpd\t{$src2, $dst|$dst, $src2}",
2946 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2948 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2949 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2950 "addsubpd\t{$src2, $dst|$dst, $src2}",
2951 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2952 (memop addr:$src2)))]>;
2955 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2956 "lddqu\t{$src, $dst|$dst, $src}",
2957 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2960 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2961 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2962 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2963 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2964 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2965 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2966 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2967 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2968 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2969 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2970 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2971 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2972 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2973 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2974 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2975 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2977 let Constraints = "$src1 = $dst" in {
2978 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2979 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2980 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2981 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2982 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2983 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2984 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2985 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2988 // Thread synchronization
2989 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2990 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2991 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2992 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2994 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2995 let AddedComplexity = 15 in
2996 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2997 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2998 let AddedComplexity = 20 in
2999 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3000 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3002 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3003 let AddedComplexity = 15 in
3004 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3005 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3006 let AddedComplexity = 20 in
3007 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3008 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3010 //===---------------------------------------------------------------------===//
3011 // SSSE3 Instructions
3012 //===---------------------------------------------------------------------===//
3014 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
3015 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
3016 Intrinsic IntId64, Intrinsic IntId128> {
3017 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3018 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3019 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3021 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3024 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
3026 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3028 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3029 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3032 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3034 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3037 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
3040 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
3041 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
3042 Intrinsic IntId64, Intrinsic IntId128> {
3043 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3045 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3046 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3048 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3050 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3053 (bitconvert (memopv4i16 addr:$src))))]>;
3055 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3057 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3058 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3061 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3063 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3066 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3069 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
3070 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
3071 Intrinsic IntId64, Intrinsic IntId128> {
3072 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3075 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3077 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3079 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3082 (bitconvert (memopv2i32 addr:$src))))]>;
3084 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3086 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3087 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3090 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3092 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3095 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
3098 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
3099 int_x86_ssse3_pabs_b,
3100 int_x86_ssse3_pabs_b_128>;
3101 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
3102 int_x86_ssse3_pabs_w,
3103 int_x86_ssse3_pabs_w_128>;
3104 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
3105 int_x86_ssse3_pabs_d,
3106 int_x86_ssse3_pabs_d_128>;
3108 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
3109 let Constraints = "$src1 = $dst" in {
3110 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
3111 Intrinsic IntId64, Intrinsic IntId128,
3112 bit Commutable = 0> {
3113 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3114 (ins VR64:$src1, VR64:$src2),
3115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3116 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3117 let isCommutable = Commutable;
3119 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3120 (ins VR64:$src1, i64mem:$src2),
3121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3123 (IntId64 VR64:$src1,
3124 (bitconvert (memopv8i8 addr:$src2))))]>;
3126 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3127 (ins VR128:$src1, VR128:$src2),
3128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3129 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3131 let isCommutable = Commutable;
3133 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3134 (ins VR128:$src1, i128mem:$src2),
3135 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3137 (IntId128 VR128:$src1,
3138 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3142 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
3143 let Constraints = "$src1 = $dst" in {
3144 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
3145 Intrinsic IntId64, Intrinsic IntId128,
3146 bit Commutable = 0> {
3147 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3148 (ins VR64:$src1, VR64:$src2),
3149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3150 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3151 let isCommutable = Commutable;
3153 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3154 (ins VR64:$src1, i64mem:$src2),
3155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3157 (IntId64 VR64:$src1,
3158 (bitconvert (memopv4i16 addr:$src2))))]>;
3160 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3161 (ins VR128:$src1, VR128:$src2),
3162 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3163 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3165 let isCommutable = Commutable;
3167 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3168 (ins VR128:$src1, i128mem:$src2),
3169 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3171 (IntId128 VR128:$src1,
3172 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
3176 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
3177 let Constraints = "$src1 = $dst" in {
3178 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
3179 Intrinsic IntId64, Intrinsic IntId128,
3180 bit Commutable = 0> {
3181 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3182 (ins VR64:$src1, VR64:$src2),
3183 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3184 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3185 let isCommutable = Commutable;
3187 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3188 (ins VR64:$src1, i64mem:$src2),
3189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3191 (IntId64 VR64:$src1,
3192 (bitconvert (memopv2i32 addr:$src2))))]>;
3194 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3195 (ins VR128:$src1, VR128:$src2),
3196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3197 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3199 let isCommutable = Commutable;
3201 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3202 (ins VR128:$src1, i128mem:$src2),
3203 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3205 (IntId128 VR128:$src1,
3206 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
3210 let ImmT = NoImm in { // None of these have i8 immediate fields.
3211 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
3212 int_x86_ssse3_phadd_w,
3213 int_x86_ssse3_phadd_w_128>;
3214 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
3215 int_x86_ssse3_phadd_d,
3216 int_x86_ssse3_phadd_d_128>;
3217 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
3218 int_x86_ssse3_phadd_sw,
3219 int_x86_ssse3_phadd_sw_128>;
3220 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
3221 int_x86_ssse3_phsub_w,
3222 int_x86_ssse3_phsub_w_128>;
3223 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
3224 int_x86_ssse3_phsub_d,
3225 int_x86_ssse3_phsub_d_128>;
3226 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
3227 int_x86_ssse3_phsub_sw,
3228 int_x86_ssse3_phsub_sw_128>;
3229 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
3230 int_x86_ssse3_pmadd_ub_sw,
3231 int_x86_ssse3_pmadd_ub_sw_128>;
3232 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
3233 int_x86_ssse3_pmul_hr_sw,
3234 int_x86_ssse3_pmul_hr_sw_128, 1>;
3236 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
3237 int_x86_ssse3_pshuf_b,
3238 int_x86_ssse3_pshuf_b_128>;
3239 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
3240 int_x86_ssse3_psign_b,
3241 int_x86_ssse3_psign_b_128>;
3242 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
3243 int_x86_ssse3_psign_w,
3244 int_x86_ssse3_psign_w_128>;
3245 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
3246 int_x86_ssse3_psign_d,
3247 int_x86_ssse3_psign_d_128>;
3250 // palignr patterns.
3251 let Constraints = "$src1 = $dst" in {
3252 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3253 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3254 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3256 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3257 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3258 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3261 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3262 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3263 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3265 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3266 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3267 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3271 let AddedComplexity = 5 in {
3273 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3274 (PALIGNR64rr VR64:$src2, VR64:$src1,
3275 (SHUFFLE_get_palign_imm VR64:$src3))>,
3276 Requires<[HasSSSE3]>;
3277 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3278 (PALIGNR64rr VR64:$src2, VR64:$src1,
3279 (SHUFFLE_get_palign_imm VR64:$src3))>,
3280 Requires<[HasSSSE3]>;
3281 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
3282 (PALIGNR64rr VR64:$src2, VR64:$src1,
3283 (SHUFFLE_get_palign_imm VR64:$src3))>,
3284 Requires<[HasSSSE3]>;
3285 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3286 (PALIGNR64rr VR64:$src2, VR64:$src1,
3287 (SHUFFLE_get_palign_imm VR64:$src3))>,
3288 Requires<[HasSSSE3]>;
3289 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3290 (PALIGNR64rr VR64:$src2, VR64:$src1,
3291 (SHUFFLE_get_palign_imm VR64:$src3))>,
3292 Requires<[HasSSSE3]>;
3294 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3295 (PALIGNR128rr VR128:$src2, VR128:$src1,
3296 (SHUFFLE_get_palign_imm VR128:$src3))>,
3297 Requires<[HasSSSE3]>;
3298 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3299 (PALIGNR128rr VR128:$src2, VR128:$src1,
3300 (SHUFFLE_get_palign_imm VR128:$src3))>,
3301 Requires<[HasSSSE3]>;
3302 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3303 (PALIGNR128rr VR128:$src2, VR128:$src1,
3304 (SHUFFLE_get_palign_imm VR128:$src3))>,
3305 Requires<[HasSSSE3]>;
3306 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3307 (PALIGNR128rr VR128:$src2, VR128:$src1,
3308 (SHUFFLE_get_palign_imm VR128:$src3))>,
3309 Requires<[HasSSSE3]>;
3312 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3313 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3314 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3315 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3317 //===---------------------------------------------------------------------===//
3318 // Non-Instruction Patterns
3319 //===---------------------------------------------------------------------===//
3321 // extload f32 -> f64. This matches load+fextend because we have a hack in
3322 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3324 // Since these loads aren't folded into the fextend, we have to match it
3326 let Predicates = [HasSSE2] in
3327 def : Pat<(fextend (loadf32 addr:$src)),
3328 (CVTSS2SDrm addr:$src)>;
3331 let Predicates = [HasSSE2] in {
3332 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3333 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3334 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3335 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3336 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3337 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3338 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3339 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3340 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3341 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3342 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3343 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3344 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3345 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3346 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3347 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3348 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3349 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3350 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3351 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3352 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3353 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3354 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3355 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3356 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3357 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3358 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3359 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3360 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3361 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3364 // Move scalar to XMM zero-extended
3365 // movd to XMM register zero-extends
3366 let AddedComplexity = 15 in {
3367 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3368 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3369 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3370 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3371 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3372 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3373 (MOVSSrr (v4f32 (V_SET0PS)),
3374 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3375 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3376 (MOVSSrr (v4i32 (V_SET0PI)),
3377 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3380 // Splat v2f64 / v2i64
3381 let AddedComplexity = 10 in {
3382 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3383 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3384 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3385 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3386 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3387 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3388 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3389 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3392 // Special unary SHUFPSrri case.
3393 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3394 (SHUFPSrri VR128:$src1, VR128:$src1,
3395 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3396 let AddedComplexity = 5 in
3397 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3398 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3399 Requires<[HasSSE2]>;
3400 // Special unary SHUFPDrri case.
3401 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3402 (SHUFPDrri VR128:$src1, VR128:$src1,
3403 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3404 Requires<[HasSSE2]>;
3405 // Special unary SHUFPDrri case.
3406 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3407 (SHUFPDrri VR128:$src1, VR128:$src1,
3408 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3409 Requires<[HasSSE2]>;
3410 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3411 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3412 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3413 Requires<[HasSSE2]>;
3415 // Special binary v4i32 shuffle cases with SHUFPS.
3416 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3417 (SHUFPSrri VR128:$src1, VR128:$src2,
3418 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3419 Requires<[HasSSE2]>;
3420 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3421 (SHUFPSrmi VR128:$src1, addr:$src2,
3422 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3423 Requires<[HasSSE2]>;
3424 // Special binary v2i64 shuffle cases using SHUFPDrri.
3425 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3426 (SHUFPDrri VR128:$src1, VR128:$src2,
3427 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3428 Requires<[HasSSE2]>;
3430 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3431 let AddedComplexity = 15 in {
3432 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3433 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3434 Requires<[OptForSpeed, HasSSE2]>;
3435 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3436 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3437 Requires<[OptForSpeed, HasSSE2]>;
3439 let AddedComplexity = 10 in {
3440 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3441 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3442 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3443 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3444 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3445 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3446 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3447 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3450 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3451 let AddedComplexity = 15 in {
3452 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3453 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3454 Requires<[OptForSpeed, HasSSE2]>;
3455 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3456 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3457 Requires<[OptForSpeed, HasSSE2]>;
3459 let AddedComplexity = 10 in {
3460 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3461 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3462 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3463 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3464 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3465 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3466 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3467 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3470 let AddedComplexity = 20 in {
3471 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3472 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3473 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3475 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3476 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3477 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3479 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3480 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3481 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3482 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3483 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3486 let AddedComplexity = 20 in {
3487 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3488 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3489 (MOVLPSrm VR128:$src1, addr:$src2)>;
3490 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3491 (MOVLPDrm VR128:$src1, addr:$src2)>;
3492 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3493 (MOVLPSrm VR128:$src1, addr:$src2)>;
3494 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3495 (MOVLPDrm VR128:$src1, addr:$src2)>;
3498 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3499 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3500 (MOVLPSmr addr:$src1, VR128:$src2)>;
3501 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3502 (MOVLPDmr addr:$src1, VR128:$src2)>;
3503 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3505 (MOVLPSmr addr:$src1, VR128:$src2)>;
3506 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3507 (MOVLPDmr addr:$src1, VR128:$src2)>;
3509 let AddedComplexity = 15 in {
3510 // Setting the lowest element in the vector.
3511 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3512 (MOVSSrr (v4i32 VR128:$src1),
3513 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3514 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3515 (MOVSDrr (v2i64 VR128:$src1),
3516 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3518 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3519 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3520 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3521 Requires<[HasSSE2]>;
3522 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3523 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3524 Requires<[HasSSE2]>;
3527 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3528 // fall back to this for SSE1)
3529 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3530 (SHUFPSrri VR128:$src2, VR128:$src1,
3531 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3533 // Set lowest element and zero upper elements.
3534 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3535 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3537 // Some special case pandn patterns.
3538 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3540 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3541 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3543 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3544 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3546 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3548 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3549 (memop addr:$src2))),
3550 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3551 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3552 (memop addr:$src2))),
3553 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3554 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3555 (memop addr:$src2))),
3556 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3558 // vector -> vector casts
3559 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3560 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3561 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3562 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3563 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3564 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3565 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3566 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3568 // Use movaps / movups for SSE integer load / store (one byte shorter).
3569 def : Pat<(alignedloadv4i32 addr:$src),
3570 (MOVAPSrm addr:$src)>;
3571 def : Pat<(loadv4i32 addr:$src),
3572 (MOVUPSrm addr:$src)>;
3573 def : Pat<(alignedloadv2i64 addr:$src),
3574 (MOVAPSrm addr:$src)>;
3575 def : Pat<(loadv2i64 addr:$src),
3576 (MOVUPSrm addr:$src)>;
3578 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3579 (MOVAPSmr addr:$dst, VR128:$src)>;
3580 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3581 (MOVAPSmr addr:$dst, VR128:$src)>;
3582 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3583 (MOVAPSmr addr:$dst, VR128:$src)>;
3584 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3585 (MOVAPSmr addr:$dst, VR128:$src)>;
3586 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3587 (MOVUPSmr addr:$dst, VR128:$src)>;
3588 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3589 (MOVUPSmr addr:$dst, VR128:$src)>;
3590 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3591 (MOVUPSmr addr:$dst, VR128:$src)>;
3592 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3593 (MOVUPSmr addr:$dst, VR128:$src)>;
3595 //===----------------------------------------------------------------------===//
3596 // SSE4.1 Instructions
3597 //===----------------------------------------------------------------------===//
3599 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3602 Intrinsic V2F64Int> {
3603 // Intrinsic operation, reg.
3604 // Vector intrinsic operation, reg
3605 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3606 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3607 !strconcat(OpcodeStr,
3608 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3609 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3612 // Vector intrinsic operation, mem
3613 def PSm_Int : Ii8<opcps, MRMSrcMem,
3614 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3615 !strconcat(OpcodeStr,
3616 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3618 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3620 Requires<[HasSSE41]>;
3622 // Vector intrinsic operation, reg
3623 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3624 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3625 !strconcat(OpcodeStr,
3626 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3627 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3630 // Vector intrinsic operation, mem
3631 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3632 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3633 !strconcat(OpcodeStr,
3634 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3636 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3640 let Constraints = "$src1 = $dst" in {
3641 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3645 // Intrinsic operation, reg.
3646 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3648 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3649 !strconcat(OpcodeStr,
3650 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3652 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3655 // Intrinsic operation, mem.
3656 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3658 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3659 !strconcat(OpcodeStr,
3660 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3662 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3665 // Intrinsic operation, reg.
3666 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3668 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3669 !strconcat(OpcodeStr,
3670 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3672 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3675 // Intrinsic operation, mem.
3676 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3678 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3679 !strconcat(OpcodeStr,
3680 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3682 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3687 // FP round - roundss, roundps, roundsd, roundpd
3688 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3689 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3690 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3691 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3693 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3694 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3695 Intrinsic IntId128> {
3696 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3699 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3700 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3705 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3708 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3709 int_x86_sse41_phminposuw>;
3711 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3712 let Constraints = "$src1 = $dst" in {
3713 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3714 Intrinsic IntId128, bit Commutable = 0> {
3715 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3716 (ins VR128:$src1, VR128:$src2),
3717 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3718 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3720 let isCommutable = Commutable;
3722 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3723 (ins VR128:$src1, i128mem:$src2),
3724 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3726 (IntId128 VR128:$src1,
3727 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3731 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3732 int_x86_sse41_pcmpeqq, 1>;
3733 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3734 int_x86_sse41_packusdw, 0>;
3735 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3736 int_x86_sse41_pminsb, 1>;
3737 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3738 int_x86_sse41_pminsd, 1>;
3739 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3740 int_x86_sse41_pminud, 1>;
3741 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3742 int_x86_sse41_pminuw, 1>;
3743 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3744 int_x86_sse41_pmaxsb, 1>;
3745 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3746 int_x86_sse41_pmaxsd, 1>;
3747 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3748 int_x86_sse41_pmaxud, 1>;
3749 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3750 int_x86_sse41_pmaxuw, 1>;
3752 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3754 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3755 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3756 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3757 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3759 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3760 let Constraints = "$src1 = $dst" in {
3761 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3762 SDNode OpNode, Intrinsic IntId128,
3763 bit Commutable = 0> {
3764 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3765 (ins VR128:$src1, VR128:$src2),
3766 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3767 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3768 VR128:$src2))]>, OpSize {
3769 let isCommutable = Commutable;
3771 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3772 (ins VR128:$src1, VR128:$src2),
3773 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3774 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3776 let isCommutable = Commutable;
3778 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3779 (ins VR128:$src1, i128mem:$src2),
3780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3782 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3783 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3784 (ins VR128:$src1, i128mem:$src2),
3785 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3787 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3792 /// SS48I_binop_rm - Simple SSE41 binary operator.
3793 let Constraints = "$src1 = $dst" in {
3794 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3795 ValueType OpVT, bit Commutable = 0> {
3796 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3797 (ins VR128:$src1, VR128:$src2),
3798 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3799 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3801 let isCommutable = Commutable;
3803 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3804 (ins VR128:$src1, i128mem:$src2),
3805 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3806 [(set VR128:$dst, (OpNode VR128:$src1,
3807 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3812 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3814 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3815 let Constraints = "$src1 = $dst" in {
3816 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3817 Intrinsic IntId128, bit Commutable = 0> {
3818 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3819 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3820 !strconcat(OpcodeStr,
3821 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3823 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3825 let isCommutable = Commutable;
3827 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3828 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3829 !strconcat(OpcodeStr,
3830 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3832 (IntId128 VR128:$src1,
3833 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3838 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3839 int_x86_sse41_blendps, 0>;
3840 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3841 int_x86_sse41_blendpd, 0>;
3842 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3843 int_x86_sse41_pblendw, 0>;
3844 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3845 int_x86_sse41_dpps, 1>;
3846 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3847 int_x86_sse41_dppd, 1>;
3848 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3849 int_x86_sse41_mpsadbw, 0>;
3852 /// SS41I_ternary_int - SSE 4.1 ternary operator
3853 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3854 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3855 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3856 (ins VR128:$src1, VR128:$src2),
3857 !strconcat(OpcodeStr,
3858 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3859 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3862 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3863 (ins VR128:$src1, i128mem:$src2),
3864 !strconcat(OpcodeStr,
3865 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3868 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3872 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3873 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3874 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3877 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3878 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3880 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3882 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3883 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3885 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3889 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3890 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3891 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3892 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3893 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3894 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3896 // Common patterns involving scalar load.
3897 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3898 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3899 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3900 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3902 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3903 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3904 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3905 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3907 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3908 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3909 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3910 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3912 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3913 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3914 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3915 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3917 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3918 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3919 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3920 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3922 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3923 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3924 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3925 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3928 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3929 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3931 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3933 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3934 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3936 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3940 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3941 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3942 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3943 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3945 // Common patterns involving scalar load
3946 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3947 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3948 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3949 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3951 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3952 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3953 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3954 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3957 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3958 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3959 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3960 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3962 // Expecting a i16 load any extended to i32 value.
3963 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3964 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3965 [(set VR128:$dst, (IntId (bitconvert
3966 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3970 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3971 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3973 // Common patterns involving scalar load
3974 def : Pat<(int_x86_sse41_pmovsxbq
3975 (bitconvert (v4i32 (X86vzmovl
3976 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3977 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3979 def : Pat<(int_x86_sse41_pmovzxbq
3980 (bitconvert (v4i32 (X86vzmovl
3981 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3982 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3985 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3986 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3987 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3988 (ins VR128:$src1, i32i8imm:$src2),
3989 !strconcat(OpcodeStr,
3990 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3991 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3993 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3994 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3995 !strconcat(OpcodeStr,
3996 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3999 // There's an AssertZext in the way of writing the store pattern
4000 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4003 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4006 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4007 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4008 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4009 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4010 !strconcat(OpcodeStr,
4011 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4014 // There's an AssertZext in the way of writing the store pattern
4015 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4018 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4021 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4022 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4023 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4024 (ins VR128:$src1, i32i8imm:$src2),
4025 !strconcat(OpcodeStr,
4026 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4028 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4029 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4030 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4031 !strconcat(OpcodeStr,
4032 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4033 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4034 addr:$dst)]>, OpSize;
4037 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4040 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4042 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4043 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4044 (ins VR128:$src1, i32i8imm:$src2),
4045 !strconcat(OpcodeStr,
4046 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4048 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4050 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4051 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4052 !strconcat(OpcodeStr,
4053 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4054 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4055 addr:$dst)]>, OpSize;
4058 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4060 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4061 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4064 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4065 Requires<[HasSSE41]>;
4067 let Constraints = "$src1 = $dst" in {
4068 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
4069 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4070 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4071 !strconcat(OpcodeStr,
4072 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4074 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4075 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4076 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4077 !strconcat(OpcodeStr,
4078 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4080 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4081 imm:$src3))]>, OpSize;
4085 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4087 let Constraints = "$src1 = $dst" in {
4088 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
4089 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4090 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4091 !strconcat(OpcodeStr,
4092 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4094 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4096 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4097 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4098 !strconcat(OpcodeStr,
4099 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4101 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4102 imm:$src3)))]>, OpSize;
4106 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4108 // insertps has a few different modes, there's the first two here below which
4109 // are optimized inserts that won't zero arbitrary elements in the destination
4110 // vector. The next one matches the intrinsic and could zero arbitrary elements
4111 // in the target vector.
4112 let Constraints = "$src1 = $dst" in {
4113 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
4114 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4115 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4116 !strconcat(OpcodeStr,
4117 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4119 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4121 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4122 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4123 !strconcat(OpcodeStr,
4124 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4126 (X86insrtps VR128:$src1,
4127 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4128 imm:$src3))]>, OpSize;
4132 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4134 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4135 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
4137 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4138 // the intel intrinsic that corresponds to this.
4139 let Defs = [EFLAGS] in {
4140 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4141 "ptest \t{$src2, $src1|$src1, $src2}",
4142 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4144 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4145 "ptest \t{$src2, $src1|$src1, $src2}",
4146 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4150 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4151 "movntdqa\t{$src, $dst|$dst, $src}",
4152 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4156 //===----------------------------------------------------------------------===//
4157 // SSE4.2 Instructions
4158 //===----------------------------------------------------------------------===//
4160 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4161 let Constraints = "$src1 = $dst" in {
4162 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4163 Intrinsic IntId128, bit Commutable = 0> {
4164 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4165 (ins VR128:$src1, VR128:$src2),
4166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4167 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4169 let isCommutable = Commutable;
4171 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4172 (ins VR128:$src1, i128mem:$src2),
4173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4175 (IntId128 VR128:$src1,
4176 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4180 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4182 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4183 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4184 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4185 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4187 // crc intrinsic instruction
4188 // This set of instructions are only rm, the only difference is the size
4190 let Constraints = "$src1 = $dst" in {
4191 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4192 (ins GR32:$src1, i8mem:$src2),
4193 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4195 (int_x86_sse42_crc32_8 GR32:$src1,
4196 (load addr:$src2)))]>;
4197 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4198 (ins GR32:$src1, GR8:$src2),
4199 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4201 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4202 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4203 (ins GR32:$src1, i16mem:$src2),
4204 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4206 (int_x86_sse42_crc32_16 GR32:$src1,
4207 (load addr:$src2)))]>,
4209 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4210 (ins GR32:$src1, GR16:$src2),
4211 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4213 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4215 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4216 (ins GR32:$src1, i32mem:$src2),
4217 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4219 (int_x86_sse42_crc32_32 GR32:$src1,
4220 (load addr:$src2)))]>;
4221 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4222 (ins GR32:$src1, GR32:$src2),
4223 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4225 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4226 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4227 (ins GR64:$src1, i8mem:$src2),
4228 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4230 (int_x86_sse42_crc64_8 GR64:$src1,
4231 (load addr:$src2)))]>,
4233 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4234 (ins GR64:$src1, GR8:$src2),
4235 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4237 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4239 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4240 (ins GR64:$src1, i64mem:$src2),
4241 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4243 (int_x86_sse42_crc64_64 GR64:$src1,
4244 (load addr:$src2)))]>,
4246 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4247 (ins GR64:$src1, GR64:$src2),
4248 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4250 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
4254 // String/text processing instructions.
4255 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4256 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4257 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4258 "#PCMPISTRM128rr PSEUDO!",
4259 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4260 imm:$src3))]>, OpSize;
4261 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4262 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4263 "#PCMPISTRM128rm PSEUDO!",
4264 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
4265 imm:$src3))]>, OpSize;
4268 let Defs = [XMM0, EFLAGS] in {
4269 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4270 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4271 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4272 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4273 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4274 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4277 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4278 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4279 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4280 "#PCMPESTRM128rr PSEUDO!",
4282 (int_x86_sse42_pcmpestrm128
4283 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
4285 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4286 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4287 "#PCMPESTRM128rm PSEUDO!",
4288 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4289 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
4293 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4294 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4295 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4296 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4297 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4298 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4299 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4302 let Defs = [ECX, EFLAGS] in {
4303 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
4304 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4305 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4306 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4307 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4308 (implicit EFLAGS)]>, OpSize;
4309 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4310 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4311 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4312 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4313 (implicit EFLAGS)]>, OpSize;
4317 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4318 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4319 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4320 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4321 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4322 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4324 let Defs = [ECX, EFLAGS] in {
4325 let Uses = [EAX, EDX] in {
4326 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4327 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4328 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4329 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4330 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4331 (implicit EFLAGS)]>, OpSize;
4332 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4333 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4334 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4336 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4337 (implicit EFLAGS)]>, OpSize;
4342 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4343 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4344 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4345 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4346 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4347 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4349 //===----------------------------------------------------------------------===//
4350 // AES-NI Instructions
4351 //===----------------------------------------------------------------------===//
4353 let Constraints = "$src1 = $dst" in {
4354 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4355 Intrinsic IntId128, bit Commutable = 0> {
4356 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4357 (ins VR128:$src1, VR128:$src2),
4358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4359 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4361 let isCommutable = Commutable;
4363 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4364 (ins VR128:$src1, i128mem:$src2),
4365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4367 (IntId128 VR128:$src1,
4368 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4372 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4373 int_x86_aesni_aesenc>;
4374 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4375 int_x86_aesni_aesenclast>;
4376 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4377 int_x86_aesni_aesdec>;
4378 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4379 int_x86_aesni_aesdeclast>;
4381 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4382 (AESENCrr VR128:$src1, VR128:$src2)>;
4383 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4384 (AESENCrm VR128:$src1, addr:$src2)>;
4385 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4386 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4387 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4388 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4389 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4390 (AESDECrr VR128:$src1, VR128:$src2)>;
4391 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4392 (AESDECrm VR128:$src1, addr:$src2)>;
4393 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4394 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4395 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4396 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4398 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4400 "aesimc\t{$src1, $dst|$dst, $src1}",
4402 (int_x86_aesni_aesimc VR128:$src1))]>,
4405 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4406 (ins i128mem:$src1),
4407 "aesimc\t{$src1, $dst|$dst, $src1}",
4409 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4412 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4413 (ins VR128:$src1, i8imm:$src2),
4414 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4416 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4418 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4419 (ins i128mem:$src1, i8imm:$src2),
4420 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4422 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),