1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 let isCommutable = 1, hasSideEffects = 0 in
208 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
212 pat_rr, IIC_DEFAULT, d>;
213 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 pat_rm, IIC_DEFAULT, d>;
220 //===----------------------------------------------------------------------===//
221 // Non-instruction patterns
222 //===----------------------------------------------------------------------===//
224 // A vector extract of the first f32/f64 position is a subregister copy
225 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
226 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
227 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
228 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
230 // A 128-bit subvector extract from the first 256-bit vector position
231 // is a subregister copy that needs no instruction.
232 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
233 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
234 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
235 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
237 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
238 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
239 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
240 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
242 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
243 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
244 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
245 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
247 // A 128-bit subvector insert to the first 256-bit vector position
248 // is a subregister copy that needs no instruction.
249 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
250 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
251 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
252 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
253 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
254 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
255 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
256 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
257 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
258 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
259 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
260 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
261 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
264 // Implicitly promote a 32-bit scalar to a vector.
265 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
266 (COPY_TO_REGCLASS FR32:$src, VR128)>;
267 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
268 (COPY_TO_REGCLASS FR32:$src, VR128)>;
269 // Implicitly promote a 64-bit scalar to a vector.
270 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
271 (COPY_TO_REGCLASS FR64:$src, VR128)>;
272 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
273 (COPY_TO_REGCLASS FR64:$src, VR128)>;
275 // Bitcasts between 128-bit vector types. Return the original type since
276 // no instruction is needed for the conversion
277 let Predicates = [HasSSE2] in {
278 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
279 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
280 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
281 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
282 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
283 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
284 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
285 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
286 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
287 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
288 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
289 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
290 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
291 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
292 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
293 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
294 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
295 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
296 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
297 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
298 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
299 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
300 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
301 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
302 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
303 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
304 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
305 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
306 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
307 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
310 // Bitcasts between 256-bit vector types. Return the original type since
311 // no instruction is needed for the conversion
312 let Predicates = [HasAVX] in {
313 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
314 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
315 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
316 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
317 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
318 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
319 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
320 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
321 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
322 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
323 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
324 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
325 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
326 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
327 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
328 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
329 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
330 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
331 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
332 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
333 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
334 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
335 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
336 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
337 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
338 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
339 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
340 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
341 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
342 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
345 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
346 // This is expanded by ExpandPostRAPseudos.
347 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
349 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
350 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
351 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
352 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
355 //===----------------------------------------------------------------------===//
356 // AVX & SSE - Zero/One Vectors
357 //===----------------------------------------------------------------------===//
359 // Alias instruction that maps zero vector to pxor / xorp* for sse.
360 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
361 // swizzled by ExecutionDepsFix to pxor.
362 // We set canFoldAsLoad because this can be converted to a constant-pool
363 // load of an all-zeros value if folding it would be beneficial.
364 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
366 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
367 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
370 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
371 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
372 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
373 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
374 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
377 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
378 // and doesn't need it because on sandy bridge the register is set to zero
379 // at the rename stage without using any execution unit, so SET0PSY
380 // and SET0PDY can be used for vector int instructions without penalty
381 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
382 isPseudo = 1, Predicates = [HasAVX] in {
383 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
384 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
387 let Predicates = [HasAVX] in
388 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
390 let Predicates = [HasAVX2] in {
391 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
392 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
393 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
394 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
397 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
398 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
399 let Predicates = [HasAVX1Only] in {
400 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
401 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
402 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
404 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
405 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
406 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
408 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
409 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
410 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
412 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
413 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
414 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
417 // We set canFoldAsLoad because this can be converted to a constant-pool
418 // load of an all-ones value if folding it would be beneficial.
419 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
421 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
422 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
423 let Predicates = [HasAVX2] in
424 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
425 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
429 //===----------------------------------------------------------------------===//
430 // SSE 1 & 2 - Move FP Scalar Instructions
432 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
433 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
434 // is used instead. Register-to-register movss/movsd is not modeled as an
435 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
436 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
437 //===----------------------------------------------------------------------===//
439 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
440 X86MemOperand x86memop, string base_opc,
442 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
443 (ins VR128:$src1, RC:$src2),
444 !strconcat(base_opc, asm_opr),
445 [(set VR128:$dst, (vt (OpNode VR128:$src1,
446 (scalar_to_vector RC:$src2))))],
449 // For the disassembler
450 let isCodeGenOnly = 1, hasSideEffects = 0 in
451 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
452 (ins VR128:$src1, RC:$src2),
453 !strconcat(base_opc, asm_opr),
454 [], IIC_SSE_MOV_S_RR>;
457 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
458 X86MemOperand x86memop, string OpcodeStr> {
460 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
461 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
464 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
465 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
466 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
469 let Constraints = "$src1 = $dst" in {
470 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
471 "\t{$src2, $dst|$dst, $src2}">;
474 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
475 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
476 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
479 // Loading from memory automatically zeroing upper bits.
480 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
481 PatFrag mem_pat, string OpcodeStr> {
482 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
483 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
484 [(set RC:$dst, (mem_pat addr:$src))],
485 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG;
486 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
488 [(set RC:$dst, (mem_pat addr:$src))],
492 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
493 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
495 let canFoldAsLoad = 1, isReMaterializable = 1 in {
496 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
498 let AddedComplexity = 20 in
499 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
503 let Predicates = [HasAVX] in {
504 let AddedComplexity = 15 in {
505 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
506 // MOVS{S,D} to the lower bits.
507 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
508 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
509 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
510 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
511 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
512 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
513 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
514 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
516 // Move low f32 and clear high bits.
517 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
518 (SUBREG_TO_REG (i32 0),
519 (VMOVSSrr (v4f32 (V_SET0)),
520 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
521 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
522 (SUBREG_TO_REG (i32 0),
523 (VMOVSSrr (v4i32 (V_SET0)),
524 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
527 let AddedComplexity = 20 in {
528 // MOVSSrm zeros the high parts of the register; represent this
529 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
530 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
531 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
532 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
533 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
534 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
535 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
537 // MOVSDrm zeros the high parts of the register; represent this
538 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
539 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
540 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
541 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
542 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
543 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
544 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
545 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
546 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
547 def : Pat<(v2f64 (X86vzload addr:$src)),
548 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
550 // Represent the same patterns above but in the form they appear for
552 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
553 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
554 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
555 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
556 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
557 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
558 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
559 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
560 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
562 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
563 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
564 (SUBREG_TO_REG (i32 0),
565 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
567 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
568 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
569 (SUBREG_TO_REG (i64 0),
570 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
572 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
573 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
574 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
576 // Move low f64 and clear high bits.
577 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
578 (SUBREG_TO_REG (i32 0),
579 (VMOVSDrr (v2f64 (V_SET0)),
580 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
582 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
583 (SUBREG_TO_REG (i32 0),
584 (VMOVSDrr (v2i64 (V_SET0)),
585 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
587 // Extract and store.
588 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
590 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
591 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
593 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
595 // Shuffle with VMOVSS
596 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
597 (VMOVSSrr (v4i32 VR128:$src1),
598 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
599 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
600 (VMOVSSrr (v4f32 VR128:$src1),
601 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
604 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
605 (SUBREG_TO_REG (i32 0),
606 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
607 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
609 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
610 (SUBREG_TO_REG (i32 0),
611 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
612 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
615 // Shuffle with VMOVSD
616 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
617 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
618 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
619 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
620 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
621 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
622 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
623 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
626 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
627 (SUBREG_TO_REG (i32 0),
628 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
629 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
631 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
634 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
638 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
639 // is during lowering, where it's not possible to recognize the fold cause
640 // it has two uses through a bitcast. One use disappears at isel time and the
641 // fold opportunity reappears.
642 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
643 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
644 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
646 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
648 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
649 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
652 let Predicates = [UseSSE1] in {
653 let AddedComplexity = 15 in {
654 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
655 // MOVSS to the lower bits.
656 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
657 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
658 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
659 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
660 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
661 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
664 let AddedComplexity = 20 in {
665 // MOVSSrm already zeros the high parts of the register.
666 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
667 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
668 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
669 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
670 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
671 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
674 // Extract and store.
675 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
677 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
679 // Shuffle with MOVSS
680 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
681 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
682 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
683 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
686 let Predicates = [UseSSE2] in {
687 let AddedComplexity = 15 in {
688 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
689 // MOVSD to the lower bits.
690 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
691 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
694 let AddedComplexity = 20 in {
695 // MOVSDrm already zeros the high parts of the register.
696 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
697 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
698 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
699 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
700 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
701 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
702 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
703 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
704 def : Pat<(v2f64 (X86vzload addr:$src)),
705 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
708 // Extract and store.
709 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
711 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
713 // Shuffle with MOVSD
714 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
715 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
717 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
719 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
720 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
721 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
723 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
724 // is during lowering, where it's not possible to recognize the fold cause
725 // it has two uses through a bitcast. One use disappears at isel time and the
726 // fold opportunity reappears.
727 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
728 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
729 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
730 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
731 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
732 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
733 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
734 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
737 //===----------------------------------------------------------------------===//
738 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
739 //===----------------------------------------------------------------------===//
741 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
742 X86MemOperand x86memop, PatFrag ld_frag,
743 string asm, Domain d,
745 bit IsReMaterializable = 1> {
746 let neverHasSideEffects = 1 in
747 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
748 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
749 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
750 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
751 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
752 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
755 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
756 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
758 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
759 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
761 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
762 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
764 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
765 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
768 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
769 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
771 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
772 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
773 TB, OpSize, VEX, VEX_L;
774 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
775 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
777 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
778 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
779 TB, OpSize, VEX, VEX_L;
780 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
781 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
783 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
784 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
786 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
787 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
789 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
790 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
793 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
794 "movaps\t{$src, $dst|$dst, $src}",
795 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
796 IIC_SSE_MOVA_P_MR>, VEX;
797 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
798 "movapd\t{$src, $dst|$dst, $src}",
799 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
800 IIC_SSE_MOVA_P_MR>, VEX;
801 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
802 "movups\t{$src, $dst|$dst, $src}",
803 [(store (v4f32 VR128:$src), addr:$dst)],
804 IIC_SSE_MOVU_P_MR>, VEX;
805 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
806 "movupd\t{$src, $dst|$dst, $src}",
807 [(store (v2f64 VR128:$src), addr:$dst)],
808 IIC_SSE_MOVU_P_MR>, VEX;
809 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
810 "movaps\t{$src, $dst|$dst, $src}",
811 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
812 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
813 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
814 "movapd\t{$src, $dst|$dst, $src}",
815 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
816 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
817 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
818 "movups\t{$src, $dst|$dst, $src}",
819 [(store (v8f32 VR256:$src), addr:$dst)],
820 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
821 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
822 "movupd\t{$src, $dst|$dst, $src}",
823 [(store (v4f64 VR256:$src), addr:$dst)],
824 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
827 let isCodeGenOnly = 1, hasSideEffects = 0 in {
828 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
830 "movaps\t{$src, $dst|$dst, $src}", [],
831 IIC_SSE_MOVA_P_RR>, VEX;
832 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
834 "movapd\t{$src, $dst|$dst, $src}", [],
835 IIC_SSE_MOVA_P_RR>, VEX;
836 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
838 "movups\t{$src, $dst|$dst, $src}", [],
839 IIC_SSE_MOVU_P_RR>, VEX;
840 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
842 "movupd\t{$src, $dst|$dst, $src}", [],
843 IIC_SSE_MOVU_P_RR>, VEX;
844 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
846 "movaps\t{$src, $dst|$dst, $src}", [],
847 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
848 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
850 "movapd\t{$src, $dst|$dst, $src}", [],
851 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
852 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
854 "movups\t{$src, $dst|$dst, $src}", [],
855 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
856 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
858 "movupd\t{$src, $dst|$dst, $src}", [],
859 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
862 let Predicates = [HasAVX] in {
863 def : Pat<(v8i32 (X86vzmovl
864 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
865 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
866 def : Pat<(v4i64 (X86vzmovl
867 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
868 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
869 def : Pat<(v8f32 (X86vzmovl
870 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
871 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
872 def : Pat<(v4f64 (X86vzmovl
873 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
874 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
878 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
879 (VMOVUPSYmr addr:$dst, VR256:$src)>;
880 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
881 (VMOVUPDYmr addr:$dst, VR256:$src)>;
883 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
887 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
891 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v4f32 VR128:$src), addr:$dst)],
895 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v2f64 VR128:$src), addr:$dst)],
901 let isCodeGenOnly = 1, hasSideEffects = 0 in {
902 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
903 "movaps\t{$src, $dst|$dst, $src}", [],
905 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
906 "movapd\t{$src, $dst|$dst, $src}", [],
908 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
909 "movups\t{$src, $dst|$dst, $src}", [],
911 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
912 "movupd\t{$src, $dst|$dst, $src}", [],
916 let Predicates = [HasAVX] in {
917 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
918 (VMOVUPSmr addr:$dst, VR128:$src)>;
919 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
920 (VMOVUPDmr addr:$dst, VR128:$src)>;
923 let Predicates = [UseSSE1] in
924 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
925 (MOVUPSmr addr:$dst, VR128:$src)>;
926 let Predicates = [UseSSE2] in
927 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
928 (MOVUPDmr addr:$dst, VR128:$src)>;
930 // Use vmovaps/vmovups for AVX integer load/store.
931 let Predicates = [HasAVX] in {
932 // 128-bit load/store
933 def : Pat<(alignedloadv2i64 addr:$src),
934 (VMOVAPSrm addr:$src)>;
935 def : Pat<(loadv2i64 addr:$src),
936 (VMOVUPSrm addr:$src)>;
938 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
939 (VMOVAPSmr addr:$dst, VR128:$src)>;
940 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
941 (VMOVAPSmr addr:$dst, VR128:$src)>;
942 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
943 (VMOVAPSmr addr:$dst, VR128:$src)>;
944 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
945 (VMOVAPSmr addr:$dst, VR128:$src)>;
946 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
947 (VMOVUPSmr addr:$dst, VR128:$src)>;
948 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
949 (VMOVUPSmr addr:$dst, VR128:$src)>;
950 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
951 (VMOVUPSmr addr:$dst, VR128:$src)>;
952 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
953 (VMOVUPSmr addr:$dst, VR128:$src)>;
955 // 256-bit load/store
956 def : Pat<(alignedloadv4i64 addr:$src),
957 (VMOVAPSYrm addr:$src)>;
958 def : Pat<(loadv4i64 addr:$src),
959 (VMOVUPSYrm addr:$src)>;
960 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
961 (VMOVAPSYmr addr:$dst, VR256:$src)>;
962 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
963 (VMOVAPSYmr addr:$dst, VR256:$src)>;
964 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
965 (VMOVAPSYmr addr:$dst, VR256:$src)>;
966 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
967 (VMOVAPSYmr addr:$dst, VR256:$src)>;
968 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
969 (VMOVUPSYmr addr:$dst, VR256:$src)>;
970 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
971 (VMOVUPSYmr addr:$dst, VR256:$src)>;
972 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
973 (VMOVUPSYmr addr:$dst, VR256:$src)>;
974 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
975 (VMOVUPSYmr addr:$dst, VR256:$src)>;
977 // Special patterns for storing subvector extracts of lower 128-bits
978 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
979 def : Pat<(alignedstore (v2f64 (extract_subvector
980 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
981 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
982 def : Pat<(alignedstore (v4f32 (extract_subvector
983 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
984 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
985 def : Pat<(alignedstore (v2i64 (extract_subvector
986 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
987 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
988 def : Pat<(alignedstore (v4i32 (extract_subvector
989 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
990 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
991 def : Pat<(alignedstore (v8i16 (extract_subvector
992 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
993 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
994 def : Pat<(alignedstore (v16i8 (extract_subvector
995 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
996 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
998 def : Pat<(store (v2f64 (extract_subvector
999 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1000 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1001 def : Pat<(store (v4f32 (extract_subvector
1002 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1003 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1004 def : Pat<(store (v2i64 (extract_subvector
1005 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1006 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1007 def : Pat<(store (v4i32 (extract_subvector
1008 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1009 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1010 def : Pat<(store (v8i16 (extract_subvector
1011 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1012 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1013 def : Pat<(store (v16i8 (extract_subvector
1014 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1015 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1018 // Use movaps / movups for SSE integer load / store (one byte shorter).
1019 // The instructions selected below are then converted to MOVDQA/MOVDQU
1020 // during the SSE domain pass.
1021 let Predicates = [UseSSE1] in {
1022 def : Pat<(alignedloadv2i64 addr:$src),
1023 (MOVAPSrm addr:$src)>;
1024 def : Pat<(loadv2i64 addr:$src),
1025 (MOVUPSrm addr:$src)>;
1027 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1028 (MOVAPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1030 (MOVAPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1032 (MOVAPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1034 (MOVAPSmr addr:$dst, VR128:$src)>;
1035 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1036 (MOVUPSmr addr:$dst, VR128:$src)>;
1037 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1038 (MOVUPSmr addr:$dst, VR128:$src)>;
1039 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1040 (MOVUPSmr addr:$dst, VR128:$src)>;
1041 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1042 (MOVUPSmr addr:$dst, VR128:$src)>;
1045 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1046 // bits are disregarded. FIXME: Set encoding to pseudo!
1047 let neverHasSideEffects = 1 in {
1048 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1049 "movaps\t{$src, $dst|$dst, $src}", [],
1050 IIC_SSE_MOVA_P_RR>, VEX;
1051 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1052 "movapd\t{$src, $dst|$dst, $src}", [],
1053 IIC_SSE_MOVA_P_RR>, VEX;
1054 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1055 "movaps\t{$src, $dst|$dst, $src}", [],
1057 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1058 "movapd\t{$src, $dst|$dst, $src}", [],
1062 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1063 // bits are disregarded. FIXME: Set encoding to pseudo!
1064 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1065 let isCodeGenOnly = 1 in {
1066 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1067 "movaps\t{$src, $dst|$dst, $src}",
1068 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1069 IIC_SSE_MOVA_P_RM>, VEX;
1070 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1071 "movapd\t{$src, $dst|$dst, $src}",
1072 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1073 IIC_SSE_MOVA_P_RM>, VEX;
1075 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1076 "movaps\t{$src, $dst|$dst, $src}",
1077 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1079 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1080 "movapd\t{$src, $dst|$dst, $src}",
1081 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1085 //===----------------------------------------------------------------------===//
1086 // SSE 1 & 2 - Move Low packed FP Instructions
1087 //===----------------------------------------------------------------------===//
1089 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1090 string base_opc, string asm_opr,
1091 InstrItinClass itin> {
1092 def PSrm : PI<opc, MRMSrcMem,
1093 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1094 !strconcat(base_opc, "s", asm_opr),
1096 (psnode VR128:$src1,
1097 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1098 itin, SSEPackedSingle>, TB;
1100 def PDrm : PI<opc, MRMSrcMem,
1101 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1102 !strconcat(base_opc, "d", asm_opr),
1103 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1104 (scalar_to_vector (loadf64 addr:$src2)))))],
1105 itin, SSEPackedDouble>, TB, OpSize;
1109 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1110 string base_opc, InstrItinClass itin> {
1111 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1112 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1115 let Constraints = "$src1 = $dst" in
1116 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1117 "\t{$src2, $dst|$dst, $src2}",
1121 let AddedComplexity = 20 in {
1122 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1126 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1127 "movlps\t{$src, $dst|$dst, $src}",
1128 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1129 (iPTR 0))), addr:$dst)],
1130 IIC_SSE_MOV_LH>, VEX;
1131 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1132 "movlpd\t{$src, $dst|$dst, $src}",
1133 [(store (f64 (vector_extract (v2f64 VR128:$src),
1134 (iPTR 0))), addr:$dst)],
1135 IIC_SSE_MOV_LH>, VEX;
1136 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1137 "movlps\t{$src, $dst|$dst, $src}",
1138 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1139 (iPTR 0))), addr:$dst)],
1141 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1142 "movlpd\t{$src, $dst|$dst, $src}",
1143 [(store (f64 (vector_extract (v2f64 VR128:$src),
1144 (iPTR 0))), addr:$dst)],
1147 let Predicates = [HasAVX] in {
1148 // Shuffle with VMOVLPS
1149 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1150 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1151 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1152 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1154 // Shuffle with VMOVLPD
1155 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1156 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1157 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1158 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1161 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1163 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1164 def : Pat<(store (v4i32 (X86Movlps
1165 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1166 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1167 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1169 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1170 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1172 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1175 let Predicates = [UseSSE1] in {
1176 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1177 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1178 (iPTR 0))), addr:$src1),
1179 (MOVLPSmr addr:$src1, VR128:$src2)>;
1181 // Shuffle with MOVLPS
1182 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1183 (MOVLPSrm VR128:$src1, addr:$src2)>;
1184 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1185 (MOVLPSrm VR128:$src1, addr:$src2)>;
1186 def : Pat<(X86Movlps VR128:$src1,
1187 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1188 (MOVLPSrm VR128:$src1, addr:$src2)>;
1191 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1193 (MOVLPSmr addr:$src1, VR128:$src2)>;
1194 def : Pat<(store (v4i32 (X86Movlps
1195 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1197 (MOVLPSmr addr:$src1, VR128:$src2)>;
1200 let Predicates = [UseSSE2] in {
1201 // Shuffle with MOVLPD
1202 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1203 (MOVLPDrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1205 (MOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1210 (MOVLPDmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1213 (MOVLPDmr addr:$src1, VR128:$src2)>;
1216 //===----------------------------------------------------------------------===//
1217 // SSE 1 & 2 - Move Hi packed FP Instructions
1218 //===----------------------------------------------------------------------===//
1220 let AddedComplexity = 20 in {
1221 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1225 // v2f64 extract element 1 is always custom lowered to unpack high to low
1226 // and extract element 0 so the non-store version isn't too horrible.
1227 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1228 "movhps\t{$src, $dst|$dst, $src}",
1229 [(store (f64 (vector_extract
1230 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1231 (bc_v2f64 (v4f32 VR128:$src))),
1232 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1233 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1234 "movhpd\t{$src, $dst|$dst, $src}",
1235 [(store (f64 (vector_extract
1236 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1237 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1238 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1239 "movhps\t{$src, $dst|$dst, $src}",
1240 [(store (f64 (vector_extract
1241 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1242 (bc_v2f64 (v4f32 VR128:$src))),
1243 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1244 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1245 "movhpd\t{$src, $dst|$dst, $src}",
1246 [(store (f64 (vector_extract
1247 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1248 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1250 let Predicates = [HasAVX] in {
1252 def : Pat<(X86Movlhps VR128:$src1,
1253 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1254 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlhps VR128:$src1,
1256 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1257 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1259 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1260 // is during lowering, where it's not possible to recognize the load fold
1261 // cause it has two uses through a bitcast. One use disappears at isel time
1262 // and the fold opportunity reappears.
1263 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1264 (scalar_to_vector (loadf64 addr:$src2)))),
1265 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1268 let Predicates = [UseSSE1] in {
1270 def : Pat<(X86Movlhps VR128:$src1,
1271 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1272 (MOVHPSrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(X86Movlhps VR128:$src1,
1274 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1275 (MOVHPSrm VR128:$src1, addr:$src2)>;
1278 let Predicates = [UseSSE2] in {
1279 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1280 // is during lowering, where it's not possible to recognize the load fold
1281 // cause it has two uses through a bitcast. One use disappears at isel time
1282 // and the fold opportunity reappears.
1283 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1284 (scalar_to_vector (loadf64 addr:$src2)))),
1285 (MOVHPDrm VR128:$src1, addr:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1294 (ins VR128:$src1, VR128:$src2),
1295 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1297 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1300 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1301 (ins VR128:$src1, VR128:$src2),
1302 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1304 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1308 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1309 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1310 (ins VR128:$src1, VR128:$src2),
1311 "movlhps\t{$src2, $dst|$dst, $src2}",
1313 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1315 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1316 (ins VR128:$src1, VR128:$src2),
1317 "movhlps\t{$src2, $dst|$dst, $src2}",
1319 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1323 let Predicates = [HasAVX] in {
1325 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1326 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1327 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1328 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1331 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1332 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1335 let Predicates = [UseSSE1] in {
1337 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1338 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1339 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1340 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1343 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1344 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1347 //===----------------------------------------------------------------------===//
1348 // SSE 1 & 2 - Conversion Instructions
1349 //===----------------------------------------------------------------------===//
1351 def SSE_CVT_PD : OpndItins<
1352 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1355 def SSE_CVT_PS : OpndItins<
1356 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1359 def SSE_CVT_Scalar : OpndItins<
1360 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1363 def SSE_CVT_SS2SI_32 : OpndItins<
1364 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1367 def SSE_CVT_SS2SI_64 : OpndItins<
1368 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1371 def SSE_CVT_SD2SI : OpndItins<
1372 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1375 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1376 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1377 string asm, OpndItins itins> {
1378 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1379 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1381 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1382 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1386 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1387 X86MemOperand x86memop, string asm, Domain d,
1389 let neverHasSideEffects = 1 in {
1390 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1393 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1398 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1399 X86MemOperand x86memop, string asm> {
1400 let neverHasSideEffects = 1 in {
1401 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1402 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1404 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1405 (ins DstRC:$src1, x86memop:$src),
1406 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1407 } // neverHasSideEffects = 1
1410 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1411 "cvttss2si\t{$src, $dst|$dst, $src}",
1414 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1415 "cvttss2si\t{$src, $dst|$dst, $src}",
1417 XS, VEX, VEX_W, VEX_LIG;
1418 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1419 "cvttsd2si\t{$src, $dst|$dst, $src}",
1422 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1423 "cvttsd2si\t{$src, $dst|$dst, $src}",
1425 XD, VEX, VEX_W, VEX_LIG;
1427 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1428 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1429 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1430 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1431 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1432 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1433 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1434 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1435 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1436 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1437 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1438 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1439 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1440 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1441 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1442 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1444 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1445 // register, but the same isn't true when only using memory operands,
1446 // provide other assembly "l" and "q" forms to address this explicitly
1447 // where appropriate to do so.
1448 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1449 XS, VEX_4V, VEX_LIG;
1450 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1451 XS, VEX_4V, VEX_W, VEX_LIG;
1452 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1453 XD, VEX_4V, VEX_LIG;
1454 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1455 XD, VEX_4V, VEX_W, VEX_LIG;
1457 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1458 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1459 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1460 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1462 let Predicates = [HasAVX] in {
1463 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1464 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1465 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1466 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1467 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1468 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1469 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1470 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1472 def : Pat<(f32 (sint_to_fp GR32:$src)),
1473 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1474 def : Pat<(f32 (sint_to_fp GR64:$src)),
1475 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1476 def : Pat<(f64 (sint_to_fp GR32:$src)),
1477 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1478 def : Pat<(f64 (sint_to_fp GR64:$src)),
1479 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1482 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1483 "cvttss2si\t{$src, $dst|$dst, $src}",
1484 SSE_CVT_SS2SI_32>, XS;
1485 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1486 "cvttss2si\t{$src, $dst|$dst, $src}",
1487 SSE_CVT_SS2SI_64>, XS, REX_W;
1488 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1489 "cvttsd2si\t{$src, $dst|$dst, $src}",
1491 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1492 "cvttsd2si\t{$src, $dst|$dst, $src}",
1493 SSE_CVT_SD2SI>, XD, REX_W;
1494 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1495 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1496 SSE_CVT_Scalar>, XS;
1497 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1498 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1499 SSE_CVT_Scalar>, XS, REX_W;
1500 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1501 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1502 SSE_CVT_Scalar>, XD;
1503 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1504 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1505 SSE_CVT_Scalar>, XD, REX_W;
1507 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1508 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1509 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1510 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1511 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1512 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1513 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1514 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1515 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1516 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1517 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1518 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1519 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1520 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1521 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1522 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1524 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1525 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1526 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1527 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1529 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1530 // and/or XMM operand(s).
1532 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1533 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1534 string asm, OpndItins itins> {
1535 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1536 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1537 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1538 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1540 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1543 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1544 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1545 PatFrag ld_frag, string asm, OpndItins itins,
1547 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1549 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1550 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1551 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1553 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1554 (ins DstRC:$src1, x86memop:$src2),
1556 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1557 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1558 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1562 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1563 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1564 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1565 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1566 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1567 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1569 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1570 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1571 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1572 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1575 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1576 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1577 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1578 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1579 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1580 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1582 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1583 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1584 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1585 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1586 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1587 SSE_CVT_Scalar, 0>, XD,
1590 let Constraints = "$src1 = $dst" in {
1591 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1592 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1593 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1594 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1595 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1596 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1597 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1598 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1599 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1600 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1601 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1602 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1607 // Aliases for intrinsics
1608 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1609 ssmem, sse_load_f32, "cvttss2si",
1610 SSE_CVT_SS2SI_32>, XS, VEX;
1611 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1612 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1613 "cvttss2si", SSE_CVT_SS2SI_64>,
1615 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1616 sdmem, sse_load_f64, "cvttsd2si",
1617 SSE_CVT_SD2SI>, XD, VEX;
1618 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1619 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1620 "cvttsd2si", SSE_CVT_SD2SI>,
1622 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1623 ssmem, sse_load_f32, "cvttss2si",
1624 SSE_CVT_SS2SI_32>, XS;
1625 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1626 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1627 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1628 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1629 sdmem, sse_load_f64, "cvttsd2si",
1631 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1632 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1633 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1635 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1636 ssmem, sse_load_f32, "cvtss2si",
1637 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1638 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1639 ssmem, sse_load_f32, "cvtss2si",
1640 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1642 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1643 ssmem, sse_load_f32, "cvtss2si",
1644 SSE_CVT_SS2SI_32>, XS;
1645 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1646 ssmem, sse_load_f32, "cvtss2si",
1647 SSE_CVT_SS2SI_64>, XS, REX_W;
1649 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1650 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1651 SSEPackedSingle, SSE_CVT_PS>,
1652 TB, VEX, Requires<[HasAVX]>;
1653 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1654 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1655 SSEPackedSingle, SSE_CVT_PS>,
1656 TB, VEX, VEX_L, Requires<[HasAVX]>;
1658 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1659 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1660 SSEPackedSingle, SSE_CVT_PS>,
1661 TB, Requires<[UseSSE2]>;
1663 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1664 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1665 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1666 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1667 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1668 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1669 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1670 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1671 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1672 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1673 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1674 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1675 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1676 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1677 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1678 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1680 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1681 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1682 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1683 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1684 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1685 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1686 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1687 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1688 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1689 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1690 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1691 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1692 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1693 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1694 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1695 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1699 // Convert scalar double to scalar single
1700 let neverHasSideEffects = 1 in {
1701 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1702 (ins FR64:$src1, FR64:$src2),
1703 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1704 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1706 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1707 (ins FR64:$src1, f64mem:$src2),
1708 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1709 [], IIC_SSE_CVT_Scalar_RM>,
1710 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1713 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1716 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1717 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1718 [(set FR32:$dst, (fround FR64:$src))],
1719 IIC_SSE_CVT_Scalar_RR>;
1720 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1721 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1722 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1723 IIC_SSE_CVT_Scalar_RM>,
1725 Requires<[UseSSE2, OptForSize]>;
1727 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1729 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1731 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1732 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1733 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1734 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1735 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1737 VR128:$src1, sse_load_f64:$src2))],
1738 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1740 let Constraints = "$src1 = $dst" in {
1741 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1742 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1743 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1745 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1746 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1747 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1749 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1750 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1751 VR128:$src1, sse_load_f64:$src2))],
1752 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1755 // Convert scalar single to scalar double
1756 // SSE2 instructions with XS prefix
1757 let neverHasSideEffects = 1 in {
1758 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1759 (ins FR32:$src1, FR32:$src2),
1760 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1761 [], IIC_SSE_CVT_Scalar_RR>,
1762 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1764 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1765 (ins FR32:$src1, f32mem:$src2),
1766 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1767 [], IIC_SSE_CVT_Scalar_RM>,
1768 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1771 def : Pat<(f64 (fextend FR32:$src)),
1772 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1773 def : Pat<(fextend (loadf32 addr:$src)),
1774 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1776 def : Pat<(extloadf32 addr:$src),
1777 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1778 Requires<[HasAVX, OptForSize]>;
1779 def : Pat<(extloadf32 addr:$src),
1780 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1781 Requires<[HasAVX, OptForSpeed]>;
1783 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1784 "cvtss2sd\t{$src, $dst|$dst, $src}",
1785 [(set FR64:$dst, (fextend FR32:$src))],
1786 IIC_SSE_CVT_Scalar_RR>, XS,
1787 Requires<[UseSSE2]>;
1788 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1789 "cvtss2sd\t{$src, $dst|$dst, $src}",
1790 [(set FR64:$dst, (extloadf32 addr:$src))],
1791 IIC_SSE_CVT_Scalar_RM>, XS,
1792 Requires<[UseSSE2, OptForSize]>;
1794 // extload f32 -> f64. This matches load+fextend because we have a hack in
1795 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1797 // Since these loads aren't folded into the fextend, we have to match it
1799 def : Pat<(fextend (loadf32 addr:$src)),
1800 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1801 def : Pat<(extloadf32 addr:$src),
1802 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1804 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1806 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1808 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1809 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1810 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1811 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1812 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1815 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1816 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1817 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1818 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1819 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1821 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1822 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1823 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1824 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1825 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1827 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1828 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1831 // Convert packed single/double fp to doubleword
1832 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1833 "cvtps2dq\t{$src, $dst|$dst, $src}",
1834 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1835 IIC_SSE_CVT_PS_RR>, VEX;
1836 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1837 "cvtps2dq\t{$src, $dst|$dst, $src}",
1839 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1840 IIC_SSE_CVT_PS_RM>, VEX;
1841 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1842 "cvtps2dq\t{$src, $dst|$dst, $src}",
1844 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1845 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1846 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1847 "cvtps2dq\t{$src, $dst|$dst, $src}",
1849 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1850 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1851 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 "cvtps2dq\t{$src, $dst|$dst, $src}",
1853 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1855 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1856 "cvtps2dq\t{$src, $dst|$dst, $src}",
1858 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1862 // Convert Packed Double FP to Packed DW Integers
1863 let Predicates = [HasAVX] in {
1864 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1865 // register, but the same isn't true when using memory operands instead.
1866 // Provide other assembly rr and rm forms to address this explicitly.
1867 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1868 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1873 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1874 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1875 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1876 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1878 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1881 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1882 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1884 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1885 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1886 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1888 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1890 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1891 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1894 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1895 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1897 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1899 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1904 // Convert with truncation packed single/double fp to doubleword
1905 // SSE2 packed instructions with XS prefix
1906 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1907 "cvttps2dq\t{$src, $dst|$dst, $src}",
1909 (int_x86_sse2_cvttps2dq VR128:$src))],
1910 IIC_SSE_CVT_PS_RR>, VEX;
1911 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1912 "cvttps2dq\t{$src, $dst|$dst, $src}",
1913 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1914 (memopv4f32 addr:$src)))],
1915 IIC_SSE_CVT_PS_RM>, VEX;
1916 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1917 "cvttps2dq\t{$src, $dst|$dst, $src}",
1919 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1920 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1921 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1922 "cvttps2dq\t{$src, $dst|$dst, $src}",
1923 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1924 (memopv8f32 addr:$src)))],
1925 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1927 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1928 "cvttps2dq\t{$src, $dst|$dst, $src}",
1929 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1931 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1932 "cvttps2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1937 let Predicates = [HasAVX] in {
1938 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1939 (VCVTDQ2PSrr VR128:$src)>;
1940 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1941 (VCVTDQ2PSrm addr:$src)>;
1943 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1944 (VCVTDQ2PSrr VR128:$src)>;
1945 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1946 (VCVTDQ2PSrm addr:$src)>;
1948 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1949 (VCVTTPS2DQrr VR128:$src)>;
1950 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1951 (VCVTTPS2DQrm addr:$src)>;
1953 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1954 (VCVTDQ2PSYrr VR256:$src)>;
1955 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1956 (VCVTDQ2PSYrm addr:$src)>;
1958 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1959 (VCVTTPS2DQYrr VR256:$src)>;
1960 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1961 (VCVTTPS2DQYrm addr:$src)>;
1964 let Predicates = [UseSSE2] in {
1965 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1966 (CVTDQ2PSrr VR128:$src)>;
1967 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1968 (CVTDQ2PSrm addr:$src)>;
1970 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1971 (CVTDQ2PSrr VR128:$src)>;
1972 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1973 (CVTDQ2PSrm addr:$src)>;
1975 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1976 (CVTTPS2DQrr VR128:$src)>;
1977 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1978 (CVTTPS2DQrm addr:$src)>;
1981 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1982 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_sse2_cvttpd2dq VR128:$src))],
1985 IIC_SSE_CVT_PD_RR>, VEX;
1987 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1988 // register, but the same isn't true when using memory operands instead.
1989 // Provide other assembly rr and rm forms to address this explicitly.
1992 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1993 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1994 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1995 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1996 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1997 (memopv2f64 addr:$src)))],
1998 IIC_SSE_CVT_PD_RM>, VEX;
2001 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2002 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2004 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2005 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2006 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2007 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2009 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2010 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2011 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2012 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2014 let Predicates = [HasAVX] in {
2015 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2016 (VCVTTPD2DQYrr VR256:$src)>;
2017 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2018 (VCVTTPD2DQYrm addr:$src)>;
2019 } // Predicates = [HasAVX]
2021 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2022 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2023 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2025 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2026 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2027 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2028 (memopv2f64 addr:$src)))],
2031 // Convert packed single to packed double
2032 let Predicates = [HasAVX] in {
2033 // SSE2 instructions without OpSize prefix
2034 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2035 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2036 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2037 IIC_SSE_CVT_PD_RR>, TB, VEX;
2038 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2039 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2040 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2041 IIC_SSE_CVT_PD_RM>, TB, VEX;
2042 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2043 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2045 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2046 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
2047 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2048 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2050 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2051 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2054 let Predicates = [UseSSE2] in {
2055 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2056 "cvtps2pd\t{$src, $dst|$dst, $src}",
2057 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2058 IIC_SSE_CVT_PD_RR>, TB;
2059 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2060 "cvtps2pd\t{$src, $dst|$dst, $src}",
2061 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2062 IIC_SSE_CVT_PD_RM>, TB;
2065 // Convert Packed DW Integers to Packed Double FP
2066 let Predicates = [HasAVX] in {
2067 let neverHasSideEffects = 1, mayLoad = 1 in
2068 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2069 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2071 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2072 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2074 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2075 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2076 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2078 (int_x86_avx_cvtdq2_pd_256
2079 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2080 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2081 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2083 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2086 let neverHasSideEffects = 1, mayLoad = 1 in
2087 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2088 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2090 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2091 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2092 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2095 // AVX 256-bit register conversion intrinsics
2096 let Predicates = [HasAVX] in {
2097 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2098 (VCVTDQ2PDYrr VR128:$src)>;
2099 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2100 (VCVTDQ2PDYrm addr:$src)>;
2101 } // Predicates = [HasAVX]
2103 // Convert packed double to packed single
2104 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2105 // register, but the same isn't true when using memory operands instead.
2106 // Provide other assembly rr and rm forms to address this explicitly.
2107 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2110 IIC_SSE_CVT_PD_RR>, VEX;
2113 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2114 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2115 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2116 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2118 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2119 IIC_SSE_CVT_PD_RM>, VEX;
2122 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2123 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2125 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2126 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2127 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2128 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2130 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2131 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2132 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2133 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2135 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2136 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2137 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2139 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2140 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2142 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2146 // AVX 256-bit register conversion intrinsics
2147 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2148 // whenever possible to avoid declaring two versions of each one.
2149 let Predicates = [HasAVX] in {
2150 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2151 (VCVTDQ2PSYrr VR256:$src)>;
2152 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2153 (VCVTDQ2PSYrm addr:$src)>;
2155 // Match fround and fextend for 128/256-bit conversions
2156 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2157 (VCVTPD2PSrr VR128:$src)>;
2158 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2159 (VCVTPD2PSXrm addr:$src)>;
2160 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2161 (VCVTPD2PSYrr VR256:$src)>;
2162 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2163 (VCVTPD2PSYrm addr:$src)>;
2165 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2166 (VCVTPS2PDrr VR128:$src)>;
2167 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2168 (VCVTPS2PDYrr VR128:$src)>;
2169 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2170 (VCVTPS2PDYrm addr:$src)>;
2173 let Predicates = [UseSSE2] in {
2174 // Match fround and fextend for 128 conversions
2175 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2176 (CVTPD2PSrr VR128:$src)>;
2177 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2178 (CVTPD2PSrm addr:$src)>;
2180 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2181 (CVTPS2PDrr VR128:$src)>;
2184 //===----------------------------------------------------------------------===//
2185 // SSE 1 & 2 - Compare Instructions
2186 //===----------------------------------------------------------------------===//
2188 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2189 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2190 Operand CC, SDNode OpNode, ValueType VT,
2191 PatFrag ld_frag, string asm, string asm_alt,
2193 def rr : SIi8<0xC2, MRMSrcReg,
2194 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2195 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2197 def rm : SIi8<0xC2, MRMSrcMem,
2198 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2199 [(set RC:$dst, (OpNode (VT RC:$src1),
2200 (ld_frag addr:$src2), imm:$cc))],
2203 // Accept explicit immediate argument form instead of comparison code.
2204 let neverHasSideEffects = 1 in {
2205 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2206 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2207 IIC_SSE_ALU_F32S_RR>;
2209 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2210 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2211 IIC_SSE_ALU_F32S_RM>;
2215 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2216 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2217 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2219 XS, VEX_4V, VEX_LIG;
2220 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2221 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2222 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2223 SSE_ALU_F32S>, // same latency as 32 bit compare
2224 XD, VEX_4V, VEX_LIG;
2226 let Constraints = "$src1 = $dst" in {
2227 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2228 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2229 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2231 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2232 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2233 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2234 SSE_ALU_F32S>, // same latency as 32 bit compare
2238 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2239 Intrinsic Int, string asm, OpndItins itins> {
2240 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2241 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2242 [(set VR128:$dst, (Int VR128:$src1,
2243 VR128:$src, imm:$cc))],
2245 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2246 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2247 [(set VR128:$dst, (Int VR128:$src1,
2248 (load addr:$src), imm:$cc))],
2252 // Aliases to match intrinsics which expect XMM operand(s).
2253 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2254 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2257 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2258 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2259 SSE_ALU_F32S>, // same latency as f32
2261 let Constraints = "$src1 = $dst" in {
2262 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2263 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2265 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2266 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2267 SSE_ALU_F32S>, // same latency as f32
2272 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2273 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2274 ValueType vt, X86MemOperand x86memop,
2275 PatFrag ld_frag, string OpcodeStr, Domain d> {
2276 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2277 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2278 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2279 IIC_SSE_COMIS_RR, d>;
2280 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2281 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2282 [(set EFLAGS, (OpNode (vt RC:$src1),
2283 (ld_frag addr:$src2)))],
2284 IIC_SSE_COMIS_RM, d>;
2287 let Defs = [EFLAGS] in {
2288 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2289 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2290 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2291 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2293 let Pattern = []<dag> in {
2294 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2295 "comiss", SSEPackedSingle>, TB, VEX,
2297 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2298 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2302 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2303 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2304 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2305 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2307 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2308 load, "comiss", SSEPackedSingle>, TB, VEX;
2309 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2310 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2311 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2312 "ucomiss", SSEPackedSingle>, TB;
2313 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2314 "ucomisd", SSEPackedDouble>, TB, OpSize;
2316 let Pattern = []<dag> in {
2317 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2318 "comiss", SSEPackedSingle>, TB;
2319 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2320 "comisd", SSEPackedDouble>, TB, OpSize;
2323 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2324 load, "ucomiss", SSEPackedSingle>, TB;
2325 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2326 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2328 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2329 "comiss", SSEPackedSingle>, TB;
2330 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2331 "comisd", SSEPackedDouble>, TB, OpSize;
2332 } // Defs = [EFLAGS]
2334 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2335 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2336 Operand CC, Intrinsic Int, string asm,
2337 string asm_alt, Domain d> {
2338 def rri : PIi8<0xC2, MRMSrcReg,
2339 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2340 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2341 IIC_SSE_CMPP_RR, d>;
2342 def rmi : PIi8<0xC2, MRMSrcMem,
2343 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2344 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2345 IIC_SSE_CMPP_RM, d>;
2347 // Accept explicit immediate argument form instead of comparison code.
2348 let neverHasSideEffects = 1 in {
2349 def rri_alt : PIi8<0xC2, MRMSrcReg,
2350 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2351 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2352 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2353 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2354 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2358 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2359 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2360 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2361 SSEPackedSingle>, TB, VEX_4V;
2362 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2363 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2364 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2365 SSEPackedDouble>, TB, OpSize, VEX_4V;
2366 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2367 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2368 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2369 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2370 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2371 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2372 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2373 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2374 let Constraints = "$src1 = $dst" in {
2375 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2376 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2377 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2378 SSEPackedSingle>, TB;
2379 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2380 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2381 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2382 SSEPackedDouble>, TB, OpSize;
2385 let Predicates = [HasAVX] in {
2386 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2387 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2388 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2389 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2390 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2391 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2392 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2393 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2395 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2396 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2397 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2398 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2399 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2400 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2401 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2402 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2405 let Predicates = [UseSSE1] in {
2406 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2407 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2408 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2409 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2412 let Predicates = [UseSSE2] in {
2413 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2414 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2415 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2416 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2419 //===----------------------------------------------------------------------===//
2420 // SSE 1 & 2 - Shuffle Instructions
2421 //===----------------------------------------------------------------------===//
2423 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2424 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2425 ValueType vt, string asm, PatFrag mem_frag,
2426 Domain d, bit IsConvertibleToThreeAddress = 0> {
2427 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2428 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2429 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2430 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2431 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2432 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2433 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2434 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2435 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2438 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2439 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2440 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2441 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2442 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2443 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2444 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2445 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2446 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2447 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2448 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2449 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2451 let Constraints = "$src1 = $dst" in {
2452 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2453 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2454 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2456 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2457 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2458 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2462 let Predicates = [HasAVX] in {
2463 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2464 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2465 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2466 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2467 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2469 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2470 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2471 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2472 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2473 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2476 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2477 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2478 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2479 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2480 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2482 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2483 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2484 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2485 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2486 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2489 let Predicates = [UseSSE1] in {
2490 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2491 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2492 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2493 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2494 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2497 let Predicates = [UseSSE2] in {
2498 // Generic SHUFPD patterns
2499 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2500 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2501 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2502 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2503 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2506 //===----------------------------------------------------------------------===//
2507 // SSE 1 & 2 - Unpack Instructions
2508 //===----------------------------------------------------------------------===//
2510 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2511 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2512 PatFrag mem_frag, RegisterClass RC,
2513 X86MemOperand x86memop, string asm,
2515 def rr : PI<opc, MRMSrcReg,
2516 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2518 (vt (OpNode RC:$src1, RC:$src2)))],
2520 def rm : PI<opc, MRMSrcMem,
2521 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2523 (vt (OpNode RC:$src1,
2524 (mem_frag addr:$src2))))],
2528 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2529 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2530 SSEPackedSingle>, TB, VEX_4V;
2531 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2532 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 SSEPackedDouble>, TB, OpSize, VEX_4V;
2534 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2535 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 SSEPackedSingle>, TB, VEX_4V;
2537 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2538 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2539 SSEPackedDouble>, TB, OpSize, VEX_4V;
2541 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2542 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2543 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2544 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2545 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2546 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2547 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2548 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2549 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2550 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2551 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2552 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2554 let Constraints = "$src1 = $dst" in {
2555 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2556 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2557 SSEPackedSingle>, TB;
2558 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2559 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2560 SSEPackedDouble>, TB, OpSize;
2561 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2562 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2563 SSEPackedSingle>, TB;
2564 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2565 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2566 SSEPackedDouble>, TB, OpSize;
2567 } // Constraints = "$src1 = $dst"
2569 let Predicates = [HasAVX1Only] in {
2570 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2571 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2572 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2573 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2574 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2575 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2576 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2577 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2579 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2580 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2581 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2582 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2583 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2584 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2585 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2586 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2589 let Predicates = [HasAVX] in {
2590 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2591 // problem is during lowering, where it's not possible to recognize the load
2592 // fold cause it has two uses through a bitcast. One use disappears at isel
2593 // time and the fold opportunity reappears.
2594 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2595 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2598 let Predicates = [UseSSE2] in {
2599 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2600 // problem is during lowering, where it's not possible to recognize the load
2601 // fold cause it has two uses through a bitcast. One use disappears at isel
2602 // time and the fold opportunity reappears.
2603 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2604 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2607 //===----------------------------------------------------------------------===//
2608 // SSE 1 & 2 - Extract Floating-Point Sign mask
2609 //===----------------------------------------------------------------------===//
2611 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2612 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2614 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2615 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2616 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2617 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2618 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2619 IIC_SSE_MOVMSK, d>, REX_W;
2622 let Predicates = [HasAVX] in {
2623 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2624 "movmskps", SSEPackedSingle>, TB, VEX;
2625 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2626 "movmskpd", SSEPackedDouble>, TB,
2628 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2629 "movmskps", SSEPackedSingle>, TB,
2631 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2632 "movmskpd", SSEPackedDouble>, TB,
2635 def : Pat<(i32 (X86fgetsign FR32:$src)),
2636 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2637 def : Pat<(i64 (X86fgetsign FR32:$src)),
2638 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2639 def : Pat<(i32 (X86fgetsign FR64:$src)),
2640 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2641 def : Pat<(i64 (X86fgetsign FR64:$src)),
2642 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2645 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2646 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2647 SSEPackedSingle>, TB, VEX;
2648 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2649 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2650 SSEPackedDouble>, TB,
2652 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2653 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2654 SSEPackedSingle>, TB, VEX, VEX_L;
2655 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2656 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2657 SSEPackedDouble>, TB,
2661 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2662 SSEPackedSingle>, TB;
2663 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2664 SSEPackedDouble>, TB, OpSize;
2666 def : Pat<(i32 (X86fgetsign FR32:$src)),
2667 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2668 Requires<[UseSSE1]>;
2669 def : Pat<(i64 (X86fgetsign FR32:$src)),
2670 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2671 Requires<[UseSSE1]>;
2672 def : Pat<(i32 (X86fgetsign FR64:$src)),
2673 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2674 Requires<[UseSSE2]>;
2675 def : Pat<(i64 (X86fgetsign FR64:$src)),
2676 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2677 Requires<[UseSSE2]>;
2679 //===---------------------------------------------------------------------===//
2680 // SSE2 - Packed Integer Logical Instructions
2681 //===---------------------------------------------------------------------===//
2683 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2685 /// PDI_binop_rm - Simple SSE2 binary operator.
2686 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2687 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2688 X86MemOperand x86memop, OpndItins itins,
2689 bit IsCommutable, bit Is2Addr> {
2690 let isCommutable = IsCommutable in
2691 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2692 (ins RC:$src1, RC:$src2),
2694 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2695 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2696 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2697 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2698 (ins RC:$src1, x86memop:$src2),
2700 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2702 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2703 (bitconvert (memop_frag addr:$src2)))))],
2706 } // ExeDomain = SSEPackedInt
2708 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2709 ValueType OpVT128, ValueType OpVT256,
2710 OpndItins itins, bit IsCommutable = 0> {
2711 let Predicates = [HasAVX] in
2712 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2713 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2715 let Constraints = "$src1 = $dst" in
2716 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2717 memopv2i64, i128mem, itins, IsCommutable, 1>;
2719 let Predicates = [HasAVX2] in
2720 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2721 OpVT256, VR256, memopv4i64, i256mem, itins,
2722 IsCommutable, 0>, VEX_4V, VEX_L;
2725 // These are ordered here for pattern ordering requirements with the fp versions
2727 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2728 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2729 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2730 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2731 SSE_BIT_ITINS_P, 0>;
2733 //===----------------------------------------------------------------------===//
2734 // SSE 1 & 2 - Logical Instructions
2735 //===----------------------------------------------------------------------===//
2737 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2739 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2740 SDNode OpNode, OpndItins itins> {
2741 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2742 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2745 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2746 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2749 let Constraints = "$src1 = $dst" in {
2750 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2751 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2754 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2755 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2760 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2761 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2763 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2765 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2768 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2769 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2772 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2774 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2776 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2777 !strconcat(OpcodeStr, "ps"), f256mem,
2778 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2779 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2780 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2782 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2783 !strconcat(OpcodeStr, "pd"), f256mem,
2784 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2785 (bc_v4i64 (v4f64 VR256:$src2))))],
2786 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2787 (memopv4i64 addr:$src2)))], 0>,
2788 TB, OpSize, VEX_4V, VEX_L;
2790 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2791 // are all promoted to v2i64, and the patterns are covered by the int
2792 // version. This is needed in SSE only, because v2i64 isn't supported on
2793 // SSE1, but only on SSE2.
2794 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2795 !strconcat(OpcodeStr, "ps"), f128mem, [],
2796 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2797 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2799 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2800 !strconcat(OpcodeStr, "pd"), f128mem,
2801 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2802 (bc_v2i64 (v2f64 VR128:$src2))))],
2803 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2804 (memopv2i64 addr:$src2)))], 0>,
2807 let Constraints = "$src1 = $dst" in {
2808 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2809 !strconcat(OpcodeStr, "ps"), f128mem,
2810 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2811 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2812 (memopv2i64 addr:$src2)))]>, TB;
2814 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2815 !strconcat(OpcodeStr, "pd"), f128mem,
2816 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2817 (bc_v2i64 (v2f64 VR128:$src2))))],
2818 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2819 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2823 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2824 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2825 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2826 let isCommutable = 0 in
2827 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2829 //===----------------------------------------------------------------------===//
2830 // SSE 1 & 2 - Arithmetic Instructions
2831 //===----------------------------------------------------------------------===//
2833 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2836 /// In addition, we also have a special variant of the scalar form here to
2837 /// represent the associated intrinsic operation. This form is unlike the
2838 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2839 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2841 /// These three forms can each be reg+reg or reg+mem.
2844 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2846 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2849 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2850 OpNode, FR32, f32mem,
2851 itins.s, Is2Addr>, XS;
2852 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2853 OpNode, FR64, f64mem,
2854 itins.d, Is2Addr>, XD;
2857 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2858 SDNode OpNode, SizeItins itins> {
2859 let Predicates = [HasAVX] in {
2860 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2861 VR128, v4f32, f128mem, memopv4f32,
2862 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2863 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2864 VR128, v2f64, f128mem, memopv2f64,
2865 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2867 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2868 OpNode, VR256, v8f32, f256mem, memopv8f32,
2869 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2870 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2871 OpNode, VR256, v4f64, f256mem, memopv4f64,
2872 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2875 let Constraints = "$src1 = $dst" in {
2876 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2877 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2879 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2880 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2881 itins.d, 1>, TB, OpSize;
2885 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2888 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2889 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2890 itins.s, Is2Addr>, XS;
2891 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2892 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2893 itins.d, Is2Addr>, XD;
2896 // Binary Arithmetic instructions
2897 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
2898 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
2899 let isCommutable = 0 in {
2900 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
2901 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
2902 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
2903 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
2906 let isCodeGenOnly = 1 in {
2907 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2908 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2911 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2912 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2914 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2915 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2918 let isCommutable = 0 in {
2919 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2920 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2922 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2923 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2925 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2926 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2928 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2929 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2933 let Constraints = "$src1 = $dst" in {
2934 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2935 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2936 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2937 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2939 let isCommutable = 0 in {
2940 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2941 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2942 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2943 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2944 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2945 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
2946 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2947 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
2951 let isCodeGenOnly = 1 in {
2952 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2954 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2956 let Constraints = "$src1 = $dst" in {
2957 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
2958 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
2963 /// In addition, we also have a special variant of the scalar form here to
2964 /// represent the associated intrinsic operation. This form is unlike the
2965 /// plain scalar form, in that it takes an entire vector (instead of a
2966 /// scalar) and leaves the top elements undefined.
2968 /// And, we have a special variant form for a full-vector intrinsic form.
2970 def SSE_SQRTP : OpndItins<
2971 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2974 def SSE_SQRTS : OpndItins<
2975 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2978 def SSE_RCPP : OpndItins<
2979 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2982 def SSE_RCPS : OpndItins<
2983 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2986 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2987 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2988 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2989 let Predicates = [HasAVX], hasSideEffects = 0 in {
2990 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
2991 (ins FR32:$src1, FR32:$src2),
2992 !strconcat("v", OpcodeStr,
2993 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2994 []>, VEX_4V, VEX_LIG;
2995 let mayLoad = 1 in {
2996 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
2997 (ins FR32:$src1,f32mem:$src2),
2998 !strconcat("v", OpcodeStr,
2999 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3000 []>, VEX_4V, VEX_LIG;
3001 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3002 (ins VR128:$src1, ssmem:$src2),
3003 !strconcat("v", OpcodeStr,
3004 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3005 []>, VEX_4V, VEX_LIG;
3009 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3010 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3011 [(set FR32:$dst, (OpNode FR32:$src))]>;
3012 // For scalar unary operations, fold a load into the operation
3013 // only in OptForSize mode. It eliminates an instruction, but it also
3014 // eliminates a whole-register clobber (the load), so it introduces a
3015 // partial register update condition.
3016 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3017 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3018 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3019 Requires<[UseSSE1, OptForSize]>;
3020 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3021 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3022 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3023 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3024 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3025 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3028 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3029 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3031 let Predicates = [HasAVX], hasSideEffects = 0 in {
3032 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3033 (ins FR32:$src1, FR32:$src2),
3034 !strconcat("v", OpcodeStr,
3035 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3036 []>, VEX_4V, VEX_LIG;
3037 let mayLoad = 1 in {
3038 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3039 (ins FR32:$src1,f32mem:$src2),
3040 !strconcat("v", OpcodeStr,
3041 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3042 []>, VEX_4V, VEX_LIG;
3043 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3044 (ins VR128:$src1, ssmem:$src2),
3045 !strconcat("v", OpcodeStr,
3046 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3047 []>, VEX_4V, VEX_LIG;
3051 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3052 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3053 [(set FR32:$dst, (OpNode FR32:$src))]>;
3054 // For scalar unary operations, fold a load into the operation
3055 // only in OptForSize mode. It eliminates an instruction, but it also
3056 // eliminates a whole-register clobber (the load), so it introduces a
3057 // partial register update condition.
3058 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3059 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3060 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3061 Requires<[UseSSE1, OptForSize]>;
3062 let Constraints = "$src1 = $dst" in {
3063 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3064 (ins VR128:$src1, VR128:$src2),
3065 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3067 let mayLoad = 1, hasSideEffects = 0 in
3068 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3069 (ins VR128:$src1, ssmem:$src2),
3070 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3075 /// sse1_fp_unop_p - SSE1 unops in packed form.
3076 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3078 let Predicates = [HasAVX] in {
3079 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3080 !strconcat("v", OpcodeStr,
3081 "ps\t{$src, $dst|$dst, $src}"),
3082 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3084 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3085 !strconcat("v", OpcodeStr,
3086 "ps\t{$src, $dst|$dst, $src}"),
3087 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3089 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3090 !strconcat("v", OpcodeStr,
3091 "ps\t{$src, $dst|$dst, $src}"),
3092 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3093 itins.rr>, VEX, VEX_L;
3094 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3095 !strconcat("v", OpcodeStr,
3096 "ps\t{$src, $dst|$dst, $src}"),
3097 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3098 itins.rm>, VEX, VEX_L;
3101 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3102 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3103 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3104 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3105 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3106 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3109 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3110 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3111 Intrinsic V4F32Int, Intrinsic V8F32Int,
3113 let Predicates = [HasAVX] in {
3114 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3115 !strconcat("v", OpcodeStr,
3116 "ps\t{$src, $dst|$dst, $src}"),
3117 [(set VR128:$dst, (V4F32Int VR128:$src))],
3119 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3120 !strconcat("v", OpcodeStr,
3121 "ps\t{$src, $dst|$dst, $src}"),
3122 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3124 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3125 !strconcat("v", OpcodeStr,
3126 "ps\t{$src, $dst|$dst, $src}"),
3127 [(set VR256:$dst, (V8F32Int VR256:$src))],
3128 itins.rr>, VEX, VEX_L;
3129 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3131 !strconcat("v", OpcodeStr,
3132 "ps\t{$src, $dst|$dst, $src}"),
3133 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3134 itins.rm>, VEX, VEX_L;
3137 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3138 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3139 [(set VR128:$dst, (V4F32Int VR128:$src))],
3141 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3142 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3143 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3147 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3148 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3149 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3150 let Predicates = [HasAVX], hasSideEffects = 0 in {
3151 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3152 (ins FR64:$src1, FR64:$src2),
3153 !strconcat("v", OpcodeStr,
3154 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3155 []>, VEX_4V, VEX_LIG;
3156 let mayLoad = 1 in {
3157 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3158 (ins FR64:$src1,f64mem:$src2),
3159 !strconcat("v", OpcodeStr,
3160 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3161 []>, VEX_4V, VEX_LIG;
3162 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3163 (ins VR128:$src1, sdmem:$src2),
3164 !strconcat("v", OpcodeStr,
3165 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3166 []>, VEX_4V, VEX_LIG;
3170 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3171 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3172 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3173 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3174 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3175 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3176 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3177 Requires<[UseSSE2, OptForSize]>;
3178 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3179 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3180 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3181 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3182 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3183 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3186 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3187 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3188 SDNode OpNode, OpndItins itins> {
3189 let Predicates = [HasAVX] in {
3190 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3191 !strconcat("v", OpcodeStr,
3192 "pd\t{$src, $dst|$dst, $src}"),
3193 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3195 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3196 !strconcat("v", OpcodeStr,
3197 "pd\t{$src, $dst|$dst, $src}"),
3198 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3200 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3201 !strconcat("v", OpcodeStr,
3202 "pd\t{$src, $dst|$dst, $src}"),
3203 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3204 itins.rr>, VEX, VEX_L;
3205 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3206 !strconcat("v", OpcodeStr,
3207 "pd\t{$src, $dst|$dst, $src}"),
3208 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3209 itins.rm>, VEX, VEX_L;
3212 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3213 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3214 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3215 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3216 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3217 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3221 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3223 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
3224 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3226 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
3228 // Reciprocal approximations. Note that these typically require refinement
3229 // in order to obtain suitable precision.
3230 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3231 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
3232 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3233 int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;
3234 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3235 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3236 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3237 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3239 def : Pat<(f32 (fsqrt FR32:$src)),
3240 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3241 def : Pat<(f32 (fsqrt (load addr:$src))),
3242 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3243 Requires<[HasAVX, OptForSize]>;
3244 def : Pat<(f64 (fsqrt FR64:$src)),
3245 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3246 def : Pat<(f64 (fsqrt (load addr:$src))),
3247 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3248 Requires<[HasAVX, OptForSize]>;
3250 def : Pat<(f32 (X86frsqrt FR32:$src)),
3251 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3252 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3253 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3254 Requires<[HasAVX, OptForSize]>;
3256 def : Pat<(f32 (X86frcp FR32:$src)),
3257 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3258 def : Pat<(f32 (X86frcp (load addr:$src))),
3259 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3260 Requires<[HasAVX, OptForSize]>;
3262 let Predicates = [HasAVX] in {
3263 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3264 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3265 (COPY_TO_REGCLASS VR128:$src, FR32)),
3267 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3268 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3270 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3271 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3272 (COPY_TO_REGCLASS VR128:$src, FR64)),
3274 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3275 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3277 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3278 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3279 (COPY_TO_REGCLASS VR128:$src, FR32)),
3281 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3282 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3284 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3285 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3286 (COPY_TO_REGCLASS VR128:$src, FR32)),
3288 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3289 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3292 // Reciprocal approximations. Note that these typically require refinement
3293 // in order to obtain suitable precision.
3294 let Predicates = [UseSSE1] in {
3295 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3296 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3297 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3298 (RCPSSr_Int VR128:$src, VR128:$src)>;
3301 // There is no f64 version of the reciprocal approximation instructions.
3303 //===----------------------------------------------------------------------===//
3304 // SSE 1 & 2 - Non-temporal stores
3305 //===----------------------------------------------------------------------===//
3307 let AddedComplexity = 400 in { // Prefer non-temporal versions
3308 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3309 (ins f128mem:$dst, VR128:$src),
3310 "movntps\t{$src, $dst|$dst, $src}",
3311 [(alignednontemporalstore (v4f32 VR128:$src),
3313 IIC_SSE_MOVNT>, VEX;
3314 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3315 (ins f128mem:$dst, VR128:$src),
3316 "movntpd\t{$src, $dst|$dst, $src}",
3317 [(alignednontemporalstore (v2f64 VR128:$src),
3319 IIC_SSE_MOVNT>, VEX;
3321 let ExeDomain = SSEPackedInt in
3322 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3323 (ins f128mem:$dst, VR128:$src),
3324 "movntdq\t{$src, $dst|$dst, $src}",
3325 [(alignednontemporalstore (v2i64 VR128:$src),
3327 IIC_SSE_MOVNT>, VEX;
3329 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3330 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3332 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3333 (ins f256mem:$dst, VR256:$src),
3334 "movntps\t{$src, $dst|$dst, $src}",
3335 [(alignednontemporalstore (v8f32 VR256:$src),
3337 IIC_SSE_MOVNT>, VEX, VEX_L;
3338 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3339 (ins f256mem:$dst, VR256:$src),
3340 "movntpd\t{$src, $dst|$dst, $src}",
3341 [(alignednontemporalstore (v4f64 VR256:$src),
3343 IIC_SSE_MOVNT>, VEX, VEX_L;
3344 let ExeDomain = SSEPackedInt in
3345 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3346 (ins f256mem:$dst, VR256:$src),
3347 "movntdq\t{$src, $dst|$dst, $src}",
3348 [(alignednontemporalstore (v4i64 VR256:$src),
3350 IIC_SSE_MOVNT>, VEX, VEX_L;
3353 let AddedComplexity = 400 in { // Prefer non-temporal versions
3354 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3355 "movntps\t{$src, $dst|$dst, $src}",
3356 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3358 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3359 "movntpd\t{$src, $dst|$dst, $src}",
3360 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3363 let ExeDomain = SSEPackedInt in
3364 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3365 "movntdq\t{$src, $dst|$dst, $src}",
3366 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3369 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3370 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3372 // There is no AVX form for instructions below this point
3373 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3374 "movnti{l}\t{$src, $dst|$dst, $src}",
3375 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3377 TB, Requires<[HasSSE2]>;
3378 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3379 "movnti{q}\t{$src, $dst|$dst, $src}",
3380 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3382 TB, Requires<[HasSSE2]>;
3385 //===----------------------------------------------------------------------===//
3386 // SSE 1 & 2 - Prefetch and memory fence
3387 //===----------------------------------------------------------------------===//
3389 // Prefetch intrinsic.
3390 let Predicates = [HasSSE1] in {
3391 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3392 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3393 IIC_SSE_PREFETCH>, TB;
3394 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3395 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3396 IIC_SSE_PREFETCH>, TB;
3397 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3398 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3399 IIC_SSE_PREFETCH>, TB;
3400 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3401 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3402 IIC_SSE_PREFETCH>, TB;
3406 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3407 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3408 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3410 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3411 // was introduced with SSE2, it's backward compatible.
3412 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3414 // Load, store, and memory fence
3415 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3416 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3417 TB, Requires<[HasSSE1]>;
3418 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3419 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3420 TB, Requires<[HasSSE2]>;
3421 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3422 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3423 TB, Requires<[HasSSE2]>;
3425 def : Pat<(X86SFence), (SFENCE)>;
3426 def : Pat<(X86LFence), (LFENCE)>;
3427 def : Pat<(X86MFence), (MFENCE)>;
3429 //===----------------------------------------------------------------------===//
3430 // SSE 1 & 2 - Load/Store XCSR register
3431 //===----------------------------------------------------------------------===//
3433 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3434 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3435 IIC_SSE_LDMXCSR>, VEX;
3436 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3437 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3438 IIC_SSE_STMXCSR>, VEX;
3440 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3441 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3443 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3444 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3447 //===---------------------------------------------------------------------===//
3448 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3449 //===---------------------------------------------------------------------===//
3451 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3453 let neverHasSideEffects = 1 in {
3454 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3455 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3457 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3458 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3460 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3461 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3463 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3464 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3469 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3470 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3471 "movdqa\t{$src, $dst|$dst, $src}", [],
3474 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3475 "movdqa\t{$src, $dst|$dst, $src}", [],
3476 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3477 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3478 "movdqu\t{$src, $dst|$dst, $src}", [],
3481 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3482 "movdqu\t{$src, $dst|$dst, $src}", [],
3483 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3486 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3487 neverHasSideEffects = 1 in {
3488 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3489 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3491 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3492 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3494 let Predicates = [HasAVX] in {
3495 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3496 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3498 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3499 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3504 let mayStore = 1, neverHasSideEffects = 1 in {
3505 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3506 (ins i128mem:$dst, VR128:$src),
3507 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3509 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3510 (ins i256mem:$dst, VR256:$src),
3511 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3513 let Predicates = [HasAVX] in {
3514 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3515 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3517 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3518 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3523 let neverHasSideEffects = 1 in
3524 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3525 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3527 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3528 "movdqu\t{$src, $dst|$dst, $src}",
3529 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3532 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3533 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3534 "movdqa\t{$src, $dst|$dst, $src}", [],
3537 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3538 "movdqu\t{$src, $dst|$dst, $src}",
3539 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3542 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3543 neverHasSideEffects = 1 in {
3544 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3545 "movdqa\t{$src, $dst|$dst, $src}",
3546 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3548 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3549 "movdqu\t{$src, $dst|$dst, $src}",
3550 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3552 XS, Requires<[UseSSE2]>;
3555 let mayStore = 1 in {
3556 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3557 "movdqa\t{$src, $dst|$dst, $src}",
3558 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3560 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3561 "movdqu\t{$src, $dst|$dst, $src}",
3562 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3564 XS, Requires<[UseSSE2]>;
3567 } // ExeDomain = SSEPackedInt
3569 let Predicates = [HasAVX] in {
3570 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3571 (VMOVDQUmr addr:$dst, VR128:$src)>;
3572 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3573 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3575 let Predicates = [UseSSE2] in
3576 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3577 (MOVDQUmr addr:$dst, VR128:$src)>;
3579 //===---------------------------------------------------------------------===//
3580 // SSE2 - Packed Integer Arithmetic Instructions
3581 //===---------------------------------------------------------------------===//
3583 def SSE_PMADD : OpndItins<
3584 IIC_SSE_PMADD, IIC_SSE_PMADD
3587 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3589 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3590 RegisterClass RC, PatFrag memop_frag,
3591 X86MemOperand x86memop,
3593 bit IsCommutable = 0,
3595 let isCommutable = IsCommutable in
3596 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3597 (ins RC:$src1, RC:$src2),
3599 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3601 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3602 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3603 (ins RC:$src1, x86memop:$src2),
3605 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3606 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3607 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3611 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3612 Intrinsic IntId256, OpndItins itins,
3613 bit IsCommutable = 0> {
3614 let Predicates = [HasAVX] in
3615 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3616 VR128, memopv2i64, i128mem, itins,
3617 IsCommutable, 0>, VEX_4V;
3619 let Constraints = "$src1 = $dst" in
3620 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3621 i128mem, itins, IsCommutable, 1>;
3623 let Predicates = [HasAVX2] in
3624 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3625 VR256, memopv4i64, i256mem, itins,
3626 IsCommutable, 0>, VEX_4V, VEX_L;
3629 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3630 string OpcodeStr, SDNode OpNode,
3631 SDNode OpNode2, RegisterClass RC,
3632 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3633 ShiftOpndItins itins,
3635 // src2 is always 128-bit
3636 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3637 (ins RC:$src1, VR128:$src2),
3639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3640 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3641 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3643 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3644 (ins RC:$src1, i128mem:$src2),
3646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3648 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3649 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3650 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3651 (ins RC:$src1, i32i8imm:$src2),
3653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3655 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3658 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3659 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3660 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3661 PatFrag memop_frag, X86MemOperand x86memop,
3663 bit IsCommutable = 0, bit Is2Addr = 1> {
3664 let isCommutable = IsCommutable in
3665 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3666 (ins RC:$src1, RC:$src2),
3668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3670 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3671 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3672 (ins RC:$src1, x86memop:$src2),
3674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3676 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3677 (bitconvert (memop_frag addr:$src2)))))]>;
3679 } // ExeDomain = SSEPackedInt
3681 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3682 SSE_INTALU_ITINS_P, 1>;
3683 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3684 SSE_INTALU_ITINS_P, 1>;
3685 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3686 SSE_INTALU_ITINS_P, 1>;
3687 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3688 SSE_INTALUQ_ITINS_P, 1>;
3689 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3690 SSE_INTMUL_ITINS_P, 1>;
3691 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3692 SSE_INTALU_ITINS_P, 0>;
3693 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3694 SSE_INTALU_ITINS_P, 0>;
3695 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3696 SSE_INTALU_ITINS_P, 0>;
3697 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3698 SSE_INTALUQ_ITINS_P, 0>;
3699 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3700 SSE_INTALU_ITINS_P, 0>;
3701 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3702 SSE_INTALU_ITINS_P, 0>;
3703 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3704 SSE_INTALU_ITINS_P, 1>;
3705 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3706 SSE_INTALU_ITINS_P, 1>;
3707 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3708 SSE_INTALU_ITINS_P, 1>;
3709 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3710 SSE_INTALU_ITINS_P, 1>;
3713 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3714 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3715 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3716 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3717 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3718 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3719 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3720 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3721 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3722 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3723 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3724 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3725 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3726 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3727 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3728 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3729 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3730 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3731 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3732 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3733 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3734 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3735 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3736 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3738 let Predicates = [HasAVX] in
3739 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3740 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3742 let Predicates = [HasAVX2] in
3743 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3744 VR256, memopv4i64, i256mem,
3745 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3746 let Constraints = "$src1 = $dst" in
3747 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3748 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3750 //===---------------------------------------------------------------------===//
3751 // SSE2 - Packed Integer Logical Instructions
3752 //===---------------------------------------------------------------------===//
3754 let Predicates = [HasAVX] in {
3755 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3756 VR128, v8i16, v8i16, bc_v8i16,
3757 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3758 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3759 VR128, v4i32, v4i32, bc_v4i32,
3760 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3761 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3762 VR128, v2i64, v2i64, bc_v2i64,
3763 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3765 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3766 VR128, v8i16, v8i16, bc_v8i16,
3767 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3768 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3769 VR128, v4i32, v4i32, bc_v4i32,
3770 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3771 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3772 VR128, v2i64, v2i64, bc_v2i64,
3773 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3775 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3776 VR128, v8i16, v8i16, bc_v8i16,
3777 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3778 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3779 VR128, v4i32, v4i32, bc_v4i32,
3780 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3782 let ExeDomain = SSEPackedInt in {
3783 // 128-bit logical shifts.
3784 def VPSLLDQri : PDIi8<0x73, MRM7r,
3785 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3786 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3788 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3790 def VPSRLDQri : PDIi8<0x73, MRM3r,
3791 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3792 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3794 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3796 // PSRADQri doesn't exist in SSE[1-3].
3798 } // Predicates = [HasAVX]
3800 let Predicates = [HasAVX2] in {
3801 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3802 VR256, v16i16, v8i16, bc_v8i16,
3803 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3804 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3805 VR256, v8i32, v4i32, bc_v4i32,
3806 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3807 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3808 VR256, v4i64, v2i64, bc_v2i64,
3809 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3811 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3812 VR256, v16i16, v8i16, bc_v8i16,
3813 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3814 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3815 VR256, v8i32, v4i32, bc_v4i32,
3816 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3817 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3818 VR256, v4i64, v2i64, bc_v2i64,
3819 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3821 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3822 VR256, v16i16, v8i16, bc_v8i16,
3823 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3824 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3825 VR256, v8i32, v4i32, bc_v4i32,
3826 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3828 let ExeDomain = SSEPackedInt in {
3829 // 256-bit logical shifts.
3830 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3831 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3832 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3834 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3836 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3837 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3838 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3840 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3842 // PSRADQYri doesn't exist in SSE[1-3].
3844 } // Predicates = [HasAVX2]
3846 let Constraints = "$src1 = $dst" in {
3847 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3848 VR128, v8i16, v8i16, bc_v8i16,
3849 SSE_INTSHIFT_ITINS_P>;
3850 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3851 VR128, v4i32, v4i32, bc_v4i32,
3852 SSE_INTSHIFT_ITINS_P>;
3853 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3854 VR128, v2i64, v2i64, bc_v2i64,
3855 SSE_INTSHIFT_ITINS_P>;
3857 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3858 VR128, v8i16, v8i16, bc_v8i16,
3859 SSE_INTSHIFT_ITINS_P>;
3860 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3861 VR128, v4i32, v4i32, bc_v4i32,
3862 SSE_INTSHIFT_ITINS_P>;
3863 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3864 VR128, v2i64, v2i64, bc_v2i64,
3865 SSE_INTSHIFT_ITINS_P>;
3867 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3868 VR128, v8i16, v8i16, bc_v8i16,
3869 SSE_INTSHIFT_ITINS_P>;
3870 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3871 VR128, v4i32, v4i32, bc_v4i32,
3872 SSE_INTSHIFT_ITINS_P>;
3874 let ExeDomain = SSEPackedInt in {
3875 // 128-bit logical shifts.
3876 def PSLLDQri : PDIi8<0x73, MRM7r,
3877 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3878 "pslldq\t{$src2, $dst|$dst, $src2}",
3880 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3881 def PSRLDQri : PDIi8<0x73, MRM3r,
3882 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3883 "psrldq\t{$src2, $dst|$dst, $src2}",
3885 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3886 // PSRADQri doesn't exist in SSE[1-3].
3888 } // Constraints = "$src1 = $dst"
3890 let Predicates = [HasAVX] in {
3891 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3892 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3893 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3894 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3895 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3896 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3898 // Shift up / down and insert zero's.
3899 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3900 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3901 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3902 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3905 let Predicates = [HasAVX2] in {
3906 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3907 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3908 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3909 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3912 let Predicates = [UseSSE2] in {
3913 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3914 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3915 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3916 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3917 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3918 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3920 // Shift up / down and insert zero's.
3921 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3922 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3923 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3924 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3927 //===---------------------------------------------------------------------===//
3928 // SSE2 - Packed Integer Comparison Instructions
3929 //===---------------------------------------------------------------------===//
3931 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
3932 SSE_INTALU_ITINS_P, 1>;
3933 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
3934 SSE_INTALU_ITINS_P, 1>;
3935 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
3936 SSE_INTALU_ITINS_P, 1>;
3937 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
3938 SSE_INTALU_ITINS_P, 0>;
3939 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
3940 SSE_INTALU_ITINS_P, 0>;
3941 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
3942 SSE_INTALU_ITINS_P, 0>;
3944 //===---------------------------------------------------------------------===//
3945 // SSE2 - Packed Integer Pack Instructions
3946 //===---------------------------------------------------------------------===//
3948 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3949 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
3950 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3951 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
3952 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3953 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
3955 //===---------------------------------------------------------------------===//
3956 // SSE2 - Packed Integer Shuffle Instructions
3957 //===---------------------------------------------------------------------===//
3959 let ExeDomain = SSEPackedInt in {
3960 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
3962 let Predicates = [HasAVX] in {
3963 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
3964 (ins VR128:$src1, i8imm:$src2),
3965 !strconcat("v", OpcodeStr,
3966 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3968 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
3969 IIC_SSE_PSHUF>, VEX;
3970 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
3971 (ins i128mem:$src1, i8imm:$src2),
3972 !strconcat("v", OpcodeStr,
3973 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3975 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
3976 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX;
3979 let Predicates = [HasAVX2] in {
3980 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
3981 (ins VR256:$src1, i8imm:$src2),
3982 !strconcat("v", OpcodeStr,
3983 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3985 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
3986 IIC_SSE_PSHUF>, VEX, VEX_L;
3987 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
3988 (ins i256mem:$src1, i8imm:$src2),
3989 !strconcat("v", OpcodeStr,
3990 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3992 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
3993 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX, VEX_L;
3996 let Predicates = [UseSSE2] in {
3997 def ri : Ii8<0x70, MRMSrcReg,
3998 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3999 !strconcat(OpcodeStr,
4000 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4002 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4004 def mi : Ii8<0x70, MRMSrcMem,
4005 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4006 !strconcat(OpcodeStr,
4007 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4009 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4010 (i8 imm:$src2))))], IIC_SSE_PSHUF>;
4013 } // ExeDomain = SSEPackedInt
4015 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4016 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4017 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4019 let Predicates = [HasAVX] in {
4020 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4021 (VPSHUFDmi addr:$src1, imm:$imm)>;
4022 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4023 (VPSHUFDri VR128:$src1, imm:$imm)>;
4026 let Predicates = [UseSSE2] in {
4027 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4028 (PSHUFDmi addr:$src1, imm:$imm)>;
4029 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4030 (PSHUFDri VR128:$src1, imm:$imm)>;
4033 //===---------------------------------------------------------------------===//
4034 // SSE2 - Packed Integer Unpack Instructions
4035 //===---------------------------------------------------------------------===//
4037 let ExeDomain = SSEPackedInt in {
4038 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4039 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4040 def rr : PDI<opc, MRMSrcReg,
4041 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4043 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4044 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4045 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4047 def rm : PDI<opc, MRMSrcMem,
4048 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4050 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4051 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4052 [(set VR128:$dst, (OpNode VR128:$src1,
4053 (bc_frag (memopv2i64
4058 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4059 SDNode OpNode, PatFrag bc_frag> {
4060 def Yrr : PDI<opc, MRMSrcReg,
4061 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4062 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4063 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4064 def Yrm : PDI<opc, MRMSrcMem,
4065 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4066 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4067 [(set VR256:$dst, (OpNode VR256:$src1,
4068 (bc_frag (memopv4i64 addr:$src2))))]>;
4071 let Predicates = [HasAVX] in {
4072 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4073 bc_v16i8, 0>, VEX_4V;
4074 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4075 bc_v8i16, 0>, VEX_4V;
4076 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4077 bc_v4i32, 0>, VEX_4V;
4078 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4079 bc_v2i64, 0>, VEX_4V;
4081 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4082 bc_v16i8, 0>, VEX_4V;
4083 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4084 bc_v8i16, 0>, VEX_4V;
4085 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4086 bc_v4i32, 0>, VEX_4V;
4087 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4088 bc_v2i64, 0>, VEX_4V;
4091 let Predicates = [HasAVX2] in {
4092 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4093 bc_v32i8>, VEX_4V, VEX_L;
4094 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4095 bc_v16i16>, VEX_4V, VEX_L;
4096 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4097 bc_v8i32>, VEX_4V, VEX_L;
4098 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4099 bc_v4i64>, VEX_4V, VEX_L;
4101 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4102 bc_v32i8>, VEX_4V, VEX_L;
4103 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4104 bc_v16i16>, VEX_4V, VEX_L;
4105 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4106 bc_v8i32>, VEX_4V, VEX_L;
4107 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4108 bc_v4i64>, VEX_4V, VEX_L;
4111 let Constraints = "$src1 = $dst" in {
4112 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4114 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4116 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4118 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4121 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4123 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4125 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4127 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4130 } // ExeDomain = SSEPackedInt
4132 //===---------------------------------------------------------------------===//
4133 // SSE2 - Packed Integer Extract and Insert
4134 //===---------------------------------------------------------------------===//
4136 let ExeDomain = SSEPackedInt in {
4137 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4138 def rri : Ii8<0xC4, MRMSrcReg,
4139 (outs VR128:$dst), (ins VR128:$src1,
4140 GR32:$src2, i32i8imm:$src3),
4142 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4143 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4145 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4146 def rmi : Ii8<0xC4, MRMSrcMem,
4147 (outs VR128:$dst), (ins VR128:$src1,
4148 i16mem:$src2, i32i8imm:$src3),
4150 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4151 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4153 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4154 imm:$src3))], IIC_SSE_PINSRW>;
4158 let Predicates = [HasAVX] in
4159 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4160 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4161 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4162 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4163 imm:$src2))]>, TB, OpSize, VEX;
4164 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4165 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4166 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4167 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4168 imm:$src2))], IIC_SSE_PEXTRW>;
4171 let Predicates = [HasAVX] in {
4172 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4173 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4174 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4175 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4176 []>, TB, OpSize, VEX_4V;
4179 let Constraints = "$src1 = $dst" in
4180 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4182 } // ExeDomain = SSEPackedInt
4184 //===---------------------------------------------------------------------===//
4185 // SSE2 - Packed Mask Creation
4186 //===---------------------------------------------------------------------===//
4188 let ExeDomain = SSEPackedInt in {
4190 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4191 "pmovmskb\t{$src, $dst|$dst, $src}",
4192 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4193 IIC_SSE_MOVMSK>, VEX;
4194 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4195 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4197 let Predicates = [HasAVX2] in {
4198 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4199 "pmovmskb\t{$src, $dst|$dst, $src}",
4200 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4201 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4202 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4205 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4206 "pmovmskb\t{$src, $dst|$dst, $src}",
4207 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4210 } // ExeDomain = SSEPackedInt
4212 //===---------------------------------------------------------------------===//
4213 // SSE2 - Conditional Store
4214 //===---------------------------------------------------------------------===//
4216 let ExeDomain = SSEPackedInt in {
4219 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4220 (ins VR128:$src, VR128:$mask),
4221 "maskmovdqu\t{$mask, $src|$src, $mask}",
4222 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4223 IIC_SSE_MASKMOV>, VEX;
4225 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4226 (ins VR128:$src, VR128:$mask),
4227 "maskmovdqu\t{$mask, $src|$src, $mask}",
4228 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4229 IIC_SSE_MASKMOV>, VEX;
4232 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4233 "maskmovdqu\t{$mask, $src|$src, $mask}",
4234 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4237 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4238 "maskmovdqu\t{$mask, $src|$src, $mask}",
4239 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4242 } // ExeDomain = SSEPackedInt
4244 //===---------------------------------------------------------------------===//
4245 // SSE2 - Move Doubleword
4246 //===---------------------------------------------------------------------===//
4248 //===---------------------------------------------------------------------===//
4249 // Move Int Doubleword to Packed Double Int
4251 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4252 "movd\t{$src, $dst|$dst, $src}",
4254 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4256 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4257 "movd\t{$src, $dst|$dst, $src}",
4259 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4262 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4263 "mov{d|q}\t{$src, $dst|$dst, $src}",
4265 (v2i64 (scalar_to_vector GR64:$src)))],
4266 IIC_SSE_MOVDQ>, VEX;
4267 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4268 "mov{d|q}\t{$src, $dst|$dst, $src}",
4269 [(set FR64:$dst, (bitconvert GR64:$src))],
4270 IIC_SSE_MOVDQ>, VEX;
4272 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4273 "movd\t{$src, $dst|$dst, $src}",
4275 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4276 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4277 "movd\t{$src, $dst|$dst, $src}",
4279 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4281 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4282 "mov{d|q}\t{$src, $dst|$dst, $src}",
4284 (v2i64 (scalar_to_vector GR64:$src)))],
4286 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4287 "mov{d|q}\t{$src, $dst|$dst, $src}",
4288 [(set FR64:$dst, (bitconvert GR64:$src))],
4291 //===---------------------------------------------------------------------===//
4292 // Move Int Doubleword to Single Scalar
4294 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4295 "movd\t{$src, $dst|$dst, $src}",
4296 [(set FR32:$dst, (bitconvert GR32:$src))],
4297 IIC_SSE_MOVDQ>, VEX;
4299 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4300 "movd\t{$src, $dst|$dst, $src}",
4301 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4304 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4305 "movd\t{$src, $dst|$dst, $src}",
4306 [(set FR32:$dst, (bitconvert GR32:$src))],
4309 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4310 "movd\t{$src, $dst|$dst, $src}",
4311 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4314 //===---------------------------------------------------------------------===//
4315 // Move Packed Doubleword Int to Packed Double Int
4317 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4318 "movd\t{$src, $dst|$dst, $src}",
4319 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4320 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4321 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4322 (ins i32mem:$dst, VR128:$src),
4323 "movd\t{$src, $dst|$dst, $src}",
4324 [(store (i32 (vector_extract (v4i32 VR128:$src),
4325 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4327 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4328 "movd\t{$src, $dst|$dst, $src}",
4329 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4330 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4331 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4332 "movd\t{$src, $dst|$dst, $src}",
4333 [(store (i32 (vector_extract (v4i32 VR128:$src),
4334 (iPTR 0))), addr:$dst)],
4337 //===---------------------------------------------------------------------===//
4338 // Move Packed Doubleword Int first element to Doubleword Int
4340 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4341 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4342 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4345 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4347 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4348 "mov{d|q}\t{$src, $dst|$dst, $src}",
4349 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4353 //===---------------------------------------------------------------------===//
4354 // Bitcast FR64 <-> GR64
4356 let Predicates = [HasAVX] in
4357 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4358 "vmovq\t{$src, $dst|$dst, $src}",
4359 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4361 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4362 "mov{d|q}\t{$src, $dst|$dst, $src}",
4363 [(set GR64:$dst, (bitconvert FR64:$src))],
4364 IIC_SSE_MOVDQ>, VEX;
4365 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4366 "movq\t{$src, $dst|$dst, $src}",
4367 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4368 IIC_SSE_MOVDQ>, VEX;
4370 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4371 "movq\t{$src, $dst|$dst, $src}",
4372 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4374 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4375 "mov{d|q}\t{$src, $dst|$dst, $src}",
4376 [(set GR64:$dst, (bitconvert FR64:$src))],
4378 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4379 "movq\t{$src, $dst|$dst, $src}",
4380 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4383 //===---------------------------------------------------------------------===//
4384 // Move Scalar Single to Double Int
4386 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4387 "movd\t{$src, $dst|$dst, $src}",
4388 [(set GR32:$dst, (bitconvert FR32:$src))],
4389 IIC_SSE_MOVD_ToGP>, VEX;
4390 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4391 "movd\t{$src, $dst|$dst, $src}",
4392 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4393 IIC_SSE_MOVDQ>, VEX;
4394 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4395 "movd\t{$src, $dst|$dst, $src}",
4396 [(set GR32:$dst, (bitconvert FR32:$src))],
4398 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4399 "movd\t{$src, $dst|$dst, $src}",
4400 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4403 //===---------------------------------------------------------------------===//
4404 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4406 let AddedComplexity = 15 in {
4407 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4408 "movd\t{$src, $dst|$dst, $src}",
4409 [(set VR128:$dst, (v4i32 (X86vzmovl
4410 (v4i32 (scalar_to_vector GR32:$src)))))],
4411 IIC_SSE_MOVDQ>, VEX;
4412 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4413 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4414 [(set VR128:$dst, (v2i64 (X86vzmovl
4415 (v2i64 (scalar_to_vector GR64:$src)))))],
4419 let AddedComplexity = 15 in {
4420 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4421 "movd\t{$src, $dst|$dst, $src}",
4422 [(set VR128:$dst, (v4i32 (X86vzmovl
4423 (v4i32 (scalar_to_vector GR32:$src)))))],
4425 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4426 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4427 [(set VR128:$dst, (v2i64 (X86vzmovl
4428 (v2i64 (scalar_to_vector GR64:$src)))))],
4432 let AddedComplexity = 20 in {
4433 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4434 "movd\t{$src, $dst|$dst, $src}",
4436 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4437 (loadi32 addr:$src))))))],
4438 IIC_SSE_MOVDQ>, VEX;
4439 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4440 "movd\t{$src, $dst|$dst, $src}",
4442 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4443 (loadi32 addr:$src))))))],
4447 let Predicates = [HasAVX] in {
4448 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4449 let AddedComplexity = 20 in {
4450 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4451 (VMOVZDI2PDIrm addr:$src)>;
4452 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4453 (VMOVZDI2PDIrm addr:$src)>;
4455 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4456 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4457 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4458 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4459 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4460 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4461 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4464 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4465 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4466 (MOVZDI2PDIrm addr:$src)>;
4467 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4468 (MOVZDI2PDIrm addr:$src)>;
4471 // These are the correct encodings of the instructions so that we know how to
4472 // read correct assembly, even though we continue to emit the wrong ones for
4473 // compatibility with Darwin's buggy assembler.
4474 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4475 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4476 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4477 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4478 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4479 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4480 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4481 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4482 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4483 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4484 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4485 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4487 //===---------------------------------------------------------------------===//
4488 // SSE2 - Move Quadword
4489 //===---------------------------------------------------------------------===//
4491 //===---------------------------------------------------------------------===//
4492 // Move Quadword Int to Packed Quadword Int
4494 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4495 "vmovq\t{$src, $dst|$dst, $src}",
4497 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4498 VEX, Requires<[HasAVX]>;
4499 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4500 "movq\t{$src, $dst|$dst, $src}",
4502 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4504 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4506 //===---------------------------------------------------------------------===//
4507 // Move Packed Quadword Int to Quadword Int
4509 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4510 "movq\t{$src, $dst|$dst, $src}",
4511 [(store (i64 (vector_extract (v2i64 VR128:$src),
4512 (iPTR 0))), addr:$dst)],
4513 IIC_SSE_MOVDQ>, VEX;
4514 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4515 "movq\t{$src, $dst|$dst, $src}",
4516 [(store (i64 (vector_extract (v2i64 VR128:$src),
4517 (iPTR 0))), addr:$dst)],
4520 //===---------------------------------------------------------------------===//
4521 // Store / copy lower 64-bits of a XMM register.
4523 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4524 "movq\t{$src, $dst|$dst, $src}",
4525 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4526 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4527 "movq\t{$src, $dst|$dst, $src}",
4528 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4531 let AddedComplexity = 20 in
4532 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4533 "vmovq\t{$src, $dst|$dst, $src}",
4535 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4536 (loadi64 addr:$src))))))],
4538 XS, VEX, Requires<[HasAVX]>;
4540 let AddedComplexity = 20 in
4541 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4542 "movq\t{$src, $dst|$dst, $src}",
4544 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4545 (loadi64 addr:$src))))))],
4547 XS, Requires<[UseSSE2]>;
4549 let Predicates = [HasAVX], AddedComplexity = 20 in {
4550 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4551 (VMOVZQI2PQIrm addr:$src)>;
4552 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4553 (VMOVZQI2PQIrm addr:$src)>;
4554 def : Pat<(v2i64 (X86vzload addr:$src)),
4555 (VMOVZQI2PQIrm addr:$src)>;
4558 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4559 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4560 (MOVZQI2PQIrm addr:$src)>;
4561 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4562 (MOVZQI2PQIrm addr:$src)>;
4563 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4566 let Predicates = [HasAVX] in {
4567 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4568 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4569 def : Pat<(v4i64 (X86vzload addr:$src)),
4570 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4573 //===---------------------------------------------------------------------===//
4574 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4575 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4577 let AddedComplexity = 15 in
4578 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4579 "vmovq\t{$src, $dst|$dst, $src}",
4580 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4582 XS, VEX, Requires<[HasAVX]>;
4583 let AddedComplexity = 15 in
4584 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4585 "movq\t{$src, $dst|$dst, $src}",
4586 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4588 XS, Requires<[UseSSE2]>;
4590 let AddedComplexity = 20 in
4591 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4592 "vmovq\t{$src, $dst|$dst, $src}",
4593 [(set VR128:$dst, (v2i64 (X86vzmovl
4594 (loadv2i64 addr:$src))))],
4596 XS, VEX, Requires<[HasAVX]>;
4597 let AddedComplexity = 20 in {
4598 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4599 "movq\t{$src, $dst|$dst, $src}",
4600 [(set VR128:$dst, (v2i64 (X86vzmovl
4601 (loadv2i64 addr:$src))))],
4603 XS, Requires<[UseSSE2]>;
4606 let AddedComplexity = 20 in {
4607 let Predicates = [HasAVX] in {
4608 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4609 (VMOVZPQILo2PQIrm addr:$src)>;
4610 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4611 (VMOVZPQILo2PQIrr VR128:$src)>;
4613 let Predicates = [UseSSE2] in {
4614 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4615 (MOVZPQILo2PQIrm addr:$src)>;
4616 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4617 (MOVZPQILo2PQIrr VR128:$src)>;
4621 // Instructions to match in the assembler
4622 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4623 "movq\t{$src, $dst|$dst, $src}", [],
4624 IIC_SSE_MOVDQ>, VEX, VEX_W;
4625 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4626 "movq\t{$src, $dst|$dst, $src}", [],
4627 IIC_SSE_MOVDQ>, VEX, VEX_W;
4628 // Recognize "movd" with GR64 destination, but encode as a "movq"
4629 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4630 "movd\t{$src, $dst|$dst, $src}", [],
4631 IIC_SSE_MOVDQ>, VEX, VEX_W;
4633 // Instructions for the disassembler
4634 // xr = XMM register
4637 let Predicates = [HasAVX] in
4638 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4639 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4640 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4641 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4643 //===---------------------------------------------------------------------===//
4644 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4645 //===---------------------------------------------------------------------===//
4646 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4647 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4648 X86MemOperand x86memop> {
4649 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4651 [(set RC:$dst, (vt (OpNode RC:$src)))],
4653 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4654 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4655 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4659 let Predicates = [HasAVX] in {
4660 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4661 v4f32, VR128, memopv4f32, f128mem>, VEX;
4662 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4663 v4f32, VR128, memopv4f32, f128mem>, VEX;
4664 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4665 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4666 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4667 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4669 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4670 memopv4f32, f128mem>;
4671 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4672 memopv4f32, f128mem>;
4674 let Predicates = [HasAVX] in {
4675 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4676 (VMOVSHDUPrr VR128:$src)>;
4677 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4678 (VMOVSHDUPrm addr:$src)>;
4679 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4680 (VMOVSLDUPrr VR128:$src)>;
4681 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4682 (VMOVSLDUPrm addr:$src)>;
4683 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4684 (VMOVSHDUPYrr VR256:$src)>;
4685 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4686 (VMOVSHDUPYrm addr:$src)>;
4687 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4688 (VMOVSLDUPYrr VR256:$src)>;
4689 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4690 (VMOVSLDUPYrm addr:$src)>;
4693 let Predicates = [UseSSE3] in {
4694 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4695 (MOVSHDUPrr VR128:$src)>;
4696 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4697 (MOVSHDUPrm addr:$src)>;
4698 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4699 (MOVSLDUPrr VR128:$src)>;
4700 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4701 (MOVSLDUPrm addr:$src)>;
4704 //===---------------------------------------------------------------------===//
4705 // SSE3 - Replicate Double FP - MOVDDUP
4706 //===---------------------------------------------------------------------===//
4708 multiclass sse3_replicate_dfp<string OpcodeStr> {
4709 let neverHasSideEffects = 1 in
4710 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4712 [], IIC_SSE_MOV_LH>;
4713 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4717 (scalar_to_vector (loadf64 addr:$src)))))],
4721 // FIXME: Merge with above classe when there're patterns for the ymm version
4722 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4723 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4725 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4726 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4727 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4730 (scalar_to_vector (loadf64 addr:$src)))))]>;
4733 let Predicates = [HasAVX] in {
4734 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4735 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4738 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4740 let Predicates = [HasAVX] in {
4741 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4742 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4743 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4744 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4745 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4746 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4747 def : Pat<(X86Movddup (bc_v2f64
4748 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4749 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4752 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4753 (VMOVDDUPYrm addr:$src)>;
4754 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4755 (VMOVDDUPYrm addr:$src)>;
4756 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4757 (VMOVDDUPYrm addr:$src)>;
4758 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4759 (VMOVDDUPYrr VR256:$src)>;
4762 let Predicates = [UseSSE3] in {
4763 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4764 (MOVDDUPrm addr:$src)>;
4765 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4766 (MOVDDUPrm addr:$src)>;
4767 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4768 (MOVDDUPrm addr:$src)>;
4769 def : Pat<(X86Movddup (bc_v2f64
4770 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4771 (MOVDDUPrm addr:$src)>;
4774 //===---------------------------------------------------------------------===//
4775 // SSE3 - Move Unaligned Integer
4776 //===---------------------------------------------------------------------===//
4778 let Predicates = [HasAVX] in {
4779 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4780 "vlddqu\t{$src, $dst|$dst, $src}",
4781 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4782 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4783 "vlddqu\t{$src, $dst|$dst, $src}",
4784 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4787 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4788 "lddqu\t{$src, $dst|$dst, $src}",
4789 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4792 //===---------------------------------------------------------------------===//
4793 // SSE3 - Arithmetic
4794 //===---------------------------------------------------------------------===//
4796 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4797 X86MemOperand x86memop, OpndItins itins,
4799 def rr : I<0xD0, MRMSrcReg,
4800 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4802 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4804 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
4805 def rm : I<0xD0, MRMSrcMem,
4806 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4809 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4810 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
4813 let Predicates = [HasAVX] in {
4814 let ExeDomain = SSEPackedSingle in {
4815 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4816 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4817 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4818 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4820 let ExeDomain = SSEPackedDouble in {
4821 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4822 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4823 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4824 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4827 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4828 let ExeDomain = SSEPackedSingle in
4829 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4830 f128mem, SSE_ALU_F32P>, TB, XD;
4831 let ExeDomain = SSEPackedDouble in
4832 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4833 f128mem, SSE_ALU_F64P>, TB, OpSize;
4836 //===---------------------------------------------------------------------===//
4837 // SSE3 Instructions
4838 //===---------------------------------------------------------------------===//
4841 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4842 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4843 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4847 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4849 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4851 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4852 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4853 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4854 IIC_SSE_HADDSUB_RM>;
4856 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4857 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4858 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4860 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4861 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4862 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4864 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4868 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4869 IIC_SSE_HADDSUB_RM>;
4872 let Predicates = [HasAVX] in {
4873 let ExeDomain = SSEPackedSingle in {
4874 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4875 X86fhadd, 0>, VEX_4V;
4876 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4877 X86fhsub, 0>, VEX_4V;
4878 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4879 X86fhadd, 0>, VEX_4V, VEX_L;
4880 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4881 X86fhsub, 0>, VEX_4V, VEX_L;
4883 let ExeDomain = SSEPackedDouble in {
4884 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4885 X86fhadd, 0>, VEX_4V;
4886 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4887 X86fhsub, 0>, VEX_4V;
4888 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4889 X86fhadd, 0>, VEX_4V, VEX_L;
4890 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4891 X86fhsub, 0>, VEX_4V, VEX_L;
4895 let Constraints = "$src1 = $dst" in {
4896 let ExeDomain = SSEPackedSingle in {
4897 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4898 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4900 let ExeDomain = SSEPackedDouble in {
4901 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4902 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4906 //===---------------------------------------------------------------------===//
4907 // SSSE3 - Packed Absolute Instructions
4908 //===---------------------------------------------------------------------===//
4911 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4912 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4913 Intrinsic IntId128> {
4914 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4916 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4917 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
4920 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4922 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4925 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
4929 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4930 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4931 Intrinsic IntId256> {
4932 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4934 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4935 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4938 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4940 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4943 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4946 let Predicates = [HasAVX] in {
4947 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4948 int_x86_ssse3_pabs_b_128>, VEX;
4949 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4950 int_x86_ssse3_pabs_w_128>, VEX;
4951 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4952 int_x86_ssse3_pabs_d_128>, VEX;
4955 let Predicates = [HasAVX2] in {
4956 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4957 int_x86_avx2_pabs_b>, VEX, VEX_L;
4958 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4959 int_x86_avx2_pabs_w>, VEX, VEX_L;
4960 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4961 int_x86_avx2_pabs_d>, VEX, VEX_L;
4964 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4965 int_x86_ssse3_pabs_b_128>;
4966 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4967 int_x86_ssse3_pabs_w_128>;
4968 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4969 int_x86_ssse3_pabs_d_128>;
4971 //===---------------------------------------------------------------------===//
4972 // SSSE3 - Packed Binary Operator Instructions
4973 //===---------------------------------------------------------------------===//
4975 def SSE_PHADDSUBD : OpndItins<
4976 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
4978 def SSE_PHADDSUBSW : OpndItins<
4979 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
4981 def SSE_PHADDSUBW : OpndItins<
4982 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
4984 def SSE_PSHUFB : OpndItins<
4985 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
4987 def SSE_PSIGN : OpndItins<
4988 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
4990 def SSE_PMULHRSW : OpndItins<
4991 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
4994 /// SS3I_binop_rm - Simple SSSE3 bin op
4995 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4996 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
4997 X86MemOperand x86memop, OpndItins itins,
4999 let isCommutable = 1 in
5000 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5001 (ins RC:$src1, RC:$src2),
5003 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5005 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5007 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5008 (ins RC:$src1, x86memop:$src2),
5010 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5013 (OpVT (OpNode RC:$src1,
5014 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5017 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5018 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5019 Intrinsic IntId128, OpndItins itins,
5021 let isCommutable = 1 in
5022 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5023 (ins VR128:$src1, VR128:$src2),
5025 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5027 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5029 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5030 (ins VR128:$src1, i128mem:$src2),
5032 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5035 (IntId128 VR128:$src1,
5036 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5039 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5040 Intrinsic IntId256> {
5041 let isCommutable = 1 in
5042 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5043 (ins VR256:$src1, VR256:$src2),
5044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5045 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5047 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5048 (ins VR256:$src1, i256mem:$src2),
5049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5051 (IntId256 VR256:$src1,
5052 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5055 let ImmT = NoImm, Predicates = [HasAVX] in {
5056 let isCommutable = 0 in {
5057 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5058 memopv2i64, i128mem,
5059 SSE_PHADDSUBW, 0>, VEX_4V;
5060 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5061 memopv2i64, i128mem,
5062 SSE_PHADDSUBD, 0>, VEX_4V;
5063 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5064 memopv2i64, i128mem,
5065 SSE_PHADDSUBW, 0>, VEX_4V;
5066 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5067 memopv2i64, i128mem,
5068 SSE_PHADDSUBD, 0>, VEX_4V;
5069 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5070 memopv2i64, i128mem,
5071 SSE_PSIGN, 0>, VEX_4V;
5072 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5073 memopv2i64, i128mem,
5074 SSE_PSIGN, 0>, VEX_4V;
5075 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5076 memopv2i64, i128mem,
5077 SSE_PSIGN, 0>, VEX_4V;
5078 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5079 memopv2i64, i128mem,
5080 SSE_PSHUFB, 0>, VEX_4V;
5081 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5082 int_x86_ssse3_phadd_sw_128,
5083 SSE_PHADDSUBSW, 0>, VEX_4V;
5084 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5085 int_x86_ssse3_phsub_sw_128,
5086 SSE_PHADDSUBSW, 0>, VEX_4V;
5087 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5088 int_x86_ssse3_pmadd_ub_sw_128,
5089 SSE_PMADD, 0>, VEX_4V;
5091 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5092 int_x86_ssse3_pmul_hr_sw_128,
5093 SSE_PMULHRSW, 0>, VEX_4V;
5096 let ImmT = NoImm, Predicates = [HasAVX2] in {
5097 let isCommutable = 0 in {
5098 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5099 memopv4i64, i256mem,
5100 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5101 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5102 memopv4i64, i256mem,
5103 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5104 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5105 memopv4i64, i256mem,
5106 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5107 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5108 memopv4i64, i256mem,
5109 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5110 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5111 memopv4i64, i256mem,
5112 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5113 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5114 memopv4i64, i256mem,
5115 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5116 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5117 memopv4i64, i256mem,
5118 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5119 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5120 memopv4i64, i256mem,
5121 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5122 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5123 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5124 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5125 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5126 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5127 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5129 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5130 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5133 // None of these have i8 immediate fields.
5134 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5135 let isCommutable = 0 in {
5136 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5137 memopv2i64, i128mem, SSE_PHADDSUBW>;
5138 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5139 memopv2i64, i128mem, SSE_PHADDSUBD>;
5140 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5141 memopv2i64, i128mem, SSE_PHADDSUBW>;
5142 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5143 memopv2i64, i128mem, SSE_PHADDSUBD>;
5144 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5145 memopv2i64, i128mem, SSE_PSIGN>;
5146 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5147 memopv2i64, i128mem, SSE_PSIGN>;
5148 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5149 memopv2i64, i128mem, SSE_PSIGN>;
5150 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5151 memopv2i64, i128mem, SSE_PSHUFB>;
5152 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5153 int_x86_ssse3_phadd_sw_128,
5155 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5156 int_x86_ssse3_phsub_sw_128,
5158 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5159 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5161 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5162 int_x86_ssse3_pmul_hr_sw_128,
5166 //===---------------------------------------------------------------------===//
5167 // SSSE3 - Packed Align Instruction Patterns
5168 //===---------------------------------------------------------------------===//
5170 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5171 let neverHasSideEffects = 1 in {
5172 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5173 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5175 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5177 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5178 [], IIC_SSE_PALIGNR>, OpSize;
5180 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5181 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5183 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5185 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5186 [], IIC_SSE_PALIGNR>, OpSize;
5190 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5191 let neverHasSideEffects = 1 in {
5192 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5193 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5195 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5198 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5199 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5201 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5206 let Predicates = [HasAVX] in
5207 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5208 let Predicates = [HasAVX2] in
5209 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5210 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5211 defm PALIGN : ssse3_palignr<"palignr">;
5213 let Predicates = [HasAVX2] in {
5214 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5215 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5216 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5217 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5218 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5219 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5220 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5221 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5224 let Predicates = [HasAVX] in {
5225 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5226 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5227 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5228 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5229 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5230 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5231 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5232 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5235 let Predicates = [UseSSSE3] in {
5236 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5237 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5238 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5239 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5240 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5241 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5242 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5243 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5246 //===---------------------------------------------------------------------===//
5247 // SSSE3 - Thread synchronization
5248 //===---------------------------------------------------------------------===//
5250 let usesCustomInserter = 1 in {
5251 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5252 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5253 Requires<[HasSSE3]>;
5256 let Uses = [EAX, ECX, EDX] in
5257 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5258 TB, Requires<[HasSSE3]>;
5259 let Uses = [ECX, EAX] in
5260 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5261 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5262 TB, Requires<[HasSSE3]>;
5264 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5265 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5267 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5268 Requires<[In32BitMode]>;
5269 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5270 Requires<[In64BitMode]>;
5272 //===----------------------------------------------------------------------===//
5273 // SSE4.1 - Packed Move with Sign/Zero Extend
5274 //===----------------------------------------------------------------------===//
5276 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5277 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5278 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5279 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5281 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5282 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5284 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5288 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5290 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5291 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5292 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5294 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5295 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5296 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5299 let Predicates = [HasAVX] in {
5300 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5302 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5304 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5306 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5308 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5310 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5314 let Predicates = [HasAVX2] in {
5315 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5316 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5317 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5318 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5319 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5320 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5321 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5322 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5323 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5324 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5325 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5326 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5329 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5330 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5331 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5332 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5333 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5334 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5336 let Predicates = [HasAVX] in {
5337 // Common patterns involving scalar load.
5338 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5339 (VPMOVSXBWrm addr:$src)>;
5340 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5341 (VPMOVSXBWrm addr:$src)>;
5342 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5343 (VPMOVSXBWrm addr:$src)>;
5345 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5346 (VPMOVSXWDrm addr:$src)>;
5347 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5348 (VPMOVSXWDrm addr:$src)>;
5349 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5350 (VPMOVSXWDrm addr:$src)>;
5352 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5353 (VPMOVSXDQrm addr:$src)>;
5354 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5355 (VPMOVSXDQrm addr:$src)>;
5356 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5357 (VPMOVSXDQrm addr:$src)>;
5359 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5360 (VPMOVZXBWrm addr:$src)>;
5361 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5362 (VPMOVZXBWrm addr:$src)>;
5363 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5364 (VPMOVZXBWrm addr:$src)>;
5366 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5367 (VPMOVZXWDrm addr:$src)>;
5368 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5369 (VPMOVZXWDrm addr:$src)>;
5370 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5371 (VPMOVZXWDrm addr:$src)>;
5373 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5374 (VPMOVZXDQrm addr:$src)>;
5375 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5376 (VPMOVZXDQrm addr:$src)>;
5377 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5378 (VPMOVZXDQrm addr:$src)>;
5381 let Predicates = [UseSSE41] in {
5382 // Common patterns involving scalar load.
5383 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5384 (PMOVSXBWrm addr:$src)>;
5385 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5386 (PMOVSXBWrm addr:$src)>;
5387 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5388 (PMOVSXBWrm addr:$src)>;
5390 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5391 (PMOVSXWDrm addr:$src)>;
5392 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5393 (PMOVSXWDrm addr:$src)>;
5394 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5395 (PMOVSXWDrm addr:$src)>;
5397 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5398 (PMOVSXDQrm addr:$src)>;
5399 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5400 (PMOVSXDQrm addr:$src)>;
5401 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5402 (PMOVSXDQrm addr:$src)>;
5404 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5405 (PMOVZXBWrm addr:$src)>;
5406 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5407 (PMOVZXBWrm addr:$src)>;
5408 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5409 (PMOVZXBWrm addr:$src)>;
5411 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5412 (PMOVZXWDrm addr:$src)>;
5413 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5414 (PMOVZXWDrm addr:$src)>;
5415 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5416 (PMOVZXWDrm addr:$src)>;
5418 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5419 (PMOVZXDQrm addr:$src)>;
5420 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5421 (PMOVZXDQrm addr:$src)>;
5422 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5423 (PMOVZXDQrm addr:$src)>;
5426 let Predicates = [HasAVX2] in {
5427 let AddedComplexity = 15 in {
5428 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5429 (VPMOVZXDQYrr VR128:$src)>;
5430 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5431 (VPMOVZXWDYrr VR128:$src)>;
5434 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5435 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5438 let Predicates = [HasAVX] in {
5439 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5440 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5443 let Predicates = [UseSSE41] in {
5444 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5445 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5449 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5450 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5451 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5452 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5454 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5455 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5457 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5461 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5463 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5464 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5465 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5467 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5470 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5474 let Predicates = [HasAVX] in {
5475 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5477 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5479 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5481 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5485 let Predicates = [HasAVX2] in {
5486 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5487 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5488 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5489 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5490 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5491 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5492 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5493 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5496 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5497 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5498 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5499 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5501 let Predicates = [HasAVX] in {
5502 // Common patterns involving scalar load
5503 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5504 (VPMOVSXBDrm addr:$src)>;
5505 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5506 (VPMOVSXWQrm addr:$src)>;
5508 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5509 (VPMOVZXBDrm addr:$src)>;
5510 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5511 (VPMOVZXWQrm addr:$src)>;
5514 let Predicates = [UseSSE41] in {
5515 // Common patterns involving scalar load
5516 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5517 (PMOVSXBDrm addr:$src)>;
5518 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5519 (PMOVSXWQrm addr:$src)>;
5521 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5522 (PMOVZXBDrm addr:$src)>;
5523 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5524 (PMOVZXWQrm addr:$src)>;
5527 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5528 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5529 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5530 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5532 // Expecting a i16 load any extended to i32 value.
5533 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5534 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5535 [(set VR128:$dst, (IntId (bitconvert
5536 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5540 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5542 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5544 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5546 // Expecting a i16 load any extended to i32 value.
5547 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5548 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5549 [(set VR256:$dst, (IntId (bitconvert
5550 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5554 let Predicates = [HasAVX] in {
5555 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5557 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5560 let Predicates = [HasAVX2] in {
5561 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5562 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5563 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5564 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5566 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5567 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5569 let Predicates = [HasAVX2] in {
5570 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5571 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5572 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5574 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5575 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5577 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5579 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5580 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5581 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5582 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5583 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5584 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5586 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5587 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5588 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5589 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5591 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5592 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5594 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5595 (VPMOVSXWDYrm addr:$src)>;
5596 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5597 (VPMOVSXDQYrm addr:$src)>;
5599 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5600 (scalar_to_vector (loadi64 addr:$src))))))),
5601 (VPMOVSXBDYrm addr:$src)>;
5602 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5603 (scalar_to_vector (loadf64 addr:$src))))))),
5604 (VPMOVSXBDYrm addr:$src)>;
5606 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5607 (scalar_to_vector (loadi64 addr:$src))))))),
5608 (VPMOVSXWQYrm addr:$src)>;
5609 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5610 (scalar_to_vector (loadf64 addr:$src))))))),
5611 (VPMOVSXWQYrm addr:$src)>;
5613 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5614 (scalar_to_vector (loadi32 addr:$src))))))),
5615 (VPMOVSXBQYrm addr:$src)>;
5618 let Predicates = [HasAVX] in {
5619 // Common patterns involving scalar load
5620 def : Pat<(int_x86_sse41_pmovsxbq
5621 (bitconvert (v4i32 (X86vzmovl
5622 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5623 (VPMOVSXBQrm addr:$src)>;
5625 def : Pat<(int_x86_sse41_pmovzxbq
5626 (bitconvert (v4i32 (X86vzmovl
5627 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5628 (VPMOVZXBQrm addr:$src)>;
5631 let Predicates = [UseSSE41] in {
5632 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5633 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5634 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5636 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5637 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5639 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5641 // Common patterns involving scalar load
5642 def : Pat<(int_x86_sse41_pmovsxbq
5643 (bitconvert (v4i32 (X86vzmovl
5644 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5645 (PMOVSXBQrm addr:$src)>;
5647 def : Pat<(int_x86_sse41_pmovzxbq
5648 (bitconvert (v4i32 (X86vzmovl
5649 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5650 (PMOVZXBQrm addr:$src)>;
5652 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5653 (scalar_to_vector (loadi64 addr:$src))))))),
5654 (PMOVSXWDrm addr:$src)>;
5655 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5656 (scalar_to_vector (loadf64 addr:$src))))))),
5657 (PMOVSXWDrm addr:$src)>;
5658 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5659 (scalar_to_vector (loadi32 addr:$src))))))),
5660 (PMOVSXBDrm addr:$src)>;
5661 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5662 (scalar_to_vector (loadi32 addr:$src))))))),
5663 (PMOVSXWQrm addr:$src)>;
5664 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5665 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5666 (PMOVSXBQrm addr:$src)>;
5667 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5668 (scalar_to_vector (loadi64 addr:$src))))))),
5669 (PMOVSXDQrm addr:$src)>;
5670 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5671 (scalar_to_vector (loadf64 addr:$src))))))),
5672 (PMOVSXDQrm addr:$src)>;
5673 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5674 (scalar_to_vector (loadi64 addr:$src))))))),
5675 (PMOVSXBWrm addr:$src)>;
5676 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5677 (scalar_to_vector (loadf64 addr:$src))))))),
5678 (PMOVSXBWrm addr:$src)>;
5681 let Predicates = [HasAVX2] in {
5682 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5683 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5684 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5686 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5687 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5689 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5691 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5692 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5693 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5694 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5695 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5696 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5698 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5699 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5700 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5701 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5703 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5704 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5707 let Predicates = [HasAVX] in {
5708 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5709 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5710 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5712 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5713 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5715 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5717 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5718 (VPMOVZXBWrm addr:$src)>;
5719 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5720 (VPMOVZXBWrm addr:$src)>;
5721 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5722 (VPMOVZXBDrm addr:$src)>;
5723 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5724 (VPMOVZXBQrm addr:$src)>;
5726 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5727 (VPMOVZXWDrm addr:$src)>;
5728 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5729 (VPMOVZXWDrm addr:$src)>;
5730 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5731 (VPMOVZXWQrm addr:$src)>;
5733 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5734 (VPMOVZXDQrm addr:$src)>;
5735 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5736 (VPMOVZXDQrm addr:$src)>;
5737 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5738 (VPMOVZXDQrm addr:$src)>;
5740 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5741 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5742 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5744 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5745 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5747 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5749 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5750 (scalar_to_vector (loadi64 addr:$src))))))),
5751 (VPMOVSXWDrm addr:$src)>;
5752 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5753 (scalar_to_vector (loadi64 addr:$src))))))),
5754 (VPMOVSXDQrm addr:$src)>;
5755 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5756 (scalar_to_vector (loadf64 addr:$src))))))),
5757 (VPMOVSXWDrm addr:$src)>;
5758 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5759 (scalar_to_vector (loadf64 addr:$src))))))),
5760 (VPMOVSXDQrm addr:$src)>;
5761 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5762 (scalar_to_vector (loadi64 addr:$src))))))),
5763 (VPMOVSXBWrm addr:$src)>;
5764 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5765 (scalar_to_vector (loadf64 addr:$src))))))),
5766 (VPMOVSXBWrm addr:$src)>;
5768 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5769 (scalar_to_vector (loadi32 addr:$src))))))),
5770 (VPMOVSXBDrm addr:$src)>;
5771 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5772 (scalar_to_vector (loadi32 addr:$src))))))),
5773 (VPMOVSXWQrm addr:$src)>;
5774 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5775 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5776 (VPMOVSXBQrm addr:$src)>;
5779 let Predicates = [UseSSE41] in {
5780 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5781 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5782 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5784 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5785 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5787 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5789 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5790 (PMOVZXBWrm addr:$src)>;
5791 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5792 (PMOVZXBWrm addr:$src)>;
5793 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5794 (PMOVZXBDrm addr:$src)>;
5795 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5796 (PMOVZXBQrm addr:$src)>;
5798 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5799 (PMOVZXWDrm addr:$src)>;
5800 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5801 (PMOVZXWDrm addr:$src)>;
5802 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5803 (PMOVZXWQrm addr:$src)>;
5805 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5806 (PMOVZXDQrm addr:$src)>;
5807 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5808 (PMOVZXDQrm addr:$src)>;
5809 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5810 (PMOVZXDQrm addr:$src)>;
5813 //===----------------------------------------------------------------------===//
5814 // SSE4.1 - Extract Instructions
5815 //===----------------------------------------------------------------------===//
5817 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5818 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5819 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5820 (ins VR128:$src1, i32i8imm:$src2),
5821 !strconcat(OpcodeStr,
5822 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5823 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5825 let neverHasSideEffects = 1, mayStore = 1 in
5826 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5827 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5828 !strconcat(OpcodeStr,
5829 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5832 // There's an AssertZext in the way of writing the store pattern
5833 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5836 let Predicates = [HasAVX] in {
5837 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5838 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5839 (ins VR128:$src1, i32i8imm:$src2),
5840 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5843 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5846 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5847 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5848 let neverHasSideEffects = 1, mayStore = 1 in
5849 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5850 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5851 !strconcat(OpcodeStr,
5852 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5855 // There's an AssertZext in the way of writing the store pattern
5856 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5859 let Predicates = [HasAVX] in
5860 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5862 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5865 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5866 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5867 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5868 (ins VR128:$src1, i32i8imm:$src2),
5869 !strconcat(OpcodeStr,
5870 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5872 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5873 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5874 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5875 !strconcat(OpcodeStr,
5876 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5877 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5878 addr:$dst)]>, OpSize;
5881 let Predicates = [HasAVX] in
5882 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5884 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5886 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5887 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5888 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5889 (ins VR128:$src1, i32i8imm:$src2),
5890 !strconcat(OpcodeStr,
5891 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5893 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5894 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5895 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5896 !strconcat(OpcodeStr,
5897 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5898 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5899 addr:$dst)]>, OpSize, REX_W;
5902 let Predicates = [HasAVX] in
5903 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5905 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5907 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5909 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5910 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5911 (ins VR128:$src1, i32i8imm:$src2),
5912 !strconcat(OpcodeStr,
5913 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5915 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5917 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5918 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5919 !strconcat(OpcodeStr,
5920 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5921 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5922 addr:$dst)]>, OpSize;
5925 let ExeDomain = SSEPackedSingle in {
5926 let Predicates = [HasAVX] in {
5927 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5928 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5929 (ins VR128:$src1, i32i8imm:$src2),
5930 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5933 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5936 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5937 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5940 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5942 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5945 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5946 Requires<[UseSSE41]>;
5948 //===----------------------------------------------------------------------===//
5949 // SSE4.1 - Insert Instructions
5950 //===----------------------------------------------------------------------===//
5952 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5953 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5954 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5956 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5958 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5960 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5961 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5962 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5964 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5966 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5968 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5969 imm:$src3))]>, OpSize;
5972 let Predicates = [HasAVX] in
5973 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5974 let Constraints = "$src1 = $dst" in
5975 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5977 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5978 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5979 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5981 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5983 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5985 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5987 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5988 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5990 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5992 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5994 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5995 imm:$src3)))]>, OpSize;
5998 let Predicates = [HasAVX] in
5999 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6000 let Constraints = "$src1 = $dst" in
6001 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6003 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6004 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6005 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6007 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6009 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6011 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6013 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6014 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6016 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6018 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6020 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6021 imm:$src3)))]>, OpSize;
6024 let Predicates = [HasAVX] in
6025 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6026 let Constraints = "$src1 = $dst" in
6027 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6029 // insertps has a few different modes, there's the first two here below which
6030 // are optimized inserts that won't zero arbitrary elements in the destination
6031 // vector. The next one matches the intrinsic and could zero arbitrary elements
6032 // in the target vector.
6033 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6034 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6035 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6037 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6039 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6041 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6043 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6044 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6046 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6048 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6050 (X86insrtps VR128:$src1,
6051 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6052 imm:$src3))]>, OpSize;
6055 let ExeDomain = SSEPackedSingle in {
6056 let Predicates = [HasAVX] in
6057 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6058 let Constraints = "$src1 = $dst" in
6059 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6062 //===----------------------------------------------------------------------===//
6063 // SSE4.1 - Round Instructions
6064 //===----------------------------------------------------------------------===//
6066 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6067 X86MemOperand x86memop, RegisterClass RC,
6068 PatFrag mem_frag32, PatFrag mem_frag64,
6069 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6070 let ExeDomain = SSEPackedSingle in {
6071 // Intrinsic operation, reg.
6072 // Vector intrinsic operation, reg
6073 def PSr : SS4AIi8<opcps, MRMSrcReg,
6074 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6075 !strconcat(OpcodeStr,
6076 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6077 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6080 // Vector intrinsic operation, mem
6081 def PSm : SS4AIi8<opcps, MRMSrcMem,
6082 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6083 !strconcat(OpcodeStr,
6084 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6086 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6088 } // ExeDomain = SSEPackedSingle
6090 let ExeDomain = SSEPackedDouble in {
6091 // Vector intrinsic operation, reg
6092 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6093 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6094 !strconcat(OpcodeStr,
6095 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6096 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6099 // Vector intrinsic operation, mem
6100 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6101 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6102 !strconcat(OpcodeStr,
6103 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6105 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6107 } // ExeDomain = SSEPackedDouble
6110 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6113 Intrinsic F64Int, bit Is2Addr = 1> {
6114 let ExeDomain = GenericDomain in {
6116 let hasSideEffects = 0 in
6117 def SSr : SS4AIi8<opcss, MRMSrcReg,
6118 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6120 !strconcat(OpcodeStr,
6121 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6122 !strconcat(OpcodeStr,
6123 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6126 // Intrinsic operation, reg.
6127 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6128 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6130 !strconcat(OpcodeStr,
6131 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6132 !strconcat(OpcodeStr,
6133 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6134 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6137 // Intrinsic operation, mem.
6138 def SSm : SS4AIi8<opcss, MRMSrcMem,
6139 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6141 !strconcat(OpcodeStr,
6142 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6143 !strconcat(OpcodeStr,
6144 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6146 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6150 let hasSideEffects = 0 in
6151 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6152 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6154 !strconcat(OpcodeStr,
6155 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6156 !strconcat(OpcodeStr,
6157 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6160 // Intrinsic operation, reg.
6161 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6162 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6164 !strconcat(OpcodeStr,
6165 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6166 !strconcat(OpcodeStr,
6167 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6168 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6171 // Intrinsic operation, mem.
6172 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6173 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6175 !strconcat(OpcodeStr,
6176 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6177 !strconcat(OpcodeStr,
6178 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6180 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6182 } // ExeDomain = GenericDomain
6185 // FP round - roundss, roundps, roundsd, roundpd
6186 let Predicates = [HasAVX] in {
6188 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6189 memopv4f32, memopv2f64,
6190 int_x86_sse41_round_ps,
6191 int_x86_sse41_round_pd>, VEX;
6192 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6193 memopv8f32, memopv4f64,
6194 int_x86_avx_round_ps_256,
6195 int_x86_avx_round_pd_256>, VEX, VEX_L;
6196 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6197 int_x86_sse41_round_ss,
6198 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6200 def : Pat<(ffloor FR32:$src),
6201 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6202 def : Pat<(f64 (ffloor FR64:$src)),
6203 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6204 def : Pat<(f32 (fnearbyint FR32:$src)),
6205 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6206 def : Pat<(f64 (fnearbyint FR64:$src)),
6207 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6208 def : Pat<(f32 (fceil FR32:$src)),
6209 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6210 def : Pat<(f64 (fceil FR64:$src)),
6211 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6212 def : Pat<(f32 (frint FR32:$src)),
6213 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6214 def : Pat<(f64 (frint FR64:$src)),
6215 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6216 def : Pat<(f32 (ftrunc FR32:$src)),
6217 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6218 def : Pat<(f64 (ftrunc FR64:$src)),
6219 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6221 def : Pat<(v4f32 (ffloor VR128:$src)),
6222 (VROUNDPSr VR128:$src, (i32 0x1))>;
6223 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6224 (VROUNDPSr VR128:$src, (i32 0xC))>;
6225 def : Pat<(v4f32 (fceil VR128:$src)),
6226 (VROUNDPSr VR128:$src, (i32 0x2))>;
6227 def : Pat<(v4f32 (frint VR128:$src)),
6228 (VROUNDPSr VR128:$src, (i32 0x4))>;
6229 def : Pat<(v4f32 (ftrunc VR128:$src)),
6230 (VROUNDPSr VR128:$src, (i32 0x3))>;
6232 def : Pat<(v2f64 (ffloor VR128:$src)),
6233 (VROUNDPDr VR128:$src, (i32 0x1))>;
6234 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6235 (VROUNDPDr VR128:$src, (i32 0xC))>;
6236 def : Pat<(v2f64 (fceil VR128:$src)),
6237 (VROUNDPDr VR128:$src, (i32 0x2))>;
6238 def : Pat<(v2f64 (frint VR128:$src)),
6239 (VROUNDPDr VR128:$src, (i32 0x4))>;
6240 def : Pat<(v2f64 (ftrunc VR128:$src)),
6241 (VROUNDPDr VR128:$src, (i32 0x3))>;
6243 def : Pat<(v8f32 (ffloor VR256:$src)),
6244 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6245 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6246 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6247 def : Pat<(v8f32 (fceil VR256:$src)),
6248 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6249 def : Pat<(v8f32 (frint VR256:$src)),
6250 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6251 def : Pat<(v8f32 (ftrunc VR256:$src)),
6252 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6254 def : Pat<(v4f64 (ffloor VR256:$src)),
6255 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6256 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6257 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6258 def : Pat<(v4f64 (fceil VR256:$src)),
6259 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6260 def : Pat<(v4f64 (frint VR256:$src)),
6261 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6262 def : Pat<(v4f64 (ftrunc VR256:$src)),
6263 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6266 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6267 memopv4f32, memopv2f64,
6268 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6269 let Constraints = "$src1 = $dst" in
6270 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6271 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6273 let Predicates = [UseSSE41] in {
6274 def : Pat<(ffloor FR32:$src),
6275 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6276 def : Pat<(f64 (ffloor FR64:$src)),
6277 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6278 def : Pat<(f32 (fnearbyint FR32:$src)),
6279 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6280 def : Pat<(f64 (fnearbyint FR64:$src)),
6281 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6282 def : Pat<(f32 (fceil FR32:$src)),
6283 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6284 def : Pat<(f64 (fceil FR64:$src)),
6285 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6286 def : Pat<(f32 (frint FR32:$src)),
6287 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6288 def : Pat<(f64 (frint FR64:$src)),
6289 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6290 def : Pat<(f32 (ftrunc FR32:$src)),
6291 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6292 def : Pat<(f64 (ftrunc FR64:$src)),
6293 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6295 def : Pat<(v4f32 (ffloor VR128:$src)),
6296 (ROUNDPSr VR128:$src, (i32 0x1))>;
6297 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6298 (ROUNDPSr VR128:$src, (i32 0xC))>;
6299 def : Pat<(v4f32 (fceil VR128:$src)),
6300 (ROUNDPSr VR128:$src, (i32 0x2))>;
6301 def : Pat<(v4f32 (frint VR128:$src)),
6302 (ROUNDPSr VR128:$src, (i32 0x4))>;
6303 def : Pat<(v4f32 (ftrunc VR128:$src)),
6304 (ROUNDPSr VR128:$src, (i32 0x3))>;
6306 def : Pat<(v2f64 (ffloor VR128:$src)),
6307 (ROUNDPDr VR128:$src, (i32 0x1))>;
6308 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6309 (ROUNDPDr VR128:$src, (i32 0xC))>;
6310 def : Pat<(v2f64 (fceil VR128:$src)),
6311 (ROUNDPDr VR128:$src, (i32 0x2))>;
6312 def : Pat<(v2f64 (frint VR128:$src)),
6313 (ROUNDPDr VR128:$src, (i32 0x4))>;
6314 def : Pat<(v2f64 (ftrunc VR128:$src)),
6315 (ROUNDPDr VR128:$src, (i32 0x3))>;
6318 //===----------------------------------------------------------------------===//
6319 // SSE4.1 - Packed Bit Test
6320 //===----------------------------------------------------------------------===//
6322 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6323 // the intel intrinsic that corresponds to this.
6324 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6325 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6326 "vptest\t{$src2, $src1|$src1, $src2}",
6327 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6329 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6330 "vptest\t{$src2, $src1|$src1, $src2}",
6331 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6334 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6335 "vptest\t{$src2, $src1|$src1, $src2}",
6336 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6338 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6339 "vptest\t{$src2, $src1|$src1, $src2}",
6340 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6344 let Defs = [EFLAGS] in {
6345 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6346 "ptest\t{$src2, $src1|$src1, $src2}",
6347 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6349 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6350 "ptest\t{$src2, $src1|$src1, $src2}",
6351 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6355 // The bit test instructions below are AVX only
6356 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6357 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6358 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6359 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6360 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6361 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6362 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6363 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6367 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6368 let ExeDomain = SSEPackedSingle in {
6369 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6370 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6373 let ExeDomain = SSEPackedDouble in {
6374 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6375 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6380 //===----------------------------------------------------------------------===//
6381 // SSE4.1 - Misc Instructions
6382 //===----------------------------------------------------------------------===//
6384 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6385 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6386 "popcnt{w}\t{$src, $dst|$dst, $src}",
6387 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6389 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6390 "popcnt{w}\t{$src, $dst|$dst, $src}",
6391 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6392 (implicit EFLAGS)]>, OpSize, XS;
6394 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6395 "popcnt{l}\t{$src, $dst|$dst, $src}",
6396 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6398 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6399 "popcnt{l}\t{$src, $dst|$dst, $src}",
6400 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6401 (implicit EFLAGS)]>, XS;
6403 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6404 "popcnt{q}\t{$src, $dst|$dst, $src}",
6405 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6407 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6408 "popcnt{q}\t{$src, $dst|$dst, $src}",
6409 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6410 (implicit EFLAGS)]>, XS;
6415 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6416 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6417 Intrinsic IntId128> {
6418 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6421 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6422 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6427 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6430 let Predicates = [HasAVX] in
6431 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6432 int_x86_sse41_phminposuw>, VEX;
6433 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6434 int_x86_sse41_phminposuw>;
6436 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6437 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6438 Intrinsic IntId128, bit Is2Addr = 1> {
6439 let isCommutable = 1 in
6440 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6441 (ins VR128:$src1, VR128:$src2),
6443 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6444 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6445 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6446 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6447 (ins VR128:$src1, i128mem:$src2),
6449 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6450 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6452 (IntId128 VR128:$src1,
6453 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6456 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6457 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6458 Intrinsic IntId256> {
6459 let isCommutable = 1 in
6460 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6461 (ins VR256:$src1, VR256:$src2),
6462 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6463 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6464 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6465 (ins VR256:$src1, i256mem:$src2),
6466 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6468 (IntId256 VR256:$src1,
6469 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6473 /// SS48I_binop_rm - Simple SSE41 binary operator.
6474 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6475 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6476 X86MemOperand x86memop, bit Is2Addr = 1> {
6477 let isCommutable = 1 in
6478 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6479 (ins RC:$src1, RC:$src2),
6481 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6482 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6483 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6484 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6485 (ins RC:$src1, x86memop:$src2),
6487 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6488 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6490 (OpVT (OpNode RC:$src1,
6491 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6494 let Predicates = [HasAVX] in {
6495 let isCommutable = 0 in
6496 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6498 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6499 memopv2i64, i128mem, 0>, VEX_4V;
6500 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6501 memopv2i64, i128mem, 0>, VEX_4V;
6502 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6503 memopv2i64, i128mem, 0>, VEX_4V;
6504 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6505 memopv2i64, i128mem, 0>, VEX_4V;
6506 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6507 memopv2i64, i128mem, 0>, VEX_4V;
6508 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6509 memopv2i64, i128mem, 0>, VEX_4V;
6510 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6511 memopv2i64, i128mem, 0>, VEX_4V;
6512 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6513 memopv2i64, i128mem, 0>, VEX_4V;
6514 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6518 let Predicates = [HasAVX2] in {
6519 let isCommutable = 0 in
6520 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6521 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6522 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6523 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6524 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6525 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6526 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6527 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6528 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6529 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6530 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6531 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6532 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6533 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6534 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6535 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6536 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6537 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6538 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6539 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6542 let Constraints = "$src1 = $dst" in {
6543 let isCommutable = 0 in
6544 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6545 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6546 memopv2i64, i128mem>;
6547 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6548 memopv2i64, i128mem>;
6549 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6550 memopv2i64, i128mem>;
6551 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6552 memopv2i64, i128mem>;
6553 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6554 memopv2i64, i128mem>;
6555 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6556 memopv2i64, i128mem>;
6557 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6558 memopv2i64, i128mem>;
6559 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6560 memopv2i64, i128mem>;
6561 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6564 let Predicates = [HasAVX] in {
6565 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6566 memopv2i64, i128mem, 0>, VEX_4V;
6567 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6568 memopv2i64, i128mem, 0>, VEX_4V;
6570 let Predicates = [HasAVX2] in {
6571 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6572 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6573 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6574 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6577 let Constraints = "$src1 = $dst" in {
6578 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6579 memopv2i64, i128mem>;
6580 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6581 memopv2i64, i128mem>;
6584 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6585 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6586 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6587 X86MemOperand x86memop, bit Is2Addr = 1> {
6588 let isCommutable = 1 in
6589 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6590 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6592 !strconcat(OpcodeStr,
6593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6594 !strconcat(OpcodeStr,
6595 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6596 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6598 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6599 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6601 !strconcat(OpcodeStr,
6602 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6603 !strconcat(OpcodeStr,
6604 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6607 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6611 let Predicates = [HasAVX] in {
6612 let isCommutable = 0 in {
6613 let ExeDomain = SSEPackedSingle in {
6614 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6615 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6616 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6617 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6618 f256mem, 0>, VEX_4V, VEX_L;
6620 let ExeDomain = SSEPackedDouble in {
6621 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6622 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6623 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6624 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6625 f256mem, 0>, VEX_4V, VEX_L;
6627 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6628 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6629 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6630 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6632 let ExeDomain = SSEPackedSingle in
6633 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6634 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6635 let ExeDomain = SSEPackedDouble in
6636 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6637 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6638 let ExeDomain = SSEPackedSingle in
6639 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6640 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6643 let Predicates = [HasAVX2] in {
6644 let isCommutable = 0 in {
6645 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6646 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6647 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6648 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6652 let Constraints = "$src1 = $dst" in {
6653 let isCommutable = 0 in {
6654 let ExeDomain = SSEPackedSingle in
6655 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6656 VR128, memopv4f32, f128mem>;
6657 let ExeDomain = SSEPackedDouble in
6658 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6659 VR128, memopv2f64, f128mem>;
6660 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6661 VR128, memopv2i64, i128mem>;
6662 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6663 VR128, memopv2i64, i128mem>;
6665 let ExeDomain = SSEPackedSingle in
6666 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6667 VR128, memopv4f32, f128mem>;
6668 let ExeDomain = SSEPackedDouble in
6669 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6670 VR128, memopv2f64, f128mem>;
6673 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6674 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6675 RegisterClass RC, X86MemOperand x86memop,
6676 PatFrag mem_frag, Intrinsic IntId> {
6677 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6678 (ins RC:$src1, RC:$src2, RC:$src3),
6679 !strconcat(OpcodeStr,
6680 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6681 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6682 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6684 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6685 (ins RC:$src1, x86memop:$src2, RC:$src3),
6686 !strconcat(OpcodeStr,
6687 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6689 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6691 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6694 let Predicates = [HasAVX] in {
6695 let ExeDomain = SSEPackedDouble in {
6696 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6697 memopv2f64, int_x86_sse41_blendvpd>;
6698 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6699 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6700 } // ExeDomain = SSEPackedDouble
6701 let ExeDomain = SSEPackedSingle in {
6702 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6703 memopv4f32, int_x86_sse41_blendvps>;
6704 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6705 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6706 } // ExeDomain = SSEPackedSingle
6707 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6708 memopv2i64, int_x86_sse41_pblendvb>;
6711 let Predicates = [HasAVX2] in {
6712 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6713 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6716 let Predicates = [HasAVX] in {
6717 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6718 (v16i8 VR128:$src2))),
6719 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6720 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6721 (v4i32 VR128:$src2))),
6722 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6723 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6724 (v4f32 VR128:$src2))),
6725 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6726 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6727 (v2i64 VR128:$src2))),
6728 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6729 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6730 (v2f64 VR128:$src2))),
6731 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6732 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6733 (v8i32 VR256:$src2))),
6734 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6735 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6736 (v8f32 VR256:$src2))),
6737 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6738 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6739 (v4i64 VR256:$src2))),
6740 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6741 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6742 (v4f64 VR256:$src2))),
6743 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6745 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6747 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6748 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6750 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6752 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6754 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6755 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6757 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6758 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6760 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6763 let Predicates = [HasAVX2] in {
6764 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6765 (v32i8 VR256:$src2))),
6766 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6767 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6769 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6772 /// SS41I_ternary_int - SSE 4.1 ternary operator
6773 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6774 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6775 X86MemOperand x86memop, Intrinsic IntId> {
6776 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6777 (ins VR128:$src1, VR128:$src2),
6778 !strconcat(OpcodeStr,
6779 "\t{$src2, $dst|$dst, $src2}"),
6780 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6783 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6784 (ins VR128:$src1, x86memop:$src2),
6785 !strconcat(OpcodeStr,
6786 "\t{$src2, $dst|$dst, $src2}"),
6789 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6793 let ExeDomain = SSEPackedDouble in
6794 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6795 int_x86_sse41_blendvpd>;
6796 let ExeDomain = SSEPackedSingle in
6797 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6798 int_x86_sse41_blendvps>;
6799 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6800 int_x86_sse41_pblendvb>;
6802 // Aliases with the implicit xmm0 argument
6803 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6804 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6805 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6806 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6807 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6808 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6809 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6810 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6811 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6812 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6813 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6814 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6816 let Predicates = [UseSSE41] in {
6817 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6818 (v16i8 VR128:$src2))),
6819 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6820 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6821 (v4i32 VR128:$src2))),
6822 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6823 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6824 (v4f32 VR128:$src2))),
6825 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6826 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6827 (v2i64 VR128:$src2))),
6828 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6829 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6830 (v2f64 VR128:$src2))),
6831 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6833 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6835 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6836 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6838 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6839 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6841 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6845 let Predicates = [HasAVX] in
6846 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6847 "vmovntdqa\t{$src, $dst|$dst, $src}",
6848 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6850 let Predicates = [HasAVX2] in
6851 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6852 "vmovntdqa\t{$src, $dst|$dst, $src}",
6853 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6855 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6856 "movntdqa\t{$src, $dst|$dst, $src}",
6857 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6860 //===----------------------------------------------------------------------===//
6861 // SSE4.2 - Compare Instructions
6862 //===----------------------------------------------------------------------===//
6864 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6865 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6866 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6867 X86MemOperand x86memop, bit Is2Addr = 1> {
6868 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6869 (ins RC:$src1, RC:$src2),
6871 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6872 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6873 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6875 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6876 (ins RC:$src1, x86memop:$src2),
6878 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6879 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6881 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6884 let Predicates = [HasAVX] in
6885 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6886 memopv2i64, i128mem, 0>, VEX_4V;
6888 let Predicates = [HasAVX2] in
6889 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6890 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6892 let Constraints = "$src1 = $dst" in
6893 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6894 memopv2i64, i128mem>;
6896 //===----------------------------------------------------------------------===//
6897 // SSE4.2 - String/text Processing Instructions
6898 //===----------------------------------------------------------------------===//
6900 // Packed Compare Implicit Length Strings, Return Mask
6901 multiclass pseudo_pcmpistrm<string asm> {
6902 def REG : PseudoI<(outs VR128:$dst),
6903 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6904 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6906 def MEM : PseudoI<(outs VR128:$dst),
6907 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6908 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
6909 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6912 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6913 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6914 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6917 multiclass pcmpistrm_SS42AI<string asm> {
6918 def rr : SS42AI<0x62, MRMSrcReg, (outs),
6919 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6920 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6923 def rm :SS42AI<0x62, MRMSrcMem, (outs),
6924 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6925 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6929 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6930 let Predicates = [HasAVX] in
6931 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
6932 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
6935 // Packed Compare Explicit Length Strings, Return Mask
6936 multiclass pseudo_pcmpestrm<string asm> {
6937 def REG : PseudoI<(outs VR128:$dst),
6938 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6939 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6940 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6941 def MEM : PseudoI<(outs VR128:$dst),
6942 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6943 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
6944 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
6947 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6948 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6949 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6952 multiclass SS42AI_pcmpestrm<string asm> {
6953 def rr : SS42AI<0x60, MRMSrcReg, (outs),
6954 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6955 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6958 def rm : SS42AI<0x60, MRMSrcMem, (outs),
6959 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6960 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6964 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6965 let Predicates = [HasAVX] in
6966 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
6967 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
6970 // Packed Compare Implicit Length Strings, Return Index
6971 multiclass pseudo_pcmpistri<string asm> {
6972 def REG : PseudoI<(outs GR32:$dst),
6973 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6974 [(set GR32:$dst, EFLAGS,
6975 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
6976 def MEM : PseudoI<(outs GR32:$dst),
6977 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6978 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
6979 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6982 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6983 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
6984 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
6987 multiclass SS42AI_pcmpistri<string asm> {
6988 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6989 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6990 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6993 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6994 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6995 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6999 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7000 let Predicates = [HasAVX] in
7001 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7002 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7005 // Packed Compare Explicit Length Strings, Return Index
7006 multiclass pseudo_pcmpestri<string asm> {
7007 def REG : PseudoI<(outs GR32:$dst),
7008 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7009 [(set GR32:$dst, EFLAGS,
7010 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7011 def MEM : PseudoI<(outs GR32:$dst),
7012 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7013 [(set GR32:$dst, EFLAGS,
7014 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7018 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7019 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7020 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7023 multiclass SS42AI_pcmpestri<string asm> {
7024 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7025 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7026 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7029 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7030 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7031 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7035 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7036 let Predicates = [HasAVX] in
7037 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7038 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7041 //===----------------------------------------------------------------------===//
7042 // SSE4.2 - CRC Instructions
7043 //===----------------------------------------------------------------------===//
7045 // No CRC instructions have AVX equivalents
7047 // crc intrinsic instruction
7048 // This set of instructions are only rm, the only difference is the size
7050 let Constraints = "$src1 = $dst" in {
7051 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7052 (ins GR32:$src1, i8mem:$src2),
7053 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7055 (int_x86_sse42_crc32_32_8 GR32:$src1,
7056 (load addr:$src2)))]>;
7057 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7058 (ins GR32:$src1, GR8:$src2),
7059 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7061 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7062 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7063 (ins GR32:$src1, i16mem:$src2),
7064 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7066 (int_x86_sse42_crc32_32_16 GR32:$src1,
7067 (load addr:$src2)))]>,
7069 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7070 (ins GR32:$src1, GR16:$src2),
7071 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7073 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7075 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7076 (ins GR32:$src1, i32mem:$src2),
7077 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7079 (int_x86_sse42_crc32_32_32 GR32:$src1,
7080 (load addr:$src2)))]>;
7081 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7082 (ins GR32:$src1, GR32:$src2),
7083 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7085 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7086 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7087 (ins GR64:$src1, i8mem:$src2),
7088 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7090 (int_x86_sse42_crc32_64_8 GR64:$src1,
7091 (load addr:$src2)))]>,
7093 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7094 (ins GR64:$src1, GR8:$src2),
7095 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7097 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7099 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7100 (ins GR64:$src1, i64mem:$src2),
7101 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7103 (int_x86_sse42_crc32_64_64 GR64:$src1,
7104 (load addr:$src2)))]>,
7106 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7107 (ins GR64:$src1, GR64:$src2),
7108 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7110 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7114 //===----------------------------------------------------------------------===//
7115 // AES-NI Instructions
7116 //===----------------------------------------------------------------------===//
7118 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7119 Intrinsic IntId128, bit Is2Addr = 1> {
7120 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7121 (ins VR128:$src1, VR128:$src2),
7123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7125 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7127 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7128 (ins VR128:$src1, i128mem:$src2),
7130 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7131 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7133 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7136 // Perform One Round of an AES Encryption/Decryption Flow
7137 let Predicates = [HasAVX, HasAES] in {
7138 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7139 int_x86_aesni_aesenc, 0>, VEX_4V;
7140 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7141 int_x86_aesni_aesenclast, 0>, VEX_4V;
7142 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7143 int_x86_aesni_aesdec, 0>, VEX_4V;
7144 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7145 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7148 let Constraints = "$src1 = $dst" in {
7149 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7150 int_x86_aesni_aesenc>;
7151 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7152 int_x86_aesni_aesenclast>;
7153 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7154 int_x86_aesni_aesdec>;
7155 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7156 int_x86_aesni_aesdeclast>;
7159 // Perform the AES InvMixColumn Transformation
7160 let Predicates = [HasAVX, HasAES] in {
7161 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7163 "vaesimc\t{$src1, $dst|$dst, $src1}",
7165 (int_x86_aesni_aesimc VR128:$src1))]>,
7167 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7168 (ins i128mem:$src1),
7169 "vaesimc\t{$src1, $dst|$dst, $src1}",
7170 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7173 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7175 "aesimc\t{$src1, $dst|$dst, $src1}",
7177 (int_x86_aesni_aesimc VR128:$src1))]>,
7179 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7180 (ins i128mem:$src1),
7181 "aesimc\t{$src1, $dst|$dst, $src1}",
7182 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7185 // AES Round Key Generation Assist
7186 let Predicates = [HasAVX, HasAES] in {
7187 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7188 (ins VR128:$src1, i8imm:$src2),
7189 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7191 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7193 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7194 (ins i128mem:$src1, i8imm:$src2),
7195 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7197 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7200 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7201 (ins VR128:$src1, i8imm:$src2),
7202 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7204 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7206 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7207 (ins i128mem:$src1, i8imm:$src2),
7208 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7210 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7213 //===----------------------------------------------------------------------===//
7214 // PCLMUL Instructions
7215 //===----------------------------------------------------------------------===//
7217 // AVX carry-less Multiplication instructions
7218 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7219 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7220 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7222 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7224 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7225 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7226 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7227 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7228 (memopv2i64 addr:$src2), imm:$src3))]>;
7230 // Carry-less Multiplication instructions
7231 let Constraints = "$src1 = $dst" in {
7232 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7233 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7234 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7236 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7238 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7239 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7240 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7241 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7242 (memopv2i64 addr:$src2), imm:$src3))]>;
7243 } // Constraints = "$src1 = $dst"
7246 multiclass pclmul_alias<string asm, int immop> {
7247 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7248 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7250 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7251 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7253 def : InstAlias<!strconcat("vpclmul", asm,
7254 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7255 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7257 def : InstAlias<!strconcat("vpclmul", asm,
7258 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7259 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7261 defm : pclmul_alias<"hqhq", 0x11>;
7262 defm : pclmul_alias<"hqlq", 0x01>;
7263 defm : pclmul_alias<"lqhq", 0x10>;
7264 defm : pclmul_alias<"lqlq", 0x00>;
7266 //===----------------------------------------------------------------------===//
7267 // SSE4A Instructions
7268 //===----------------------------------------------------------------------===//
7270 let Predicates = [HasSSE4A] in {
7272 let Constraints = "$src = $dst" in {
7273 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7274 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7275 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7276 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7277 imm:$idx))]>, TB, OpSize;
7278 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7279 (ins VR128:$src, VR128:$mask),
7280 "extrq\t{$mask, $src|$src, $mask}",
7281 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7282 VR128:$mask))]>, TB, OpSize;
7284 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7285 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7286 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7287 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7288 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7289 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7290 (ins VR128:$src, VR128:$mask),
7291 "insertq\t{$mask, $src|$src, $mask}",
7292 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7293 VR128:$mask))]>, XD;
7296 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7297 "movntss\t{$src, $dst|$dst, $src}",
7298 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7300 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7301 "movntsd\t{$src, $dst|$dst, $src}",
7302 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7305 //===----------------------------------------------------------------------===//
7307 //===----------------------------------------------------------------------===//
7309 //===----------------------------------------------------------------------===//
7310 // VBROADCAST - Load from memory and broadcast to all elements of the
7311 // destination operand
7313 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7314 X86MemOperand x86memop, Intrinsic Int> :
7315 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7316 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7317 [(set RC:$dst, (Int addr:$src))]>, VEX;
7319 // AVX2 adds register forms
7320 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7322 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7324 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7326 let ExeDomain = SSEPackedSingle in {
7327 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7328 int_x86_avx_vbroadcast_ss>;
7329 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7330 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7332 let ExeDomain = SSEPackedDouble in
7333 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7334 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7335 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7336 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7338 let ExeDomain = SSEPackedSingle in {
7339 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7340 int_x86_avx2_vbroadcast_ss_ps>;
7341 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7342 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7344 let ExeDomain = SSEPackedDouble in
7345 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7346 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7348 let Predicates = [HasAVX2] in
7349 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7350 int_x86_avx2_vbroadcasti128>, VEX_L;
7352 let Predicates = [HasAVX] in
7353 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7354 (VBROADCASTF128 addr:$src)>;
7357 //===----------------------------------------------------------------------===//
7358 // VINSERTF128 - Insert packed floating-point values
7360 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7361 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7362 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7363 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7366 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7367 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7368 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7372 let Predicates = [HasAVX] in {
7373 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7375 (VINSERTF128rr VR256:$src1, VR128:$src2,
7376 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7377 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7379 (VINSERTF128rr VR256:$src1, VR128:$src2,
7380 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7382 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7384 (VINSERTF128rm VR256:$src1, addr:$src2,
7385 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7386 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7388 (VINSERTF128rm VR256:$src1, addr:$src2,
7389 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7392 let Predicates = [HasAVX1Only] in {
7393 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7395 (VINSERTF128rr VR256:$src1, VR128:$src2,
7396 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7397 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7399 (VINSERTF128rr VR256:$src1, VR128:$src2,
7400 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7401 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7403 (VINSERTF128rr VR256:$src1, VR128:$src2,
7404 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7405 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7407 (VINSERTF128rr VR256:$src1, VR128:$src2,
7408 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7410 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7412 (VINSERTF128rm VR256:$src1, addr:$src2,
7413 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7414 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7415 (bc_v4i32 (memopv2i64 addr:$src2)),
7417 (VINSERTF128rm VR256:$src1, addr:$src2,
7418 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7419 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7420 (bc_v16i8 (memopv2i64 addr:$src2)),
7422 (VINSERTF128rm VR256:$src1, addr:$src2,
7423 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7424 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7425 (bc_v8i16 (memopv2i64 addr:$src2)),
7427 (VINSERTF128rm VR256:$src1, addr:$src2,
7428 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7431 //===----------------------------------------------------------------------===//
7432 // VEXTRACTF128 - Extract packed floating-point values
7434 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7435 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7436 (ins VR256:$src1, i8imm:$src2),
7437 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7440 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7441 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7442 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7447 let Predicates = [HasAVX] in {
7448 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7449 (v4f32 (VEXTRACTF128rr
7450 (v8f32 VR256:$src1),
7451 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7452 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7453 (v2f64 (VEXTRACTF128rr
7454 (v4f64 VR256:$src1),
7455 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7457 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7458 (iPTR imm))), addr:$dst),
7459 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7460 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7461 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7462 (iPTR imm))), addr:$dst),
7463 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7464 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7467 let Predicates = [HasAVX1Only] in {
7468 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7469 (v2i64 (VEXTRACTF128rr
7470 (v4i64 VR256:$src1),
7471 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7472 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7473 (v4i32 (VEXTRACTF128rr
7474 (v8i32 VR256:$src1),
7475 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7476 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7477 (v8i16 (VEXTRACTF128rr
7478 (v16i16 VR256:$src1),
7479 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7480 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7481 (v16i8 (VEXTRACTF128rr
7482 (v32i8 VR256:$src1),
7483 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7485 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7486 (iPTR imm))), addr:$dst),
7487 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7488 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7489 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7490 (iPTR imm))), addr:$dst),
7491 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7492 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7493 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7494 (iPTR imm))), addr:$dst),
7495 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7496 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7497 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7498 (iPTR imm))), addr:$dst),
7499 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7500 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7503 //===----------------------------------------------------------------------===//
7504 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7506 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7507 Intrinsic IntLd, Intrinsic IntLd256,
7508 Intrinsic IntSt, Intrinsic IntSt256> {
7509 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7510 (ins VR128:$src1, f128mem:$src2),
7511 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7512 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7514 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7515 (ins VR256:$src1, f256mem:$src2),
7516 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7517 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7519 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7520 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7521 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7522 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7523 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7524 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7526 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7529 let ExeDomain = SSEPackedSingle in
7530 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7531 int_x86_avx_maskload_ps,
7532 int_x86_avx_maskload_ps_256,
7533 int_x86_avx_maskstore_ps,
7534 int_x86_avx_maskstore_ps_256>;
7535 let ExeDomain = SSEPackedDouble in
7536 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7537 int_x86_avx_maskload_pd,
7538 int_x86_avx_maskload_pd_256,
7539 int_x86_avx_maskstore_pd,
7540 int_x86_avx_maskstore_pd_256>;
7542 //===----------------------------------------------------------------------===//
7543 // VPERMIL - Permute Single and Double Floating-Point Values
7545 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7546 RegisterClass RC, X86MemOperand x86memop_f,
7547 X86MemOperand x86memop_i, PatFrag i_frag,
7548 Intrinsic IntVar, ValueType vt> {
7549 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7550 (ins RC:$src1, RC:$src2),
7551 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7552 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7553 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7554 (ins RC:$src1, x86memop_i:$src2),
7555 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7556 [(set RC:$dst, (IntVar RC:$src1,
7557 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7559 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7560 (ins RC:$src1, i8imm:$src2),
7561 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7562 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7563 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7564 (ins x86memop_f:$src1, i8imm:$src2),
7565 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7567 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7570 let ExeDomain = SSEPackedSingle in {
7571 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7572 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7573 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7574 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7576 let ExeDomain = SSEPackedDouble in {
7577 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7578 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7579 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7580 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7583 let Predicates = [HasAVX] in {
7584 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7585 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7586 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7587 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7588 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7590 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7591 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7592 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7594 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7595 (VPERMILPDri VR128:$src1, imm:$imm)>;
7596 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7597 (VPERMILPDmi addr:$src1, imm:$imm)>;
7600 //===----------------------------------------------------------------------===//
7601 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7603 let ExeDomain = SSEPackedSingle in {
7604 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7605 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7606 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7607 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7608 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7609 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7610 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7611 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7612 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7613 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7616 let Predicates = [HasAVX] in {
7617 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7618 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7619 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7620 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7621 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7624 let Predicates = [HasAVX1Only] in {
7625 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7626 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7627 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7628 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7629 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7630 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7631 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7632 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7634 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7635 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7636 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7637 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7638 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7639 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7640 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7641 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7642 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7643 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7644 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7645 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7648 //===----------------------------------------------------------------------===//
7649 // VZERO - Zero YMM registers
7651 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7652 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7653 // Zero All YMM registers
7654 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7655 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7657 // Zero Upper bits of YMM registers
7658 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7659 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7662 //===----------------------------------------------------------------------===//
7663 // Half precision conversion instructions
7664 //===----------------------------------------------------------------------===//
7665 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7666 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7667 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7668 [(set RC:$dst, (Int VR128:$src))]>,
7670 let neverHasSideEffects = 1, mayLoad = 1 in
7671 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7672 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7675 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7676 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7677 (ins RC:$src1, i32i8imm:$src2),
7678 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7679 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7681 let neverHasSideEffects = 1, mayStore = 1 in
7682 def mr : Ii8<0x1D, MRMDestMem, (outs),
7683 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7684 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7688 let Predicates = [HasAVX, HasF16C] in {
7689 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7690 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7691 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7692 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7695 //===----------------------------------------------------------------------===//
7696 // AVX2 Instructions
7697 //===----------------------------------------------------------------------===//
7699 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7700 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7701 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7702 X86MemOperand x86memop> {
7703 let isCommutable = 1 in
7704 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7705 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7706 !strconcat(OpcodeStr,
7707 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7708 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7710 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7711 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7712 !strconcat(OpcodeStr,
7713 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7716 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7720 let isCommutable = 0 in {
7721 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7722 VR128, memopv2i64, i128mem>;
7723 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7724 VR256, memopv4i64, i256mem>, VEX_L;
7727 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7729 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7730 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7732 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7734 //===----------------------------------------------------------------------===//
7735 // VPBROADCAST - Load from memory and broadcast to all elements of the
7736 // destination operand
7738 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7739 X86MemOperand x86memop, PatFrag ld_frag,
7740 Intrinsic Int128, Intrinsic Int256> {
7741 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7742 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7743 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7744 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7747 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7748 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7749 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7750 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7751 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7754 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7758 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7759 int_x86_avx2_pbroadcastb_128,
7760 int_x86_avx2_pbroadcastb_256>;
7761 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7762 int_x86_avx2_pbroadcastw_128,
7763 int_x86_avx2_pbroadcastw_256>;
7764 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7765 int_x86_avx2_pbroadcastd_128,
7766 int_x86_avx2_pbroadcastd_256>;
7767 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7768 int_x86_avx2_pbroadcastq_128,
7769 int_x86_avx2_pbroadcastq_256>;
7771 let Predicates = [HasAVX2] in {
7772 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7773 (VPBROADCASTBrm addr:$src)>;
7774 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7775 (VPBROADCASTBYrm addr:$src)>;
7776 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7777 (VPBROADCASTWrm addr:$src)>;
7778 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7779 (VPBROADCASTWYrm addr:$src)>;
7780 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7781 (VPBROADCASTDrm addr:$src)>;
7782 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7783 (VPBROADCASTDYrm addr:$src)>;
7784 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7785 (VPBROADCASTQrm addr:$src)>;
7786 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7787 (VPBROADCASTQYrm addr:$src)>;
7789 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7790 (VPBROADCASTBrr VR128:$src)>;
7791 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7792 (VPBROADCASTBYrr VR128:$src)>;
7793 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7794 (VPBROADCASTWrr VR128:$src)>;
7795 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7796 (VPBROADCASTWYrr VR128:$src)>;
7797 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7798 (VPBROADCASTDrr VR128:$src)>;
7799 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7800 (VPBROADCASTDYrr VR128:$src)>;
7801 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7802 (VPBROADCASTQrr VR128:$src)>;
7803 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7804 (VPBROADCASTQYrr VR128:$src)>;
7805 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7806 (VBROADCASTSSrr VR128:$src)>;
7807 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7808 (VBROADCASTSSYrr VR128:$src)>;
7809 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7810 (VPBROADCASTQrr VR128:$src)>;
7811 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7812 (VBROADCASTSDYrr VR128:$src)>;
7814 // Provide fallback in case the load node that is used in the patterns above
7815 // is used by additional users, which prevents the pattern selection.
7816 let AddedComplexity = 20 in {
7817 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7818 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7819 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7820 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7821 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7822 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7824 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7825 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7826 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7827 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7828 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7829 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7833 // AVX1 broadcast patterns
7834 let Predicates = [HasAVX1Only] in {
7835 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7836 (VBROADCASTSSYrm addr:$src)>;
7837 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7838 (VBROADCASTSDYrm addr:$src)>;
7839 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7840 (VBROADCASTSSrm addr:$src)>;
7843 let Predicates = [HasAVX] in {
7844 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7845 (VBROADCASTSSYrm addr:$src)>;
7846 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7847 (VBROADCASTSDYrm addr:$src)>;
7848 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7849 (VBROADCASTSSrm addr:$src)>;
7851 // Provide fallback in case the load node that is used in the patterns above
7852 // is used by additional users, which prevents the pattern selection.
7853 let AddedComplexity = 20 in {
7854 // 128bit broadcasts:
7855 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7856 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7857 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7858 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7859 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7860 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7861 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7862 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7863 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7864 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7866 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7867 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7868 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7869 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7870 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7871 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7872 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7873 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7874 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7875 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7879 //===----------------------------------------------------------------------===//
7880 // VPERM - Permute instructions
7883 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7885 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7886 (ins VR256:$src1, VR256:$src2),
7887 !strconcat(OpcodeStr,
7888 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7890 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
7892 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7893 (ins VR256:$src1, i256mem:$src2),
7894 !strconcat(OpcodeStr,
7895 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7897 (OpVT (X86VPermv VR256:$src1,
7898 (bitconvert (mem_frag addr:$src2)))))]>,
7902 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7903 let ExeDomain = SSEPackedSingle in
7904 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7906 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7908 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7909 (ins VR256:$src1, i8imm:$src2),
7910 !strconcat(OpcodeStr,
7911 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7913 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
7915 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7916 (ins i256mem:$src1, i8imm:$src2),
7917 !strconcat(OpcodeStr,
7918 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7920 (OpVT (X86VPermi (mem_frag addr:$src1),
7921 (i8 imm:$src2))))]>, VEX, VEX_L;
7924 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7925 let ExeDomain = SSEPackedDouble in
7926 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7928 //===----------------------------------------------------------------------===//
7929 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7931 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7932 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7933 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7934 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7935 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7936 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7937 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7938 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7939 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7940 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7942 let Predicates = [HasAVX2] in {
7943 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7944 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7945 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7946 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7947 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7948 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7950 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7952 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7953 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7954 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7955 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7956 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7958 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7962 //===----------------------------------------------------------------------===//
7963 // VINSERTI128 - Insert packed integer values
7965 let neverHasSideEffects = 1 in {
7966 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7967 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7968 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7971 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7972 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7973 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7977 let Predicates = [HasAVX2] in {
7978 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7980 (VINSERTI128rr VR256:$src1, VR128:$src2,
7981 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7982 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7984 (VINSERTI128rr VR256:$src1, VR128:$src2,
7985 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7986 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7988 (VINSERTI128rr VR256:$src1, VR128:$src2,
7989 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7990 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7992 (VINSERTI128rr VR256:$src1, VR128:$src2,
7993 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7995 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7997 (VINSERTI128rm VR256:$src1, addr:$src2,
7998 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7999 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
8000 (bc_v4i32 (memopv2i64 addr:$src2)),
8002 (VINSERTI128rm VR256:$src1, addr:$src2,
8003 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8004 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
8005 (bc_v16i8 (memopv2i64 addr:$src2)),
8007 (VINSERTI128rm VR256:$src1, addr:$src2,
8008 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8009 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
8010 (bc_v8i16 (memopv2i64 addr:$src2)),
8012 (VINSERTI128rm VR256:$src1, addr:$src2,
8013 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8016 //===----------------------------------------------------------------------===//
8017 // VEXTRACTI128 - Extract packed integer values
8019 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8020 (ins VR256:$src1, i8imm:$src2),
8021 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8023 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8025 let neverHasSideEffects = 1, mayStore = 1 in
8026 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8027 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8028 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8031 let Predicates = [HasAVX2] in {
8032 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8033 (v2i64 (VEXTRACTI128rr
8034 (v4i64 VR256:$src1),
8035 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8036 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8037 (v4i32 (VEXTRACTI128rr
8038 (v8i32 VR256:$src1),
8039 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8040 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8041 (v8i16 (VEXTRACTI128rr
8042 (v16i16 VR256:$src1),
8043 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8044 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8045 (v16i8 (VEXTRACTI128rr
8046 (v32i8 VR256:$src1),
8047 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8049 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8050 (iPTR imm))), addr:$dst),
8051 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8052 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8053 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8054 (iPTR imm))), addr:$dst),
8055 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8056 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8057 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8058 (iPTR imm))), addr:$dst),
8059 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8060 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8061 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8062 (iPTR imm))), addr:$dst),
8063 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8064 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8067 //===----------------------------------------------------------------------===//
8068 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8070 multiclass avx2_pmovmask<string OpcodeStr,
8071 Intrinsic IntLd128, Intrinsic IntLd256,
8072 Intrinsic IntSt128, Intrinsic IntSt256> {
8073 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8074 (ins VR128:$src1, i128mem:$src2),
8075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8076 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8077 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8078 (ins VR256:$src1, i256mem:$src2),
8079 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8080 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8082 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8083 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8085 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8086 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8087 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8089 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8092 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8093 int_x86_avx2_maskload_d,
8094 int_x86_avx2_maskload_d_256,
8095 int_x86_avx2_maskstore_d,
8096 int_x86_avx2_maskstore_d_256>;
8097 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8098 int_x86_avx2_maskload_q,
8099 int_x86_avx2_maskload_q_256,
8100 int_x86_avx2_maskstore_q,
8101 int_x86_avx2_maskstore_q_256>, VEX_W;
8104 //===----------------------------------------------------------------------===//
8105 // Variable Bit Shifts
8107 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8108 ValueType vt128, ValueType vt256> {
8109 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8110 (ins VR128:$src1, VR128:$src2),
8111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8113 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8115 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8116 (ins VR128:$src1, i128mem:$src2),
8117 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8119 (vt128 (OpNode VR128:$src1,
8120 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8122 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8123 (ins VR256:$src1, VR256:$src2),
8124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8126 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8128 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8129 (ins VR256:$src1, i256mem:$src2),
8130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8132 (vt256 (OpNode VR256:$src1,
8133 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8137 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8138 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8139 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8140 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8141 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8143 //===----------------------------------------------------------------------===//
8144 // VGATHER - GATHER Operations
8145 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8146 X86MemOperand memop128, X86MemOperand memop256> {
8147 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8148 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8149 !strconcat(OpcodeStr,
8150 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8152 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8153 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8154 !strconcat(OpcodeStr,
8155 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8156 []>, VEX_4VOp3, VEX_L;
8159 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8160 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8161 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8162 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8163 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8164 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8165 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8166 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8167 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;