1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instructions that map zero vector to pxor / xorp* for sse.
264 // We set canFoldAsLoad because this can be converted to a constant-pool
265 // load of an all-zeros value if folding it would be beneficial.
266 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
267 // JIT implementation, it does not expand the instructions below like
268 // X86MCInstLower does.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isCodeGenOnly = 1 in {
271 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
272 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
273 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
274 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
275 let ExeDomain = SSEPackedInt in
276 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
277 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
280 // The same as done above but for AVX. The 128-bit versions are the
281 // same, but re-encoded. The 256-bit does not support PI version, and
282 // doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
291 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
293 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
294 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
295 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
296 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
297 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 let ExeDomain = SSEPackedInt in
299 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
300 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
303 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
304 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
305 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
307 // AVX has no support for 256-bit integer instructions, but since the 128-bit
308 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
309 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
310 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
311 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
313 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
314 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
315 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
317 // We set canFoldAsLoad because this can be converted to a constant-pool
318 // load of an all-ones value if folding it would be beneficial.
319 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
320 // JIT implementation, it does not expand the instructions below like
321 // X86MCInstLower does.
322 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
323 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
324 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
325 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
326 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
327 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
332 //===----------------------------------------------------------------------===//
333 // SSE 1 & 2 - Move FP Scalar Instructions
335 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
336 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
337 // is used instead. Register-to-register movss/movsd is not modeled as an
338 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
339 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
340 //===----------------------------------------------------------------------===//
342 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
343 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
344 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
346 // Loading from memory automatically zeroing upper bits.
347 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
348 PatFrag mem_pat, string OpcodeStr> :
349 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
350 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
351 [(set RC:$dst, (mem_pat addr:$src))]>;
354 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
355 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
356 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
357 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
359 // For the disassembler
360 let isCodeGenOnly = 1 in {
361 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
362 (ins VR128:$src1, FR32:$src2),
363 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
365 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
366 (ins VR128:$src1, FR64:$src2),
367 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
371 let canFoldAsLoad = 1, isReMaterializable = 1 in {
372 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
373 let AddedComplexity = 20 in
374 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
377 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
378 "movss\t{$src, $dst|$dst, $src}",
379 [(store FR32:$src, addr:$dst)]>, XS, VEX;
380 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
381 "movsd\t{$src, $dst|$dst, $src}",
382 [(store FR64:$src, addr:$dst)]>, XD, VEX;
385 let Constraints = "$src1 = $dst" in {
386 def MOVSSrr : sse12_move_rr<FR32, v4f32,
387 "movss\t{$src2, $dst|$dst, $src2}">, XS;
388 def MOVSDrr : sse12_move_rr<FR64, v2f64,
389 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
391 // For the disassembler
392 let isCodeGenOnly = 1 in {
393 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
394 (ins VR128:$src1, FR32:$src2),
395 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
396 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
397 (ins VR128:$src1, FR64:$src2),
398 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
402 let canFoldAsLoad = 1, isReMaterializable = 1 in {
403 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
405 let AddedComplexity = 20 in
406 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
409 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
410 "movss\t{$src, $dst|$dst, $src}",
411 [(store FR32:$src, addr:$dst)]>;
412 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
413 "movsd\t{$src, $dst|$dst, $src}",
414 [(store FR64:$src, addr:$dst)]>;
417 let Predicates = [HasSSE1] in {
418 let AddedComplexity = 15 in {
419 // Extract the low 32-bit value from one vector and insert it into another.
420 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
421 (MOVSSrr (v4f32 VR128:$src1),
422 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
423 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
424 (MOVSSrr (v4i32 VR128:$src1),
425 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
427 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
428 // MOVSS to the lower bits.
429 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
430 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
431 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
432 (MOVSSrr (v4f32 (V_SET0PS)),
433 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
434 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
435 (MOVSSrr (v4i32 (V_SET0PI)),
436 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
439 let AddedComplexity = 20 in {
440 // MOVSSrm zeros the high parts of the register; represent this
441 // with SUBREG_TO_REG.
442 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
443 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
444 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
445 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
446 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
447 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
450 // Extract and store.
451 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
454 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
456 // Shuffle with MOVSS
457 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
458 (MOVSSrr VR128:$src1, FR32:$src2)>;
459 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
460 (MOVSSrr (v4i32 VR128:$src1),
461 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
462 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
463 (MOVSSrr (v4f32 VR128:$src1),
464 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
467 let Predicates = [HasSSE2] in {
468 let AddedComplexity = 15 in {
469 // Extract the low 64-bit value from one vector and insert it into another.
470 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
471 (MOVSDrr (v2f64 VR128:$src1),
472 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
473 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
474 (MOVSDrr (v2i64 VR128:$src1),
475 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
477 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
478 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
479 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
480 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
481 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
483 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
484 // MOVSD to the lower bits.
485 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
486 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
489 let AddedComplexity = 20 in {
490 // MOVSDrm zeros the high parts of the register; represent this
491 // with SUBREG_TO_REG.
492 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
493 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
495 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
496 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
497 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
498 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
499 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
500 def : Pat<(v2f64 (X86vzload addr:$src)),
501 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
504 // Extract and store.
505 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
508 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
510 // Shuffle with MOVSD
511 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
512 (MOVSDrr VR128:$src1, FR64:$src2)>;
513 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
514 (MOVSDrr (v2i64 VR128:$src1),
515 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
516 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
517 (MOVSDrr (v2f64 VR128:$src1),
518 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
519 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
520 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
521 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
522 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
524 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
525 // is during lowering, where it's not possible to recognize the fold cause
526 // it has two uses through a bitcast. One use disappears at isel time and the
527 // fold opportunity reappears.
528 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
529 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
530 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
531 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
534 let Predicates = [HasAVX] in {
535 let AddedComplexity = 15 in {
536 // Extract the low 32-bit value from one vector and insert it into another.
537 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
538 (VMOVSSrr (v4f32 VR128:$src1),
539 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
540 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
541 (VMOVSSrr (v4i32 VR128:$src1),
542 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
544 // Extract the low 64-bit value from one vector and insert it into another.
545 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
546 (VMOVSDrr (v2f64 VR128:$src1),
547 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
548 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
549 (VMOVSDrr (v2i64 VR128:$src1),
550 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
552 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
553 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
554 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
555 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
556 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
558 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
559 // MOVS{S,D} to the lower bits.
560 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
561 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
562 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
563 (VMOVSSrr (v4f32 (AVX_SET0PS)),
564 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (AVX_SET0PI)),
567 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
568 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
569 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
572 let AddedComplexity = 20 in {
573 // MOVSSrm zeros the high parts of the register; represent this
574 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
575 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
576 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
577 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
578 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
579 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
582 // MOVSDrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
585 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
586 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
588 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
589 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
590 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
591 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
592 def : Pat<(v2f64 (X86vzload addr:$src)),
593 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
595 // Represent the same patterns above but in the form they appear for
597 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
598 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
599 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
600 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
601 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
602 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
605 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
606 (SUBREG_TO_REG (i32 0),
607 (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
609 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
610 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
611 (SUBREG_TO_REG (i64 0),
612 (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
615 // Extract and store.
616 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
619 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
620 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
623 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
625 // Shuffle with VMOVSS
626 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
627 (VMOVSSrr VR128:$src1, FR32:$src2)>;
628 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
629 (VMOVSSrr (v4i32 VR128:$src1),
630 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
631 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
632 (VMOVSSrr (v4f32 VR128:$src1),
633 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
635 // Shuffle with VMOVSD
636 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
637 (VMOVSDrr VR128:$src1, FR64:$src2)>;
638 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
639 (VMOVSDrr (v2i64 VR128:$src1),
640 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
641 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
642 (VMOVSDrr (v2f64 VR128:$src1),
643 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
644 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
647 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
648 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
651 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
652 // is during lowering, where it's not possible to recognize the fold cause
653 // it has two uses through a bitcast. One use disappears at isel time and the
654 // fold opportunity reappears.
655 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
656 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
658 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
659 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
663 //===----------------------------------------------------------------------===//
664 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
665 //===----------------------------------------------------------------------===//
667 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
668 X86MemOperand x86memop, PatFrag ld_frag,
669 string asm, Domain d,
670 bit IsReMaterializable = 1> {
671 let neverHasSideEffects = 1 in
672 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
673 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
674 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
675 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
676 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
677 [(set RC:$dst, (ld_frag addr:$src))], d>;
680 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
681 "movaps", SSEPackedSingle>, TB, VEX;
682 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
683 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
684 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
685 "movups", SSEPackedSingle>, TB, VEX;
686 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
687 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
689 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
690 "movaps", SSEPackedSingle>, TB, VEX;
691 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
692 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
693 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
694 "movups", SSEPackedSingle>, TB, VEX;
695 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
696 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
697 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
698 "movaps", SSEPackedSingle>, TB;
699 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
700 "movapd", SSEPackedDouble>, TB, OpSize;
701 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
702 "movups", SSEPackedSingle>, TB;
703 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
704 "movupd", SSEPackedDouble, 0>, TB, OpSize;
706 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
707 "movaps\t{$src, $dst|$dst, $src}",
708 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
709 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movapd\t{$src, $dst|$dst, $src}",
711 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
712 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
713 "movups\t{$src, $dst|$dst, $src}",
714 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
715 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
716 "movupd\t{$src, $dst|$dst, $src}",
717 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
718 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
719 "movaps\t{$src, $dst|$dst, $src}",
720 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
721 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
722 "movapd\t{$src, $dst|$dst, $src}",
723 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
724 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
725 "movups\t{$src, $dst|$dst, $src}",
726 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
727 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
728 "movupd\t{$src, $dst|$dst, $src}",
729 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
732 let isCodeGenOnly = 1 in {
733 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
735 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
736 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
738 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
739 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
741 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
742 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
744 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
745 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
747 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
748 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
750 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
751 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
753 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
754 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
756 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
759 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
760 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
761 (VMOVUPSYmr addr:$dst, VR256:$src)>;
763 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
764 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
765 (VMOVUPDYmr addr:$dst, VR256:$src)>;
767 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
768 "movaps\t{$src, $dst|$dst, $src}",
769 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
770 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
771 "movapd\t{$src, $dst|$dst, $src}",
772 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
773 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
774 "movups\t{$src, $dst|$dst, $src}",
775 [(store (v4f32 VR128:$src), addr:$dst)]>;
776 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
777 "movupd\t{$src, $dst|$dst, $src}",
778 [(store (v2f64 VR128:$src), addr:$dst)]>;
781 let isCodeGenOnly = 1 in {
782 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
783 "movaps\t{$src, $dst|$dst, $src}", []>;
784 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
785 "movapd\t{$src, $dst|$dst, $src}", []>;
786 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
787 "movups\t{$src, $dst|$dst, $src}", []>;
788 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
789 "movupd\t{$src, $dst|$dst, $src}", []>;
792 let Predicates = [HasAVX] in {
793 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
794 (VMOVUPSmr addr:$dst, VR128:$src)>;
795 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
796 (VMOVUPDmr addr:$dst, VR128:$src)>;
799 let Predicates = [HasSSE1] in
800 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
801 (MOVUPSmr addr:$dst, VR128:$src)>;
802 let Predicates = [HasSSE2] in
803 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
804 (MOVUPDmr addr:$dst, VR128:$src)>;
806 // Use movaps / movups for SSE integer load / store (one byte shorter).
807 // The instructions selected below are then converted to MOVDQA/MOVDQU
808 // during the SSE domain pass.
809 let Predicates = [HasSSE1] in {
810 def : Pat<(alignedloadv4i32 addr:$src),
811 (MOVAPSrm addr:$src)>;
812 def : Pat<(loadv4i32 addr:$src),
813 (MOVUPSrm addr:$src)>;
814 def : Pat<(alignedloadv2i64 addr:$src),
815 (MOVAPSrm addr:$src)>;
816 def : Pat<(loadv2i64 addr:$src),
817 (MOVUPSrm addr:$src)>;
819 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
820 (MOVAPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
822 (MOVAPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
824 (MOVAPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
826 (MOVAPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
828 (MOVUPSmr addr:$dst, VR128:$src)>;
829 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
830 (MOVUPSmr addr:$dst, VR128:$src)>;
831 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
832 (MOVUPSmr addr:$dst, VR128:$src)>;
833 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
834 (MOVUPSmr addr:$dst, VR128:$src)>;
837 // Use vmovaps/vmovups for AVX integer load/store.
838 let Predicates = [HasAVX] in {
839 // 128-bit load/store
840 def : Pat<(alignedloadv4i32 addr:$src),
841 (VMOVAPSrm addr:$src)>;
842 def : Pat<(loadv4i32 addr:$src),
843 (VMOVUPSrm addr:$src)>;
844 def : Pat<(alignedloadv2i64 addr:$src),
845 (VMOVAPSrm addr:$src)>;
846 def : Pat<(loadv2i64 addr:$src),
847 (VMOVUPSrm addr:$src)>;
849 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
850 (VMOVAPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
852 (VMOVAPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
854 (VMOVAPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
856 (VMOVAPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
860 (VMOVUPSmr addr:$dst, VR128:$src)>;
861 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
862 (VMOVUPSmr addr:$dst, VR128:$src)>;
863 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
864 (VMOVUPSmr addr:$dst, VR128:$src)>;
866 // 256-bit load/store
867 def : Pat<(alignedloadv4i64 addr:$src),
868 (VMOVAPSYrm addr:$src)>;
869 def : Pat<(loadv4i64 addr:$src),
870 (VMOVUPSYrm addr:$src)>;
871 def : Pat<(alignedloadv8i32 addr:$src),
872 (VMOVAPSYrm addr:$src)>;
873 def : Pat<(loadv8i32 addr:$src),
874 (VMOVUPSYrm addr:$src)>;
875 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
876 (VMOVAPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
878 (VMOVAPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
880 (VMOVAPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
882 (VMOVAPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
884 (VMOVUPSYmr addr:$dst, VR256:$src)>;
885 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
886 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
888 (VMOVUPSYmr addr:$dst, VR256:$src)>;
889 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
890 (VMOVUPSYmr addr:$dst, VR256:$src)>;
893 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
894 // bits are disregarded. FIXME: Set encoding to pseudo!
895 let neverHasSideEffects = 1 in {
896 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
897 "movaps\t{$src, $dst|$dst, $src}", []>;
898 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
899 "movapd\t{$src, $dst|$dst, $src}", []>;
900 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
901 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
902 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
903 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
906 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
907 // bits are disregarded. FIXME: Set encoding to pseudo!
908 let canFoldAsLoad = 1, isReMaterializable = 1 in {
909 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
910 "movaps\t{$src, $dst|$dst, $src}",
911 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
912 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
913 "movapd\t{$src, $dst|$dst, $src}",
914 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
915 let isCodeGenOnly = 1 in {
916 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
917 "movaps\t{$src, $dst|$dst, $src}",
918 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
919 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
920 "movapd\t{$src, $dst|$dst, $src}",
921 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
925 //===----------------------------------------------------------------------===//
926 // SSE 1 & 2 - Move Low packed FP Instructions
927 //===----------------------------------------------------------------------===//
929 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
930 PatFrag mov_frag, string base_opc,
932 def PSrm : PI<opc, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
934 !strconcat(base_opc, "s", asm_opr),
937 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
938 SSEPackedSingle>, TB;
940 def PDrm : PI<opc, MRMSrcMem,
941 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
942 !strconcat(base_opc, "d", asm_opr),
943 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
944 (scalar_to_vector (loadf64 addr:$src2)))))],
945 SSEPackedDouble>, TB, OpSize;
948 let AddedComplexity = 20 in {
949 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
950 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
952 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
953 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
954 "\t{$src2, $dst|$dst, $src2}">;
957 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
958 "movlps\t{$src, $dst|$dst, $src}",
959 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
960 (iPTR 0))), addr:$dst)]>, VEX;
961 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
962 "movlpd\t{$src, $dst|$dst, $src}",
963 [(store (f64 (vector_extract (v2f64 VR128:$src),
964 (iPTR 0))), addr:$dst)]>, VEX;
965 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
966 "movlps\t{$src, $dst|$dst, $src}",
967 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
968 (iPTR 0))), addr:$dst)]>;
969 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
970 "movlpd\t{$src, $dst|$dst, $src}",
971 [(store (f64 (vector_extract (v2f64 VR128:$src),
972 (iPTR 0))), addr:$dst)]>;
974 let Predicates = [HasAVX] in {
975 let AddedComplexity = 20 in {
976 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
977 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
978 (VMOVLPSrm VR128:$src1, addr:$src2)>;
979 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
980 (VMOVLPSrm VR128:$src1, addr:$src2)>;
981 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
982 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
983 (VMOVLPDrm VR128:$src1, addr:$src2)>;
984 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPDrm VR128:$src1, addr:$src2)>;
988 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
989 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
990 (VMOVLPSmr addr:$src1, VR128:$src2)>;
991 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
992 VR128:$src2)), addr:$src1),
993 (VMOVLPSmr addr:$src1, VR128:$src2)>;
995 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
996 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
997 (VMOVLPDmr addr:$src1, VR128:$src2)>;
998 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
999 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1001 // Shuffle with VMOVLPS
1002 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1003 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1004 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1005 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1006 def : Pat<(X86Movlps VR128:$src1,
1007 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1008 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1010 // Shuffle with VMOVLPD
1011 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1012 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1013 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1014 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1015 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1016 (scalar_to_vector (loadf64 addr:$src2)))),
1017 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1020 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1022 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1023 def : Pat<(store (v4i32 (X86Movlps
1024 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1025 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1026 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1028 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1029 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1031 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1034 let Predicates = [HasSSE1] in {
1035 let AddedComplexity = 20 in {
1036 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1037 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1038 (MOVLPSrm VR128:$src1, addr:$src2)>;
1039 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1040 (MOVLPSrm VR128:$src1, addr:$src2)>;
1043 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1044 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1045 (MOVLPSmr addr:$src1, VR128:$src2)>;
1046 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1047 VR128:$src2)), addr:$src1),
1048 (MOVLPSmr addr:$src1, VR128:$src2)>;
1050 // Shuffle with MOVLPS
1051 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1052 (MOVLPSrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1054 (MOVLPSrm VR128:$src1, addr:$src2)>;
1055 def : Pat<(X86Movlps VR128:$src1,
1056 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1057 (MOVLPSrm VR128:$src1, addr:$src2)>;
1060 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1062 (MOVLPSmr addr:$src1, VR128:$src2)>;
1063 def : Pat<(store (v4i32 (X86Movlps
1064 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1066 (MOVLPSmr addr:$src1, VR128:$src2)>;
1069 let Predicates = [HasSSE2] in {
1070 let AddedComplexity = 20 in {
1071 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1072 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1073 (MOVLPDrm VR128:$src1, addr:$src2)>;
1074 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1075 (MOVLPDrm VR128:$src1, addr:$src2)>;
1078 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1079 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1080 (MOVLPDmr addr:$src1, VR128:$src2)>;
1081 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1082 (MOVLPDmr addr:$src1, VR128:$src2)>;
1084 // Shuffle with MOVLPD
1085 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1086 (MOVLPDrm VR128:$src1, addr:$src2)>;
1087 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1088 (MOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1090 (scalar_to_vector (loadf64 addr:$src2)))),
1091 (MOVLPDrm VR128:$src1, addr:$src2)>;
1094 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1096 (MOVLPDmr addr:$src1, VR128:$src2)>;
1097 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1099 (MOVLPDmr addr:$src1, VR128:$src2)>;
1102 //===----------------------------------------------------------------------===//
1103 // SSE 1 & 2 - Move Hi packed FP Instructions
1104 //===----------------------------------------------------------------------===//
1106 let AddedComplexity = 20 in {
1107 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1108 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1110 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1111 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1112 "\t{$src2, $dst|$dst, $src2}">;
1115 // v2f64 extract element 1 is always custom lowered to unpack high to low
1116 // and extract element 0 so the non-store version isn't too horrible.
1117 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1118 "movhps\t{$src, $dst|$dst, $src}",
1119 [(store (f64 (vector_extract
1120 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1121 (undef)), (iPTR 0))), addr:$dst)]>,
1123 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movhpd\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract
1126 (v2f64 (unpckh VR128:$src, (undef))),
1127 (iPTR 0))), addr:$dst)]>,
1129 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1130 "movhps\t{$src, $dst|$dst, $src}",
1131 [(store (f64 (vector_extract
1132 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1133 (undef)), (iPTR 0))), addr:$dst)]>;
1134 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movhpd\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract
1137 (v2f64 (unpckh VR128:$src, (undef))),
1138 (iPTR 0))), addr:$dst)]>;
1140 let Predicates = [HasAVX] in {
1142 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1143 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1144 def : Pat<(X86Movlhps VR128:$src1,
1145 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1146 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1147 def : Pat<(X86Movlhps VR128:$src1,
1148 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1149 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1151 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1152 // is during lowering, where it's not possible to recognize the load fold cause
1153 // it has two uses through a bitcast. One use disappears at isel time and the
1154 // fold opportunity reappears.
1155 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1156 (scalar_to_vector (loadf64 addr:$src2)))),
1157 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1159 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1160 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1161 (scalar_to_vector (loadf64 addr:$src2)))),
1162 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1165 def : Pat<(store (f64 (vector_extract
1166 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1167 (VMOVHPSmr addr:$dst, VR128:$src)>;
1168 def : Pat<(store (f64 (vector_extract
1169 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1170 (VMOVHPDmr addr:$dst, VR128:$src)>;
1173 let Predicates = [HasSSE1] in {
1175 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1176 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1177 def : Pat<(X86Movlhps VR128:$src1,
1178 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1179 (MOVHPSrm VR128:$src1, addr:$src2)>;
1180 def : Pat<(X86Movlhps VR128:$src1,
1181 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1182 (MOVHPSrm VR128:$src1, addr:$src2)>;
1185 def : Pat<(store (f64 (vector_extract
1186 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1187 (MOVHPSmr addr:$dst, VR128:$src)>;
1190 let Predicates = [HasSSE2] in {
1191 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1192 // is during lowering, where it's not possible to recognize the load fold cause
1193 // it has two uses through a bitcast. One use disappears at isel time and the
1194 // fold opportunity reappears.
1195 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1196 (scalar_to_vector (loadf64 addr:$src2)))),
1197 (MOVHPDrm VR128:$src1, addr:$src2)>;
1199 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1200 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1201 (scalar_to_vector (loadf64 addr:$src2)))),
1202 (MOVHPDrm VR128:$src1, addr:$src2)>;
1205 def : Pat<(store (f64 (vector_extract
1206 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1207 (MOVHPDmr addr:$dst, VR128:$src)>;
1210 //===----------------------------------------------------------------------===//
1211 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1212 //===----------------------------------------------------------------------===//
1214 let AddedComplexity = 20 in {
1215 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1216 (ins VR128:$src1, VR128:$src2),
1217 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1219 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1221 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1222 (ins VR128:$src1, VR128:$src2),
1223 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1225 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1228 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1229 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1230 (ins VR128:$src1, VR128:$src2),
1231 "movlhps\t{$src2, $dst|$dst, $src2}",
1233 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1234 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1235 (ins VR128:$src1, VR128:$src2),
1236 "movhlps\t{$src2, $dst|$dst, $src2}",
1238 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1241 let Predicates = [HasAVX] in {
1243 let AddedComplexity = 20 in {
1244 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1245 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1246 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1247 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1249 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1250 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1251 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1253 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1254 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1255 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1256 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1257 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1258 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1261 let AddedComplexity = 20 in {
1262 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1263 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1264 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1266 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1267 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1268 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1269 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1270 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1273 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1274 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1275 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1276 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1279 let Predicates = [HasSSE1] in {
1281 let AddedComplexity = 20 in {
1282 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1283 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1284 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1285 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1287 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1288 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1289 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1291 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1292 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1293 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1294 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1295 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1296 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1299 let AddedComplexity = 20 in {
1300 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1301 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1302 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1304 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1305 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1306 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1307 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1308 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1311 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1312 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1313 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1314 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1317 //===----------------------------------------------------------------------===//
1318 // SSE 1 & 2 - Conversion Instructions
1319 //===----------------------------------------------------------------------===//
1321 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1322 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1324 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1325 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1326 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1327 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1330 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1331 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1332 string asm, Domain d> {
1333 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1334 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1335 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1336 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1339 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1340 X86MemOperand x86memop, string asm> {
1341 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1342 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1343 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1344 (ins DstRC:$src1, x86memop:$src),
1345 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1348 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1349 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
1350 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1351 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1353 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1354 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1355 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1356 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1359 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1360 // register, but the same isn't true when only using memory operands,
1361 // provide other assembly "l" and "q" forms to address this explicitly
1362 // where appropriate to do so.
1363 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1365 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1367 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1369 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1371 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1374 let Predicates = [HasAVX] in {
1375 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1376 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1377 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1378 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1379 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1380 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1381 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1382 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1384 def : Pat<(f32 (sint_to_fp GR32:$src)),
1385 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1386 def : Pat<(f32 (sint_to_fp GR64:$src)),
1387 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1388 def : Pat<(f64 (sint_to_fp GR32:$src)),
1389 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1390 def : Pat<(f64 (sint_to_fp GR64:$src)),
1391 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1394 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1395 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1396 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1397 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1398 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1399 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1400 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1401 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1402 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1403 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1404 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1405 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1406 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1407 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1408 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1409 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1411 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1412 // and/or XMM operand(s).
1414 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1415 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1417 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1418 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1419 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1420 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1421 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1422 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1425 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1426 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1427 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1428 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1430 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1431 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1432 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1433 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1434 (ins DstRC:$src1, x86memop:$src2),
1436 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1437 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1438 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1441 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1442 f128mem, load, "cvtsd2si">, XD, VEX;
1443 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1444 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1447 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1448 // Get rid of this hack or rename the intrinsics, there are several
1449 // intructions that only match with the intrinsic form, why create duplicates
1450 // to let them be recognized by the assembler?
1451 let Pattern = []<dag> in {
1452 defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load,
1453 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1454 defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load,
1455 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1457 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1458 f128mem, load, "cvtsd2si{l}">, XD;
1459 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1460 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1463 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1464 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1465 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1466 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1468 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1469 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1470 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1471 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1474 let Constraints = "$src1 = $dst" in {
1475 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1476 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1478 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1479 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1480 "cvtsi2ss{q}">, XS, REX_W;
1481 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1482 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1484 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1485 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1486 "cvtsi2sd">, XD, REX_W;
1491 // Aliases for intrinsics
1492 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1493 f32mem, load, "cvttss2si">, XS, VEX;
1494 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1495 int_x86_sse_cvttss2si64, f32mem, load,
1496 "cvttss2si">, XS, VEX, VEX_W;
1497 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1498 f128mem, load, "cvttsd2si">, XD, VEX;
1499 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1500 int_x86_sse2_cvttsd2si64, f128mem, load,
1501 "cvttsd2si">, XD, VEX, VEX_W;
1502 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1503 f32mem, load, "cvttss2si">, XS;
1504 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1505 int_x86_sse_cvttss2si64, f32mem, load,
1506 "cvttss2si{q}">, XS, REX_W;
1507 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1508 f128mem, load, "cvttsd2si">, XD;
1509 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1510 int_x86_sse2_cvttsd2si64, f128mem, load,
1511 "cvttsd2si{q}">, XD, REX_W;
1513 let Pattern = []<dag> in {
1514 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1515 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1516 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1517 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1519 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1520 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1521 SSEPackedSingle>, TB, VEX;
1522 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1523 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1524 SSEPackedSingle>, TB, VEX;
1527 let Pattern = []<dag> in {
1528 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1529 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1530 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1531 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1532 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1533 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1534 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1537 let Predicates = [HasSSE1] in {
1538 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1539 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1540 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1541 (CVTSS2SIrm addr:$src)>;
1542 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1543 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1544 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1545 (CVTSS2SI64rm addr:$src)>;
1548 let Predicates = [HasAVX] in {
1549 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1550 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1551 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1552 (VCVTSS2SIrm addr:$src)>;
1553 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1554 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1555 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1556 (VCVTSS2SI64rm addr:$src)>;
1561 // Convert scalar double to scalar single
1562 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1563 (ins FR64:$src1, FR64:$src2),
1564 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1566 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1567 (ins FR64:$src1, f64mem:$src2),
1568 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1569 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1571 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1574 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1575 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1576 [(set FR32:$dst, (fround FR64:$src))]>;
1577 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1578 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1579 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1580 Requires<[HasSSE2, OptForSize]>;
1582 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1583 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1585 let Constraints = "$src1 = $dst" in
1586 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1587 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1589 // Convert scalar single to scalar double
1590 // SSE2 instructions with XS prefix
1591 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1592 (ins FR32:$src1, FR32:$src2),
1593 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1594 []>, XS, Requires<[HasAVX]>, VEX_4V;
1595 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1596 (ins FR32:$src1, f32mem:$src2),
1597 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1598 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1600 let Predicates = [HasAVX] in {
1601 def : Pat<(f64 (fextend FR32:$src)),
1602 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1603 def : Pat<(fextend (loadf32 addr:$src)),
1604 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1605 def : Pat<(extloadf32 addr:$src),
1606 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1609 def : Pat<(extloadf32 addr:$src),
1610 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1611 Requires<[HasAVX, OptForSpeed]>;
1613 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1614 "cvtss2sd\t{$src, $dst|$dst, $src}",
1615 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1616 Requires<[HasSSE2]>;
1617 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1618 "cvtss2sd\t{$src, $dst|$dst, $src}",
1619 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1620 Requires<[HasSSE2, OptForSize]>;
1622 // extload f32 -> f64. This matches load+fextend because we have a hack in
1623 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1625 // Since these loads aren't folded into the fextend, we have to match it
1627 def : Pat<(fextend (loadf32 addr:$src)),
1628 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1629 def : Pat<(extloadf32 addr:$src),
1630 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1632 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1633 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1634 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1635 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1636 VR128:$src2))]>, XS, VEX_4V,
1638 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1639 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1640 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1641 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1642 (load addr:$src2)))]>, XS, VEX_4V,
1644 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1645 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1646 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1647 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1648 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1649 VR128:$src2))]>, XS,
1650 Requires<[HasSSE2]>;
1651 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1652 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1653 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1654 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1655 (load addr:$src2)))]>, XS,
1656 Requires<[HasSSE2]>;
1659 // Convert doubleword to packed single/double fp
1660 // SSE2 instructions without OpSize prefix
1661 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1662 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1663 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1664 TB, VEX, Requires<[HasAVX]>;
1665 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1666 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1667 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1668 (bitconvert (memopv2i64 addr:$src))))]>,
1669 TB, VEX, Requires<[HasAVX]>;
1670 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1671 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1673 TB, Requires<[HasSSE2]>;
1674 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1675 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1677 (bitconvert (memopv2i64 addr:$src))))]>,
1678 TB, Requires<[HasSSE2]>;
1680 // FIXME: why the non-intrinsic version is described as SSE3?
1681 // SSE2 instructions with XS prefix
1682 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1683 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1685 XS, VEX, Requires<[HasAVX]>;
1686 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1687 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1688 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1689 (bitconvert (memopv2i64 addr:$src))))]>,
1690 XS, VEX, Requires<[HasAVX]>;
1691 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1692 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1694 XS, Requires<[HasSSE2]>;
1695 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1696 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1698 (bitconvert (memopv2i64 addr:$src))))]>,
1699 XS, Requires<[HasSSE2]>;
1702 // Convert packed single/double fp to doubleword
1703 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1705 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1706 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1707 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1708 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1709 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1710 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1711 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1712 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1713 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1714 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1716 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1717 "cvtps2dq\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1720 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1722 "cvtps2dq\t{$src, $dst|$dst, $src}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1724 (memop addr:$src)))]>, VEX;
1725 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1726 "cvtps2dq\t{$src, $dst|$dst, $src}",
1727 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1728 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1729 "cvtps2dq\t{$src, $dst|$dst, $src}",
1730 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1731 (memop addr:$src)))]>;
1733 // SSE2 packed instructions with XD prefix
1734 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1737 XD, VEX, Requires<[HasAVX]>;
1738 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1739 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1740 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1741 (memop addr:$src)))]>,
1742 XD, VEX, Requires<[HasAVX]>;
1743 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1744 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1745 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1746 XD, Requires<[HasSSE2]>;
1747 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1748 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1750 (memop addr:$src)))]>,
1751 XD, Requires<[HasSSE2]>;
1754 // Convert with truncation packed single/double fp to doubleword
1755 // SSE2 packed instructions with XS prefix
1756 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1758 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1759 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1760 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1761 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1762 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1763 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1764 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1765 "cvttps2dq\t{$src, $dst|$dst, $src}",
1767 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1768 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1769 "cvttps2dq\t{$src, $dst|$dst, $src}",
1771 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1773 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1774 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1776 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1777 XS, VEX, Requires<[HasAVX]>;
1778 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1781 (memop addr:$src)))]>,
1782 XS, VEX, Requires<[HasAVX]>;
1784 let Predicates = [HasSSE2] in {
1785 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1786 (Int_CVTDQ2PSrr VR128:$src)>;
1787 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1788 (CVTTPS2DQrr VR128:$src)>;
1791 let Predicates = [HasAVX] in {
1792 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1793 (Int_VCVTDQ2PSrr VR128:$src)>;
1794 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1795 (VCVTTPS2DQrr VR128:$src)>;
1796 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1797 (VCVTDQ2PSYrr VR256:$src)>;
1798 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1799 (VCVTTPS2DQYrr VR256:$src)>;
1802 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1804 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1805 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1807 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1809 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1810 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1811 (memop addr:$src)))]>, VEX;
1812 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1813 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1815 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1816 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1817 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1818 (memop addr:$src)))]>;
1820 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1821 // register, but the same isn't true when using memory operands instead.
1822 // Provide other assembly rr and rm forms to address this explicitly.
1823 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1825 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1826 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1829 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1831 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1832 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1835 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1836 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1837 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1838 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1840 // Convert packed single to packed double
1841 let Predicates = [HasAVX] in {
1842 // SSE2 instructions without OpSize prefix
1843 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1844 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1845 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1846 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1847 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1848 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1849 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1850 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1852 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1853 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1854 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1855 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1857 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1858 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1860 TB, VEX, Requires<[HasAVX]>;
1861 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1862 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1863 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1864 (load addr:$src)))]>,
1865 TB, VEX, Requires<[HasAVX]>;
1866 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1867 "cvtps2pd\t{$src, $dst|$dst, $src}",
1868 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1869 TB, Requires<[HasSSE2]>;
1870 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1871 "cvtps2pd\t{$src, $dst|$dst, $src}",
1872 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1873 (load addr:$src)))]>,
1874 TB, Requires<[HasSSE2]>;
1876 // Convert packed double to packed single
1877 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1878 // register, but the same isn't true when using memory operands instead.
1879 // Provide other assembly rr and rm forms to address this explicitly.
1880 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1881 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1882 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1883 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1886 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1887 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1888 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1889 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1892 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1893 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1894 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1895 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1896 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1897 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1898 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1899 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1902 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1903 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1904 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1905 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1907 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1908 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1909 (memop addr:$src)))]>;
1910 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1913 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1914 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1915 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1916 (memop addr:$src)))]>;
1918 // AVX 256-bit register conversion intrinsics
1919 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1920 // whenever possible to avoid declaring two versions of each one.
1921 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1922 (VCVTDQ2PSYrr VR256:$src)>;
1923 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1924 (VCVTDQ2PSYrm addr:$src)>;
1926 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1927 (VCVTPD2PSYrr VR256:$src)>;
1928 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1929 (VCVTPD2PSYrm addr:$src)>;
1931 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1932 (VCVTPS2DQYrr VR256:$src)>;
1933 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1934 (VCVTPS2DQYrm addr:$src)>;
1936 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1937 (VCVTPS2PDYrr VR128:$src)>;
1938 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1939 (VCVTPS2PDYrm addr:$src)>;
1941 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1942 (VCVTTPD2DQYrr VR256:$src)>;
1943 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1944 (VCVTTPD2DQYrm addr:$src)>;
1946 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1947 (VCVTTPS2DQYrr VR256:$src)>;
1948 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1949 (VCVTTPS2DQYrm addr:$src)>;
1951 // Match fround and fextend for 128/256-bit conversions
1952 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1953 (VCVTPD2PSYrr VR256:$src)>;
1954 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1955 (VCVTPD2PSYrm addr:$src)>;
1957 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1958 (VCVTPS2PDYrr VR128:$src)>;
1959 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1960 (VCVTPS2PDYrm addr:$src)>;
1962 //===----------------------------------------------------------------------===//
1963 // SSE 1 & 2 - Compare Instructions
1964 //===----------------------------------------------------------------------===//
1966 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1967 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1968 string asm, string asm_alt> {
1969 let isAsmParserOnly = 1 in {
1970 def rr : SIi8<0xC2, MRMSrcReg,
1971 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1974 def rm : SIi8<0xC2, MRMSrcMem,
1975 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1979 // Accept explicit immediate argument form instead of comparison code.
1980 def rr_alt : SIi8<0xC2, MRMSrcReg,
1981 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1984 def rm_alt : SIi8<0xC2, MRMSrcMem,
1985 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1989 let neverHasSideEffects = 1 in {
1990 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1991 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1992 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1994 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1995 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1996 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
2000 let Constraints = "$src1 = $dst" in {
2001 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
2002 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
2003 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2004 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2,
2006 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
2007 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
2008 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2009 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1),
2010 (loadf32 addr:$src2), imm:$cc))]>, XS;
2011 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
2012 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
2013 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2014 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2,
2016 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
2017 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
2018 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2019 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2),
2022 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2023 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
2024 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
2025 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
2026 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
2027 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
2028 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
2029 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
2030 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
2031 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
2032 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
2033 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
2034 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
2037 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2038 Intrinsic Int, string asm> {
2039 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2040 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2041 [(set VR128:$dst, (Int VR128:$src1,
2042 VR128:$src, imm:$cc))]>;
2043 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2044 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2045 [(set VR128:$dst, (Int VR128:$src1,
2046 (load addr:$src), imm:$cc))]>;
2049 // Aliases to match intrinsics which expect XMM operand(s).
2050 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2051 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2053 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2054 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2056 let Constraints = "$src1 = $dst" in {
2057 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2058 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2059 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2060 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2064 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2065 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2066 ValueType vt, X86MemOperand x86memop,
2067 PatFrag ld_frag, string OpcodeStr, Domain d> {
2068 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2070 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2071 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2072 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2073 [(set EFLAGS, (OpNode (vt RC:$src1),
2074 (ld_frag addr:$src2)))], d>;
2077 let Defs = [EFLAGS] in {
2078 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2079 "ucomiss", SSEPackedSingle>, TB, VEX;
2080 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2081 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2082 let Pattern = []<dag> in {
2083 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2084 "comiss", SSEPackedSingle>, TB, VEX;
2085 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2086 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2089 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2090 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2091 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2092 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2094 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2095 load, "comiss", SSEPackedSingle>, TB, VEX;
2096 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2097 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2098 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2099 "ucomiss", SSEPackedSingle>, TB;
2100 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2101 "ucomisd", SSEPackedDouble>, TB, OpSize;
2103 let Pattern = []<dag> in {
2104 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2105 "comiss", SSEPackedSingle>, TB;
2106 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2107 "comisd", SSEPackedDouble>, TB, OpSize;
2110 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2111 load, "ucomiss", SSEPackedSingle>, TB;
2112 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2113 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2115 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2116 "comiss", SSEPackedSingle>, TB;
2117 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2118 "comisd", SSEPackedDouble>, TB, OpSize;
2119 } // Defs = [EFLAGS]
2121 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2122 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2123 Intrinsic Int, string asm, string asm_alt,
2125 let isAsmParserOnly = 1 in {
2126 def rri : PIi8<0xC2, MRMSrcReg,
2127 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2128 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2129 def rmi : PIi8<0xC2, MRMSrcMem,
2130 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2131 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2134 // Accept explicit immediate argument form instead of comparison code.
2135 def rri_alt : PIi8<0xC2, MRMSrcReg,
2136 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2138 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2139 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2143 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2144 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2145 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2146 SSEPackedSingle>, TB, VEX_4V;
2147 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2148 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2149 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2150 SSEPackedDouble>, TB, OpSize, VEX_4V;
2151 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2152 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2153 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2154 SSEPackedSingle>, TB, VEX_4V;
2155 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2156 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2157 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2158 SSEPackedDouble>, TB, OpSize, VEX_4V;
2159 let Constraints = "$src1 = $dst" in {
2160 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2161 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2162 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2163 SSEPackedSingle>, TB;
2164 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2165 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2166 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2167 SSEPackedDouble>, TB, OpSize;
2170 let Predicates = [HasSSE1] in {
2171 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2172 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2173 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2174 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2177 let Predicates = [HasSSE2] in {
2178 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2179 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2180 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2181 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2184 let Predicates = [HasAVX] in {
2185 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2186 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2187 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2188 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2189 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2190 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2191 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2192 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2194 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2195 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2196 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2197 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2198 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2199 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2200 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2201 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2204 //===----------------------------------------------------------------------===//
2205 // SSE 1 & 2 - Shuffle Instructions
2206 //===----------------------------------------------------------------------===//
2208 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2209 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2210 ValueType vt, string asm, PatFrag mem_frag,
2211 Domain d, bit IsConvertibleToThreeAddress = 0> {
2212 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2213 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2214 [(set RC:$dst, (vt (shufp:$src3
2215 RC:$src1, (mem_frag addr:$src2))))], d>;
2216 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2217 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2218 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2220 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2223 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2224 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2225 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2226 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2227 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2228 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2229 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2230 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2231 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2232 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2233 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2234 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2236 let Constraints = "$src1 = $dst" in {
2237 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2238 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2239 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2241 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2242 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2243 memopv2f64, SSEPackedDouble>, TB, OpSize;
2246 let Predicates = [HasSSE1] in {
2247 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2248 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2249 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2250 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2251 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2252 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2253 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2254 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2255 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2256 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2257 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2258 // fall back to this for SSE1)
2259 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2260 (SHUFPSrri VR128:$src2, VR128:$src1,
2261 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2262 // Special unary SHUFPSrri case.
2263 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2264 (SHUFPSrri VR128:$src1, VR128:$src1,
2265 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2268 let Predicates = [HasSSE2] in {
2269 // Special binary v4i32 shuffle cases with SHUFPS.
2270 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2271 (SHUFPSrri VR128:$src1, VR128:$src2,
2272 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2273 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2274 (bc_v4i32 (memopv2i64 addr:$src2)))),
2275 (SHUFPSrmi VR128:$src1, addr:$src2,
2276 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2277 // Special unary SHUFPDrri cases.
2278 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2279 (SHUFPDrri VR128:$src1, VR128:$src1,
2280 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2281 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2282 (SHUFPDrri VR128:$src1, VR128:$src1,
2283 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2284 // Special binary v2i64 shuffle cases using SHUFPDrri.
2285 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2286 (SHUFPDrri VR128:$src1, VR128:$src2,
2287 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2288 // Generic SHUFPD patterns
2289 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2290 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2291 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2292 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2293 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2294 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2295 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2298 let Predicates = [HasAVX] in {
2299 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2300 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2301 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2302 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2303 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2304 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2305 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2306 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2307 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2308 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2309 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2310 // fall back to this for SSE1)
2311 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2312 (VSHUFPSrri VR128:$src2, VR128:$src1,
2313 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2314 // Special unary SHUFPSrri case.
2315 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2316 (VSHUFPSrri VR128:$src1, VR128:$src1,
2317 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2318 // Special binary v4i32 shuffle cases with SHUFPS.
2319 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2320 (VSHUFPSrri VR128:$src1, VR128:$src2,
2321 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2322 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2323 (bc_v4i32 (memopv2i64 addr:$src2)))),
2324 (VSHUFPSrmi VR128:$src1, addr:$src2,
2325 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2326 // Special unary SHUFPDrri cases.
2327 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2328 (VSHUFPDrri VR128:$src1, VR128:$src1,
2329 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2330 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2331 (VSHUFPDrri VR128:$src1, VR128:$src1,
2332 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2333 // Special binary v2i64 shuffle cases using SHUFPDrri.
2334 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2335 (VSHUFPDrri VR128:$src1, VR128:$src2,
2336 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2338 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2339 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2340 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2341 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2342 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2343 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2344 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2347 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2348 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2349 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2350 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2351 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2353 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2354 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2355 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2356 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2357 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2359 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2360 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2361 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2362 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2363 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2365 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2366 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2367 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2368 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2369 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2372 //===----------------------------------------------------------------------===//
2373 // SSE 1 & 2 - Unpack Instructions
2374 //===----------------------------------------------------------------------===//
2376 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2377 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2378 PatFrag mem_frag, RegisterClass RC,
2379 X86MemOperand x86memop, string asm,
2381 def rr : PI<opc, MRMSrcReg,
2382 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2384 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2385 def rm : PI<opc, MRMSrcMem,
2386 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2388 (vt (OpNode RC:$src1,
2389 (mem_frag addr:$src2))))], d>;
2392 let AddedComplexity = 10 in {
2393 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2394 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2395 SSEPackedSingle>, TB, VEX_4V;
2396 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2397 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2398 SSEPackedDouble>, TB, OpSize, VEX_4V;
2399 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2400 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2401 SSEPackedSingle>, TB, VEX_4V;
2402 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2403 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2404 SSEPackedDouble>, TB, OpSize, VEX_4V;
2406 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2407 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 SSEPackedSingle>, TB, VEX_4V;
2409 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2410 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2411 SSEPackedDouble>, TB, OpSize, VEX_4V;
2412 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2413 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2414 SSEPackedSingle>, TB, VEX_4V;
2415 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2416 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2417 SSEPackedDouble>, TB, OpSize, VEX_4V;
2419 let Constraints = "$src1 = $dst" in {
2420 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2421 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2422 SSEPackedSingle>, TB;
2423 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2424 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2425 SSEPackedDouble>, TB, OpSize;
2426 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2427 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2428 SSEPackedSingle>, TB;
2429 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2430 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2431 SSEPackedDouble>, TB, OpSize;
2432 } // Constraints = "$src1 = $dst"
2433 } // AddedComplexity
2435 let Predicates = [HasSSE1] in {
2436 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2437 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2438 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2439 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2440 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2441 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2442 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2443 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2446 let Predicates = [HasSSE2] in {
2447 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2448 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2449 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2450 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2451 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2452 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2453 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2454 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2456 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2457 // problem is during lowering, where it's not possible to recognize the load
2458 // fold cause it has two uses through a bitcast. One use disappears at isel
2459 // time and the fold opportunity reappears.
2460 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2461 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2463 let AddedComplexity = 10 in
2464 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2465 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2468 let Predicates = [HasAVX] in {
2469 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2470 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2471 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2472 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2473 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2474 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2475 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2476 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2478 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2479 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2480 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2481 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2482 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2483 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2484 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2485 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2486 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2487 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2488 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2489 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2490 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2491 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2492 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2493 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2495 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2496 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2497 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2498 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2499 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2500 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2501 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2502 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2504 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2505 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2506 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2507 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2508 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2509 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2510 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2511 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2512 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2513 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2514 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2515 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2516 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2517 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2518 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2519 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2521 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2522 // problem is during lowering, where it's not possible to recognize the load
2523 // fold cause it has two uses through a bitcast. One use disappears at isel
2524 // time and the fold opportunity reappears.
2525 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2526 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2527 let AddedComplexity = 10 in
2528 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2529 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2532 //===----------------------------------------------------------------------===//
2533 // SSE 1 & 2 - Extract Floating-Point Sign mask
2534 //===----------------------------------------------------------------------===//
2536 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2537 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2539 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2540 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2541 [(set GR32:$dst, (Int RC:$src))], d>;
2542 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2543 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2546 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2547 SSEPackedSingle>, TB;
2548 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2549 SSEPackedDouble>, TB, OpSize;
2551 def : Pat<(i32 (X86fgetsign FR32:$src)),
2552 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2553 sub_ss))>, Requires<[HasSSE1]>;
2554 def : Pat<(i64 (X86fgetsign FR32:$src)),
2555 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2556 sub_ss))>, Requires<[HasSSE1]>;
2557 def : Pat<(i32 (X86fgetsign FR64:$src)),
2558 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2559 sub_sd))>, Requires<[HasSSE2]>;
2560 def : Pat<(i64 (X86fgetsign FR64:$src)),
2561 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2562 sub_sd))>, Requires<[HasSSE2]>;
2564 let Predicates = [HasAVX] in {
2565 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2566 "movmskps", SSEPackedSingle>, TB, VEX;
2567 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2568 "movmskpd", SSEPackedDouble>, TB,
2570 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2571 "movmskps", SSEPackedSingle>, TB, VEX;
2572 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2573 "movmskpd", SSEPackedDouble>, TB,
2576 def : Pat<(i32 (X86fgetsign FR32:$src)),
2577 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2579 def : Pat<(i64 (X86fgetsign FR32:$src)),
2580 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2582 def : Pat<(i32 (X86fgetsign FR64:$src)),
2583 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2585 def : Pat<(i64 (X86fgetsign FR64:$src)),
2586 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2590 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2591 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2592 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2593 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2595 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2596 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2597 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2598 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2602 //===----------------------------------------------------------------------===//
2603 // SSE 1 & 2 - Logical Instructions
2604 //===----------------------------------------------------------------------===//
2606 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2608 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2610 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2611 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2613 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2614 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2616 let Constraints = "$src1 = $dst" in {
2617 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2618 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2620 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2621 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2625 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2626 let mayLoad = 0 in {
2627 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2628 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2629 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2632 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2633 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2635 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2637 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2639 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2640 // are all promoted to v2i64, and the patterns are covered by the int
2641 // version. This is needed in SSE only, because v2i64 isn't supported on
2642 // SSE1, but only on SSE2.
2643 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2644 !strconcat(OpcodeStr, "ps"), f128mem, [],
2645 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2646 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2648 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2649 !strconcat(OpcodeStr, "pd"), f128mem,
2650 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2651 (bc_v2i64 (v2f64 VR128:$src2))))],
2652 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2653 (memopv2i64 addr:$src2)))], 0>,
2655 let Constraints = "$src1 = $dst" in {
2656 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2657 !strconcat(OpcodeStr, "ps"), f128mem,
2658 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2659 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2660 (memopv2i64 addr:$src2)))]>, TB;
2662 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2663 !strconcat(OpcodeStr, "pd"), f128mem,
2664 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2665 (bc_v2i64 (v2f64 VR128:$src2))))],
2666 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2667 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2671 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2673 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2675 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2676 !strconcat(OpcodeStr, "ps"), f256mem,
2677 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2678 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2679 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2681 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2682 !strconcat(OpcodeStr, "pd"), f256mem,
2683 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2684 (bc_v4i64 (v4f64 VR256:$src2))))],
2685 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2686 (memopv4i64 addr:$src2)))], 0>,
2690 // AVX 256-bit packed logical ops forms
2691 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2692 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2693 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2694 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2696 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2697 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2698 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2699 let isCommutable = 0 in
2700 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Arithmetic Instructions
2704 //===----------------------------------------------------------------------===//
2706 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2709 /// In addition, we also have a special variant of the scalar form here to
2710 /// represent the associated intrinsic operation. This form is unlike the
2711 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2712 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2714 /// These three forms can each be reg+reg or reg+mem.
2717 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2719 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2721 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2722 OpNode, FR32, f32mem, Is2Addr>, XS;
2723 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2724 OpNode, FR64, f64mem, Is2Addr>, XD;
2727 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2729 let mayLoad = 0 in {
2730 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2731 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2732 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2733 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2737 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2739 let mayLoad = 0 in {
2740 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2741 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2742 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2743 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2747 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2749 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2750 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2751 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2752 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2755 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2757 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2758 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2759 SSEPackedSingle, Is2Addr>, TB;
2761 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2762 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2763 SSEPackedDouble, Is2Addr>, TB, OpSize;
2766 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2767 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2768 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2769 SSEPackedSingle, 0>, TB;
2771 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2772 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2773 SSEPackedDouble, 0>, TB, OpSize;
2776 // Binary Arithmetic instructions
2777 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2778 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2779 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2780 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2781 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2782 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2783 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2784 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2786 let isCommutable = 0 in {
2787 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2788 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2789 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2790 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2791 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2792 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2793 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2794 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2795 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2796 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2797 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2798 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2799 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2800 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2801 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2802 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2803 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2804 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2805 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2806 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2809 let Constraints = "$src1 = $dst" in {
2810 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2811 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2812 basic_sse12_fp_binop_s_int<0x58, "add">;
2813 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2814 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2815 basic_sse12_fp_binop_s_int<0x59, "mul">;
2817 let isCommutable = 0 in {
2818 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2819 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2820 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2821 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2822 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2823 basic_sse12_fp_binop_s_int<0x5E, "div">;
2824 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2825 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2826 basic_sse12_fp_binop_s_int<0x5F, "max">,
2827 basic_sse12_fp_binop_p_int<0x5F, "max">;
2828 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2829 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2830 basic_sse12_fp_binop_s_int<0x5D, "min">,
2831 basic_sse12_fp_binop_p_int<0x5D, "min">;
2836 /// In addition, we also have a special variant of the scalar form here to
2837 /// represent the associated intrinsic operation. This form is unlike the
2838 /// plain scalar form, in that it takes an entire vector (instead of a
2839 /// scalar) and leaves the top elements undefined.
2841 /// And, we have a special variant form for a full-vector intrinsic form.
2843 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2844 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2845 SDNode OpNode, Intrinsic F32Int> {
2846 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2847 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2848 [(set FR32:$dst, (OpNode FR32:$src))]>;
2849 // For scalar unary operations, fold a load into the operation
2850 // only in OptForSize mode. It eliminates an instruction, but it also
2851 // eliminates a whole-register clobber (the load), so it introduces a
2852 // partial register update condition.
2853 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2854 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2855 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2856 Requires<[HasSSE1, OptForSize]>;
2857 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2858 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2859 [(set VR128:$dst, (F32Int VR128:$src))]>;
2860 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2861 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2862 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2865 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2866 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2867 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2868 !strconcat(OpcodeStr,
2869 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2870 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2871 !strconcat(OpcodeStr,
2872 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2873 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2874 (ins ssmem:$src1, VR128:$src2),
2875 !strconcat(OpcodeStr,
2876 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2879 /// sse1_fp_unop_p - SSE1 unops in packed form.
2880 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2881 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2882 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2883 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2884 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2885 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2886 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2889 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2890 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2891 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2892 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2893 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2894 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2895 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2896 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2899 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2900 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2901 Intrinsic V4F32Int> {
2902 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2903 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2904 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2905 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2906 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2907 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2910 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2911 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2912 Intrinsic V4F32Int> {
2913 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2914 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2915 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2916 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2917 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2918 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2921 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2922 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2923 SDNode OpNode, Intrinsic F64Int> {
2924 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2925 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2926 [(set FR64:$dst, (OpNode FR64:$src))]>;
2927 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2928 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2929 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2930 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2931 Requires<[HasSSE2, OptForSize]>;
2932 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2933 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2934 [(set VR128:$dst, (F64Int VR128:$src))]>;
2935 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2936 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2937 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2940 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2941 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2942 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2943 !strconcat(OpcodeStr,
2944 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2945 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2946 !strconcat(OpcodeStr,
2947 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2948 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2949 (ins VR128:$src1, sdmem:$src2),
2950 !strconcat(OpcodeStr,
2951 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2954 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2955 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2957 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2958 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2959 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2960 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2961 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2962 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2965 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2966 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2967 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2968 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2969 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2970 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2971 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2972 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2975 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2976 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2977 Intrinsic V2F64Int> {
2978 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2979 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2980 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2981 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2982 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2983 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2986 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2987 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2988 Intrinsic V2F64Int> {
2989 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2990 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2991 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2992 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2993 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2994 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2997 let Predicates = [HasAVX] in {
2999 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3000 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
3002 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3003 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3004 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3005 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3006 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3007 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3008 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3009 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3012 // Reciprocal approximations. Note that these typically require refinement
3013 // in order to obtain suitable precision.
3014 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
3015 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3016 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3017 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3018 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3020 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
3021 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3022 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3023 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3024 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3027 def : Pat<(f32 (fsqrt FR32:$src)),
3028 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3029 def : Pat<(f32 (fsqrt (load addr:$src))),
3030 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3031 Requires<[HasAVX, OptForSize]>;
3032 def : Pat<(f64 (fsqrt FR64:$src)),
3033 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3034 def : Pat<(f64 (fsqrt (load addr:$src))),
3035 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3036 Requires<[HasAVX, OptForSize]>;
3038 def : Pat<(f32 (X86frsqrt FR32:$src)),
3039 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3040 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3041 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3042 Requires<[HasAVX, OptForSize]>;
3044 def : Pat<(f32 (X86frcp FR32:$src)),
3045 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3046 def : Pat<(f32 (X86frcp (load addr:$src))),
3047 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3048 Requires<[HasAVX, OptForSize]>;
3050 let Predicates = [HasAVX] in {
3051 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3052 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3053 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3054 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3056 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3057 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3059 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3060 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3061 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3062 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3064 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3065 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3067 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3068 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3069 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3070 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3072 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3073 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3075 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3076 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3077 (VRCPSSr (f32 (IMPLICIT_DEF)),
3078 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3080 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3081 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3085 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3086 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3087 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3088 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3089 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3090 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3092 // Reciprocal approximations. Note that these typically require refinement
3093 // in order to obtain suitable precision.
3094 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3095 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3096 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3097 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3098 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3099 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3101 // There is no f64 version of the reciprocal approximation instructions.
3103 //===----------------------------------------------------------------------===//
3104 // SSE 1 & 2 - Non-temporal stores
3105 //===----------------------------------------------------------------------===//
3107 let AddedComplexity = 400 in { // Prefer non-temporal versions
3108 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3109 (ins f128mem:$dst, VR128:$src),
3110 "movntps\t{$src, $dst|$dst, $src}",
3111 [(alignednontemporalstore (v4f32 VR128:$src),
3113 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3114 (ins f128mem:$dst, VR128:$src),
3115 "movntpd\t{$src, $dst|$dst, $src}",
3116 [(alignednontemporalstore (v2f64 VR128:$src),
3118 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3119 (ins f128mem:$dst, VR128:$src),
3120 "movntdq\t{$src, $dst|$dst, $src}",
3121 [(alignednontemporalstore (v2f64 VR128:$src),
3124 let ExeDomain = SSEPackedInt in
3125 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3126 (ins f128mem:$dst, VR128:$src),
3127 "movntdq\t{$src, $dst|$dst, $src}",
3128 [(alignednontemporalstore (v4f32 VR128:$src),
3131 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3132 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3134 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3135 (ins f256mem:$dst, VR256:$src),
3136 "movntps\t{$src, $dst|$dst, $src}",
3137 [(alignednontemporalstore (v8f32 VR256:$src),
3139 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3140 (ins f256mem:$dst, VR256:$src),
3141 "movntpd\t{$src, $dst|$dst, $src}",
3142 [(alignednontemporalstore (v4f64 VR256:$src),
3144 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3145 (ins f256mem:$dst, VR256:$src),
3146 "movntdq\t{$src, $dst|$dst, $src}",
3147 [(alignednontemporalstore (v4f64 VR256:$src),
3149 let ExeDomain = SSEPackedInt in
3150 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3151 (ins f256mem:$dst, VR256:$src),
3152 "movntdq\t{$src, $dst|$dst, $src}",
3153 [(alignednontemporalstore (v8f32 VR256:$src),
3157 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3158 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3159 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3160 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3161 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3162 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3164 let AddedComplexity = 400 in { // Prefer non-temporal versions
3165 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3166 "movntps\t{$src, $dst|$dst, $src}",
3167 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3168 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3169 "movntpd\t{$src, $dst|$dst, $src}",
3170 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3172 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3173 "movntdq\t{$src, $dst|$dst, $src}",
3174 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3176 let ExeDomain = SSEPackedInt in
3177 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3178 "movntdq\t{$src, $dst|$dst, $src}",
3179 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3181 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3182 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3184 // There is no AVX form for instructions below this point
3185 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3186 "movnti{l}\t{$src, $dst|$dst, $src}",
3187 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3188 TB, Requires<[HasSSE2]>;
3189 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3190 "movnti{q}\t{$src, $dst|$dst, $src}",
3191 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3192 TB, Requires<[HasSSE2]>;
3195 //===----------------------------------------------------------------------===//
3196 // SSE 1 & 2 - Prefetch and memory fence
3197 //===----------------------------------------------------------------------===//
3199 // Prefetch intrinsic.
3200 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3201 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3202 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3203 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3204 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3205 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3206 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3207 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3210 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3211 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3212 TB, Requires<[HasSSE2]>;
3214 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3215 // was introduced with SSE2, it's backward compatible.
3216 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3218 // Load, store, and memory fence
3219 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3220 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3221 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3222 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3223 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3224 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3226 def : Pat<(X86SFence), (SFENCE)>;
3227 def : Pat<(X86LFence), (LFENCE)>;
3228 def : Pat<(X86MFence), (MFENCE)>;
3230 //===----------------------------------------------------------------------===//
3231 // SSE 1 & 2 - Load/Store XCSR register
3232 //===----------------------------------------------------------------------===//
3234 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3235 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3236 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3237 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3239 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3240 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3241 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3242 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3244 //===---------------------------------------------------------------------===//
3245 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3246 //===---------------------------------------------------------------------===//
3248 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3250 let neverHasSideEffects = 1 in {
3251 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3252 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3253 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3254 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3256 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3257 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
3258 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3259 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
3261 let canFoldAsLoad = 1, mayLoad = 1 in {
3262 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3263 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3264 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3265 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3266 let Predicates = [HasAVX] in {
3267 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3268 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3269 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3270 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3274 let mayStore = 1 in {
3275 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3276 (ins i128mem:$dst, VR128:$src),
3277 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3278 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3279 (ins i256mem:$dst, VR256:$src),
3280 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3281 let Predicates = [HasAVX] in {
3282 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3283 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3284 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3285 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3289 let neverHasSideEffects = 1 in
3290 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3291 "movdqa\t{$src, $dst|$dst, $src}", []>;
3293 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3294 "movdqu\t{$src, $dst|$dst, $src}",
3295 []>, XS, Requires<[HasSSE2]>;
3297 let canFoldAsLoad = 1, mayLoad = 1 in {
3298 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3299 "movdqa\t{$src, $dst|$dst, $src}",
3300 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3301 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3302 "movdqu\t{$src, $dst|$dst, $src}",
3303 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3304 XS, Requires<[HasSSE2]>;
3307 let mayStore = 1 in {
3308 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3309 "movdqa\t{$src, $dst|$dst, $src}",
3310 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3311 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3312 "movdqu\t{$src, $dst|$dst, $src}",
3313 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3314 XS, Requires<[HasSSE2]>;
3317 // Intrinsic forms of MOVDQU load and store
3318 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3319 "vmovdqu\t{$src, $dst|$dst, $src}",
3320 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3321 XS, VEX, Requires<[HasAVX]>;
3323 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3324 "movdqu\t{$src, $dst|$dst, $src}",
3325 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3326 XS, Requires<[HasSSE2]>;
3328 } // ExeDomain = SSEPackedInt
3330 let Predicates = [HasAVX] in {
3331 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3332 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3333 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3336 //===---------------------------------------------------------------------===//
3337 // SSE2 - Packed Integer Arithmetic Instructions
3338 //===---------------------------------------------------------------------===//
3340 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3342 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3343 bit IsCommutable = 0, bit Is2Addr = 1> {
3344 let isCommutable = IsCommutable in
3345 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3346 (ins VR128:$src1, VR128:$src2),
3348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3350 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3351 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3352 (ins VR128:$src1, i128mem:$src2),
3354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3356 [(set VR128:$dst, (IntId VR128:$src1,
3357 (bitconvert (memopv2i64 addr:$src2))))]>;
3360 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3361 string OpcodeStr, Intrinsic IntId,
3362 Intrinsic IntId2, bit Is2Addr = 1> {
3363 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3364 (ins VR128:$src1, VR128:$src2),
3366 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3368 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3369 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3370 (ins VR128:$src1, i128mem:$src2),
3372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3374 [(set VR128:$dst, (IntId VR128:$src1,
3375 (bitconvert (memopv2i64 addr:$src2))))]>;
3376 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3377 (ins VR128:$src1, i32i8imm:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3381 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3384 /// PDI_binop_rm - Simple SSE2 binary operator.
3385 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3386 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3387 let isCommutable = IsCommutable in
3388 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3389 (ins VR128:$src1, VR128:$src2),
3391 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3392 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3393 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3394 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3395 (ins VR128:$src1, i128mem:$src2),
3397 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3398 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3399 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3400 (bitconvert (memopv2i64 addr:$src2)))))]>;
3403 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3405 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3406 /// to collapse (bitconvert VT to VT) into its operand.
3408 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3409 bit IsCommutable = 0, bit Is2Addr = 1> {
3410 let isCommutable = IsCommutable in
3411 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3412 (ins VR128:$src1, VR128:$src2),
3414 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3416 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3417 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3418 (ins VR128:$src1, i128mem:$src2),
3420 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3422 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3425 } // ExeDomain = SSEPackedInt
3427 // 128-bit Integer Arithmetic
3429 let Predicates = [HasAVX] in {
3430 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3431 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3432 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3433 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3434 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3435 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3436 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3437 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3438 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3441 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3443 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3445 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3447 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3449 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3451 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3453 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3455 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3457 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3459 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3461 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3463 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3465 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3467 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3469 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3471 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3473 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3475 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3477 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3481 let Constraints = "$src1 = $dst" in {
3482 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3483 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3484 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3485 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3486 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3487 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3488 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3489 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3490 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3493 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3494 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3495 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3496 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3497 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3498 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3499 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3500 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3501 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3502 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3503 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3504 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3505 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3506 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3507 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3508 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3509 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3510 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3511 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3513 } // Constraints = "$src1 = $dst"
3515 //===---------------------------------------------------------------------===//
3516 // SSE2 - Packed Integer Logical Instructions
3517 //===---------------------------------------------------------------------===//
3519 let Predicates = [HasAVX] in {
3520 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3521 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3523 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3524 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3526 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3527 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3530 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3531 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3533 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3534 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3536 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3537 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3540 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3541 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3543 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3544 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3547 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3548 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3549 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3551 let ExeDomain = SSEPackedInt in {
3552 let neverHasSideEffects = 1 in {
3553 // 128-bit logical shifts.
3554 def VPSLLDQri : PDIi8<0x73, MRM7r,
3555 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3556 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3558 def VPSRLDQri : PDIi8<0x73, MRM3r,
3559 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3560 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3562 // PSRADQri doesn't exist in SSE[1-3].
3564 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3565 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3566 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3568 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3570 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3571 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3572 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3573 [(set VR128:$dst, (X86andnp VR128:$src1,
3574 (memopv2i64 addr:$src2)))]>, VEX_4V;
3578 let Constraints = "$src1 = $dst" in {
3579 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3580 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3581 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3582 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3583 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3584 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3586 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3587 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3588 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3589 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3590 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3591 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3593 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3594 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3595 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3596 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3598 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3599 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3600 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3602 let ExeDomain = SSEPackedInt in {
3603 let neverHasSideEffects = 1 in {
3604 // 128-bit logical shifts.
3605 def PSLLDQri : PDIi8<0x73, MRM7r,
3606 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3607 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3608 def PSRLDQri : PDIi8<0x73, MRM3r,
3609 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3610 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3611 // PSRADQri doesn't exist in SSE[1-3].
3613 def PANDNrr : PDI<0xDF, MRMSrcReg,
3614 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3615 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3617 def PANDNrm : PDI<0xDF, MRMSrcMem,
3618 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3619 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3621 } // Constraints = "$src1 = $dst"
3623 let Predicates = [HasAVX] in {
3624 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3625 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3626 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3627 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3628 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3629 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3630 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3631 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3632 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3633 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3635 // Shift up / down and insert zero's.
3636 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3637 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3638 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3639 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3642 let Predicates = [HasSSE2] in {
3643 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3644 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3645 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3646 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3647 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3648 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3649 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3650 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3651 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3652 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3654 // Shift up / down and insert zero's.
3655 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3656 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3657 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3658 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3661 //===---------------------------------------------------------------------===//
3662 // SSE2 - Packed Integer Comparison Instructions
3663 //===---------------------------------------------------------------------===//
3665 let Predicates = [HasAVX] in {
3666 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3668 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3670 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3672 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3674 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3676 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3679 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3680 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3681 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3682 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3683 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3684 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3685 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3686 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3687 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3688 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3689 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3690 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3692 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3693 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3694 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3695 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3696 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3697 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3698 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3699 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3700 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3701 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3702 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3703 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3706 let Constraints = "$src1 = $dst" in {
3707 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3708 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3709 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3710 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3711 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3712 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3713 } // Constraints = "$src1 = $dst"
3715 let Predicates = [HasSSE2] in {
3716 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3717 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3718 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3719 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3720 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3721 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3722 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3723 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3724 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3725 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3726 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3727 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3729 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3730 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3731 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3732 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3733 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3734 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3735 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3736 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3737 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3738 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3739 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3740 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3743 //===---------------------------------------------------------------------===//
3744 // SSE2 - Packed Integer Pack Instructions
3745 //===---------------------------------------------------------------------===//
3747 let Predicates = [HasAVX] in {
3748 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3750 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3752 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3756 let Constraints = "$src1 = $dst" in {
3757 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3758 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3759 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3760 } // Constraints = "$src1 = $dst"
3762 //===---------------------------------------------------------------------===//
3763 // SSE2 - Packed Integer Shuffle Instructions
3764 //===---------------------------------------------------------------------===//
3766 let ExeDomain = SSEPackedInt in {
3767 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3769 def ri : Ii8<0x70, MRMSrcReg,
3770 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3771 !strconcat(OpcodeStr,
3772 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3773 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3775 def mi : Ii8<0x70, MRMSrcMem,
3776 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3777 !strconcat(OpcodeStr,
3778 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3779 [(set VR128:$dst, (vt (pshuf_frag:$src2
3780 (bc_frag (memopv2i64 addr:$src1)),
3783 } // ExeDomain = SSEPackedInt
3785 let Predicates = [HasAVX] in {
3786 let AddedComplexity = 5 in
3787 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3790 // SSE2 with ImmT == Imm8 and XS prefix.
3791 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3794 // SSE2 with ImmT == Imm8 and XD prefix.
3795 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3798 let AddedComplexity = 5 in
3799 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3800 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3801 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3802 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3803 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3805 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3807 (VPSHUFDmi addr:$src1, imm:$imm)>;
3808 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3810 (VPSHUFDmi addr:$src1, imm:$imm)>;
3811 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3812 (VPSHUFDri VR128:$src1, imm:$imm)>;
3813 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3814 (VPSHUFDri VR128:$src1, imm:$imm)>;
3815 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3816 (VPSHUFHWri VR128:$src, imm:$imm)>;
3817 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3819 (VPSHUFHWmi addr:$src, imm:$imm)>;
3820 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3821 (VPSHUFLWri VR128:$src, imm:$imm)>;
3822 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3824 (VPSHUFLWmi addr:$src, imm:$imm)>;
3827 let Predicates = [HasSSE2] in {
3828 let AddedComplexity = 5 in
3829 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3831 // SSE2 with ImmT == Imm8 and XS prefix.
3832 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3834 // SSE2 with ImmT == Imm8 and XD prefix.
3835 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3837 let AddedComplexity = 5 in
3838 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3839 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3840 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3841 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3842 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3844 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3846 (PSHUFDmi addr:$src1, imm:$imm)>;
3847 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3849 (PSHUFDmi addr:$src1, imm:$imm)>;
3850 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3851 (PSHUFDri VR128:$src1, imm:$imm)>;
3852 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3853 (PSHUFDri VR128:$src1, imm:$imm)>;
3854 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3855 (PSHUFHWri VR128:$src, imm:$imm)>;
3856 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3858 (PSHUFHWmi addr:$src, imm:$imm)>;
3859 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3860 (PSHUFLWri VR128:$src, imm:$imm)>;
3861 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3863 (PSHUFLWmi addr:$src, imm:$imm)>;
3866 //===---------------------------------------------------------------------===//
3867 // SSE2 - Packed Integer Unpack Instructions
3868 //===---------------------------------------------------------------------===//
3870 let ExeDomain = SSEPackedInt in {
3871 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3872 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3873 def rr : PDI<opc, MRMSrcReg,
3874 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3876 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3877 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3878 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3879 def rm : PDI<opc, MRMSrcMem,
3880 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3882 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3883 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3884 [(set VR128:$dst, (OpNode VR128:$src1,
3885 (bc_frag (memopv2i64
3889 let Predicates = [HasAVX] in {
3890 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3891 bc_v16i8, 0>, VEX_4V;
3892 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3893 bc_v8i16, 0>, VEX_4V;
3894 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3895 bc_v4i32, 0>, VEX_4V;
3897 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3898 /// knew to collapse (bitconvert VT to VT) into its operand.
3899 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3900 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3901 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3902 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3903 VR128:$src2)))]>, VEX_4V;
3904 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3905 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3906 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3907 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3908 (memopv2i64 addr:$src2))))]>, VEX_4V;
3910 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3911 bc_v16i8, 0>, VEX_4V;
3912 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3913 bc_v8i16, 0>, VEX_4V;
3914 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3915 bc_v4i32, 0>, VEX_4V;
3917 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3918 /// knew to collapse (bitconvert VT to VT) into its operand.
3919 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3920 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3921 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3922 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3923 VR128:$src2)))]>, VEX_4V;
3924 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3925 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3926 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3927 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3928 (memopv2i64 addr:$src2))))]>, VEX_4V;
3931 let Constraints = "$src1 = $dst" in {
3932 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3933 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3934 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3936 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3937 /// knew to collapse (bitconvert VT to VT) into its operand.
3938 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3939 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3940 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3942 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3943 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3944 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3945 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3947 (v2i64 (X86Punpcklqdq VR128:$src1,
3948 (memopv2i64 addr:$src2))))]>;
3950 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3951 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3952 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3954 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3955 /// knew to collapse (bitconvert VT to VT) into its operand.
3956 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3957 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3958 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3960 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3961 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3962 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3963 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3965 (v2i64 (X86Punpckhqdq VR128:$src1,
3966 (memopv2i64 addr:$src2))))]>;
3968 } // ExeDomain = SSEPackedInt
3970 // Splat v2f64 / v2i64
3971 let AddedComplexity = 10 in {
3972 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3973 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3974 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3975 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3978 //===---------------------------------------------------------------------===//
3979 // SSE2 - Packed Integer Extract and Insert
3980 //===---------------------------------------------------------------------===//
3982 let ExeDomain = SSEPackedInt in {
3983 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3984 def rri : Ii8<0xC4, MRMSrcReg,
3985 (outs VR128:$dst), (ins VR128:$src1,
3986 GR32:$src2, i32i8imm:$src3),
3988 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3989 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3991 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3992 def rmi : Ii8<0xC4, MRMSrcMem,
3993 (outs VR128:$dst), (ins VR128:$src1,
3994 i16mem:$src2, i32i8imm:$src3),
3996 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3997 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3999 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4004 let Predicates = [HasAVX] in
4005 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4006 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4007 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4008 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4009 imm:$src2))]>, TB, OpSize, VEX;
4010 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4011 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4012 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4013 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4017 let Predicates = [HasAVX] in {
4018 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4019 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4020 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4021 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4022 []>, TB, OpSize, VEX_4V;
4025 let Constraints = "$src1 = $dst" in
4026 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4028 } // ExeDomain = SSEPackedInt
4030 //===---------------------------------------------------------------------===//
4031 // SSE2 - Packed Mask Creation
4032 //===---------------------------------------------------------------------===//
4034 let ExeDomain = SSEPackedInt in {
4036 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4037 "pmovmskb\t{$src, $dst|$dst, $src}",
4038 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4039 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4040 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4041 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4042 "pmovmskb\t{$src, $dst|$dst, $src}",
4043 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4045 } // ExeDomain = SSEPackedInt
4047 //===---------------------------------------------------------------------===//
4048 // SSE2 - Conditional Store
4049 //===---------------------------------------------------------------------===//
4051 let ExeDomain = SSEPackedInt in {
4054 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4055 (ins VR128:$src, VR128:$mask),
4056 "maskmovdqu\t{$mask, $src|$src, $mask}",
4057 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4059 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4060 (ins VR128:$src, VR128:$mask),
4061 "maskmovdqu\t{$mask, $src|$src, $mask}",
4062 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4065 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4066 "maskmovdqu\t{$mask, $src|$src, $mask}",
4067 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4069 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4070 "maskmovdqu\t{$mask, $src|$src, $mask}",
4071 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4073 } // ExeDomain = SSEPackedInt
4075 //===---------------------------------------------------------------------===//
4076 // SSE2 - Move Doubleword
4077 //===---------------------------------------------------------------------===//
4079 //===---------------------------------------------------------------------===//
4080 // Move Int Doubleword to Packed Double Int
4082 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4083 "movd\t{$src, $dst|$dst, $src}",
4085 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4086 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4087 "movd\t{$src, $dst|$dst, $src}",
4089 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4091 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4092 "mov{d|q}\t{$src, $dst|$dst, $src}",
4094 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4095 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4096 "mov{d|q}\t{$src, $dst|$dst, $src}",
4097 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4099 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4100 "movd\t{$src, $dst|$dst, $src}",
4102 (v4i32 (scalar_to_vector GR32:$src)))]>;
4103 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4104 "movd\t{$src, $dst|$dst, $src}",
4106 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4107 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4108 "mov{d|q}\t{$src, $dst|$dst, $src}",
4110 (v2i64 (scalar_to_vector GR64:$src)))]>;
4111 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4112 "mov{d|q}\t{$src, $dst|$dst, $src}",
4113 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4115 //===---------------------------------------------------------------------===//
4116 // Move Int Doubleword to Single Scalar
4118 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4119 "movd\t{$src, $dst|$dst, $src}",
4120 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4122 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4123 "movd\t{$src, $dst|$dst, $src}",
4124 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4126 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4127 "movd\t{$src, $dst|$dst, $src}",
4128 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4130 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4131 "movd\t{$src, $dst|$dst, $src}",
4132 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4134 //===---------------------------------------------------------------------===//
4135 // Move Packed Doubleword Int to Packed Double Int
4137 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4138 "movd\t{$src, $dst|$dst, $src}",
4139 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4141 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4142 (ins i32mem:$dst, VR128:$src),
4143 "movd\t{$src, $dst|$dst, $src}",
4144 [(store (i32 (vector_extract (v4i32 VR128:$src),
4145 (iPTR 0))), addr:$dst)]>, VEX;
4146 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4147 "movd\t{$src, $dst|$dst, $src}",
4148 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4150 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4151 "movd\t{$src, $dst|$dst, $src}",
4152 [(store (i32 (vector_extract (v4i32 VR128:$src),
4153 (iPTR 0))), addr:$dst)]>;
4155 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4156 "mov{d|q}\t{$src, $dst|$dst, $src}",
4157 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4159 //===---------------------------------------------------------------------===//
4160 // Bitcast FR64 <-> GR64
4162 let Predicates = [HasAVX] in
4163 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4164 "vmovq\t{$src, $dst|$dst, $src}",
4165 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4167 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4168 "mov{d|q}\t{$src, $dst|$dst, $src}",
4169 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4170 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4171 "movq\t{$src, $dst|$dst, $src}",
4172 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4174 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4175 "movq\t{$src, $dst|$dst, $src}",
4176 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4177 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4178 "mov{d|q}\t{$src, $dst|$dst, $src}",
4179 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4180 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4181 "movq\t{$src, $dst|$dst, $src}",
4182 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4184 //===---------------------------------------------------------------------===//
4185 // Move Scalar Single to Double Int
4187 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4188 "movd\t{$src, $dst|$dst, $src}",
4189 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4190 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4191 "movd\t{$src, $dst|$dst, $src}",
4192 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4193 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4194 "movd\t{$src, $dst|$dst, $src}",
4195 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4196 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4197 "movd\t{$src, $dst|$dst, $src}",
4198 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4200 //===---------------------------------------------------------------------===//
4201 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4203 let AddedComplexity = 15 in {
4204 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4205 "movd\t{$src, $dst|$dst, $src}",
4206 [(set VR128:$dst, (v4i32 (X86vzmovl
4207 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4209 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4210 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4211 [(set VR128:$dst, (v2i64 (X86vzmovl
4212 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4215 let AddedComplexity = 15 in {
4216 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4217 "movd\t{$src, $dst|$dst, $src}",
4218 [(set VR128:$dst, (v4i32 (X86vzmovl
4219 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4220 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4221 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4222 [(set VR128:$dst, (v2i64 (X86vzmovl
4223 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4226 let AddedComplexity = 20 in {
4227 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4228 "movd\t{$src, $dst|$dst, $src}",
4230 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4231 (loadi32 addr:$src))))))]>,
4233 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4234 "movd\t{$src, $dst|$dst, $src}",
4236 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4237 (loadi32 addr:$src))))))]>;
4240 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4241 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4242 (MOVZDI2PDIrm addr:$src)>;
4243 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4244 (MOVZDI2PDIrm addr:$src)>;
4245 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4246 (MOVZDI2PDIrm addr:$src)>;
4249 let Predicates = [HasAVX] in {
4250 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4251 let AddedComplexity = 20 in {
4252 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4253 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4254 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4255 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4256 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4257 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4259 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4260 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4261 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4262 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4263 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4264 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4265 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4268 // These are the correct encodings of the instructions so that we know how to
4269 // read correct assembly, even though we continue to emit the wrong ones for
4270 // compatibility with Darwin's buggy assembler.
4271 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4272 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4273 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4274 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4275 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4276 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4277 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4278 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4279 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4280 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4281 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4282 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4284 //===---------------------------------------------------------------------===//
4285 // SSE2 - Move Quadword
4286 //===---------------------------------------------------------------------===//
4288 //===---------------------------------------------------------------------===//
4289 // Move Quadword Int to Packed Quadword Int
4291 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4292 "vmovq\t{$src, $dst|$dst, $src}",
4294 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4295 VEX, Requires<[HasAVX]>;
4296 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4297 "movq\t{$src, $dst|$dst, $src}",
4299 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4300 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4302 //===---------------------------------------------------------------------===//
4303 // Move Packed Quadword Int to Quadword Int
4305 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4306 "movq\t{$src, $dst|$dst, $src}",
4307 [(store (i64 (vector_extract (v2i64 VR128:$src),
4308 (iPTR 0))), addr:$dst)]>, VEX;
4309 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4310 "movq\t{$src, $dst|$dst, $src}",
4311 [(store (i64 (vector_extract (v2i64 VR128:$src),
4312 (iPTR 0))), addr:$dst)]>;
4314 //===---------------------------------------------------------------------===//
4315 // Store / copy lower 64-bits of a XMM register.
4317 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4318 "movq\t{$src, $dst|$dst, $src}",
4319 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4320 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4321 "movq\t{$src, $dst|$dst, $src}",
4322 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4324 let AddedComplexity = 20 in
4325 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4326 "vmovq\t{$src, $dst|$dst, $src}",
4328 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4329 (loadi64 addr:$src))))))]>,
4330 XS, VEX, Requires<[HasAVX]>;
4332 let AddedComplexity = 20 in
4333 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4334 "movq\t{$src, $dst|$dst, $src}",
4336 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4337 (loadi64 addr:$src))))))]>,
4338 XS, Requires<[HasSSE2]>;
4340 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4341 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4342 (MOVZQI2PQIrm addr:$src)>;
4343 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4344 (MOVZQI2PQIrm addr:$src)>;
4345 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4348 let Predicates = [HasAVX], AddedComplexity = 20 in {
4349 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4350 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4351 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4352 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4353 def : Pat<(v2i64 (X86vzload addr:$src)),
4354 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4357 //===---------------------------------------------------------------------===//
4358 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4359 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4361 let AddedComplexity = 15 in
4362 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4363 "vmovq\t{$src, $dst|$dst, $src}",
4364 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4365 XS, VEX, Requires<[HasAVX]>;
4366 let AddedComplexity = 15 in
4367 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4368 "movq\t{$src, $dst|$dst, $src}",
4369 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4370 XS, Requires<[HasSSE2]>;
4372 let AddedComplexity = 20 in
4373 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4374 "vmovq\t{$src, $dst|$dst, $src}",
4375 [(set VR128:$dst, (v2i64 (X86vzmovl
4376 (loadv2i64 addr:$src))))]>,
4377 XS, VEX, Requires<[HasAVX]>;
4378 let AddedComplexity = 20 in {
4379 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4380 "movq\t{$src, $dst|$dst, $src}",
4381 [(set VR128:$dst, (v2i64 (X86vzmovl
4382 (loadv2i64 addr:$src))))]>,
4383 XS, Requires<[HasSSE2]>;
4386 let AddedComplexity = 20 in {
4387 let Predicates = [HasSSE2] in {
4388 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4389 (MOVZPQILo2PQIrm addr:$src)>;
4390 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4391 (MOVZPQILo2PQIrr VR128:$src)>;
4393 let Predicates = [HasAVX] in {
4394 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4395 (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIrm addr:$src), sub_xmm)>;
4396 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4397 (SUBREG_TO_REG (i64 0), (MOVZPQILo2PQIrr VR128:$src), sub_xmm)>;
4401 // Instructions to match in the assembler
4402 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4403 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4404 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4405 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4406 // Recognize "movd" with GR64 destination, but encode as a "movq"
4407 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4408 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4410 // Instructions for the disassembler
4411 // xr = XMM register
4414 let Predicates = [HasAVX] in
4415 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4416 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4417 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4418 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4420 //===---------------------------------------------------------------------===//
4421 // SSE3 - Conversion Instructions
4422 //===---------------------------------------------------------------------===//
4424 // Convert Packed Double FP to Packed DW Integers
4425 let Predicates = [HasAVX] in {
4426 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4427 // register, but the same isn't true when using memory operands instead.
4428 // Provide other assembly rr and rm forms to address this explicitly.
4429 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4430 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4431 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4432 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4435 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4436 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4437 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4438 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4441 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4442 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4443 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4444 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4447 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4448 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4449 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4450 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4452 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4453 (VCVTPD2DQYrr VR256:$src)>;
4454 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4455 (VCVTPD2DQYrm addr:$src)>;
4457 // Convert Packed DW Integers to Packed Double FP
4458 let Predicates = [HasAVX] in {
4459 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4460 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4461 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4462 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4463 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4464 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4465 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4466 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4469 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4470 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4471 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4472 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4474 // AVX 256-bit register conversion intrinsics
4475 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4476 (VCVTDQ2PDYrr VR128:$src)>;
4477 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4478 (VCVTDQ2PDYrm addr:$src)>;
4480 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4481 (VCVTPD2DQYrr VR256:$src)>;
4482 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4483 (VCVTPD2DQYrm addr:$src)>;
4485 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4486 (VCVTDQ2PDYrr VR128:$src)>;
4487 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4488 (VCVTDQ2PDYrm addr:$src)>;
4490 //===---------------------------------------------------------------------===//
4491 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4492 //===---------------------------------------------------------------------===//
4493 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4494 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4495 X86MemOperand x86memop> {
4496 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4497 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4498 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4499 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4501 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4504 let Predicates = [HasAVX] in {
4505 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4506 v4f32, VR128, memopv4f32, f128mem>, VEX;
4507 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4508 v4f32, VR128, memopv4f32, f128mem>, VEX;
4509 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4510 v8f32, VR256, memopv8f32, f256mem>, VEX;
4511 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4512 v8f32, VR256, memopv8f32, f256mem>, VEX;
4514 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4515 memopv4f32, f128mem>;
4516 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4517 memopv4f32, f128mem>;
4519 let Predicates = [HasSSE3] in {
4520 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4521 (MOVSHDUPrr VR128:$src)>;
4522 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4523 (MOVSHDUPrm addr:$src)>;
4524 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4525 (MOVSLDUPrr VR128:$src)>;
4526 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4527 (MOVSLDUPrm addr:$src)>;
4530 let Predicates = [HasAVX] in {
4531 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4532 (VMOVSHDUPrr VR128:$src)>;
4533 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4534 (VMOVSHDUPrm addr:$src)>;
4535 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4536 (VMOVSLDUPrr VR128:$src)>;
4537 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4538 (VMOVSLDUPrm addr:$src)>;
4539 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4540 (VMOVSHDUPYrr VR256:$src)>;
4541 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4542 (VMOVSHDUPYrm addr:$src)>;
4543 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4544 (VMOVSLDUPYrr VR256:$src)>;
4545 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4546 (VMOVSLDUPYrm addr:$src)>;
4549 //===---------------------------------------------------------------------===//
4550 // SSE3 - Replicate Double FP - MOVDDUP
4551 //===---------------------------------------------------------------------===//
4553 multiclass sse3_replicate_dfp<string OpcodeStr> {
4554 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4556 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4557 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4560 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4564 // FIXME: Merge with above classe when there're patterns for the ymm version
4565 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4566 let Predicates = [HasAVX] in {
4567 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4570 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4576 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4577 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4578 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4580 let Predicates = [HasSSE3] in {
4581 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4583 (MOVDDUPrm addr:$src)>;
4584 let AddedComplexity = 5 in {
4585 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4586 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4587 (MOVDDUPrm addr:$src)>;
4588 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4589 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4590 (MOVDDUPrm addr:$src)>;
4592 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4593 (MOVDDUPrm addr:$src)>;
4594 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4595 (MOVDDUPrm addr:$src)>;
4596 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4597 (MOVDDUPrm addr:$src)>;
4598 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4599 (MOVDDUPrm addr:$src)>;
4600 def : Pat<(X86Movddup (bc_v2f64
4601 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4602 (MOVDDUPrm addr:$src)>;
4605 let Predicates = [HasAVX] in {
4606 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4608 (VMOVDDUPrm addr:$src)>;
4609 let AddedComplexity = 5 in {
4610 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4611 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4612 (VMOVDDUPrm addr:$src)>;
4613 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4614 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4615 (VMOVDDUPrm addr:$src)>;
4617 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4618 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4619 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4620 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4621 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4622 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4623 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4624 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4625 def : Pat<(X86Movddup (bc_v2f64
4626 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4627 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4630 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4631 (VMOVDDUPYrm addr:$src)>;
4632 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4633 (VMOVDDUPYrm addr:$src)>;
4634 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4635 (VMOVDDUPYrm addr:$src)>;
4636 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4637 (VMOVDDUPYrm addr:$src)>;
4638 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4639 (VMOVDDUPYrr VR256:$src)>;
4640 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4641 (VMOVDDUPYrr VR256:$src)>;
4644 //===---------------------------------------------------------------------===//
4645 // SSE3 - Move Unaligned Integer
4646 //===---------------------------------------------------------------------===//
4648 let Predicates = [HasAVX] in {
4649 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4650 "vlddqu\t{$src, $dst|$dst, $src}",
4651 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4652 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4653 "vlddqu\t{$src, $dst|$dst, $src}",
4654 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4656 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4657 "lddqu\t{$src, $dst|$dst, $src}",
4658 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4660 //===---------------------------------------------------------------------===//
4661 // SSE3 - Arithmetic
4662 //===---------------------------------------------------------------------===//
4664 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4665 X86MemOperand x86memop, bit Is2Addr = 1> {
4666 def rr : I<0xD0, MRMSrcReg,
4667 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4670 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4671 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4672 def rm : I<0xD0, MRMSrcMem,
4673 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4675 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4677 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4680 let Predicates = [HasAVX],
4681 ExeDomain = SSEPackedDouble in {
4682 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4683 f128mem, 0>, TB, XD, VEX_4V;
4684 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4685 f128mem, 0>, TB, OpSize, VEX_4V;
4686 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4687 f256mem, 0>, TB, XD, VEX_4V;
4688 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4689 f256mem, 0>, TB, OpSize, VEX_4V;
4691 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4692 ExeDomain = SSEPackedDouble in {
4693 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4695 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4696 f128mem>, TB, OpSize;
4699 //===---------------------------------------------------------------------===//
4700 // SSE3 Instructions
4701 //===---------------------------------------------------------------------===//
4704 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4705 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4706 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4708 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4709 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4710 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4712 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4715 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4716 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4718 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4719 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4720 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4722 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4723 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4724 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4726 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4728 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4729 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4730 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4733 let Predicates = [HasAVX] in {
4734 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4735 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4736 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4737 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4738 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4739 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4740 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4741 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4742 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4743 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4744 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4745 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4746 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4747 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4748 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4749 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4752 let Constraints = "$src1 = $dst" in {
4753 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4754 int_x86_sse3_hadd_ps>;
4755 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4756 int_x86_sse3_hadd_pd>;
4757 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4758 int_x86_sse3_hsub_ps>;
4759 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4760 int_x86_sse3_hsub_pd>;
4763 //===---------------------------------------------------------------------===//
4764 // SSSE3 - Packed Absolute Instructions
4765 //===---------------------------------------------------------------------===//
4768 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4769 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4770 PatFrag mem_frag128, Intrinsic IntId128> {
4771 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4773 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4774 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4777 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4779 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4782 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4785 let Predicates = [HasAVX] in {
4786 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4787 int_x86_ssse3_pabs_b_128>, VEX;
4788 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4789 int_x86_ssse3_pabs_w_128>, VEX;
4790 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4791 int_x86_ssse3_pabs_d_128>, VEX;
4794 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4795 int_x86_ssse3_pabs_b_128>;
4796 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4797 int_x86_ssse3_pabs_w_128>;
4798 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4799 int_x86_ssse3_pabs_d_128>;
4801 //===---------------------------------------------------------------------===//
4802 // SSSE3 - Packed Binary Operator Instructions
4803 //===---------------------------------------------------------------------===//
4805 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4806 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4807 PatFrag mem_frag128, Intrinsic IntId128,
4809 let isCommutable = 1 in
4810 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4811 (ins VR128:$src1, VR128:$src2),
4813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4814 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4815 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4817 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4818 (ins VR128:$src1, i128mem:$src2),
4820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4823 (IntId128 VR128:$src1,
4824 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4827 let Predicates = [HasAVX] in {
4828 let isCommutable = 0 in {
4829 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4830 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4831 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4832 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4833 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4834 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4835 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4836 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4837 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4838 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4839 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4840 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4841 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4842 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4843 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4844 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4845 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4846 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4847 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4848 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4849 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4850 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4852 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4853 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4856 // None of these have i8 immediate fields.
4857 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4858 let isCommutable = 0 in {
4859 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4860 int_x86_ssse3_phadd_w_128>;
4861 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4862 int_x86_ssse3_phadd_d_128>;
4863 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4864 int_x86_ssse3_phadd_sw_128>;
4865 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4866 int_x86_ssse3_phsub_w_128>;
4867 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4868 int_x86_ssse3_phsub_d_128>;
4869 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4870 int_x86_ssse3_phsub_sw_128>;
4871 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4872 int_x86_ssse3_pmadd_ub_sw_128>;
4873 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4874 int_x86_ssse3_pshuf_b_128>;
4875 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4876 int_x86_ssse3_psign_b_128>;
4877 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4878 int_x86_ssse3_psign_w_128>;
4879 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4880 int_x86_ssse3_psign_d_128>;
4882 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4883 int_x86_ssse3_pmul_hr_sw_128>;
4886 let Predicates = [HasSSSE3] in {
4887 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4888 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4889 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4890 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4892 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4893 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4894 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4895 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4896 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4897 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4900 let Predicates = [HasAVX] in {
4901 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4902 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4903 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4904 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4906 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4907 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4908 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4909 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4910 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4911 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4914 //===---------------------------------------------------------------------===//
4915 // SSSE3 - Packed Align Instruction Patterns
4916 //===---------------------------------------------------------------------===//
4918 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4919 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4920 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4922 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4924 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4926 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4927 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4929 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4931 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4935 let Predicates = [HasAVX] in
4936 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4937 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4938 defm PALIGN : ssse3_palign<"palignr">;
4940 let Predicates = [HasSSSE3] in {
4941 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4942 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4943 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4944 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4945 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4946 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4947 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4948 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4951 let Predicates = [HasAVX] in {
4952 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4953 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4954 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4955 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4956 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4957 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4958 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4959 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4962 //===---------------------------------------------------------------------===//
4963 // SSSE3 - Thread synchronization
4964 //===---------------------------------------------------------------------===//
4966 let usesCustomInserter = 1 in {
4967 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4968 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4969 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4970 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4973 let Uses = [EAX, ECX, EDX] in
4974 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4975 Requires<[HasSSE3]>;
4976 let Uses = [ECX, EAX] in
4977 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4978 Requires<[HasSSE3]>;
4980 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4981 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4983 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4984 Requires<[In32BitMode]>;
4985 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4986 Requires<[In64BitMode]>;
4988 //===----------------------------------------------------------------------===//
4989 // SSE4.1 - Packed Move with Sign/Zero Extend
4990 //===----------------------------------------------------------------------===//
4992 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4993 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4994 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4995 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4997 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5000 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5004 let Predicates = [HasAVX] in {
5005 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5007 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5009 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5011 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5013 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5015 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5019 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5020 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5021 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5022 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5023 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5024 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5026 let Predicates = [HasSSE41] in {
5027 // Common patterns involving scalar load.
5028 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5029 (PMOVSXBWrm addr:$src)>;
5030 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5031 (PMOVSXBWrm addr:$src)>;
5033 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5034 (PMOVSXWDrm addr:$src)>;
5035 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5036 (PMOVSXWDrm addr:$src)>;
5038 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5039 (PMOVSXDQrm addr:$src)>;
5040 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5041 (PMOVSXDQrm addr:$src)>;
5043 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5044 (PMOVZXBWrm addr:$src)>;
5045 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5046 (PMOVZXBWrm addr:$src)>;
5048 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5049 (PMOVZXWDrm addr:$src)>;
5050 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5051 (PMOVZXWDrm addr:$src)>;
5053 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5054 (PMOVZXDQrm addr:$src)>;
5055 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5056 (PMOVZXDQrm addr:$src)>;
5059 let Predicates = [HasAVX] in {
5060 // Common patterns involving scalar load.
5061 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5062 (VPMOVSXBWrm addr:$src)>;
5063 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5064 (VPMOVSXBWrm addr:$src)>;
5066 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5067 (VPMOVSXWDrm addr:$src)>;
5068 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5069 (VPMOVSXWDrm addr:$src)>;
5071 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5072 (VPMOVSXDQrm addr:$src)>;
5073 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5074 (VPMOVSXDQrm addr:$src)>;
5076 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5077 (VPMOVZXBWrm addr:$src)>;
5078 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5079 (VPMOVZXBWrm addr:$src)>;
5081 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5082 (VPMOVZXWDrm addr:$src)>;
5083 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5084 (VPMOVZXWDrm addr:$src)>;
5086 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5087 (VPMOVZXDQrm addr:$src)>;
5088 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5089 (VPMOVZXDQrm addr:$src)>;
5093 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5094 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5095 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5096 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5098 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5099 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5101 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5105 let Predicates = [HasAVX] in {
5106 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5108 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5110 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5112 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5116 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5117 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5118 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5119 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5121 let Predicates = [HasSSE41] in {
5122 // Common patterns involving scalar load
5123 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5124 (PMOVSXBDrm addr:$src)>;
5125 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5126 (PMOVSXWQrm addr:$src)>;
5128 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5129 (PMOVZXBDrm addr:$src)>;
5130 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5131 (PMOVZXWQrm addr:$src)>;
5134 let Predicates = [HasAVX] in {
5135 // Common patterns involving scalar load
5136 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5137 (VPMOVSXBDrm addr:$src)>;
5138 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5139 (VPMOVSXWQrm addr:$src)>;
5141 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5142 (VPMOVZXBDrm addr:$src)>;
5143 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5144 (VPMOVZXWQrm addr:$src)>;
5147 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5148 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5149 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5150 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5152 // Expecting a i16 load any extended to i32 value.
5153 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5154 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5155 [(set VR128:$dst, (IntId (bitconvert
5156 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5160 let Predicates = [HasAVX] in {
5161 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5163 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5166 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5167 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5169 let Predicates = [HasSSE41] in {
5170 // Common patterns involving scalar load
5171 def : Pat<(int_x86_sse41_pmovsxbq
5172 (bitconvert (v4i32 (X86vzmovl
5173 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5174 (PMOVSXBQrm addr:$src)>;
5176 def : Pat<(int_x86_sse41_pmovzxbq
5177 (bitconvert (v4i32 (X86vzmovl
5178 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5179 (PMOVZXBQrm addr:$src)>;
5182 let Predicates = [HasAVX] in {
5183 // Common patterns involving scalar load
5184 def : Pat<(int_x86_sse41_pmovsxbq
5185 (bitconvert (v4i32 (X86vzmovl
5186 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5187 (VPMOVSXBQrm addr:$src)>;
5189 def : Pat<(int_x86_sse41_pmovzxbq
5190 (bitconvert (v4i32 (X86vzmovl
5191 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5192 (VPMOVZXBQrm addr:$src)>;
5195 //===----------------------------------------------------------------------===//
5196 // SSE4.1 - Extract Instructions
5197 //===----------------------------------------------------------------------===//
5199 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5200 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5201 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5202 (ins VR128:$src1, i32i8imm:$src2),
5203 !strconcat(OpcodeStr,
5204 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5205 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5207 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5208 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5209 !strconcat(OpcodeStr,
5210 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5213 // There's an AssertZext in the way of writing the store pattern
5214 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5217 let Predicates = [HasAVX] in {
5218 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5219 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5220 (ins VR128:$src1, i32i8imm:$src2),
5221 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5224 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5227 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5228 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5229 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5230 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5231 !strconcat(OpcodeStr,
5232 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5235 // There's an AssertZext in the way of writing the store pattern
5236 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5239 let Predicates = [HasAVX] in
5240 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5242 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5245 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5246 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5247 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5248 (ins VR128:$src1, i32i8imm:$src2),
5249 !strconcat(OpcodeStr,
5250 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5252 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5253 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5254 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5255 !strconcat(OpcodeStr,
5256 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5257 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5258 addr:$dst)]>, OpSize;
5261 let Predicates = [HasAVX] in
5262 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5264 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5266 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5267 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5268 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5269 (ins VR128:$src1, i32i8imm:$src2),
5270 !strconcat(OpcodeStr,
5271 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5273 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5274 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5275 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5276 !strconcat(OpcodeStr,
5277 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5278 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5279 addr:$dst)]>, OpSize, REX_W;
5282 let Predicates = [HasAVX] in
5283 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5285 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5287 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5289 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5290 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5291 (ins VR128:$src1, i32i8imm:$src2),
5292 !strconcat(OpcodeStr,
5293 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5295 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5297 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5298 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5299 !strconcat(OpcodeStr,
5300 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5301 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5302 addr:$dst)]>, OpSize;
5305 let Predicates = [HasAVX] in {
5306 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5307 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5308 (ins VR128:$src1, i32i8imm:$src2),
5309 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5312 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5314 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5315 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5318 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5319 Requires<[HasSSE41]>;
5320 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5323 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5326 //===----------------------------------------------------------------------===//
5327 // SSE4.1 - Insert Instructions
5328 //===----------------------------------------------------------------------===//
5330 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5331 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5332 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5334 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5336 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5338 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5339 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5340 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5342 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5346 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5347 imm:$src3))]>, OpSize;
5350 let Predicates = [HasAVX] in
5351 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5352 let Constraints = "$src1 = $dst" in
5353 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5355 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5356 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5357 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5359 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5363 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5365 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5366 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5368 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5370 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5372 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5373 imm:$src3)))]>, OpSize;
5376 let Predicates = [HasAVX] in
5377 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5378 let Constraints = "$src1 = $dst" in
5379 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5381 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5382 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5383 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5385 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5389 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5391 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5392 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5394 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5396 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5398 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5399 imm:$src3)))]>, OpSize;
5402 let Predicates = [HasAVX] in
5403 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5404 let Constraints = "$src1 = $dst" in
5405 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5407 // insertps has a few different modes, there's the first two here below which
5408 // are optimized inserts that won't zero arbitrary elements in the destination
5409 // vector. The next one matches the intrinsic and could zero arbitrary elements
5410 // in the target vector.
5411 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5412 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5413 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5415 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5417 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5419 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5421 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5422 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5424 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5428 (X86insrtps VR128:$src1,
5429 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5430 imm:$src3))]>, OpSize;
5433 let Constraints = "$src1 = $dst" in
5434 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5435 let Predicates = [HasAVX] in
5436 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5438 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5439 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5441 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5442 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5443 Requires<[HasSSE41]>;
5445 //===----------------------------------------------------------------------===//
5446 // SSE4.1 - Round Instructions
5447 //===----------------------------------------------------------------------===//
5449 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5450 X86MemOperand x86memop, RegisterClass RC,
5451 PatFrag mem_frag32, PatFrag mem_frag64,
5452 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5453 // Intrinsic operation, reg.
5454 // Vector intrinsic operation, reg
5455 def PSr : SS4AIi8<opcps, MRMSrcReg,
5456 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5457 !strconcat(OpcodeStr,
5458 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5459 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5462 // Vector intrinsic operation, mem
5463 def PSm : Ii8<opcps, MRMSrcMem,
5464 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5465 !strconcat(OpcodeStr,
5466 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5468 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5470 Requires<[HasSSE41]>;
5472 // Vector intrinsic operation, reg
5473 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5474 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5475 !strconcat(OpcodeStr,
5476 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5477 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5480 // Vector intrinsic operation, mem
5481 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5482 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5483 !strconcat(OpcodeStr,
5484 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5486 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5490 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5491 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5492 // Intrinsic operation, reg.
5493 // Vector intrinsic operation, reg
5494 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5495 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5496 !strconcat(OpcodeStr,
5497 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5500 // Vector intrinsic operation, mem
5501 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5502 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5503 !strconcat(OpcodeStr,
5504 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5505 []>, TA, OpSize, Requires<[HasSSE41]>;
5507 // Vector intrinsic operation, reg
5508 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5509 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5510 !strconcat(OpcodeStr,
5511 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5514 // Vector intrinsic operation, mem
5515 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5516 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5517 !strconcat(OpcodeStr,
5518 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5522 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5525 Intrinsic F64Int, bit Is2Addr = 1> {
5526 // Intrinsic operation, reg.
5527 def SSr : SS4AIi8<opcss, MRMSrcReg,
5528 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5530 !strconcat(OpcodeStr,
5531 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5532 !strconcat(OpcodeStr,
5533 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5534 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5537 // Intrinsic operation, mem.
5538 def SSm : SS4AIi8<opcss, MRMSrcMem,
5539 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5541 !strconcat(OpcodeStr,
5542 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5543 !strconcat(OpcodeStr,
5544 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5546 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5549 // Intrinsic operation, reg.
5550 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5551 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5553 !strconcat(OpcodeStr,
5554 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5555 !strconcat(OpcodeStr,
5556 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5557 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5560 // Intrinsic operation, mem.
5561 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5562 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5564 !strconcat(OpcodeStr,
5565 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5566 !strconcat(OpcodeStr,
5567 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5569 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5573 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5575 // Intrinsic operation, reg.
5576 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5577 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5578 !strconcat(OpcodeStr,
5579 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5582 // Intrinsic operation, mem.
5583 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5584 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5585 !strconcat(OpcodeStr,
5586 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5589 // Intrinsic operation, reg.
5590 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5591 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5592 !strconcat(OpcodeStr,
5593 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5596 // Intrinsic operation, mem.
5597 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5598 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5599 !strconcat(OpcodeStr,
5600 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5604 // FP round - roundss, roundps, roundsd, roundpd
5605 let Predicates = [HasAVX] in {
5607 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5608 memopv4f32, memopv2f64,
5609 int_x86_sse41_round_ps,
5610 int_x86_sse41_round_pd>, VEX;
5611 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5612 memopv8f32, memopv4f64,
5613 int_x86_avx_round_ps_256,
5614 int_x86_avx_round_pd_256>, VEX;
5615 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5616 int_x86_sse41_round_ss,
5617 int_x86_sse41_round_sd, 0>, VEX_4V;
5619 // Instructions for the assembler
5620 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5622 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5624 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5627 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5628 memopv4f32, memopv2f64,
5629 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5630 let Constraints = "$src1 = $dst" in
5631 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5632 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5634 //===----------------------------------------------------------------------===//
5635 // SSE4.1 - Packed Bit Test
5636 //===----------------------------------------------------------------------===//
5638 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5639 // the intel intrinsic that corresponds to this.
5640 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5641 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5642 "vptest\t{$src2, $src1|$src1, $src2}",
5643 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5645 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5646 "vptest\t{$src2, $src1|$src1, $src2}",
5647 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5650 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5651 "vptest\t{$src2, $src1|$src1, $src2}",
5652 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5654 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5655 "vptest\t{$src2, $src1|$src1, $src2}",
5656 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5660 let Defs = [EFLAGS] in {
5661 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5662 "ptest \t{$src2, $src1|$src1, $src2}",
5663 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5665 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5666 "ptest \t{$src2, $src1|$src1, $src2}",
5667 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5671 // The bit test instructions below are AVX only
5672 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5673 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5674 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5675 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5676 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5677 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5678 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5679 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5683 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5684 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5685 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5686 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5687 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5690 //===----------------------------------------------------------------------===//
5691 // SSE4.1 - Misc Instructions
5692 //===----------------------------------------------------------------------===//
5694 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5695 "popcnt{w}\t{$src, $dst|$dst, $src}",
5696 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5697 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5698 "popcnt{w}\t{$src, $dst|$dst, $src}",
5699 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5701 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5702 "popcnt{l}\t{$src, $dst|$dst, $src}",
5703 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5704 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5705 "popcnt{l}\t{$src, $dst|$dst, $src}",
5706 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5708 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5709 "popcnt{q}\t{$src, $dst|$dst, $src}",
5710 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5711 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5712 "popcnt{q}\t{$src, $dst|$dst, $src}",
5713 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5717 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5718 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5719 Intrinsic IntId128> {
5720 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5723 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5724 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5726 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5729 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5732 let Predicates = [HasAVX] in
5733 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5734 int_x86_sse41_phminposuw>, VEX;
5735 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5736 int_x86_sse41_phminposuw>;
5738 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5739 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5740 Intrinsic IntId128, bit Is2Addr = 1> {
5741 let isCommutable = 1 in
5742 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5743 (ins VR128:$src1, VR128:$src2),
5745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5747 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5748 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5749 (ins VR128:$src1, i128mem:$src2),
5751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5754 (IntId128 VR128:$src1,
5755 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5758 let Predicates = [HasAVX] in {
5759 let isCommutable = 0 in
5760 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5762 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5764 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5766 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5768 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5770 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5772 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5774 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5776 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5778 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5780 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5783 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5784 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5785 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5786 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5789 let Constraints = "$src1 = $dst" in {
5790 let isCommutable = 0 in
5791 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5792 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5793 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5794 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5795 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5796 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5797 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5798 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5799 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5800 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5801 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5804 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5805 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5806 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5807 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5809 /// SS48I_binop_rm - Simple SSE41 binary operator.
5810 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5811 ValueType OpVT, bit Is2Addr = 1> {
5812 let isCommutable = 1 in
5813 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5814 (ins VR128:$src1, VR128:$src2),
5816 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5817 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5818 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5820 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5821 (ins VR128:$src1, i128mem:$src2),
5823 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5824 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5825 [(set VR128:$dst, (OpNode VR128:$src1,
5826 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5830 let Predicates = [HasAVX] in
5831 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5832 let Constraints = "$src1 = $dst" in
5833 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5835 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5836 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5837 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5838 X86MemOperand x86memop, bit Is2Addr = 1> {
5839 let isCommutable = 1 in
5840 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5841 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5843 !strconcat(OpcodeStr,
5844 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5845 !strconcat(OpcodeStr,
5846 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5847 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5849 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5850 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5852 !strconcat(OpcodeStr,
5853 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5854 !strconcat(OpcodeStr,
5855 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5858 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5862 let Predicates = [HasAVX] in {
5863 let isCommutable = 0 in {
5864 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5865 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5866 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5867 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5868 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5869 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5870 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5871 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5872 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5873 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5874 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5875 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5877 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5878 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5879 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5880 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5881 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5882 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5885 let Constraints = "$src1 = $dst" in {
5886 let isCommutable = 0 in {
5887 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5888 VR128, memopv16i8, i128mem>;
5889 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5890 VR128, memopv16i8, i128mem>;
5891 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5892 VR128, memopv16i8, i128mem>;
5893 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5894 VR128, memopv16i8, i128mem>;
5896 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5897 VR128, memopv16i8, i128mem>;
5898 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5899 VR128, memopv16i8, i128mem>;
5902 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5903 let Predicates = [HasAVX] in {
5904 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5905 RegisterClass RC, X86MemOperand x86memop,
5906 PatFrag mem_frag, Intrinsic IntId> {
5907 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5908 (ins RC:$src1, RC:$src2, RC:$src3),
5909 !strconcat(OpcodeStr,
5910 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5911 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5912 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5914 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5915 (ins RC:$src1, x86memop:$src2, RC:$src3),
5916 !strconcat(OpcodeStr,
5917 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5919 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5921 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5925 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5926 memopv16i8, int_x86_sse41_blendvpd>;
5927 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5928 memopv16i8, int_x86_sse41_blendvps>;
5929 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5930 memopv16i8, int_x86_sse41_pblendvb>;
5931 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5932 memopv32i8, int_x86_avx_blendv_pd_256>;
5933 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5934 memopv32i8, int_x86_avx_blendv_ps_256>;
5936 let Predicates = [HasAVX] in {
5937 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5938 (v16i8 VR128:$src2))),
5939 (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5940 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5941 (v4i32 VR128:$src2))),
5942 (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5943 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5944 (v4f32 VR128:$src2))),
5945 (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5946 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5947 (v2i64 VR128:$src2))),
5948 (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5949 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5950 (v2f64 VR128:$src2))),
5951 (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5952 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5953 (v8i32 VR256:$src2))),
5954 (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5955 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5956 (v8f32 VR256:$src2))),
5957 (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5958 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5959 (v4i64 VR256:$src2))),
5960 (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5961 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5962 (v4f64 VR256:$src2))),
5963 (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5966 /// SS41I_ternary_int - SSE 4.1 ternary operator
5967 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5968 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5969 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5970 (ins VR128:$src1, VR128:$src2),
5971 !strconcat(OpcodeStr,
5972 "\t{$src2, $dst|$dst, $src2}"),
5973 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5976 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5977 (ins VR128:$src1, i128mem:$src2),
5978 !strconcat(OpcodeStr,
5979 "\t{$src2, $dst|$dst, $src2}"),
5982 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5986 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5987 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5988 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5990 let Predicates = [HasSSE41] in {
5991 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
5992 (v16i8 VR128:$src2))),
5993 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5994 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
5995 (v4i32 VR128:$src2))),
5996 (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5997 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
5998 (v4f32 VR128:$src2))),
5999 (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
6000 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6001 (v2i64 VR128:$src2))),
6002 (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
6003 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6004 (v2f64 VR128:$src2))),
6005 (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
6008 let Predicates = [HasAVX] in
6009 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6010 "vmovntdqa\t{$src, $dst|$dst, $src}",
6011 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6013 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6014 "movntdqa\t{$src, $dst|$dst, $src}",
6015 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6018 //===----------------------------------------------------------------------===//
6019 // SSE4.2 - Compare Instructions
6020 //===----------------------------------------------------------------------===//
6022 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6023 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6024 Intrinsic IntId128, bit Is2Addr = 1> {
6025 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6026 (ins VR128:$src1, VR128:$src2),
6028 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6030 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6032 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6033 (ins VR128:$src1, i128mem:$src2),
6035 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6036 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6038 (IntId128 VR128:$src1,
6039 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6042 let Predicates = [HasAVX] in {
6043 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6046 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6047 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6048 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6049 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6052 let Constraints = "$src1 = $dst" in
6053 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6055 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6056 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6057 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6058 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6060 //===----------------------------------------------------------------------===//
6061 // SSE4.2 - String/text Processing Instructions
6062 //===----------------------------------------------------------------------===//
6064 // Packed Compare Implicit Length Strings, Return Mask
6065 multiclass pseudo_pcmpistrm<string asm> {
6066 def REG : PseudoI<(outs VR128:$dst),
6067 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6068 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6070 def MEM : PseudoI<(outs VR128:$dst),
6071 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6072 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6073 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6076 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6077 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6078 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6081 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
6082 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6083 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6084 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6085 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6086 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6087 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6090 let Defs = [XMM0, EFLAGS] in {
6091 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6092 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6093 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6094 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6095 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6096 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6099 // Packed Compare Explicit Length Strings, Return Mask
6100 multiclass pseudo_pcmpestrm<string asm> {
6101 def REG : PseudoI<(outs VR128:$dst),
6102 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6103 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6104 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6105 def MEM : PseudoI<(outs VR128:$dst),
6106 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6107 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6108 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6111 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6112 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6113 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6116 let Predicates = [HasAVX],
6117 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6118 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6119 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6120 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6121 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6122 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6123 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6126 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6127 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6128 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6129 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6130 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6131 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6132 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6135 // Packed Compare Implicit Length Strings, Return Index
6136 let Defs = [ECX, EFLAGS] in {
6137 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6138 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6139 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6140 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6141 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6142 (implicit EFLAGS)]>, OpSize;
6143 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6144 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6145 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6146 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6147 (implicit EFLAGS)]>, OpSize;
6151 let Predicates = [HasAVX] in {
6152 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6154 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6156 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6158 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6160 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6162 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6166 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6167 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6168 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6169 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6170 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6171 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6173 // Packed Compare Explicit Length Strings, Return Index
6174 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6175 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6176 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6177 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6178 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6179 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6180 (implicit EFLAGS)]>, OpSize;
6181 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6182 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6183 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6185 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6186 (implicit EFLAGS)]>, OpSize;
6190 let Predicates = [HasAVX] in {
6191 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6193 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6195 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6197 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6199 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6201 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6205 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6206 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6207 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6208 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6209 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6210 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6212 //===----------------------------------------------------------------------===//
6213 // SSE4.2 - CRC Instructions
6214 //===----------------------------------------------------------------------===//
6216 // No CRC instructions have AVX equivalents
6218 // crc intrinsic instruction
6219 // This set of instructions are only rm, the only difference is the size
6221 let Constraints = "$src1 = $dst" in {
6222 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6223 (ins GR32:$src1, i8mem:$src2),
6224 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6226 (int_x86_sse42_crc32_32_8 GR32:$src1,
6227 (load addr:$src2)))]>;
6228 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6229 (ins GR32:$src1, GR8:$src2),
6230 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6232 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6233 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6234 (ins GR32:$src1, i16mem:$src2),
6235 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6237 (int_x86_sse42_crc32_32_16 GR32:$src1,
6238 (load addr:$src2)))]>,
6240 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6241 (ins GR32:$src1, GR16:$src2),
6242 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6244 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6246 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6247 (ins GR32:$src1, i32mem:$src2),
6248 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6250 (int_x86_sse42_crc32_32_32 GR32:$src1,
6251 (load addr:$src2)))]>;
6252 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6253 (ins GR32:$src1, GR32:$src2),
6254 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6256 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6257 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6258 (ins GR64:$src1, i8mem:$src2),
6259 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6261 (int_x86_sse42_crc32_64_8 GR64:$src1,
6262 (load addr:$src2)))]>,
6264 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6265 (ins GR64:$src1, GR8:$src2),
6266 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6268 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6270 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6271 (ins GR64:$src1, i64mem:$src2),
6272 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6274 (int_x86_sse42_crc32_64_64 GR64:$src1,
6275 (load addr:$src2)))]>,
6277 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6278 (ins GR64:$src1, GR64:$src2),
6279 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6281 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6285 //===----------------------------------------------------------------------===//
6286 // AES-NI Instructions
6287 //===----------------------------------------------------------------------===//
6289 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6290 Intrinsic IntId128, bit Is2Addr = 1> {
6291 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6292 (ins VR128:$src1, VR128:$src2),
6294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6296 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6298 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6299 (ins VR128:$src1, i128mem:$src2),
6301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6304 (IntId128 VR128:$src1,
6305 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6308 // Perform One Round of an AES Encryption/Decryption Flow
6309 let Predicates = [HasAVX, HasAES] in {
6310 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6311 int_x86_aesni_aesenc, 0>, VEX_4V;
6312 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6313 int_x86_aesni_aesenclast, 0>, VEX_4V;
6314 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6315 int_x86_aesni_aesdec, 0>, VEX_4V;
6316 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6317 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6320 let Constraints = "$src1 = $dst" in {
6321 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6322 int_x86_aesni_aesenc>;
6323 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6324 int_x86_aesni_aesenclast>;
6325 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6326 int_x86_aesni_aesdec>;
6327 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6328 int_x86_aesni_aesdeclast>;
6331 let Predicates = [HasAES] in {
6332 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6333 (AESENCrr VR128:$src1, VR128:$src2)>;
6334 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6335 (AESENCrm VR128:$src1, addr:$src2)>;
6336 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6337 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6338 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6339 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6340 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6341 (AESDECrr VR128:$src1, VR128:$src2)>;
6342 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6343 (AESDECrm VR128:$src1, addr:$src2)>;
6344 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6345 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6346 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6347 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6350 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6351 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6352 (VAESENCrr VR128:$src1, VR128:$src2)>;
6353 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6354 (VAESENCrm VR128:$src1, addr:$src2)>;
6355 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6356 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6357 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6358 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6359 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6360 (VAESDECrr VR128:$src1, VR128:$src2)>;
6361 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6362 (VAESDECrm VR128:$src1, addr:$src2)>;
6363 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6364 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6365 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6366 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6369 // Perform the AES InvMixColumn Transformation
6370 let Predicates = [HasAVX, HasAES] in {
6371 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6373 "vaesimc\t{$src1, $dst|$dst, $src1}",
6375 (int_x86_aesni_aesimc VR128:$src1))]>,
6377 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6378 (ins i128mem:$src1),
6379 "vaesimc\t{$src1, $dst|$dst, $src1}",
6381 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6384 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6386 "aesimc\t{$src1, $dst|$dst, $src1}",
6388 (int_x86_aesni_aesimc VR128:$src1))]>,
6390 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6391 (ins i128mem:$src1),
6392 "aesimc\t{$src1, $dst|$dst, $src1}",
6394 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6397 // AES Round Key Generation Assist
6398 let Predicates = [HasAVX, HasAES] in {
6399 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6400 (ins VR128:$src1, i8imm:$src2),
6401 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6403 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6405 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6406 (ins i128mem:$src1, i8imm:$src2),
6407 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6409 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6413 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6414 (ins VR128:$src1, i8imm:$src2),
6415 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6417 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6419 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6420 (ins i128mem:$src1, i8imm:$src2),
6421 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6423 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6427 //===----------------------------------------------------------------------===//
6428 // CLMUL Instructions
6429 //===----------------------------------------------------------------------===//
6431 // Carry-less Multiplication instructions
6432 let Constraints = "$src1 = $dst" in {
6433 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6434 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6435 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6438 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6439 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6440 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6444 // AVX carry-less Multiplication instructions
6445 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6446 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6447 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6450 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6451 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6452 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6456 multiclass pclmul_alias<string asm, int immop> {
6457 def : InstAlias<!strconcat("pclmul", asm,
6458 "dq {$src, $dst|$dst, $src}"),
6459 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6461 def : InstAlias<!strconcat("pclmul", asm,
6462 "dq {$src, $dst|$dst, $src}"),
6463 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6465 def : InstAlias<!strconcat("vpclmul", asm,
6466 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6467 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6469 def : InstAlias<!strconcat("vpclmul", asm,
6470 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6471 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6473 defm : pclmul_alias<"hqhq", 0x11>;
6474 defm : pclmul_alias<"hqlq", 0x01>;
6475 defm : pclmul_alias<"lqhq", 0x10>;
6476 defm : pclmul_alias<"lqlq", 0x00>;
6478 //===----------------------------------------------------------------------===//
6480 //===----------------------------------------------------------------------===//
6482 //===----------------------------------------------------------------------===//
6483 // VBROADCAST - Load from memory and broadcast to all elements of the
6484 // destination operand
6486 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6487 X86MemOperand x86memop, Intrinsic Int> :
6488 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6490 [(set RC:$dst, (Int addr:$src))]>, VEX;
6492 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6493 int_x86_avx_vbroadcastss>;
6494 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6495 int_x86_avx_vbroadcastss_256>;
6496 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6497 int_x86_avx_vbroadcast_sd_256>;
6498 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6499 int_x86_avx_vbroadcastf128_pd_256>;
6501 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6502 (VBROADCASTF128 addr:$src)>;
6504 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6505 (VBROADCASTSSY addr:$src)>;
6506 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6507 (VBROADCASTSD addr:$src)>;
6508 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6509 (VBROADCASTSSY addr:$src)>;
6510 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6511 (VBROADCASTSD addr:$src)>;
6513 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6514 (VBROADCASTSS addr:$src)>;
6515 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6516 (VBROADCASTSS addr:$src)>;
6518 //===----------------------------------------------------------------------===//
6519 // VINSERTF128 - Insert packed floating-point values
6521 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6522 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6523 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6525 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6526 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6527 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6530 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6531 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6532 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6533 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6534 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6535 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6537 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6539 (VINSERTF128rr VR256:$src1, VR128:$src2,
6540 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6541 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6543 (VINSERTF128rr VR256:$src1, VR128:$src2,
6544 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6545 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6547 (VINSERTF128rr VR256:$src1, VR128:$src2,
6548 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6549 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6551 (VINSERTF128rr VR256:$src1, VR128:$src2,
6552 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6553 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6555 (VINSERTF128rr VR256:$src1, VR128:$src2,
6556 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6557 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6559 (VINSERTF128rr VR256:$src1, VR128:$src2,
6560 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6562 //===----------------------------------------------------------------------===//
6563 // VEXTRACTF128 - Extract packed floating-point values
6565 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6566 (ins VR256:$src1, i8imm:$src2),
6567 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6569 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6570 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6571 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6574 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6575 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6576 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6577 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6578 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6579 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6581 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6582 (v4f32 (VEXTRACTF128rr
6583 (v8f32 VR256:$src1),
6584 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6585 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6586 (v2f64 (VEXTRACTF128rr
6587 (v4f64 VR256:$src1),
6588 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6589 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6590 (v4i32 (VEXTRACTF128rr
6591 (v8i32 VR256:$src1),
6592 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6593 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6594 (v2i64 (VEXTRACTF128rr
6595 (v4i64 VR256:$src1),
6596 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6597 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6598 (v8i16 (VEXTRACTF128rr
6599 (v16i16 VR256:$src1),
6600 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6601 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6602 (v16i8 (VEXTRACTF128rr
6603 (v32i8 VR256:$src1),
6604 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6606 //===----------------------------------------------------------------------===//
6607 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6609 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6610 Intrinsic IntLd, Intrinsic IntLd256,
6611 Intrinsic IntSt, Intrinsic IntSt256,
6612 PatFrag pf128, PatFrag pf256> {
6613 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6614 (ins VR128:$src1, f128mem:$src2),
6615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6616 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6618 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6619 (ins VR256:$src1, f256mem:$src2),
6620 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6621 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6623 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6624 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6626 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6627 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6628 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6630 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6633 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6634 int_x86_avx_maskload_ps,
6635 int_x86_avx_maskload_ps_256,
6636 int_x86_avx_maskstore_ps,
6637 int_x86_avx_maskstore_ps_256,
6638 memopv4f32, memopv8f32>;
6639 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6640 int_x86_avx_maskload_pd,
6641 int_x86_avx_maskload_pd_256,
6642 int_x86_avx_maskstore_pd,
6643 int_x86_avx_maskstore_pd_256,
6644 memopv2f64, memopv4f64>;
6646 //===----------------------------------------------------------------------===//
6647 // VPERMIL - Permute Single and Double Floating-Point Values
6649 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6650 RegisterClass RC, X86MemOperand x86memop_f,
6651 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6652 Intrinsic IntVar, Intrinsic IntImm> {
6653 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6654 (ins RC:$src1, RC:$src2),
6655 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6656 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6657 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6658 (ins RC:$src1, x86memop_i:$src2),
6659 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6660 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6662 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6663 (ins RC:$src1, i8imm:$src2),
6664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6665 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6666 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6667 (ins x86memop_f:$src1, i8imm:$src2),
6668 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6669 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6672 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6673 memopv4f32, memopv4i32,
6674 int_x86_avx_vpermilvar_ps,
6675 int_x86_avx_vpermil_ps>;
6676 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6677 memopv8f32, memopv8i32,
6678 int_x86_avx_vpermilvar_ps_256,
6679 int_x86_avx_vpermil_ps_256>;
6680 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6681 memopv2f64, memopv2i64,
6682 int_x86_avx_vpermilvar_pd,
6683 int_x86_avx_vpermil_pd>;
6684 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6685 memopv4f64, memopv4i64,
6686 int_x86_avx_vpermilvar_pd_256,
6687 int_x86_avx_vpermil_pd_256>;
6689 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6690 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6691 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6692 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6693 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6694 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6695 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6696 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6698 //===----------------------------------------------------------------------===//
6699 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6701 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6702 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6703 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6705 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6706 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6707 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6710 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6711 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6712 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6713 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6714 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6715 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6717 def : Pat<(int_x86_avx_vperm2f128_ps_256
6718 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6719 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6720 def : Pat<(int_x86_avx_vperm2f128_pd_256
6721 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6722 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6723 def : Pat<(int_x86_avx_vperm2f128_si_256
6724 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6725 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6727 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6728 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6729 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6730 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6731 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6732 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6733 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6734 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6735 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6736 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6737 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6738 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6740 //===----------------------------------------------------------------------===//
6741 // VZERO - Zero YMM registers
6743 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6744 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6745 // Zero All YMM registers
6746 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6747 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6749 // Zero Upper bits of YMM registers
6750 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6751 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;