1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
939 (VMOVUPSYmr addr:$dst, VR256:$src)>;
940 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
941 (VMOVUPDYmr addr:$dst, VR256:$src)>;
943 let SchedRW = [WriteStore] in {
944 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
945 "movaps\t{$src, $dst|$dst, $src}",
946 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
948 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
949 "movapd\t{$src, $dst|$dst, $src}",
950 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
952 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
953 "movups\t{$src, $dst|$dst, $src}",
954 [(store (v4f32 VR128:$src), addr:$dst)],
956 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movupd\t{$src, $dst|$dst, $src}",
958 [(store (v2f64 VR128:$src), addr:$dst)],
963 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
964 SchedRW = [WriteFShuffle] in {
965 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movaps\t{$src, $dst|$dst, $src}", [],
968 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movapd\t{$src, $dst|$dst, $src}", [],
971 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movups\t{$src, $dst|$dst, $src}", [],
974 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}", [],
979 let Predicates = [HasAVX] in {
980 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
981 (VMOVUPSmr addr:$dst, VR128:$src)>;
982 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
983 (VMOVUPDmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE1] in
987 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
988 (MOVUPSmr addr:$dst, VR128:$src)>;
989 let Predicates = [UseSSE2] in
990 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
991 (MOVUPDmr addr:$dst, VR128:$src)>;
993 // Use vmovaps/vmovups for AVX integer load/store.
994 let Predicates = [HasAVX, NoVLX] in {
995 // 128-bit load/store
996 def : Pat<(alignedloadv2i64 addr:$src),
997 (VMOVAPSrm addr:$src)>;
998 def : Pat<(loadv2i64 addr:$src),
999 (VMOVUPSrm addr:$src)>;
1001 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1002 (VMOVAPSmr addr:$dst, VR128:$src)>;
1003 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1004 (VMOVAPSmr addr:$dst, VR128:$src)>;
1005 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1006 (VMOVAPSmr addr:$dst, VR128:$src)>;
1007 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1008 (VMOVAPSmr addr:$dst, VR128:$src)>;
1009 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1010 (VMOVUPSmr addr:$dst, VR128:$src)>;
1011 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1012 (VMOVUPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1014 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1016 (VMOVUPSmr addr:$dst, VR128:$src)>;
1018 // 256-bit load/store
1019 def : Pat<(alignedloadv4i64 addr:$src),
1020 (VMOVAPSYrm addr:$src)>;
1021 def : Pat<(loadv4i64 addr:$src),
1022 (VMOVUPSYrm addr:$src)>;
1023 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1024 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1025 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1026 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1027 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1028 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1029 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1030 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1031 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1032 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1033 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1034 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1036 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1038 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1040 // Special patterns for storing subvector extracts of lower 128-bits
1041 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1042 def : Pat<(alignedstore (v2f64 (extract_subvector
1043 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v4f32 (extract_subvector
1046 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v2i64 (extract_subvector
1049 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v4i32 (extract_subvector
1052 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v8i16 (extract_subvector
1055 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1057 def : Pat<(alignedstore (v16i8 (extract_subvector
1058 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1059 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v2f64 (extract_subvector
1062 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v4f32 (extract_subvector
1065 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v2i64 (extract_subvector
1068 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v4i32 (extract_subvector
1071 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v8i16 (extract_subvector
1074 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1076 def : Pat<(store (v16i8 (extract_subvector
1077 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1078 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1081 // Use movaps / movups for SSE integer load / store (one byte shorter).
1082 // The instructions selected below are then converted to MOVDQA/MOVDQU
1083 // during the SSE domain pass.
1084 let Predicates = [UseSSE1] in {
1085 def : Pat<(alignedloadv2i64 addr:$src),
1086 (MOVAPSrm addr:$src)>;
1087 def : Pat<(loadv2i64 addr:$src),
1088 (MOVUPSrm addr:$src)>;
1090 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1091 (MOVAPSmr addr:$dst, VR128:$src)>;
1092 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1093 (MOVAPSmr addr:$dst, VR128:$src)>;
1094 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1095 (MOVAPSmr addr:$dst, VR128:$src)>;
1096 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1097 (MOVAPSmr addr:$dst, VR128:$src)>;
1098 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1099 (MOVUPSmr addr:$dst, VR128:$src)>;
1100 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1101 (MOVUPSmr addr:$dst, VR128:$src)>;
1102 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1103 (MOVUPSmr addr:$dst, VR128:$src)>;
1104 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1105 (MOVUPSmr addr:$dst, VR128:$src)>;
1108 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1109 // bits are disregarded. FIXME: Set encoding to pseudo!
1110 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1111 let isCodeGenOnly = 1 in {
1112 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1113 "movaps\t{$src, $dst|$dst, $src}",
1114 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1115 IIC_SSE_MOVA_P_RM>, VEX;
1116 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1117 "movapd\t{$src, $dst|$dst, $src}",
1118 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1119 IIC_SSE_MOVA_P_RM>, VEX;
1120 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1121 "movaps\t{$src, $dst|$dst, $src}",
1122 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1124 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1125 "movapd\t{$src, $dst|$dst, $src}",
1126 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1131 //===----------------------------------------------------------------------===//
1132 // SSE 1 & 2 - Move Low packed FP Instructions
1133 //===----------------------------------------------------------------------===//
1135 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1136 string base_opc, string asm_opr,
1137 InstrItinClass itin> {
1138 def PSrm : PI<opc, MRMSrcMem,
1139 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1140 !strconcat(base_opc, "s", asm_opr),
1142 (psnode VR128:$src1,
1143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, PS,
1145 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1147 def PDrm : PI<opc, MRMSrcMem,
1148 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1149 !strconcat(base_opc, "d", asm_opr),
1150 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1151 (scalar_to_vector (loadf64 addr:$src2)))))],
1152 itin, SSEPackedDouble>, PD,
1153 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1157 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1158 string base_opc, InstrItinClass itin> {
1159 let Predicates = [UseAVX] in
1160 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1161 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1164 let Constraints = "$src1 = $dst" in
1165 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1166 "\t{$src2, $dst|$dst, $src2}",
1170 let AddedComplexity = 20 in {
1171 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1175 let SchedRW = [WriteStore] in {
1176 let Predicates = [UseAVX] in {
1177 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1178 "movlps\t{$src, $dst|$dst, $src}",
1179 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1180 (iPTR 0))), addr:$dst)],
1181 IIC_SSE_MOV_LH>, VEX;
1182 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1183 "movlpd\t{$src, $dst|$dst, $src}",
1184 [(store (f64 (vector_extract (v2f64 VR128:$src),
1185 (iPTR 0))), addr:$dst)],
1186 IIC_SSE_MOV_LH>, VEX;
1188 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1189 "movlps\t{$src, $dst|$dst, $src}",
1190 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1191 (iPTR 0))), addr:$dst)],
1193 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlpd\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (v2f64 VR128:$src),
1196 (iPTR 0))), addr:$dst)],
1200 let Predicates = [UseAVX] in {
1201 // Shuffle with VMOVLPS
1202 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1203 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1205 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1207 // Shuffle with VMOVLPD
1208 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1209 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1211 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1213 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1214 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1222 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1223 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1225 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1226 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1228 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1231 let Predicates = [UseSSE1] in {
1232 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1233 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1234 (iPTR 0))), addr:$src1),
1235 (MOVLPSmr addr:$src1, VR128:$src2)>;
1237 // Shuffle with MOVLPS
1238 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1239 (MOVLPSrm VR128:$src1, addr:$src2)>;
1240 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1241 (MOVLPSrm VR128:$src1, addr:$src2)>;
1242 def : Pat<(X86Movlps VR128:$src1,
1243 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1244 (MOVLPSrm VR128:$src1, addr:$src2)>;
1247 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1249 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 def : Pat<(store (v4i32 (X86Movlps
1251 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1253 (MOVLPSmr addr:$src1, VR128:$src2)>;
1256 let Predicates = [UseSSE2] in {
1257 // Shuffle with MOVLPD
1258 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1259 (MOVLPDrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1261 (MOVLPDrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1263 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1264 (MOVLPDrm VR128:$src1, addr:$src2)>;
1267 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1269 (MOVLPDmr addr:$src1, VR128:$src2)>;
1270 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1272 (MOVLPDmr addr:$src1, VR128:$src2)>;
1275 //===----------------------------------------------------------------------===//
1276 // SSE 1 & 2 - Move Hi packed FP Instructions
1277 //===----------------------------------------------------------------------===//
1279 let AddedComplexity = 20 in {
1280 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1284 let SchedRW = [WriteStore] in {
1285 // v2f64 extract element 1 is always custom lowered to unpack high to low
1286 // and extract element 0 so the non-store version isn't too horrible.
1287 let Predicates = [UseAVX] in {
1288 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1289 "movhps\t{$src, $dst|$dst, $src}",
1290 [(store (f64 (vector_extract
1291 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1292 (bc_v2f64 (v4f32 VR128:$src))),
1293 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1294 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1295 "movhpd\t{$src, $dst|$dst, $src}",
1296 [(store (f64 (vector_extract
1297 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1298 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1300 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1306 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1313 let Predicates = [UseAVX] in {
1315 def : Pat<(X86Movlhps VR128:$src1,
1316 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1317 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1320 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1324 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1325 // is during lowering, where it's not possible to recognize the load fold
1326 // cause it has two uses through a bitcast. One use disappears at isel time
1327 // and the fold opportunity reappears.
1328 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1329 (scalar_to_vector (loadf64 addr:$src2)))),
1330 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1331 // Also handle an i64 load because that may get selected as a faster way to
1333 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1334 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1335 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1337 def : Pat<(store (f64 (vector_extract
1338 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1339 (iPTR 0))), addr:$dst),
1340 (VMOVHPDmr addr:$dst, VR128:$src)>;
1343 let Predicates = [UseSSE1] in {
1345 def : Pat<(X86Movlhps VR128:$src1,
1346 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1347 (MOVHPSrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(X86Movlhps VR128:$src1,
1349 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1350 (MOVHPSrm VR128:$src1, addr:$src2)>;
1353 let Predicates = [UseSSE2] in {
1356 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1357 // is during lowering, where it's not possible to recognize the load fold
1358 // cause it has two uses through a bitcast. One use disappears at isel time
1359 // and the fold opportunity reappears.
1360 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1361 (scalar_to_vector (loadf64 addr:$src2)))),
1362 (MOVHPDrm VR128:$src1, addr:$src2)>;
1363 // Also handle an i64 load because that may get selected as a faster way to
1365 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1366 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1367 (MOVHPDrm VR128:$src1, addr:$src2)>;
1369 def : Pat<(store (f64 (vector_extract
1370 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1371 (iPTR 0))), addr:$dst),
1372 (MOVHPDmr addr:$dst, VR128:$src)>;
1375 //===----------------------------------------------------------------------===//
1376 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1377 //===----------------------------------------------------------------------===//
1379 let AddedComplexity = 20, Predicates = [UseAVX] in {
1380 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1381 (ins VR128:$src1, VR128:$src2),
1382 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1384 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1386 VEX_4V, Sched<[WriteFShuffle]>;
1387 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1388 (ins VR128:$src1, VR128:$src2),
1389 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1391 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1393 VEX_4V, Sched<[WriteFShuffle]>;
1395 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1396 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1397 (ins VR128:$src1, VR128:$src2),
1398 "movlhps\t{$src2, $dst|$dst, $src2}",
1400 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1401 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1402 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1403 (ins VR128:$src1, VR128:$src2),
1404 "movhlps\t{$src2, $dst|$dst, $src2}",
1406 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1407 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1410 let Predicates = [UseAVX] in {
1412 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1413 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1414 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1415 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1418 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1419 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1422 let Predicates = [UseSSE1] in {
1424 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1425 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1426 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1427 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1430 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1431 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1434 //===----------------------------------------------------------------------===//
1435 // SSE 1 & 2 - Conversion Instructions
1436 //===----------------------------------------------------------------------===//
1438 def SSE_CVT_PD : OpndItins<
1439 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1442 let Sched = WriteCvtI2F in
1443 def SSE_CVT_PS : OpndItins<
1444 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1447 let Sched = WriteCvtI2F in
1448 def SSE_CVT_Scalar : OpndItins<
1449 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1452 let Sched = WriteCvtF2I in
1453 def SSE_CVT_SS2SI_32 : OpndItins<
1454 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1457 let Sched = WriteCvtF2I in
1458 def SSE_CVT_SS2SI_64 : OpndItins<
1459 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1462 let Sched = WriteCvtF2I in
1463 def SSE_CVT_SD2SI : OpndItins<
1464 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1467 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1468 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1469 string asm, OpndItins itins> {
1470 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1471 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1472 itins.rr>, Sched<[itins.Sched]>;
1473 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1474 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1475 itins.rm>, Sched<[itins.Sched.Folded]>;
1478 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 X86MemOperand x86memop, string asm, Domain d,
1481 let hasSideEffects = 0 in {
1482 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1483 [], itins.rr, d>, Sched<[itins.Sched]>;
1485 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1486 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1490 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1491 X86MemOperand x86memop, string asm> {
1492 let hasSideEffects = 0, Predicates = [UseAVX] in {
1493 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1494 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1495 Sched<[WriteCvtI2F]>;
1497 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1498 (ins DstRC:$src1, x86memop:$src),
1499 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1500 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1501 } // hasSideEffects = 0
1504 let Predicates = [UseAVX] in {
1505 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1506 "cvttss2si\t{$src, $dst|$dst, $src}",
1509 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1510 "cvttss2si\t{$src, $dst|$dst, $src}",
1512 XS, VEX, VEX_W, VEX_LIG;
1513 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1514 "cvttsd2si\t{$src, $dst|$dst, $src}",
1517 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1518 "cvttsd2si\t{$src, $dst|$dst, $src}",
1520 XD, VEX, VEX_W, VEX_LIG;
1522 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1523 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1524 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1525 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1526 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1527 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1528 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1529 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1530 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1531 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1532 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1533 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1534 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1535 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1536 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1537 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1539 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1540 // register, but the same isn't true when only using memory operands,
1541 // provide other assembly "l" and "q" forms to address this explicitly
1542 // where appropriate to do so.
1543 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1544 XS, VEX_4V, VEX_LIG;
1545 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1546 XS, VEX_4V, VEX_W, VEX_LIG;
1547 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1548 XD, VEX_4V, VEX_LIG;
1549 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1550 XD, VEX_4V, VEX_W, VEX_LIG;
1552 let Predicates = [UseAVX] in {
1553 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1554 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1555 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1556 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1558 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1559 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1560 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1561 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1562 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1563 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1564 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1565 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1567 def : Pat<(f32 (sint_to_fp GR32:$src)),
1568 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1569 def : Pat<(f32 (sint_to_fp GR64:$src)),
1570 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1571 def : Pat<(f64 (sint_to_fp GR32:$src)),
1572 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1573 def : Pat<(f64 (sint_to_fp GR64:$src)),
1574 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1577 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1578 "cvttss2si\t{$src, $dst|$dst, $src}",
1579 SSE_CVT_SS2SI_32>, XS;
1580 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1581 "cvttss2si\t{$src, $dst|$dst, $src}",
1582 SSE_CVT_SS2SI_64>, XS, REX_W;
1583 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1584 "cvttsd2si\t{$src, $dst|$dst, $src}",
1586 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1587 "cvttsd2si\t{$src, $dst|$dst, $src}",
1588 SSE_CVT_SD2SI>, XD, REX_W;
1589 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1590 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1591 SSE_CVT_Scalar>, XS;
1592 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1593 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1594 SSE_CVT_Scalar>, XS, REX_W;
1595 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1596 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1597 SSE_CVT_Scalar>, XD;
1598 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1599 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1600 SSE_CVT_Scalar>, XD, REX_W;
1602 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1603 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1604 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1605 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1606 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1607 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1608 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1609 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1610 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1611 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1612 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1613 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1614 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1615 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1616 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1617 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1619 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1620 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1621 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1622 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1624 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1625 // and/or XMM operand(s).
1627 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1628 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1629 string asm, OpndItins itins> {
1630 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1631 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1632 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1633 Sched<[itins.Sched]>;
1634 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1635 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1636 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1637 Sched<[itins.Sched.Folded]>;
1640 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1641 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1642 PatFrag ld_frag, string asm, OpndItins itins,
1644 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1646 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1647 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1648 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1649 itins.rr>, Sched<[itins.Sched]>;
1650 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1651 (ins DstRC:$src1, x86memop:$src2),
1653 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1654 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1655 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1656 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1659 let Predicates = [UseAVX] in {
1660 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1661 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1662 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1663 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1664 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1665 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1667 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1668 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1669 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1670 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1673 let isCodeGenOnly = 1 in {
1674 let Predicates = [UseAVX] in {
1675 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1676 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1677 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1678 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1679 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1680 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1682 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1683 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1684 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1685 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1686 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1687 SSE_CVT_Scalar, 0>, XD,
1690 let Constraints = "$src1 = $dst" in {
1691 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1692 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1693 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1694 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1695 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1696 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1697 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1698 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1699 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1700 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1701 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1702 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1704 } // isCodeGenOnly = 1
1708 // Aliases for intrinsics
1709 let isCodeGenOnly = 1 in {
1710 let Predicates = [UseAVX] in {
1711 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1712 ssmem, sse_load_f32, "cvttss2si",
1713 SSE_CVT_SS2SI_32>, XS, VEX;
1714 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1715 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1716 "cvttss2si", SSE_CVT_SS2SI_64>,
1718 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1719 sdmem, sse_load_f64, "cvttsd2si",
1720 SSE_CVT_SD2SI>, XD, VEX;
1721 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1722 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1723 "cvttsd2si", SSE_CVT_SD2SI>,
1726 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1727 ssmem, sse_load_f32, "cvttss2si",
1728 SSE_CVT_SS2SI_32>, XS;
1729 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1730 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1731 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1732 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1733 sdmem, sse_load_f64, "cvttsd2si",
1735 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1736 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1737 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1738 } // isCodeGenOnly = 1
1740 let Predicates = [UseAVX] in {
1741 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1742 ssmem, sse_load_f32, "cvtss2si",
1743 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1744 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1745 ssmem, sse_load_f32, "cvtss2si",
1746 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1748 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1749 ssmem, sse_load_f32, "cvtss2si",
1750 SSE_CVT_SS2SI_32>, XS;
1751 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1752 ssmem, sse_load_f32, "cvtss2si",
1753 SSE_CVT_SS2SI_64>, XS, REX_W;
1755 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1756 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1757 SSEPackedSingle, SSE_CVT_PS>,
1758 PS, VEX, Requires<[HasAVX]>;
1759 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1760 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1761 SSEPackedSingle, SSE_CVT_PS>,
1762 PS, VEX, VEX_L, Requires<[HasAVX]>;
1764 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1765 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1766 SSEPackedSingle, SSE_CVT_PS>,
1767 PS, Requires<[UseSSE2]>;
1769 let Predicates = [UseAVX] in {
1770 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1771 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1772 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1773 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1774 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1775 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1776 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1777 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1778 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1779 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1780 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1781 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1782 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1783 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1784 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1785 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1788 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1789 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1790 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1791 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1792 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1793 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1794 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1795 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1796 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1797 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1798 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1799 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1800 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1801 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1802 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1803 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1807 // Convert scalar double to scalar single
1808 let hasSideEffects = 0, Predicates = [UseAVX] in {
1809 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1810 (ins FR64:$src1, FR64:$src2),
1811 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1812 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1813 Sched<[WriteCvtF2F]>;
1815 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1816 (ins FR64:$src1, f64mem:$src2),
1817 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1818 [], IIC_SSE_CVT_Scalar_RM>,
1819 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1820 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1823 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1826 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1827 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1828 [(set FR32:$dst, (fround FR64:$src))],
1829 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1830 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1831 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1832 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1833 IIC_SSE_CVT_Scalar_RM>,
1835 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1837 let isCodeGenOnly = 1 in {
1838 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1839 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1842 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1843 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1844 Sched<[WriteCvtF2F]>;
1845 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1846 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1847 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1848 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1849 VR128:$src1, sse_load_f64:$src2))],
1850 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1851 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1853 let Constraints = "$src1 = $dst" in {
1854 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1855 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1856 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1858 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1859 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1860 Sched<[WriteCvtF2F]>;
1861 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1862 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1863 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1864 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1865 VR128:$src1, sse_load_f64:$src2))],
1866 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1867 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1869 } // isCodeGenOnly = 1
1871 // Convert scalar single to scalar double
1872 // SSE2 instructions with XS prefix
1873 let hasSideEffects = 0, Predicates = [UseAVX] in {
1874 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1875 (ins FR32:$src1, FR32:$src2),
1876 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1877 [], IIC_SSE_CVT_Scalar_RR>,
1878 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1879 Sched<[WriteCvtF2F]>;
1881 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1882 (ins FR32:$src1, f32mem:$src2),
1883 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1884 [], IIC_SSE_CVT_Scalar_RM>,
1885 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1886 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1889 def : Pat<(f64 (fextend FR32:$src)),
1890 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1891 def : Pat<(fextend (loadf32 addr:$src)),
1892 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1894 def : Pat<(extloadf32 addr:$src),
1895 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1896 Requires<[UseAVX, OptForSize]>;
1897 def : Pat<(extloadf32 addr:$src),
1898 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1899 Requires<[UseAVX, OptForSpeed]>;
1901 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1902 "cvtss2sd\t{$src, $dst|$dst, $src}",
1903 [(set FR64:$dst, (fextend FR32:$src))],
1904 IIC_SSE_CVT_Scalar_RR>, XS,
1905 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1906 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1907 "cvtss2sd\t{$src, $dst|$dst, $src}",
1908 [(set FR64:$dst, (extloadf32 addr:$src))],
1909 IIC_SSE_CVT_Scalar_RM>, XS,
1910 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1912 // extload f32 -> f64. This matches load+fextend because we have a hack in
1913 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1915 // Since these loads aren't folded into the fextend, we have to match it
1917 def : Pat<(fextend (loadf32 addr:$src)),
1918 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1919 def : Pat<(extloadf32 addr:$src),
1920 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1922 let isCodeGenOnly = 1 in {
1923 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1924 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1925 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1927 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1928 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1929 Sched<[WriteCvtF2F]>;
1930 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1931 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1932 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1934 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1935 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1936 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1937 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1938 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1939 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1940 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1942 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1943 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1944 Sched<[WriteCvtF2F]>;
1945 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1946 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1947 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1949 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1950 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1951 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1953 } // isCodeGenOnly = 1
1955 // Convert packed single/double fp to doubleword
1956 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1957 "cvtps2dq\t{$src, $dst|$dst, $src}",
1958 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1959 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1960 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1961 "cvtps2dq\t{$src, $dst|$dst, $src}",
1963 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1964 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1965 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1966 "cvtps2dq\t{$src, $dst|$dst, $src}",
1968 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1969 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1970 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1971 "cvtps2dq\t{$src, $dst|$dst, $src}",
1973 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1974 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1975 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1976 "cvtps2dq\t{$src, $dst|$dst, $src}",
1977 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1978 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1979 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1980 "cvtps2dq\t{$src, $dst|$dst, $src}",
1982 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1983 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1986 // Convert Packed Double FP to Packed DW Integers
1987 let Predicates = [HasAVX] in {
1988 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1989 // register, but the same isn't true when using memory operands instead.
1990 // Provide other assembly rr and rm forms to address this explicitly.
1991 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1992 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1994 VEX, Sched<[WriteCvtF2I]>;
1997 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1998 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
1999 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2000 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2002 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2003 Sched<[WriteCvtF2ILd]>;
2006 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2007 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2009 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2010 Sched<[WriteCvtF2I]>;
2011 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2012 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2014 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2015 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2016 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2017 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2020 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2021 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2023 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2024 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2025 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2026 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2027 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2028 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2030 // Convert with truncation packed single/double fp to doubleword
2031 // SSE2 packed instructions with XS prefix
2032 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2033 "cvttps2dq\t{$src, $dst|$dst, $src}",
2035 (int_x86_sse2_cvttps2dq VR128:$src))],
2036 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2037 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2038 "cvttps2dq\t{$src, $dst|$dst, $src}",
2039 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2040 (loadv4f32 addr:$src)))],
2041 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2042 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2043 "cvttps2dq\t{$src, $dst|$dst, $src}",
2045 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2046 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2047 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2048 "cvttps2dq\t{$src, $dst|$dst, $src}",
2049 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2050 (loadv8f32 addr:$src)))],
2051 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2052 Sched<[WriteCvtF2ILd]>;
2054 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2055 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2057 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2058 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2061 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2064 let Predicates = [HasAVX] in {
2065 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2066 (VCVTDQ2PSrr VR128:$src)>;
2067 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2068 (VCVTDQ2PSrm addr:$src)>;
2071 let Predicates = [HasAVX, NoVLX] in {
2072 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2073 (VCVTDQ2PSrr VR128:$src)>;
2074 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2075 (VCVTDQ2PSrm addr:$src)>;
2077 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2078 (VCVTTPS2DQrr VR128:$src)>;
2079 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2080 (VCVTTPS2DQrm addr:$src)>;
2082 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2083 (VCVTDQ2PSYrr VR256:$src)>;
2084 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2085 (VCVTDQ2PSYrm addr:$src)>;
2087 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2088 (VCVTTPS2DQYrr VR256:$src)>;
2089 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2090 (VCVTTPS2DQYrm addr:$src)>;
2093 let Predicates = [UseSSE2] in {
2094 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2095 (CVTDQ2PSrr VR128:$src)>;
2096 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2097 (CVTDQ2PSrm addr:$src)>;
2099 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2100 (CVTDQ2PSrr VR128:$src)>;
2101 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2102 (CVTDQ2PSrm addr:$src)>;
2104 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2105 (CVTTPS2DQrr VR128:$src)>;
2106 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2107 (CVTTPS2DQrm addr:$src)>;
2110 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2111 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2113 (int_x86_sse2_cvttpd2dq VR128:$src))],
2114 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2116 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2117 // register, but the same isn't true when using memory operands instead.
2118 // Provide other assembly rr and rm forms to address this explicitly.
2121 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2122 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2123 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2124 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2125 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2126 (loadv2f64 addr:$src)))],
2127 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2130 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2131 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2133 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2134 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2135 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2136 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2138 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2139 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2140 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2141 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2143 let Predicates = [HasAVX, NoVLX] in {
2144 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2145 (VCVTTPD2DQYrr VR256:$src)>;
2146 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2147 (VCVTTPD2DQYrm addr:$src)>;
2148 } // Predicates = [HasAVX]
2150 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2151 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2152 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2153 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2154 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2155 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2156 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2157 (memopv2f64 addr:$src)))],
2159 Sched<[WriteCvtF2ILd]>;
2161 // Convert packed single to packed double
2162 let Predicates = [HasAVX] in {
2163 // SSE2 instructions without OpSize prefix
2164 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2165 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2166 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2167 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2168 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2169 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2170 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2171 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2172 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2173 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2175 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2177 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2178 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2180 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2181 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2184 let Predicates = [UseSSE2] in {
2185 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2186 "cvtps2pd\t{$src, $dst|$dst, $src}",
2187 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2188 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2189 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2190 "cvtps2pd\t{$src, $dst|$dst, $src}",
2191 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2195 // Convert Packed DW Integers to Packed Double FP
2196 let Predicates = [HasAVX] in {
2197 let hasSideEffects = 0, mayLoad = 1 in
2198 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2199 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2200 []>, VEX, Sched<[WriteCvtI2FLd]>;
2201 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2204 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2205 Sched<[WriteCvtI2F]>;
2206 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2207 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2209 (int_x86_avx_cvtdq2_pd_256
2210 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2211 Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2216 Sched<[WriteCvtI2F]>;
2219 let hasSideEffects = 0, mayLoad = 1 in
2220 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2221 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2222 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2223 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2224 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2225 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2226 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2228 // AVX register conversion intrinsics
2229 let Predicates = [HasAVX] in {
2230 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2231 (VCVTDQ2PDrr VR128:$src)>;
2232 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2233 (VCVTDQ2PDrm addr:$src)>;
2235 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2236 (VCVTDQ2PDYrr VR128:$src)>;
2237 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2238 (VCVTDQ2PDYrm addr:$src)>;
2239 } // Predicates = [HasAVX]
2241 // SSE2 register conversion intrinsics
2242 let Predicates = [HasSSE2] in {
2243 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2244 (CVTDQ2PDrr VR128:$src)>;
2245 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2246 (CVTDQ2PDrm addr:$src)>;
2247 } // Predicates = [HasSSE2]
2249 // Convert packed double to packed single
2250 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2251 // register, but the same isn't true when using memory operands instead.
2252 // Provide other assembly rr and rm forms to address this explicitly.
2253 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2254 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2255 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2256 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2259 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2260 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2261 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2262 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2264 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2265 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2268 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2269 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2271 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2272 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2273 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2274 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2276 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2277 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2278 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2279 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2281 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2282 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2283 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2284 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2285 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2286 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2288 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2289 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2292 // AVX 256-bit register conversion intrinsics
2293 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2294 // whenever possible to avoid declaring two versions of each one.
2295 let Predicates = [HasAVX] in {
2296 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2297 (VCVTDQ2PSYrr VR256:$src)>;
2298 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2299 (VCVTDQ2PSYrm addr:$src)>;
2302 let Predicates = [HasAVX, NoVLX] in {
2303 // Match fround and fextend for 128/256-bit conversions
2304 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2305 (VCVTPD2PSrr VR128:$src)>;
2306 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2307 (VCVTPD2PSXrm addr:$src)>;
2308 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2309 (VCVTPD2PSYrr VR256:$src)>;
2310 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2311 (VCVTPD2PSYrm addr:$src)>;
2313 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2314 (VCVTPS2PDrr VR128:$src)>;
2315 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2316 (VCVTPS2PDYrr VR128:$src)>;
2317 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2318 (VCVTPS2PDYrm addr:$src)>;
2321 let Predicates = [UseSSE2] in {
2322 // Match fround and fextend for 128 conversions
2323 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2324 (CVTPD2PSrr VR128:$src)>;
2325 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2326 (CVTPD2PSrm addr:$src)>;
2328 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2329 (CVTPS2PDrr VR128:$src)>;
2332 //===----------------------------------------------------------------------===//
2333 // SSE 1 & 2 - Compare Instructions
2334 //===----------------------------------------------------------------------===//
2336 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2337 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2338 Operand CC, SDNode OpNode, ValueType VT,
2339 PatFrag ld_frag, string asm, string asm_alt,
2340 OpndItins itins, ImmLeaf immLeaf> {
2341 def rr : SIi8<0xC2, MRMSrcReg,
2342 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2343 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2344 itins.rr>, Sched<[itins.Sched]>;
2345 def rm : SIi8<0xC2, MRMSrcMem,
2346 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2347 [(set RC:$dst, (OpNode (VT RC:$src1),
2348 (ld_frag addr:$src2), immLeaf:$cc))],
2350 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2352 // Accept explicit immediate argument form instead of comparison code.
2353 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2354 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2355 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2356 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2358 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2359 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2360 IIC_SSE_ALU_F32S_RM>,
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2365 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2366 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2367 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2368 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2369 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2370 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2371 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2372 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2373 XD, VEX_4V, VEX_LIG;
2375 let Constraints = "$src1 = $dst" in {
2376 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2378 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2380 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2381 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2382 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2383 SSE_ALU_F64S, i8immZExt3>, XD;
2386 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2387 Intrinsic Int, string asm, OpndItins itins,
2389 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2390 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2391 [(set VR128:$dst, (Int VR128:$src1,
2392 VR128:$src, immLeaf:$cc))],
2394 Sched<[itins.Sched]>;
2395 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2396 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2397 [(set VR128:$dst, (Int VR128:$src1,
2398 (load addr:$src), immLeaf:$cc))],
2400 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2403 let isCodeGenOnly = 1 in {
2404 // Aliases to match intrinsics which expect XMM operand(s).
2405 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2406 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2407 SSE_ALU_F32S, i8immZExt5>,
2409 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2410 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2411 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2413 let Constraints = "$src1 = $dst" in {
2414 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2415 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2416 SSE_ALU_F32S, i8immZExt3>, XS;
2417 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2418 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2419 SSE_ALU_F64S, i8immZExt3>,
2425 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2426 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2427 ValueType vt, X86MemOperand x86memop,
2428 PatFrag ld_frag, string OpcodeStr> {
2429 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2430 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2431 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2434 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2435 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2436 [(set EFLAGS, (OpNode (vt RC:$src1),
2437 (ld_frag addr:$src2)))],
2439 Sched<[WriteFAddLd, ReadAfterLd]>;
2442 let Defs = [EFLAGS] in {
2443 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2444 "ucomiss">, PS, VEX, VEX_LIG;
2445 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2446 "ucomisd">, PD, VEX, VEX_LIG;
2447 let Pattern = []<dag> in {
2448 defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2449 "comiss">, PS, VEX, VEX_LIG;
2450 defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2451 "comisd">, PD, VEX, VEX_LIG;
2454 let isCodeGenOnly = 1 in {
2455 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2456 load, "ucomiss">, PS, VEX;
2457 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2458 load, "ucomisd">, PD, VEX;
2460 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2461 load, "comiss">, PS, VEX;
2462 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2463 load, "comisd">, PD, VEX;
2465 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2467 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2470 let Pattern = []<dag> in {
2471 defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2473 defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2477 let isCodeGenOnly = 1 in {
2478 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2479 load, "ucomiss">, PS;
2480 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2481 load, "ucomisd">, PD;
2483 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2485 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2488 } // Defs = [EFLAGS]
2490 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2491 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2492 Operand CC, Intrinsic Int, string asm,
2493 string asm_alt, Domain d, ImmLeaf immLeaf,
2494 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2495 let isCommutable = 1 in
2496 def rri : PIi8<0xC2, MRMSrcReg,
2497 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2498 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2501 def rmi : PIi8<0xC2, MRMSrcMem,
2502 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2503 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2505 Sched<[WriteFAddLd, ReadAfterLd]>;
2507 // Accept explicit immediate argument form instead of comparison code.
2508 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2509 def rri_alt : PIi8<0xC2, MRMSrcReg,
2510 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2511 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2513 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2514 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2515 asm_alt, [], itins.rm, d>,
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2520 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2521 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2522 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2523 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2524 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2525 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2526 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2527 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2528 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2529 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2530 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2531 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2532 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2533 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2534 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2535 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2536 let Constraints = "$src1 = $dst" in {
2537 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2538 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2539 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2540 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2541 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2542 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2543 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2544 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2547 let Predicates = [HasAVX] in {
2548 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2549 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2550 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2551 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2552 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2553 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2554 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2555 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2557 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2558 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2559 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2560 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2561 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2562 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2563 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2564 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2567 let Predicates = [UseSSE1] in {
2568 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2569 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2570 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2571 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2574 let Predicates = [UseSSE2] in {
2575 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2576 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2577 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2578 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2581 //===----------------------------------------------------------------------===//
2582 // SSE 1 & 2 - Shuffle Instructions
2583 //===----------------------------------------------------------------------===//
2585 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2586 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2587 ValueType vt, string asm, PatFrag mem_frag,
2589 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2590 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2591 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2592 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2593 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2594 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2595 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2596 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2597 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2598 Sched<[WriteFShuffle]>;
2601 let Predicates = [HasAVX, NoVLX] in {
2602 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2603 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2604 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2605 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2606 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2607 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2608 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2609 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2610 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2611 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2612 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2613 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2615 let Constraints = "$src1 = $dst" in {
2616 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2617 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2618 memopv4f32, SSEPackedSingle>, PS;
2619 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2620 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2621 memopv2f64, SSEPackedDouble>, PD;
2624 let Predicates = [HasAVX, NoVLX] in {
2625 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2626 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2627 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2628 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2629 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2631 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2632 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2633 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2634 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2635 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2638 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2639 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2640 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2641 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2642 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2645 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2646 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2647 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2648 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2651 let Predicates = [UseSSE1] in {
2652 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2653 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2654 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2655 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2656 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2659 let Predicates = [UseSSE2] in {
2660 // Generic SHUFPD patterns
2661 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2662 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2663 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2664 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2665 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2668 //===----------------------------------------------------------------------===//
2669 // SSE 1 & 2 - Unpack FP Instructions
2670 //===----------------------------------------------------------------------===//
2672 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2673 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2674 PatFrag mem_frag, RegisterClass RC,
2675 X86MemOperand x86memop, string asm,
2677 def rr : PI<opc, MRMSrcReg,
2678 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2680 (vt (OpNode RC:$src1, RC:$src2)))],
2681 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2682 def rm : PI<opc, MRMSrcMem,
2683 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2685 (vt (OpNode RC:$src1,
2686 (mem_frag addr:$src2))))],
2688 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2691 let Predicates = [HasAVX, NoVLX] in {
2692 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2693 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2694 SSEPackedSingle>, PS, VEX_4V;
2695 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2696 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2697 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2699 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V;
2701 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2702 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V;
2705 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2706 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2708 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2709 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2712 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2714 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2715 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2717 }// Predicates = [HasAVX, NoVLX]
2718 let Constraints = "$src1 = $dst" in {
2719 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2720 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2721 SSEPackedSingle>, PS;
2722 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2723 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2724 SSEPackedDouble>, PD;
2725 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2726 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2727 SSEPackedSingle>, PS;
2728 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2729 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2730 SSEPackedDouble>, PD;
2731 } // Constraints = "$src1 = $dst"
2733 let Predicates = [HasAVX1Only] in {
2734 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2735 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2736 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2737 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2738 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2739 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2740 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2741 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2743 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2744 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2746 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2747 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2748 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2749 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2750 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2753 //===----------------------------------------------------------------------===//
2754 // SSE 1 & 2 - Extract Floating-Point Sign mask
2755 //===----------------------------------------------------------------------===//
2757 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2758 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2760 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2761 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2762 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2763 Sched<[WriteVecLogic]>;
2766 let Predicates = [HasAVX] in {
2767 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2768 "movmskps", SSEPackedSingle>, PS, VEX;
2769 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2770 "movmskpd", SSEPackedDouble>, PD, VEX;
2771 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2772 "movmskps", SSEPackedSingle>, PS,
2774 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2775 "movmskpd", SSEPackedDouble>, PD,
2778 def : Pat<(i32 (X86fgetsign FR32:$src)),
2779 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2780 def : Pat<(i64 (X86fgetsign FR32:$src)),
2781 (SUBREG_TO_REG (i64 0),
2782 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2783 def : Pat<(i32 (X86fgetsign FR64:$src)),
2784 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2785 def : Pat<(i64 (X86fgetsign FR64:$src)),
2786 (SUBREG_TO_REG (i64 0),
2787 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2790 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2791 SSEPackedSingle>, PS;
2792 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2793 SSEPackedDouble>, PD;
2795 def : Pat<(i32 (X86fgetsign FR32:$src)),
2796 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2797 Requires<[UseSSE1]>;
2798 def : Pat<(i64 (X86fgetsign FR32:$src)),
2799 (SUBREG_TO_REG (i64 0),
2800 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2801 Requires<[UseSSE1]>;
2802 def : Pat<(i32 (X86fgetsign FR64:$src)),
2803 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2804 Requires<[UseSSE2]>;
2805 def : Pat<(i64 (X86fgetsign FR64:$src)),
2806 (SUBREG_TO_REG (i64 0),
2807 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2808 Requires<[UseSSE2]>;
2810 //===---------------------------------------------------------------------===//
2811 // SSE2 - Packed Integer Logical Instructions
2812 //===---------------------------------------------------------------------===//
2814 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2816 /// PDI_binop_rm - Simple SSE2 binary operator.
2817 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2818 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2819 X86MemOperand x86memop, OpndItins itins,
2820 bit IsCommutable, bit Is2Addr> {
2821 let isCommutable = IsCommutable in
2822 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2823 (ins RC:$src1, RC:$src2),
2825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2826 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2827 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2828 Sched<[itins.Sched]>;
2829 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2830 (ins RC:$src1, x86memop:$src2),
2832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2834 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2835 (bitconvert (memop_frag addr:$src2)))))],
2837 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2839 } // ExeDomain = SSEPackedInt
2841 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2842 ValueType OpVT128, ValueType OpVT256,
2843 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2844 let Predicates = [HasAVX, prd] in
2845 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2846 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2848 let Constraints = "$src1 = $dst" in
2849 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2850 memopv2i64, i128mem, itins, IsCommutable, 1>;
2852 let Predicates = [HasAVX2, prd] in
2853 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2854 OpVT256, VR256, loadv4i64, i256mem, itins,
2855 IsCommutable, 0>, VEX_4V, VEX_L;
2858 // These are ordered here for pattern ordering requirements with the fp versions
2860 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2861 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2862 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2863 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2864 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2865 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2866 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2867 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2869 //===----------------------------------------------------------------------===//
2870 // SSE 1 & 2 - Logical Instructions
2871 //===----------------------------------------------------------------------===//
2873 // Multiclass for scalars using the X86 logical operation aliases for FP.
2874 multiclass sse12_fp_packed_scalar_logical_alias<
2875 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2876 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2877 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2880 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2881 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2884 let Constraints = "$src1 = $dst" in {
2885 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2886 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2888 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2889 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2893 let isCodeGenOnly = 1 in {
2894 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2896 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2898 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2901 let isCommutable = 0 in
2902 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2906 // Multiclass for vectors using the X86 logical operation aliases for FP.
2907 multiclass sse12_fp_packed_vector_logical_alias<
2908 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2909 let Predicates = [HasAVX, NoVLX] in {
2910 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2911 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2914 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2915 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2918 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2919 VR256, v8f32, f256mem, loadv8f32, SSEPackedSingle, itins, 0>,
2922 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2923 VR256, v4f64, f256mem, loadv4f64, SSEPackedDouble, itins, 0>,
2927 let Constraints = "$src1 = $dst" in {
2928 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2929 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2932 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2933 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2938 let isCodeGenOnly = 1 in {
2939 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2941 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2943 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2946 let isCommutable = 0 in
2947 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2951 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2953 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2955 let Predicates = [HasAVX, NoVLX] in {
2956 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2957 !strconcat(OpcodeStr, "ps"), f256mem,
2958 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2959 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2960 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2962 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2963 !strconcat(OpcodeStr, "pd"), f256mem,
2964 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2965 (bc_v4i64 (v4f64 VR256:$src2))))],
2966 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2967 (loadv4i64 addr:$src2)))], 0>,
2970 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2971 // are all promoted to v2i64, and the patterns are covered by the int
2972 // version. This is needed in SSE only, because v2i64 isn't supported on
2973 // SSE1, but only on SSE2.
2974 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2975 !strconcat(OpcodeStr, "ps"), f128mem, [],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2977 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2979 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2980 !strconcat(OpcodeStr, "pd"), f128mem,
2981 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2982 (bc_v2i64 (v2f64 VR128:$src2))))],
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (loadv2i64 addr:$src2)))], 0>,
2988 let Constraints = "$src1 = $dst" in {
2989 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2990 !strconcat(OpcodeStr, "ps"), f128mem,
2991 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2992 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2993 (memopv2i64 addr:$src2)))]>, PS;
2995 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2996 !strconcat(OpcodeStr, "pd"), f128mem,
2997 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2998 (bc_v2i64 (v2f64 VR128:$src2))))],
2999 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3000 (memopv2i64 addr:$src2)))]>, PD;
3004 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3005 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3006 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3007 let isCommutable = 0 in
3008 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3010 // AVX1 requires type coercions in order to fold loads directly into logical
3012 let Predicates = [HasAVX1Only] in {
3013 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3014 (VANDPSYrm VR256:$src1, addr:$src2)>;
3015 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3016 (VORPSYrm VR256:$src1, addr:$src2)>;
3017 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3018 (VXORPSYrm VR256:$src1, addr:$src2)>;
3019 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3020 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3023 //===----------------------------------------------------------------------===//
3024 // SSE 1 & 2 - Arithmetic Instructions
3025 //===----------------------------------------------------------------------===//
3027 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3030 /// In addition, we also have a special variant of the scalar form here to
3031 /// represent the associated intrinsic operation. This form is unlike the
3032 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3033 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3035 /// These three forms can each be reg+reg or reg+mem.
3038 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3040 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3041 SDNode OpNode, SizeItins itins> {
3042 let Predicates = [HasAVX, NoVLX] in {
3043 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3044 VR128, v4f32, f128mem, loadv4f32,
3045 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3046 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3047 VR128, v2f64, f128mem, loadv2f64,
3048 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3050 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3051 OpNode, VR256, v8f32, f256mem, loadv8f32,
3052 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3053 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3054 OpNode, VR256, v4f64, f256mem, loadv4f64,
3055 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3058 let Constraints = "$src1 = $dst" in {
3059 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3060 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3062 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3063 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3068 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3070 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3071 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3072 XS, VEX_4V, VEX_LIG;
3073 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3074 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3075 XD, VEX_4V, VEX_LIG;
3077 let Constraints = "$src1 = $dst" in {
3078 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3079 OpNode, FR32, f32mem, SSEPackedSingle,
3081 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3082 OpNode, FR64, f64mem, SSEPackedDouble,
3087 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3089 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3090 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3091 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3092 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3093 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3094 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3096 let Constraints = "$src1 = $dst" in {
3097 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3098 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3099 SSEPackedSingle, itins.s>, XS;
3100 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3101 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3102 SSEPackedDouble, itins.d>, XD;
3106 // Binary Arithmetic instructions
3107 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3110 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3111 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3112 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3113 let isCommutable = 0 in {
3114 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3115 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3116 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3117 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3118 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3119 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3120 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3121 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3122 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3123 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3124 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3125 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3128 let isCodeGenOnly = 1 in {
3129 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3130 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3131 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3132 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3135 // Patterns used to select SSE scalar fp arithmetic instructions from
3138 // (1) a scalar fp operation followed by a blend
3140 // The effect is that the backend no longer emits unnecessary vector
3141 // insert instructions immediately after SSE scalar fp instructions
3142 // like addss or mulss.
3144 // For example, given the following code:
3145 // __m128 foo(__m128 A, __m128 B) {
3150 // Previously we generated:
3151 // addss %xmm0, %xmm1
3152 // movss %xmm1, %xmm0
3155 // addss %xmm1, %xmm0
3157 // (2) a vector packed single/double fp operation followed by a vector insert
3159 // The effect is that the backend converts the packed fp instruction
3160 // followed by a vector insert into a single SSE scalar fp instruction.
3162 // For example, given the following code:
3163 // __m128 foo(__m128 A, __m128 B) {
3164 // __m128 C = A + B;
3165 // return (__m128) {c[0], a[1], a[2], a[3]};
3168 // Previously we generated:
3169 // addps %xmm0, %xmm1
3170 // movss %xmm1, %xmm0
3173 // addss %xmm1, %xmm0
3175 // TODO: Some canonicalization in lowering would simplify the number of
3176 // patterns we have to try to match.
3177 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3178 let Predicates = [UseSSE1] in {
3179 // extracted scalar math op with insert via movss
3180 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3181 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3183 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3184 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3186 // vector math op with insert via movss
3187 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3188 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3189 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3192 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3193 let Predicates = [UseSSE41] in {
3194 // extracted scalar math op with insert via blend
3195 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3196 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3197 FR32:$src))), (i8 1))),
3198 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3199 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3201 // vector math op with insert via blend
3202 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3203 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3204 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3208 // Repeat everything for AVX, except for the movss + scalar combo...
3209 // because that one shouldn't occur with AVX codegen?
3210 let Predicates = [HasAVX] in {
3211 // extracted scalar math op with insert via blend
3212 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3213 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3214 FR32:$src))), (i8 1))),
3215 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3216 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3218 // vector math op with insert via movss
3219 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3220 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3221 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3223 // vector math op with insert via blend
3224 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3225 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3226 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3230 defm : scalar_math_f32_patterns<fadd, "ADD">;
3231 defm : scalar_math_f32_patterns<fsub, "SUB">;
3232 defm : scalar_math_f32_patterns<fmul, "MUL">;
3233 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3235 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3236 let Predicates = [UseSSE2] in {
3237 // extracted scalar math op with insert via movsd
3238 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3239 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3241 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3242 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3244 // vector math op with insert via movsd
3245 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3246 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3247 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3250 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3251 let Predicates = [UseSSE41] in {
3252 // extracted scalar math op with insert via blend
3253 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3254 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3255 FR64:$src))), (i8 1))),
3256 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3257 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3259 // vector math op with insert via blend
3260 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3261 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3262 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3265 // Repeat everything for AVX.
3266 let Predicates = [HasAVX] in {
3267 // extracted scalar math op with insert via movsd
3268 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3269 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3271 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3272 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3274 // extracted scalar math op with insert via blend
3275 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3276 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3277 FR64:$src))), (i8 1))),
3278 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3279 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3281 // vector math op with insert via movsd
3282 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3283 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3284 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3286 // vector math op with insert via blend
3287 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3288 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3289 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3293 defm : scalar_math_f64_patterns<fadd, "ADD">;
3294 defm : scalar_math_f64_patterns<fsub, "SUB">;
3295 defm : scalar_math_f64_patterns<fmul, "MUL">;
3296 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3300 /// In addition, we also have a special variant of the scalar form here to
3301 /// represent the associated intrinsic operation. This form is unlike the
3302 /// plain scalar form, in that it takes an entire vector (instead of a
3303 /// scalar) and leaves the top elements undefined.
3305 /// And, we have a special variant form for a full-vector intrinsic form.
3307 let Sched = WriteFSqrt in {
3308 def SSE_SQRTPS : OpndItins<
3309 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3312 def SSE_SQRTSS : OpndItins<
3313 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3316 def SSE_SQRTPD : OpndItins<
3317 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3320 def SSE_SQRTSD : OpndItins<
3321 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3325 let Sched = WriteFRsqrt in {
3326 def SSE_RSQRTPS : OpndItins<
3327 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3330 def SSE_RSQRTSS : OpndItins<
3331 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3335 let Sched = WriteFRcp in {
3336 def SSE_RCPP : OpndItins<
3337 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3340 def SSE_RCPS : OpndItins<
3341 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3345 /// sse_fp_unop_s - SSE1 unops in scalar form
3346 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3347 /// the HW instructions are 2 operand / destructive.
3348 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3349 ValueType vt, ValueType ScalarVT,
3350 X86MemOperand x86memop, Operand vec_memop,
3351 ComplexPattern mem_cpat, Intrinsic Intr,
3352 SDNode OpNode, Domain d, OpndItins itins,
3353 Predicate target, string Suffix> {
3354 let hasSideEffects = 0 in {
3355 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3356 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3357 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3360 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3361 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3362 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3363 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3364 Requires<[target, OptForSize]>;
3366 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3367 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3368 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3369 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3371 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3373 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3377 let Predicates = [target] in {
3378 def : Pat<(vt (OpNode mem_cpat:$src)),
3379 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3380 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3381 // These are unary operations, but they are modeled as having 2 source operands
3382 // because the high elements of the destination are unchanged in SSE.
3383 def : Pat<(Intr VR128:$src),
3384 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3385 def : Pat<(Intr (load addr:$src)),
3386 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3387 addr:$src), VR128))>;
3388 def : Pat<(Intr mem_cpat:$src),
3389 (!cast<Instruction>(NAME#Suffix##m_Int)
3390 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3394 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3395 ValueType vt, ValueType ScalarVT,
3396 X86MemOperand x86memop, Operand vec_memop,
3397 ComplexPattern mem_cpat,
3398 Intrinsic Intr, SDNode OpNode, Domain d,
3399 OpndItins itins, string Suffix> {
3400 let hasSideEffects = 0 in {
3401 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3402 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3403 [], itins.rr, d>, Sched<[itins.Sched]>;
3405 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3406 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3408 let isCodeGenOnly = 1 in {
3409 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3410 (ins VR128:$src1, VR128:$src2),
3411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3412 []>, Sched<[itins.Sched.Folded]>;
3414 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3415 (ins VR128:$src1, vec_memop:$src2),
3416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3417 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3421 let Predicates = [UseAVX] in {
3422 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3423 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3425 def : Pat<(vt (OpNode mem_cpat:$src)),
3426 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3430 let Predicates = [HasAVX] in {
3431 def : Pat<(Intr VR128:$src),
3432 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3435 def : Pat<(Intr mem_cpat:$src),
3436 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3437 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3439 let Predicates = [UseAVX, OptForSize] in
3440 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3441 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3445 /// sse1_fp_unop_p - SSE1 unops in packed form.
3446 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3448 let Predicates = [HasAVX] in {
3449 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3450 !strconcat("v", OpcodeStr,
3451 "ps\t{$src, $dst|$dst, $src}"),
3452 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3453 itins.rr>, VEX, Sched<[itins.Sched]>;
3454 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3455 !strconcat("v", OpcodeStr,
3456 "ps\t{$src, $dst|$dst, $src}"),
3457 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3458 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3459 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3460 !strconcat("v", OpcodeStr,
3461 "ps\t{$src, $dst|$dst, $src}"),
3462 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3463 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3464 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3465 !strconcat("v", OpcodeStr,
3466 "ps\t{$src, $dst|$dst, $src}"),
3467 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3468 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3471 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3472 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3473 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3474 Sched<[itins.Sched]>;
3475 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3476 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3477 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3478 Sched<[itins.Sched.Folded]>;
3481 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3482 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3483 SDNode OpNode, OpndItins itins> {
3484 let Predicates = [HasAVX] in {
3485 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3486 !strconcat("v", OpcodeStr,
3487 "pd\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3489 itins.rr>, VEX, Sched<[itins.Sched]>;
3490 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3491 !strconcat("v", OpcodeStr,
3492 "pd\t{$src, $dst|$dst, $src}"),
3493 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3494 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3495 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3496 !strconcat("v", OpcodeStr,
3497 "pd\t{$src, $dst|$dst, $src}"),
3498 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3499 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3500 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3501 !strconcat("v", OpcodeStr,
3502 "pd\t{$src, $dst|$dst, $src}"),
3503 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3504 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3507 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3508 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3509 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3510 Sched<[itins.Sched]>;
3511 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3512 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3513 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3514 Sched<[itins.Sched.Folded]>;
3517 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3519 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3520 ssmem, sse_load_f32,
3521 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3522 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3523 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3524 f32mem, ssmem, sse_load_f32,
3525 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3526 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3529 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3531 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3532 sdmem, sse_load_f64,
3533 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3534 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3535 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3536 f64mem, sdmem, sse_load_f64,
3537 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3538 OpNode, SSEPackedDouble, itins, "SD">,
3539 XD, VEX_4V, VEX_LIG;
3543 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3544 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3545 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3546 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3548 // Reciprocal approximations. Note that these typically require refinement
3549 // in order to obtain suitable precision.
3550 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3551 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3552 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3553 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3555 // There is no f64 version of the reciprocal approximation instructions.
3557 // TODO: We should add *scalar* op patterns for these just like we have for
3558 // the binops above. If the binop and unop patterns could all be unified
3559 // that would be even better.
3561 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3562 SDNode Move, ValueType VT,
3563 Predicate BasePredicate> {
3564 let Predicates = [BasePredicate] in {
3565 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3566 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3569 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3570 let Predicates = [UseSSE41] in {
3571 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3572 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3575 // Repeat for AVX versions of the instructions.
3576 let Predicates = [HasAVX] in {
3577 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3578 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3580 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3581 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3585 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3587 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3589 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3591 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3595 //===----------------------------------------------------------------------===//
3596 // SSE 1 & 2 - Non-temporal stores
3597 //===----------------------------------------------------------------------===//
3599 let AddedComplexity = 400 in { // Prefer non-temporal versions
3600 let SchedRW = [WriteStore] in {
3601 let Predicates = [HasAVX, NoVLX] in {
3602 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3603 (ins f128mem:$dst, VR128:$src),
3604 "movntps\t{$src, $dst|$dst, $src}",
3605 [(alignednontemporalstore (v4f32 VR128:$src),
3607 IIC_SSE_MOVNT>, VEX;
3608 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3609 (ins f128mem:$dst, VR128:$src),
3610 "movntpd\t{$src, $dst|$dst, $src}",
3611 [(alignednontemporalstore (v2f64 VR128:$src),
3613 IIC_SSE_MOVNT>, VEX;
3615 let ExeDomain = SSEPackedInt in
3616 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3617 (ins f128mem:$dst, VR128:$src),
3618 "movntdq\t{$src, $dst|$dst, $src}",
3619 [(alignednontemporalstore (v2i64 VR128:$src),
3621 IIC_SSE_MOVNT>, VEX;
3623 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3624 (ins f256mem:$dst, VR256:$src),
3625 "movntps\t{$src, $dst|$dst, $src}",
3626 [(alignednontemporalstore (v8f32 VR256:$src),
3628 IIC_SSE_MOVNT>, VEX, VEX_L;
3629 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3630 (ins f256mem:$dst, VR256:$src),
3631 "movntpd\t{$src, $dst|$dst, $src}",
3632 [(alignednontemporalstore (v4f64 VR256:$src),
3634 IIC_SSE_MOVNT>, VEX, VEX_L;
3635 let ExeDomain = SSEPackedInt in
3636 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3637 (ins f256mem:$dst, VR256:$src),
3638 "movntdq\t{$src, $dst|$dst, $src}",
3639 [(alignednontemporalstore (v4i64 VR256:$src),
3641 IIC_SSE_MOVNT>, VEX, VEX_L;
3644 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3645 "movntps\t{$src, $dst|$dst, $src}",
3646 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3648 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3649 "movntpd\t{$src, $dst|$dst, $src}",
3650 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3653 let ExeDomain = SSEPackedInt in
3654 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3655 "movntdq\t{$src, $dst|$dst, $src}",
3656 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3659 // There is no AVX form for instructions below this point
3660 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3661 "movnti{l}\t{$src, $dst|$dst, $src}",
3662 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3664 PS, Requires<[HasSSE2]>;
3665 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3666 "movnti{q}\t{$src, $dst|$dst, $src}",
3667 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3669 PS, Requires<[HasSSE2]>;
3670 } // SchedRW = [WriteStore]
3672 let Predicates = [HasAVX2, NoVLX] in {
3673 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3674 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3675 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3676 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3677 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3678 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3681 let Predicates = [HasAVX, NoVLX] in {
3682 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3683 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3684 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3685 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3686 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3687 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3690 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3691 (MOVNTDQmr addr:$dst, VR128:$src)>;
3692 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3693 (MOVNTDQmr addr:$dst, VR128:$src)>;
3694 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3695 (MOVNTDQmr addr:$dst, VR128:$src)>;
3697 } // AddedComplexity
3699 //===----------------------------------------------------------------------===//
3700 // SSE 1 & 2 - Prefetch and memory fence
3701 //===----------------------------------------------------------------------===//
3703 // Prefetch intrinsic.
3704 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3705 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3706 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3707 IIC_SSE_PREFETCH>, TB;
3708 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3709 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3710 IIC_SSE_PREFETCH>, TB;
3711 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3712 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3713 IIC_SSE_PREFETCH>, TB;
3714 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3715 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3716 IIC_SSE_PREFETCH>, TB;
3719 // FIXME: How should flush instruction be modeled?
3720 let SchedRW = [WriteLoad] in {
3722 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3723 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3724 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3727 let SchedRW = [WriteNop] in {
3728 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3729 // was introduced with SSE2, it's backward compatible.
3730 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3731 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3732 OBXS, Requires<[HasSSE2]>;
3735 let SchedRW = [WriteFence] in {
3736 // Load, store, and memory fence
3737 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3738 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3739 PS, Requires<[HasSSE1]>;
3740 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3741 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3742 TB, Requires<[HasSSE2]>;
3743 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3744 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3745 TB, Requires<[HasSSE2]>;
3748 def : Pat<(X86SFence), (SFENCE)>;
3749 def : Pat<(X86LFence), (LFENCE)>;
3750 def : Pat<(X86MFence), (MFENCE)>;
3752 //===----------------------------------------------------------------------===//
3753 // SSE 1 & 2 - Load/Store XCSR register
3754 //===----------------------------------------------------------------------===//
3756 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3757 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3758 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3759 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3760 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3761 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3763 let Predicates = [UseSSE1] in {
3764 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3765 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3766 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3767 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3768 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3769 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3772 //===---------------------------------------------------------------------===//
3773 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3774 //===---------------------------------------------------------------------===//
3776 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3778 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3779 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3780 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3782 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3783 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3785 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3786 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3788 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3789 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3794 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3795 SchedRW = [WriteMove] in {
3796 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3797 "movdqa\t{$src, $dst|$dst, $src}", [],
3800 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3801 "movdqa\t{$src, $dst|$dst, $src}", [],
3802 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3803 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3804 "movdqu\t{$src, $dst|$dst, $src}", [],
3807 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3808 "movdqu\t{$src, $dst|$dst, $src}", [],
3809 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3812 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3813 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3814 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3815 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3817 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3818 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3820 let Predicates = [HasAVX] in {
3821 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3822 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3824 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3825 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3830 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3831 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3832 (ins i128mem:$dst, VR128:$src),
3833 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3835 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3836 (ins i256mem:$dst, VR256:$src),
3837 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3839 let Predicates = [HasAVX] in {
3840 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3841 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3843 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3844 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3849 let SchedRW = [WriteMove] in {
3850 let hasSideEffects = 0 in
3851 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3852 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3854 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3855 "movdqu\t{$src, $dst|$dst, $src}",
3856 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3859 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3860 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3861 "movdqa\t{$src, $dst|$dst, $src}", [],
3864 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3865 "movdqu\t{$src, $dst|$dst, $src}",
3866 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3870 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3871 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3872 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3873 "movdqa\t{$src, $dst|$dst, $src}",
3874 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3876 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3877 "movdqu\t{$src, $dst|$dst, $src}",
3878 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3880 XS, Requires<[UseSSE2]>;
3883 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3884 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3885 "movdqa\t{$src, $dst|$dst, $src}",
3886 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3888 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3889 "movdqu\t{$src, $dst|$dst, $src}",
3890 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3892 XS, Requires<[UseSSE2]>;
3895 } // ExeDomain = SSEPackedInt
3897 let Predicates = [HasAVX] in {
3898 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3899 (VMOVDQUmr addr:$dst, VR128:$src)>;
3900 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3901 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3903 let Predicates = [UseSSE2] in
3904 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3905 (MOVDQUmr addr:$dst, VR128:$src)>;
3907 //===---------------------------------------------------------------------===//
3908 // SSE2 - Packed Integer Arithmetic Instructions
3909 //===---------------------------------------------------------------------===//
3911 let Sched = WriteVecIMul in
3912 def SSE_PMADD : OpndItins<
3913 IIC_SSE_PMADD, IIC_SSE_PMADD
3916 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3918 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3919 RegisterClass RC, PatFrag memop_frag,
3920 X86MemOperand x86memop,
3922 bit IsCommutable = 0,
3924 let isCommutable = IsCommutable in
3925 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3926 (ins RC:$src1, RC:$src2),
3928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3929 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3930 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3931 Sched<[itins.Sched]>;
3932 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3933 (ins RC:$src1, x86memop:$src2),
3935 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3936 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3937 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3938 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3941 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3942 Intrinsic IntId256, OpndItins itins,
3943 bit IsCommutable = 0> {
3944 let Predicates = [HasAVX] in
3945 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3946 VR128, loadv2i64, i128mem, itins,
3947 IsCommutable, 0>, VEX_4V;
3949 let Constraints = "$src1 = $dst" in
3950 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3951 i128mem, itins, IsCommutable, 1>;
3953 let Predicates = [HasAVX2] in
3954 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3955 VR256, loadv4i64, i256mem, itins,
3956 IsCommutable, 0>, VEX_4V, VEX_L;
3959 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3960 string OpcodeStr, SDNode OpNode,
3961 SDNode OpNode2, RegisterClass RC,
3962 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3963 PatFrag ld_frag, ShiftOpndItins itins,
3965 // src2 is always 128-bit
3966 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3967 (ins RC:$src1, VR128:$src2),
3969 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3970 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3971 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3972 itins.rr>, Sched<[WriteVecShift]>;
3973 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3974 (ins RC:$src1, i128mem:$src2),
3976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3978 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3979 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3980 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3981 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3982 (ins RC:$src1, u8imm:$src2),
3984 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3986 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3987 Sched<[WriteVecShift]>;
3990 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3991 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3992 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3993 PatFrag memop_frag, X86MemOperand x86memop,
3995 bit IsCommutable = 0, bit Is2Addr = 1> {
3996 let isCommutable = IsCommutable in
3997 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3998 (ins RC:$src1, RC:$src2),
4000 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4002 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4003 Sched<[itins.Sched]>;
4004 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4005 (ins RC:$src1, x86memop:$src2),
4007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4009 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4010 (bitconvert (memop_frag addr:$src2)))))]>,
4011 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4013 } // ExeDomain = SSEPackedInt
4015 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4016 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4017 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4018 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4019 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4020 SSE_INTALU_ITINS_P, 1, NoVLX>;
4021 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4022 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4023 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4024 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4025 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4026 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4027 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4028 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4029 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4030 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4031 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4032 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4033 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4034 SSE_INTALU_ITINS_P, 0, NoVLX>;
4035 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4036 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4037 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4038 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4039 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4040 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4041 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4042 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4043 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4044 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4045 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4046 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4047 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4048 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4049 defm PAVGB : PDI_binop_all<0xE0, "pavgb", X86avg, v16i8, v32i8,
4050 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4051 defm PAVGW : PDI_binop_all<0xE3, "pavgw", X86avg, v8i16, v16i16,
4052 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4055 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4056 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4057 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4058 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4059 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4060 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4061 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4062 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4063 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4064 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4065 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4066 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4067 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4068 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4069 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4070 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4072 let Predicates = [HasAVX2] in
4073 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4074 (v32i8 VR256:$src2))),
4075 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4077 let Predicates = [HasAVX] in
4078 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4079 (v16i8 VR128:$src2))),
4080 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4082 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4083 (v16i8 VR128:$src2))),
4084 (PSADBWrr VR128:$src2, VR128:$src1)>;
4086 let Predicates = [HasAVX] in
4087 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4088 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4090 let Predicates = [HasAVX2] in
4091 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4092 VR256, loadv4i64, i256mem,
4093 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4094 let Constraints = "$src1 = $dst" in
4095 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4096 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4098 //===---------------------------------------------------------------------===//
4099 // SSE2 - Packed Integer Logical Instructions
4100 //===---------------------------------------------------------------------===//
4102 let Predicates = [HasAVX, NoVLX] in {
4103 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4104 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4105 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4106 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4107 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4108 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4109 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4110 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4111 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4113 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4114 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4115 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4116 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4117 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4118 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4119 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4120 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4121 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4123 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4124 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4125 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4126 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4127 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4128 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4129 } // Predicates = [HasAVX]
4131 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] ,
4132 Predicates = [HasAVX, NoVLX_Or_NoBWI]in {
4133 // 128-bit logical shifts.
4134 def VPSLLDQri : PDIi8<0x73, MRM7r,
4135 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4136 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4138 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4140 def VPSRLDQri : PDIi8<0x73, MRM3r,
4141 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4142 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4144 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4146 // PSRADQri doesn't exist in SSE[1-3].
4147 } // Predicates = [HasAVX, NoVLX_Or_NoBWI]
4149 let Predicates = [HasAVX2, NoVLX] in {
4150 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4151 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4152 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4153 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4154 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4155 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4156 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4157 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4158 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4160 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4161 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4162 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4163 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4164 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4165 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4166 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4167 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4168 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4170 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4171 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4172 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4173 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4174 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4175 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4176 }// Predicates = [HasAVX2]
4178 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 ,
4179 Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4180 // 256-bit logical shifts.
4181 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4182 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4183 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4185 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4187 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4188 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4189 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4191 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4193 // PSRADQYri doesn't exist in SSE[1-3].
4194 } // Predicates = [HasAVX2, NoVLX_Or_NoBWI]
4196 let Constraints = "$src1 = $dst" in {
4197 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4198 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4199 SSE_INTSHIFT_ITINS_P>;
4200 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4201 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4202 SSE_INTSHIFT_ITINS_P>;
4203 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4204 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4205 SSE_INTSHIFT_ITINS_P>;
4207 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4208 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4209 SSE_INTSHIFT_ITINS_P>;
4210 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4211 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4212 SSE_INTSHIFT_ITINS_P>;
4213 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4214 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4215 SSE_INTSHIFT_ITINS_P>;
4217 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4218 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4219 SSE_INTSHIFT_ITINS_P>;
4220 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4221 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4222 SSE_INTSHIFT_ITINS_P>;
4224 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4225 // 128-bit logical shifts.
4226 def PSLLDQri : PDIi8<0x73, MRM7r,
4227 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4228 "pslldq\t{$src2, $dst|$dst, $src2}",
4230 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4231 IIC_SSE_INTSHDQ_P_RI>;
4232 def PSRLDQri : PDIi8<0x73, MRM3r,
4233 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4234 "psrldq\t{$src2, $dst|$dst, $src2}",
4236 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4237 IIC_SSE_INTSHDQ_P_RI>;
4238 // PSRADQri doesn't exist in SSE[1-3].
4240 } // Constraints = "$src1 = $dst"
4242 //===---------------------------------------------------------------------===//
4243 // SSE2 - Packed Integer Comparison Instructions
4244 //===---------------------------------------------------------------------===//
4246 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4247 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4248 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4249 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4250 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4251 SSE_INTALU_ITINS_P, 1, NoVLX>;
4252 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4253 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4254 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4255 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4256 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4257 SSE_INTALU_ITINS_P, 0, NoVLX>;
4259 //===---------------------------------------------------------------------===//
4260 // SSE2 - Packed Integer Shuffle Instructions
4261 //===---------------------------------------------------------------------===//
4263 let ExeDomain = SSEPackedInt in {
4264 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4266 let Predicates = [HasAVX] in {
4267 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4268 (ins VR128:$src1, u8imm:$src2),
4269 !strconcat("v", OpcodeStr,
4270 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4272 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4273 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4274 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4275 (ins i128mem:$src1, u8imm:$src2),
4276 !strconcat("v", OpcodeStr,
4277 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4279 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4280 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4281 Sched<[WriteShuffleLd]>;
4284 let Predicates = [HasAVX2] in {
4285 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4286 (ins VR256:$src1, u8imm:$src2),
4287 !strconcat("v", OpcodeStr,
4288 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4290 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4291 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4292 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4293 (ins i256mem:$src1, u8imm:$src2),
4294 !strconcat("v", OpcodeStr,
4295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4297 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4298 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4299 Sched<[WriteShuffleLd]>;
4302 let Predicates = [UseSSE2] in {
4303 def ri : Ii8<0x70, MRMSrcReg,
4304 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4305 !strconcat(OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4309 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4310 def mi : Ii8<0x70, MRMSrcMem,
4311 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4316 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4317 Sched<[WriteShuffleLd, ReadAfterLd]>;
4320 } // ExeDomain = SSEPackedInt
4322 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4323 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4324 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4326 let Predicates = [HasAVX] in {
4327 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4328 (VPSHUFDmi addr:$src1, imm:$imm)>;
4329 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4330 (VPSHUFDri VR128:$src1, imm:$imm)>;
4333 let Predicates = [UseSSE2] in {
4334 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4335 (PSHUFDmi addr:$src1, imm:$imm)>;
4336 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4337 (PSHUFDri VR128:$src1, imm:$imm)>;
4340 //===---------------------------------------------------------------------===//
4341 // Packed Integer Pack Instructions (SSE & AVX)
4342 //===---------------------------------------------------------------------===//
4344 let ExeDomain = SSEPackedInt in {
4345 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4346 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4347 PatFrag ld_frag, bit Is2Addr = 1> {
4348 def rr : PDI<opc, MRMSrcReg,
4349 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4352 !strconcat(OpcodeStr,
4353 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4355 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4356 Sched<[WriteShuffle]>;
4357 def rm : PDI<opc, MRMSrcMem,
4358 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4360 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4361 !strconcat(OpcodeStr,
4362 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4364 (OutVT (OpNode VR128:$src1,
4365 (bc_frag (ld_frag addr:$src2)))))]>,
4366 Sched<[WriteShuffleLd, ReadAfterLd]>;
4369 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4370 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4371 def Yrr : PDI<opc, MRMSrcReg,
4372 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4373 !strconcat(OpcodeStr,
4374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4376 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4377 Sched<[WriteShuffle]>;
4378 def Yrm : PDI<opc, MRMSrcMem,
4379 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4380 !strconcat(OpcodeStr,
4381 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4383 (OutVT (OpNode VR256:$src1,
4384 (bc_frag (loadv4i64 addr:$src2)))))]>,
4385 Sched<[WriteShuffleLd, ReadAfterLd]>;
4388 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4389 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4390 PatFrag ld_frag, bit Is2Addr = 1> {
4391 def rr : SS48I<opc, MRMSrcReg,
4392 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4395 !strconcat(OpcodeStr,
4396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4398 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4399 Sched<[WriteShuffle]>;
4400 def rm : SS48I<opc, MRMSrcMem,
4401 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4403 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4404 !strconcat(OpcodeStr,
4405 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4407 (OutVT (OpNode VR128:$src1,
4408 (bc_frag (ld_frag addr:$src2)))))]>,
4409 Sched<[WriteShuffleLd, ReadAfterLd]>;
4412 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4413 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4414 def Yrr : SS48I<opc, MRMSrcReg,
4415 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4416 !strconcat(OpcodeStr,
4417 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4419 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4420 Sched<[WriteShuffle]>;
4421 def Yrm : SS48I<opc, MRMSrcMem,
4422 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4423 !strconcat(OpcodeStr,
4424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4426 (OutVT (OpNode VR256:$src1,
4427 (bc_frag (loadv4i64 addr:$src2)))))]>,
4428 Sched<[WriteShuffleLd, ReadAfterLd]>;
4431 let Predicates = [HasAVX] in {
4432 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4433 bc_v8i16, loadv2i64, 0>, VEX_4V;
4434 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4435 bc_v4i32, loadv2i64, 0>, VEX_4V;
4437 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4438 bc_v8i16, loadv2i64, 0>, VEX_4V;
4439 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4440 bc_v4i32, loadv2i64, 0>, VEX_4V;
4443 let Predicates = [HasAVX2] in {
4444 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4445 bc_v16i16>, VEX_4V, VEX_L;
4446 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4447 bc_v8i32>, VEX_4V, VEX_L;
4449 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4450 bc_v16i16>, VEX_4V, VEX_L;
4451 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4452 bc_v8i32>, VEX_4V, VEX_L;
4455 let Constraints = "$src1 = $dst" in {
4456 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4457 bc_v8i16, memopv2i64>;
4458 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4459 bc_v4i32, memopv2i64>;
4461 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4462 bc_v8i16, memopv2i64>;
4464 let Predicates = [HasSSE41] in
4465 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4466 bc_v4i32, memopv2i64>;
4468 } // ExeDomain = SSEPackedInt
4470 //===---------------------------------------------------------------------===//
4471 // SSE2 - Packed Integer Unpack Instructions
4472 //===---------------------------------------------------------------------===//
4474 let ExeDomain = SSEPackedInt in {
4475 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4476 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4478 def rr : PDI<opc, MRMSrcReg,
4479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4481 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4482 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4483 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4484 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4485 def rm : PDI<opc, MRMSrcMem,
4486 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4488 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4489 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4490 [(set VR128:$dst, (OpNode VR128:$src1,
4491 (bc_frag (ld_frag addr:$src2))))],
4493 Sched<[WriteShuffleLd, ReadAfterLd]>;
4496 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4497 SDNode OpNode, PatFrag bc_frag> {
4498 def Yrr : PDI<opc, MRMSrcReg,
4499 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4500 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4501 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4502 Sched<[WriteShuffle]>;
4503 def Yrm : PDI<opc, MRMSrcMem,
4504 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4505 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4506 [(set VR256:$dst, (OpNode VR256:$src1,
4507 (bc_frag (loadv4i64 addr:$src2))))]>,
4508 Sched<[WriteShuffleLd, ReadAfterLd]>;
4512 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4513 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4514 bc_v16i8, loadv2i64, 0>, VEX_4V;
4515 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4516 bc_v8i16, loadv2i64, 0>, VEX_4V;
4517 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4518 bc_v16i8, loadv2i64, 0>, VEX_4V;
4519 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4520 bc_v8i16, loadv2i64, 0>, VEX_4V;
4522 let Predicates = [HasAVX, NoVLX] in {
4523 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4524 bc_v4i32, loadv2i64, 0>, VEX_4V;
4525 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4526 bc_v2i64, loadv2i64, 0>, VEX_4V;
4527 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4528 bc_v4i32, loadv2i64, 0>, VEX_4V;
4529 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4530 bc_v2i64, loadv2i64, 0>, VEX_4V;
4533 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4534 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4535 bc_v32i8>, VEX_4V, VEX_L;
4536 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4537 bc_v16i16>, VEX_4V, VEX_L;
4538 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4539 bc_v32i8>, VEX_4V, VEX_L;
4540 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4541 bc_v16i16>, VEX_4V, VEX_L;
4543 let Predicates = [HasAVX2, NoVLX] in {
4544 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4545 bc_v8i32>, VEX_4V, VEX_L;
4546 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4547 bc_v4i64>, VEX_4V, VEX_L;
4548 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4549 bc_v8i32>, VEX_4V, VEX_L;
4550 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4551 bc_v4i64>, VEX_4V, VEX_L;
4554 let Constraints = "$src1 = $dst" in {
4555 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4556 bc_v16i8, memopv2i64>;
4557 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4558 bc_v8i16, memopv2i64>;
4559 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4560 bc_v4i32, memopv2i64>;
4561 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4562 bc_v2i64, memopv2i64>;
4564 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4565 bc_v16i8, memopv2i64>;
4566 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4567 bc_v8i16, memopv2i64>;
4568 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4569 bc_v4i32, memopv2i64>;
4570 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4571 bc_v2i64, memopv2i64>;
4573 } // ExeDomain = SSEPackedInt
4575 //===---------------------------------------------------------------------===//
4576 // SSE2 - Packed Integer Extract and Insert
4577 //===---------------------------------------------------------------------===//
4579 let ExeDomain = SSEPackedInt in {
4580 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4581 def rri : Ii8<0xC4, MRMSrcReg,
4582 (outs VR128:$dst), (ins VR128:$src1,
4583 GR32orGR64:$src2, u8imm:$src3),
4585 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4586 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4588 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4589 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4590 def rmi : Ii8<0xC4, MRMSrcMem,
4591 (outs VR128:$dst), (ins VR128:$src1,
4592 i16mem:$src2, u8imm:$src3),
4594 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4595 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4597 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4598 imm:$src3))], IIC_SSE_PINSRW>,
4599 Sched<[WriteShuffleLd, ReadAfterLd]>;
4603 let Predicates = [HasAVX, NoBWI] in
4604 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4605 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4606 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4607 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4608 imm:$src2))]>, PD, VEX,
4609 Sched<[WriteShuffle]>;
4610 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4611 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4612 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4613 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4614 imm:$src2))], IIC_SSE_PEXTRW>,
4615 Sched<[WriteShuffleLd, ReadAfterLd]>;
4618 let Predicates = [HasAVX, NoBWI] in
4619 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4621 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4622 defm PINSRW : sse2_pinsrw, PD;
4624 } // ExeDomain = SSEPackedInt
4626 //===---------------------------------------------------------------------===//
4627 // SSE2 - Packed Mask Creation
4628 //===---------------------------------------------------------------------===//
4630 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4632 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4634 "pmovmskb\t{$src, $dst|$dst, $src}",
4635 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4636 IIC_SSE_MOVMSK>, VEX;
4638 let Predicates = [HasAVX2] in {
4639 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4641 "pmovmskb\t{$src, $dst|$dst, $src}",
4642 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4646 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4647 "pmovmskb\t{$src, $dst|$dst, $src}",
4648 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4651 } // ExeDomain = SSEPackedInt
4653 //===---------------------------------------------------------------------===//
4654 // SSE2 - Conditional Store
4655 //===---------------------------------------------------------------------===//
4657 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4659 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4660 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4661 (ins VR128:$src, VR128:$mask),
4662 "maskmovdqu\t{$mask, $src|$src, $mask}",
4663 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4664 IIC_SSE_MASKMOV>, VEX;
4665 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4666 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4667 (ins VR128:$src, VR128:$mask),
4668 "maskmovdqu\t{$mask, $src|$src, $mask}",
4669 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4670 IIC_SSE_MASKMOV>, VEX;
4672 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4673 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4674 "maskmovdqu\t{$mask, $src|$src, $mask}",
4675 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4677 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4678 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4679 "maskmovdqu\t{$mask, $src|$src, $mask}",
4680 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4683 } // ExeDomain = SSEPackedInt
4685 //===---------------------------------------------------------------------===//
4686 // SSE2 - Move Doubleword/Quadword
4687 //===---------------------------------------------------------------------===//
4689 //===---------------------------------------------------------------------===//
4690 // Move Int Doubleword to Packed Double Int
4692 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4693 "movd\t{$src, $dst|$dst, $src}",
4695 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4696 VEX, Sched<[WriteMove]>;
4697 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4698 "movd\t{$src, $dst|$dst, $src}",
4700 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4702 VEX, Sched<[WriteLoad]>;
4703 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4704 "movq\t{$src, $dst|$dst, $src}",
4706 (v2i64 (scalar_to_vector GR64:$src)))],
4707 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4708 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4709 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4710 "movq\t{$src, $dst|$dst, $src}",
4711 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4712 let isCodeGenOnly = 1 in
4713 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4714 "movq\t{$src, $dst|$dst, $src}",
4715 [(set FR64:$dst, (bitconvert GR64:$src))],
4716 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4718 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4719 "movd\t{$src, $dst|$dst, $src}",
4721 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4723 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4724 "movd\t{$src, $dst|$dst, $src}",
4726 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4727 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4728 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4729 "mov{d|q}\t{$src, $dst|$dst, $src}",
4731 (v2i64 (scalar_to_vector GR64:$src)))],
4732 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4733 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4734 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4735 "mov{d|q}\t{$src, $dst|$dst, $src}",
4736 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4737 let isCodeGenOnly = 1 in
4738 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4739 "mov{d|q}\t{$src, $dst|$dst, $src}",
4740 [(set FR64:$dst, (bitconvert GR64:$src))],
4741 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4743 //===---------------------------------------------------------------------===//
4744 // Move Int Doubleword to Single Scalar
4746 let isCodeGenOnly = 1 in {
4747 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4748 "movd\t{$src, $dst|$dst, $src}",
4749 [(set FR32:$dst, (bitconvert GR32:$src))],
4750 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4752 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4753 "movd\t{$src, $dst|$dst, $src}",
4754 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4756 VEX, Sched<[WriteLoad]>;
4757 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4758 "movd\t{$src, $dst|$dst, $src}",
4759 [(set FR32:$dst, (bitconvert GR32:$src))],
4760 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4762 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4763 "movd\t{$src, $dst|$dst, $src}",
4764 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4765 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4768 //===---------------------------------------------------------------------===//
4769 // Move Packed Doubleword Int to Packed Double Int
4771 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4772 "movd\t{$src, $dst|$dst, $src}",
4773 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4774 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4776 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4777 (ins i32mem:$dst, VR128:$src),
4778 "movd\t{$src, $dst|$dst, $src}",
4779 [(store (i32 (vector_extract (v4i32 VR128:$src),
4780 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4781 VEX, Sched<[WriteStore]>;
4782 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4783 "movd\t{$src, $dst|$dst, $src}",
4784 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4785 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4787 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4788 "movd\t{$src, $dst|$dst, $src}",
4789 [(store (i32 (vector_extract (v4i32 VR128:$src),
4790 (iPTR 0))), addr:$dst)],
4791 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4793 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4794 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4796 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4797 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4799 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4800 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4802 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4803 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4805 //===---------------------------------------------------------------------===//
4806 // Move Packed Doubleword Int first element to Doubleword Int
4808 let SchedRW = [WriteMove] in {
4809 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4810 "movq\t{$src, $dst|$dst, $src}",
4811 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4816 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4817 "mov{d|q}\t{$src, $dst|$dst, $src}",
4818 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4823 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4824 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4825 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4826 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4827 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4828 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4829 "mov{d|q}\t{$src, $dst|$dst, $src}",
4830 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4832 //===---------------------------------------------------------------------===//
4833 // Bitcast FR64 <-> GR64
4835 let isCodeGenOnly = 1 in {
4836 let Predicates = [UseAVX] in
4837 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4838 "movq\t{$src, $dst|$dst, $src}",
4839 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4840 VEX, Sched<[WriteLoad]>;
4841 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4842 "movq\t{$src, $dst|$dst, $src}",
4843 [(set GR64:$dst, (bitconvert FR64:$src))],
4844 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4845 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4846 "movq\t{$src, $dst|$dst, $src}",
4847 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4848 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4850 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4851 "movq\t{$src, $dst|$dst, $src}",
4852 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4853 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4854 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4855 "mov{d|q}\t{$src, $dst|$dst, $src}",
4856 [(set GR64:$dst, (bitconvert FR64:$src))],
4857 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4858 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4859 "movq\t{$src, $dst|$dst, $src}",
4860 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4861 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4864 //===---------------------------------------------------------------------===//
4865 // Move Scalar Single to Double Int
4867 let isCodeGenOnly = 1 in {
4868 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4869 "movd\t{$src, $dst|$dst, $src}",
4870 [(set GR32:$dst, (bitconvert FR32:$src))],
4871 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4872 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4873 "movd\t{$src, $dst|$dst, $src}",
4874 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4875 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4876 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4877 "movd\t{$src, $dst|$dst, $src}",
4878 [(set GR32:$dst, (bitconvert FR32:$src))],
4879 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4880 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4881 "movd\t{$src, $dst|$dst, $src}",
4882 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4883 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4886 let Predicates = [UseAVX] in {
4887 let AddedComplexity = 15 in {
4888 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4889 (VMOVDI2PDIrr GR32:$src)>;
4891 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
4892 (VMOV64toPQIrr GR64:$src)>;
4894 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4895 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4896 (SUBREG_TO_REG (i64 0), (VMOV64toPQIrr GR64:$src), sub_xmm)>;
4898 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4899 // These instructions also write zeros in the high part of a 256-bit register.
4900 let AddedComplexity = 20 in {
4901 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4902 (VMOVDI2PDIrm addr:$src)>;
4903 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4904 (VMOVDI2PDIrm addr:$src)>;
4905 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4906 (VMOVDI2PDIrm addr:$src)>;
4907 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4908 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4909 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4911 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4912 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4913 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4914 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4917 let Predicates = [UseSSE2] in {
4918 let AddedComplexity = 15 in {
4919 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4920 (MOVDI2PDIrr GR32:$src)>;
4922 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
4923 (MOV64toPQIrr GR64:$src)>;
4925 let AddedComplexity = 20 in {
4926 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4927 (MOVDI2PDIrm addr:$src)>;
4928 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4929 (MOVDI2PDIrm addr:$src)>;
4930 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4931 (MOVDI2PDIrm addr:$src)>;
4935 // These are the correct encodings of the instructions so that we know how to
4936 // read correct assembly, even though we continue to emit the wrong ones for
4937 // compatibility with Darwin's buggy assembler.
4938 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4939 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4940 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4941 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4942 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4943 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4944 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4945 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4946 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4948 //===---------------------------------------------------------------------===//
4949 // SSE2 - Move Quadword
4950 //===---------------------------------------------------------------------===//
4952 //===---------------------------------------------------------------------===//
4953 // Move Quadword Int to Packed Quadword Int
4956 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4957 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4958 "vmovq\t{$src, $dst|$dst, $src}",
4960 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4961 VEX, Requires<[UseAVX]>;
4962 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4963 "movq\t{$src, $dst|$dst, $src}",
4965 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4967 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4968 } // ExeDomain, SchedRW
4970 //===---------------------------------------------------------------------===//
4971 // Move Packed Quadword Int to Quadword Int
4973 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4974 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4975 "movq\t{$src, $dst|$dst, $src}",
4976 [(store (i64 (vector_extract (v2i64 VR128:$src),
4977 (iPTR 0))), addr:$dst)],
4978 IIC_SSE_MOVDQ>, VEX;
4979 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4980 "movq\t{$src, $dst|$dst, $src}",
4981 [(store (i64 (vector_extract (v2i64 VR128:$src),
4982 (iPTR 0))), addr:$dst)],
4984 } // ExeDomain, SchedRW
4986 // For disassembler only
4987 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4988 SchedRW = [WriteVecLogic] in {
4989 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4990 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4991 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4992 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4995 //===---------------------------------------------------------------------===//
4996 // Store / copy lower 64-bits of a XMM register.
4998 let Predicates = [HasAVX] in
4999 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5000 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5001 let Predicates = [UseSSE2] in
5002 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5003 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5005 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5006 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5007 "vmovq\t{$src, $dst|$dst, $src}",
5009 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5010 (loadi64 addr:$src))))))],
5012 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5014 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5015 "movq\t{$src, $dst|$dst, $src}",
5017 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5018 (loadi64 addr:$src))))))],
5020 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5021 } // ExeDomain, isCodeGenOnly, AddedComplexity
5023 let Predicates = [UseAVX], AddedComplexity = 20 in {
5024 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5025 (VMOVZQI2PQIrm addr:$src)>;
5026 def : Pat<(v2i64 (X86vzload addr:$src)),
5027 (VMOVZQI2PQIrm addr:$src)>;
5028 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5029 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5030 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5033 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5034 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5035 (MOVZQI2PQIrm addr:$src)>;
5036 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5039 let Predicates = [HasAVX] in {
5040 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5041 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5042 def : Pat<(v4i64 (X86vzload addr:$src)),
5043 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5046 //===---------------------------------------------------------------------===//
5047 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5048 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5050 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5051 let AddedComplexity = 15 in
5052 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5053 "vmovq\t{$src, $dst|$dst, $src}",
5054 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5056 XS, VEX, Requires<[UseAVX]>;
5057 let AddedComplexity = 15 in
5058 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5059 "movq\t{$src, $dst|$dst, $src}",
5060 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5062 XS, Requires<[UseSSE2]>;
5063 } // ExeDomain, SchedRW
5065 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5066 let AddedComplexity = 20 in
5067 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5068 "vmovq\t{$src, $dst|$dst, $src}",
5069 [(set VR128:$dst, (v2i64 (X86vzmovl
5070 (loadv2i64 addr:$src))))],
5072 XS, VEX, Requires<[UseAVX]>;
5073 let AddedComplexity = 20 in {
5074 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5075 "movq\t{$src, $dst|$dst, $src}",
5076 [(set VR128:$dst, (v2i64 (X86vzmovl
5077 (loadv2i64 addr:$src))))],
5079 XS, Requires<[UseSSE2]>;
5081 } // ExeDomain, isCodeGenOnly, SchedRW
5083 let AddedComplexity = 20 in {
5084 let Predicates = [UseAVX] in {
5085 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5086 (VMOVZPQILo2PQIrr VR128:$src)>;
5088 let Predicates = [UseSSE2] in {
5089 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5090 (MOVZPQILo2PQIrr VR128:$src)>;
5094 //===---------------------------------------------------------------------===//
5095 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5096 //===---------------------------------------------------------------------===//
5097 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5098 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5099 X86MemOperand x86memop> {
5100 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5102 [(set RC:$dst, (vt (OpNode RC:$src)))],
5103 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5104 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5106 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5107 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5110 let Predicates = [HasAVX, NoVLX] in {
5111 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5112 v4f32, VR128, loadv4f32, f128mem>, VEX;
5113 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5114 v4f32, VR128, loadv4f32, f128mem>, VEX;
5115 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5116 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5117 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5118 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5120 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5121 memopv4f32, f128mem>;
5122 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5123 memopv4f32, f128mem>;
5125 let Predicates = [HasAVX, NoVLX] in {
5126 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5127 (VMOVSHDUPrr VR128:$src)>;
5128 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5129 (VMOVSHDUPrm addr:$src)>;
5130 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5131 (VMOVSLDUPrr VR128:$src)>;
5132 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5133 (VMOVSLDUPrm addr:$src)>;
5134 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5135 (VMOVSHDUPYrr VR256:$src)>;
5136 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5137 (VMOVSHDUPYrm addr:$src)>;
5138 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5139 (VMOVSLDUPYrr VR256:$src)>;
5140 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5141 (VMOVSLDUPYrm addr:$src)>;
5144 let Predicates = [UseSSE3] in {
5145 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5146 (MOVSHDUPrr VR128:$src)>;
5147 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5148 (MOVSHDUPrm addr:$src)>;
5149 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5150 (MOVSLDUPrr VR128:$src)>;
5151 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5152 (MOVSLDUPrm addr:$src)>;
5155 //===---------------------------------------------------------------------===//
5156 // SSE3 - Replicate Double FP - MOVDDUP
5157 //===---------------------------------------------------------------------===//
5159 multiclass sse3_replicate_dfp<string OpcodeStr> {
5160 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5161 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5162 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5163 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5164 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5168 (scalar_to_vector (loadf64 addr:$src)))))],
5169 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5172 // FIXME: Merge with above classe when there're patterns for the ymm version
5173 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5174 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5175 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5176 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5177 Sched<[WriteFShuffle]>;
5178 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5179 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5181 (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>,
5185 let Predicates = [HasAVX, NoVLX] in {
5186 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5187 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5190 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5193 let Predicates = [HasAVX, NoVLX] in {
5194 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5195 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5198 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5199 (VMOVDDUPYrm addr:$src)>;
5200 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5201 (VMOVDDUPYrr VR256:$src)>;
5204 let Predicates = [HasAVX] in {
5205 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5206 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5207 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5208 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5209 def : Pat<(X86Movddup (bc_v2f64
5210 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5211 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5214 let Predicates = [UseAVX, OptForSize] in {
5215 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5216 (VMOVDDUPrm addr:$src)>;
5217 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5218 (VMOVDDUPrm addr:$src)>;
5221 let Predicates = [UseSSE3] in {
5222 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5223 (MOVDDUPrm addr:$src)>;
5224 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5225 (MOVDDUPrm addr:$src)>;
5226 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5227 (MOVDDUPrm addr:$src)>;
5228 def : Pat<(X86Movddup (bc_v2f64
5229 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5230 (MOVDDUPrm addr:$src)>;
5233 //===---------------------------------------------------------------------===//
5234 // SSE3 - Move Unaligned Integer
5235 //===---------------------------------------------------------------------===//
5237 let SchedRW = [WriteLoad] in {
5238 let Predicates = [HasAVX] in {
5239 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5240 "vlddqu\t{$src, $dst|$dst, $src}",
5241 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5242 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5243 "vlddqu\t{$src, $dst|$dst, $src}",
5244 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5247 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5248 "lddqu\t{$src, $dst|$dst, $src}",
5249 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5253 //===---------------------------------------------------------------------===//
5254 // SSE3 - Arithmetic
5255 //===---------------------------------------------------------------------===//
5257 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5258 X86MemOperand x86memop, OpndItins itins,
5259 PatFrag ld_frag, bit Is2Addr = 1> {
5260 def rr : I<0xD0, MRMSrcReg,
5261 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5263 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5264 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5265 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5266 Sched<[itins.Sched]>;
5267 def rm : I<0xD0, MRMSrcMem,
5268 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5270 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5271 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5272 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5273 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5276 let Predicates = [HasAVX] in {
5277 let ExeDomain = SSEPackedSingle in {
5278 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5279 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5280 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5281 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5283 let ExeDomain = SSEPackedDouble in {
5284 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5285 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5286 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5287 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5290 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5291 let ExeDomain = SSEPackedSingle in
5292 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5293 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5294 let ExeDomain = SSEPackedDouble in
5295 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5296 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5299 // Patterns used to select 'addsub' instructions.
5300 let Predicates = [HasAVX] in {
5301 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5302 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5303 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5304 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5305 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5306 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5307 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5308 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5310 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5311 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5312 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5313 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5314 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5315 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5316 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5317 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5320 let Predicates = [UseSSE3] in {
5321 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5322 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5323 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5324 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5325 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5326 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5327 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5328 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5331 //===---------------------------------------------------------------------===//
5332 // SSE3 Instructions
5333 //===---------------------------------------------------------------------===//
5336 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5337 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5339 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5343 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5346 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5350 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5351 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5353 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5354 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5356 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5360 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5363 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5367 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5368 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5371 let Predicates = [HasAVX] in {
5372 let ExeDomain = SSEPackedSingle in {
5373 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5374 X86fhadd, loadv4f32, 0>, VEX_4V;
5375 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5376 X86fhsub, loadv4f32, 0>, VEX_4V;
5377 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5378 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5379 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5380 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5382 let ExeDomain = SSEPackedDouble in {
5383 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5384 X86fhadd, loadv2f64, 0>, VEX_4V;
5385 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5386 X86fhsub, loadv2f64, 0>, VEX_4V;
5387 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5388 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5389 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5390 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5394 let Constraints = "$src1 = $dst" in {
5395 let ExeDomain = SSEPackedSingle in {
5396 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5398 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5401 let ExeDomain = SSEPackedDouble in {
5402 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5404 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5409 //===---------------------------------------------------------------------===//
5410 // SSSE3 - Packed Absolute Instructions
5411 //===---------------------------------------------------------------------===//
5414 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5415 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5417 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5419 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5420 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5421 Sched<[WriteVecALU]>;
5423 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5428 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5429 Sched<[WriteVecALULd]>;
5432 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5433 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5434 Intrinsic IntId256> {
5435 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5438 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5439 Sched<[WriteVecALU]>;
5441 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5443 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5446 (bitconvert (loadv4i64 addr:$src))))]>,
5447 Sched<[WriteVecALULd]>;
5450 // Helper fragments to match sext vXi1 to vXiY.
5451 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5453 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5454 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5455 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5457 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5458 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5460 let Predicates = [HasAVX] in {
5461 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5463 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5465 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5469 (bc_v2i64 (v16i1sextv16i8)),
5470 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5471 (VPABSBrr128 VR128:$src)>;
5473 (bc_v2i64 (v8i1sextv8i16)),
5474 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5475 (VPABSWrr128 VR128:$src)>;
5477 (bc_v2i64 (v4i1sextv4i32)),
5478 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5479 (VPABSDrr128 VR128:$src)>;
5482 let Predicates = [HasAVX2] in {
5483 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5484 int_x86_avx2_pabs_b>, VEX, VEX_L;
5485 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5486 int_x86_avx2_pabs_w>, VEX, VEX_L;
5487 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5488 int_x86_avx2_pabs_d>, VEX, VEX_L;
5491 (bc_v4i64 (v32i1sextv32i8)),
5492 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5493 (VPABSBrr256 VR256:$src)>;
5495 (bc_v4i64 (v16i1sextv16i16)),
5496 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5497 (VPABSWrr256 VR256:$src)>;
5499 (bc_v4i64 (v8i1sextv8i32)),
5500 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5501 (VPABSDrr256 VR256:$src)>;
5504 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5506 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5508 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5511 let Predicates = [HasSSSE3] in {
5513 (bc_v2i64 (v16i1sextv16i8)),
5514 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5515 (PABSBrr128 VR128:$src)>;
5517 (bc_v2i64 (v8i1sextv8i16)),
5518 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5519 (PABSWrr128 VR128:$src)>;
5521 (bc_v2i64 (v4i1sextv4i32)),
5522 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5523 (PABSDrr128 VR128:$src)>;
5526 //===---------------------------------------------------------------------===//
5527 // SSSE3 - Packed Binary Operator Instructions
5528 //===---------------------------------------------------------------------===//
5530 let Sched = WriteVecALU in {
5531 def SSE_PHADDSUBD : OpndItins<
5532 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5534 def SSE_PHADDSUBSW : OpndItins<
5535 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5537 def SSE_PHADDSUBW : OpndItins<
5538 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5541 let Sched = WriteShuffle in
5542 def SSE_PSHUFB : OpndItins<
5543 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5545 let Sched = WriteVecALU in
5546 def SSE_PSIGN : OpndItins<
5547 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5549 let Sched = WriteVecIMul in
5550 def SSE_PMULHRSW : OpndItins<
5551 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5554 /// SS3I_binop_rm - Simple SSSE3 bin op
5555 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5556 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5557 X86MemOperand x86memop, OpndItins itins,
5559 let isCommutable = 1 in
5560 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5561 (ins RC:$src1, RC:$src2),
5563 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5564 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5565 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5566 Sched<[itins.Sched]>;
5567 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5568 (ins RC:$src1, x86memop:$src2),
5570 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5571 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5573 (OpVT (OpNode RC:$src1,
5574 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5575 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5578 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5579 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5580 Intrinsic IntId128, OpndItins itins,
5581 PatFrag ld_frag, bit Is2Addr = 1> {
5582 let isCommutable = 1 in
5583 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5584 (ins VR128:$src1, VR128:$src2),
5586 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5587 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5588 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5589 Sched<[itins.Sched]>;
5590 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5591 (ins VR128:$src1, i128mem:$src2),
5593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5596 (IntId128 VR128:$src1,
5597 (bitconvert (ld_frag addr:$src2))))]>,
5598 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5601 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5603 X86FoldableSchedWrite Sched> {
5604 let isCommutable = 1 in
5605 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5606 (ins VR256:$src1, VR256:$src2),
5607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5608 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5610 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5611 (ins VR256:$src1, i256mem:$src2),
5612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5614 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5615 Sched<[Sched.Folded, ReadAfterLd]>;
5618 let ImmT = NoImm, Predicates = [HasAVX] in {
5619 let isCommutable = 0 in {
5620 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5622 SSE_PHADDSUBW, 0>, VEX_4V;
5623 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5625 SSE_PHADDSUBD, 0>, VEX_4V;
5626 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5628 SSE_PHADDSUBW, 0>, VEX_4V;
5629 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5631 SSE_PHADDSUBD, 0>, VEX_4V;
5632 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5634 SSE_PSIGN, 0>, VEX_4V;
5635 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5637 SSE_PSIGN, 0>, VEX_4V;
5638 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5640 SSE_PSIGN, 0>, VEX_4V;
5641 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5643 SSE_PSHUFB, 0>, VEX_4V;
5644 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5645 int_x86_ssse3_phadd_sw_128,
5646 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5647 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5648 int_x86_ssse3_phsub_sw_128,
5649 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5650 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5651 int_x86_ssse3_pmadd_ub_sw_128,
5652 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5654 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5655 int_x86_ssse3_pmul_hr_sw_128,
5656 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5659 let ImmT = NoImm, Predicates = [HasAVX2] in {
5660 let isCommutable = 0 in {
5661 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5663 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5664 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5666 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5667 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5669 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5670 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5672 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5673 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5675 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5676 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5678 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5679 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5681 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5682 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5684 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5685 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5686 int_x86_avx2_phadd_sw,
5687 WriteVecALU>, VEX_4V, VEX_L;
5688 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5689 int_x86_avx2_phsub_sw,
5690 WriteVecALU>, VEX_4V, VEX_L;
5691 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5692 int_x86_avx2_pmadd_ub_sw,
5693 WriteVecIMul>, VEX_4V, VEX_L;
5695 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5696 int_x86_avx2_pmul_hr_sw,
5697 WriteVecIMul>, VEX_4V, VEX_L;
5700 // None of these have i8 immediate fields.
5701 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5702 let isCommutable = 0 in {
5703 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5704 memopv2i64, i128mem, SSE_PHADDSUBW>;
5705 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5706 memopv2i64, i128mem, SSE_PHADDSUBD>;
5707 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5708 memopv2i64, i128mem, SSE_PHADDSUBW>;
5709 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5710 memopv2i64, i128mem, SSE_PHADDSUBD>;
5711 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5712 memopv2i64, i128mem, SSE_PSIGN>;
5713 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5714 memopv2i64, i128mem, SSE_PSIGN>;
5715 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5716 memopv2i64, i128mem, SSE_PSIGN>;
5717 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5718 memopv2i64, i128mem, SSE_PSHUFB>;
5719 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5720 int_x86_ssse3_phadd_sw_128,
5721 SSE_PHADDSUBSW, memopv2i64>;
5722 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5723 int_x86_ssse3_phsub_sw_128,
5724 SSE_PHADDSUBSW, memopv2i64>;
5725 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5726 int_x86_ssse3_pmadd_ub_sw_128,
5727 SSE_PMADD, memopv2i64>;
5729 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5730 int_x86_ssse3_pmul_hr_sw_128,
5731 SSE_PMULHRSW, memopv2i64>;
5734 //===---------------------------------------------------------------------===//
5735 // SSSE3 - Packed Align Instruction Patterns
5736 //===---------------------------------------------------------------------===//
5738 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5739 let hasSideEffects = 0 in {
5740 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5741 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5743 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5745 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5746 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5748 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5749 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5751 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5753 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5754 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5758 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5759 let hasSideEffects = 0 in {
5760 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5761 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5763 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5764 []>, Sched<[WriteShuffle]>;
5766 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5767 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5769 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5770 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5774 let Predicates = [HasAVX] in
5775 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5776 let Predicates = [HasAVX2] in
5777 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5778 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5779 defm PALIGN : ssse3_palignr<"palignr">;
5781 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
5782 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5783 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5784 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5785 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5786 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5787 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5788 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5789 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5792 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
5793 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5794 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5795 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5796 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5797 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5798 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5799 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5800 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5803 let Predicates = [UseSSSE3] in {
5804 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5805 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5806 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5807 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5808 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5809 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5810 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5811 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5814 //===---------------------------------------------------------------------===//
5815 // SSSE3 - Thread synchronization
5816 //===---------------------------------------------------------------------===//
5818 let SchedRW = [WriteSystem] in {
5819 let usesCustomInserter = 1 in {
5820 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5821 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5822 Requires<[HasSSE3]>;
5825 let Uses = [EAX, ECX, EDX] in
5826 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5827 TB, Requires<[HasSSE3]>;
5828 let Uses = [ECX, EAX] in
5829 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5830 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5831 TB, Requires<[HasSSE3]>;
5834 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5835 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5837 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5838 Requires<[Not64BitMode]>;
5839 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5840 Requires<[In64BitMode]>;
5842 //===----------------------------------------------------------------------===//
5843 // SSE4.1 - Packed Move with Sign/Zero Extend
5844 //===----------------------------------------------------------------------===//
5846 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5847 RegisterClass OutRC, RegisterClass InRC,
5849 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5850 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5852 Sched<[itins.Sched]>;
5854 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5855 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5857 itins.rm>, Sched<[itins.Sched.Folded]>;
5860 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5861 X86MemOperand MemOp, X86MemOperand MemYOp,
5862 OpndItins SSEItins, OpndItins AVXItins,
5863 OpndItins AVX2Itins> {
5864 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5865 let Predicates = [HasAVX, NoVLX] in
5866 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5867 VR128, VR128, AVXItins>, VEX;
5868 let Predicates = [HasAVX2, NoVLX] in
5869 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5870 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5873 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5874 X86MemOperand MemOp, X86MemOperand MemYOp> {
5875 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5877 SSE_INTALU_ITINS_SHUFF_P,
5878 DEFAULT_ITINS_SHUFFLESCHED,
5879 DEFAULT_ITINS_SHUFFLESCHED>;
5880 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5881 !strconcat("pmovzx", OpcodeStr),
5883 SSE_INTALU_ITINS_SHUFF_P,
5884 DEFAULT_ITINS_SHUFFLESCHED,
5885 DEFAULT_ITINS_SHUFFLESCHED>;
5888 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5889 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5890 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5892 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5893 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5895 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5898 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5899 // Register-Register patterns
5900 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5901 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5902 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5903 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5904 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5905 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5907 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5908 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5909 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5910 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5912 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5913 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5915 // On AVX2, we also support 256bit inputs.
5916 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5917 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5918 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5919 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5920 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5921 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5923 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5924 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5925 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5926 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5928 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5929 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5931 // Simple Register-Memory patterns
5932 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5933 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5934 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5935 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5936 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5937 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5939 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5940 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5941 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5942 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5944 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5945 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5947 // AVX2 Register-Memory patterns
5948 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5949 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5950 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5951 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5952 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5953 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5954 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5955 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5957 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5958 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5959 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5961 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5962 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5963 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5964 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5966 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5967 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5968 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5969 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5970 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5971 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5972 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5973 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5975 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5977 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5978 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5979 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5980 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5981 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5982 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5984 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5985 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5986 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5988 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5989 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5990 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5991 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5994 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5995 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5996 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5997 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5998 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5999 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6000 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6003 let Predicates = [HasAVX2, NoVLX] in {
6004 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6005 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6008 // SSE4.1/AVX patterns.
6009 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6010 SDNode ExtOp, PatFrag ExtLoad16> {
6011 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6012 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6013 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6014 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6015 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6016 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6018 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6019 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6020 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6021 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6023 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6024 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6026 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6027 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6028 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6029 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6030 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6031 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6033 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6034 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6035 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6036 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6038 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6039 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6041 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6042 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6043 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6044 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6045 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6046 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6047 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6048 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6049 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6050 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6052 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6053 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6054 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6056 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6057 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6058 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6059 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6061 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6062 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6063 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6064 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6065 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6066 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6067 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6068 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6070 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6071 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6072 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6073 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6074 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6075 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6076 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6077 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6078 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6079 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6081 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6082 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6083 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6084 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6085 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6086 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6087 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6088 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6090 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6091 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6092 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6093 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6094 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6095 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6096 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6097 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6098 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6099 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6102 let Predicates = [HasAVX, NoVLX] in {
6103 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6104 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6107 let Predicates = [UseSSE41] in {
6108 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6109 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6112 //===----------------------------------------------------------------------===//
6113 // SSE4.1 - Extract Instructions
6114 //===----------------------------------------------------------------------===//
6116 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6117 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6118 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6119 (ins VR128:$src1, u8imm:$src2),
6120 !strconcat(OpcodeStr,
6121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6122 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6124 Sched<[WriteShuffle]>;
6125 let hasSideEffects = 0, mayStore = 1,
6126 SchedRW = [WriteShuffleLd, WriteRMW] in
6127 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6128 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6129 !strconcat(OpcodeStr,
6130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6131 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6132 imm:$src2)))), addr:$dst)]>;
6135 let Predicates = [HasAVX, NoBWI] in
6136 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6138 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6141 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6142 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6143 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6144 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6145 (ins VR128:$src1, u8imm:$src2),
6146 !strconcat(OpcodeStr,
6147 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6148 []>, Sched<[WriteShuffle]>;
6150 let hasSideEffects = 0, mayStore = 1,
6151 SchedRW = [WriteShuffleLd, WriteRMW] in
6152 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6153 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6154 !strconcat(OpcodeStr,
6155 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6156 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6157 imm:$src2)))), addr:$dst)]>;
6160 let Predicates = [HasAVX, NoBWI] in
6161 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6163 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6166 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6167 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6168 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6169 (ins VR128:$src1, u8imm:$src2),
6170 !strconcat(OpcodeStr,
6171 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6173 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6174 Sched<[WriteShuffle]>;
6175 let SchedRW = [WriteShuffleLd, WriteRMW] in
6176 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6177 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6178 !strconcat(OpcodeStr,
6179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6180 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6184 let Predicates = [HasAVX, NoDQI] in
6185 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6187 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6189 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6190 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6191 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6192 (ins VR128:$src1, u8imm:$src2),
6193 !strconcat(OpcodeStr,
6194 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6196 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6197 Sched<[WriteShuffle]>, REX_W;
6198 let SchedRW = [WriteShuffleLd, WriteRMW] in
6199 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6200 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6201 !strconcat(OpcodeStr,
6202 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6203 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6204 addr:$dst)]>, REX_W;
6207 let Predicates = [HasAVX, NoDQI] in
6208 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6210 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6212 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6214 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6215 OpndItins itins = DEFAULT_ITINS> {
6216 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6217 (ins VR128:$src1, u8imm:$src2),
6218 !strconcat(OpcodeStr,
6219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6220 [(set GR32orGR64:$dst,
6221 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6222 itins.rr>, Sched<[WriteFBlend]>;
6223 let SchedRW = [WriteFBlendLd, WriteRMW] in
6224 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6225 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6226 !strconcat(OpcodeStr,
6227 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6228 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6229 addr:$dst)], itins.rm>;
6232 let ExeDomain = SSEPackedSingle in {
6233 let Predicates = [UseAVX] in
6234 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6235 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6238 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6239 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6242 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6244 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6247 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6248 Requires<[UseSSE41]>;
6250 //===----------------------------------------------------------------------===//
6251 // SSE4.1 - Insert Instructions
6252 //===----------------------------------------------------------------------===//
6254 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6255 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6256 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6258 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6260 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6262 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6263 Sched<[WriteShuffle]>;
6264 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6265 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6267 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6269 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6271 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6272 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6275 let Predicates = [HasAVX, NoBWI] in
6276 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6277 let Constraints = "$src1 = $dst" in
6278 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6280 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6281 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6282 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6284 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6286 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6288 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6289 Sched<[WriteShuffle]>;
6290 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6291 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6293 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6297 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6298 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6301 let Predicates = [HasAVX, NoDQI] in
6302 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6303 let Constraints = "$src1 = $dst" in
6304 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6306 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6307 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6308 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6310 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6312 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6314 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6315 Sched<[WriteShuffle]>;
6316 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6317 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6319 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6321 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6323 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6324 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6327 let Predicates = [HasAVX, NoDQI] in
6328 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6329 let Constraints = "$src1 = $dst" in
6330 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6332 // insertps has a few different modes, there's the first two here below which
6333 // are optimized inserts that won't zero arbitrary elements in the destination
6334 // vector. The next one matches the intrinsic and could zero arbitrary elements
6335 // in the target vector.
6336 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6337 OpndItins itins = DEFAULT_ITINS> {
6338 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6339 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6341 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6345 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6346 Sched<[WriteFShuffle]>;
6347 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6348 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6350 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6352 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6354 (X86insertps VR128:$src1,
6355 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6356 imm:$src3))], itins.rm>,
6357 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6360 let ExeDomain = SSEPackedSingle in {
6361 let Predicates = [UseAVX] in
6362 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6363 let Constraints = "$src1 = $dst" in
6364 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6367 let Predicates = [UseSSE41] in {
6368 // If we're inserting an element from a load or a null pshuf of a load,
6369 // fold the load into the insertps instruction.
6370 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6371 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6373 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6374 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6375 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6376 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6379 let Predicates = [UseAVX] in {
6380 // If we're inserting an element from a vbroadcast of a load, fold the
6381 // load into the X86insertps instruction.
6382 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6383 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6384 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6385 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6386 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6387 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6390 //===----------------------------------------------------------------------===//
6391 // SSE4.1 - Round Instructions
6392 //===----------------------------------------------------------------------===//
6394 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6395 X86MemOperand x86memop, RegisterClass RC,
6396 PatFrag mem_frag32, PatFrag mem_frag64,
6397 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6398 let ExeDomain = SSEPackedSingle in {
6399 // Intrinsic operation, reg.
6400 // Vector intrinsic operation, reg
6401 def PSr : SS4AIi8<opcps, MRMSrcReg,
6402 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6403 !strconcat(OpcodeStr,
6404 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6405 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6406 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6408 // Vector intrinsic operation, mem
6409 def PSm : SS4AIi8<opcps, MRMSrcMem,
6410 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6411 !strconcat(OpcodeStr,
6412 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6414 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6415 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6416 } // ExeDomain = SSEPackedSingle
6418 let ExeDomain = SSEPackedDouble in {
6419 // Vector intrinsic operation, reg
6420 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6421 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6422 !strconcat(OpcodeStr,
6423 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6424 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6425 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6427 // Vector intrinsic operation, mem
6428 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6429 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6430 !strconcat(OpcodeStr,
6431 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6433 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6434 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6435 } // ExeDomain = SSEPackedDouble
6438 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6441 Intrinsic F64Int, bit Is2Addr = 1> {
6442 let ExeDomain = GenericDomain in {
6444 let hasSideEffects = 0 in
6445 def SSr : SS4AIi8<opcss, MRMSrcReg,
6446 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6448 !strconcat(OpcodeStr,
6449 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6450 !strconcat(OpcodeStr,
6451 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6452 []>, Sched<[WriteFAdd]>;
6454 // Intrinsic operation, reg.
6455 let isCodeGenOnly = 1 in
6456 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6457 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6459 !strconcat(OpcodeStr,
6460 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6461 !strconcat(OpcodeStr,
6462 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6463 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6466 // Intrinsic operation, mem.
6467 def SSm : SS4AIi8<opcss, MRMSrcMem,
6468 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6470 !strconcat(OpcodeStr,
6471 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6472 !strconcat(OpcodeStr,
6473 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6475 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6476 Sched<[WriteFAddLd, ReadAfterLd]>;
6479 let hasSideEffects = 0 in
6480 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6481 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6483 !strconcat(OpcodeStr,
6484 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6485 !strconcat(OpcodeStr,
6486 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6487 []>, Sched<[WriteFAdd]>;
6489 // Intrinsic operation, reg.
6490 let isCodeGenOnly = 1 in
6491 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6492 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6494 !strconcat(OpcodeStr,
6495 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6496 !strconcat(OpcodeStr,
6497 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6498 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6501 // Intrinsic operation, mem.
6502 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6503 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6505 !strconcat(OpcodeStr,
6506 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6507 !strconcat(OpcodeStr,
6508 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6510 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6511 Sched<[WriteFAddLd, ReadAfterLd]>;
6512 } // ExeDomain = GenericDomain
6515 // FP round - roundss, roundps, roundsd, roundpd
6516 let Predicates = [HasAVX] in {
6518 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6519 loadv4f32, loadv2f64,
6520 int_x86_sse41_round_ps,
6521 int_x86_sse41_round_pd>, VEX;
6522 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6523 loadv8f32, loadv4f64,
6524 int_x86_avx_round_ps_256,
6525 int_x86_avx_round_pd_256>, VEX, VEX_L;
6526 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6527 int_x86_sse41_round_ss,
6528 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6531 let Predicates = [UseAVX] in {
6532 def : Pat<(ffloor FR32:$src),
6533 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6534 def : Pat<(f64 (ffloor FR64:$src)),
6535 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6536 def : Pat<(f32 (fnearbyint FR32:$src)),
6537 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6538 def : Pat<(f64 (fnearbyint FR64:$src)),
6539 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6540 def : Pat<(f32 (fceil FR32:$src)),
6541 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6542 def : Pat<(f64 (fceil FR64:$src)),
6543 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6544 def : Pat<(f32 (frint FR32:$src)),
6545 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6546 def : Pat<(f64 (frint FR64:$src)),
6547 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6548 def : Pat<(f32 (ftrunc FR32:$src)),
6549 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6550 def : Pat<(f64 (ftrunc FR64:$src)),
6551 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6554 let Predicates = [HasAVX] in {
6555 def : Pat<(v4f32 (ffloor VR128:$src)),
6556 (VROUNDPSr VR128:$src, (i32 0x9))>;
6557 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6558 (VROUNDPSr VR128:$src, (i32 0xC))>;
6559 def : Pat<(v4f32 (fceil VR128:$src)),
6560 (VROUNDPSr VR128:$src, (i32 0xA))>;
6561 def : Pat<(v4f32 (frint VR128:$src)),
6562 (VROUNDPSr VR128:$src, (i32 0x4))>;
6563 def : Pat<(v4f32 (ftrunc VR128:$src)),
6564 (VROUNDPSr VR128:$src, (i32 0xB))>;
6566 def : Pat<(v2f64 (ffloor VR128:$src)),
6567 (VROUNDPDr VR128:$src, (i32 0x9))>;
6568 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6569 (VROUNDPDr VR128:$src, (i32 0xC))>;
6570 def : Pat<(v2f64 (fceil VR128:$src)),
6571 (VROUNDPDr VR128:$src, (i32 0xA))>;
6572 def : Pat<(v2f64 (frint VR128:$src)),
6573 (VROUNDPDr VR128:$src, (i32 0x4))>;
6574 def : Pat<(v2f64 (ftrunc VR128:$src)),
6575 (VROUNDPDr VR128:$src, (i32 0xB))>;
6577 def : Pat<(v8f32 (ffloor VR256:$src)),
6578 (VROUNDYPSr VR256:$src, (i32 0x9))>;
6579 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6580 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6581 def : Pat<(v8f32 (fceil VR256:$src)),
6582 (VROUNDYPSr VR256:$src, (i32 0xA))>;
6583 def : Pat<(v8f32 (frint VR256:$src)),
6584 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6585 def : Pat<(v8f32 (ftrunc VR256:$src)),
6586 (VROUNDYPSr VR256:$src, (i32 0xB))>;
6588 def : Pat<(v4f64 (ffloor VR256:$src)),
6589 (VROUNDYPDr VR256:$src, (i32 0x9))>;
6590 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6591 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6592 def : Pat<(v4f64 (fceil VR256:$src)),
6593 (VROUNDYPDr VR256:$src, (i32 0xA))>;
6594 def : Pat<(v4f64 (frint VR256:$src)),
6595 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6596 def : Pat<(v4f64 (ftrunc VR256:$src)),
6597 (VROUNDYPDr VR256:$src, (i32 0xB))>;
6600 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6601 memopv4f32, memopv2f64,
6602 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6603 let Constraints = "$src1 = $dst" in
6604 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6605 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6607 let Predicates = [UseSSE41] in {
6608 def : Pat<(ffloor FR32:$src),
6609 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6610 def : Pat<(f64 (ffloor FR64:$src)),
6611 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6612 def : Pat<(f32 (fnearbyint FR32:$src)),
6613 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6614 def : Pat<(f64 (fnearbyint FR64:$src)),
6615 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6616 def : Pat<(f32 (fceil FR32:$src)),
6617 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6618 def : Pat<(f64 (fceil FR64:$src)),
6619 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6620 def : Pat<(f32 (frint FR32:$src)),
6621 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6622 def : Pat<(f64 (frint FR64:$src)),
6623 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6624 def : Pat<(f32 (ftrunc FR32:$src)),
6625 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6626 def : Pat<(f64 (ftrunc FR64:$src)),
6627 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6629 def : Pat<(v4f32 (ffloor VR128:$src)),
6630 (ROUNDPSr VR128:$src, (i32 0x9))>;
6631 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6632 (ROUNDPSr VR128:$src, (i32 0xC))>;
6633 def : Pat<(v4f32 (fceil VR128:$src)),
6634 (ROUNDPSr VR128:$src, (i32 0xA))>;
6635 def : Pat<(v4f32 (frint VR128:$src)),
6636 (ROUNDPSr VR128:$src, (i32 0x4))>;
6637 def : Pat<(v4f32 (ftrunc VR128:$src)),
6638 (ROUNDPSr VR128:$src, (i32 0xB))>;
6640 def : Pat<(v2f64 (ffloor VR128:$src)),
6641 (ROUNDPDr VR128:$src, (i32 0x9))>;
6642 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6643 (ROUNDPDr VR128:$src, (i32 0xC))>;
6644 def : Pat<(v2f64 (fceil VR128:$src)),
6645 (ROUNDPDr VR128:$src, (i32 0xA))>;
6646 def : Pat<(v2f64 (frint VR128:$src)),
6647 (ROUNDPDr VR128:$src, (i32 0x4))>;
6648 def : Pat<(v2f64 (ftrunc VR128:$src)),
6649 (ROUNDPDr VR128:$src, (i32 0xB))>;
6652 //===----------------------------------------------------------------------===//
6653 // SSE4.1 - Packed Bit Test
6654 //===----------------------------------------------------------------------===//
6656 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6657 // the intel intrinsic that corresponds to this.
6658 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6659 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6660 "vptest\t{$src2, $src1|$src1, $src2}",
6661 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6662 Sched<[WriteVecLogic]>, VEX;
6663 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6664 "vptest\t{$src2, $src1|$src1, $src2}",
6665 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6666 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6668 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6669 "vptest\t{$src2, $src1|$src1, $src2}",
6670 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6671 Sched<[WriteVecLogic]>, VEX, VEX_L;
6672 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6673 "vptest\t{$src2, $src1|$src1, $src2}",
6674 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6675 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6678 let Defs = [EFLAGS] in {
6679 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6680 "ptest\t{$src2, $src1|$src1, $src2}",
6681 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6682 Sched<[WriteVecLogic]>;
6683 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6684 "ptest\t{$src2, $src1|$src1, $src2}",
6685 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6686 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6689 // The bit test instructions below are AVX only
6690 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6691 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6692 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6693 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6694 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6695 Sched<[WriteVecLogic]>, VEX;
6696 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6697 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6698 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6699 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6702 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6703 let ExeDomain = SSEPackedSingle in {
6704 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6705 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6708 let ExeDomain = SSEPackedDouble in {
6709 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6710 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6715 //===----------------------------------------------------------------------===//
6716 // SSE4.1 - Misc Instructions
6717 //===----------------------------------------------------------------------===//
6719 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6720 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6721 "popcnt{w}\t{$src, $dst|$dst, $src}",
6722 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6723 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6725 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6726 "popcnt{w}\t{$src, $dst|$dst, $src}",
6727 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6728 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6729 Sched<[WriteFAddLd]>, OpSize16, XS;
6731 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6732 "popcnt{l}\t{$src, $dst|$dst, $src}",
6733 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6734 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6737 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6738 "popcnt{l}\t{$src, $dst|$dst, $src}",
6739 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6740 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6741 Sched<[WriteFAddLd]>, OpSize32, XS;
6743 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6744 "popcnt{q}\t{$src, $dst|$dst, $src}",
6745 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6746 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6747 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6748 "popcnt{q}\t{$src, $dst|$dst, $src}",
6749 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6750 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6751 Sched<[WriteFAddLd]>, XS;
6756 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6757 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6758 Intrinsic IntId128, PatFrag ld_frag,
6759 X86FoldableSchedWrite Sched> {
6760 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6763 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6765 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6767 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6769 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6770 Sched<[Sched.Folded]>;
6773 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6774 // model, although the naming is misleading.
6775 let Predicates = [HasAVX] in
6776 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6777 int_x86_sse41_phminposuw, loadv2i64,
6779 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6780 int_x86_sse41_phminposuw, memopv2i64,
6783 /// SS48I_binop_rm - Simple SSE41 binary operator.
6784 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6785 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6786 X86MemOperand x86memop, bit Is2Addr = 1,
6787 OpndItins itins = SSE_INTALU_ITINS_P> {
6788 let isCommutable = 1 in
6789 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6790 (ins RC:$src1, RC:$src2),
6792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6794 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6795 Sched<[itins.Sched]>;
6796 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6797 (ins RC:$src1, x86memop:$src2),
6799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6800 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6802 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6803 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6806 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6808 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6809 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6810 PatFrag memop_frag, X86MemOperand x86memop,
6812 bit IsCommutable = 0, bit Is2Addr = 1> {
6813 let isCommutable = IsCommutable in
6814 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6815 (ins RC:$src1, RC:$src2),
6817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6819 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6820 Sched<[itins.Sched]>;
6821 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6822 (ins RC:$src1, x86memop:$src2),
6824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6826 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6827 (bitconvert (memop_frag addr:$src2)))))]>,
6828 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6831 let Predicates = [HasAVX, NoVLX] in {
6832 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6833 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6835 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6836 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6838 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6839 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6841 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6842 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6844 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6845 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6847 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6848 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6850 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6851 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6853 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6854 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6856 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6857 VR128, loadv2i64, i128mem,
6858 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6861 let Predicates = [HasAVX2, NoVLX] in {
6862 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6863 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6865 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6866 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6868 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6869 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6871 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6872 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6874 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6875 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6877 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6878 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6880 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6881 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6883 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6884 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6886 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6887 VR256, loadv4i64, i256mem,
6888 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6891 let Constraints = "$src1 = $dst" in {
6892 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6893 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6894 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6895 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6896 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6897 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6898 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6899 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6900 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6901 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6902 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6903 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6904 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6905 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6906 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6907 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6908 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6909 VR128, memopv2i64, i128mem,
6910 SSE_INTMUL_ITINS_P, 1>;
6913 let Predicates = [HasAVX, NoVLX] in {
6914 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6915 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6917 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6918 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6921 let Predicates = [HasAVX2] in {
6922 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6923 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6925 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6926 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6930 let Constraints = "$src1 = $dst" in {
6931 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6932 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6933 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6934 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6937 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6938 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6939 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6940 X86MemOperand x86memop, bit Is2Addr = 1,
6941 OpndItins itins = DEFAULT_ITINS> {
6942 let isCommutable = 1 in
6943 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6944 (ins RC:$src1, RC:$src2, u8imm:$src3),
6946 !strconcat(OpcodeStr,
6947 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6948 !strconcat(OpcodeStr,
6949 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6950 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6951 Sched<[itins.Sched]>;
6952 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6953 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6955 !strconcat(OpcodeStr,
6956 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6957 !strconcat(OpcodeStr,
6958 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6961 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6962 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6965 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6966 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6967 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6968 X86MemOperand x86memop, bit Is2Addr = 1,
6969 OpndItins itins = DEFAULT_ITINS> {
6970 let isCommutable = 1 in
6971 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6972 (ins RC:$src1, RC:$src2, u8imm:$src3),
6974 !strconcat(OpcodeStr,
6975 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6976 !strconcat(OpcodeStr,
6977 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6978 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6979 itins.rr>, Sched<[itins.Sched]>;
6980 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6981 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6983 !strconcat(OpcodeStr,
6984 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6985 !strconcat(OpcodeStr,
6986 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6988 (OpVT (OpNode RC:$src1,
6989 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6990 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6993 let Predicates = [HasAVX] in {
6994 let isCommutable = 0 in {
6995 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6996 VR128, loadv2i64, i128mem, 0,
6997 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7000 let ExeDomain = SSEPackedSingle in {
7001 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7002 VR128, loadv4f32, f128mem, 0,
7003 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7004 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7005 VR256, loadv8f32, f256mem, 0,
7006 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7008 let ExeDomain = SSEPackedDouble in {
7009 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7010 VR128, loadv2f64, f128mem, 0,
7011 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7012 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7013 VR256, loadv4f64, f256mem, 0,
7014 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7016 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7017 VR128, loadv2i64, i128mem, 0,
7018 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7020 let ExeDomain = SSEPackedSingle in
7021 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7022 VR128, loadv4f32, f128mem, 0,
7023 SSE_DPPS_ITINS>, VEX_4V;
7024 let ExeDomain = SSEPackedDouble in
7025 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7026 VR128, loadv2f64, f128mem, 0,
7027 SSE_DPPS_ITINS>, VEX_4V;
7028 let ExeDomain = SSEPackedSingle in
7029 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7030 VR256, loadv8f32, i256mem, 0,
7031 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7034 let Predicates = [HasAVX2] in {
7035 let isCommutable = 0 in {
7036 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7037 VR256, loadv4i64, i256mem, 0,
7038 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7040 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7041 VR256, loadv4i64, i256mem, 0,
7042 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7045 let Constraints = "$src1 = $dst" in {
7046 let isCommutable = 0 in {
7047 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7048 VR128, memopv2i64, i128mem,
7049 1, SSE_MPSADBW_ITINS>;
7051 let ExeDomain = SSEPackedSingle in
7052 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7053 VR128, memopv4f32, f128mem,
7054 1, SSE_INTALU_ITINS_FBLEND_P>;
7055 let ExeDomain = SSEPackedDouble in
7056 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7057 VR128, memopv2f64, f128mem,
7058 1, SSE_INTALU_ITINS_FBLEND_P>;
7059 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7060 VR128, memopv2i64, i128mem,
7061 1, SSE_INTALU_ITINS_BLEND_P>;
7062 let ExeDomain = SSEPackedSingle in
7063 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7064 VR128, memopv4f32, f128mem, 1,
7066 let ExeDomain = SSEPackedDouble in
7067 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7068 VR128, memopv2f64, f128mem, 1,
7072 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7073 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7074 RegisterClass RC, X86MemOperand x86memop,
7075 PatFrag mem_frag, Intrinsic IntId,
7076 X86FoldableSchedWrite Sched> {
7077 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7078 (ins RC:$src1, RC:$src2, RC:$src3),
7079 !strconcat(OpcodeStr,
7080 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7081 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7082 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7085 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7086 (ins RC:$src1, x86memop:$src2, RC:$src3),
7087 !strconcat(OpcodeStr,
7088 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7090 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7092 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7093 Sched<[Sched.Folded, ReadAfterLd]>;
7096 let Predicates = [HasAVX] in {
7097 let ExeDomain = SSEPackedDouble in {
7098 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7099 loadv2f64, int_x86_sse41_blendvpd,
7101 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7102 loadv4f64, int_x86_avx_blendv_pd_256,
7103 WriteFVarBlend>, VEX_L;
7104 } // ExeDomain = SSEPackedDouble
7105 let ExeDomain = SSEPackedSingle in {
7106 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7107 loadv4f32, int_x86_sse41_blendvps,
7109 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7110 loadv8f32, int_x86_avx_blendv_ps_256,
7111 WriteFVarBlend>, VEX_L;
7112 } // ExeDomain = SSEPackedSingle
7113 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7114 loadv2i64, int_x86_sse41_pblendvb,
7118 let Predicates = [HasAVX2] in {
7119 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7120 loadv4i64, int_x86_avx2_pblendvb,
7121 WriteVarBlend>, VEX_L;
7124 let Predicates = [HasAVX] in {
7125 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7126 (v16i8 VR128:$src2))),
7127 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7128 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7129 (v4i32 VR128:$src2))),
7130 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7131 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7132 (v4f32 VR128:$src2))),
7133 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7134 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7135 (v2i64 VR128:$src2))),
7136 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7137 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7138 (v2f64 VR128:$src2))),
7139 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7140 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7141 (v8i32 VR256:$src2))),
7142 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7143 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7144 (v8f32 VR256:$src2))),
7145 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7146 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7147 (v4i64 VR256:$src2))),
7148 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7149 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7150 (v4f64 VR256:$src2))),
7151 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7154 let Predicates = [HasAVX2] in {
7155 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7156 (v32i8 VR256:$src2))),
7157 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7161 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7162 // on targets where they have equal performance. These were changed to use
7163 // blends because blends have better throughput on SandyBridge and Haswell, but
7164 // movs[s/d] are 1-2 byte shorter instructions.
7165 let Predicates = [UseAVX] in {
7166 let AddedComplexity = 15 in {
7167 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7168 // MOVS{S,D} to the lower bits.
7169 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7170 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7171 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7172 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7173 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7174 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7175 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7176 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7178 // Move low f32 and clear high bits.
7179 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7180 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7182 // Move low f64 and clear high bits.
7183 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7184 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7187 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7188 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7189 (SUBREG_TO_REG (i32 0),
7190 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7192 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7193 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7194 (SUBREG_TO_REG (i64 0),
7195 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7198 // These will incur an FP/int domain crossing penalty, but it may be the only
7199 // way without AVX2. Do not add any complexity because we may be able to match
7200 // more optimal patterns defined earlier in this file.
7201 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7202 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7203 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7204 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7207 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7208 // on targets where they have equal performance. These were changed to use
7209 // blends because blends have better throughput on SandyBridge and Haswell, but
7210 // movs[s/d] are 1-2 byte shorter instructions.
7211 let Predicates = [UseSSE41] in {
7212 // With SSE41 we can use blends for these patterns.
7213 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7214 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7215 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7216 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7217 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7218 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7222 /// SS41I_ternary_int - SSE 4.1 ternary operator
7223 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7224 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7225 X86MemOperand x86memop, Intrinsic IntId,
7226 OpndItins itins = DEFAULT_ITINS> {
7227 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7228 (ins VR128:$src1, VR128:$src2),
7229 !strconcat(OpcodeStr,
7230 "\t{$src2, $dst|$dst, $src2}"),
7231 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7232 itins.rr>, Sched<[itins.Sched]>;
7234 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7235 (ins VR128:$src1, x86memop:$src2),
7236 !strconcat(OpcodeStr,
7237 "\t{$src2, $dst|$dst, $src2}"),
7240 (bitconvert (mem_frag addr:$src2)), XMM0))],
7241 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7245 let ExeDomain = SSEPackedDouble in
7246 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7247 int_x86_sse41_blendvpd,
7248 DEFAULT_ITINS_FBLENDSCHED>;
7249 let ExeDomain = SSEPackedSingle in
7250 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7251 int_x86_sse41_blendvps,
7252 DEFAULT_ITINS_FBLENDSCHED>;
7253 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7254 int_x86_sse41_pblendvb,
7255 DEFAULT_ITINS_VARBLENDSCHED>;
7257 // Aliases with the implicit xmm0 argument
7258 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7259 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7260 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7261 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7262 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7263 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7264 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7265 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7266 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7267 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7268 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7269 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7271 let Predicates = [UseSSE41] in {
7272 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7273 (v16i8 VR128:$src2))),
7274 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7275 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7276 (v4i32 VR128:$src2))),
7277 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7278 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7279 (v4f32 VR128:$src2))),
7280 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7281 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7282 (v2i64 VR128:$src2))),
7283 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7284 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7285 (v2f64 VR128:$src2))),
7286 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7289 let SchedRW = [WriteLoad] in {
7290 let Predicates = [HasAVX] in
7291 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7292 "vmovntdqa\t{$src, $dst|$dst, $src}",
7293 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7295 let Predicates = [HasAVX2] in
7296 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7297 "vmovntdqa\t{$src, $dst|$dst, $src}",
7298 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7300 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7301 "movntdqa\t{$src, $dst|$dst, $src}",
7302 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7305 //===----------------------------------------------------------------------===//
7306 // SSE4.2 - Compare Instructions
7307 //===----------------------------------------------------------------------===//
7309 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7310 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7311 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7312 X86MemOperand x86memop, bit Is2Addr = 1> {
7313 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7314 (ins RC:$src1, RC:$src2),
7316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7318 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7319 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7320 (ins RC:$src1, x86memop:$src2),
7322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7325 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7328 let Predicates = [HasAVX] in
7329 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7330 loadv2i64, i128mem, 0>, VEX_4V;
7332 let Predicates = [HasAVX2] in
7333 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7334 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7336 let Constraints = "$src1 = $dst" in
7337 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7338 memopv2i64, i128mem>;
7340 //===----------------------------------------------------------------------===//
7341 // SSE4.2 - String/text Processing Instructions
7342 //===----------------------------------------------------------------------===//
7344 // Packed Compare Implicit Length Strings, Return Mask
7345 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7346 def REG : PseudoI<(outs VR128:$dst),
7347 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7348 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7350 def MEM : PseudoI<(outs VR128:$dst),
7351 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7352 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7353 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7356 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7357 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7359 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7360 Requires<[UseSSE42]>;
7363 multiclass pcmpistrm_SS42AI<string asm> {
7364 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7365 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7366 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7367 []>, Sched<[WritePCmpIStrM]>;
7369 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7370 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7371 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7372 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7375 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7376 let Predicates = [HasAVX] in
7377 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7378 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7381 // Packed Compare Explicit Length Strings, Return Mask
7382 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7383 def REG : PseudoI<(outs VR128:$dst),
7384 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7385 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7386 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7387 def MEM : PseudoI<(outs VR128:$dst),
7388 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7389 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7390 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7393 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7394 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7396 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7397 Requires<[UseSSE42]>;
7400 multiclass SS42AI_pcmpestrm<string asm> {
7401 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7402 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7403 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7404 []>, Sched<[WritePCmpEStrM]>;
7406 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7407 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7408 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7409 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7412 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7413 let Predicates = [HasAVX] in
7414 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7415 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7418 // Packed Compare Implicit Length Strings, Return Index
7419 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7420 def REG : PseudoI<(outs GR32:$dst),
7421 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7422 [(set GR32:$dst, EFLAGS,
7423 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7424 def MEM : PseudoI<(outs GR32:$dst),
7425 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7426 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7427 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7430 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7431 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7433 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7434 Requires<[UseSSE42]>;
7437 multiclass SS42AI_pcmpistri<string asm> {
7438 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7439 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7440 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7441 []>, Sched<[WritePCmpIStrI]>;
7443 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7444 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7445 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7446 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7449 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7450 let Predicates = [HasAVX] in
7451 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7452 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7455 // Packed Compare Explicit Length Strings, Return Index
7456 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7457 def REG : PseudoI<(outs GR32:$dst),
7458 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7459 [(set GR32:$dst, EFLAGS,
7460 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7461 def MEM : PseudoI<(outs GR32:$dst),
7462 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7463 [(set GR32:$dst, EFLAGS,
7464 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7468 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7469 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7471 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7472 Requires<[UseSSE42]>;
7475 multiclass SS42AI_pcmpestri<string asm> {
7476 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7477 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7478 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7479 []>, Sched<[WritePCmpEStrI]>;
7481 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7482 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7483 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7484 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7487 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7488 let Predicates = [HasAVX] in
7489 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7490 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7493 //===----------------------------------------------------------------------===//
7494 // SSE4.2 - CRC Instructions
7495 //===----------------------------------------------------------------------===//
7497 // No CRC instructions have AVX equivalents
7499 // crc intrinsic instruction
7500 // This set of instructions are only rm, the only difference is the size
7502 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7503 RegisterClass RCIn, SDPatternOperator Int> :
7504 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7505 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7506 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7509 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7510 X86MemOperand x86memop, SDPatternOperator Int> :
7511 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7512 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7513 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7514 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7516 let Constraints = "$src1 = $dst" in {
7517 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7518 int_x86_sse42_crc32_32_8>;
7519 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7520 int_x86_sse42_crc32_32_8>;
7521 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7522 int_x86_sse42_crc32_32_16>, OpSize16;
7523 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7524 int_x86_sse42_crc32_32_16>, OpSize16;
7525 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7526 int_x86_sse42_crc32_32_32>, OpSize32;
7527 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7528 int_x86_sse42_crc32_32_32>, OpSize32;
7529 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7530 int_x86_sse42_crc32_64_64>, REX_W;
7531 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7532 int_x86_sse42_crc32_64_64>, REX_W;
7533 let hasSideEffects = 0 in {
7535 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7537 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7542 //===----------------------------------------------------------------------===//
7543 // SHA-NI Instructions
7544 //===----------------------------------------------------------------------===//
7546 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7548 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7549 (ins VR128:$src1, VR128:$src2),
7550 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7552 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7553 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7555 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7556 (ins VR128:$src1, i128mem:$src2),
7557 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7559 (set VR128:$dst, (IntId VR128:$src1,
7560 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7561 (set VR128:$dst, (IntId VR128:$src1,
7562 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7565 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7566 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7567 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7568 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7570 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7571 (i8 imm:$src3)))]>, TA;
7572 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7573 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7574 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7576 (int_x86_sha1rnds4 VR128:$src1,
7577 (bc_v4i32 (memopv2i64 addr:$src2)),
7578 (i8 imm:$src3)))]>, TA;
7580 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7581 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7582 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7585 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7587 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7588 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7591 // Aliases with explicit %xmm0
7592 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7593 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7594 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7595 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7597 //===----------------------------------------------------------------------===//
7598 // AES-NI Instructions
7599 //===----------------------------------------------------------------------===//
7601 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7602 PatFrag ld_frag, bit Is2Addr = 1> {
7603 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7604 (ins VR128:$src1, VR128:$src2),
7606 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7608 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7609 Sched<[WriteAESDecEnc]>;
7610 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7611 (ins VR128:$src1, i128mem:$src2),
7613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7616 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7617 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7620 // Perform One Round of an AES Encryption/Decryption Flow
7621 let Predicates = [HasAVX, HasAES] in {
7622 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7623 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7624 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7625 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7626 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7627 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7628 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7629 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7632 let Constraints = "$src1 = $dst" in {
7633 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7634 int_x86_aesni_aesenc, memopv2i64>;
7635 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7636 int_x86_aesni_aesenclast, memopv2i64>;
7637 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7638 int_x86_aesni_aesdec, memopv2i64>;
7639 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7640 int_x86_aesni_aesdeclast, memopv2i64>;
7643 // Perform the AES InvMixColumn Transformation
7644 let Predicates = [HasAVX, HasAES] in {
7645 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7647 "vaesimc\t{$src1, $dst|$dst, $src1}",
7649 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7651 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7652 (ins i128mem:$src1),
7653 "vaesimc\t{$src1, $dst|$dst, $src1}",
7654 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7655 Sched<[WriteAESIMCLd]>, VEX;
7657 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7659 "aesimc\t{$src1, $dst|$dst, $src1}",
7661 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7662 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7663 (ins i128mem:$src1),
7664 "aesimc\t{$src1, $dst|$dst, $src1}",
7665 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7666 Sched<[WriteAESIMCLd]>;
7668 // AES Round Key Generation Assist
7669 let Predicates = [HasAVX, HasAES] in {
7670 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7671 (ins VR128:$src1, u8imm:$src2),
7672 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7674 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7675 Sched<[WriteAESKeyGen]>, VEX;
7676 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7677 (ins i128mem:$src1, u8imm:$src2),
7678 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7680 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7681 Sched<[WriteAESKeyGenLd]>, VEX;
7683 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7684 (ins VR128:$src1, u8imm:$src2),
7685 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7687 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7688 Sched<[WriteAESKeyGen]>;
7689 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7690 (ins i128mem:$src1, u8imm:$src2),
7691 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7693 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7694 Sched<[WriteAESKeyGenLd]>;
7696 //===----------------------------------------------------------------------===//
7697 // PCLMUL Instructions
7698 //===----------------------------------------------------------------------===//
7700 // AVX carry-less Multiplication instructions
7701 let isCommutable = 1 in
7702 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7703 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7704 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7706 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7707 Sched<[WriteCLMul]>;
7709 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7710 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7711 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7712 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7713 (loadv2i64 addr:$src2), imm:$src3))]>,
7714 Sched<[WriteCLMulLd, ReadAfterLd]>;
7716 // Carry-less Multiplication instructions
7717 let Constraints = "$src1 = $dst" in {
7718 let isCommutable = 1 in
7719 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7720 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7721 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7723 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7724 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7726 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7727 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7728 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7729 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7730 (memopv2i64 addr:$src2), imm:$src3))],
7731 IIC_SSE_PCLMULQDQ_RM>,
7732 Sched<[WriteCLMulLd, ReadAfterLd]>;
7733 } // Constraints = "$src1 = $dst"
7736 multiclass pclmul_alias<string asm, int immop> {
7737 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7738 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7740 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7741 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7743 def : InstAlias<!strconcat("vpclmul", asm,
7744 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7745 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7748 def : InstAlias<!strconcat("vpclmul", asm,
7749 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7750 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7753 defm : pclmul_alias<"hqhq", 0x11>;
7754 defm : pclmul_alias<"hqlq", 0x01>;
7755 defm : pclmul_alias<"lqhq", 0x10>;
7756 defm : pclmul_alias<"lqlq", 0x00>;
7758 //===----------------------------------------------------------------------===//
7759 // SSE4A Instructions
7760 //===----------------------------------------------------------------------===//
7762 let Predicates = [HasSSE4A] in {
7764 let Constraints = "$src = $dst" in {
7765 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7766 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7767 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7768 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7770 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7771 (ins VR128:$src, VR128:$mask),
7772 "extrq\t{$mask, $src|$src, $mask}",
7773 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7774 VR128:$mask))]>, PD;
7776 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7777 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7778 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7779 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7780 imm:$len, imm:$idx))]>, XD;
7781 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7782 (ins VR128:$src, VR128:$mask),
7783 "insertq\t{$mask, $src|$src, $mask}",
7784 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7785 VR128:$mask))]>, XD;
7788 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7789 "movntss\t{$src, $dst|$dst, $src}",
7790 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7792 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7793 "movntsd\t{$src, $dst|$dst, $src}",
7794 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7797 //===----------------------------------------------------------------------===//
7799 //===----------------------------------------------------------------------===//
7801 //===----------------------------------------------------------------------===//
7802 // VBROADCAST - Load from memory and broadcast to all elements of the
7803 // destination operand
7805 class avx_broadcast_rm<bits<8> opc, string OpcodeStr, RegisterClass RC,
7806 X86MemOperand x86memop, ValueType VT,
7807 PatFrag ld_frag, SchedWrite Sched> :
7808 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7809 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7810 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7811 Sched<[Sched]>, VEX {
7815 // AVX2 adds register forms
7816 class avx2_broadcast_rr<bits<8> opc, string OpcodeStr, RegisterClass RC,
7817 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7818 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7819 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7820 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
7821 Sched<[Sched]>, VEX;
7823 let ExeDomain = SSEPackedSingle in {
7824 def VBROADCASTSSrm : avx_broadcast_rm<0x18, "vbroadcastss", VR128,
7825 f32mem, v4f32, loadf32, WriteLoad>;
7826 def VBROADCASTSSYrm : avx_broadcast_rm<0x18, "vbroadcastss", VR256,
7827 f32mem, v8f32, loadf32,
7828 WriteFShuffleLd>, VEX_L;
7830 let ExeDomain = SSEPackedDouble in
7831 def VBROADCASTSDYrm : avx_broadcast_rm<0x19, "vbroadcastsd", VR256, f64mem,
7832 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7834 let ExeDomain = SSEPackedSingle in {
7835 def VBROADCASTSSrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR128,
7836 v4f32, v4f32, WriteFShuffle>;
7837 def VBROADCASTSSYrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR256,
7838 v8f32, v4f32, WriteFShuffle256>, VEX_L;
7840 let ExeDomain = SSEPackedDouble in
7841 def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
7842 v4f64, v2f64, WriteFShuffle256>, VEX_L;
7844 let mayLoad = 1, Predicates = [HasAVX2] in
7845 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7847 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7848 Sched<[WriteLoad]>, VEX, VEX_L;
7850 def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
7852 "vbroadcastf128\t{$src, $dst|$dst, $src}",
7854 (int_x86_avx_vbroadcastf128_pd_256 addr:$src))]>,
7855 Sched<[WriteFShuffleLd]>, VEX, VEX_L;
7857 let Predicates = [HasAVX] in
7858 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7859 (VBROADCASTF128 addr:$src)>;
7862 //===----------------------------------------------------------------------===//
7863 // VINSERTF128 - Insert packed floating-point values
7865 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7866 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7867 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7868 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7869 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7871 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7872 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7873 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7874 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7877 let Predicates = [HasAVX, NoVLX] in {
7878 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7880 (VINSERTF128rr VR256:$src1, VR128:$src2,
7881 (INSERT_get_vinsert128_imm VR256:$ins))>;
7882 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7884 (VINSERTF128rr VR256:$src1, VR128:$src2,
7885 (INSERT_get_vinsert128_imm VR256:$ins))>;
7887 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7889 (VINSERTF128rm VR256:$src1, addr:$src2,
7890 (INSERT_get_vinsert128_imm VR256:$ins))>;
7891 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7893 (VINSERTF128rm VR256:$src1, addr:$src2,
7894 (INSERT_get_vinsert128_imm VR256:$ins))>;
7897 let Predicates = [HasAVX1Only] in {
7898 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7900 (VINSERTF128rr VR256:$src1, VR128:$src2,
7901 (INSERT_get_vinsert128_imm VR256:$ins))>;
7902 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7904 (VINSERTF128rr VR256:$src1, VR128:$src2,
7905 (INSERT_get_vinsert128_imm VR256:$ins))>;
7906 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7908 (VINSERTF128rr VR256:$src1, VR128:$src2,
7909 (INSERT_get_vinsert128_imm VR256:$ins))>;
7910 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7912 (VINSERTF128rr VR256:$src1, VR128:$src2,
7913 (INSERT_get_vinsert128_imm VR256:$ins))>;
7915 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7917 (VINSERTF128rm VR256:$src1, addr:$src2,
7918 (INSERT_get_vinsert128_imm VR256:$ins))>;
7919 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7920 (bc_v4i32 (loadv2i64 addr:$src2)),
7922 (VINSERTF128rm VR256:$src1, addr:$src2,
7923 (INSERT_get_vinsert128_imm VR256:$ins))>;
7924 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7925 (bc_v16i8 (loadv2i64 addr:$src2)),
7927 (VINSERTF128rm VR256:$src1, addr:$src2,
7928 (INSERT_get_vinsert128_imm VR256:$ins))>;
7929 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7930 (bc_v8i16 (loadv2i64 addr:$src2)),
7932 (VINSERTF128rm VR256:$src1, addr:$src2,
7933 (INSERT_get_vinsert128_imm VR256:$ins))>;
7936 //===----------------------------------------------------------------------===//
7937 // VEXTRACTF128 - Extract packed floating-point values
7939 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7940 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7941 (ins VR256:$src1, u8imm:$src2),
7942 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7943 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7945 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7946 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7947 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7948 []>, Sched<[WriteStore]>, VEX, VEX_L;
7952 let Predicates = [HasAVX] in {
7953 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7954 (v4f32 (VEXTRACTF128rr
7955 (v8f32 VR256:$src1),
7956 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7957 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7958 (v2f64 (VEXTRACTF128rr
7959 (v4f64 VR256:$src1),
7960 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7962 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7963 (iPTR imm))), addr:$dst),
7964 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7965 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7966 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7967 (iPTR imm))), addr:$dst),
7968 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7969 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7972 let Predicates = [HasAVX1Only] in {
7973 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7974 (v2i64 (VEXTRACTF128rr
7975 (v4i64 VR256:$src1),
7976 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7977 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7978 (v4i32 (VEXTRACTF128rr
7979 (v8i32 VR256:$src1),
7980 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7981 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7982 (v8i16 (VEXTRACTF128rr
7983 (v16i16 VR256:$src1),
7984 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7985 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7986 (v16i8 (VEXTRACTF128rr
7987 (v32i8 VR256:$src1),
7988 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7990 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7991 (iPTR imm))), addr:$dst),
7992 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7993 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7994 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7995 (iPTR imm))), addr:$dst),
7996 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7997 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7998 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7999 (iPTR imm))), addr:$dst),
8000 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8001 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8002 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8003 (iPTR imm))), addr:$dst),
8004 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8005 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8008 //===----------------------------------------------------------------------===//
8009 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8011 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8012 Intrinsic IntLd, Intrinsic IntLd256,
8013 Intrinsic IntSt, Intrinsic IntSt256> {
8014 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8015 (ins VR128:$src1, f128mem:$src2),
8016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8017 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8019 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8020 (ins VR256:$src1, f256mem:$src2),
8021 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8022 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8024 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8025 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8027 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8028 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8029 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8031 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8034 let ExeDomain = SSEPackedSingle in
8035 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8036 int_x86_avx_maskload_ps,
8037 int_x86_avx_maskload_ps_256,
8038 int_x86_avx_maskstore_ps,
8039 int_x86_avx_maskstore_ps_256>;
8040 let ExeDomain = SSEPackedDouble in
8041 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8042 int_x86_avx_maskload_pd,
8043 int_x86_avx_maskload_pd_256,
8044 int_x86_avx_maskstore_pd,
8045 int_x86_avx_maskstore_pd_256>;
8047 //===----------------------------------------------------------------------===//
8048 // VPERMIL - Permute Single and Double Floating-Point Values
8050 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8051 RegisterClass RC, X86MemOperand x86memop_f,
8052 X86MemOperand x86memop_i, PatFrag i_frag,
8053 Intrinsic IntVar, ValueType vt> {
8054 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8055 (ins RC:$src1, RC:$src2),
8056 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8057 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8058 Sched<[WriteFShuffle]>;
8059 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8060 (ins RC:$src1, x86memop_i:$src2),
8061 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8062 [(set RC:$dst, (IntVar RC:$src1,
8063 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8064 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8066 let Predicates = [HasAVX, NoVLX] in {
8067 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8068 (ins RC:$src1, u8imm:$src2),
8069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8070 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8071 Sched<[WriteFShuffle]>;
8072 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8073 (ins x86memop_f:$src1, u8imm:$src2),
8074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8076 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8077 Sched<[WriteFShuffleLd]>;
8078 }// Predicates = [HasAVX, NoVLX]
8081 let ExeDomain = SSEPackedSingle in {
8082 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8083 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8084 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8085 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8087 let ExeDomain = SSEPackedDouble in {
8088 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8089 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8090 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8091 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8094 let Predicates = [HasAVX, NoVLX] in {
8095 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8096 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8097 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8098 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8099 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8100 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8101 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8102 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8104 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8105 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8106 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8107 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8108 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8110 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8111 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8112 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8114 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8115 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8116 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8117 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8118 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8119 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8120 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8121 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8123 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8124 (VPERMILPDri VR128:$src1, imm:$imm)>;
8125 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8126 (VPERMILPDmi addr:$src1, imm:$imm)>;
8129 //===----------------------------------------------------------------------===//
8130 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8132 let ExeDomain = SSEPackedSingle in {
8133 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8134 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8135 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8136 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8137 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8138 Sched<[WriteFShuffle]>;
8139 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8140 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8141 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8142 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8143 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8144 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8147 let Predicates = [HasAVX] in {
8148 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8149 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8150 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8151 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8152 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8155 let Predicates = [HasAVX1Only] in {
8156 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8157 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8158 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8159 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8160 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8161 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8162 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8163 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8165 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8166 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8167 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8168 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8169 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8170 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8171 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8172 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8173 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8174 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8175 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8176 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8179 //===----------------------------------------------------------------------===//
8180 // VZERO - Zero YMM registers
8182 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8183 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8184 // Zero All YMM registers
8185 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8186 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8188 // Zero Upper bits of YMM registers
8189 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8190 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8193 //===----------------------------------------------------------------------===//
8194 // Half precision conversion instructions
8195 //===----------------------------------------------------------------------===//
8196 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8197 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8198 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8199 [(set RC:$dst, (Int VR128:$src))]>,
8200 T8PD, VEX, Sched<[WriteCvtF2F]>;
8201 let hasSideEffects = 0, mayLoad = 1 in
8202 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8203 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8204 Sched<[WriteCvtF2FLd]>;
8207 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8208 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8209 (ins RC:$src1, i32u8imm:$src2),
8210 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8211 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8212 TAPD, VEX, Sched<[WriteCvtF2F]>;
8213 let hasSideEffects = 0, mayStore = 1,
8214 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8215 def mr : Ii8<0x1D, MRMDestMem, (outs),
8216 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8217 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8221 let Predicates = [HasF16C] in {
8222 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8223 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8224 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8225 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8227 // Pattern match vcvtph2ps of a scalar i64 load.
8228 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8229 (VCVTPH2PSrm addr:$src)>;
8230 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8231 (VCVTPH2PSrm addr:$src)>;
8233 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8234 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8236 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8237 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8238 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8240 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8241 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8243 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8246 // Patterns for matching conversions from float to half-float and vice versa.
8247 let Predicates = [HasF16C] in {
8248 def : Pat<(fp_to_f16 FR32:$src),
8249 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8250 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8252 def : Pat<(f16_to_fp GR16:$src),
8253 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8254 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8256 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8257 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8258 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8261 //===----------------------------------------------------------------------===//
8262 // AVX2 Instructions
8263 //===----------------------------------------------------------------------===//
8265 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8266 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8267 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8268 X86MemOperand x86memop> {
8269 let isCommutable = 1 in
8270 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8271 (ins RC:$src1, RC:$src2, u8imm:$src3),
8272 !strconcat(OpcodeStr,
8273 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8274 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8275 Sched<[WriteBlend]>, VEX_4V;
8276 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8277 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8278 !strconcat(OpcodeStr,
8279 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8281 (OpVT (OpNode RC:$src1,
8282 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8283 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8286 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8287 VR128, loadv2i64, i128mem>;
8288 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8289 VR256, loadv4i64, i256mem>, VEX_L;
8291 //===----------------------------------------------------------------------===//
8292 // VPBROADCAST - Load from memory and broadcast to all elements of the
8293 // destination operand
8295 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8296 X86MemOperand x86memop, PatFrag ld_frag,
8297 ValueType OpVT128, ValueType OpVT256, Predicate prd> {
8298 let Predicates = [HasAVX2, prd] in {
8299 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8302 (OpVT128 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8303 Sched<[WriteShuffle]>, VEX;
8304 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8305 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8307 (OpVT128 (X86VBroadcast (ld_frag addr:$src))))]>,
8308 Sched<[WriteLoad]>, VEX;
8309 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8310 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8312 (OpVT256 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8313 Sched<[WriteShuffle256]>, VEX, VEX_L;
8314 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8317 (OpVT256 (X86VBroadcast (ld_frag addr:$src))))]>,
8318 Sched<[WriteLoad]>, VEX, VEX_L;
8320 // Provide aliases for broadcast from the same register class that
8321 // automatically does the extract.
8322 def : Pat<(OpVT256 (X86VBroadcast (OpVT256 VR256:$src))),
8323 (!cast<Instruction>(NAME#"Yrr")
8324 (OpVT128 (EXTRACT_SUBREG (OpVT256 VR256:$src),sub_xmm)))>;
8328 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8329 v16i8, v32i8, NoVLX_Or_NoBWI>;
8330 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8331 v8i16, v16i16, NoVLX_Or_NoBWI>;
8332 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8333 v4i32, v8i32, NoVLX>;
8334 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8335 v2i64, v4i64, NoVLX>;
8337 let Predicates = [HasAVX2] in {
8338 // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
8339 // This means we'll encounter truncated i32 loads; match that here.
8340 def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8341 (VPBROADCASTWrm addr:$src)>;
8342 def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8343 (VPBROADCASTWYrm addr:$src)>;
8344 def : Pat<(v8i16 (X86VBroadcast
8345 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
8346 (VPBROADCASTWrm addr:$src)>;
8347 def : Pat<(v16i16 (X86VBroadcast
8348 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
8349 (VPBROADCASTWYrm addr:$src)>;
8351 // Provide aliases for broadcast from the same register class that
8352 // automatically does the extract.
8353 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8354 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8356 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8357 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8360 // Provide fallback in case the load node that is used in the patterns above
8361 // is used by additional users, which prevents the pattern selection.
8362 let AddedComplexity = 20 in {
8363 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8364 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8365 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8366 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8367 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8368 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8370 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8371 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8372 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8373 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8374 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8375 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8377 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8378 (VPBROADCASTBrr (COPY_TO_REGCLASS
8379 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8381 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8382 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8383 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8386 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8387 (VPBROADCASTWrr (COPY_TO_REGCLASS
8388 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8390 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8391 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8392 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8395 // The patterns for VPBROADCASTD are not needed because they would match
8396 // the exact same thing as VBROADCASTSS patterns.
8398 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8399 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8400 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8404 // AVX1 broadcast patterns
8405 let Predicates = [HasAVX1Only] in {
8406 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8407 (VBROADCASTSSYrm addr:$src)>;
8408 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8409 (VBROADCASTSDYrm addr:$src)>;
8410 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8411 (VBROADCASTSSrm addr:$src)>;
8414 let Predicates = [HasAVX] in {
8415 // Provide fallback in case the load node that is used in the patterns above
8416 // is used by additional users, which prevents the pattern selection.
8417 let AddedComplexity = 20 in {
8418 // 128bit broadcasts:
8419 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8420 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8421 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8422 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8423 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8424 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8425 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8426 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8427 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8428 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8430 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8431 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8432 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8433 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8434 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8435 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8436 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8437 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8438 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8439 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8442 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8443 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8444 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8445 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8448 //===----------------------------------------------------------------------===//
8449 // VPERM - Permute instructions
8452 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8453 ValueType OpVT, X86FoldableSchedWrite Sched> {
8454 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8455 (ins VR256:$src1, VR256:$src2),
8456 !strconcat(OpcodeStr,
8457 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8459 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8460 Sched<[Sched]>, VEX_4V, VEX_L;
8461 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8462 (ins VR256:$src1, i256mem:$src2),
8463 !strconcat(OpcodeStr,
8464 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8466 (OpVT (X86VPermv VR256:$src1,
8467 (bitconvert (mem_frag addr:$src2)))))]>,
8468 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8471 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8472 let ExeDomain = SSEPackedSingle in
8473 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8475 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8476 ValueType OpVT, X86FoldableSchedWrite Sched> {
8477 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8478 (ins VR256:$src1, u8imm:$src2),
8479 !strconcat(OpcodeStr,
8480 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8482 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8483 Sched<[Sched]>, VEX, VEX_L;
8484 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8485 (ins i256mem:$src1, u8imm:$src2),
8486 !strconcat(OpcodeStr,
8487 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8489 (OpVT (X86VPermi (mem_frag addr:$src1),
8490 (i8 imm:$src2))))]>,
8491 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8494 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8495 WriteShuffle256>, VEX_W;
8496 let ExeDomain = SSEPackedDouble in
8497 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8498 WriteFShuffle256>, VEX_W;
8500 //===----------------------------------------------------------------------===//
8501 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8503 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8504 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8505 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8506 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8507 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8509 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8510 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8511 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8512 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8514 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8516 let Predicates = [HasAVX2] in {
8517 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8518 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8519 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8520 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8521 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8522 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8524 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8526 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8527 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8528 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8529 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8530 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8532 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8536 //===----------------------------------------------------------------------===//
8537 // VINSERTI128 - Insert packed integer values
8539 let hasSideEffects = 0 in {
8540 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8541 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8542 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8543 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8545 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8546 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8547 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8548 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8551 let Predicates = [HasAVX2, NoVLX] in {
8552 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8554 (VINSERTI128rr VR256:$src1, VR128:$src2,
8555 (INSERT_get_vinsert128_imm VR256:$ins))>;
8556 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8558 (VINSERTI128rr VR256:$src1, VR128:$src2,
8559 (INSERT_get_vinsert128_imm VR256:$ins))>;
8560 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8562 (VINSERTI128rr VR256:$src1, VR128:$src2,
8563 (INSERT_get_vinsert128_imm VR256:$ins))>;
8564 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8566 (VINSERTI128rr VR256:$src1, VR128:$src2,
8567 (INSERT_get_vinsert128_imm VR256:$ins))>;
8569 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8571 (VINSERTI128rm VR256:$src1, addr:$src2,
8572 (INSERT_get_vinsert128_imm VR256:$ins))>;
8573 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8574 (bc_v4i32 (loadv2i64 addr:$src2)),
8576 (VINSERTI128rm VR256:$src1, addr:$src2,
8577 (INSERT_get_vinsert128_imm VR256:$ins))>;
8578 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8579 (bc_v16i8 (loadv2i64 addr:$src2)),
8581 (VINSERTI128rm VR256:$src1, addr:$src2,
8582 (INSERT_get_vinsert128_imm VR256:$ins))>;
8583 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8584 (bc_v8i16 (loadv2i64 addr:$src2)),
8586 (VINSERTI128rm VR256:$src1, addr:$src2,
8587 (INSERT_get_vinsert128_imm VR256:$ins))>;
8590 //===----------------------------------------------------------------------===//
8591 // VEXTRACTI128 - Extract packed integer values
8593 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8594 (ins VR256:$src1, u8imm:$src2),
8595 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8596 Sched<[WriteShuffle256]>, VEX, VEX_L;
8597 let hasSideEffects = 0, mayStore = 1 in
8598 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8599 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8600 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8601 Sched<[WriteStore]>, VEX, VEX_L;
8603 let Predicates = [HasAVX2] in {
8604 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8605 (v2i64 (VEXTRACTI128rr
8606 (v4i64 VR256:$src1),
8607 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8608 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8609 (v4i32 (VEXTRACTI128rr
8610 (v8i32 VR256:$src1),
8611 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8612 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8613 (v8i16 (VEXTRACTI128rr
8614 (v16i16 VR256:$src1),
8615 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8616 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8617 (v16i8 (VEXTRACTI128rr
8618 (v32i8 VR256:$src1),
8619 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8621 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8622 (iPTR imm))), addr:$dst),
8623 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8624 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8625 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8626 (iPTR imm))), addr:$dst),
8627 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8628 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8629 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8630 (iPTR imm))), addr:$dst),
8631 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8632 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8633 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8634 (iPTR imm))), addr:$dst),
8635 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8636 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8639 //===----------------------------------------------------------------------===//
8640 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8642 multiclass avx2_pmovmask<string OpcodeStr,
8643 Intrinsic IntLd128, Intrinsic IntLd256,
8644 Intrinsic IntSt128, Intrinsic IntSt256> {
8645 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8646 (ins VR128:$src1, i128mem:$src2),
8647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8648 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8649 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8650 (ins VR256:$src1, i256mem:$src2),
8651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8652 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8654 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8655 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8657 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8658 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8659 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8661 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8664 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8665 int_x86_avx2_maskload_d,
8666 int_x86_avx2_maskload_d_256,
8667 int_x86_avx2_maskstore_d,
8668 int_x86_avx2_maskstore_d_256>;
8669 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8670 int_x86_avx2_maskload_q,
8671 int_x86_avx2_maskload_q_256,
8672 int_x86_avx2_maskstore_q,
8673 int_x86_avx2_maskstore_q_256>, VEX_W;
8675 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8676 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8678 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8679 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8681 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8682 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8684 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8685 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8687 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8688 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8690 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8691 (bc_v8f32 (v8i32 immAllZerosV)))),
8692 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8694 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8695 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8698 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8699 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8701 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8702 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8704 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8705 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8708 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8709 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8711 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8712 (bc_v4f32 (v4i32 immAllZerosV)))),
8713 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8715 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8716 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8719 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8720 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8722 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8723 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8725 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8726 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8729 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8730 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8732 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8733 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8735 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8736 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8738 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8739 (v4f64 immAllZerosV))),
8740 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8742 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8743 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8746 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8747 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8749 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8750 (bc_v4i64 (v8i32 immAllZerosV)))),
8751 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8753 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8754 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8757 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8758 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8760 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8761 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8763 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8764 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8766 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8767 (v2f64 immAllZerosV))),
8768 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8770 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8771 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8774 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8775 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8777 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8778 (bc_v2i64 (v4i32 immAllZerosV)))),
8779 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8781 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8782 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8785 //===----------------------------------------------------------------------===//
8786 // Variable Bit Shifts
8788 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8789 ValueType vt128, ValueType vt256> {
8790 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8791 (ins VR128:$src1, VR128:$src2),
8792 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8794 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8795 VEX_4V, Sched<[WriteVarVecShift]>;
8796 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8797 (ins VR128:$src1, i128mem:$src2),
8798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8800 (vt128 (OpNode VR128:$src1,
8801 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8802 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8803 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8804 (ins VR256:$src1, VR256:$src2),
8805 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8807 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8808 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8809 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8810 (ins VR256:$src1, i256mem:$src2),
8811 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8813 (vt256 (OpNode VR256:$src1,
8814 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8815 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8818 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8819 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8820 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8821 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8822 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8824 //===----------------------------------------------------------------------===//
8825 // VGATHER - GATHER Operations
8826 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8827 X86MemOperand memop128, X86MemOperand memop256> {
8828 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8829 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8830 !strconcat(OpcodeStr,
8831 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8833 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8834 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8835 !strconcat(OpcodeStr,
8836 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8837 []>, VEX_4VOp3, VEX_L;
8840 let mayLoad = 1, Constraints
8841 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8843 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8844 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8845 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8846 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8848 let ExeDomain = SSEPackedDouble in {
8849 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8850 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8853 let ExeDomain = SSEPackedSingle in {
8854 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8855 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;