1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2079 (VCVTDQ2PSrm addr:$src)>;
2082 let Predicates = [HasAVX, NoVLX] in {
2083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX, NoVLX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2242 (VCVTDQ2PDrr VR128:$src)>;
2243 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDrm addr:$src)>;
2246 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2247 (VCVTDQ2PDYrr VR128:$src)>;
2248 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2249 (VCVTDQ2PDYrm addr:$src)>;
2250 } // Predicates = [HasAVX]
2252 // SSE2 register conversion intrinsics
2253 let Predicates = [HasSSE2] in {
2254 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2255 (CVTDQ2PDrr VR128:$src)>;
2256 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2257 (CVTDQ2PDrm addr:$src)>;
2258 } // Predicates = [HasSSE2]
2260 // Convert packed double to packed single
2261 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2262 // register, but the same isn't true when using memory operands instead.
2263 // Provide other assembly rr and rm forms to address this explicitly.
2264 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2265 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2266 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2267 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2270 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2271 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2272 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2273 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2275 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2276 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2279 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2280 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2282 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2283 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2284 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2285 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2287 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2288 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2289 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2290 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2292 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2293 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2294 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2295 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2296 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2297 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2299 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2300 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2303 // AVX 256-bit register conversion intrinsics
2304 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2305 // whenever possible to avoid declaring two versions of each one.
2306 let Predicates = [HasAVX] in {
2307 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2308 (VCVTDQ2PSYrr VR256:$src)>;
2309 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2310 (VCVTDQ2PSYrm addr:$src)>;
2313 let Predicates = [HasAVX, NoVLX] in {
2314 // Match fround and fextend for 128/256-bit conversions
2315 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2316 (VCVTPD2PSrr VR128:$src)>;
2317 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2318 (VCVTPD2PSXrm addr:$src)>;
2319 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2320 (VCVTPD2PSYrr VR256:$src)>;
2321 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2322 (VCVTPD2PSYrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (VCVTPS2PDrr VR128:$src)>;
2326 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2327 (VCVTPS2PDYrr VR128:$src)>;
2328 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2329 (VCVTPS2PDYrm addr:$src)>;
2332 let Predicates = [UseSSE2] in {
2333 // Match fround and fextend for 128 conversions
2334 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2335 (CVTPD2PSrr VR128:$src)>;
2336 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2337 (CVTPD2PSrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2340 (CVTPS2PDrr VR128:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // SSE 1 & 2 - Compare Instructions
2345 //===----------------------------------------------------------------------===//
2347 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2348 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2349 Operand CC, SDNode OpNode, ValueType VT,
2350 PatFrag ld_frag, string asm, string asm_alt,
2351 OpndItins itins, ImmLeaf immLeaf> {
2352 def rr : SIi8<0xC2, MRMSrcReg,
2353 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2355 itins.rr>, Sched<[itins.Sched]>;
2356 def rm : SIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2358 [(set RC:$dst, (OpNode (VT RC:$src1),
2359 (ld_frag addr:$src2), immLeaf:$cc))],
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2363 // Accept explicit immediate argument form instead of comparison code.
2364 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2365 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2369 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2371 IIC_SSE_ALU_F32S_RM>,
2372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2376 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2379 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2380 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2381 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2382 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2383 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2384 XD, VEX_4V, VEX_LIG;
2386 let Constraints = "$src1 = $dst" in {
2387 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2388 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2389 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2391 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2392 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2393 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2394 SSE_ALU_F64S, i8immZExt3>, XD;
2397 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2398 Intrinsic Int, string asm, OpndItins itins,
2400 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2401 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2402 [(set VR128:$dst, (Int VR128:$src1,
2403 VR128:$src, immLeaf:$cc))],
2405 Sched<[itins.Sched]>;
2406 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2407 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2408 [(set VR128:$dst, (Int VR128:$src1,
2409 (load addr:$src), immLeaf:$cc))],
2411 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2414 let isCodeGenOnly = 1 in {
2415 // Aliases to match intrinsics which expect XMM operand(s).
2416 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2418 SSE_ALU_F32S, i8immZExt5>,
2420 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2421 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2422 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2424 let Constraints = "$src1 = $dst" in {
2425 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2427 SSE_ALU_F32S, i8immZExt3>, XS;
2428 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2429 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2430 SSE_ALU_F64S, i8immZExt3>,
2436 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2437 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2438 ValueType vt, X86MemOperand x86memop,
2439 PatFrag ld_frag, string OpcodeStr> {
2440 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2441 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2442 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2445 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2446 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2447 [(set EFLAGS, (OpNode (vt RC:$src1),
2448 (ld_frag addr:$src2)))],
2450 Sched<[WriteFAddLd, ReadAfterLd]>;
2453 let Defs = [EFLAGS] in {
2454 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2455 "ucomiss">, PS, VEX, VEX_LIG;
2456 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2457 "ucomisd">, PD, VEX, VEX_LIG;
2458 let Pattern = []<dag> in {
2459 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2460 "comiss">, PS, VEX, VEX_LIG;
2461 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2462 "comisd">, PD, VEX, VEX_LIG;
2465 let isCodeGenOnly = 1 in {
2466 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2467 load, "ucomiss">, PS, VEX;
2468 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2469 load, "ucomisd">, PD, VEX;
2471 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2472 load, "comiss">, PS, VEX;
2473 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2474 load, "comisd">, PD, VEX;
2476 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2478 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2481 let Pattern = []<dag> in {
2482 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2484 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2488 let isCodeGenOnly = 1 in {
2489 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2490 load, "ucomiss">, PS;
2491 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2492 load, "ucomisd">, PD;
2494 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2496 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2499 } // Defs = [EFLAGS]
2501 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2502 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2503 Operand CC, Intrinsic Int, string asm,
2504 string asm_alt, Domain d, ImmLeaf immLeaf,
2505 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2506 let isCommutable = 1 in
2507 def rri : PIi8<0xC2, MRMSrcReg,
2508 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2509 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2512 def rmi : PIi8<0xC2, MRMSrcMem,
2513 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2514 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2518 // Accept explicit immediate argument form instead of comparison code.
2519 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2520 def rri_alt : PIi8<0xC2, MRMSrcReg,
2521 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2522 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2524 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2525 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2526 asm_alt, [], itins.rm, d>,
2527 Sched<[WriteFAddLd, ReadAfterLd]>;
2531 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2535 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2539 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2540 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2543 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2544 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2545 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2547 let Constraints = "$src1 = $dst" in {
2548 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2549 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2550 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2551 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2552 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2553 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2554 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2555 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2558 let Predicates = [HasAVX] in {
2559 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2560 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2561 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2562 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2565 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2566 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2568 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2569 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2570 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2571 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2572 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2573 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2574 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2575 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2578 let Predicates = [UseSSE1] in {
2579 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2580 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2581 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2582 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2585 let Predicates = [UseSSE2] in {
2586 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2587 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2588 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2589 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2592 //===----------------------------------------------------------------------===//
2593 // SSE 1 & 2 - Shuffle Instructions
2594 //===----------------------------------------------------------------------===//
2596 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2597 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2598 ValueType vt, string asm, PatFrag mem_frag,
2600 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2601 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2602 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2603 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2604 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2605 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2606 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2607 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2608 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2609 Sched<[WriteFShuffle]>;
2612 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2613 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2615 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2616 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2617 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2618 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2619 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2620 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2621 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2622 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2623 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2625 let Constraints = "$src1 = $dst" in {
2626 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2627 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2628 memopv4f32, SSEPackedSingle>, PS;
2629 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2630 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 memopv2f64, SSEPackedDouble>, PD;
2634 let Predicates = [HasAVX] in {
2635 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2636 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2637 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2639 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2641 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2642 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2643 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2645 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2648 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2649 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2650 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2651 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2652 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2654 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2655 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2656 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2657 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2658 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2661 let Predicates = [UseSSE1] in {
2662 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2663 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2664 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 let Predicates = [UseSSE2] in {
2670 // Generic SHUFPD patterns
2671 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2672 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2673 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2674 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2675 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2678 //===----------------------------------------------------------------------===//
2679 // SSE 1 & 2 - Unpack FP Instructions
2680 //===----------------------------------------------------------------------===//
2682 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2683 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2684 PatFrag mem_frag, RegisterClass RC,
2685 X86MemOperand x86memop, string asm,
2687 def rr : PI<opc, MRMSrcReg,
2688 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2690 (vt (OpNode RC:$src1, RC:$src2)))],
2691 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2692 def rm : PI<opc, MRMSrcMem,
2693 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2695 (vt (OpNode RC:$src1,
2696 (mem_frag addr:$src2))))],
2698 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2701 let Predicates = [HasAVX, NoVLX] in {
2702 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2703 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2704 SSEPackedSingle>, PS, VEX_4V;
2705 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2706 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedDouble>, PD, VEX_4V;
2708 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2709 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedSingle>, PS, VEX_4V;
2711 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2712 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedDouble>, PD, VEX_4V;
2715 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2716 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2717 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2718 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2719 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2720 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2721 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2722 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2723 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2724 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2725 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2726 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2727 }// Predicates = [HasAVX, NoVLX]
2728 let Constraints = "$src1 = $dst" in {
2729 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2730 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2731 SSEPackedSingle>, PS;
2732 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2733 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2734 SSEPackedDouble>, PD;
2735 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2736 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2737 SSEPackedSingle>, PS;
2738 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2739 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2740 SSEPackedDouble>, PD;
2741 } // Constraints = "$src1 = $dst"
2743 let Predicates = [HasAVX1Only] in {
2744 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2745 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2746 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2747 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2748 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2749 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2750 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2751 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2753 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2754 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2755 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2756 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2757 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2758 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2759 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2760 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2763 //===----------------------------------------------------------------------===//
2764 // SSE 1 & 2 - Extract Floating-Point Sign mask
2765 //===----------------------------------------------------------------------===//
2767 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2768 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2770 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2771 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2772 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2773 Sched<[WriteVecLogic]>;
2776 let Predicates = [HasAVX] in {
2777 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2778 "movmskps", SSEPackedSingle>, PS, VEX;
2779 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2780 "movmskpd", SSEPackedDouble>, PD, VEX;
2781 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2782 "movmskps", SSEPackedSingle>, PS,
2784 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2785 "movmskpd", SSEPackedDouble>, PD,
2788 def : Pat<(i32 (X86fgetsign FR32:$src)),
2789 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2790 def : Pat<(i64 (X86fgetsign FR32:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2793 def : Pat<(i32 (X86fgetsign FR64:$src)),
2794 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2795 def : Pat<(i64 (X86fgetsign FR64:$src)),
2796 (SUBREG_TO_REG (i64 0),
2797 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2800 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2801 SSEPackedSingle>, PS;
2802 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2803 SSEPackedDouble>, PD;
2805 def : Pat<(i32 (X86fgetsign FR32:$src)),
2806 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2807 Requires<[UseSSE1]>;
2808 def : Pat<(i64 (X86fgetsign FR32:$src)),
2809 (SUBREG_TO_REG (i64 0),
2810 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2811 Requires<[UseSSE1]>;
2812 def : Pat<(i32 (X86fgetsign FR64:$src)),
2813 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2814 Requires<[UseSSE2]>;
2815 def : Pat<(i64 (X86fgetsign FR64:$src)),
2816 (SUBREG_TO_REG (i64 0),
2817 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2818 Requires<[UseSSE2]>;
2820 //===---------------------------------------------------------------------===//
2821 // SSE2 - Packed Integer Logical Instructions
2822 //===---------------------------------------------------------------------===//
2824 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2826 /// PDI_binop_rm - Simple SSE2 binary operator.
2827 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2828 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2829 X86MemOperand x86memop, OpndItins itins,
2830 bit IsCommutable, bit Is2Addr> {
2831 let isCommutable = IsCommutable in
2832 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2833 (ins RC:$src1, RC:$src2),
2835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2837 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2838 Sched<[itins.Sched]>;
2839 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2840 (ins RC:$src1, x86memop:$src2),
2842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2844 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2845 (bitconvert (memop_frag addr:$src2)))))],
2847 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2849 } // ExeDomain = SSEPackedInt
2851 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2852 ValueType OpVT128, ValueType OpVT256,
2853 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2854 let Predicates = [HasAVX, prd] in
2855 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2856 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2858 let Constraints = "$src1 = $dst" in
2859 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2860 memopv2i64, i128mem, itins, IsCommutable, 1>;
2862 let Predicates = [HasAVX2, prd] in
2863 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2864 OpVT256, VR256, loadv4i64, i256mem, itins,
2865 IsCommutable, 0>, VEX_4V, VEX_L;
2868 // These are ordered here for pattern ordering requirements with the fp versions
2870 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2871 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2872 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2873 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2874 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2875 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2876 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2877 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2879 //===----------------------------------------------------------------------===//
2880 // SSE 1 & 2 - Logical Instructions
2881 //===----------------------------------------------------------------------===//
2883 // Multiclass for scalars using the X86 logical operation aliases for FP.
2884 multiclass sse12_fp_packed_scalar_logical_alias<
2885 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2886 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2887 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2890 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2891 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2894 let Constraints = "$src1 = $dst" in {
2895 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2896 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2898 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2899 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2903 let isCodeGenOnly = 1 in {
2904 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2906 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2908 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2911 let isCommutable = 0 in
2912 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2916 // Multiclass for vectors using the X86 logical operation aliases for FP.
2917 multiclass sse12_fp_packed_vector_logical_alias<
2918 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2919 let Predicates = [HasAVX, NoVLX] in {
2920 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2921 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2924 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2925 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2928 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2929 VR256, v8f32, f256mem, loadv8f32, SSEPackedSingle, itins, 0>,
2932 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2933 VR256, v4f64, f256mem, loadv4f64, SSEPackedDouble, itins, 0>,
2937 let Constraints = "$src1 = $dst" in {
2938 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2939 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2942 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2943 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2948 let isCodeGenOnly = 1 in {
2949 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2951 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2953 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2956 let isCommutable = 0 in
2957 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2961 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2963 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2965 let Predicates = [HasAVX, NoVLX] in {
2966 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2967 !strconcat(OpcodeStr, "ps"), f256mem,
2968 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2969 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2970 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2972 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2973 !strconcat(OpcodeStr, "pd"), f256mem,
2974 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2975 (bc_v4i64 (v4f64 VR256:$src2))))],
2976 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2977 (loadv4i64 addr:$src2)))], 0>,
2980 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2981 // are all promoted to v2i64, and the patterns are covered by the int
2982 // version. This is needed in SSE only, because v2i64 isn't supported on
2983 // SSE1, but only on SSE2.
2984 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2985 !strconcat(OpcodeStr, "ps"), f128mem, [],
2986 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2987 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2989 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2990 !strconcat(OpcodeStr, "pd"), f128mem,
2991 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2992 (bc_v2i64 (v2f64 VR128:$src2))))],
2993 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2994 (loadv2i64 addr:$src2)))], 0>,
2998 let Constraints = "$src1 = $dst" in {
2999 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
3000 !strconcat(OpcodeStr, "ps"), f128mem,
3001 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
3002 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
3003 (memopv2i64 addr:$src2)))]>, PS;
3005 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
3006 !strconcat(OpcodeStr, "pd"), f128mem,
3007 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3008 (bc_v2i64 (v2f64 VR128:$src2))))],
3009 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3010 (memopv2i64 addr:$src2)))]>, PD;
3014 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3015 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3016 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3017 let isCommutable = 0 in
3018 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3020 // AVX1 requires type coercions in order to fold loads directly into logical
3022 let Predicates = [HasAVX1Only] in {
3023 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3024 (VANDPSYrm VR256:$src1, addr:$src2)>;
3025 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3026 (VORPSYrm VR256:$src1, addr:$src2)>;
3027 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3028 (VXORPSYrm VR256:$src1, addr:$src2)>;
3029 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3030 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3033 //===----------------------------------------------------------------------===//
3034 // SSE 1 & 2 - Arithmetic Instructions
3035 //===----------------------------------------------------------------------===//
3037 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3040 /// In addition, we also have a special variant of the scalar form here to
3041 /// represent the associated intrinsic operation. This form is unlike the
3042 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3043 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3045 /// These three forms can each be reg+reg or reg+mem.
3048 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3050 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3051 SDNode OpNode, SizeItins itins> {
3052 let Predicates = [HasAVX, NoVLX] in {
3053 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3054 VR128, v4f32, f128mem, loadv4f32,
3055 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3056 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3057 VR128, v2f64, f128mem, loadv2f64,
3058 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3060 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3061 OpNode, VR256, v8f32, f256mem, loadv8f32,
3062 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3063 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3064 OpNode, VR256, v4f64, f256mem, loadv4f64,
3065 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3068 let Constraints = "$src1 = $dst" in {
3069 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3070 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3072 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3073 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3078 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3080 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3081 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3082 XS, VEX_4V, VEX_LIG;
3083 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3084 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3085 XD, VEX_4V, VEX_LIG;
3087 let Constraints = "$src1 = $dst" in {
3088 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3089 OpNode, FR32, f32mem, SSEPackedSingle,
3091 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3092 OpNode, FR64, f64mem, SSEPackedDouble,
3097 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3099 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3100 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3101 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3102 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3103 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3104 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3106 let Constraints = "$src1 = $dst" in {
3107 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3108 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3109 SSEPackedSingle, itins.s>, XS;
3110 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3111 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3112 SSEPackedDouble, itins.d>, XD;
3116 // Binary Arithmetic instructions
3117 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3118 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3119 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3120 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3121 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3122 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3123 let isCommutable = 0 in {
3124 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3125 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3126 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3127 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3128 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3129 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3130 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3131 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3132 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3133 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3134 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3135 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3138 let isCodeGenOnly = 1 in {
3139 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3140 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3141 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3142 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3145 // Patterns used to select SSE scalar fp arithmetic instructions from
3148 // (1) a scalar fp operation followed by a blend
3150 // The effect is that the backend no longer emits unnecessary vector
3151 // insert instructions immediately after SSE scalar fp instructions
3152 // like addss or mulss.
3154 // For example, given the following code:
3155 // __m128 foo(__m128 A, __m128 B) {
3160 // Previously we generated:
3161 // addss %xmm0, %xmm1
3162 // movss %xmm1, %xmm0
3165 // addss %xmm1, %xmm0
3167 // (2) a vector packed single/double fp operation followed by a vector insert
3169 // The effect is that the backend converts the packed fp instruction
3170 // followed by a vector insert into a single SSE scalar fp instruction.
3172 // For example, given the following code:
3173 // __m128 foo(__m128 A, __m128 B) {
3174 // __m128 C = A + B;
3175 // return (__m128) {c[0], a[1], a[2], a[3]};
3178 // Previously we generated:
3179 // addps %xmm0, %xmm1
3180 // movss %xmm1, %xmm0
3183 // addss %xmm1, %xmm0
3185 // TODO: Some canonicalization in lowering would simplify the number of
3186 // patterns we have to try to match.
3187 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3188 let Predicates = [UseSSE1] in {
3189 // extracted scalar math op with insert via movss
3190 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3191 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3193 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3194 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3196 // vector math op with insert via movss
3197 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3198 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3199 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3202 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3203 let Predicates = [UseSSE41] in {
3204 // extracted scalar math op with insert via blend
3205 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3206 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3207 FR32:$src))), (i8 1))),
3208 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3209 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3211 // vector math op with insert via blend
3212 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3213 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3214 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3218 // Repeat everything for AVX, except for the movss + scalar combo...
3219 // because that one shouldn't occur with AVX codegen?
3220 let Predicates = [HasAVX] in {
3221 // extracted scalar math op with insert via blend
3222 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3223 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3224 FR32:$src))), (i8 1))),
3225 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3226 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3228 // vector math op with insert via movss
3229 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3230 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3231 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3233 // vector math op with insert via blend
3234 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3235 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3236 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3240 defm : scalar_math_f32_patterns<fadd, "ADD">;
3241 defm : scalar_math_f32_patterns<fsub, "SUB">;
3242 defm : scalar_math_f32_patterns<fmul, "MUL">;
3243 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3245 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3246 let Predicates = [UseSSE2] in {
3247 // extracted scalar math op with insert via movsd
3248 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3249 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3251 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3252 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3254 // vector math op with insert via movsd
3255 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3256 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3257 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3260 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3261 let Predicates = [UseSSE41] in {
3262 // extracted scalar math op with insert via blend
3263 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3264 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3265 FR64:$src))), (i8 1))),
3266 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3267 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3269 // vector math op with insert via blend
3270 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3271 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3272 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3275 // Repeat everything for AVX.
3276 let Predicates = [HasAVX] in {
3277 // extracted scalar math op with insert via movsd
3278 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3279 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3281 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3282 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3284 // extracted scalar math op with insert via blend
3285 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3286 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3287 FR64:$src))), (i8 1))),
3288 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3289 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3291 // vector math op with insert via movsd
3292 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3293 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3294 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3296 // vector math op with insert via blend
3297 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3298 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3299 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3303 defm : scalar_math_f64_patterns<fadd, "ADD">;
3304 defm : scalar_math_f64_patterns<fsub, "SUB">;
3305 defm : scalar_math_f64_patterns<fmul, "MUL">;
3306 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3310 /// In addition, we also have a special variant of the scalar form here to
3311 /// represent the associated intrinsic operation. This form is unlike the
3312 /// plain scalar form, in that it takes an entire vector (instead of a
3313 /// scalar) and leaves the top elements undefined.
3315 /// And, we have a special variant form for a full-vector intrinsic form.
3317 let Sched = WriteFSqrt in {
3318 def SSE_SQRTPS : OpndItins<
3319 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3322 def SSE_SQRTSS : OpndItins<
3323 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3326 def SSE_SQRTPD : OpndItins<
3327 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3330 def SSE_SQRTSD : OpndItins<
3331 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3335 let Sched = WriteFRsqrt in {
3336 def SSE_RSQRTPS : OpndItins<
3337 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3340 def SSE_RSQRTSS : OpndItins<
3341 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3345 let Sched = WriteFRcp in {
3346 def SSE_RCPP : OpndItins<
3347 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3350 def SSE_RCPS : OpndItins<
3351 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3355 /// sse_fp_unop_s - SSE1 unops in scalar form
3356 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3357 /// the HW instructions are 2 operand / destructive.
3358 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3359 ValueType vt, ValueType ScalarVT,
3360 X86MemOperand x86memop, Operand vec_memop,
3361 ComplexPattern mem_cpat, Intrinsic Intr,
3362 SDNode OpNode, Domain d, OpndItins itins,
3363 Predicate target, string Suffix> {
3364 let hasSideEffects = 0 in {
3365 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3366 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3367 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3370 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3371 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3372 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3373 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3374 Requires<[target, OptForSize]>;
3376 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3377 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3378 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3379 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3381 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3382 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3383 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3387 let Predicates = [target] in {
3388 def : Pat<(vt (OpNode mem_cpat:$src)),
3389 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3390 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3391 // These are unary operations, but they are modeled as having 2 source operands
3392 // because the high elements of the destination are unchanged in SSE.
3393 def : Pat<(Intr VR128:$src),
3394 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3395 def : Pat<(Intr (load addr:$src)),
3396 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3397 addr:$src), VR128))>;
3398 def : Pat<(Intr mem_cpat:$src),
3399 (!cast<Instruction>(NAME#Suffix##m_Int)
3400 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3404 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3405 ValueType vt, ValueType ScalarVT,
3406 X86MemOperand x86memop, Operand vec_memop,
3407 ComplexPattern mem_cpat,
3408 Intrinsic Intr, SDNode OpNode, Domain d,
3409 OpndItins itins, string Suffix> {
3410 let hasSideEffects = 0 in {
3411 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3413 [], itins.rr, d>, Sched<[itins.Sched]>;
3415 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3417 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3418 let isCodeGenOnly = 1 in {
3419 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3420 (ins VR128:$src1, VR128:$src2),
3421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3422 []>, Sched<[itins.Sched.Folded]>;
3424 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3425 (ins VR128:$src1, vec_memop:$src2),
3426 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3427 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3431 let Predicates = [UseAVX] in {
3432 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3433 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3435 def : Pat<(vt (OpNode mem_cpat:$src)),
3436 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3440 let Predicates = [HasAVX] in {
3441 def : Pat<(Intr VR128:$src),
3442 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3445 def : Pat<(Intr mem_cpat:$src),
3446 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3447 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3449 let Predicates = [UseAVX, OptForSize] in
3450 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3451 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3455 /// sse1_fp_unop_p - SSE1 unops in packed form.
3456 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3458 let Predicates = [HasAVX] in {
3459 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3460 !strconcat("v", OpcodeStr,
3461 "ps\t{$src, $dst|$dst, $src}"),
3462 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3463 itins.rr>, VEX, Sched<[itins.Sched]>;
3464 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3465 !strconcat("v", OpcodeStr,
3466 "ps\t{$src, $dst|$dst, $src}"),
3467 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3468 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3469 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3470 !strconcat("v", OpcodeStr,
3471 "ps\t{$src, $dst|$dst, $src}"),
3472 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3473 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3474 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3475 !strconcat("v", OpcodeStr,
3476 "ps\t{$src, $dst|$dst, $src}"),
3477 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3478 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3481 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3482 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3483 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3484 Sched<[itins.Sched]>;
3485 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3486 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3487 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3488 Sched<[itins.Sched.Folded]>;
3491 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3492 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3493 SDNode OpNode, OpndItins itins> {
3494 let Predicates = [HasAVX] in {
3495 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3496 !strconcat("v", OpcodeStr,
3497 "pd\t{$src, $dst|$dst, $src}"),
3498 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3499 itins.rr>, VEX, Sched<[itins.Sched]>;
3500 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3501 !strconcat("v", OpcodeStr,
3502 "pd\t{$src, $dst|$dst, $src}"),
3503 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3504 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3505 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3506 !strconcat("v", OpcodeStr,
3507 "pd\t{$src, $dst|$dst, $src}"),
3508 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3509 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3510 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3511 !strconcat("v", OpcodeStr,
3512 "pd\t{$src, $dst|$dst, $src}"),
3513 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3514 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3517 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3518 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3519 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3520 Sched<[itins.Sched]>;
3521 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3522 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3523 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3524 Sched<[itins.Sched.Folded]>;
3527 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3529 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3530 ssmem, sse_load_f32,
3531 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3532 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3533 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3534 f32mem, ssmem, sse_load_f32,
3535 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3536 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3539 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3541 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3542 sdmem, sse_load_f64,
3543 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3544 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3545 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3546 f64mem, sdmem, sse_load_f64,
3547 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3548 OpNode, SSEPackedDouble, itins, "SD">,
3549 XD, VEX_4V, VEX_LIG;
3553 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3554 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3555 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3556 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3558 // Reciprocal approximations. Note that these typically require refinement
3559 // in order to obtain suitable precision.
3560 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3561 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3562 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3563 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3565 // There is no f64 version of the reciprocal approximation instructions.
3567 // TODO: We should add *scalar* op patterns for these just like we have for
3568 // the binops above. If the binop and unop patterns could all be unified
3569 // that would be even better.
3571 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3572 SDNode Move, ValueType VT,
3573 Predicate BasePredicate> {
3574 let Predicates = [BasePredicate] in {
3575 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3576 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3579 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3580 let Predicates = [UseSSE41] in {
3581 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3582 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3585 // Repeat for AVX versions of the instructions.
3586 let Predicates = [HasAVX] in {
3587 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3588 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3590 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3591 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3595 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3597 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3599 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3601 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3605 //===----------------------------------------------------------------------===//
3606 // SSE 1 & 2 - Non-temporal stores
3607 //===----------------------------------------------------------------------===//
3609 let AddedComplexity = 400 in { // Prefer non-temporal versions
3610 let SchedRW = [WriteStore] in {
3611 let Predicates = [HasAVX, NoVLX] in {
3612 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3613 (ins f128mem:$dst, VR128:$src),
3614 "movntps\t{$src, $dst|$dst, $src}",
3615 [(alignednontemporalstore (v4f32 VR128:$src),
3617 IIC_SSE_MOVNT>, VEX;
3618 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3619 (ins f128mem:$dst, VR128:$src),
3620 "movntpd\t{$src, $dst|$dst, $src}",
3621 [(alignednontemporalstore (v2f64 VR128:$src),
3623 IIC_SSE_MOVNT>, VEX;
3625 let ExeDomain = SSEPackedInt in
3626 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3627 (ins f128mem:$dst, VR128:$src),
3628 "movntdq\t{$src, $dst|$dst, $src}",
3629 [(alignednontemporalstore (v2i64 VR128:$src),
3631 IIC_SSE_MOVNT>, VEX;
3633 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3634 (ins f256mem:$dst, VR256:$src),
3635 "movntps\t{$src, $dst|$dst, $src}",
3636 [(alignednontemporalstore (v8f32 VR256:$src),
3638 IIC_SSE_MOVNT>, VEX, VEX_L;
3639 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3640 (ins f256mem:$dst, VR256:$src),
3641 "movntpd\t{$src, $dst|$dst, $src}",
3642 [(alignednontemporalstore (v4f64 VR256:$src),
3644 IIC_SSE_MOVNT>, VEX, VEX_L;
3645 let ExeDomain = SSEPackedInt in
3646 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3647 (ins f256mem:$dst, VR256:$src),
3648 "movntdq\t{$src, $dst|$dst, $src}",
3649 [(alignednontemporalstore (v4i64 VR256:$src),
3651 IIC_SSE_MOVNT>, VEX, VEX_L;
3654 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3655 "movntps\t{$src, $dst|$dst, $src}",
3656 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3658 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3659 "movntpd\t{$src, $dst|$dst, $src}",
3660 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3663 let ExeDomain = SSEPackedInt in
3664 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3665 "movntdq\t{$src, $dst|$dst, $src}",
3666 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3669 // There is no AVX form for instructions below this point
3670 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3671 "movnti{l}\t{$src, $dst|$dst, $src}",
3672 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3674 PS, Requires<[HasSSE2]>;
3675 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3676 "movnti{q}\t{$src, $dst|$dst, $src}",
3677 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3679 PS, Requires<[HasSSE2]>;
3680 } // SchedRW = [WriteStore]
3682 let Predicates = [HasAVX2, NoVLX] in {
3683 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3684 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3685 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3686 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3687 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3688 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3691 let Predicates = [HasAVX, NoVLX] in {
3692 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3693 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3694 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3695 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3696 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3697 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3700 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3701 (MOVNTDQmr addr:$dst, VR128:$src)>;
3702 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3703 (MOVNTDQmr addr:$dst, VR128:$src)>;
3704 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3705 (MOVNTDQmr addr:$dst, VR128:$src)>;
3707 } // AddedComplexity
3709 //===----------------------------------------------------------------------===//
3710 // SSE 1 & 2 - Prefetch and memory fence
3711 //===----------------------------------------------------------------------===//
3713 // Prefetch intrinsic.
3714 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3715 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3716 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3717 IIC_SSE_PREFETCH>, TB;
3718 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3719 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3720 IIC_SSE_PREFETCH>, TB;
3721 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3722 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3723 IIC_SSE_PREFETCH>, TB;
3724 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3725 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3726 IIC_SSE_PREFETCH>, TB;
3729 // FIXME: How should flush instruction be modeled?
3730 let SchedRW = [WriteLoad] in {
3732 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3733 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3734 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3737 let SchedRW = [WriteNop] in {
3738 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3739 // was introduced with SSE2, it's backward compatible.
3740 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3741 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3742 OBXS, Requires<[HasSSE2]>;
3745 let SchedRW = [WriteFence] in {
3746 // Load, store, and memory fence
3747 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3748 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3749 PS, Requires<[HasSSE1]>;
3750 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3751 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3752 TB, Requires<[HasSSE2]>;
3753 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3754 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3755 TB, Requires<[HasSSE2]>;
3758 def : Pat<(X86SFence), (SFENCE)>;
3759 def : Pat<(X86LFence), (LFENCE)>;
3760 def : Pat<(X86MFence), (MFENCE)>;
3762 //===----------------------------------------------------------------------===//
3763 // SSE 1 & 2 - Load/Store XCSR register
3764 //===----------------------------------------------------------------------===//
3766 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3767 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3768 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3769 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3770 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3771 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3773 let Predicates = [UseSSE1] in {
3774 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3775 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3776 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3777 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3778 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3779 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3782 //===---------------------------------------------------------------------===//
3783 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3784 //===---------------------------------------------------------------------===//
3786 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3788 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3789 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3790 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3792 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3793 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3795 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3796 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3798 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3799 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3804 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3805 SchedRW = [WriteMove] in {
3806 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3807 "movdqa\t{$src, $dst|$dst, $src}", [],
3810 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3811 "movdqa\t{$src, $dst|$dst, $src}", [],
3812 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3813 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3814 "movdqu\t{$src, $dst|$dst, $src}", [],
3817 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3818 "movdqu\t{$src, $dst|$dst, $src}", [],
3819 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3822 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3823 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3824 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3825 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3827 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3828 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3830 let Predicates = [HasAVX] in {
3831 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3832 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3834 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3835 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3840 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3841 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3842 (ins i128mem:$dst, VR128:$src),
3843 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3845 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3846 (ins i256mem:$dst, VR256:$src),
3847 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3849 let Predicates = [HasAVX] in {
3850 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3851 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3853 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3854 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3859 let SchedRW = [WriteMove] in {
3860 let hasSideEffects = 0 in
3861 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3862 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3864 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3865 "movdqu\t{$src, $dst|$dst, $src}",
3866 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3869 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3870 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3871 "movdqa\t{$src, $dst|$dst, $src}", [],
3874 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3875 "movdqu\t{$src, $dst|$dst, $src}",
3876 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3880 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3881 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3882 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3883 "movdqa\t{$src, $dst|$dst, $src}",
3884 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3886 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3887 "movdqu\t{$src, $dst|$dst, $src}",
3888 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3890 XS, Requires<[UseSSE2]>;
3893 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3894 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3895 "movdqa\t{$src, $dst|$dst, $src}",
3896 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3898 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3899 "movdqu\t{$src, $dst|$dst, $src}",
3900 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3902 XS, Requires<[UseSSE2]>;
3905 } // ExeDomain = SSEPackedInt
3907 let Predicates = [HasAVX] in {
3908 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3909 (VMOVDQUmr addr:$dst, VR128:$src)>;
3910 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3911 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3913 let Predicates = [UseSSE2] in
3914 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3915 (MOVDQUmr addr:$dst, VR128:$src)>;
3917 //===---------------------------------------------------------------------===//
3918 // SSE2 - Packed Integer Arithmetic Instructions
3919 //===---------------------------------------------------------------------===//
3921 let Sched = WriteVecIMul in
3922 def SSE_PMADD : OpndItins<
3923 IIC_SSE_PMADD, IIC_SSE_PMADD
3926 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3928 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3929 RegisterClass RC, PatFrag memop_frag,
3930 X86MemOperand x86memop,
3932 bit IsCommutable = 0,
3934 let isCommutable = IsCommutable in
3935 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3936 (ins RC:$src1, RC:$src2),
3938 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3940 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3941 Sched<[itins.Sched]>;
3942 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3943 (ins RC:$src1, x86memop:$src2),
3945 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3947 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3948 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3951 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3952 Intrinsic IntId256, OpndItins itins,
3953 bit IsCommutable = 0> {
3954 let Predicates = [HasAVX] in
3955 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3956 VR128, loadv2i64, i128mem, itins,
3957 IsCommutable, 0>, VEX_4V;
3959 let Constraints = "$src1 = $dst" in
3960 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3961 i128mem, itins, IsCommutable, 1>;
3963 let Predicates = [HasAVX2] in
3964 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3965 VR256, loadv4i64, i256mem, itins,
3966 IsCommutable, 0>, VEX_4V, VEX_L;
3969 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3970 string OpcodeStr, SDNode OpNode,
3971 SDNode OpNode2, RegisterClass RC,
3972 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3973 PatFrag ld_frag, ShiftOpndItins itins,
3975 // src2 is always 128-bit
3976 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3977 (ins RC:$src1, VR128:$src2),
3979 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3981 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3982 itins.rr>, Sched<[WriteVecShift]>;
3983 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3984 (ins RC:$src1, i128mem:$src2),
3986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3988 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3989 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3990 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3991 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3992 (ins RC:$src1, u8imm:$src2),
3994 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3996 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3997 Sched<[WriteVecShift]>;
4000 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4001 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4002 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4003 PatFrag memop_frag, X86MemOperand x86memop,
4005 bit IsCommutable = 0, bit Is2Addr = 1> {
4006 let isCommutable = IsCommutable in
4007 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4008 (ins RC:$src1, RC:$src2),
4010 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4012 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4013 Sched<[itins.Sched]>;
4014 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4015 (ins RC:$src1, x86memop:$src2),
4017 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4019 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4020 (bitconvert (memop_frag addr:$src2)))))]>,
4021 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4023 } // ExeDomain = SSEPackedInt
4025 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4026 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4027 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4028 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4029 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4030 SSE_INTALU_ITINS_P, 1, NoVLX>;
4031 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4032 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4033 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4034 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4035 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4036 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4037 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4038 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4039 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4040 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4041 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4042 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4043 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4044 SSE_INTALU_ITINS_P, 0, NoVLX>;
4045 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4046 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4047 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4048 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4049 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4050 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4051 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4052 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4053 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4054 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4055 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4056 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4057 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4058 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4061 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4062 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4063 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4064 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4065 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4066 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4067 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4068 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4069 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4070 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4071 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4072 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4073 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4074 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4075 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4076 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4077 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4078 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4079 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4080 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4082 let Predicates = [HasAVX2] in
4083 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4084 (v32i8 VR256:$src2))),
4085 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4087 let Predicates = [HasAVX] in
4088 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4089 (v16i8 VR128:$src2))),
4090 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4092 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4093 (v16i8 VR128:$src2))),
4094 (PSADBWrr VR128:$src2, VR128:$src1)>;
4096 let Predicates = [HasAVX] in
4097 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4098 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4100 let Predicates = [HasAVX2] in
4101 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4102 VR256, loadv4i64, i256mem,
4103 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4104 let Constraints = "$src1 = $dst" in
4105 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4106 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4108 //===---------------------------------------------------------------------===//
4109 // SSE2 - Packed Integer Logical Instructions
4110 //===---------------------------------------------------------------------===//
4112 let Predicates = [HasAVX, NoVLX] in {
4113 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4114 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4115 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4116 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4117 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4118 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4119 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4120 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4121 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4123 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4124 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4125 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4126 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4127 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4128 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4129 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4130 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4131 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4133 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4134 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4135 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4136 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4137 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4138 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4140 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4141 // 128-bit logical shifts.
4142 def VPSLLDQri : PDIi8<0x73, MRM7r,
4143 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4144 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4146 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4148 def VPSRLDQri : PDIi8<0x73, MRM3r,
4149 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4150 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4152 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4154 // PSRADQri doesn't exist in SSE[1-3].
4156 } // Predicates = [HasAVX]
4158 let Predicates = [HasAVX2, NoVLX] in {
4159 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4160 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4161 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4162 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4163 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4164 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4165 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4166 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4167 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4169 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4170 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4171 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4172 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4173 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4174 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4175 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4176 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4177 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4179 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4180 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4181 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4182 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4183 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4184 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4186 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4187 // 256-bit logical shifts.
4188 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4189 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4190 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4192 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4194 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4195 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4196 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4198 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4200 // PSRADQYri doesn't exist in SSE[1-3].
4202 } // Predicates = [HasAVX2]
4204 let Constraints = "$src1 = $dst" in {
4205 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4206 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4207 SSE_INTSHIFT_ITINS_P>;
4208 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4209 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4210 SSE_INTSHIFT_ITINS_P>;
4211 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4212 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4213 SSE_INTSHIFT_ITINS_P>;
4215 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4216 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4217 SSE_INTSHIFT_ITINS_P>;
4218 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4219 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4220 SSE_INTSHIFT_ITINS_P>;
4221 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4222 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4223 SSE_INTSHIFT_ITINS_P>;
4225 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4226 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4227 SSE_INTSHIFT_ITINS_P>;
4228 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4229 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4230 SSE_INTSHIFT_ITINS_P>;
4232 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4233 // 128-bit logical shifts.
4234 def PSLLDQri : PDIi8<0x73, MRM7r,
4235 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4236 "pslldq\t{$src2, $dst|$dst, $src2}",
4238 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4239 IIC_SSE_INTSHDQ_P_RI>;
4240 def PSRLDQri : PDIi8<0x73, MRM3r,
4241 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4242 "psrldq\t{$src2, $dst|$dst, $src2}",
4244 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4245 IIC_SSE_INTSHDQ_P_RI>;
4246 // PSRADQri doesn't exist in SSE[1-3].
4248 } // Constraints = "$src1 = $dst"
4250 //===---------------------------------------------------------------------===//
4251 // SSE2 - Packed Integer Comparison Instructions
4252 //===---------------------------------------------------------------------===//
4254 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4255 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4256 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4257 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4258 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4259 SSE_INTALU_ITINS_P, 1, NoVLX>;
4260 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4261 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4262 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4263 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4264 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4265 SSE_INTALU_ITINS_P, 0, NoVLX>;
4267 //===---------------------------------------------------------------------===//
4268 // SSE2 - Packed Integer Shuffle Instructions
4269 //===---------------------------------------------------------------------===//
4271 let ExeDomain = SSEPackedInt in {
4272 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4274 let Predicates = [HasAVX] in {
4275 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4276 (ins VR128:$src1, u8imm:$src2),
4277 !strconcat("v", OpcodeStr,
4278 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4280 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4281 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4282 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4283 (ins i128mem:$src1, u8imm:$src2),
4284 !strconcat("v", OpcodeStr,
4285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4287 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4288 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4289 Sched<[WriteShuffleLd]>;
4292 let Predicates = [HasAVX2] in {
4293 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4294 (ins VR256:$src1, u8imm:$src2),
4295 !strconcat("v", OpcodeStr,
4296 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4298 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4299 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4300 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4301 (ins i256mem:$src1, u8imm:$src2),
4302 !strconcat("v", OpcodeStr,
4303 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4305 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4306 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4307 Sched<[WriteShuffleLd]>;
4310 let Predicates = [UseSSE2] in {
4311 def ri : Ii8<0x70, MRMSrcReg,
4312 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4313 !strconcat(OpcodeStr,
4314 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4316 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4317 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4318 def mi : Ii8<0x70, MRMSrcMem,
4319 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4320 !strconcat(OpcodeStr,
4321 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4323 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4324 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4325 Sched<[WriteShuffleLd, ReadAfterLd]>;
4328 } // ExeDomain = SSEPackedInt
4330 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4331 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4332 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4334 let Predicates = [HasAVX] in {
4335 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4336 (VPSHUFDmi addr:$src1, imm:$imm)>;
4337 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4338 (VPSHUFDri VR128:$src1, imm:$imm)>;
4341 let Predicates = [UseSSE2] in {
4342 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4343 (PSHUFDmi addr:$src1, imm:$imm)>;
4344 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4345 (PSHUFDri VR128:$src1, imm:$imm)>;
4348 //===---------------------------------------------------------------------===//
4349 // Packed Integer Pack Instructions (SSE & AVX)
4350 //===---------------------------------------------------------------------===//
4352 let ExeDomain = SSEPackedInt in {
4353 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4354 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4355 PatFrag ld_frag, bit Is2Addr = 1> {
4356 def rr : PDI<opc, MRMSrcReg,
4357 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4360 !strconcat(OpcodeStr,
4361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4363 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4364 Sched<[WriteShuffle]>;
4365 def rm : PDI<opc, MRMSrcMem,
4366 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4368 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4369 !strconcat(OpcodeStr,
4370 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4372 (OutVT (OpNode VR128:$src1,
4373 (bc_frag (ld_frag addr:$src2)))))]>,
4374 Sched<[WriteShuffleLd, ReadAfterLd]>;
4377 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4378 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4379 def Yrr : PDI<opc, MRMSrcReg,
4380 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4381 !strconcat(OpcodeStr,
4382 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4384 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4385 Sched<[WriteShuffle]>;
4386 def Yrm : PDI<opc, MRMSrcMem,
4387 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4388 !strconcat(OpcodeStr,
4389 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4391 (OutVT (OpNode VR256:$src1,
4392 (bc_frag (loadv4i64 addr:$src2)))))]>,
4393 Sched<[WriteShuffleLd, ReadAfterLd]>;
4396 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4397 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4398 PatFrag ld_frag, bit Is2Addr = 1> {
4399 def rr : SS48I<opc, MRMSrcReg,
4400 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4402 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4403 !strconcat(OpcodeStr,
4404 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4406 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4407 Sched<[WriteShuffle]>;
4408 def rm : SS48I<opc, MRMSrcMem,
4409 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4411 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4412 !strconcat(OpcodeStr,
4413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4415 (OutVT (OpNode VR128:$src1,
4416 (bc_frag (ld_frag addr:$src2)))))]>,
4417 Sched<[WriteShuffleLd, ReadAfterLd]>;
4420 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4421 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4422 def Yrr : SS48I<opc, MRMSrcReg,
4423 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4424 !strconcat(OpcodeStr,
4425 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4427 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4428 Sched<[WriteShuffle]>;
4429 def Yrm : SS48I<opc, MRMSrcMem,
4430 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4431 !strconcat(OpcodeStr,
4432 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4434 (OutVT (OpNode VR256:$src1,
4435 (bc_frag (loadv4i64 addr:$src2)))))]>,
4436 Sched<[WriteShuffleLd, ReadAfterLd]>;
4439 let Predicates = [HasAVX] in {
4440 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4441 bc_v8i16, loadv2i64, 0>, VEX_4V;
4442 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4443 bc_v4i32, loadv2i64, 0>, VEX_4V;
4445 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4446 bc_v8i16, loadv2i64, 0>, VEX_4V;
4447 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4448 bc_v4i32, loadv2i64, 0>, VEX_4V;
4451 let Predicates = [HasAVX2] in {
4452 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4453 bc_v16i16>, VEX_4V, VEX_L;
4454 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4455 bc_v8i32>, VEX_4V, VEX_L;
4457 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4458 bc_v16i16>, VEX_4V, VEX_L;
4459 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4460 bc_v8i32>, VEX_4V, VEX_L;
4463 let Constraints = "$src1 = $dst" in {
4464 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4465 bc_v8i16, memopv2i64>;
4466 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4467 bc_v4i32, memopv2i64>;
4469 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4470 bc_v8i16, memopv2i64>;
4472 let Predicates = [HasSSE41] in
4473 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4474 bc_v4i32, memopv2i64>;
4476 } // ExeDomain = SSEPackedInt
4478 //===---------------------------------------------------------------------===//
4479 // SSE2 - Packed Integer Unpack Instructions
4480 //===---------------------------------------------------------------------===//
4482 let ExeDomain = SSEPackedInt in {
4483 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4484 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4486 def rr : PDI<opc, MRMSrcReg,
4487 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4489 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4490 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4491 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4492 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4493 def rm : PDI<opc, MRMSrcMem,
4494 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4496 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4497 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4498 [(set VR128:$dst, (OpNode VR128:$src1,
4499 (bc_frag (ld_frag addr:$src2))))],
4501 Sched<[WriteShuffleLd, ReadAfterLd]>;
4504 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4505 SDNode OpNode, PatFrag bc_frag> {
4506 def Yrr : PDI<opc, MRMSrcReg,
4507 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4508 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4509 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4510 Sched<[WriteShuffle]>;
4511 def Yrm : PDI<opc, MRMSrcMem,
4512 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4513 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4514 [(set VR256:$dst, (OpNode VR256:$src1,
4515 (bc_frag (loadv4i64 addr:$src2))))]>,
4516 Sched<[WriteShuffleLd, ReadAfterLd]>;
4520 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4521 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4522 bc_v16i8, loadv2i64, 0>, VEX_4V;
4523 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4524 bc_v8i16, loadv2i64, 0>, VEX_4V;
4525 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4526 bc_v16i8, loadv2i64, 0>, VEX_4V;
4527 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4528 bc_v8i16, loadv2i64, 0>, VEX_4V;
4530 let Predicates = [HasAVX, NoVLX] in {
4531 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4532 bc_v4i32, loadv2i64, 0>, VEX_4V;
4533 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4534 bc_v2i64, loadv2i64, 0>, VEX_4V;
4535 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4536 bc_v4i32, loadv2i64, 0>, VEX_4V;
4537 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4538 bc_v2i64, loadv2i64, 0>, VEX_4V;
4541 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4542 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4543 bc_v32i8>, VEX_4V, VEX_L;
4544 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4545 bc_v16i16>, VEX_4V, VEX_L;
4546 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4547 bc_v32i8>, VEX_4V, VEX_L;
4548 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4549 bc_v16i16>, VEX_4V, VEX_L;
4551 let Predicates = [HasAVX2, NoVLX] in {
4552 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4553 bc_v8i32>, VEX_4V, VEX_L;
4554 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4555 bc_v4i64>, VEX_4V, VEX_L;
4556 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4557 bc_v8i32>, VEX_4V, VEX_L;
4558 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4559 bc_v4i64>, VEX_4V, VEX_L;
4562 let Constraints = "$src1 = $dst" in {
4563 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4564 bc_v16i8, memopv2i64>;
4565 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4566 bc_v8i16, memopv2i64>;
4567 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4568 bc_v4i32, memopv2i64>;
4569 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4570 bc_v2i64, memopv2i64>;
4572 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4573 bc_v16i8, memopv2i64>;
4574 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4575 bc_v8i16, memopv2i64>;
4576 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4577 bc_v4i32, memopv2i64>;
4578 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4579 bc_v2i64, memopv2i64>;
4581 } // ExeDomain = SSEPackedInt
4583 //===---------------------------------------------------------------------===//
4584 // SSE2 - Packed Integer Extract and Insert
4585 //===---------------------------------------------------------------------===//
4587 let ExeDomain = SSEPackedInt in {
4588 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4589 def rri : Ii8<0xC4, MRMSrcReg,
4590 (outs VR128:$dst), (ins VR128:$src1,
4591 GR32orGR64:$src2, u8imm:$src3),
4593 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4594 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4596 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4597 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4598 def rmi : Ii8<0xC4, MRMSrcMem,
4599 (outs VR128:$dst), (ins VR128:$src1,
4600 i16mem:$src2, u8imm:$src3),
4602 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4603 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4605 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4606 imm:$src3))], IIC_SSE_PINSRW>,
4607 Sched<[WriteShuffleLd, ReadAfterLd]>;
4611 let Predicates = [HasAVX] in
4612 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4613 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4614 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4615 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4616 imm:$src2))]>, PD, VEX,
4617 Sched<[WriteShuffle]>;
4618 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4619 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4620 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4621 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4622 imm:$src2))], IIC_SSE_PEXTRW>,
4623 Sched<[WriteShuffleLd, ReadAfterLd]>;
4626 let Predicates = [HasAVX] in
4627 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4629 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4630 defm PINSRW : sse2_pinsrw, PD;
4632 } // ExeDomain = SSEPackedInt
4634 //===---------------------------------------------------------------------===//
4635 // SSE2 - Packed Mask Creation
4636 //===---------------------------------------------------------------------===//
4638 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4640 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4642 "pmovmskb\t{$src, $dst|$dst, $src}",
4643 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4644 IIC_SSE_MOVMSK>, VEX;
4646 let Predicates = [HasAVX2] in {
4647 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4649 "pmovmskb\t{$src, $dst|$dst, $src}",
4650 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4654 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4655 "pmovmskb\t{$src, $dst|$dst, $src}",
4656 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4659 } // ExeDomain = SSEPackedInt
4661 //===---------------------------------------------------------------------===//
4662 // SSE2 - Conditional Store
4663 //===---------------------------------------------------------------------===//
4665 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4667 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4668 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4669 (ins VR128:$src, VR128:$mask),
4670 "maskmovdqu\t{$mask, $src|$src, $mask}",
4671 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4672 IIC_SSE_MASKMOV>, VEX;
4673 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4674 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4675 (ins VR128:$src, VR128:$mask),
4676 "maskmovdqu\t{$mask, $src|$src, $mask}",
4677 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4678 IIC_SSE_MASKMOV>, VEX;
4680 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4681 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4682 "maskmovdqu\t{$mask, $src|$src, $mask}",
4683 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4685 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4686 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4687 "maskmovdqu\t{$mask, $src|$src, $mask}",
4688 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4691 } // ExeDomain = SSEPackedInt
4693 //===---------------------------------------------------------------------===//
4694 // SSE2 - Move Doubleword
4695 //===---------------------------------------------------------------------===//
4697 //===---------------------------------------------------------------------===//
4698 // Move Int Doubleword to Packed Double Int
4700 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4701 "movd\t{$src, $dst|$dst, $src}",
4703 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4704 VEX, Sched<[WriteMove]>;
4705 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4706 "movd\t{$src, $dst|$dst, $src}",
4708 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4710 VEX, Sched<[WriteLoad]>;
4711 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4712 "movq\t{$src, $dst|$dst, $src}",
4714 (v2i64 (scalar_to_vector GR64:$src)))],
4715 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4716 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4717 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4718 "movq\t{$src, $dst|$dst, $src}",
4719 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4720 let isCodeGenOnly = 1 in
4721 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4722 "movq\t{$src, $dst|$dst, $src}",
4723 [(set FR64:$dst, (bitconvert GR64:$src))],
4724 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4726 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4727 "movd\t{$src, $dst|$dst, $src}",
4729 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4731 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4732 "movd\t{$src, $dst|$dst, $src}",
4734 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4735 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4736 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4737 "mov{d|q}\t{$src, $dst|$dst, $src}",
4739 (v2i64 (scalar_to_vector GR64:$src)))],
4740 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4741 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4742 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4743 "mov{d|q}\t{$src, $dst|$dst, $src}",
4744 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4745 let isCodeGenOnly = 1 in
4746 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4747 "mov{d|q}\t{$src, $dst|$dst, $src}",
4748 [(set FR64:$dst, (bitconvert GR64:$src))],
4749 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4751 //===---------------------------------------------------------------------===//
4752 // Move Int Doubleword to Single Scalar
4754 let isCodeGenOnly = 1 in {
4755 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4756 "movd\t{$src, $dst|$dst, $src}",
4757 [(set FR32:$dst, (bitconvert GR32:$src))],
4758 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4760 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4761 "movd\t{$src, $dst|$dst, $src}",
4762 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4764 VEX, Sched<[WriteLoad]>;
4765 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4766 "movd\t{$src, $dst|$dst, $src}",
4767 [(set FR32:$dst, (bitconvert GR32:$src))],
4768 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4770 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4771 "movd\t{$src, $dst|$dst, $src}",
4772 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4773 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4776 //===---------------------------------------------------------------------===//
4777 // Move Packed Doubleword Int to Packed Double Int
4779 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4780 "movd\t{$src, $dst|$dst, $src}",
4781 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4782 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4784 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4785 (ins i32mem:$dst, VR128:$src),
4786 "movd\t{$src, $dst|$dst, $src}",
4787 [(store (i32 (vector_extract (v4i32 VR128:$src),
4788 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4789 VEX, Sched<[WriteStore]>;
4790 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4791 "movd\t{$src, $dst|$dst, $src}",
4792 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4793 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4795 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4796 "movd\t{$src, $dst|$dst, $src}",
4797 [(store (i32 (vector_extract (v4i32 VR128:$src),
4798 (iPTR 0))), addr:$dst)],
4799 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4801 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4802 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4804 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4805 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4807 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4808 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4810 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4811 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4813 //===---------------------------------------------------------------------===//
4814 // Move Packed Doubleword Int first element to Doubleword Int
4816 let SchedRW = [WriteMove] in {
4817 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4818 "movq\t{$src, $dst|$dst, $src}",
4819 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4824 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4825 "mov{d|q}\t{$src, $dst|$dst, $src}",
4826 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4831 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4832 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4833 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4834 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4835 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4836 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4837 "mov{d|q}\t{$src, $dst|$dst, $src}",
4838 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4840 //===---------------------------------------------------------------------===//
4841 // Bitcast FR64 <-> GR64
4843 let isCodeGenOnly = 1 in {
4844 let Predicates = [UseAVX] in
4845 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4846 "movq\t{$src, $dst|$dst, $src}",
4847 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4848 VEX, Sched<[WriteLoad]>;
4849 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4850 "movq\t{$src, $dst|$dst, $src}",
4851 [(set GR64:$dst, (bitconvert FR64:$src))],
4852 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4853 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4854 "movq\t{$src, $dst|$dst, $src}",
4855 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4856 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4858 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4859 "movq\t{$src, $dst|$dst, $src}",
4860 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4861 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4862 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4863 "mov{d|q}\t{$src, $dst|$dst, $src}",
4864 [(set GR64:$dst, (bitconvert FR64:$src))],
4865 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4866 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4867 "movq\t{$src, $dst|$dst, $src}",
4868 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4869 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4872 //===---------------------------------------------------------------------===//
4873 // Move Scalar Single to Double Int
4875 let isCodeGenOnly = 1 in {
4876 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4877 "movd\t{$src, $dst|$dst, $src}",
4878 [(set GR32:$dst, (bitconvert FR32:$src))],
4879 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4880 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4881 "movd\t{$src, $dst|$dst, $src}",
4882 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4883 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4884 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4885 "movd\t{$src, $dst|$dst, $src}",
4886 [(set GR32:$dst, (bitconvert FR32:$src))],
4887 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4888 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4889 "movd\t{$src, $dst|$dst, $src}",
4890 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4891 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4894 //===---------------------------------------------------------------------===//
4895 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4897 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4898 let AddedComplexity = 15 in {
4899 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4900 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4901 [(set VR128:$dst, (v2i64 (X86vzmovl
4902 (v2i64 (scalar_to_vector GR64:$src)))))],
4905 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4906 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4907 [(set VR128:$dst, (v2i64 (X86vzmovl
4908 (v2i64 (scalar_to_vector GR64:$src)))))],
4911 } // isCodeGenOnly, SchedRW
4913 let Predicates = [UseAVX] in {
4914 let AddedComplexity = 15 in
4915 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4916 (VMOVDI2PDIrr GR32:$src)>;
4918 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4919 // These instructions also write zeros in the high part of a 256-bit register.
4920 let AddedComplexity = 20 in {
4921 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4922 (VMOVDI2PDIrm addr:$src)>;
4923 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4924 (VMOVDI2PDIrm addr:$src)>;
4925 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4926 (VMOVDI2PDIrm addr:$src)>;
4927 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4928 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4929 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4931 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4932 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4933 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4934 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4935 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4936 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4937 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4940 let Predicates = [UseSSE2] in {
4941 let AddedComplexity = 15 in
4942 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4943 (MOVDI2PDIrr GR32:$src)>;
4945 let AddedComplexity = 20 in {
4946 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4947 (MOVDI2PDIrm addr:$src)>;
4948 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4949 (MOVDI2PDIrm addr:$src)>;
4950 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4951 (MOVDI2PDIrm addr:$src)>;
4955 // These are the correct encodings of the instructions so that we know how to
4956 // read correct assembly, even though we continue to emit the wrong ones for
4957 // compatibility with Darwin's buggy assembler.
4958 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4959 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4960 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4961 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4962 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4963 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4964 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4965 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4966 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4968 //===---------------------------------------------------------------------===//
4969 // SSE2 - Move Quadword
4970 //===---------------------------------------------------------------------===//
4972 //===---------------------------------------------------------------------===//
4973 // Move Quadword Int to Packed Quadword Int
4976 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4977 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4978 "vmovq\t{$src, $dst|$dst, $src}",
4980 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4981 VEX, Requires<[UseAVX]>;
4982 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4983 "movq\t{$src, $dst|$dst, $src}",
4985 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4987 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4988 } // ExeDomain, SchedRW
4990 //===---------------------------------------------------------------------===//
4991 // Move Packed Quadword Int to Quadword Int
4993 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4994 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4995 "movq\t{$src, $dst|$dst, $src}",
4996 [(store (i64 (vector_extract (v2i64 VR128:$src),
4997 (iPTR 0))), addr:$dst)],
4998 IIC_SSE_MOVDQ>, VEX;
4999 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5000 "movq\t{$src, $dst|$dst, $src}",
5001 [(store (i64 (vector_extract (v2i64 VR128:$src),
5002 (iPTR 0))), addr:$dst)],
5004 } // ExeDomain, SchedRW
5006 // For disassembler only
5007 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5008 SchedRW = [WriteVecLogic] in {
5009 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5010 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5011 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5012 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5015 //===---------------------------------------------------------------------===//
5016 // Store / copy lower 64-bits of a XMM register.
5018 let Predicates = [HasAVX] in
5019 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5020 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5021 let Predicates = [UseSSE2] in
5022 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5023 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5025 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5026 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5027 "vmovq\t{$src, $dst|$dst, $src}",
5029 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5030 (loadi64 addr:$src))))))],
5032 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5034 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5035 "movq\t{$src, $dst|$dst, $src}",
5037 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5038 (loadi64 addr:$src))))))],
5040 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5041 } // ExeDomain, isCodeGenOnly, AddedComplexity
5043 let Predicates = [UseAVX], AddedComplexity = 20 in {
5044 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5045 (VMOVZQI2PQIrm addr:$src)>;
5046 def : Pat<(v2i64 (X86vzload addr:$src)),
5047 (VMOVZQI2PQIrm addr:$src)>;
5048 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5049 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5050 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5053 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5054 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5055 (MOVZQI2PQIrm addr:$src)>;
5056 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5059 let Predicates = [HasAVX] in {
5060 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5061 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5062 def : Pat<(v4i64 (X86vzload addr:$src)),
5063 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5066 //===---------------------------------------------------------------------===//
5067 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5068 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5070 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5071 let AddedComplexity = 15 in
5072 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5073 "vmovq\t{$src, $dst|$dst, $src}",
5074 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5076 XS, VEX, Requires<[UseAVX]>;
5077 let AddedComplexity = 15 in
5078 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5079 "movq\t{$src, $dst|$dst, $src}",
5080 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5082 XS, Requires<[UseSSE2]>;
5083 } // ExeDomain, SchedRW
5085 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5086 let AddedComplexity = 20 in
5087 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5088 "vmovq\t{$src, $dst|$dst, $src}",
5089 [(set VR128:$dst, (v2i64 (X86vzmovl
5090 (loadv2i64 addr:$src))))],
5092 XS, VEX, Requires<[UseAVX]>;
5093 let AddedComplexity = 20 in {
5094 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5095 "movq\t{$src, $dst|$dst, $src}",
5096 [(set VR128:$dst, (v2i64 (X86vzmovl
5097 (loadv2i64 addr:$src))))],
5099 XS, Requires<[UseSSE2]>;
5101 } // ExeDomain, isCodeGenOnly, SchedRW
5103 let AddedComplexity = 20 in {
5104 let Predicates = [UseAVX] in {
5105 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5106 (VMOVZPQILo2PQIrr VR128:$src)>;
5108 let Predicates = [UseSSE2] in {
5109 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5110 (MOVZPQILo2PQIrr VR128:$src)>;
5114 //===---------------------------------------------------------------------===//
5115 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5116 //===---------------------------------------------------------------------===//
5117 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5118 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5119 X86MemOperand x86memop> {
5120 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5121 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5122 [(set RC:$dst, (vt (OpNode RC:$src)))],
5123 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5124 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5125 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5126 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5127 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5130 let Predicates = [HasAVX] in {
5131 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5132 v4f32, VR128, loadv4f32, f128mem>, VEX;
5133 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5134 v4f32, VR128, loadv4f32, f128mem>, VEX;
5135 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5136 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5137 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5138 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5140 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5141 memopv4f32, f128mem>;
5142 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5143 memopv4f32, f128mem>;
5145 let Predicates = [HasAVX] in {
5146 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5147 (VMOVSHDUPrr VR128:$src)>;
5148 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5149 (VMOVSHDUPrm addr:$src)>;
5150 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5151 (VMOVSLDUPrr VR128:$src)>;
5152 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5153 (VMOVSLDUPrm addr:$src)>;
5154 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5155 (VMOVSHDUPYrr VR256:$src)>;
5156 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5157 (VMOVSHDUPYrm addr:$src)>;
5158 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5159 (VMOVSLDUPYrr VR256:$src)>;
5160 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5161 (VMOVSLDUPYrm addr:$src)>;
5164 let Predicates = [UseSSE3] in {
5165 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5166 (MOVSHDUPrr VR128:$src)>;
5167 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5168 (MOVSHDUPrm addr:$src)>;
5169 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5170 (MOVSLDUPrr VR128:$src)>;
5171 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5172 (MOVSLDUPrm addr:$src)>;
5175 //===---------------------------------------------------------------------===//
5176 // SSE3 - Replicate Double FP - MOVDDUP
5177 //===---------------------------------------------------------------------===//
5179 multiclass sse3_replicate_dfp<string OpcodeStr> {
5180 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5182 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5183 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5184 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5185 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5188 (scalar_to_vector (loadf64 addr:$src)))))],
5189 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5192 // FIXME: Merge with above classe when there're patterns for the ymm version
5193 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5194 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5195 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5196 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5197 Sched<[WriteFShuffle]>;
5198 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5199 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5202 (scalar_to_vector (loadf64 addr:$src)))))]>,
5206 let Predicates = [HasAVX] in {
5207 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5208 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5211 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5213 let Predicates = [HasAVX] in {
5214 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5215 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5216 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5217 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5218 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5219 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5220 def : Pat<(X86Movddup (bc_v2f64
5221 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5222 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5225 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5226 (VMOVDDUPYrm addr:$src)>;
5227 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5228 (VMOVDDUPYrm addr:$src)>;
5229 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5230 (VMOVDDUPYrm addr:$src)>;
5231 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5232 (VMOVDDUPYrr VR256:$src)>;
5235 let Predicates = [UseAVX, OptForSize] in {
5236 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5237 (VMOVDDUPrm addr:$src)>;
5238 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5239 (VMOVDDUPrm addr:$src)>;
5242 let Predicates = [UseSSE3] in {
5243 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5244 (MOVDDUPrm addr:$src)>;
5245 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5246 (MOVDDUPrm addr:$src)>;
5247 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5248 (MOVDDUPrm addr:$src)>;
5249 def : Pat<(X86Movddup (bc_v2f64
5250 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5251 (MOVDDUPrm addr:$src)>;
5254 //===---------------------------------------------------------------------===//
5255 // SSE3 - Move Unaligned Integer
5256 //===---------------------------------------------------------------------===//
5258 let SchedRW = [WriteLoad] in {
5259 let Predicates = [HasAVX] in {
5260 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5261 "vlddqu\t{$src, $dst|$dst, $src}",
5262 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5263 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5264 "vlddqu\t{$src, $dst|$dst, $src}",
5265 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5268 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5269 "lddqu\t{$src, $dst|$dst, $src}",
5270 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5274 //===---------------------------------------------------------------------===//
5275 // SSE3 - Arithmetic
5276 //===---------------------------------------------------------------------===//
5278 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5279 X86MemOperand x86memop, OpndItins itins,
5280 PatFrag ld_frag, bit Is2Addr = 1> {
5281 def rr : I<0xD0, MRMSrcReg,
5282 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5285 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5286 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5287 Sched<[itins.Sched]>;
5288 def rm : I<0xD0, MRMSrcMem,
5289 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5291 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5292 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5293 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5294 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5297 let Predicates = [HasAVX] in {
5298 let ExeDomain = SSEPackedSingle in {
5299 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5300 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5301 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5302 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5304 let ExeDomain = SSEPackedDouble in {
5305 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5306 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5307 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5308 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5311 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5312 let ExeDomain = SSEPackedSingle in
5313 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5314 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5315 let ExeDomain = SSEPackedDouble in
5316 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5317 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5320 // Patterns used to select 'addsub' instructions.
5321 let Predicates = [HasAVX] in {
5322 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5323 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5324 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5325 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5326 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5327 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5328 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5329 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5331 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5332 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5333 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5334 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5335 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5336 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5337 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5338 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5341 let Predicates = [UseSSE3] in {
5342 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5343 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5344 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5345 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5346 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5347 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5348 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5349 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5352 //===---------------------------------------------------------------------===//
5353 // SSE3 Instructions
5354 //===---------------------------------------------------------------------===//
5357 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5358 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5360 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5364 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5367 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5371 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5372 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5374 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5375 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5377 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5381 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5384 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5386 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5388 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5389 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5392 let Predicates = [HasAVX] in {
5393 let ExeDomain = SSEPackedSingle in {
5394 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5395 X86fhadd, loadv4f32, 0>, VEX_4V;
5396 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5397 X86fhsub, loadv4f32, 0>, VEX_4V;
5398 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5399 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5400 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5401 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5403 let ExeDomain = SSEPackedDouble in {
5404 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5405 X86fhadd, loadv2f64, 0>, VEX_4V;
5406 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5407 X86fhsub, loadv2f64, 0>, VEX_4V;
5408 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5409 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5410 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5411 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5415 let Constraints = "$src1 = $dst" in {
5416 let ExeDomain = SSEPackedSingle in {
5417 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5419 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5422 let ExeDomain = SSEPackedDouble in {
5423 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5425 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5430 //===---------------------------------------------------------------------===//
5431 // SSSE3 - Packed Absolute Instructions
5432 //===---------------------------------------------------------------------===//
5435 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5436 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5438 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5441 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5442 Sched<[WriteVecALU]>;
5444 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5446 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5449 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5450 Sched<[WriteVecALULd]>;
5453 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5454 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5455 Intrinsic IntId256> {
5456 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5458 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5459 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5460 Sched<[WriteVecALU]>;
5462 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5464 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5467 (bitconvert (loadv4i64 addr:$src))))]>,
5468 Sched<[WriteVecALULd]>;
5471 // Helper fragments to match sext vXi1 to vXiY.
5472 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5474 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5475 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5476 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5478 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5479 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5481 let Predicates = [HasAVX] in {
5482 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5484 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5486 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5490 (bc_v2i64 (v16i1sextv16i8)),
5491 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5492 (VPABSBrr128 VR128:$src)>;
5494 (bc_v2i64 (v8i1sextv8i16)),
5495 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5496 (VPABSWrr128 VR128:$src)>;
5498 (bc_v2i64 (v4i1sextv4i32)),
5499 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5500 (VPABSDrr128 VR128:$src)>;
5503 let Predicates = [HasAVX2] in {
5504 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5505 int_x86_avx2_pabs_b>, VEX, VEX_L;
5506 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5507 int_x86_avx2_pabs_w>, VEX, VEX_L;
5508 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5509 int_x86_avx2_pabs_d>, VEX, VEX_L;
5512 (bc_v4i64 (v32i1sextv32i8)),
5513 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5514 (VPABSBrr256 VR256:$src)>;
5516 (bc_v4i64 (v16i1sextv16i16)),
5517 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5518 (VPABSWrr256 VR256:$src)>;
5520 (bc_v4i64 (v8i1sextv8i32)),
5521 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5522 (VPABSDrr256 VR256:$src)>;
5525 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5527 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5529 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5532 let Predicates = [HasSSSE3] in {
5534 (bc_v2i64 (v16i1sextv16i8)),
5535 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5536 (PABSBrr128 VR128:$src)>;
5538 (bc_v2i64 (v8i1sextv8i16)),
5539 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5540 (PABSWrr128 VR128:$src)>;
5542 (bc_v2i64 (v4i1sextv4i32)),
5543 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5544 (PABSDrr128 VR128:$src)>;
5547 //===---------------------------------------------------------------------===//
5548 // SSSE3 - Packed Binary Operator Instructions
5549 //===---------------------------------------------------------------------===//
5551 let Sched = WriteVecALU in {
5552 def SSE_PHADDSUBD : OpndItins<
5553 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5555 def SSE_PHADDSUBSW : OpndItins<
5556 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5558 def SSE_PHADDSUBW : OpndItins<
5559 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5562 let Sched = WriteShuffle in
5563 def SSE_PSHUFB : OpndItins<
5564 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5566 let Sched = WriteVecALU in
5567 def SSE_PSIGN : OpndItins<
5568 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5570 let Sched = WriteVecIMul in
5571 def SSE_PMULHRSW : OpndItins<
5572 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5575 /// SS3I_binop_rm - Simple SSSE3 bin op
5576 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5577 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5578 X86MemOperand x86memop, OpndItins itins,
5580 let isCommutable = 1 in
5581 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5582 (ins RC:$src1, RC:$src2),
5584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5585 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5586 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5587 Sched<[itins.Sched]>;
5588 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5589 (ins RC:$src1, x86memop:$src2),
5591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5594 (OpVT (OpNode RC:$src1,
5595 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5596 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5599 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5600 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5601 Intrinsic IntId128, OpndItins itins,
5602 PatFrag ld_frag, bit Is2Addr = 1> {
5603 let isCommutable = 1 in
5604 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5605 (ins VR128:$src1, VR128:$src2),
5607 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5608 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5609 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5610 Sched<[itins.Sched]>;
5611 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5612 (ins VR128:$src1, i128mem:$src2),
5614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5617 (IntId128 VR128:$src1,
5618 (bitconvert (ld_frag addr:$src2))))]>,
5619 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5622 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5624 X86FoldableSchedWrite Sched> {
5625 let isCommutable = 1 in
5626 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5627 (ins VR256:$src1, VR256:$src2),
5628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5629 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5631 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5632 (ins VR256:$src1, i256mem:$src2),
5633 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5635 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5636 Sched<[Sched.Folded, ReadAfterLd]>;
5639 let ImmT = NoImm, Predicates = [HasAVX] in {
5640 let isCommutable = 0 in {
5641 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5643 SSE_PHADDSUBW, 0>, VEX_4V;
5644 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5646 SSE_PHADDSUBD, 0>, VEX_4V;
5647 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5649 SSE_PHADDSUBW, 0>, VEX_4V;
5650 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5652 SSE_PHADDSUBD, 0>, VEX_4V;
5653 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5655 SSE_PSIGN, 0>, VEX_4V;
5656 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5658 SSE_PSIGN, 0>, VEX_4V;
5659 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5661 SSE_PSIGN, 0>, VEX_4V;
5662 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5664 SSE_PSHUFB, 0>, VEX_4V;
5665 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5666 int_x86_ssse3_phadd_sw_128,
5667 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5668 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5669 int_x86_ssse3_phsub_sw_128,
5670 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5671 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5672 int_x86_ssse3_pmadd_ub_sw_128,
5673 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5675 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5676 int_x86_ssse3_pmul_hr_sw_128,
5677 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5680 let ImmT = NoImm, Predicates = [HasAVX2] in {
5681 let isCommutable = 0 in {
5682 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5684 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5685 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5687 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5688 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5690 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5691 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5693 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5694 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5696 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5697 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5699 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5700 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5702 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5703 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5705 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5706 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5707 int_x86_avx2_phadd_sw,
5708 WriteVecALU>, VEX_4V, VEX_L;
5709 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5710 int_x86_avx2_phsub_sw,
5711 WriteVecALU>, VEX_4V, VEX_L;
5712 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5713 int_x86_avx2_pmadd_ub_sw,
5714 WriteVecIMul>, VEX_4V, VEX_L;
5716 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5717 int_x86_avx2_pmul_hr_sw,
5718 WriteVecIMul>, VEX_4V, VEX_L;
5721 // None of these have i8 immediate fields.
5722 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5723 let isCommutable = 0 in {
5724 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5725 memopv2i64, i128mem, SSE_PHADDSUBW>;
5726 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5727 memopv2i64, i128mem, SSE_PHADDSUBD>;
5728 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5729 memopv2i64, i128mem, SSE_PHADDSUBW>;
5730 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5731 memopv2i64, i128mem, SSE_PHADDSUBD>;
5732 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5733 memopv2i64, i128mem, SSE_PSIGN>;
5734 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5735 memopv2i64, i128mem, SSE_PSIGN>;
5736 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5737 memopv2i64, i128mem, SSE_PSIGN>;
5738 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5739 memopv2i64, i128mem, SSE_PSHUFB>;
5740 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5741 int_x86_ssse3_phadd_sw_128,
5742 SSE_PHADDSUBSW, memopv2i64>;
5743 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5744 int_x86_ssse3_phsub_sw_128,
5745 SSE_PHADDSUBSW, memopv2i64>;
5746 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5747 int_x86_ssse3_pmadd_ub_sw_128,
5748 SSE_PMADD, memopv2i64>;
5750 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5751 int_x86_ssse3_pmul_hr_sw_128,
5752 SSE_PMULHRSW, memopv2i64>;
5755 //===---------------------------------------------------------------------===//
5756 // SSSE3 - Packed Align Instruction Patterns
5757 //===---------------------------------------------------------------------===//
5759 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5760 let hasSideEffects = 0 in {
5761 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5762 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5764 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5766 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5767 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5769 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5770 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5772 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5774 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5775 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5779 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5780 let hasSideEffects = 0 in {
5781 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5782 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5784 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5785 []>, Sched<[WriteShuffle]>;
5787 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5788 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5790 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5791 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5795 let Predicates = [HasAVX] in
5796 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5797 let Predicates = [HasAVX2] in
5798 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5799 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5800 defm PALIGN : ssse3_palignr<"palignr">;
5802 let Predicates = [HasAVX2] in {
5803 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5804 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5805 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5806 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5807 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5808 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5809 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5810 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5813 let Predicates = [HasAVX] in {
5814 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5815 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5816 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5817 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5818 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5819 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5820 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5821 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5824 let Predicates = [UseSSSE3] in {
5825 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5826 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5827 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5828 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5829 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5830 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5831 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5832 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5835 //===---------------------------------------------------------------------===//
5836 // SSSE3 - Thread synchronization
5837 //===---------------------------------------------------------------------===//
5839 let SchedRW = [WriteSystem] in {
5840 let usesCustomInserter = 1 in {
5841 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5842 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5843 Requires<[HasSSE3]>;
5846 let Uses = [EAX, ECX, EDX] in
5847 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5848 TB, Requires<[HasSSE3]>;
5849 let Uses = [ECX, EAX] in
5850 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5851 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5852 TB, Requires<[HasSSE3]>;
5855 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5856 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5858 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5859 Requires<[Not64BitMode]>;
5860 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5861 Requires<[In64BitMode]>;
5863 //===----------------------------------------------------------------------===//
5864 // SSE4.1 - Packed Move with Sign/Zero Extend
5865 //===----------------------------------------------------------------------===//
5867 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5868 RegisterClass OutRC, RegisterClass InRC,
5870 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5871 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5873 Sched<[itins.Sched]>;
5875 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5878 itins.rm>, Sched<[itins.Sched.Folded]>;
5881 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5882 X86MemOperand MemOp, X86MemOperand MemYOp,
5883 OpndItins SSEItins, OpndItins AVXItins,
5884 OpndItins AVX2Itins> {
5885 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5886 let Predicates = [HasAVX, NoVLX] in
5887 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5888 VR128, VR128, AVXItins>, VEX;
5889 let Predicates = [HasAVX2, NoVLX] in
5890 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5891 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5894 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5895 X86MemOperand MemOp, X86MemOperand MemYOp> {
5896 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5898 SSE_INTALU_ITINS_SHUFF_P,
5899 DEFAULT_ITINS_SHUFFLESCHED,
5900 DEFAULT_ITINS_SHUFFLESCHED>;
5901 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5902 !strconcat("pmovzx", OpcodeStr),
5904 SSE_INTALU_ITINS_SHUFF_P,
5905 DEFAULT_ITINS_SHUFFLESCHED,
5906 DEFAULT_ITINS_SHUFFLESCHED>;
5909 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5910 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5911 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5913 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5914 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5916 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5919 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5920 // Register-Register patterns
5921 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5922 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5923 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5924 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5925 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5926 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5928 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5929 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5930 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5931 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5933 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5934 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5936 // On AVX2, we also support 256bit inputs.
5937 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5938 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5939 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5940 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5941 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5942 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5944 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5945 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5946 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5947 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5949 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5950 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5952 // Simple Register-Memory patterns
5953 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5954 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5955 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5956 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5957 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5958 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5960 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5961 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5962 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5963 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5965 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5966 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5968 // AVX2 Register-Memory patterns
5969 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5970 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5971 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5972 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5973 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5974 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5975 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5978 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5979 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5980 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5981 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5982 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5983 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5984 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5987 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5988 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5989 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5990 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5991 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5992 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5994 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5996 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5997 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5998 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5999 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6000 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6001 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6002 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6003 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6005 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6006 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6007 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6008 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6009 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6010 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6011 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6012 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6014 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6015 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6016 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6017 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6018 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6019 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6020 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6021 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6024 let Predicates = [HasAVX2, NoVLX] in {
6025 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6026 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6029 // SSE4.1/AVX patterns.
6030 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6031 SDNode ExtOp, PatFrag ExtLoad16> {
6032 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6033 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6034 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6035 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6036 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6037 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6039 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6040 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6041 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6042 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6044 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6045 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6047 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6048 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6049 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6050 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6051 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6052 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6054 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6055 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6056 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6057 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6059 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6060 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6062 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6063 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6064 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6065 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6066 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6067 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6068 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6069 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6070 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6071 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6073 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6074 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6075 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6076 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6077 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6078 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6079 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6080 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6082 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6083 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6084 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6085 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6086 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6087 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6088 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6089 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6091 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6092 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6093 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6094 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6095 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6096 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6097 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6098 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6099 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6100 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6102 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6103 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6104 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6105 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6106 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6107 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6108 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6109 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6111 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6112 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6113 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6114 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6115 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6116 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6117 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6118 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6119 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6120 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6123 let Predicates = [HasAVX, NoVLX] in {
6124 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6125 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6128 let Predicates = [UseSSE41] in {
6129 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6130 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6133 //===----------------------------------------------------------------------===//
6134 // SSE4.1 - Extract Instructions
6135 //===----------------------------------------------------------------------===//
6137 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6138 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6139 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6140 (ins VR128:$src1, u8imm:$src2),
6141 !strconcat(OpcodeStr,
6142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6143 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6145 Sched<[WriteShuffle]>;
6146 let hasSideEffects = 0, mayStore = 1,
6147 SchedRW = [WriteShuffleLd, WriteRMW] in
6148 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6149 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6150 !strconcat(OpcodeStr,
6151 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6152 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6153 imm:$src2)))), addr:$dst)]>;
6156 let Predicates = [HasAVX] in
6157 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6159 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6162 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6163 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6164 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6165 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6166 (ins VR128:$src1, u8imm:$src2),
6167 !strconcat(OpcodeStr,
6168 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6169 []>, Sched<[WriteShuffle]>;
6171 let hasSideEffects = 0, mayStore = 1,
6172 SchedRW = [WriteShuffleLd, WriteRMW] in
6173 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6174 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6175 !strconcat(OpcodeStr,
6176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6177 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6178 imm:$src2)))), addr:$dst)]>;
6181 let Predicates = [HasAVX] in
6182 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6184 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6187 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6188 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6189 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6190 (ins VR128:$src1, u8imm:$src2),
6191 !strconcat(OpcodeStr,
6192 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6194 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6195 Sched<[WriteShuffle]>;
6196 let SchedRW = [WriteShuffleLd, WriteRMW] in
6197 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6198 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6199 !strconcat(OpcodeStr,
6200 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6201 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6205 let Predicates = [HasAVX] in
6206 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6208 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6210 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6211 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6212 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6213 (ins VR128:$src1, u8imm:$src2),
6214 !strconcat(OpcodeStr,
6215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6217 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6218 Sched<[WriteShuffle]>, REX_W;
6219 let SchedRW = [WriteShuffleLd, WriteRMW] in
6220 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6221 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6222 !strconcat(OpcodeStr,
6223 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6224 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6225 addr:$dst)]>, REX_W;
6228 let Predicates = [HasAVX] in
6229 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6231 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6233 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6235 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6236 OpndItins itins = DEFAULT_ITINS> {
6237 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6238 (ins VR128:$src1, u8imm:$src2),
6239 !strconcat(OpcodeStr,
6240 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6241 [(set GR32orGR64:$dst,
6242 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6243 itins.rr>, Sched<[WriteFBlend]>;
6244 let SchedRW = [WriteFBlendLd, WriteRMW] in
6245 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6246 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6247 !strconcat(OpcodeStr,
6248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6249 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6250 addr:$dst)], itins.rm>;
6253 let ExeDomain = SSEPackedSingle in {
6254 let Predicates = [UseAVX] in
6255 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6256 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6259 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6260 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6263 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6265 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6268 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6269 Requires<[UseSSE41]>;
6271 //===----------------------------------------------------------------------===//
6272 // SSE4.1 - Insert Instructions
6273 //===----------------------------------------------------------------------===//
6275 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6276 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6277 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6279 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6281 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6283 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6284 Sched<[WriteShuffle]>;
6285 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6286 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6288 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6290 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6292 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6293 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6296 let Predicates = [HasAVX] in
6297 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6298 let Constraints = "$src1 = $dst" in
6299 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6301 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6302 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6303 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6305 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6307 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6309 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6310 Sched<[WriteShuffle]>;
6311 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6312 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6314 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6316 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6318 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6319 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6322 let Predicates = [HasAVX] in
6323 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6324 let Constraints = "$src1 = $dst" in
6325 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6327 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6328 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6329 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6331 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6333 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6335 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6336 Sched<[WriteShuffle]>;
6337 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6338 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6340 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6342 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6344 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6345 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6348 let Predicates = [HasAVX] in
6349 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6350 let Constraints = "$src1 = $dst" in
6351 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6353 // insertps has a few different modes, there's the first two here below which
6354 // are optimized inserts that won't zero arbitrary elements in the destination
6355 // vector. The next one matches the intrinsic and could zero arbitrary elements
6356 // in the target vector.
6357 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6358 OpndItins itins = DEFAULT_ITINS> {
6359 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6360 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6362 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6366 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6367 Sched<[WriteFShuffle]>;
6368 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6369 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6371 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6375 (X86insertps VR128:$src1,
6376 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6377 imm:$src3))], itins.rm>,
6378 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6381 let ExeDomain = SSEPackedSingle in {
6382 let Predicates = [UseAVX] in
6383 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6384 let Constraints = "$src1 = $dst" in
6385 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6388 let Predicates = [UseSSE41] in {
6389 // If we're inserting an element from a load or a null pshuf of a load,
6390 // fold the load into the insertps instruction.
6391 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6392 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6394 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6395 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6396 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6397 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6400 let Predicates = [UseAVX] in {
6401 // If we're inserting an element from a vbroadcast of a load, fold the
6402 // load into the X86insertps instruction.
6403 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6404 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6405 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6406 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6407 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6408 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6411 //===----------------------------------------------------------------------===//
6412 // SSE4.1 - Round Instructions
6413 //===----------------------------------------------------------------------===//
6415 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6416 X86MemOperand x86memop, RegisterClass RC,
6417 PatFrag mem_frag32, PatFrag mem_frag64,
6418 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6419 let ExeDomain = SSEPackedSingle in {
6420 // Intrinsic operation, reg.
6421 // Vector intrinsic operation, reg
6422 def PSr : SS4AIi8<opcps, MRMSrcReg,
6423 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6424 !strconcat(OpcodeStr,
6425 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6426 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6427 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6429 // Vector intrinsic operation, mem
6430 def PSm : SS4AIi8<opcps, MRMSrcMem,
6431 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6432 !strconcat(OpcodeStr,
6433 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6435 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6436 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6437 } // ExeDomain = SSEPackedSingle
6439 let ExeDomain = SSEPackedDouble in {
6440 // Vector intrinsic operation, reg
6441 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6442 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6443 !strconcat(OpcodeStr,
6444 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6445 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6446 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6448 // Vector intrinsic operation, mem
6449 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6450 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6451 !strconcat(OpcodeStr,
6452 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6454 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6455 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6456 } // ExeDomain = SSEPackedDouble
6459 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6462 Intrinsic F64Int, bit Is2Addr = 1> {
6463 let ExeDomain = GenericDomain in {
6465 let hasSideEffects = 0 in
6466 def SSr : SS4AIi8<opcss, MRMSrcReg,
6467 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6469 !strconcat(OpcodeStr,
6470 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6471 !strconcat(OpcodeStr,
6472 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6473 []>, Sched<[WriteFAdd]>;
6475 // Intrinsic operation, reg.
6476 let isCodeGenOnly = 1 in
6477 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6478 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6480 !strconcat(OpcodeStr,
6481 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6482 !strconcat(OpcodeStr,
6483 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6484 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6487 // Intrinsic operation, mem.
6488 def SSm : SS4AIi8<opcss, MRMSrcMem,
6489 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6491 !strconcat(OpcodeStr,
6492 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6493 !strconcat(OpcodeStr,
6494 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6496 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6497 Sched<[WriteFAddLd, ReadAfterLd]>;
6500 let hasSideEffects = 0 in
6501 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6502 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6504 !strconcat(OpcodeStr,
6505 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6506 !strconcat(OpcodeStr,
6507 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6508 []>, Sched<[WriteFAdd]>;
6510 // Intrinsic operation, reg.
6511 let isCodeGenOnly = 1 in
6512 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6513 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6515 !strconcat(OpcodeStr,
6516 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6517 !strconcat(OpcodeStr,
6518 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6519 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6522 // Intrinsic operation, mem.
6523 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6524 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6526 !strconcat(OpcodeStr,
6527 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6528 !strconcat(OpcodeStr,
6529 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6531 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6532 Sched<[WriteFAddLd, ReadAfterLd]>;
6533 } // ExeDomain = GenericDomain
6536 // FP round - roundss, roundps, roundsd, roundpd
6537 let Predicates = [HasAVX] in {
6539 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6540 loadv4f32, loadv2f64,
6541 int_x86_sse41_round_ps,
6542 int_x86_sse41_round_pd>, VEX;
6543 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6544 loadv8f32, loadv4f64,
6545 int_x86_avx_round_ps_256,
6546 int_x86_avx_round_pd_256>, VEX, VEX_L;
6547 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6548 int_x86_sse41_round_ss,
6549 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6552 let Predicates = [UseAVX] in {
6553 def : Pat<(ffloor FR32:$src),
6554 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6555 def : Pat<(f64 (ffloor FR64:$src)),
6556 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6557 def : Pat<(f32 (fnearbyint FR32:$src)),
6558 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6559 def : Pat<(f64 (fnearbyint FR64:$src)),
6560 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6561 def : Pat<(f32 (fceil FR32:$src)),
6562 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6563 def : Pat<(f64 (fceil FR64:$src)),
6564 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6565 def : Pat<(f32 (frint FR32:$src)),
6566 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6567 def : Pat<(f64 (frint FR64:$src)),
6568 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6569 def : Pat<(f32 (ftrunc FR32:$src)),
6570 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6571 def : Pat<(f64 (ftrunc FR64:$src)),
6572 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6575 let Predicates = [HasAVX] in {
6576 def : Pat<(v4f32 (ffloor VR128:$src)),
6577 (VROUNDPSr VR128:$src, (i32 0x1))>;
6578 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6579 (VROUNDPSr VR128:$src, (i32 0xC))>;
6580 def : Pat<(v4f32 (fceil VR128:$src)),
6581 (VROUNDPSr VR128:$src, (i32 0x2))>;
6582 def : Pat<(v4f32 (frint VR128:$src)),
6583 (VROUNDPSr VR128:$src, (i32 0x4))>;
6584 def : Pat<(v4f32 (ftrunc VR128:$src)),
6585 (VROUNDPSr VR128:$src, (i32 0x3))>;
6587 def : Pat<(v2f64 (ffloor VR128:$src)),
6588 (VROUNDPDr VR128:$src, (i32 0x1))>;
6589 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6590 (VROUNDPDr VR128:$src, (i32 0xC))>;
6591 def : Pat<(v2f64 (fceil VR128:$src)),
6592 (VROUNDPDr VR128:$src, (i32 0x2))>;
6593 def : Pat<(v2f64 (frint VR128:$src)),
6594 (VROUNDPDr VR128:$src, (i32 0x4))>;
6595 def : Pat<(v2f64 (ftrunc VR128:$src)),
6596 (VROUNDPDr VR128:$src, (i32 0x3))>;
6598 def : Pat<(v8f32 (ffloor VR256:$src)),
6599 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6600 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6601 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6602 def : Pat<(v8f32 (fceil VR256:$src)),
6603 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6604 def : Pat<(v8f32 (frint VR256:$src)),
6605 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6606 def : Pat<(v8f32 (ftrunc VR256:$src)),
6607 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6609 def : Pat<(v4f64 (ffloor VR256:$src)),
6610 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6611 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6612 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6613 def : Pat<(v4f64 (fceil VR256:$src)),
6614 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6615 def : Pat<(v4f64 (frint VR256:$src)),
6616 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6617 def : Pat<(v4f64 (ftrunc VR256:$src)),
6618 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6621 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6622 memopv4f32, memopv2f64,
6623 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6624 let Constraints = "$src1 = $dst" in
6625 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6626 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6628 let Predicates = [UseSSE41] in {
6629 def : Pat<(ffloor FR32:$src),
6630 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6631 def : Pat<(f64 (ffloor FR64:$src)),
6632 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6633 def : Pat<(f32 (fnearbyint FR32:$src)),
6634 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6635 def : Pat<(f64 (fnearbyint FR64:$src)),
6636 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6637 def : Pat<(f32 (fceil FR32:$src)),
6638 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6639 def : Pat<(f64 (fceil FR64:$src)),
6640 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6641 def : Pat<(f32 (frint FR32:$src)),
6642 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6643 def : Pat<(f64 (frint FR64:$src)),
6644 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6645 def : Pat<(f32 (ftrunc FR32:$src)),
6646 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6647 def : Pat<(f64 (ftrunc FR64:$src)),
6648 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6650 def : Pat<(v4f32 (ffloor VR128:$src)),
6651 (ROUNDPSr VR128:$src, (i32 0x1))>;
6652 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6653 (ROUNDPSr VR128:$src, (i32 0xC))>;
6654 def : Pat<(v4f32 (fceil VR128:$src)),
6655 (ROUNDPSr VR128:$src, (i32 0x2))>;
6656 def : Pat<(v4f32 (frint VR128:$src)),
6657 (ROUNDPSr VR128:$src, (i32 0x4))>;
6658 def : Pat<(v4f32 (ftrunc VR128:$src)),
6659 (ROUNDPSr VR128:$src, (i32 0x3))>;
6661 def : Pat<(v2f64 (ffloor VR128:$src)),
6662 (ROUNDPDr VR128:$src, (i32 0x1))>;
6663 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6664 (ROUNDPDr VR128:$src, (i32 0xC))>;
6665 def : Pat<(v2f64 (fceil VR128:$src)),
6666 (ROUNDPDr VR128:$src, (i32 0x2))>;
6667 def : Pat<(v2f64 (frint VR128:$src)),
6668 (ROUNDPDr VR128:$src, (i32 0x4))>;
6669 def : Pat<(v2f64 (ftrunc VR128:$src)),
6670 (ROUNDPDr VR128:$src, (i32 0x3))>;
6673 //===----------------------------------------------------------------------===//
6674 // SSE4.1 - Packed Bit Test
6675 //===----------------------------------------------------------------------===//
6677 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6678 // the intel intrinsic that corresponds to this.
6679 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6680 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6681 "vptest\t{$src2, $src1|$src1, $src2}",
6682 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6683 Sched<[WriteVecLogic]>, VEX;
6684 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6685 "vptest\t{$src2, $src1|$src1, $src2}",
6686 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6687 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6689 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6690 "vptest\t{$src2, $src1|$src1, $src2}",
6691 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6692 Sched<[WriteVecLogic]>, VEX, VEX_L;
6693 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6694 "vptest\t{$src2, $src1|$src1, $src2}",
6695 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6696 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6699 let Defs = [EFLAGS] in {
6700 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6701 "ptest\t{$src2, $src1|$src1, $src2}",
6702 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6703 Sched<[WriteVecLogic]>;
6704 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6705 "ptest\t{$src2, $src1|$src1, $src2}",
6706 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6707 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6710 // The bit test instructions below are AVX only
6711 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6712 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6713 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6714 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6715 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6716 Sched<[WriteVecLogic]>, VEX;
6717 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6718 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6719 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6720 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6723 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6724 let ExeDomain = SSEPackedSingle in {
6725 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6726 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6729 let ExeDomain = SSEPackedDouble in {
6730 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6731 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6736 //===----------------------------------------------------------------------===//
6737 // SSE4.1 - Misc Instructions
6738 //===----------------------------------------------------------------------===//
6740 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6741 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6742 "popcnt{w}\t{$src, $dst|$dst, $src}",
6743 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6744 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6746 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6747 "popcnt{w}\t{$src, $dst|$dst, $src}",
6748 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6749 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6750 Sched<[WriteFAddLd]>, OpSize16, XS;
6752 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6753 "popcnt{l}\t{$src, $dst|$dst, $src}",
6754 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6755 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6758 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6759 "popcnt{l}\t{$src, $dst|$dst, $src}",
6760 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6761 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6762 Sched<[WriteFAddLd]>, OpSize32, XS;
6764 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6765 "popcnt{q}\t{$src, $dst|$dst, $src}",
6766 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6767 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6768 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6769 "popcnt{q}\t{$src, $dst|$dst, $src}",
6770 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6771 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6772 Sched<[WriteFAddLd]>, XS;
6777 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6778 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6779 Intrinsic IntId128, PatFrag ld_frag,
6780 X86FoldableSchedWrite Sched> {
6781 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6784 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6786 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6790 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6791 Sched<[Sched.Folded]>;
6794 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6795 // model, although the naming is misleading.
6796 let Predicates = [HasAVX] in
6797 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6798 int_x86_sse41_phminposuw, loadv2i64,
6800 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6801 int_x86_sse41_phminposuw, memopv2i64,
6804 /// SS48I_binop_rm - Simple SSE41 binary operator.
6805 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6806 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6807 X86MemOperand x86memop, bit Is2Addr = 1,
6808 OpndItins itins = SSE_INTALU_ITINS_P> {
6809 let isCommutable = 1 in
6810 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6811 (ins RC:$src1, RC:$src2),
6813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6814 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6815 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6816 Sched<[itins.Sched]>;
6817 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6818 (ins RC:$src1, x86memop:$src2),
6820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6823 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6824 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6827 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6829 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6830 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6831 PatFrag memop_frag, X86MemOperand x86memop,
6833 bit IsCommutable = 0, bit Is2Addr = 1> {
6834 let isCommutable = IsCommutable in
6835 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6836 (ins RC:$src1, RC:$src2),
6838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6839 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6840 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6841 Sched<[itins.Sched]>;
6842 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6843 (ins RC:$src1, x86memop:$src2),
6845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6847 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6848 (bitconvert (memop_frag addr:$src2)))))]>,
6849 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6852 let Predicates = [HasAVX, NoVLX] in {
6853 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6854 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6856 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6857 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6859 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6860 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6862 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6863 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6865 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6866 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6868 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6869 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6871 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6872 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6874 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6875 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6877 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6878 VR128, loadv2i64, i128mem,
6879 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6882 let Predicates = [HasAVX2, NoVLX] in {
6883 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6884 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6886 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6887 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6889 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6890 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6892 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6893 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6895 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6896 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6898 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6899 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6901 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6902 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6904 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6905 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6907 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6908 VR256, loadv4i64, i256mem,
6909 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6912 let Constraints = "$src1 = $dst" in {
6913 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6914 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6915 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6916 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6917 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6918 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6919 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6920 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6921 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6922 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6923 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6924 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6925 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6926 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6927 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6928 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6929 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6930 VR128, memopv2i64, i128mem,
6931 SSE_INTMUL_ITINS_P, 1>;
6934 let Predicates = [HasAVX, NoVLX] in {
6935 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6936 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6938 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6939 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6942 let Predicates = [HasAVX2] in {
6943 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6944 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6946 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6947 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6951 let Constraints = "$src1 = $dst" in {
6952 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6953 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6954 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6955 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6958 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6959 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6960 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6961 X86MemOperand x86memop, bit Is2Addr = 1,
6962 OpndItins itins = DEFAULT_ITINS> {
6963 let isCommutable = 1 in
6964 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6965 (ins RC:$src1, RC:$src2, u8imm:$src3),
6967 !strconcat(OpcodeStr,
6968 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6969 !strconcat(OpcodeStr,
6970 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6971 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6972 Sched<[itins.Sched]>;
6973 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6974 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6976 !strconcat(OpcodeStr,
6977 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6978 !strconcat(OpcodeStr,
6979 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6982 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6983 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6986 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6987 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6988 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6989 X86MemOperand x86memop, bit Is2Addr = 1,
6990 OpndItins itins = DEFAULT_ITINS> {
6991 let isCommutable = 1 in
6992 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6993 (ins RC:$src1, RC:$src2, u8imm:$src3),
6995 !strconcat(OpcodeStr,
6996 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6997 !strconcat(OpcodeStr,
6998 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6999 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
7000 itins.rr>, Sched<[itins.Sched]>;
7001 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7002 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
7004 !strconcat(OpcodeStr,
7005 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7006 !strconcat(OpcodeStr,
7007 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7009 (OpVT (OpNode RC:$src1,
7010 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
7011 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7014 let Predicates = [HasAVX] in {
7015 let isCommutable = 0 in {
7016 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7017 VR128, loadv2i64, i128mem, 0,
7018 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7021 let ExeDomain = SSEPackedSingle in {
7022 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7023 VR128, loadv4f32, f128mem, 0,
7024 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7025 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7026 VR256, loadv8f32, f256mem, 0,
7027 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7029 let ExeDomain = SSEPackedDouble in {
7030 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7031 VR128, loadv2f64, f128mem, 0,
7032 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7033 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7034 VR256, loadv4f64, f256mem, 0,
7035 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7037 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7038 VR128, loadv2i64, i128mem, 0,
7039 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7041 let ExeDomain = SSEPackedSingle in
7042 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7043 VR128, loadv4f32, f128mem, 0,
7044 SSE_DPPS_ITINS>, VEX_4V;
7045 let ExeDomain = SSEPackedDouble in
7046 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7047 VR128, loadv2f64, f128mem, 0,
7048 SSE_DPPS_ITINS>, VEX_4V;
7049 let ExeDomain = SSEPackedSingle in
7050 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7051 VR256, loadv8f32, i256mem, 0,
7052 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7055 let Predicates = [HasAVX2] in {
7056 let isCommutable = 0 in {
7057 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7058 VR256, loadv4i64, i256mem, 0,
7059 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7061 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7062 VR256, loadv4i64, i256mem, 0,
7063 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7066 let Constraints = "$src1 = $dst" in {
7067 let isCommutable = 0 in {
7068 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7069 VR128, memopv2i64, i128mem,
7070 1, SSE_MPSADBW_ITINS>;
7072 let ExeDomain = SSEPackedSingle in
7073 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7074 VR128, memopv4f32, f128mem,
7075 1, SSE_INTALU_ITINS_FBLEND_P>;
7076 let ExeDomain = SSEPackedDouble in
7077 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7078 VR128, memopv2f64, f128mem,
7079 1, SSE_INTALU_ITINS_FBLEND_P>;
7080 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7081 VR128, memopv2i64, i128mem,
7082 1, SSE_INTALU_ITINS_BLEND_P>;
7083 let ExeDomain = SSEPackedSingle in
7084 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7085 VR128, memopv4f32, f128mem, 1,
7087 let ExeDomain = SSEPackedDouble in
7088 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7089 VR128, memopv2f64, f128mem, 1,
7093 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7094 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7095 RegisterClass RC, X86MemOperand x86memop,
7096 PatFrag mem_frag, Intrinsic IntId,
7097 X86FoldableSchedWrite Sched> {
7098 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7099 (ins RC:$src1, RC:$src2, RC:$src3),
7100 !strconcat(OpcodeStr,
7101 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7102 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7103 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7106 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7107 (ins RC:$src1, x86memop:$src2, RC:$src3),
7108 !strconcat(OpcodeStr,
7109 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7111 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7113 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7114 Sched<[Sched.Folded, ReadAfterLd]>;
7117 let Predicates = [HasAVX] in {
7118 let ExeDomain = SSEPackedDouble in {
7119 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7120 loadv2f64, int_x86_sse41_blendvpd,
7122 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7123 loadv4f64, int_x86_avx_blendv_pd_256,
7124 WriteFVarBlend>, VEX_L;
7125 } // ExeDomain = SSEPackedDouble
7126 let ExeDomain = SSEPackedSingle in {
7127 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7128 loadv4f32, int_x86_sse41_blendvps,
7130 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7131 loadv8f32, int_x86_avx_blendv_ps_256,
7132 WriteFVarBlend>, VEX_L;
7133 } // ExeDomain = SSEPackedSingle
7134 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7135 loadv2i64, int_x86_sse41_pblendvb,
7139 let Predicates = [HasAVX2] in {
7140 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7141 loadv4i64, int_x86_avx2_pblendvb,
7142 WriteVarBlend>, VEX_L;
7145 let Predicates = [HasAVX] in {
7146 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7147 (v16i8 VR128:$src2))),
7148 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7149 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7150 (v4i32 VR128:$src2))),
7151 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7152 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7153 (v4f32 VR128:$src2))),
7154 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7155 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7156 (v2i64 VR128:$src2))),
7157 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7158 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7159 (v2f64 VR128:$src2))),
7160 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7161 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7162 (v8i32 VR256:$src2))),
7163 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7164 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7165 (v8f32 VR256:$src2))),
7166 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7167 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7168 (v4i64 VR256:$src2))),
7169 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7170 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7171 (v4f64 VR256:$src2))),
7172 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7175 let Predicates = [HasAVX2] in {
7176 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7177 (v32i8 VR256:$src2))),
7178 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7182 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7183 // on targets where they have equal performance. These were changed to use
7184 // blends because blends have better throughput on SandyBridge and Haswell, but
7185 // movs[s/d] are 1-2 byte shorter instructions.
7186 let Predicates = [UseAVX] in {
7187 let AddedComplexity = 15 in {
7188 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7189 // MOVS{S,D} to the lower bits.
7190 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7191 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7192 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7193 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7194 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7195 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7196 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7197 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7199 // Move low f32 and clear high bits.
7200 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7201 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7203 // Move low f64 and clear high bits.
7204 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7205 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7208 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7209 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7210 (SUBREG_TO_REG (i32 0),
7211 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7213 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7214 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7215 (SUBREG_TO_REG (i64 0),
7216 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7219 // These will incur an FP/int domain crossing penalty, but it may be the only
7220 // way without AVX2. Do not add any complexity because we may be able to match
7221 // more optimal patterns defined earlier in this file.
7222 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7223 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7224 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7225 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7228 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7229 // on targets where they have equal performance. These were changed to use
7230 // blends because blends have better throughput on SandyBridge and Haswell, but
7231 // movs[s/d] are 1-2 byte shorter instructions.
7232 let Predicates = [UseSSE41] in {
7233 // With SSE41 we can use blends for these patterns.
7234 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7235 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7236 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7237 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7238 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7239 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7243 /// SS41I_ternary_int - SSE 4.1 ternary operator
7244 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7245 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7246 X86MemOperand x86memop, Intrinsic IntId,
7247 OpndItins itins = DEFAULT_ITINS> {
7248 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7249 (ins VR128:$src1, VR128:$src2),
7250 !strconcat(OpcodeStr,
7251 "\t{$src2, $dst|$dst, $src2}"),
7252 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7253 itins.rr>, Sched<[itins.Sched]>;
7255 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7256 (ins VR128:$src1, x86memop:$src2),
7257 !strconcat(OpcodeStr,
7258 "\t{$src2, $dst|$dst, $src2}"),
7261 (bitconvert (mem_frag addr:$src2)), XMM0))],
7262 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7266 let ExeDomain = SSEPackedDouble in
7267 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7268 int_x86_sse41_blendvpd,
7269 DEFAULT_ITINS_FBLENDSCHED>;
7270 let ExeDomain = SSEPackedSingle in
7271 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7272 int_x86_sse41_blendvps,
7273 DEFAULT_ITINS_FBLENDSCHED>;
7274 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7275 int_x86_sse41_pblendvb,
7276 DEFAULT_ITINS_VARBLENDSCHED>;
7278 // Aliases with the implicit xmm0 argument
7279 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7280 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7281 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7282 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7283 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7284 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7285 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7286 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7287 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7288 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7289 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7290 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7292 let Predicates = [UseSSE41] in {
7293 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7294 (v16i8 VR128:$src2))),
7295 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7296 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7297 (v4i32 VR128:$src2))),
7298 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7299 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7300 (v4f32 VR128:$src2))),
7301 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7302 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7303 (v2i64 VR128:$src2))),
7304 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7305 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7306 (v2f64 VR128:$src2))),
7307 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7310 let SchedRW = [WriteLoad] in {
7311 let Predicates = [HasAVX] in
7312 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7313 "vmovntdqa\t{$src, $dst|$dst, $src}",
7314 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7316 let Predicates = [HasAVX2] in
7317 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7318 "vmovntdqa\t{$src, $dst|$dst, $src}",
7319 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7321 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7322 "movntdqa\t{$src, $dst|$dst, $src}",
7323 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7326 //===----------------------------------------------------------------------===//
7327 // SSE4.2 - Compare Instructions
7328 //===----------------------------------------------------------------------===//
7330 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7331 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7332 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7333 X86MemOperand x86memop, bit Is2Addr = 1> {
7334 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7335 (ins RC:$src1, RC:$src2),
7337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7339 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7340 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7341 (ins RC:$src1, x86memop:$src2),
7343 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7344 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7346 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7349 let Predicates = [HasAVX] in
7350 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7351 loadv2i64, i128mem, 0>, VEX_4V;
7353 let Predicates = [HasAVX2] in
7354 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7355 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7357 let Constraints = "$src1 = $dst" in
7358 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7359 memopv2i64, i128mem>;
7361 //===----------------------------------------------------------------------===//
7362 // SSE4.2 - String/text Processing Instructions
7363 //===----------------------------------------------------------------------===//
7365 // Packed Compare Implicit Length Strings, Return Mask
7366 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7367 def REG : PseudoI<(outs VR128:$dst),
7368 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7369 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7371 def MEM : PseudoI<(outs VR128:$dst),
7372 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7373 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7374 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7377 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7378 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7380 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7381 Requires<[UseSSE42]>;
7384 multiclass pcmpistrm_SS42AI<string asm> {
7385 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7386 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7387 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7388 []>, Sched<[WritePCmpIStrM]>;
7390 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7391 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7392 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7393 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7396 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7397 let Predicates = [HasAVX] in
7398 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7399 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7402 // Packed Compare Explicit Length Strings, Return Mask
7403 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7404 def REG : PseudoI<(outs VR128:$dst),
7405 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7406 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7407 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7408 def MEM : PseudoI<(outs VR128:$dst),
7409 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7410 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7411 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7414 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7415 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7417 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7418 Requires<[UseSSE42]>;
7421 multiclass SS42AI_pcmpestrm<string asm> {
7422 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7423 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7424 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7425 []>, Sched<[WritePCmpEStrM]>;
7427 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7428 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7429 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7430 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7433 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7434 let Predicates = [HasAVX] in
7435 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7436 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7439 // Packed Compare Implicit Length Strings, Return Index
7440 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7441 def REG : PseudoI<(outs GR32:$dst),
7442 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7443 [(set GR32:$dst, EFLAGS,
7444 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7445 def MEM : PseudoI<(outs GR32:$dst),
7446 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7447 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7448 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7451 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7452 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7454 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7455 Requires<[UseSSE42]>;
7458 multiclass SS42AI_pcmpistri<string asm> {
7459 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7460 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7461 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7462 []>, Sched<[WritePCmpIStrI]>;
7464 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7465 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7466 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7467 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7470 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7471 let Predicates = [HasAVX] in
7472 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7473 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7476 // Packed Compare Explicit Length Strings, Return Index
7477 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7478 def REG : PseudoI<(outs GR32:$dst),
7479 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7480 [(set GR32:$dst, EFLAGS,
7481 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7482 def MEM : PseudoI<(outs GR32:$dst),
7483 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7484 [(set GR32:$dst, EFLAGS,
7485 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7489 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7490 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7492 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7493 Requires<[UseSSE42]>;
7496 multiclass SS42AI_pcmpestri<string asm> {
7497 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7498 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7499 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7500 []>, Sched<[WritePCmpEStrI]>;
7502 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7503 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7504 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7505 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7508 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7509 let Predicates = [HasAVX] in
7510 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7511 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7514 //===----------------------------------------------------------------------===//
7515 // SSE4.2 - CRC Instructions
7516 //===----------------------------------------------------------------------===//
7518 // No CRC instructions have AVX equivalents
7520 // crc intrinsic instruction
7521 // This set of instructions are only rm, the only difference is the size
7523 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7524 RegisterClass RCIn, SDPatternOperator Int> :
7525 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7526 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7527 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7530 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7531 X86MemOperand x86memop, SDPatternOperator Int> :
7532 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7533 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7534 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7535 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7537 let Constraints = "$src1 = $dst" in {
7538 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7539 int_x86_sse42_crc32_32_8>;
7540 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7541 int_x86_sse42_crc32_32_8>;
7542 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7543 int_x86_sse42_crc32_32_16>, OpSize16;
7544 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7545 int_x86_sse42_crc32_32_16>, OpSize16;
7546 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7547 int_x86_sse42_crc32_32_32>, OpSize32;
7548 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7549 int_x86_sse42_crc32_32_32>, OpSize32;
7550 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7551 int_x86_sse42_crc32_64_64>, REX_W;
7552 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7553 int_x86_sse42_crc32_64_64>, REX_W;
7554 let hasSideEffects = 0 in {
7556 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7558 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7563 //===----------------------------------------------------------------------===//
7564 // SHA-NI Instructions
7565 //===----------------------------------------------------------------------===//
7567 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7569 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7570 (ins VR128:$src1, VR128:$src2),
7571 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7573 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7574 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7576 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7577 (ins VR128:$src1, i128mem:$src2),
7578 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7580 (set VR128:$dst, (IntId VR128:$src1,
7581 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7582 (set VR128:$dst, (IntId VR128:$src1,
7583 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7586 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7587 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7588 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7589 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7591 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7592 (i8 imm:$src3)))]>, TA;
7593 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7594 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7595 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7597 (int_x86_sha1rnds4 VR128:$src1,
7598 (bc_v4i32 (memopv2i64 addr:$src2)),
7599 (i8 imm:$src3)))]>, TA;
7601 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7602 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7603 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7606 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7608 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7609 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7612 // Aliases with explicit %xmm0
7613 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7614 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7615 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7616 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7618 //===----------------------------------------------------------------------===//
7619 // AES-NI Instructions
7620 //===----------------------------------------------------------------------===//
7622 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7623 PatFrag ld_frag, bit Is2Addr = 1> {
7624 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7625 (ins VR128:$src1, VR128:$src2),
7627 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7629 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7630 Sched<[WriteAESDecEnc]>;
7631 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7632 (ins VR128:$src1, i128mem:$src2),
7634 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7635 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7637 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7638 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7641 // Perform One Round of an AES Encryption/Decryption Flow
7642 let Predicates = [HasAVX, HasAES] in {
7643 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7644 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7645 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7646 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7647 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7648 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7649 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7650 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7653 let Constraints = "$src1 = $dst" in {
7654 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7655 int_x86_aesni_aesenc, memopv2i64>;
7656 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7657 int_x86_aesni_aesenclast, memopv2i64>;
7658 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7659 int_x86_aesni_aesdec, memopv2i64>;
7660 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7661 int_x86_aesni_aesdeclast, memopv2i64>;
7664 // Perform the AES InvMixColumn Transformation
7665 let Predicates = [HasAVX, HasAES] in {
7666 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7668 "vaesimc\t{$src1, $dst|$dst, $src1}",
7670 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7672 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7673 (ins i128mem:$src1),
7674 "vaesimc\t{$src1, $dst|$dst, $src1}",
7675 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7676 Sched<[WriteAESIMCLd]>, VEX;
7678 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7680 "aesimc\t{$src1, $dst|$dst, $src1}",
7682 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7683 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7684 (ins i128mem:$src1),
7685 "aesimc\t{$src1, $dst|$dst, $src1}",
7686 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7687 Sched<[WriteAESIMCLd]>;
7689 // AES Round Key Generation Assist
7690 let Predicates = [HasAVX, HasAES] in {
7691 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7692 (ins VR128:$src1, u8imm:$src2),
7693 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7695 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7696 Sched<[WriteAESKeyGen]>, VEX;
7697 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7698 (ins i128mem:$src1, u8imm:$src2),
7699 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7701 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7702 Sched<[WriteAESKeyGenLd]>, VEX;
7704 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7705 (ins VR128:$src1, u8imm:$src2),
7706 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7708 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7709 Sched<[WriteAESKeyGen]>;
7710 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7711 (ins i128mem:$src1, u8imm:$src2),
7712 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7714 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7715 Sched<[WriteAESKeyGenLd]>;
7717 //===----------------------------------------------------------------------===//
7718 // PCLMUL Instructions
7719 //===----------------------------------------------------------------------===//
7721 // AVX carry-less Multiplication instructions
7722 let isCommutable = 1 in
7723 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7724 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7725 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7727 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7728 Sched<[WriteCLMul]>;
7730 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7731 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7732 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7733 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7734 (loadv2i64 addr:$src2), imm:$src3))]>,
7735 Sched<[WriteCLMulLd, ReadAfterLd]>;
7737 // Carry-less Multiplication instructions
7738 let Constraints = "$src1 = $dst" in {
7739 let isCommutable = 1 in
7740 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7741 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7742 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7744 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7745 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7747 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7748 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7749 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7750 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7751 (memopv2i64 addr:$src2), imm:$src3))],
7752 IIC_SSE_PCLMULQDQ_RM>,
7753 Sched<[WriteCLMulLd, ReadAfterLd]>;
7754 } // Constraints = "$src1 = $dst"
7757 multiclass pclmul_alias<string asm, int immop> {
7758 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7759 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7761 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7762 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7764 def : InstAlias<!strconcat("vpclmul", asm,
7765 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7766 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7769 def : InstAlias<!strconcat("vpclmul", asm,
7770 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7771 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7774 defm : pclmul_alias<"hqhq", 0x11>;
7775 defm : pclmul_alias<"hqlq", 0x01>;
7776 defm : pclmul_alias<"lqhq", 0x10>;
7777 defm : pclmul_alias<"lqlq", 0x00>;
7779 //===----------------------------------------------------------------------===//
7780 // SSE4A Instructions
7781 //===----------------------------------------------------------------------===//
7783 let Predicates = [HasSSE4A] in {
7785 let Constraints = "$src = $dst" in {
7786 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7787 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7788 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7789 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7791 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7792 (ins VR128:$src, VR128:$mask),
7793 "extrq\t{$mask, $src|$src, $mask}",
7794 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7795 VR128:$mask))]>, PD;
7797 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7798 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7799 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7800 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7801 imm:$len, imm:$idx))]>, XD;
7802 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7803 (ins VR128:$src, VR128:$mask),
7804 "insertq\t{$mask, $src|$src, $mask}",
7805 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7806 VR128:$mask))]>, XD;
7809 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7810 "movntss\t{$src, $dst|$dst, $src}",
7811 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7813 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7814 "movntsd\t{$src, $dst|$dst, $src}",
7815 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7818 //===----------------------------------------------------------------------===//
7820 //===----------------------------------------------------------------------===//
7822 //===----------------------------------------------------------------------===//
7823 // VBROADCAST - Load from memory and broadcast to all elements of the
7824 // destination operand
7826 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7827 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7828 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7829 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7830 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7832 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7833 X86MemOperand x86memop, ValueType VT,
7834 PatFrag ld_frag, SchedWrite Sched> :
7835 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7836 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7837 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7838 Sched<[Sched]>, VEX {
7842 // AVX2 adds register forms
7843 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7844 Intrinsic Int, SchedWrite Sched> :
7845 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7846 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7847 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7849 let ExeDomain = SSEPackedSingle in {
7850 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7851 f32mem, v4f32, loadf32, WriteLoad>;
7852 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7853 f32mem, v8f32, loadf32,
7854 WriteFShuffleLd>, VEX_L;
7856 let ExeDomain = SSEPackedDouble in
7857 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7858 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7859 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7860 int_x86_avx_vbroadcastf128_pd_256,
7861 WriteFShuffleLd>, VEX_L;
7863 let ExeDomain = SSEPackedSingle in {
7864 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7865 int_x86_avx2_vbroadcast_ss_ps,
7867 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7868 int_x86_avx2_vbroadcast_ss_ps_256,
7869 WriteFShuffle256>, VEX_L;
7871 let ExeDomain = SSEPackedDouble in
7872 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7873 int_x86_avx2_vbroadcast_sd_pd_256,
7874 WriteFShuffle256>, VEX_L;
7876 let mayLoad = 1, Predicates = [HasAVX2] in
7877 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7879 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7880 Sched<[WriteLoad]>, VEX, VEX_L;
7882 let Predicates = [HasAVX] in
7883 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7884 (VBROADCASTF128 addr:$src)>;
7887 //===----------------------------------------------------------------------===//
7888 // VINSERTF128 - Insert packed floating-point values
7890 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7891 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7892 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7893 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7894 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7896 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7897 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7898 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7899 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7902 let Predicates = [HasAVX] in {
7903 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7905 (VINSERTF128rr VR256:$src1, VR128:$src2,
7906 (INSERT_get_vinsert128_imm VR256:$ins))>;
7907 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7909 (VINSERTF128rr VR256:$src1, VR128:$src2,
7910 (INSERT_get_vinsert128_imm VR256:$ins))>;
7912 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7914 (VINSERTF128rm VR256:$src1, addr:$src2,
7915 (INSERT_get_vinsert128_imm VR256:$ins))>;
7916 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7918 (VINSERTF128rm VR256:$src1, addr:$src2,
7919 (INSERT_get_vinsert128_imm VR256:$ins))>;
7922 let Predicates = [HasAVX1Only] in {
7923 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7925 (VINSERTF128rr VR256:$src1, VR128:$src2,
7926 (INSERT_get_vinsert128_imm VR256:$ins))>;
7927 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7929 (VINSERTF128rr VR256:$src1, VR128:$src2,
7930 (INSERT_get_vinsert128_imm VR256:$ins))>;
7931 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7933 (VINSERTF128rr VR256:$src1, VR128:$src2,
7934 (INSERT_get_vinsert128_imm VR256:$ins))>;
7935 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7937 (VINSERTF128rr VR256:$src1, VR128:$src2,
7938 (INSERT_get_vinsert128_imm VR256:$ins))>;
7940 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7942 (VINSERTF128rm VR256:$src1, addr:$src2,
7943 (INSERT_get_vinsert128_imm VR256:$ins))>;
7944 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7945 (bc_v4i32 (loadv2i64 addr:$src2)),
7947 (VINSERTF128rm VR256:$src1, addr:$src2,
7948 (INSERT_get_vinsert128_imm VR256:$ins))>;
7949 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7950 (bc_v16i8 (loadv2i64 addr:$src2)),
7952 (VINSERTF128rm VR256:$src1, addr:$src2,
7953 (INSERT_get_vinsert128_imm VR256:$ins))>;
7954 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7955 (bc_v8i16 (loadv2i64 addr:$src2)),
7957 (VINSERTF128rm VR256:$src1, addr:$src2,
7958 (INSERT_get_vinsert128_imm VR256:$ins))>;
7961 //===----------------------------------------------------------------------===//
7962 // VEXTRACTF128 - Extract packed floating-point values
7964 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7965 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7966 (ins VR256:$src1, u8imm:$src2),
7967 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7968 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7970 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7971 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7972 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7973 []>, Sched<[WriteStore]>, VEX, VEX_L;
7977 let Predicates = [HasAVX] in {
7978 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7979 (v4f32 (VEXTRACTF128rr
7980 (v8f32 VR256:$src1),
7981 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7982 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7983 (v2f64 (VEXTRACTF128rr
7984 (v4f64 VR256:$src1),
7985 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7987 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7988 (iPTR imm))), addr:$dst),
7989 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7990 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7991 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7992 (iPTR imm))), addr:$dst),
7993 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7994 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7997 let Predicates = [HasAVX1Only] in {
7998 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7999 (v2i64 (VEXTRACTF128rr
8000 (v4i64 VR256:$src1),
8001 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8002 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8003 (v4i32 (VEXTRACTF128rr
8004 (v8i32 VR256:$src1),
8005 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8006 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8007 (v8i16 (VEXTRACTF128rr
8008 (v16i16 VR256:$src1),
8009 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8010 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8011 (v16i8 (VEXTRACTF128rr
8012 (v32i8 VR256:$src1),
8013 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8015 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8016 (iPTR imm))), addr:$dst),
8017 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8018 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8019 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8020 (iPTR imm))), addr:$dst),
8021 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8022 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8023 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8024 (iPTR imm))), addr:$dst),
8025 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8026 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8027 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8028 (iPTR imm))), addr:$dst),
8029 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8030 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8033 //===----------------------------------------------------------------------===//
8034 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8036 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8037 Intrinsic IntLd, Intrinsic IntLd256,
8038 Intrinsic IntSt, Intrinsic IntSt256> {
8039 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8040 (ins VR128:$src1, f128mem:$src2),
8041 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8042 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8044 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8045 (ins VR256:$src1, f256mem:$src2),
8046 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8047 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8049 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8050 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8051 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8052 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8053 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8054 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8055 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8056 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8059 let ExeDomain = SSEPackedSingle in
8060 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8061 int_x86_avx_maskload_ps,
8062 int_x86_avx_maskload_ps_256,
8063 int_x86_avx_maskstore_ps,
8064 int_x86_avx_maskstore_ps_256>;
8065 let ExeDomain = SSEPackedDouble in
8066 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8067 int_x86_avx_maskload_pd,
8068 int_x86_avx_maskload_pd_256,
8069 int_x86_avx_maskstore_pd,
8070 int_x86_avx_maskstore_pd_256>;
8072 //===----------------------------------------------------------------------===//
8073 // VPERMIL - Permute Single and Double Floating-Point Values
8075 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8076 RegisterClass RC, X86MemOperand x86memop_f,
8077 X86MemOperand x86memop_i, PatFrag i_frag,
8078 Intrinsic IntVar, ValueType vt> {
8079 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8080 (ins RC:$src1, RC:$src2),
8081 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8082 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8083 Sched<[WriteFShuffle]>;
8084 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8085 (ins RC:$src1, x86memop_i:$src2),
8086 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8087 [(set RC:$dst, (IntVar RC:$src1,
8088 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8089 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8091 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8092 (ins RC:$src1, u8imm:$src2),
8093 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8094 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8095 Sched<[WriteFShuffle]>;
8096 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8097 (ins x86memop_f:$src1, u8imm:$src2),
8098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8100 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8101 Sched<[WriteFShuffleLd]>;
8104 let ExeDomain = SSEPackedSingle in {
8105 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8106 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8107 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8108 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8110 let ExeDomain = SSEPackedDouble in {
8111 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8112 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8113 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8114 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8117 let Predicates = [HasAVX] in {
8118 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8119 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8120 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8121 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8122 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8123 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8124 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8125 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8127 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8128 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8129 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8130 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8131 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8133 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8134 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8135 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8137 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8138 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8139 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8140 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8141 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8142 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8143 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8144 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8146 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8147 (VPERMILPDri VR128:$src1, imm:$imm)>;
8148 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8149 (VPERMILPDmi addr:$src1, imm:$imm)>;
8152 //===----------------------------------------------------------------------===//
8153 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8155 let ExeDomain = SSEPackedSingle in {
8156 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8157 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8158 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8159 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8160 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8161 Sched<[WriteFShuffle]>;
8162 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8163 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8164 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8165 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8166 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8167 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8170 let Predicates = [HasAVX] in {
8171 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8172 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8173 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8174 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8175 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8178 let Predicates = [HasAVX1Only] in {
8179 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8180 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8181 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8182 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8183 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8184 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8185 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8186 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8188 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8189 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8190 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8191 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8192 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8193 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8194 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8195 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8196 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8197 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8198 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8199 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8202 //===----------------------------------------------------------------------===//
8203 // VZERO - Zero YMM registers
8205 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8206 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8207 // Zero All YMM registers
8208 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8209 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8211 // Zero Upper bits of YMM registers
8212 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8213 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8216 //===----------------------------------------------------------------------===//
8217 // Half precision conversion instructions
8218 //===----------------------------------------------------------------------===//
8219 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8220 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8221 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8222 [(set RC:$dst, (Int VR128:$src))]>,
8223 T8PD, VEX, Sched<[WriteCvtF2F]>;
8224 let hasSideEffects = 0, mayLoad = 1 in
8225 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8226 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8227 Sched<[WriteCvtF2FLd]>;
8230 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8231 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8232 (ins RC:$src1, i32u8imm:$src2),
8233 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8234 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8235 TAPD, VEX, Sched<[WriteCvtF2F]>;
8236 let hasSideEffects = 0, mayStore = 1,
8237 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8238 def mr : Ii8<0x1D, MRMDestMem, (outs),
8239 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8240 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8244 let Predicates = [HasF16C] in {
8245 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8246 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8247 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8248 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8250 // Pattern match vcvtph2ps of a scalar i64 load.
8251 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8252 (VCVTPH2PSrm addr:$src)>;
8253 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8254 (VCVTPH2PSrm addr:$src)>;
8256 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8257 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8259 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8260 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8261 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8263 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8264 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8266 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8269 // Patterns for matching conversions from float to half-float and vice versa.
8270 let Predicates = [HasF16C] in {
8271 def : Pat<(fp_to_f16 FR32:$src),
8272 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8273 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8275 def : Pat<(f16_to_fp GR16:$src),
8276 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8277 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8279 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8280 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8281 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8284 //===----------------------------------------------------------------------===//
8285 // AVX2 Instructions
8286 //===----------------------------------------------------------------------===//
8288 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8289 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8290 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8291 X86MemOperand x86memop> {
8292 let isCommutable = 1 in
8293 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8294 (ins RC:$src1, RC:$src2, u8imm:$src3),
8295 !strconcat(OpcodeStr,
8296 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8297 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8298 Sched<[WriteBlend]>, VEX_4V;
8299 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8300 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8301 !strconcat(OpcodeStr,
8302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8304 (OpVT (OpNode RC:$src1,
8305 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8306 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8309 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8310 VR128, loadv2i64, i128mem>;
8311 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8312 VR256, loadv4i64, i256mem>, VEX_L;
8314 //===----------------------------------------------------------------------===//
8315 // VPBROADCAST - Load from memory and broadcast to all elements of the
8316 // destination operand
8318 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8319 X86MemOperand x86memop, PatFrag ld_frag,
8320 Intrinsic Int128, Intrinsic Int256> {
8321 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8322 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8323 [(set VR128:$dst, (Int128 VR128:$src))]>,
8324 Sched<[WriteShuffle]>, VEX;
8325 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8326 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8328 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8329 Sched<[WriteLoad]>, VEX;
8330 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8331 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8332 [(set VR256:$dst, (Int256 VR128:$src))]>,
8333 Sched<[WriteShuffle256]>, VEX, VEX_L;
8334 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8335 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8337 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8338 Sched<[WriteLoad]>, VEX, VEX_L;
8341 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8342 int_x86_avx2_pbroadcastb_128,
8343 int_x86_avx2_pbroadcastb_256>;
8344 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8345 int_x86_avx2_pbroadcastw_128,
8346 int_x86_avx2_pbroadcastw_256>;
8347 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8348 int_x86_avx2_pbroadcastd_128,
8349 int_x86_avx2_pbroadcastd_256>;
8350 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8351 int_x86_avx2_pbroadcastq_128,
8352 int_x86_avx2_pbroadcastq_256>;
8354 let Predicates = [HasAVX2] in {
8355 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8356 (VPBROADCASTBrm addr:$src)>;
8357 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8358 (VPBROADCASTBYrm addr:$src)>;
8359 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8360 (VPBROADCASTWrm addr:$src)>;
8361 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8362 (VPBROADCASTWYrm addr:$src)>;
8363 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8364 (VPBROADCASTDrm addr:$src)>;
8365 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8366 (VPBROADCASTDYrm addr:$src)>;
8367 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8368 (VPBROADCASTQrm addr:$src)>;
8369 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8370 (VPBROADCASTQYrm addr:$src)>;
8372 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8373 (VPBROADCASTBrr VR128:$src)>;
8374 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8375 (VPBROADCASTBYrr VR128:$src)>;
8376 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8377 (VPBROADCASTWrr VR128:$src)>;
8378 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8379 (VPBROADCASTWYrr VR128:$src)>;
8380 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8381 (VPBROADCASTDrr VR128:$src)>;
8382 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8383 (VPBROADCASTDYrr VR128:$src)>;
8384 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8385 (VPBROADCASTQrr VR128:$src)>;
8386 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8387 (VPBROADCASTQYrr VR128:$src)>;
8388 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8389 (VBROADCASTSSrr VR128:$src)>;
8390 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8391 (VBROADCASTSSYrr VR128:$src)>;
8392 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8393 (VPBROADCASTQrr VR128:$src)>;
8394 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8395 (VBROADCASTSDYrr VR128:$src)>;
8397 // Provide aliases for broadcast from the same register class that
8398 // automatically does the extract.
8399 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8400 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8402 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8403 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8405 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8406 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8408 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8409 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8411 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8412 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8414 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8415 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8418 // Provide fallback in case the load node that is used in the patterns above
8419 // is used by additional users, which prevents the pattern selection.
8420 let AddedComplexity = 20 in {
8421 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8422 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8423 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8424 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8425 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8426 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8428 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8429 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8430 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8431 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8432 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8433 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8435 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8436 (VPBROADCASTBrr (COPY_TO_REGCLASS
8437 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8439 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8440 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8441 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8444 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8445 (VPBROADCASTWrr (COPY_TO_REGCLASS
8446 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8448 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8449 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8450 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8453 // The patterns for VPBROADCASTD are not needed because they would match
8454 // the exact same thing as VBROADCASTSS patterns.
8456 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8457 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8458 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8462 // AVX1 broadcast patterns
8463 let Predicates = [HasAVX1Only] in {
8464 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8465 (VBROADCASTSSYrm addr:$src)>;
8466 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8467 (VBROADCASTSDYrm addr:$src)>;
8468 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8469 (VBROADCASTSSrm addr:$src)>;
8472 let Predicates = [HasAVX] in {
8473 // Provide fallback in case the load node that is used in the patterns above
8474 // is used by additional users, which prevents the pattern selection.
8475 let AddedComplexity = 20 in {
8476 // 128bit broadcasts:
8477 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8478 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8479 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8480 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8481 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8482 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8483 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8484 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8485 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8486 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8488 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8489 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8490 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8491 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8492 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8493 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8494 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8495 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8496 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8497 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8500 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8501 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8502 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8503 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8506 //===----------------------------------------------------------------------===//
8507 // VPERM - Permute instructions
8510 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8511 ValueType OpVT, X86FoldableSchedWrite Sched> {
8512 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8513 (ins VR256:$src1, VR256:$src2),
8514 !strconcat(OpcodeStr,
8515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8517 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8518 Sched<[Sched]>, VEX_4V, VEX_L;
8519 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8520 (ins VR256:$src1, i256mem:$src2),
8521 !strconcat(OpcodeStr,
8522 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8524 (OpVT (X86VPermv VR256:$src1,
8525 (bitconvert (mem_frag addr:$src2)))))]>,
8526 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8529 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8530 let ExeDomain = SSEPackedSingle in
8531 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8533 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8534 ValueType OpVT, X86FoldableSchedWrite Sched> {
8535 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8536 (ins VR256:$src1, u8imm:$src2),
8537 !strconcat(OpcodeStr,
8538 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8540 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8541 Sched<[Sched]>, VEX, VEX_L;
8542 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8543 (ins i256mem:$src1, u8imm:$src2),
8544 !strconcat(OpcodeStr,
8545 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8547 (OpVT (X86VPermi (mem_frag addr:$src1),
8548 (i8 imm:$src2))))]>,
8549 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8552 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8553 WriteShuffle256>, VEX_W;
8554 let ExeDomain = SSEPackedDouble in
8555 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8556 WriteFShuffle256>, VEX_W;
8558 //===----------------------------------------------------------------------===//
8559 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8561 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8562 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8563 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8564 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8565 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8567 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8568 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8569 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8570 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8572 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8574 let Predicates = [HasAVX2] in {
8575 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8576 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8577 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8578 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8579 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8580 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8582 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8584 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8585 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8586 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8587 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8588 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8590 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8594 //===----------------------------------------------------------------------===//
8595 // VINSERTI128 - Insert packed integer values
8597 let hasSideEffects = 0 in {
8598 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8599 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8600 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8601 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8603 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8604 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8605 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8606 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8609 let Predicates = [HasAVX2] in {
8610 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8612 (VINSERTI128rr VR256:$src1, VR128:$src2,
8613 (INSERT_get_vinsert128_imm VR256:$ins))>;
8614 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8616 (VINSERTI128rr VR256:$src1, VR128:$src2,
8617 (INSERT_get_vinsert128_imm VR256:$ins))>;
8618 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8620 (VINSERTI128rr VR256:$src1, VR128:$src2,
8621 (INSERT_get_vinsert128_imm VR256:$ins))>;
8622 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8624 (VINSERTI128rr VR256:$src1, VR128:$src2,
8625 (INSERT_get_vinsert128_imm VR256:$ins))>;
8627 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8629 (VINSERTI128rm VR256:$src1, addr:$src2,
8630 (INSERT_get_vinsert128_imm VR256:$ins))>;
8631 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8632 (bc_v4i32 (loadv2i64 addr:$src2)),
8634 (VINSERTI128rm VR256:$src1, addr:$src2,
8635 (INSERT_get_vinsert128_imm VR256:$ins))>;
8636 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8637 (bc_v16i8 (loadv2i64 addr:$src2)),
8639 (VINSERTI128rm VR256:$src1, addr:$src2,
8640 (INSERT_get_vinsert128_imm VR256:$ins))>;
8641 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8642 (bc_v8i16 (loadv2i64 addr:$src2)),
8644 (VINSERTI128rm VR256:$src1, addr:$src2,
8645 (INSERT_get_vinsert128_imm VR256:$ins))>;
8648 //===----------------------------------------------------------------------===//
8649 // VEXTRACTI128 - Extract packed integer values
8651 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8652 (ins VR256:$src1, u8imm:$src2),
8653 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8654 Sched<[WriteShuffle256]>, VEX, VEX_L;
8655 let hasSideEffects = 0, mayStore = 1 in
8656 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8657 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8658 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8659 Sched<[WriteStore]>, VEX, VEX_L;
8661 let Predicates = [HasAVX2] in {
8662 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8663 (v2i64 (VEXTRACTI128rr
8664 (v4i64 VR256:$src1),
8665 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8666 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8667 (v4i32 (VEXTRACTI128rr
8668 (v8i32 VR256:$src1),
8669 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8670 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8671 (v8i16 (VEXTRACTI128rr
8672 (v16i16 VR256:$src1),
8673 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8674 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8675 (v16i8 (VEXTRACTI128rr
8676 (v32i8 VR256:$src1),
8677 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8679 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8680 (iPTR imm))), addr:$dst),
8681 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8682 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8683 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8684 (iPTR imm))), addr:$dst),
8685 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8686 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8687 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8688 (iPTR imm))), addr:$dst),
8689 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8690 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8691 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8692 (iPTR imm))), addr:$dst),
8693 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8694 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8697 //===----------------------------------------------------------------------===//
8698 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8700 multiclass avx2_pmovmask<string OpcodeStr,
8701 Intrinsic IntLd128, Intrinsic IntLd256,
8702 Intrinsic IntSt128, Intrinsic IntSt256> {
8703 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8704 (ins VR128:$src1, i128mem:$src2),
8705 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8706 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8707 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8708 (ins VR256:$src1, i256mem:$src2),
8709 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8710 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8712 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8713 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8714 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8715 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8716 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8717 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8718 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8719 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8722 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8723 int_x86_avx2_maskload_d,
8724 int_x86_avx2_maskload_d_256,
8725 int_x86_avx2_maskstore_d,
8726 int_x86_avx2_maskstore_d_256>;
8727 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8728 int_x86_avx2_maskload_q,
8729 int_x86_avx2_maskload_q_256,
8730 int_x86_avx2_maskstore_q,
8731 int_x86_avx2_maskstore_q_256>, VEX_W;
8733 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8734 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8736 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8737 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8739 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8740 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8742 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8743 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8745 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8746 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8748 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8749 (bc_v8f32 (v8i32 immAllZerosV)))),
8750 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8752 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8753 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8756 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8757 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8759 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8760 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8762 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8763 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8766 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8767 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8769 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8770 (bc_v4f32 (v4i32 immAllZerosV)))),
8771 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8773 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8774 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8777 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8778 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8780 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8781 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8783 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8784 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8787 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8788 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8790 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8791 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8793 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8794 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8796 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8797 (v4f64 immAllZerosV))),
8798 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8800 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8801 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8804 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8805 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8807 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8808 (bc_v4i64 (v8i32 immAllZerosV)))),
8809 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8811 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8812 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8815 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8816 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8818 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8819 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8821 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8822 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8824 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8825 (v2f64 immAllZerosV))),
8826 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8828 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8829 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8832 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8833 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8835 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8836 (bc_v2i64 (v4i32 immAllZerosV)))),
8837 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8839 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8840 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8843 //===----------------------------------------------------------------------===//
8844 // Variable Bit Shifts
8846 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8847 ValueType vt128, ValueType vt256> {
8848 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8849 (ins VR128:$src1, VR128:$src2),
8850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8852 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8853 VEX_4V, Sched<[WriteVarVecShift]>;
8854 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8855 (ins VR128:$src1, i128mem:$src2),
8856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8858 (vt128 (OpNode VR128:$src1,
8859 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8860 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8861 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8862 (ins VR256:$src1, VR256:$src2),
8863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8865 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8866 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8867 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8868 (ins VR256:$src1, i256mem:$src2),
8869 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8871 (vt256 (OpNode VR256:$src1,
8872 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8873 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8876 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8877 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8878 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8879 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8880 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8882 //===----------------------------------------------------------------------===//
8883 // VGATHER - GATHER Operations
8884 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8885 X86MemOperand memop128, X86MemOperand memop256> {
8886 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8887 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8888 !strconcat(OpcodeStr,
8889 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8891 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8892 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8893 !strconcat(OpcodeStr,
8894 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8895 []>, VEX_4VOp3, VEX_L;
8898 let mayLoad = 1, Constraints
8899 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8901 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8902 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8903 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8904 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8906 let ExeDomain = SSEPackedDouble in {
8907 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8908 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8911 let ExeDomain = SSEPackedSingle in {
8912 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8913 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;