1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinisics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
514 let Defs = [EFLAGS] in {
515 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
516 "ucomiss\t{$src2, $src1|$src1, $src2}",
517 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
518 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
519 "ucomiss\t{$src2, $src1|$src1, $src2}",
520 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
522 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
523 "comiss\t{$src2, $src1|$src1, $src2}", []>;
524 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
525 "comiss\t{$src2, $src1|$src1, $src2}", []>;
529 // Aliases to match intrinsics which expect XMM operand(s).
530 let Constraints = "$src1 = $dst" in {
531 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
533 (ins VR128:$src1, VR128:$src, SSECC:$cc),
534 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
535 [(set VR128:$dst, (int_x86_sse_cmp_ss
537 VR128:$src, imm:$cc))]>;
538 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
540 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
541 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
542 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
543 (load addr:$src), imm:$cc))]>;
546 let Defs = [EFLAGS] in {
547 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
548 "ucomiss\t{$src2, $src1|$src1, $src2}",
549 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
551 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
552 "ucomiss\t{$src2, $src1|$src1, $src2}",
553 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
554 (load addr:$src2)))]>;
556 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
557 "comiss\t{$src2, $src1|$src1, $src2}",
558 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
560 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
561 "comiss\t{$src2, $src1|$src1, $src2}",
562 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
563 (load addr:$src2)))]>;
566 // Aliases of packed SSE1 instructions for scalar use. These all have names
567 // that start with 'Fs'.
569 // Alias instructions that map fld0 to pxor for sse.
570 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
572 // FIXME: Set encoding to pseudo!
573 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
574 [(set FR32:$dst, fp32imm0)]>,
575 Requires<[HasSSE1]>, TB, OpSize;
577 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
579 let neverHasSideEffects = 1 in
580 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
581 "movaps\t{$src, $dst|$dst, $src}", []>;
583 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
585 let canFoldAsLoad = 1, isReMaterializable = 1 in
586 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
587 "movaps\t{$src, $dst|$dst, $src}",
588 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
590 // Alias bitwise logical operations using SSE logical ops on packed FP values.
591 let Constraints = "$src1 = $dst" in {
592 let isCommutable = 1 in {
593 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
594 (ins FR32:$src1, FR32:$src2),
595 "andps\t{$src2, $dst|$dst, $src2}",
596 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
597 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
598 (ins FR32:$src1, FR32:$src2),
599 "orps\t{$src2, $dst|$dst, $src2}",
600 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
601 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
602 (ins FR32:$src1, FR32:$src2),
603 "xorps\t{$src2, $dst|$dst, $src2}",
604 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
607 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
608 (ins FR32:$src1, f128mem:$src2),
609 "andps\t{$src2, $dst|$dst, $src2}",
610 [(set FR32:$dst, (X86fand FR32:$src1,
611 (memopfsf32 addr:$src2)))]>;
612 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
613 (ins FR32:$src1, f128mem:$src2),
614 "orps\t{$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86for FR32:$src1,
616 (memopfsf32 addr:$src2)))]>;
617 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
618 (ins FR32:$src1, f128mem:$src2),
619 "xorps\t{$src2, $dst|$dst, $src2}",
620 [(set FR32:$dst, (X86fxor FR32:$src1,
621 (memopfsf32 addr:$src2)))]>;
623 let neverHasSideEffects = 1 in {
624 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
625 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
626 "andnps\t{$src2, $dst|$dst, $src2}", []>;
628 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
629 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
630 "andnps\t{$src2, $dst|$dst, $src2}", []>;
634 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
636 /// In addition, we also have a special variant of the scalar form here to
637 /// represent the associated intrinsic operation. This form is unlike the
638 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
639 /// and leaves the top elements unmodified (therefore these cannot be commuted).
641 /// These three forms can each be reg+reg or reg+mem, so there are a total of
642 /// six "instructions".
644 let Constraints = "$src1 = $dst" in {
645 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
646 SDNode OpNode, Intrinsic F32Int,
647 bit Commutable = 0> {
648 // Scalar operation, reg+reg.
649 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
652 let isCommutable = Commutable;
655 // Scalar operation, reg+mem.
656 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
657 (ins FR32:$src1, f32mem:$src2),
658 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
659 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
661 // Vector operation, reg+reg.
662 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
663 (ins VR128:$src1, VR128:$src2),
664 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
665 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
666 let isCommutable = Commutable;
669 // Vector operation, reg+mem.
670 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
671 (ins VR128:$src1, f128mem:$src2),
672 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
673 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
675 // Intrinsic operation, reg+reg.
676 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
677 (ins VR128:$src1, VR128:$src2),
678 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
681 // Intrinsic operation, reg+mem.
682 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
683 (ins VR128:$src1, ssmem:$src2),
684 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
685 [(set VR128:$dst, (F32Int VR128:$src1,
686 sse_load_f32:$src2))]>;
690 // Arithmetic instructions
691 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
692 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
693 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
694 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
696 /// sse1_fp_binop_rm - Other SSE1 binops
698 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
699 /// instructions for a full-vector intrinsic form. Operations that map
700 /// onto C operators don't use this form since they just use the plain
701 /// vector form instead of having a separate vector intrinsic form.
703 /// This provides a total of eight "instructions".
705 let Constraints = "$src1 = $dst" in {
706 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
710 bit Commutable = 0> {
712 // Scalar operation, reg+reg.
713 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
714 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
715 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
716 let isCommutable = Commutable;
719 // Scalar operation, reg+mem.
720 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
721 (ins FR32:$src1, f32mem:$src2),
722 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
723 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
725 // Vector operation, reg+reg.
726 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
727 (ins VR128:$src1, VR128:$src2),
728 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
729 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
730 let isCommutable = Commutable;
733 // Vector operation, reg+mem.
734 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
735 (ins VR128:$src1, f128mem:$src2),
736 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
737 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
739 // Intrinsic operation, reg+reg.
740 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
741 (ins VR128:$src1, VR128:$src2),
742 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
743 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
744 let isCommutable = Commutable;
747 // Intrinsic operation, reg+mem.
748 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
749 (ins VR128:$src1, ssmem:$src2),
750 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
751 [(set VR128:$dst, (F32Int VR128:$src1,
752 sse_load_f32:$src2))]>;
754 // Vector intrinsic operation, reg+reg.
755 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
756 (ins VR128:$src1, VR128:$src2),
757 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
758 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
759 let isCommutable = Commutable;
762 // Vector intrinsic operation, reg+mem.
763 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
764 (ins VR128:$src1, f128mem:$src2),
765 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
766 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
770 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
771 int_x86_sse_max_ss, int_x86_sse_max_ps>;
772 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
773 int_x86_sse_min_ss, int_x86_sse_min_ps>;
775 //===----------------------------------------------------------------------===//
776 // SSE packed FP Instructions
779 let neverHasSideEffects = 1 in
780 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
781 "movaps\t{$src, $dst|$dst, $src}", []>;
782 let canFoldAsLoad = 1, isReMaterializable = 1 in
783 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
784 "movaps\t{$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
787 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
788 "movaps\t{$src, $dst|$dst, $src}",
789 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
791 let neverHasSideEffects = 1 in
792 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 "movups\t{$src, $dst|$dst, $src}", []>;
794 let canFoldAsLoad = 1, isReMaterializable = 1 in
795 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
796 "movups\t{$src, $dst|$dst, $src}",
797 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
798 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
799 "movups\t{$src, $dst|$dst, $src}",
800 [(store (v4f32 VR128:$src), addr:$dst)]>;
802 // Intrinsic forms of MOVUPS load and store
803 let canFoldAsLoad = 1, isReMaterializable = 1 in
804 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
805 "movups\t{$src, $dst|$dst, $src}",
806 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
807 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
808 "movups\t{$src, $dst|$dst, $src}",
809 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
811 let Constraints = "$src1 = $dst" in {
812 let AddedComplexity = 20 in {
813 def MOVLPSrm : PSI<0x12, MRMSrcMem,
814 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
815 "movlps\t{$src2, $dst|$dst, $src2}",
818 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
819 def MOVHPSrm : PSI<0x16, MRMSrcMem,
820 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
821 "movhps\t{$src2, $dst|$dst, $src2}",
823 (movlhps VR128:$src1,
824 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
826 } // Constraints = "$src1 = $dst"
829 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
830 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
832 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
833 "movlps\t{$src, $dst|$dst, $src}",
834 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
835 (iPTR 0))), addr:$dst)]>;
837 // v2f64 extract element 1 is always custom lowered to unpack high to low
838 // and extract element 0 so the non-store version isn't too horrible.
839 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
840 "movhps\t{$src, $dst|$dst, $src}",
841 [(store (f64 (vector_extract
842 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
843 (undef)), (iPTR 0))), addr:$dst)]>;
845 let Constraints = "$src1 = $dst" in {
846 let AddedComplexity = 20 in {
847 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
848 (ins VR128:$src1, VR128:$src2),
849 "movlhps\t{$src2, $dst|$dst, $src2}",
851 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
853 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 "movhlps\t{$src2, $dst|$dst, $src2}",
857 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
859 } // Constraints = "$src1 = $dst"
861 let AddedComplexity = 20 in {
862 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
863 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
864 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
865 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
872 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
874 /// In addition, we also have a special variant of the scalar form here to
875 /// represent the associated intrinsic operation. This form is unlike the
876 /// plain scalar form, in that it takes an entire vector (instead of a
877 /// scalar) and leaves the top elements undefined.
879 /// And, we have a special variant form for a full-vector intrinsic form.
881 /// These four forms can each have a reg or a mem operand, so there are a
882 /// total of eight "instructions".
884 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
888 bit Commutable = 0> {
889 // Scalar operation, reg.
890 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
892 [(set FR32:$dst, (OpNode FR32:$src))]> {
893 let isCommutable = Commutable;
896 // Scalar operation, mem.
897 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
898 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
899 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
900 Requires<[HasSSE1, OptForSize]>;
902 // Vector operation, reg.
903 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
904 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
905 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
906 let isCommutable = Commutable;
909 // Vector operation, mem.
910 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
912 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
914 // Intrinsic operation, reg.
915 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
916 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
917 [(set VR128:$dst, (F32Int VR128:$src))]> {
918 let isCommutable = Commutable;
921 // Intrinsic operation, mem.
922 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
923 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
924 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
926 // Vector intrinsic operation, reg
927 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
929 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
930 let isCommutable = Commutable;
933 // Vector intrinsic operation, mem
934 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
935 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
936 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
940 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
941 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
943 // Reciprocal approximations. Note that these typically require refinement
944 // in order to obtain suitable precision.
945 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
946 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
947 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
948 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
951 let Constraints = "$src1 = $dst" in {
952 let isCommutable = 1 in {
953 def ANDPSrr : PSI<0x54, MRMSrcReg,
954 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
955 "andps\t{$src2, $dst|$dst, $src2}",
956 [(set VR128:$dst, (v2i64
957 (and VR128:$src1, VR128:$src2)))]>;
958 def ORPSrr : PSI<0x56, MRMSrcReg,
959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
960 "orps\t{$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2i64
962 (or VR128:$src1, VR128:$src2)))]>;
963 def XORPSrr : PSI<0x57, MRMSrcReg,
964 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
965 "xorps\t{$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v2i64
967 (xor VR128:$src1, VR128:$src2)))]>;
970 def ANDPSrm : PSI<0x54, MRMSrcMem,
971 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
972 "andps\t{$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
974 (memopv2i64 addr:$src2)))]>;
975 def ORPSrm : PSI<0x56, MRMSrcMem,
976 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
977 "orps\t{$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
979 (memopv2i64 addr:$src2)))]>;
980 def XORPSrm : PSI<0x57, MRMSrcMem,
981 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
982 "xorps\t{$src2, $dst|$dst, $src2}",
983 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
984 (memopv2i64 addr:$src2)))]>;
985 def ANDNPSrr : PSI<0x55, MRMSrcReg,
986 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
987 "andnps\t{$src2, $dst|$dst, $src2}",
989 (v2i64 (and (xor VR128:$src1,
990 (bc_v2i64 (v4i32 immAllOnesV))),
992 def ANDNPSrm : PSI<0x55, MRMSrcMem,
993 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
994 "andnps\t{$src2, $dst|$dst, $src2}",
996 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
997 (bc_v2i64 (v4i32 immAllOnesV))),
998 (memopv2i64 addr:$src2))))]>;
1001 let Constraints = "$src1 = $dst" in {
1002 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1003 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1004 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1006 VR128:$src, imm:$cc))]>;
1007 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1008 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1009 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1011 (memop addr:$src), imm:$cc))]>;
1013 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1014 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1015 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1016 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1018 // Shuffle and unpack instructions
1019 let Constraints = "$src1 = $dst" in {
1020 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1021 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1022 (outs VR128:$dst), (ins VR128:$src1,
1023 VR128:$src2, i8imm:$src3),
1024 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1026 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1027 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1028 (outs VR128:$dst), (ins VR128:$src1,
1029 f128mem:$src2, i8imm:$src3),
1030 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1033 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1035 let AddedComplexity = 10 in {
1036 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1037 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1038 "unpckhps\t{$src2, $dst|$dst, $src2}",
1040 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1041 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1042 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1043 "unpckhps\t{$src2, $dst|$dst, $src2}",
1045 (v4f32 (unpckh VR128:$src1,
1046 (memopv4f32 addr:$src2))))]>;
1048 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1049 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1050 "unpcklps\t{$src2, $dst|$dst, $src2}",
1052 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1053 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1054 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1055 "unpcklps\t{$src2, $dst|$dst, $src2}",
1057 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1058 } // AddedComplexity
1059 } // Constraints = "$src1 = $dst"
1062 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1063 "movmskps\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1065 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1066 "movmskpd\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1069 // Prefetch intrinsic.
1070 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1071 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1072 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1073 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1074 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1075 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1076 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1077 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1079 // Non-temporal stores
1080 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1081 "movntps\t{$src, $dst|$dst, $src}",
1082 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1084 let AddedComplexity = 400 in { // Prefer non-temporal versions
1085 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1086 "movntps\t{$src, $dst|$dst, $src}",
1087 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1090 "movntdq\t{$src, $dst|$dst, $src}",
1091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1093 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1094 "movnti\t{$src, $dst|$dst, $src}",
1095 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1096 TB, Requires<[HasSSE2]>;
1098 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1099 "movnti\t{$src, $dst|$dst, $src}",
1100 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1101 TB, Requires<[HasSSE2]>;
1104 // Load, store, and memory fence
1105 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1108 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1109 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1110 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1111 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1113 // Alias instructions that map zero vector to pxor / xorp* for sse.
1114 // We set canFoldAsLoad because this can be converted to a constant-pool
1115 // load of an all-zeros value if folding it would be beneficial.
1116 // FIXME: Change encoding to pseudo!
1117 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1118 isCodeGenOnly = 1 in {
1119 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1120 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1121 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1122 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1123 let ExeDomain = SSEPackedInt in
1124 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1125 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1128 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1129 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1130 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1132 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1133 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1135 //===---------------------------------------------------------------------===//
1136 // SSE2 Instructions
1137 //===---------------------------------------------------------------------===//
1139 // Move Instructions. Register-to-register movsd is not used for FR64
1140 // register copies because it's a partial register update; FsMOVAPDrr is
1141 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1142 // because INSERT_SUBREG requires that the insert be implementable in terms of
1143 // a copy, and just mentioned, we don't use movsd for copies.
1144 let Constraints = "$src1 = $dst" in
1145 def MOVSDrr : SDI<0x10, MRMSrcReg,
1146 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1147 "movsd\t{$src2, $dst|$dst, $src2}",
1148 [(set (v2f64 VR128:$dst),
1149 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1151 // Extract the low 64-bit value from one vector and insert it into another.
1152 let AddedComplexity = 15 in
1153 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1154 (MOVSDrr (v2f64 VR128:$src1),
1155 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1157 // Implicitly promote a 64-bit scalar to a vector.
1158 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1159 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1161 // Loading from memory automatically zeroing upper bits.
1162 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1163 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1164 "movsd\t{$src, $dst|$dst, $src}",
1165 [(set FR64:$dst, (loadf64 addr:$src))]>;
1167 // MOVSDrm zeros the high parts of the register; represent this
1168 // with SUBREG_TO_REG.
1169 let AddedComplexity = 20 in {
1170 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1171 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1172 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1173 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1174 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1175 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1176 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1177 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1178 def : Pat<(v2f64 (X86vzload addr:$src)),
1179 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1182 // Store scalar value to memory.
1183 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1184 "movsd\t{$src, $dst|$dst, $src}",
1185 [(store FR64:$src, addr:$dst)]>;
1187 // Extract and store.
1188 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1191 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1193 // Conversion instructions
1194 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1195 "cvttsd2si\t{$src, $dst|$dst, $src}",
1196 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1197 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1198 "cvttsd2si\t{$src, $dst|$dst, $src}",
1199 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1200 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1201 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1202 [(set FR32:$dst, (fround FR64:$src))]>;
1203 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1204 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1205 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1206 Requires<[HasSSE2, OptForSize]>;
1207 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1208 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1209 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1210 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1211 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1212 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1214 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1215 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1216 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1217 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1218 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1219 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1220 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1221 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1222 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1223 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1224 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1225 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1226 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1227 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1228 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1229 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1230 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1231 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1232 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1233 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1235 // SSE2 instructions with XS prefix
1236 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1237 "cvtss2sd\t{$src, $dst|$dst, $src}",
1238 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1239 Requires<[HasSSE2]>;
1240 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1241 "cvtss2sd\t{$src, $dst|$dst, $src}",
1242 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1243 Requires<[HasSSE2, OptForSize]>;
1245 def : Pat<(extloadf32 addr:$src),
1246 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1247 Requires<[HasSSE2, OptForSpeed]>;
1249 // Match intrinsics which expect XMM operand(s).
1250 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1251 "cvtsd2si\t{$src, $dst|$dst, $src}",
1252 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1253 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1254 "cvtsd2si\t{$src, $dst|$dst, $src}",
1255 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1256 (load addr:$src)))]>;
1258 // Match intrinisics which expect MM and XMM operand(s).
1259 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1260 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1261 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1262 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1263 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1264 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1265 (memop addr:$src)))]>;
1266 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1267 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1268 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1269 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1270 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1271 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1272 (memop addr:$src)))]>;
1273 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1274 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1275 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1276 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1277 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1278 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1279 (load addr:$src)))]>;
1281 // Aliases for intrinsics
1282 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1283 "cvttsd2si\t{$src, $dst|$dst, $src}",
1285 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1286 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1287 "cvttsd2si\t{$src, $dst|$dst, $src}",
1288 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1289 (load addr:$src)))]>;
1291 // Comparison instructions
1292 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1293 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1294 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1295 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1297 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1298 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1299 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1302 let Defs = [EFLAGS] in {
1303 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1304 "ucomisd\t{$src2, $src1|$src1, $src2}",
1305 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1306 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1307 "ucomisd\t{$src2, $src1|$src1, $src2}",
1308 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1309 } // Defs = [EFLAGS]
1311 // Aliases to match intrinsics which expect XMM operand(s).
1312 let Constraints = "$src1 = $dst" in {
1313 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1315 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1316 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1317 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1318 VR128:$src, imm:$cc))]>;
1319 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1321 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1322 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1323 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1324 (load addr:$src), imm:$cc))]>;
1327 let Defs = [EFLAGS] in {
1328 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1329 "ucomisd\t{$src2, $src1|$src1, $src2}",
1330 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1332 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1333 "ucomisd\t{$src2, $src1|$src1, $src2}",
1334 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1335 (load addr:$src2)))]>;
1337 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1338 "comisd\t{$src2, $src1|$src1, $src2}",
1339 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1341 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1342 "comisd\t{$src2, $src1|$src1, $src2}",
1343 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1344 (load addr:$src2)))]>;
1345 } // Defs = [EFLAGS]
1347 // Aliases of packed SSE2 instructions for scalar use. These all have names
1348 // that start with 'Fs'.
1350 // Alias instructions that map fld0 to pxor for sse.
1351 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1352 canFoldAsLoad = 1 in
1353 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1354 [(set FR64:$dst, fpimm0)]>,
1355 Requires<[HasSSE2]>, TB, OpSize;
1357 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1359 let neverHasSideEffects = 1 in
1360 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1361 "movapd\t{$src, $dst|$dst, $src}", []>;
1363 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1365 let canFoldAsLoad = 1, isReMaterializable = 1 in
1366 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1367 "movapd\t{$src, $dst|$dst, $src}",
1368 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1370 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1371 let Constraints = "$src1 = $dst" in {
1372 let isCommutable = 1 in {
1373 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1374 (ins FR64:$src1, FR64:$src2),
1375 "andpd\t{$src2, $dst|$dst, $src2}",
1376 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1377 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1378 (ins FR64:$src1, FR64:$src2),
1379 "orpd\t{$src2, $dst|$dst, $src2}",
1380 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1381 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1382 (ins FR64:$src1, FR64:$src2),
1383 "xorpd\t{$src2, $dst|$dst, $src2}",
1384 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1387 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1388 (ins FR64:$src1, f128mem:$src2),
1389 "andpd\t{$src2, $dst|$dst, $src2}",
1390 [(set FR64:$dst, (X86fand FR64:$src1,
1391 (memopfsf64 addr:$src2)))]>;
1392 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1393 (ins FR64:$src1, f128mem:$src2),
1394 "orpd\t{$src2, $dst|$dst, $src2}",
1395 [(set FR64:$dst, (X86for FR64:$src1,
1396 (memopfsf64 addr:$src2)))]>;
1397 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1398 (ins FR64:$src1, f128mem:$src2),
1399 "xorpd\t{$src2, $dst|$dst, $src2}",
1400 [(set FR64:$dst, (X86fxor FR64:$src1,
1401 (memopfsf64 addr:$src2)))]>;
1403 let neverHasSideEffects = 1 in {
1404 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1405 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1406 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1408 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1409 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1410 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1414 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1416 /// In addition, we also have a special variant of the scalar form here to
1417 /// represent the associated intrinsic operation. This form is unlike the
1418 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1419 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1421 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1422 /// six "instructions".
1424 let Constraints = "$src1 = $dst" in {
1425 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1426 SDNode OpNode, Intrinsic F64Int,
1427 bit Commutable = 0> {
1428 // Scalar operation, reg+reg.
1429 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1430 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1431 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1432 let isCommutable = Commutable;
1435 // Scalar operation, reg+mem.
1436 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1437 (ins FR64:$src1, f64mem:$src2),
1438 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1439 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1441 // Vector operation, reg+reg.
1442 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1443 (ins VR128:$src1, VR128:$src2),
1444 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1445 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1446 let isCommutable = Commutable;
1449 // Vector operation, reg+mem.
1450 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1451 (ins VR128:$src1, f128mem:$src2),
1452 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1453 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1455 // Intrinsic operation, reg+reg.
1456 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1457 (ins VR128:$src1, VR128:$src2),
1458 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1459 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1461 // Intrinsic operation, reg+mem.
1462 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1463 (ins VR128:$src1, sdmem:$src2),
1464 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1465 [(set VR128:$dst, (F64Int VR128:$src1,
1466 sse_load_f64:$src2))]>;
1470 // Arithmetic instructions
1471 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1472 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1473 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1474 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1476 /// sse2_fp_binop_rm - Other SSE2 binops
1478 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1479 /// instructions for a full-vector intrinsic form. Operations that map
1480 /// onto C operators don't use this form since they just use the plain
1481 /// vector form instead of having a separate vector intrinsic form.
1483 /// This provides a total of eight "instructions".
1485 let Constraints = "$src1 = $dst" in {
1486 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1490 bit Commutable = 0> {
1492 // Scalar operation, reg+reg.
1493 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1494 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1495 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1496 let isCommutable = Commutable;
1499 // Scalar operation, reg+mem.
1500 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1501 (ins FR64:$src1, f64mem:$src2),
1502 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1503 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1505 // Vector operation, reg+reg.
1506 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1507 (ins VR128:$src1, VR128:$src2),
1508 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1509 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1510 let isCommutable = Commutable;
1513 // Vector operation, reg+mem.
1514 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1515 (ins VR128:$src1, f128mem:$src2),
1516 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1517 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1519 // Intrinsic operation, reg+reg.
1520 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1521 (ins VR128:$src1, VR128:$src2),
1522 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1523 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1524 let isCommutable = Commutable;
1527 // Intrinsic operation, reg+mem.
1528 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1529 (ins VR128:$src1, sdmem:$src2),
1530 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1531 [(set VR128:$dst, (F64Int VR128:$src1,
1532 sse_load_f64:$src2))]>;
1534 // Vector intrinsic operation, reg+reg.
1535 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1536 (ins VR128:$src1, VR128:$src2),
1537 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1538 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1539 let isCommutable = Commutable;
1542 // Vector intrinsic operation, reg+mem.
1543 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1544 (ins VR128:$src1, f128mem:$src2),
1545 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1546 [(set VR128:$dst, (V2F64Int VR128:$src1,
1547 (memopv2f64 addr:$src2)))]>;
1551 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1552 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1553 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1554 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1556 //===---------------------------------------------------------------------===//
1557 // SSE packed FP Instructions
1559 // Move Instructions
1560 let neverHasSideEffects = 1 in
1561 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1562 "movapd\t{$src, $dst|$dst, $src}", []>;
1563 let canFoldAsLoad = 1, isReMaterializable = 1 in
1564 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1565 "movapd\t{$src, $dst|$dst, $src}",
1566 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1568 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1569 "movapd\t{$src, $dst|$dst, $src}",
1570 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1572 let neverHasSideEffects = 1 in
1573 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1574 "movupd\t{$src, $dst|$dst, $src}", []>;
1575 let canFoldAsLoad = 1 in
1576 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1577 "movupd\t{$src, $dst|$dst, $src}",
1578 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1579 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1580 "movupd\t{$src, $dst|$dst, $src}",
1581 [(store (v2f64 VR128:$src), addr:$dst)]>;
1583 // Intrinsic forms of MOVUPD load and store
1584 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1585 "movupd\t{$src, $dst|$dst, $src}",
1586 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1587 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1588 "movupd\t{$src, $dst|$dst, $src}",
1589 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1591 let Constraints = "$src1 = $dst" in {
1592 let AddedComplexity = 20 in {
1593 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1594 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1595 "movlpd\t{$src2, $dst|$dst, $src2}",
1597 (v2f64 (movlp VR128:$src1,
1598 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1599 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1600 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1601 "movhpd\t{$src2, $dst|$dst, $src2}",
1603 (v2f64 (movlhps VR128:$src1,
1604 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1605 } // AddedComplexity
1606 } // Constraints = "$src1 = $dst"
1608 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1609 "movlpd\t{$src, $dst|$dst, $src}",
1610 [(store (f64 (vector_extract (v2f64 VR128:$src),
1611 (iPTR 0))), addr:$dst)]>;
1613 // v2f64 extract element 1 is always custom lowered to unpack high to low
1614 // and extract element 0 so the non-store version isn't too horrible.
1615 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1616 "movhpd\t{$src, $dst|$dst, $src}",
1617 [(store (f64 (vector_extract
1618 (v2f64 (unpckh VR128:$src, (undef))),
1619 (iPTR 0))), addr:$dst)]>;
1621 // SSE2 instructions without OpSize prefix
1622 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1623 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1624 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1625 TB, Requires<[HasSSE2]>;
1626 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1627 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1628 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1629 (bitconvert (memopv2i64 addr:$src))))]>,
1630 TB, Requires<[HasSSE2]>;
1632 // SSE2 instructions with XS prefix
1633 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1634 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1635 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1636 XS, Requires<[HasSSE2]>;
1637 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1638 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1639 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1640 (bitconvert (memopv2i64 addr:$src))))]>,
1641 XS, Requires<[HasSSE2]>;
1643 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1644 "cvtps2dq\t{$src, $dst|$dst, $src}",
1645 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1646 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1647 "cvtps2dq\t{$src, $dst|$dst, $src}",
1648 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1649 (memop addr:$src)))]>;
1650 // SSE2 packed instructions with XS prefix
1651 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1652 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1653 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1654 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1656 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1657 "cvttps2dq\t{$src, $dst|$dst, $src}",
1659 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1660 XS, Requires<[HasSSE2]>;
1661 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1662 "cvttps2dq\t{$src, $dst|$dst, $src}",
1663 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1664 (memop addr:$src)))]>,
1665 XS, Requires<[HasSSE2]>;
1667 // SSE2 packed instructions with XD prefix
1668 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1669 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1670 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1671 XD, Requires<[HasSSE2]>;
1672 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1673 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1674 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1675 (memop addr:$src)))]>,
1676 XD, Requires<[HasSSE2]>;
1678 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1679 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1680 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1681 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1682 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1683 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1684 (memop addr:$src)))]>;
1686 // SSE2 instructions without OpSize prefix
1687 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1688 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1689 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1690 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1692 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1693 "cvtps2pd\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1695 TB, Requires<[HasSSE2]>;
1696 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1697 "cvtps2pd\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1699 (load addr:$src)))]>,
1700 TB, Requires<[HasSSE2]>;
1702 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1704 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1705 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1708 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1709 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1710 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1711 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1712 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1713 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1714 (memop addr:$src)))]>;
1716 // Match intrinsics which expect XMM operand(s).
1717 // Aliases for intrinsics
1718 let Constraints = "$src1 = $dst" in {
1719 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1721 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1724 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1725 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1726 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1727 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1728 (loadi32 addr:$src2)))]>;
1729 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1730 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1731 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1732 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1734 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1735 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1736 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1737 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1738 (load addr:$src2)))]>;
1739 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1740 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1741 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1742 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1743 VR128:$src2))]>, XS,
1744 Requires<[HasSSE2]>;
1745 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1746 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1747 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1748 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1749 (load addr:$src2)))]>, XS,
1750 Requires<[HasSSE2]>;
1755 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1757 /// In addition, we also have a special variant of the scalar form here to
1758 /// represent the associated intrinsic operation. This form is unlike the
1759 /// plain scalar form, in that it takes an entire vector (instead of a
1760 /// scalar) and leaves the top elements undefined.
1762 /// And, we have a special variant form for a full-vector intrinsic form.
1764 /// These four forms can each have a reg or a mem operand, so there are a
1765 /// total of eight "instructions".
1767 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1771 bit Commutable = 0> {
1772 // Scalar operation, reg.
1773 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1774 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1775 [(set FR64:$dst, (OpNode FR64:$src))]> {
1776 let isCommutable = Commutable;
1779 // Scalar operation, mem.
1780 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1781 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1782 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1784 // Vector operation, reg.
1785 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1786 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1788 let isCommutable = Commutable;
1791 // Vector operation, mem.
1792 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1793 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1794 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1796 // Intrinsic operation, reg.
1797 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1798 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1799 [(set VR128:$dst, (F64Int VR128:$src))]> {
1800 let isCommutable = Commutable;
1803 // Intrinsic operation, mem.
1804 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1805 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1806 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1808 // Vector intrinsic operation, reg
1809 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1810 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1811 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1812 let isCommutable = Commutable;
1815 // Vector intrinsic operation, mem
1816 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1817 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1818 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1822 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1823 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1825 // There is no f64 version of the reciprocal approximation instructions.
1828 let Constraints = "$src1 = $dst" in {
1829 let isCommutable = 1 in {
1830 def ANDPDrr : PDI<0x54, MRMSrcReg,
1831 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1832 "andpd\t{$src2, $dst|$dst, $src2}",
1834 (and (bc_v2i64 (v2f64 VR128:$src1)),
1835 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1836 def ORPDrr : PDI<0x56, MRMSrcReg,
1837 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1838 "orpd\t{$src2, $dst|$dst, $src2}",
1840 (or (bc_v2i64 (v2f64 VR128:$src1)),
1841 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1842 def XORPDrr : PDI<0x57, MRMSrcReg,
1843 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1844 "xorpd\t{$src2, $dst|$dst, $src2}",
1846 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1847 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1850 def ANDPDrm : PDI<0x54, MRMSrcMem,
1851 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1852 "andpd\t{$src2, $dst|$dst, $src2}",
1854 (and (bc_v2i64 (v2f64 VR128:$src1)),
1855 (memopv2i64 addr:$src2)))]>;
1856 def ORPDrm : PDI<0x56, MRMSrcMem,
1857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1858 "orpd\t{$src2, $dst|$dst, $src2}",
1860 (or (bc_v2i64 (v2f64 VR128:$src1)),
1861 (memopv2i64 addr:$src2)))]>;
1862 def XORPDrm : PDI<0x57, MRMSrcMem,
1863 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1864 "xorpd\t{$src2, $dst|$dst, $src2}",
1866 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1867 (memopv2i64 addr:$src2)))]>;
1868 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1869 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1870 "andnpd\t{$src2, $dst|$dst, $src2}",
1872 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1873 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1874 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1875 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1876 "andnpd\t{$src2, $dst|$dst, $src2}",
1878 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1879 (memopv2i64 addr:$src2)))]>;
1882 let Constraints = "$src1 = $dst" in {
1883 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1884 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1885 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1886 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1887 VR128:$src, imm:$cc))]>;
1888 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1889 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1890 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1891 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1892 (memop addr:$src), imm:$cc))]>;
1894 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1895 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1896 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1897 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1899 // Shuffle and unpack instructions
1900 let Constraints = "$src1 = $dst" in {
1901 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1902 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1903 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1905 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1906 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1907 (outs VR128:$dst), (ins VR128:$src1,
1908 f128mem:$src2, i8imm:$src3),
1909 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1912 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1914 let AddedComplexity = 10 in {
1915 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1916 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1917 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1919 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1920 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1921 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1922 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1924 (v2f64 (unpckh VR128:$src1,
1925 (memopv2f64 addr:$src2))))]>;
1927 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1928 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1929 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1931 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1932 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1933 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1934 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1936 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1937 } // AddedComplexity
1938 } // Constraints = "$src1 = $dst"
1941 //===---------------------------------------------------------------------===//
1942 // SSE integer instructions
1943 let ExeDomain = SSEPackedInt in {
1945 // Move Instructions
1946 let neverHasSideEffects = 1 in
1947 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1948 "movdqa\t{$src, $dst|$dst, $src}", []>;
1949 let canFoldAsLoad = 1, mayLoad = 1 in
1950 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1951 "movdqa\t{$src, $dst|$dst, $src}",
1952 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1954 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1955 "movdqa\t{$src, $dst|$dst, $src}",
1956 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1957 let canFoldAsLoad = 1, mayLoad = 1 in
1958 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1959 "movdqu\t{$src, $dst|$dst, $src}",
1960 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1961 XS, Requires<[HasSSE2]>;
1963 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1964 "movdqu\t{$src, $dst|$dst, $src}",
1965 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1966 XS, Requires<[HasSSE2]>;
1968 // Intrinsic forms of MOVDQU load and store
1969 let canFoldAsLoad = 1 in
1970 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1971 "movdqu\t{$src, $dst|$dst, $src}",
1972 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1973 XS, Requires<[HasSSE2]>;
1974 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1975 "movdqu\t{$src, $dst|$dst, $src}",
1976 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1977 XS, Requires<[HasSSE2]>;
1979 let Constraints = "$src1 = $dst" in {
1981 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1982 bit Commutable = 0> {
1983 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1984 (ins VR128:$src1, VR128:$src2),
1985 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1986 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1987 let isCommutable = Commutable;
1989 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1990 (ins VR128:$src1, i128mem:$src2),
1991 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1992 [(set VR128:$dst, (IntId VR128:$src1,
1993 (bitconvert (memopv2i64
1997 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1999 Intrinsic IntId, Intrinsic IntId2> {
2000 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2001 (ins VR128:$src1, VR128:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2003 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2004 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2005 (ins VR128:$src1, i128mem:$src2),
2006 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2007 [(set VR128:$dst, (IntId VR128:$src1,
2008 (bitconvert (memopv2i64 addr:$src2))))]>;
2009 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2010 (ins VR128:$src1, i32i8imm:$src2),
2011 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2012 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2015 /// PDI_binop_rm - Simple SSE2 binary operator.
2016 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2017 ValueType OpVT, bit Commutable = 0> {
2018 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2019 (ins VR128:$src1, VR128:$src2),
2020 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2021 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2022 let isCommutable = Commutable;
2024 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2025 (ins VR128:$src1, i128mem:$src2),
2026 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2027 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2028 (bitconvert (memopv2i64 addr:$src2)))))]>;
2031 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2033 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2034 /// to collapse (bitconvert VT to VT) into its operand.
2036 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2037 bit Commutable = 0> {
2038 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2039 (ins VR128:$src1, VR128:$src2),
2040 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2041 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2042 let isCommutable = Commutable;
2044 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2045 (ins VR128:$src1, i128mem:$src2),
2046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2047 [(set VR128:$dst, (OpNode VR128:$src1,
2048 (memopv2i64 addr:$src2)))]>;
2051 } // Constraints = "$src1 = $dst"
2052 } // ExeDomain = SSEPackedInt
2054 // 128-bit Integer Arithmetic
2056 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2057 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2058 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2059 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2061 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2062 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2063 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2064 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2066 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2067 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2068 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2069 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2071 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2072 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2073 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2074 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2076 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2078 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2079 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2080 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2082 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2084 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2085 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2088 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2089 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2090 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2091 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2092 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2095 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2096 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2097 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2098 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2099 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2100 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2102 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2103 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2104 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2105 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2106 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2107 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2109 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2110 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2111 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2112 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2114 // 128-bit logical shifts.
2115 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2116 ExeDomain = SSEPackedInt in {
2117 def PSLLDQri : PDIi8<0x73, MRM7r,
2118 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2119 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2120 def PSRLDQri : PDIi8<0x73, MRM3r,
2121 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2122 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2123 // PSRADQri doesn't exist in SSE[1-3].
2126 let Predicates = [HasSSE2] in {
2127 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2128 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2129 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2130 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2131 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2132 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2133 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2134 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2135 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2136 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2138 // Shift up / down and insert zero's.
2139 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2140 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2141 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2142 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2146 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2147 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2148 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2150 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2151 def PANDNrr : PDI<0xDF, MRMSrcReg,
2152 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2153 "pandn\t{$src2, $dst|$dst, $src2}",
2154 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2157 def PANDNrm : PDI<0xDF, MRMSrcMem,
2158 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2159 "pandn\t{$src2, $dst|$dst, $src2}",
2160 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2161 (memopv2i64 addr:$src2))))]>;
2164 // SSE2 Integer comparison
2165 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2166 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2167 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2168 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2169 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2170 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2172 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2173 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2174 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2175 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2176 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2177 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2178 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2179 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2180 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2181 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2182 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2183 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2185 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2186 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2187 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2188 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2189 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2190 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2191 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2192 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2193 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2194 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2195 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2196 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2199 // Pack instructions
2200 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2201 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2202 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2204 let ExeDomain = SSEPackedInt in {
2206 // Shuffle and unpack instructions
2207 let AddedComplexity = 5 in {
2208 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2209 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2210 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2211 [(set VR128:$dst, (v4i32 (pshufd:$src2
2212 VR128:$src1, (undef))))]>;
2213 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2214 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2215 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2216 [(set VR128:$dst, (v4i32 (pshufd:$src2
2217 (bc_v4i32 (memopv2i64 addr:$src1)),
2221 // SSE2 with ImmT == Imm8 and XS prefix.
2222 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2223 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2224 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2225 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2227 XS, Requires<[HasSSE2]>;
2228 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2229 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2230 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2231 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2232 (bc_v8i16 (memopv2i64 addr:$src1)),
2234 XS, Requires<[HasSSE2]>;
2236 // SSE2 with ImmT == Imm8 and XD prefix.
2237 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2238 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2239 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2240 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2242 XD, Requires<[HasSSE2]>;
2243 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2244 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2245 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2246 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2247 (bc_v8i16 (memopv2i64 addr:$src1)),
2249 XD, Requires<[HasSSE2]>;
2252 let Constraints = "$src1 = $dst" in {
2253 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2254 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2255 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2257 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2258 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2259 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2260 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2262 (unpckl VR128:$src1,
2263 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2264 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2265 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2266 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2268 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2269 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2270 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2271 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2273 (unpckl VR128:$src1,
2274 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2275 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2276 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2277 "punpckldq\t{$src2, $dst|$dst, $src2}",
2279 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2280 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2281 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2282 "punpckldq\t{$src2, $dst|$dst, $src2}",
2284 (unpckl VR128:$src1,
2285 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2286 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2287 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2288 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2290 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2291 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2292 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2293 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2295 (v2i64 (unpckl VR128:$src1,
2296 (memopv2i64 addr:$src2))))]>;
2298 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2299 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2300 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2302 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2303 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2304 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2305 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2307 (unpckh VR128:$src1,
2308 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2309 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2310 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2311 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2313 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2314 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2315 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2316 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2318 (unpckh VR128:$src1,
2319 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2320 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2321 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2322 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2324 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2325 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2326 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2327 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2329 (unpckh VR128:$src1,
2330 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2331 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2332 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2333 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2335 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2336 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2337 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2338 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2340 (v2i64 (unpckh VR128:$src1,
2341 (memopv2i64 addr:$src2))))]>;
2345 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2346 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2347 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2348 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2350 let Constraints = "$src1 = $dst" in {
2351 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2352 (outs VR128:$dst), (ins VR128:$src1,
2353 GR32:$src2, i32i8imm:$src3),
2354 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2356 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2357 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2358 (outs VR128:$dst), (ins VR128:$src1,
2359 i16mem:$src2, i32i8imm:$src3),
2360 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2362 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2367 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2368 "pmovmskb\t{$src, $dst|$dst, $src}",
2369 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2371 // Conditional store
2373 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2374 "maskmovdqu\t{$mask, $src|$src, $mask}",
2375 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2378 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2379 "maskmovdqu\t{$mask, $src|$src, $mask}",
2380 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2382 } // ExeDomain = SSEPackedInt
2384 // Non-temporal stores
2385 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2386 "movntpd\t{$src, $dst|$dst, $src}",
2387 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2388 let ExeDomain = SSEPackedInt in
2389 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2390 "movntdq\t{$src, $dst|$dst, $src}",
2391 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2392 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2393 "movnti\t{$src, $dst|$dst, $src}",
2394 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2395 TB, Requires<[HasSSE2]>;
2397 let AddedComplexity = 400 in { // Prefer non-temporal versions
2398 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2399 "movntpd\t{$src, $dst|$dst, $src}",
2400 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2402 let ExeDomain = SSEPackedInt in
2403 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2404 "movntdq\t{$src, $dst|$dst, $src}",
2405 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2409 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2410 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2411 TB, Requires<[HasSSE2]>;
2413 // Load, store, and memory fence
2414 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2415 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2416 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2417 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2419 //TODO: custom lower this so as to never even generate the noop
2420 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2422 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2423 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2424 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2427 // Alias instructions that map zero vector to pxor / xorp* for sse.
2428 // We set canFoldAsLoad because this can be converted to a constant-pool
2429 // load of an all-ones value if folding it would be beneficial.
2430 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2431 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2432 // FIXME: Change encoding to pseudo.
2433 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2434 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2436 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2437 "movd\t{$src, $dst|$dst, $src}",
2439 (v4i32 (scalar_to_vector GR32:$src)))]>;
2440 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2441 "movd\t{$src, $dst|$dst, $src}",
2443 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2445 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2446 "movd\t{$src, $dst|$dst, $src}",
2447 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2449 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2450 "movd\t{$src, $dst|$dst, $src}",
2451 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2453 // SSE2 instructions with XS prefix
2454 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2455 "movq\t{$src, $dst|$dst, $src}",
2457 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2458 Requires<[HasSSE2]>;
2459 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2460 "movq\t{$src, $dst|$dst, $src}",
2461 [(store (i64 (vector_extract (v2i64 VR128:$src),
2462 (iPTR 0))), addr:$dst)]>;
2464 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2465 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2467 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2468 "movd\t{$src, $dst|$dst, $src}",
2469 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2471 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2472 "movd\t{$src, $dst|$dst, $src}",
2473 [(store (i32 (vector_extract (v4i32 VR128:$src),
2474 (iPTR 0))), addr:$dst)]>;
2476 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2477 "movd\t{$src, $dst|$dst, $src}",
2478 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2479 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2480 "movd\t{$src, $dst|$dst, $src}",
2481 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2483 // Store / copy lower 64-bits of a XMM register.
2484 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2485 "movq\t{$src, $dst|$dst, $src}",
2486 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2488 // movd / movq to XMM register zero-extends
2489 let AddedComplexity = 15 in {
2490 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2491 "movd\t{$src, $dst|$dst, $src}",
2492 [(set VR128:$dst, (v4i32 (X86vzmovl
2493 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2494 // This is X86-64 only.
2495 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2496 "mov{d|q}\t{$src, $dst|$dst, $src}",
2497 [(set VR128:$dst, (v2i64 (X86vzmovl
2498 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2501 let AddedComplexity = 20 in {
2502 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2503 "movd\t{$src, $dst|$dst, $src}",
2505 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2506 (loadi32 addr:$src))))))]>;
2508 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2509 (MOVZDI2PDIrm addr:$src)>;
2510 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2511 (MOVZDI2PDIrm addr:$src)>;
2512 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2513 (MOVZDI2PDIrm addr:$src)>;
2515 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2516 "movq\t{$src, $dst|$dst, $src}",
2518 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2519 (loadi64 addr:$src))))))]>, XS,
2520 Requires<[HasSSE2]>;
2522 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2523 (MOVZQI2PQIrm addr:$src)>;
2524 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2525 (MOVZQI2PQIrm addr:$src)>;
2526 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2529 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2530 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2531 let AddedComplexity = 15 in
2532 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2533 "movq\t{$src, $dst|$dst, $src}",
2534 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2535 XS, Requires<[HasSSE2]>;
2537 let AddedComplexity = 20 in {
2538 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2539 "movq\t{$src, $dst|$dst, $src}",
2540 [(set VR128:$dst, (v2i64 (X86vzmovl
2541 (loadv2i64 addr:$src))))]>,
2542 XS, Requires<[HasSSE2]>;
2544 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2545 (MOVZPQILo2PQIrm addr:$src)>;
2548 // Instructions for the disassembler
2549 // xr = XMM register
2552 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2553 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2555 //===---------------------------------------------------------------------===//
2556 // SSE3 Instructions
2557 //===---------------------------------------------------------------------===//
2559 // Move Instructions
2560 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2561 "movshdup\t{$src, $dst|$dst, $src}",
2562 [(set VR128:$dst, (v4f32 (movshdup
2563 VR128:$src, (undef))))]>;
2564 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2565 "movshdup\t{$src, $dst|$dst, $src}",
2566 [(set VR128:$dst, (movshdup
2567 (memopv4f32 addr:$src), (undef)))]>;
2569 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2570 "movsldup\t{$src, $dst|$dst, $src}",
2571 [(set VR128:$dst, (v4f32 (movsldup
2572 VR128:$src, (undef))))]>;
2573 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2574 "movsldup\t{$src, $dst|$dst, $src}",
2575 [(set VR128:$dst, (movsldup
2576 (memopv4f32 addr:$src), (undef)))]>;
2578 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2579 "movddup\t{$src, $dst|$dst, $src}",
2580 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2581 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2582 "movddup\t{$src, $dst|$dst, $src}",
2584 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2587 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2589 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2591 let AddedComplexity = 5 in {
2592 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2593 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2594 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2595 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2596 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2597 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2598 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2599 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2603 let Constraints = "$src1 = $dst" in {
2604 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2605 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2606 "addsubps\t{$src2, $dst|$dst, $src2}",
2607 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2609 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2610 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2611 "addsubps\t{$src2, $dst|$dst, $src2}",
2612 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2613 (memop addr:$src2)))]>;
2614 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2615 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2616 "addsubpd\t{$src2, $dst|$dst, $src2}",
2617 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2619 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2620 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2621 "addsubpd\t{$src2, $dst|$dst, $src2}",
2622 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2623 (memop addr:$src2)))]>;
2626 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2627 "lddqu\t{$src, $dst|$dst, $src}",
2628 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2631 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2632 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2635 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2636 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2638 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2639 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2640 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2642 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2643 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2644 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2645 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2646 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2648 let Constraints = "$src1 = $dst" in {
2649 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2650 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2651 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2652 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2653 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2654 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2655 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2656 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2659 // Thread synchronization
2660 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2661 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2662 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2663 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2665 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2666 let AddedComplexity = 15 in
2667 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2668 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2669 let AddedComplexity = 20 in
2670 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2671 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2673 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2674 let AddedComplexity = 15 in
2675 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2676 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2677 let AddedComplexity = 20 in
2678 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2679 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2681 //===---------------------------------------------------------------------===//
2682 // SSSE3 Instructions
2683 //===---------------------------------------------------------------------===//
2685 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2686 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2687 Intrinsic IntId64, Intrinsic IntId128> {
2688 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2689 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2690 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2692 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2693 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2695 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2697 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2700 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2703 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2705 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2708 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2711 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2712 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2713 Intrinsic IntId64, Intrinsic IntId128> {
2714 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2717 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2719 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2721 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2724 (bitconvert (memopv4i16 addr:$src))))]>;
2726 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2728 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2729 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2732 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2734 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2737 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2740 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2741 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2742 Intrinsic IntId64, Intrinsic IntId128> {
2743 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2746 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2748 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2753 (bitconvert (memopv2i32 addr:$src))))]>;
2755 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2757 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2758 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2761 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2766 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2769 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2770 int_x86_ssse3_pabs_b,
2771 int_x86_ssse3_pabs_b_128>;
2772 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2773 int_x86_ssse3_pabs_w,
2774 int_x86_ssse3_pabs_w_128>;
2775 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2776 int_x86_ssse3_pabs_d,
2777 int_x86_ssse3_pabs_d_128>;
2779 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2780 let Constraints = "$src1 = $dst" in {
2781 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2782 Intrinsic IntId64, Intrinsic IntId128,
2783 bit Commutable = 0> {
2784 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2785 (ins VR64:$src1, VR64:$src2),
2786 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2787 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2788 let isCommutable = Commutable;
2790 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2791 (ins VR64:$src1, i64mem:$src2),
2792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2794 (IntId64 VR64:$src1,
2795 (bitconvert (memopv8i8 addr:$src2))))]>;
2797 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2798 (ins VR128:$src1, VR128:$src2),
2799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2800 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2802 let isCommutable = Commutable;
2804 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2805 (ins VR128:$src1, i128mem:$src2),
2806 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2808 (IntId128 VR128:$src1,
2809 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2813 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2814 let Constraints = "$src1 = $dst" in {
2815 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2816 Intrinsic IntId64, Intrinsic IntId128,
2817 bit Commutable = 0> {
2818 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2819 (ins VR64:$src1, VR64:$src2),
2820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2821 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2822 let isCommutable = Commutable;
2824 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2825 (ins VR64:$src1, i64mem:$src2),
2826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2828 (IntId64 VR64:$src1,
2829 (bitconvert (memopv4i16 addr:$src2))))]>;
2831 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2832 (ins VR128:$src1, VR128:$src2),
2833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2834 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2836 let isCommutable = Commutable;
2838 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2839 (ins VR128:$src1, i128mem:$src2),
2840 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2842 (IntId128 VR128:$src1,
2843 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2847 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2848 let Constraints = "$src1 = $dst" in {
2849 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2850 Intrinsic IntId64, Intrinsic IntId128,
2851 bit Commutable = 0> {
2852 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2853 (ins VR64:$src1, VR64:$src2),
2854 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2855 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2856 let isCommutable = Commutable;
2858 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2859 (ins VR64:$src1, i64mem:$src2),
2860 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2862 (IntId64 VR64:$src1,
2863 (bitconvert (memopv2i32 addr:$src2))))]>;
2865 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2866 (ins VR128:$src1, VR128:$src2),
2867 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2868 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2870 let isCommutable = Commutable;
2872 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2873 (ins VR128:$src1, i128mem:$src2),
2874 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2876 (IntId128 VR128:$src1,
2877 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2881 let ImmT = NoImm in { // None of these have i8 immediate fields.
2882 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2883 int_x86_ssse3_phadd_w,
2884 int_x86_ssse3_phadd_w_128>;
2885 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2886 int_x86_ssse3_phadd_d,
2887 int_x86_ssse3_phadd_d_128>;
2888 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2889 int_x86_ssse3_phadd_sw,
2890 int_x86_ssse3_phadd_sw_128>;
2891 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2892 int_x86_ssse3_phsub_w,
2893 int_x86_ssse3_phsub_w_128>;
2894 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2895 int_x86_ssse3_phsub_d,
2896 int_x86_ssse3_phsub_d_128>;
2897 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2898 int_x86_ssse3_phsub_sw,
2899 int_x86_ssse3_phsub_sw_128>;
2900 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2901 int_x86_ssse3_pmadd_ub_sw,
2902 int_x86_ssse3_pmadd_ub_sw_128>;
2903 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2904 int_x86_ssse3_pmul_hr_sw,
2905 int_x86_ssse3_pmul_hr_sw_128, 1>;
2907 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2908 int_x86_ssse3_pshuf_b,
2909 int_x86_ssse3_pshuf_b_128>;
2910 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2911 int_x86_ssse3_psign_b,
2912 int_x86_ssse3_psign_b_128>;
2913 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2914 int_x86_ssse3_psign_w,
2915 int_x86_ssse3_psign_w_128>;
2916 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2917 int_x86_ssse3_psign_d,
2918 int_x86_ssse3_psign_d_128>;
2921 // palignr patterns.
2922 let Constraints = "$src1 = $dst" in {
2923 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2924 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2925 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2927 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2928 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2929 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2932 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2933 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2934 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2936 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2937 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2938 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2942 let AddedComplexity = 5 in {
2944 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2945 (PALIGNR64rr VR64:$src2, VR64:$src1,
2946 (SHUFFLE_get_palign_imm VR64:$src3))>,
2947 Requires<[HasSSSE3]>;
2948 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2949 (PALIGNR64rr VR64:$src2, VR64:$src1,
2950 (SHUFFLE_get_palign_imm VR64:$src3))>,
2951 Requires<[HasSSSE3]>;
2952 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2953 (PALIGNR64rr VR64:$src2, VR64:$src1,
2954 (SHUFFLE_get_palign_imm VR64:$src3))>,
2955 Requires<[HasSSSE3]>;
2956 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2957 (PALIGNR64rr VR64:$src2, VR64:$src1,
2958 (SHUFFLE_get_palign_imm VR64:$src3))>,
2959 Requires<[HasSSSE3]>;
2960 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2961 (PALIGNR64rr VR64:$src2, VR64:$src1,
2962 (SHUFFLE_get_palign_imm VR64:$src3))>,
2963 Requires<[HasSSSE3]>;
2965 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2966 (PALIGNR128rr VR128:$src2, VR128:$src1,
2967 (SHUFFLE_get_palign_imm VR128:$src3))>,
2968 Requires<[HasSSSE3]>;
2969 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2970 (PALIGNR128rr VR128:$src2, VR128:$src1,
2971 (SHUFFLE_get_palign_imm VR128:$src3))>,
2972 Requires<[HasSSSE3]>;
2973 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2974 (PALIGNR128rr VR128:$src2, VR128:$src1,
2975 (SHUFFLE_get_palign_imm VR128:$src3))>,
2976 Requires<[HasSSSE3]>;
2977 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2978 (PALIGNR128rr VR128:$src2, VR128:$src1,
2979 (SHUFFLE_get_palign_imm VR128:$src3))>,
2980 Requires<[HasSSSE3]>;
2983 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2984 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2985 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2986 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2988 //===---------------------------------------------------------------------===//
2989 // Non-Instruction Patterns
2990 //===---------------------------------------------------------------------===//
2992 // extload f32 -> f64. This matches load+fextend because we have a hack in
2993 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2995 // Since these loads aren't folded into the fextend, we have to match it
2997 let Predicates = [HasSSE2] in
2998 def : Pat<(fextend (loadf32 addr:$src)),
2999 (CVTSS2SDrm addr:$src)>;
3002 let Predicates = [HasSSE2] in {
3003 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3004 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3005 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3006 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3007 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3008 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3009 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3010 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3011 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3012 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3013 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3014 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3015 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3016 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3017 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3018 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3019 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3020 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3021 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3022 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3023 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3024 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3025 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3026 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3027 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3028 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3029 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3030 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3031 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3032 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3035 // Move scalar to XMM zero-extended
3036 // movd to XMM register zero-extends
3037 let AddedComplexity = 15 in {
3038 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3039 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3040 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3041 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3042 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3043 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3044 (MOVSSrr (v4f32 (V_SET0PS)),
3045 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3046 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3047 (MOVSSrr (v4i32 (V_SET0PI)),
3048 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3051 // Splat v2f64 / v2i64
3052 let AddedComplexity = 10 in {
3053 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3054 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3055 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3056 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3057 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3058 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3059 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3060 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3063 // Special unary SHUFPSrri case.
3064 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3065 (SHUFPSrri VR128:$src1, VR128:$src1,
3066 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3067 let AddedComplexity = 5 in
3068 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3069 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3070 Requires<[HasSSE2]>;
3071 // Special unary SHUFPDrri case.
3072 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3073 (SHUFPDrri VR128:$src1, VR128:$src1,
3074 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3075 Requires<[HasSSE2]>;
3076 // Special unary SHUFPDrri case.
3077 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3078 (SHUFPDrri VR128:$src1, VR128:$src1,
3079 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3080 Requires<[HasSSE2]>;
3081 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3082 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3083 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3084 Requires<[HasSSE2]>;
3086 // Special binary v4i32 shuffle cases with SHUFPS.
3087 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3088 (SHUFPSrri VR128:$src1, VR128:$src2,
3089 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3090 Requires<[HasSSE2]>;
3091 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3092 (SHUFPSrmi VR128:$src1, addr:$src2,
3093 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3094 Requires<[HasSSE2]>;
3095 // Special binary v2i64 shuffle cases using SHUFPDrri.
3096 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3097 (SHUFPDrri VR128:$src1, VR128:$src2,
3098 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3099 Requires<[HasSSE2]>;
3101 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3102 let AddedComplexity = 15 in {
3103 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3104 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3105 Requires<[OptForSpeed, HasSSE2]>;
3106 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3107 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3108 Requires<[OptForSpeed, HasSSE2]>;
3110 let AddedComplexity = 10 in {
3111 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3112 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3113 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3114 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3115 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3116 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3117 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3118 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3121 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3122 let AddedComplexity = 15 in {
3123 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3124 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3125 Requires<[OptForSpeed, HasSSE2]>;
3126 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3127 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3128 Requires<[OptForSpeed, HasSSE2]>;
3130 let AddedComplexity = 10 in {
3131 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3132 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3133 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3134 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3135 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3136 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3137 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3138 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3141 let AddedComplexity = 20 in {
3142 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3143 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3144 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3146 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3147 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3148 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3150 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3151 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3152 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3153 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3154 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3157 let AddedComplexity = 20 in {
3158 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3159 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3160 (MOVLPSrm VR128:$src1, addr:$src2)>;
3161 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3162 (MOVLPDrm VR128:$src1, addr:$src2)>;
3163 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3164 (MOVLPSrm VR128:$src1, addr:$src2)>;
3165 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3166 (MOVLPDrm VR128:$src1, addr:$src2)>;
3169 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3170 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3171 (MOVLPSmr addr:$src1, VR128:$src2)>;
3172 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3173 (MOVLPDmr addr:$src1, VR128:$src2)>;
3174 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3176 (MOVLPSmr addr:$src1, VR128:$src2)>;
3177 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3178 (MOVLPDmr addr:$src1, VR128:$src2)>;
3180 let AddedComplexity = 15 in {
3181 // Setting the lowest element in the vector.
3182 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3183 (MOVSSrr (v4i32 VR128:$src1),
3184 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3185 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3186 (MOVSDrr (v2i64 VR128:$src1),
3187 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3189 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3190 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3191 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3192 Requires<[HasSSE2]>;
3193 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3194 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3195 Requires<[HasSSE2]>;
3198 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3199 // fall back to this for SSE1)
3200 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3201 (SHUFPSrri VR128:$src2, VR128:$src1,
3202 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3204 // Set lowest element and zero upper elements.
3205 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3206 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3208 // Some special case pandn patterns.
3209 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3211 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3212 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3214 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3215 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3217 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3219 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3220 (memop addr:$src2))),
3221 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3222 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3223 (memop addr:$src2))),
3224 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3225 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3226 (memop addr:$src2))),
3227 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3229 // vector -> vector casts
3230 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3231 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3232 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3233 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3234 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3235 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3236 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3237 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3239 // Use movaps / movups for SSE integer load / store (one byte shorter).
3240 def : Pat<(alignedloadv4i32 addr:$src),
3241 (MOVAPSrm addr:$src)>;
3242 def : Pat<(loadv4i32 addr:$src),
3243 (MOVUPSrm addr:$src)>;
3244 def : Pat<(alignedloadv2i64 addr:$src),
3245 (MOVAPSrm addr:$src)>;
3246 def : Pat<(loadv2i64 addr:$src),
3247 (MOVUPSrm addr:$src)>;
3249 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3250 (MOVAPSmr addr:$dst, VR128:$src)>;
3251 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3252 (MOVAPSmr addr:$dst, VR128:$src)>;
3253 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3254 (MOVAPSmr addr:$dst, VR128:$src)>;
3255 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3256 (MOVAPSmr addr:$dst, VR128:$src)>;
3257 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3258 (MOVUPSmr addr:$dst, VR128:$src)>;
3259 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3260 (MOVUPSmr addr:$dst, VR128:$src)>;
3261 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3262 (MOVUPSmr addr:$dst, VR128:$src)>;
3263 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3264 (MOVUPSmr addr:$dst, VR128:$src)>;
3266 //===----------------------------------------------------------------------===//
3267 // SSE4.1 Instructions
3268 //===----------------------------------------------------------------------===//
3270 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3273 Intrinsic V2F64Int> {
3274 // Intrinsic operation, reg.
3275 // Vector intrinsic operation, reg
3276 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3277 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3278 !strconcat(OpcodeStr,
3279 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3280 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3283 // Vector intrinsic operation, mem
3284 def PSm_Int : Ii8<opcps, MRMSrcMem,
3285 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3286 !strconcat(OpcodeStr,
3287 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3289 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3291 Requires<[HasSSE41]>;
3293 // Vector intrinsic operation, reg
3294 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3295 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3296 !strconcat(OpcodeStr,
3297 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3298 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3301 // Vector intrinsic operation, mem
3302 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3303 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3304 !strconcat(OpcodeStr,
3305 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3307 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3311 let Constraints = "$src1 = $dst" in {
3312 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3316 // Intrinsic operation, reg.
3317 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3319 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3320 !strconcat(OpcodeStr,
3321 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3323 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3326 // Intrinsic operation, mem.
3327 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3329 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3330 !strconcat(OpcodeStr,
3331 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3333 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3336 // Intrinsic operation, reg.
3337 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3339 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3340 !strconcat(OpcodeStr,
3341 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3343 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3346 // Intrinsic operation, mem.
3347 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3349 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3350 !strconcat(OpcodeStr,
3351 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3353 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3358 // FP round - roundss, roundps, roundsd, roundpd
3359 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3360 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3361 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3362 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3364 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3365 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3366 Intrinsic IntId128> {
3367 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3370 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3371 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3373 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3376 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3379 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3380 int_x86_sse41_phminposuw>;
3382 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3383 let Constraints = "$src1 = $dst" in {
3384 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3385 Intrinsic IntId128, bit Commutable = 0> {
3386 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3387 (ins VR128:$src1, VR128:$src2),
3388 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3389 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3391 let isCommutable = Commutable;
3393 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3394 (ins VR128:$src1, i128mem:$src2),
3395 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3397 (IntId128 VR128:$src1,
3398 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3402 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3403 int_x86_sse41_pcmpeqq, 1>;
3404 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3405 int_x86_sse41_packusdw, 0>;
3406 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3407 int_x86_sse41_pminsb, 1>;
3408 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3409 int_x86_sse41_pminsd, 1>;
3410 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3411 int_x86_sse41_pminud, 1>;
3412 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3413 int_x86_sse41_pminuw, 1>;
3414 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3415 int_x86_sse41_pmaxsb, 1>;
3416 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3417 int_x86_sse41_pmaxsd, 1>;
3418 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3419 int_x86_sse41_pmaxud, 1>;
3420 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3421 int_x86_sse41_pmaxuw, 1>;
3423 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3425 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3426 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3427 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3428 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3430 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3431 let Constraints = "$src1 = $dst" in {
3432 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3433 SDNode OpNode, Intrinsic IntId128,
3434 bit Commutable = 0> {
3435 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3436 (ins VR128:$src1, VR128:$src2),
3437 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3438 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3439 VR128:$src2))]>, OpSize {
3440 let isCommutable = Commutable;
3442 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3443 (ins VR128:$src1, VR128:$src2),
3444 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3445 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3447 let isCommutable = Commutable;
3449 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3450 (ins VR128:$src1, i128mem:$src2),
3451 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3453 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3454 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3455 (ins VR128:$src1, i128mem:$src2),
3456 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3458 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3463 /// SS48I_binop_rm - Simple SSE41 binary operator.
3464 let Constraints = "$src1 = $dst" in {
3465 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3466 ValueType OpVT, bit Commutable = 0> {
3467 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3468 (ins VR128:$src1, VR128:$src2),
3469 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3470 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3472 let isCommutable = Commutable;
3474 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3475 (ins VR128:$src1, i128mem:$src2),
3476 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3477 [(set VR128:$dst, (OpNode VR128:$src1,
3478 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3483 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3485 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3486 let Constraints = "$src1 = $dst" in {
3487 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3488 Intrinsic IntId128, bit Commutable = 0> {
3489 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3490 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3491 !strconcat(OpcodeStr,
3492 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3494 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3496 let isCommutable = Commutable;
3498 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3499 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3500 !strconcat(OpcodeStr,
3501 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3503 (IntId128 VR128:$src1,
3504 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3509 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3510 int_x86_sse41_blendps, 0>;
3511 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3512 int_x86_sse41_blendpd, 0>;
3513 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3514 int_x86_sse41_pblendw, 0>;
3515 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3516 int_x86_sse41_dpps, 1>;
3517 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3518 int_x86_sse41_dppd, 1>;
3519 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3520 int_x86_sse41_mpsadbw, 0>;
3523 /// SS41I_ternary_int - SSE 4.1 ternary operator
3524 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3525 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3526 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3527 (ins VR128:$src1, VR128:$src2),
3528 !strconcat(OpcodeStr,
3529 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3530 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3533 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3534 (ins VR128:$src1, i128mem:$src2),
3535 !strconcat(OpcodeStr,
3536 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3539 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3543 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3544 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3545 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3548 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3549 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3551 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3553 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3556 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3560 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3561 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3562 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3563 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3564 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3565 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3567 // Common patterns involving scalar load.
3568 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3569 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3570 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3571 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3573 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3574 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3575 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3576 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3578 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3579 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3580 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3581 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3583 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3584 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3585 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3586 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3588 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3589 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3590 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3591 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3593 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3594 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3595 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3596 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3599 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3600 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3602 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3604 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3607 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3611 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3612 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3613 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3614 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3616 // Common patterns involving scalar load
3617 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3618 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3619 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3620 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3622 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3623 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3624 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3625 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3628 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3629 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3631 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3633 // Expecting a i16 load any extended to i32 value.
3634 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3636 [(set VR128:$dst, (IntId (bitconvert
3637 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3641 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3642 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3644 // Common patterns involving scalar load
3645 def : Pat<(int_x86_sse41_pmovsxbq
3646 (bitconvert (v4i32 (X86vzmovl
3647 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3648 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3650 def : Pat<(int_x86_sse41_pmovzxbq
3651 (bitconvert (v4i32 (X86vzmovl
3652 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3653 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3656 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3657 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3658 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3659 (ins VR128:$src1, i32i8imm:$src2),
3660 !strconcat(OpcodeStr,
3661 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3662 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3664 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3665 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3666 !strconcat(OpcodeStr,
3667 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3670 // There's an AssertZext in the way of writing the store pattern
3671 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3674 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3677 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3678 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3679 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3680 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3681 !strconcat(OpcodeStr,
3682 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3685 // There's an AssertZext in the way of writing the store pattern
3686 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3689 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3692 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3693 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3694 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3695 (ins VR128:$src1, i32i8imm:$src2),
3696 !strconcat(OpcodeStr,
3697 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3699 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3700 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3701 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3702 !strconcat(OpcodeStr,
3703 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3704 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3705 addr:$dst)]>, OpSize;
3708 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3711 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3713 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3714 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3715 (ins VR128:$src1, i32i8imm:$src2),
3716 !strconcat(OpcodeStr,
3717 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3719 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3721 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3722 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3723 !strconcat(OpcodeStr,
3724 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3725 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3726 addr:$dst)]>, OpSize;
3729 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3731 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3732 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3735 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3736 Requires<[HasSSE41]>;
3738 let Constraints = "$src1 = $dst" in {
3739 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3740 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3741 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3742 !strconcat(OpcodeStr,
3743 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3745 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3746 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3747 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3748 !strconcat(OpcodeStr,
3749 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3751 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3752 imm:$src3))]>, OpSize;
3756 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3758 let Constraints = "$src1 = $dst" in {
3759 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3760 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3761 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3762 !strconcat(OpcodeStr,
3763 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3765 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3767 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3768 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3769 !strconcat(OpcodeStr,
3770 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3772 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3773 imm:$src3)))]>, OpSize;
3777 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3779 // insertps has a few different modes, there's the first two here below which
3780 // are optimized inserts that won't zero arbitrary elements in the destination
3781 // vector. The next one matches the intrinsic and could zero arbitrary elements
3782 // in the target vector.
3783 let Constraints = "$src1 = $dst" in {
3784 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3785 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3786 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3787 !strconcat(OpcodeStr,
3788 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3790 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3792 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3793 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3794 !strconcat(OpcodeStr,
3795 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3797 (X86insrtps VR128:$src1,
3798 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3799 imm:$src3))]>, OpSize;
3803 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3805 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3806 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3808 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3809 // the intel intrinsic that corresponds to this.
3810 let Defs = [EFLAGS] in {
3811 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3812 "ptest \t{$src2, $src1|$src1, $src2}",
3813 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3815 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3816 "ptest \t{$src2, $src1|$src1, $src2}",
3817 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3821 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3822 "movntdqa\t{$src, $dst|$dst, $src}",
3823 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3827 //===----------------------------------------------------------------------===//
3828 // SSE4.2 Instructions
3829 //===----------------------------------------------------------------------===//
3831 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3832 let Constraints = "$src1 = $dst" in {
3833 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3834 Intrinsic IntId128, bit Commutable = 0> {
3835 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3836 (ins VR128:$src1, VR128:$src2),
3837 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3838 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3840 let isCommutable = Commutable;
3842 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3843 (ins VR128:$src1, i128mem:$src2),
3844 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3846 (IntId128 VR128:$src1,
3847 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3851 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3853 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3854 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3855 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3856 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3858 // crc intrinsic instruction
3859 // This set of instructions are only rm, the only difference is the size
3861 let Constraints = "$src1 = $dst" in {
3862 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3863 (ins GR32:$src1, i8mem:$src2),
3864 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3866 (int_x86_sse42_crc32_8 GR32:$src1,
3867 (load addr:$src2)))]>;
3868 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3869 (ins GR32:$src1, GR8:$src2),
3870 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3872 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3873 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3874 (ins GR32:$src1, i16mem:$src2),
3875 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3877 (int_x86_sse42_crc32_16 GR32:$src1,
3878 (load addr:$src2)))]>,
3880 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3881 (ins GR32:$src1, GR16:$src2),
3882 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3884 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3886 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3887 (ins GR32:$src1, i32mem:$src2),
3888 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3890 (int_x86_sse42_crc32_32 GR32:$src1,
3891 (load addr:$src2)))]>;
3892 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3893 (ins GR32:$src1, GR32:$src2),
3894 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3896 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3897 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3898 (ins GR64:$src1, i8mem:$src2),
3899 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3901 (int_x86_sse42_crc64_8 GR64:$src1,
3902 (load addr:$src2)))]>,
3904 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3905 (ins GR64:$src1, GR8:$src2),
3906 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3908 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3910 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3911 (ins GR64:$src1, i64mem:$src2),
3912 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3914 (int_x86_sse42_crc64_64 GR64:$src1,
3915 (load addr:$src2)))]>,
3917 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3918 (ins GR64:$src1, GR64:$src2),
3919 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3921 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3925 // String/text processing instructions.
3926 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3927 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3928 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3929 "#PCMPISTRM128rr PSEUDO!",
3930 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3931 imm:$src3))]>, OpSize;
3932 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3933 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3934 "#PCMPISTRM128rm PSEUDO!",
3935 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3936 imm:$src3))]>, OpSize;
3939 let Defs = [XMM0, EFLAGS] in {
3940 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3941 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3942 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3943 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3944 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3945 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3948 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3949 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3950 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3951 "#PCMPESTRM128rr PSEUDO!",
3953 (int_x86_sse42_pcmpestrm128
3954 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3956 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3957 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3958 "#PCMPESTRM128rm PSEUDO!",
3959 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3960 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3964 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3965 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3966 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3967 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3968 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3969 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3970 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3973 let Defs = [ECX, EFLAGS] in {
3974 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3975 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3976 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3977 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3978 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3979 (implicit EFLAGS)]>, OpSize;
3980 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3981 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3982 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3983 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3984 (implicit EFLAGS)]>, OpSize;
3988 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3989 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3990 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3991 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3992 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3993 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3995 let Defs = [ECX, EFLAGS] in {
3996 let Uses = [EAX, EDX] in {
3997 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3998 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3999 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4000 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4001 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4002 (implicit EFLAGS)]>, OpSize;
4003 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4004 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4005 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4007 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4008 (implicit EFLAGS)]>, OpSize;
4013 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4014 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4015 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4016 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4017 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4018 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4020 //===----------------------------------------------------------------------===//
4021 // AES-NI Instructions
4022 //===----------------------------------------------------------------------===//
4024 let Constraints = "$src1 = $dst" in {
4025 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4026 Intrinsic IntId128, bit Commutable = 0> {
4027 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4028 (ins VR128:$src1, VR128:$src2),
4029 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4030 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4032 let isCommutable = Commutable;
4034 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4035 (ins VR128:$src1, i128mem:$src2),
4036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4038 (IntId128 VR128:$src1,
4039 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4043 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4044 int_x86_aesni_aesenc>;
4045 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4046 int_x86_aesni_aesenclast>;
4047 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4048 int_x86_aesni_aesdec>;
4049 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4050 int_x86_aesni_aesdeclast>;
4052 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4053 (AESENCrr VR128:$src1, VR128:$src2)>;
4054 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4055 (AESENCrm VR128:$src1, addr:$src2)>;
4056 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4057 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4058 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4059 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4060 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4061 (AESDECrr VR128:$src1, VR128:$src2)>;
4062 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4063 (AESDECrm VR128:$src1, addr:$src2)>;
4064 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4065 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4066 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4067 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4069 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4071 "aesimc\t{$src1, $dst|$dst, $src1}",
4073 (int_x86_aesni_aesimc VR128:$src1))]>,
4076 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4077 (ins i128mem:$src1),
4078 "aesimc\t{$src1, $dst|$dst, $src1}",
4080 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4083 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4084 (ins VR128:$src1, i32i8imm:$src2),
4085 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4087 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4089 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4090 (ins i128mem:$src1, i32i8imm:$src2),
4091 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4093 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),