1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 15 in {
616 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
617 // MOVS{S,D} to the lower bits.
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
619 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
620 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
621 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
622 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
623 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
624 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
625 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
627 // Move low f32 and clear high bits.
628 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSSrr (v4f32 (V_SET0)),
631 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
632 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
633 (SUBREG_TO_REG (i32 0),
634 (VMOVSSrr (v4i32 (V_SET0)),
635 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
638 let AddedComplexity = 20 in {
639 // MOVSSrm zeros the high parts of the register; represent this
640 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
641 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
642 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
643 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
644 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
645 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
646 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
648 // MOVSDrm zeros the high parts of the register; represent this
649 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
650 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
651 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
652 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
653 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
654 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
655 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
656 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
657 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
658 def : Pat<(v2f64 (X86vzload addr:$src)),
659 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
661 // Represent the same patterns above but in the form they appear for
663 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
664 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
665 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
666 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
667 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
668 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
669 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
670 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
671 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
673 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
674 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
675 (SUBREG_TO_REG (i32 0),
676 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
678 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
679 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
680 (SUBREG_TO_REG (i64 0),
681 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
683 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
684 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
685 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
687 // Move low f64 and clear high bits.
688 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
689 (SUBREG_TO_REG (i32 0),
690 (VMOVSDrr (v2f64 (V_SET0)),
691 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
693 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (v2i64 (V_SET0)),
696 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
698 // Extract and store.
699 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
701 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
702 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
704 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
706 // Shuffle with VMOVSS
707 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
708 (VMOVSSrr (v4i32 VR128:$src1),
709 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
710 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
711 (VMOVSSrr (v4f32 VR128:$src1),
712 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
715 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
716 (SUBREG_TO_REG (i32 0),
717 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
718 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
720 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
721 (SUBREG_TO_REG (i32 0),
722 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
723 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
726 // Shuffle with VMOVSD
727 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
728 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
729 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
730 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
731 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
732 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
733 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
734 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
737 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
738 (SUBREG_TO_REG (i32 0),
739 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
740 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
742 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
743 (SUBREG_TO_REG (i32 0),
744 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
745 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 let Predicates = [UseSSE1] in {
764 let AddedComplexity = 15 in {
765 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
766 // MOVSS to the lower bits.
767 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
768 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
769 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
770 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
771 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
772 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
775 let AddedComplexity = 20 in {
776 // MOVSSrm already zeros the high parts of the register.
777 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
778 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
779 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
780 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
781 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
782 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
785 // Extract and store.
786 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
788 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
790 // Shuffle with MOVSS
791 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
792 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
793 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
794 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
797 let Predicates = [UseSSE2] in {
798 let AddedComplexity = 15 in {
799 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
800 // MOVSD to the lower bits.
801 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
802 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
805 let AddedComplexity = 20 in {
806 // MOVSDrm already zeros the high parts of the register.
807 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
808 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
809 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
810 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
811 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
812 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
813 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
814 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
815 def : Pat<(v2f64 (X86vzload addr:$src)),
816 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
819 // Extract and store.
820 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
822 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
824 // Shuffle with MOVSD
825 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
826 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
827 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
828 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
829 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
830 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
831 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
832 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
834 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
835 // is during lowering, where it's not possible to recognize the fold cause
836 // it has two uses through a bitcast. One use disappears at isel time and the
837 // fold opportunity reappears.
838 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
839 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
840 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
841 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
842 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
843 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
844 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
845 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
848 //===----------------------------------------------------------------------===//
849 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
850 //===----------------------------------------------------------------------===//
852 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
853 X86MemOperand x86memop, PatFrag ld_frag,
854 string asm, Domain d,
856 bit IsReMaterializable = 1> {
857 let neverHasSideEffects = 1 in
858 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
859 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
860 Sched<[WriteFShuffle]>;
861 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
862 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
863 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
864 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
868 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
869 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
871 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
872 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
874 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
875 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
877 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
878 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
881 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
882 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
884 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
885 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
887 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
888 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
890 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
891 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
893 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
894 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
896 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
897 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
899 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
900 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
902 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
903 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
906 let SchedRW = [WriteStore] in {
907 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
908 "movaps\t{$src, $dst|$dst, $src}",
909 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
910 IIC_SSE_MOVA_P_MR>, VEX;
911 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
912 "movapd\t{$src, $dst|$dst, $src}",
913 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
914 IIC_SSE_MOVA_P_MR>, VEX;
915 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
916 "movups\t{$src, $dst|$dst, $src}",
917 [(store (v4f32 VR128:$src), addr:$dst)],
918 IIC_SSE_MOVU_P_MR>, VEX;
919 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
920 "movupd\t{$src, $dst|$dst, $src}",
921 [(store (v2f64 VR128:$src), addr:$dst)],
922 IIC_SSE_MOVU_P_MR>, VEX;
923 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
924 "movaps\t{$src, $dst|$dst, $src}",
925 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
926 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
927 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
928 "movapd\t{$src, $dst|$dst, $src}",
929 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
930 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
931 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
932 "movups\t{$src, $dst|$dst, $src}",
933 [(store (v8f32 VR256:$src), addr:$dst)],
934 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
935 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
936 "movupd\t{$src, $dst|$dst, $src}",
937 [(store (v4f64 VR256:$src), addr:$dst)],
938 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
942 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
943 SchedRW = [WriteFShuffle] in {
944 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
946 "movaps\t{$src, $dst|$dst, $src}", [],
947 IIC_SSE_MOVA_P_RR>, VEX;
948 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
950 "movapd\t{$src, $dst|$dst, $src}", [],
951 IIC_SSE_MOVA_P_RR>, VEX;
952 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
954 "movups\t{$src, $dst|$dst, $src}", [],
955 IIC_SSE_MOVU_P_RR>, VEX;
956 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
958 "movupd\t{$src, $dst|$dst, $src}", [],
959 IIC_SSE_MOVU_P_RR>, VEX;
960 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
962 "movaps\t{$src, $dst|$dst, $src}", [],
963 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
964 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
966 "movapd\t{$src, $dst|$dst, $src}", [],
967 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
968 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
970 "movups\t{$src, $dst|$dst, $src}", [],
971 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
972 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
974 "movupd\t{$src, $dst|$dst, $src}", [],
975 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
978 let Predicates = [HasAVX] in {
979 def : Pat<(v8i32 (X86vzmovl
980 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
981 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
982 def : Pat<(v4i64 (X86vzmovl
983 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
984 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
985 def : Pat<(v8f32 (X86vzmovl
986 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
987 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
988 def : Pat<(v4f64 (X86vzmovl
989 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
990 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
994 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
995 (VMOVUPSYmr addr:$dst, VR256:$src)>;
996 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
997 (VMOVUPDYmr addr:$dst, VR256:$src)>;
999 let SchedRW = [WriteStore] in {
1000 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1001 "movaps\t{$src, $dst|$dst, $src}",
1002 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
1004 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1005 "movapd\t{$src, $dst|$dst, $src}",
1006 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
1008 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1009 "movups\t{$src, $dst|$dst, $src}",
1010 [(store (v4f32 VR128:$src), addr:$dst)],
1012 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1013 "movupd\t{$src, $dst|$dst, $src}",
1014 [(store (v2f64 VR128:$src), addr:$dst)],
1019 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1020 SchedRW = [WriteFShuffle] in {
1021 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1022 "movaps\t{$src, $dst|$dst, $src}", [],
1024 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1025 "movapd\t{$src, $dst|$dst, $src}", [],
1027 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1028 "movups\t{$src, $dst|$dst, $src}", [],
1030 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1031 "movupd\t{$src, $dst|$dst, $src}", [],
1035 let Predicates = [HasAVX] in {
1036 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1037 (VMOVUPSmr addr:$dst, VR128:$src)>;
1038 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1039 (VMOVUPDmr addr:$dst, VR128:$src)>;
1042 let Predicates = [UseSSE1] in
1043 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1044 (MOVUPSmr addr:$dst, VR128:$src)>;
1045 let Predicates = [UseSSE2] in
1046 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1047 (MOVUPDmr addr:$dst, VR128:$src)>;
1049 // Use vmovaps/vmovups for AVX integer load/store.
1050 let Predicates = [HasAVX] in {
1051 // 128-bit load/store
1052 def : Pat<(alignedloadv2i64 addr:$src),
1053 (VMOVAPSrm addr:$src)>;
1054 def : Pat<(loadv2i64 addr:$src),
1055 (VMOVUPSrm addr:$src)>;
1057 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1058 (VMOVAPSmr addr:$dst, VR128:$src)>;
1059 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1060 (VMOVAPSmr addr:$dst, VR128:$src)>;
1061 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1062 (VMOVAPSmr addr:$dst, VR128:$src)>;
1063 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1064 (VMOVAPSmr addr:$dst, VR128:$src)>;
1065 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1066 (VMOVUPSmr addr:$dst, VR128:$src)>;
1067 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1068 (VMOVUPSmr addr:$dst, VR128:$src)>;
1069 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1070 (VMOVUPSmr addr:$dst, VR128:$src)>;
1071 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1072 (VMOVUPSmr addr:$dst, VR128:$src)>;
1074 // 256-bit load/store
1075 def : Pat<(alignedloadv4i64 addr:$src),
1076 (VMOVAPSYrm addr:$src)>;
1077 def : Pat<(loadv4i64 addr:$src),
1078 (VMOVUPSYrm addr:$src)>;
1079 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1080 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1081 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1082 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1083 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1084 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1085 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1086 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1087 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1088 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1089 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1090 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1091 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1092 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1093 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1094 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1096 // Special patterns for storing subvector extracts of lower 128-bits
1097 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1098 def : Pat<(alignedstore (v2f64 (extract_subvector
1099 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1100 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1101 def : Pat<(alignedstore (v4f32 (extract_subvector
1102 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1103 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1104 def : Pat<(alignedstore (v2i64 (extract_subvector
1105 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1106 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1107 def : Pat<(alignedstore (v4i32 (extract_subvector
1108 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1109 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1110 def : Pat<(alignedstore (v8i16 (extract_subvector
1111 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1112 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1113 def : Pat<(alignedstore (v16i8 (extract_subvector
1114 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1115 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1117 def : Pat<(store (v2f64 (extract_subvector
1118 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1119 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1120 def : Pat<(store (v4f32 (extract_subvector
1121 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1122 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1123 def : Pat<(store (v2i64 (extract_subvector
1124 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1125 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1126 def : Pat<(store (v4i32 (extract_subvector
1127 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1128 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1129 def : Pat<(store (v8i16 (extract_subvector
1130 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1131 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1132 def : Pat<(store (v16i8 (extract_subvector
1133 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1134 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1137 // Use movaps / movups for SSE integer load / store (one byte shorter).
1138 // The instructions selected below are then converted to MOVDQA/MOVDQU
1139 // during the SSE domain pass.
1140 let Predicates = [UseSSE1] in {
1141 def : Pat<(alignedloadv2i64 addr:$src),
1142 (MOVAPSrm addr:$src)>;
1143 def : Pat<(loadv2i64 addr:$src),
1144 (MOVUPSrm addr:$src)>;
1146 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1147 (MOVAPSmr addr:$dst, VR128:$src)>;
1148 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1149 (MOVAPSmr addr:$dst, VR128:$src)>;
1150 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1151 (MOVAPSmr addr:$dst, VR128:$src)>;
1152 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1153 (MOVAPSmr addr:$dst, VR128:$src)>;
1154 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1155 (MOVUPSmr addr:$dst, VR128:$src)>;
1156 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1157 (MOVUPSmr addr:$dst, VR128:$src)>;
1158 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1159 (MOVUPSmr addr:$dst, VR128:$src)>;
1160 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1161 (MOVUPSmr addr:$dst, VR128:$src)>;
1164 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1165 // bits are disregarded. FIXME: Set encoding to pseudo!
1166 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1167 let isCodeGenOnly = 1 in {
1168 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1169 "movaps\t{$src, $dst|$dst, $src}",
1170 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1171 IIC_SSE_MOVA_P_RM>, VEX;
1172 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1173 "movapd\t{$src, $dst|$dst, $src}",
1174 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1175 IIC_SSE_MOVA_P_RM>, VEX;
1176 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1177 "movaps\t{$src, $dst|$dst, $src}",
1178 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1180 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1181 "movapd\t{$src, $dst|$dst, $src}",
1182 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1187 //===----------------------------------------------------------------------===//
1188 // SSE 1 & 2 - Move Low packed FP Instructions
1189 //===----------------------------------------------------------------------===//
1191 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1192 string base_opc, string asm_opr,
1193 InstrItinClass itin> {
1194 def PSrm : PI<opc, MRMSrcMem,
1195 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1196 !strconcat(base_opc, "s", asm_opr),
1198 (psnode VR128:$src1,
1199 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1200 itin, SSEPackedSingle>, PS,
1201 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1203 def PDrm : PI<opc, MRMSrcMem,
1204 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1205 !strconcat(base_opc, "d", asm_opr),
1206 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1207 (scalar_to_vector (loadf64 addr:$src2)))))],
1208 itin, SSEPackedDouble>, PD,
1209 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1213 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1214 string base_opc, InstrItinClass itin> {
1215 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1216 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1219 let Constraints = "$src1 = $dst" in
1220 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1221 "\t{$src2, $dst|$dst, $src2}",
1225 let AddedComplexity = 20 in {
1226 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1230 let SchedRW = [WriteStore] in {
1231 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1232 "movlps\t{$src, $dst|$dst, $src}",
1233 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1234 (iPTR 0))), addr:$dst)],
1235 IIC_SSE_MOV_LH>, VEX;
1236 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1237 "movlpd\t{$src, $dst|$dst, $src}",
1238 [(store (f64 (vector_extract (v2f64 VR128:$src),
1239 (iPTR 0))), addr:$dst)],
1240 IIC_SSE_MOV_LH>, VEX;
1241 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1242 "movlps\t{$src, $dst|$dst, $src}",
1243 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1244 (iPTR 0))), addr:$dst)],
1246 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1247 "movlpd\t{$src, $dst|$dst, $src}",
1248 [(store (f64 (vector_extract (v2f64 VR128:$src),
1249 (iPTR 0))), addr:$dst)],
1253 let Predicates = [HasAVX] in {
1254 // Shuffle with VMOVLPS
1255 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1258 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1260 // Shuffle with VMOVLPD
1261 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1262 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1263 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1264 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1267 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1269 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1270 def : Pat<(store (v4i32 (X86Movlps
1271 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1272 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1273 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1275 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1276 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1278 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1281 let Predicates = [UseSSE1] in {
1282 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1283 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1284 (iPTR 0))), addr:$src1),
1285 (MOVLPSmr addr:$src1, VR128:$src2)>;
1287 // Shuffle with MOVLPS
1288 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1289 (MOVLPSrm VR128:$src1, addr:$src2)>;
1290 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1291 (MOVLPSrm VR128:$src1, addr:$src2)>;
1292 def : Pat<(X86Movlps VR128:$src1,
1293 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1294 (MOVLPSrm VR128:$src1, addr:$src2)>;
1297 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1299 (MOVLPSmr addr:$src1, VR128:$src2)>;
1300 def : Pat<(store (v4i32 (X86Movlps
1301 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1303 (MOVLPSmr addr:$src1, VR128:$src2)>;
1306 let Predicates = [UseSSE2] in {
1307 // Shuffle with MOVLPD
1308 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1309 (MOVLPDrm VR128:$src1, addr:$src2)>;
1310 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1311 (MOVLPDrm VR128:$src1, addr:$src2)>;
1314 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1316 (MOVLPDmr addr:$src1, VR128:$src2)>;
1317 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1319 (MOVLPDmr addr:$src1, VR128:$src2)>;
1322 //===----------------------------------------------------------------------===//
1323 // SSE 1 & 2 - Move Hi packed FP Instructions
1324 //===----------------------------------------------------------------------===//
1326 let AddedComplexity = 20 in {
1327 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1331 let SchedRW = [WriteStore] in {
1332 // v2f64 extract element 1 is always custom lowered to unpack high to low
1333 // and extract element 0 so the non-store version isn't too horrible.
1334 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1335 "movhps\t{$src, $dst|$dst, $src}",
1336 [(store (f64 (vector_extract
1337 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1338 (bc_v2f64 (v4f32 VR128:$src))),
1339 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1340 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1341 "movhpd\t{$src, $dst|$dst, $src}",
1342 [(store (f64 (vector_extract
1343 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1344 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1345 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1346 "movhps\t{$src, $dst|$dst, $src}",
1347 [(store (f64 (vector_extract
1348 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1349 (bc_v2f64 (v4f32 VR128:$src))),
1350 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1351 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1352 "movhpd\t{$src, $dst|$dst, $src}",
1353 [(store (f64 (vector_extract
1354 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1355 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1358 let Predicates = [HasAVX] in {
1360 def : Pat<(X86Movlhps VR128:$src1,
1361 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1362 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1363 def : Pat<(X86Movlhps VR128:$src1,
1364 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1365 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1376 let Predicates = [UseSSE1] in {
1378 def : Pat<(X86Movlhps VR128:$src1,
1379 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1380 (MOVHPSrm VR128:$src1, addr:$src2)>;
1381 def : Pat<(X86Movlhps VR128:$src1,
1382 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1383 (MOVHPSrm VR128:$src1, addr:$src2)>;
1386 let Predicates = [UseSSE2] in {
1387 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1388 // is during lowering, where it's not possible to recognize the load fold
1389 // cause it has two uses through a bitcast. One use disappears at isel time
1390 // and the fold opportunity reappears.
1391 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1392 (scalar_to_vector (loadf64 addr:$src2)))),
1393 (MOVHPDrm VR128:$src1, addr:$src2)>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1398 //===----------------------------------------------------------------------===//
1400 let AddedComplexity = 20, Predicates = [UseAVX] in {
1401 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1402 (ins VR128:$src1, VR128:$src2),
1403 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1405 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1407 VEX_4V, Sched<[WriteFShuffle]>;
1408 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1409 (ins VR128:$src1, VR128:$src2),
1410 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1412 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1414 VEX_4V, Sched<[WriteFShuffle]>;
1416 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1417 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1418 (ins VR128:$src1, VR128:$src2),
1419 "movlhps\t{$src2, $dst|$dst, $src2}",
1421 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1422 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1423 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1424 (ins VR128:$src1, VR128:$src2),
1425 "movhlps\t{$src2, $dst|$dst, $src2}",
1427 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1428 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1431 let Predicates = [UseAVX] in {
1433 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1434 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1435 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1439 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1440 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1443 let Predicates = [UseSSE1] in {
1445 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1446 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1447 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1448 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1451 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1452 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1455 //===----------------------------------------------------------------------===//
1456 // SSE 1 & 2 - Conversion Instructions
1457 //===----------------------------------------------------------------------===//
1459 def SSE_CVT_PD : OpndItins<
1460 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1463 let Sched = WriteCvtI2F in
1464 def SSE_CVT_PS : OpndItins<
1465 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1468 let Sched = WriteCvtI2F in
1469 def SSE_CVT_Scalar : OpndItins<
1470 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SS2SI_32 : OpndItins<
1475 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1478 let Sched = WriteCvtF2I in
1479 def SSE_CVT_SS2SI_64 : OpndItins<
1480 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1483 let Sched = WriteCvtF2I in
1484 def SSE_CVT_SD2SI : OpndItins<
1485 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1488 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1489 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1490 string asm, OpndItins itins> {
1491 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1492 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1493 itins.rr>, Sched<[itins.Sched]>;
1494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1495 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1496 itins.rm>, Sched<[itins.Sched.Folded]>;
1499 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1500 X86MemOperand x86memop, string asm, Domain d,
1502 let neverHasSideEffects = 1 in {
1503 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1504 [], itins.rr, d>, Sched<[itins.Sched]>;
1506 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1507 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1511 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1512 X86MemOperand x86memop, string asm> {
1513 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1514 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1515 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1516 Sched<[WriteCvtI2F]>;
1518 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1519 (ins DstRC:$src1, x86memop:$src),
1520 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1521 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1522 } // neverHasSideEffects = 1
1525 let Predicates = [UseAVX] in {
1526 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1527 "cvttss2si\t{$src, $dst|$dst, $src}",
1530 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1531 "cvttss2si\t{$src, $dst|$dst, $src}",
1533 XS, VEX, VEX_W, VEX_LIG;
1534 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1535 "cvttsd2si\t{$src, $dst|$dst, $src}",
1538 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1539 "cvttsd2si\t{$src, $dst|$dst, $src}",
1541 XD, VEX, VEX_W, VEX_LIG;
1543 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1545 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1549 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1551 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1552 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1553 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1554 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1555 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1556 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1557 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1558 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1560 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1561 // register, but the same isn't true when only using memory operands,
1562 // provide other assembly "l" and "q" forms to address this explicitly
1563 // where appropriate to do so.
1564 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1565 XS, VEX_4V, VEX_LIG;
1566 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1567 XS, VEX_4V, VEX_W, VEX_LIG;
1568 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1569 XD, VEX_4V, VEX_LIG;
1570 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1571 XD, VEX_4V, VEX_W, VEX_LIG;
1573 let Predicates = [UseAVX] in {
1574 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1575 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1576 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1577 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1579 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1580 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1581 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1582 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1583 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1584 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1585 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1586 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1588 def : Pat<(f32 (sint_to_fp GR32:$src)),
1589 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1590 def : Pat<(f32 (sint_to_fp GR64:$src)),
1591 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1592 def : Pat<(f64 (sint_to_fp GR32:$src)),
1593 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1594 def : Pat<(f64 (sint_to_fp GR64:$src)),
1595 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1598 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1599 "cvttss2si\t{$src, $dst|$dst, $src}",
1600 SSE_CVT_SS2SI_32>, XS;
1601 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1602 "cvttss2si\t{$src, $dst|$dst, $src}",
1603 SSE_CVT_SS2SI_64>, XS, REX_W;
1604 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1605 "cvttsd2si\t{$src, $dst|$dst, $src}",
1607 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1608 "cvttsd2si\t{$src, $dst|$dst, $src}",
1609 SSE_CVT_SD2SI>, XD, REX_W;
1610 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1611 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1612 SSE_CVT_Scalar>, XS;
1613 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1614 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1615 SSE_CVT_Scalar>, XS, REX_W;
1616 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1617 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1618 SSE_CVT_Scalar>, XD;
1619 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1620 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1621 SSE_CVT_Scalar>, XD, REX_W;
1623 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1625 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1626 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1627 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1629 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1630 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1631 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1632 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1633 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1634 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1635 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1636 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1637 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1638 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1640 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1641 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1642 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1643 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1645 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1646 // and/or XMM operand(s).
1648 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1649 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1650 string asm, OpndItins itins> {
1651 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1652 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1653 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1654 Sched<[itins.Sched]>;
1655 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1656 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1657 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1658 Sched<[itins.Sched.Folded]>;
1661 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1662 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1663 PatFrag ld_frag, string asm, OpndItins itins,
1665 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1667 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1668 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1669 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1670 itins.rr>, Sched<[itins.Sched]>;
1671 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1672 (ins DstRC:$src1, x86memop:$src2),
1674 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1675 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1676 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1677 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1680 let Predicates = [UseAVX] in {
1681 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1682 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1683 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1684 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1685 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1686 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1688 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1689 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1690 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1691 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1694 let isCodeGenOnly = 1 in {
1695 let Predicates = [UseAVX] in {
1696 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1697 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1698 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1699 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1700 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1701 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1703 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1704 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1705 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1706 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1707 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1708 SSE_CVT_Scalar, 0>, XD,
1711 let Constraints = "$src1 = $dst" in {
1712 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1713 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1714 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1715 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1716 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1717 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1718 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1719 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1720 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1721 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1722 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1723 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1725 } // isCodeGenOnly = 1
1729 // Aliases for intrinsics
1730 let isCodeGenOnly = 1 in {
1731 let Predicates = [UseAVX] in {
1732 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1733 ssmem, sse_load_f32, "cvttss2si",
1734 SSE_CVT_SS2SI_32>, XS, VEX;
1735 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1736 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1737 "cvttss2si", SSE_CVT_SS2SI_64>,
1739 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1740 sdmem, sse_load_f64, "cvttsd2si",
1741 SSE_CVT_SD2SI>, XD, VEX;
1742 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1744 "cvttsd2si", SSE_CVT_SD2SI>,
1747 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1748 ssmem, sse_load_f32, "cvttss2si",
1749 SSE_CVT_SS2SI_32>, XS;
1750 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1751 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1752 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1753 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1754 sdmem, sse_load_f64, "cvttsd2si",
1756 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1757 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1758 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1759 } // isCodeGenOnly = 1
1761 let Predicates = [UseAVX] in {
1762 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1765 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1766 ssmem, sse_load_f32, "cvtss2si",
1767 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1769 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1770 ssmem, sse_load_f32, "cvtss2si",
1771 SSE_CVT_SS2SI_32>, XS;
1772 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1773 ssmem, sse_load_f32, "cvtss2si",
1774 SSE_CVT_SS2SI_64>, XS, REX_W;
1776 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1777 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1778 SSEPackedSingle, SSE_CVT_PS>,
1779 PS, VEX, Requires<[HasAVX]>;
1780 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1781 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1782 SSEPackedSingle, SSE_CVT_PS>,
1783 PS, VEX, VEX_L, Requires<[HasAVX]>;
1785 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1786 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1787 SSEPackedSingle, SSE_CVT_PS>,
1788 PS, Requires<[UseSSE2]>;
1790 let Predicates = [UseAVX] in {
1791 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1793 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1794 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1797 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1798 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1800 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1801 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1802 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1804 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1805 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1806 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1809 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1811 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1812 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1813 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1815 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1816 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1817 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1818 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1819 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1820 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1821 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1822 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1823 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1824 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1828 // Convert scalar double to scalar single
1829 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1830 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1831 (ins FR64:$src1, FR64:$src2),
1832 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1833 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1834 Sched<[WriteCvtF2F]>;
1836 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1837 (ins FR64:$src1, f64mem:$src2),
1838 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1839 [], IIC_SSE_CVT_Scalar_RM>,
1840 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1841 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1844 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1847 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1848 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1849 [(set FR32:$dst, (fround FR64:$src))],
1850 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1851 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1852 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1853 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1854 IIC_SSE_CVT_Scalar_RM>,
1856 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1858 let isCodeGenOnly = 1 in {
1859 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1860 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1861 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1863 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1864 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1865 Sched<[WriteCvtF2F]>;
1866 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1867 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1868 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1870 VR128:$src1, sse_load_f64:$src2))],
1871 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1872 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1874 let Constraints = "$src1 = $dst" in {
1875 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1876 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1877 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1879 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1880 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1881 Sched<[WriteCvtF2F]>;
1882 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1883 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1884 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1885 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1886 VR128:$src1, sse_load_f64:$src2))],
1887 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1888 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1890 } // isCodeGenOnly = 1
1892 // Convert scalar single to scalar double
1893 // SSE2 instructions with XS prefix
1894 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1895 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1896 (ins FR32:$src1, FR32:$src2),
1897 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1898 [], IIC_SSE_CVT_Scalar_RR>,
1899 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1900 Sched<[WriteCvtF2F]>;
1902 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1903 (ins FR32:$src1, f32mem:$src2),
1904 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1905 [], IIC_SSE_CVT_Scalar_RM>,
1906 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1907 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1910 def : Pat<(f64 (fextend FR32:$src)),
1911 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1912 def : Pat<(fextend (loadf32 addr:$src)),
1913 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1915 def : Pat<(extloadf32 addr:$src),
1916 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1917 Requires<[UseAVX, OptForSize]>;
1918 def : Pat<(extloadf32 addr:$src),
1919 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1920 Requires<[UseAVX, OptForSpeed]>;
1922 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1923 "cvtss2sd\t{$src, $dst|$dst, $src}",
1924 [(set FR64:$dst, (fextend FR32:$src))],
1925 IIC_SSE_CVT_Scalar_RR>, XS,
1926 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1927 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1928 "cvtss2sd\t{$src, $dst|$dst, $src}",
1929 [(set FR64:$dst, (extloadf32 addr:$src))],
1930 IIC_SSE_CVT_Scalar_RM>, XS,
1931 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1933 // extload f32 -> f64. This matches load+fextend because we have a hack in
1934 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1936 // Since these loads aren't folded into the fextend, we have to match it
1938 def : Pat<(fextend (loadf32 addr:$src)),
1939 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1940 def : Pat<(extloadf32 addr:$src),
1941 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1943 let isCodeGenOnly = 1 in {
1944 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1945 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1946 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1948 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1949 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1950 Sched<[WriteCvtF2F]>;
1951 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1952 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1953 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1956 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1957 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1958 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1959 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1960 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1961 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1963 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1964 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1965 Sched<[WriteCvtF2F]>;
1966 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1967 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1968 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1970 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1971 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1972 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1974 } // isCodeGenOnly = 1
1976 // Convert packed single/double fp to doubleword
1977 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1978 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1986 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1990 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1991 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1992 "cvtps2dq\t{$src, $dst|$dst, $src}",
1994 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1995 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1996 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1997 "cvtps2dq\t{$src, $dst|$dst, $src}",
1998 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1999 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2000 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2001 "cvtps2dq\t{$src, $dst|$dst, $src}",
2003 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
2004 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2007 // Convert Packed Double FP to Packed DW Integers
2008 let Predicates = [HasAVX] in {
2009 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2010 // register, but the same isn't true when using memory operands instead.
2011 // Provide other assembly rr and rm forms to address this explicitly.
2012 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2013 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2014 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2015 VEX, Sched<[WriteCvtF2I]>;
2018 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2019 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2020 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2021 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2023 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2024 Sched<[WriteCvtF2ILd]>;
2027 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2028 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2030 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2031 Sched<[WriteCvtF2I]>;
2032 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2033 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2035 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2036 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2037 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2038 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2041 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2042 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2044 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2045 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2046 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2047 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2048 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2049 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2051 // Convert with truncation packed single/double fp to doubleword
2052 // SSE2 packed instructions with XS prefix
2053 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_sse2_cvttps2dq VR128:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2061 (loadv4f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2063 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2064 "cvttps2dq\t{$src, $dst|$dst, $src}",
2066 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2067 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2068 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2069 "cvttps2dq\t{$src, $dst|$dst, $src}",
2070 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2071 (loadv8f32 addr:$src)))],
2072 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2073 Sched<[WriteCvtF2ILd]>;
2075 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2076 "cvttps2dq\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2078 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2079 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2080 "cvttps2dq\t{$src, $dst|$dst, $src}",
2082 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2083 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2085 let Predicates = [HasAVX] in {
2086 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2087 (VCVTDQ2PSrr VR128:$src)>;
2088 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2089 (VCVTDQ2PSrm addr:$src)>;
2091 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2092 (VCVTDQ2PSrr VR128:$src)>;
2093 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2094 (VCVTDQ2PSrm addr:$src)>;
2096 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2097 (VCVTTPS2DQrr VR128:$src)>;
2098 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2099 (VCVTTPS2DQrm addr:$src)>;
2101 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2102 (VCVTDQ2PSYrr VR256:$src)>;
2103 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2104 (VCVTDQ2PSYrm addr:$src)>;
2106 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2107 (VCVTTPS2DQYrr VR256:$src)>;
2108 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2109 (VCVTTPS2DQYrm addr:$src)>;
2112 let Predicates = [UseSSE2] in {
2113 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2114 (CVTDQ2PSrr VR128:$src)>;
2115 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2116 (CVTDQ2PSrm addr:$src)>;
2118 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2119 (CVTDQ2PSrr VR128:$src)>;
2120 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2121 (CVTDQ2PSrm addr:$src)>;
2123 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2124 (CVTTPS2DQrr VR128:$src)>;
2125 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2126 (CVTTPS2DQrm addr:$src)>;
2129 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2130 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2132 (int_x86_sse2_cvttpd2dq VR128:$src))],
2133 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2135 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2136 // register, but the same isn't true when using memory operands instead.
2137 // Provide other assembly rr and rm forms to address this explicitly.
2140 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2141 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2142 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2143 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2144 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2145 (loadv2f64 addr:$src)))],
2146 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2149 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2150 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2152 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2153 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2154 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2155 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2157 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2158 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2159 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2160 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2162 let Predicates = [HasAVX] in {
2163 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2164 (VCVTTPD2DQYrr VR256:$src)>;
2165 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2166 (VCVTTPD2DQYrm addr:$src)>;
2167 } // Predicates = [HasAVX]
2169 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2170 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2171 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2172 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2173 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2174 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2176 (memopv2f64 addr:$src)))],
2178 Sched<[WriteCvtF2ILd]>;
2180 // Convert packed single to packed double
2181 let Predicates = [HasAVX] in {
2182 // SSE2 instructions without OpSize prefix
2183 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2185 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2186 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2187 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2188 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2189 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2190 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2191 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2192 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2194 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2195 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2196 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2197 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2199 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2200 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2203 let Predicates = [UseSSE2] in {
2204 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2205 "cvtps2pd\t{$src, $dst|$dst, $src}",
2206 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2207 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2208 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2209 "cvtps2pd\t{$src, $dst|$dst, $src}",
2210 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2211 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2214 // Convert Packed DW Integers to Packed Double FP
2215 let Predicates = [HasAVX] in {
2216 let neverHasSideEffects = 1, mayLoad = 1 in
2217 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2219 []>, VEX, Sched<[WriteCvtI2FLd]>;
2220 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2223 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2224 Sched<[WriteCvtI2F]>;
2225 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2226 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2228 (int_x86_avx_cvtdq2_pd_256
2229 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2230 Sched<[WriteCvtI2FLd]>;
2231 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2232 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2234 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2235 Sched<[WriteCvtI2F]>;
2238 let neverHasSideEffects = 1, mayLoad = 1 in
2239 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2240 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2241 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2242 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2243 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2244 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2245 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2247 // AVX 256-bit register conversion intrinsics
2248 let Predicates = [HasAVX] in {
2249 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2250 (VCVTDQ2PDYrr VR128:$src)>;
2251 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2252 (VCVTDQ2PDYrm addr:$src)>;
2253 } // Predicates = [HasAVX]
2255 // Convert packed double to packed single
2256 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2257 // register, but the same isn't true when using memory operands instead.
2258 // Provide other assembly rr and rm forms to address this explicitly.
2259 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2260 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2261 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2262 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2265 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2266 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2267 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2268 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2270 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2271 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2274 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2275 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2277 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2278 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2279 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2280 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2282 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2283 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2284 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2285 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2287 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2288 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2289 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2290 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2291 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2292 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2294 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2295 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2298 // AVX 256-bit register conversion intrinsics
2299 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2300 // whenever possible to avoid declaring two versions of each one.
2301 let Predicates = [HasAVX] in {
2302 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2303 (VCVTDQ2PSYrr VR256:$src)>;
2304 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2305 (VCVTDQ2PSYrm addr:$src)>;
2307 // Match fround and fextend for 128/256-bit conversions
2308 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2309 (VCVTPD2PSrr VR128:$src)>;
2310 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2311 (VCVTPD2PSXrm addr:$src)>;
2312 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2313 (VCVTPD2PSYrr VR256:$src)>;
2314 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2315 (VCVTPD2PSYrm addr:$src)>;
2317 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2318 (VCVTPS2PDrr VR128:$src)>;
2319 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2320 (VCVTPS2PDYrr VR128:$src)>;
2321 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2322 (VCVTPS2PDYrm addr:$src)>;
2325 let Predicates = [UseSSE2] in {
2326 // Match fround and fextend for 128 conversions
2327 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2328 (CVTPD2PSrr VR128:$src)>;
2329 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2330 (CVTPD2PSrm addr:$src)>;
2332 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2333 (CVTPS2PDrr VR128:$src)>;
2336 //===----------------------------------------------------------------------===//
2337 // SSE 1 & 2 - Compare Instructions
2338 //===----------------------------------------------------------------------===//
2340 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2341 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2342 Operand CC, SDNode OpNode, ValueType VT,
2343 PatFrag ld_frag, string asm, string asm_alt,
2345 def rr : SIi8<0xC2, MRMSrcReg,
2346 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2347 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2348 itins.rr>, Sched<[itins.Sched]>;
2349 def rm : SIi8<0xC2, MRMSrcMem,
2350 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2351 [(set RC:$dst, (OpNode (VT RC:$src1),
2352 (ld_frag addr:$src2), imm:$cc))],
2354 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2356 // Accept explicit immediate argument form instead of comparison code.
2357 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2358 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2359 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2360 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2362 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2363 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2364 IIC_SSE_ALU_F32S_RM>,
2365 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2369 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2370 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2371 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2373 XS, VEX_4V, VEX_LIG;
2374 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2375 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2376 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2377 SSE_ALU_F32S>, // same latency as 32 bit compare
2378 XD, VEX_4V, VEX_LIG;
2380 let Constraints = "$src1 = $dst" in {
2381 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2382 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2383 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2385 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2386 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2387 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2392 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2393 Intrinsic Int, string asm, OpndItins itins> {
2394 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2395 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2396 [(set VR128:$dst, (Int VR128:$src1,
2397 VR128:$src, imm:$cc))],
2399 Sched<[itins.Sched]>;
2400 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2401 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2402 [(set VR128:$dst, (Int VR128:$src1,
2403 (load addr:$src), imm:$cc))],
2405 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2408 let isCodeGenOnly = 1 in {
2409 // Aliases to match intrinsics which expect XMM operand(s).
2410 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2411 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2414 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2415 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2416 SSE_ALU_F32S>, // same latency as f32
2418 let Constraints = "$src1 = $dst" in {
2419 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2420 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2422 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2423 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2430 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2431 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2432 ValueType vt, X86MemOperand x86memop,
2433 PatFrag ld_frag, string OpcodeStr> {
2434 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2435 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2436 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2439 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2440 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2441 [(set EFLAGS, (OpNode (vt RC:$src1),
2442 (ld_frag addr:$src2)))],
2444 Sched<[WriteFAddLd, ReadAfterLd]>;
2447 let Defs = [EFLAGS] in {
2448 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2449 "ucomiss">, PS, VEX, VEX_LIG;
2450 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2451 "ucomisd">, PD, VEX, VEX_LIG;
2452 let Pattern = []<dag> in {
2453 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2454 "comiss">, PS, VEX, VEX_LIG;
2455 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2456 "comisd">, PD, VEX, VEX_LIG;
2459 let isCodeGenOnly = 1 in {
2460 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2461 load, "ucomiss">, PS, VEX;
2462 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2463 load, "ucomisd">, PD, VEX;
2465 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2466 load, "comiss">, PS, VEX;
2467 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2468 load, "comisd">, PD, VEX;
2470 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2472 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2475 let Pattern = []<dag> in {
2476 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2478 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2482 let isCodeGenOnly = 1 in {
2483 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2484 load, "ucomiss">, PS;
2485 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2486 load, "ucomisd">, PD;
2488 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2490 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2493 } // Defs = [EFLAGS]
2495 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2496 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2497 Operand CC, Intrinsic Int, string asm,
2498 string asm_alt, Domain d,
2499 OpndItins itins = SSE_ALU_F32P> {
2500 def rri : PIi8<0xC2, MRMSrcReg,
2501 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2502 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2505 def rmi : PIi8<0xC2, MRMSrcMem,
2506 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2507 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2509 Sched<[WriteFAddLd, ReadAfterLd]>;
2511 // Accept explicit immediate argument form instead of comparison code.
2512 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2513 def rri_alt : PIi8<0xC2, MRMSrcReg,
2514 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2515 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2516 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2517 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2518 asm_alt, [], itins.rm, d>,
2519 Sched<[WriteFAddLd, ReadAfterLd]>;
2523 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2524 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2525 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2526 SSEPackedSingle>, PS, VEX_4V;
2527 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2528 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2529 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2530 SSEPackedDouble>, PD, VEX_4V;
2531 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2532 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2535 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2536 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2539 let Constraints = "$src1 = $dst" in {
2540 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2541 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2542 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2543 SSEPackedSingle, SSE_ALU_F32P>, PS;
2544 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2545 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2546 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2547 SSEPackedDouble, SSE_ALU_F64P>, PD;
2550 let Predicates = [HasAVX] in {
2551 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2552 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2553 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2554 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2555 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2556 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2557 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2558 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2560 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2561 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2562 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2563 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2564 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2565 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2566 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2567 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2570 let Predicates = [UseSSE1] in {
2571 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2572 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2573 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2574 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2577 let Predicates = [UseSSE2] in {
2578 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2579 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2580 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2581 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2584 //===----------------------------------------------------------------------===//
2585 // SSE 1 & 2 - Shuffle Instructions
2586 //===----------------------------------------------------------------------===//
2588 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2589 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2590 ValueType vt, string asm, PatFrag mem_frag,
2591 Domain d, bit IsConvertibleToThreeAddress = 0> {
2592 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2593 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2594 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2595 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2596 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2597 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2598 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2599 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2600 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2601 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2602 Sched<[WriteFShuffle]>;
2605 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2606 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2607 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2608 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2609 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2610 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2611 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2612 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2613 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2614 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2615 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2616 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2618 let Constraints = "$src1 = $dst" in {
2619 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2620 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2621 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, PS;
2622 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2623 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2624 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
2627 let Predicates = [HasAVX] in {
2628 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2629 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2630 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2631 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2632 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2634 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2635 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2636 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2637 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2638 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2641 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2642 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2643 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2644 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2645 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2647 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2648 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2649 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2650 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2651 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2654 let Predicates = [UseSSE1] in {
2655 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2656 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2657 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2658 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2659 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2662 let Predicates = [UseSSE2] in {
2663 // Generic SHUFPD patterns
2664 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2665 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2666 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2667 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2668 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2671 //===----------------------------------------------------------------------===//
2672 // SSE 1 & 2 - Unpack FP Instructions
2673 //===----------------------------------------------------------------------===//
2675 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2676 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2677 PatFrag mem_frag, RegisterClass RC,
2678 X86MemOperand x86memop, string asm,
2680 def rr : PI<opc, MRMSrcReg,
2681 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2683 (vt (OpNode RC:$src1, RC:$src2)))],
2684 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2685 def rm : PI<opc, MRMSrcMem,
2686 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2688 (vt (OpNode RC:$src1,
2689 (mem_frag addr:$src2))))],
2691 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2694 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2695 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 SSEPackedSingle>, PS, VEX_4V;
2697 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2698 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedDouble>, PD, VEX_4V;
2700 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2701 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedSingle>, PS, VEX_4V;
2703 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2704 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedDouble>, PD, VEX_4V;
2707 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2708 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2710 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2711 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2713 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2714 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2715 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2716 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2717 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2720 let Constraints = "$src1 = $dst" in {
2721 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2722 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2723 SSEPackedSingle>, PS;
2724 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2725 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2726 SSEPackedDouble>, PD;
2727 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2728 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2729 SSEPackedSingle>, PS;
2730 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2731 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2732 SSEPackedDouble>, PD;
2733 } // Constraints = "$src1 = $dst"
2735 let Predicates = [HasAVX1Only] in {
2736 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2737 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2738 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2739 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2740 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2741 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2742 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2743 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2745 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2746 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2747 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2748 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2749 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2750 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2751 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2752 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2755 let Predicates = [HasAVX] in {
2756 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2757 // problem is during lowering, where it's not possible to recognize the load
2758 // fold cause it has two uses through a bitcast. One use disappears at isel
2759 // time and the fold opportunity reappears.
2760 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2761 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2764 let Predicates = [UseSSE2] in {
2765 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2766 // problem is during lowering, where it's not possible to recognize the load
2767 // fold cause it has two uses through a bitcast. One use disappears at isel
2768 // time and the fold opportunity reappears.
2769 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2770 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2773 //===----------------------------------------------------------------------===//
2774 // SSE 1 & 2 - Extract Floating-Point Sign mask
2775 //===----------------------------------------------------------------------===//
2777 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2778 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2780 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2781 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2782 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2783 Sched<[WriteVecLogic]>;
2786 let Predicates = [HasAVX] in {
2787 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2788 "movmskps", SSEPackedSingle>, PS, VEX;
2789 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2790 "movmskpd", SSEPackedDouble>, PD, VEX;
2791 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2792 "movmskps", SSEPackedSingle>, PS,
2794 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2795 "movmskpd", SSEPackedDouble>, PD,
2798 def : Pat<(i32 (X86fgetsign FR32:$src)),
2799 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2800 def : Pat<(i64 (X86fgetsign FR32:$src)),
2801 (SUBREG_TO_REG (i64 0),
2802 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2803 def : Pat<(i32 (X86fgetsign FR64:$src)),
2804 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2805 def : Pat<(i64 (X86fgetsign FR64:$src)),
2806 (SUBREG_TO_REG (i64 0),
2807 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2810 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2811 SSEPackedSingle>, PS;
2812 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2813 SSEPackedDouble>, PD;
2815 def : Pat<(i32 (X86fgetsign FR32:$src)),
2816 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2817 Requires<[UseSSE1]>;
2818 def : Pat<(i64 (X86fgetsign FR32:$src)),
2819 (SUBREG_TO_REG (i64 0),
2820 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2821 Requires<[UseSSE1]>;
2822 def : Pat<(i32 (X86fgetsign FR64:$src)),
2823 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2824 Requires<[UseSSE2]>;
2825 def : Pat<(i64 (X86fgetsign FR64:$src)),
2826 (SUBREG_TO_REG (i64 0),
2827 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2828 Requires<[UseSSE2]>;
2830 //===---------------------------------------------------------------------===//
2831 // SSE2 - Packed Integer Logical Instructions
2832 //===---------------------------------------------------------------------===//
2834 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2836 /// PDI_binop_rm - Simple SSE2 binary operator.
2837 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2838 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2839 X86MemOperand x86memop, OpndItins itins,
2840 bit IsCommutable, bit Is2Addr> {
2841 let isCommutable = IsCommutable in
2842 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2843 (ins RC:$src1, RC:$src2),
2845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2847 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2848 Sched<[itins.Sched]>;
2849 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2850 (ins RC:$src1, x86memop:$src2),
2852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2854 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2855 (bitconvert (memop_frag addr:$src2)))))],
2857 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2859 } // ExeDomain = SSEPackedInt
2861 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2862 ValueType OpVT128, ValueType OpVT256,
2863 OpndItins itins, bit IsCommutable = 0> {
2864 let Predicates = [HasAVX] in
2865 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2866 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2868 let Constraints = "$src1 = $dst" in
2869 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2870 memopv2i64, i128mem, itins, IsCommutable, 1>;
2872 let Predicates = [HasAVX2] in
2873 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2874 OpVT256, VR256, loadv4i64, i256mem, itins,
2875 IsCommutable, 0>, VEX_4V, VEX_L;
2878 // These are ordered here for pattern ordering requirements with the fp versions
2880 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2881 SSE_VEC_BIT_ITINS_P, 1>;
2882 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2883 SSE_VEC_BIT_ITINS_P, 1>;
2884 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2885 SSE_VEC_BIT_ITINS_P, 1>;
2886 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2887 SSE_VEC_BIT_ITINS_P, 0>;
2889 //===----------------------------------------------------------------------===//
2890 // SSE 1 & 2 - Logical Instructions
2891 //===----------------------------------------------------------------------===//
2893 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2895 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2896 SDNode OpNode, OpndItins itins> {
2897 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2898 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2901 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2902 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2905 let Constraints = "$src1 = $dst" in {
2906 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2907 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2910 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2911 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2916 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2917 let isCodeGenOnly = 1 in {
2918 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2920 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2922 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2925 let isCommutable = 0 in
2926 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2930 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2932 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2934 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2935 !strconcat(OpcodeStr, "ps"), f256mem,
2936 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2937 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2938 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2940 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2941 !strconcat(OpcodeStr, "pd"), f256mem,
2942 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2943 (bc_v4i64 (v4f64 VR256:$src2))))],
2944 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2945 (loadv4i64 addr:$src2)))], 0>,
2948 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2949 // are all promoted to v2i64, and the patterns are covered by the int
2950 // version. This is needed in SSE only, because v2i64 isn't supported on
2951 // SSE1, but only on SSE2.
2952 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2953 !strconcat(OpcodeStr, "ps"), f128mem, [],
2954 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2955 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2957 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2958 !strconcat(OpcodeStr, "pd"), f128mem,
2959 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2960 (bc_v2i64 (v2f64 VR128:$src2))))],
2961 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2962 (loadv2i64 addr:$src2)))], 0>,
2965 let Constraints = "$src1 = $dst" in {
2966 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2967 !strconcat(OpcodeStr, "ps"), f128mem,
2968 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2969 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2970 (memopv2i64 addr:$src2)))]>, PS;
2972 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2973 !strconcat(OpcodeStr, "pd"), f128mem,
2974 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2975 (bc_v2i64 (v2f64 VR128:$src2))))],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2977 (memopv2i64 addr:$src2)))]>, PD;
2981 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2982 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2983 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2984 let isCommutable = 0 in
2985 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2987 // AVX1 requires type coercions in order to fold loads directly into logical
2989 let Predicates = [HasAVX1Only] in {
2990 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2991 (VANDPSYrm VR256:$src1, addr:$src2)>;
2992 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2993 (VORPSYrm VR256:$src1, addr:$src2)>;
2994 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2995 (VXORPSYrm VR256:$src1, addr:$src2)>;
2996 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2997 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3000 //===----------------------------------------------------------------------===//
3001 // SSE 1 & 2 - Arithmetic Instructions
3002 //===----------------------------------------------------------------------===//
3004 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3007 /// In addition, we also have a special variant of the scalar form here to
3008 /// represent the associated intrinsic operation. This form is unlike the
3009 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3010 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3012 /// These three forms can each be reg+reg or reg+mem.
3015 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3017 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3018 SDNode OpNode, SizeItins itins> {
3019 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3020 VR128, v4f32, f128mem, loadv4f32,
3021 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3022 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3023 VR128, v2f64, f128mem, loadv2f64,
3024 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3026 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3027 OpNode, VR256, v8f32, f256mem, loadv8f32,
3028 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3029 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3030 OpNode, VR256, v4f64, f256mem, loadv4f64,
3031 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3033 let Constraints = "$src1 = $dst" in {
3034 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3035 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3037 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3038 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3043 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3045 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3046 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3047 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3048 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3050 let Constraints = "$src1 = $dst" in {
3051 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3052 OpNode, FR32, f32mem, itins.s>, XS;
3053 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3054 OpNode, FR64, f64mem, itins.d>, XD;
3058 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3060 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3061 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3062 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3063 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3064 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3065 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3067 let Constraints = "$src1 = $dst" in {
3068 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3069 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3071 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3072 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3077 // Binary Arithmetic instructions
3078 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3079 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3080 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3081 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3082 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3083 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3084 let isCommutable = 0 in {
3085 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3086 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3087 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3088 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3089 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3090 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3091 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3093 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3094 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3095 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3096 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3099 let isCodeGenOnly = 1 in {
3100 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3101 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3102 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3103 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3106 // Patterns used to select SSE scalar fp arithmetic instructions from
3107 // a scalar fp operation followed by a blend.
3109 // These patterns know, for example, how to select an ADDSS from a
3110 // float add plus vector insert.
3112 // The effect is that the backend no longer emits unnecessary vector
3113 // insert instructions immediately after SSE scalar fp instructions
3114 // like addss or mulss.
3116 // For example, given the following code:
3117 // __m128 foo(__m128 A, __m128 B) {
3122 // previously we generated:
3123 // addss %xmm0, %xmm1
3124 // movss %xmm1, %xmm0
3127 // addss %xmm1, %xmm0
3129 let Predicates = [UseSSE1] in {
3130 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3131 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3133 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3134 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3135 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3137 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3138 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3139 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3141 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3142 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3143 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3145 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3148 let Predicates = [UseSSE2] in {
3149 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3151 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3152 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3154 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3155 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3156 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3158 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3159 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3160 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3162 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3163 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3164 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3166 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3169 let Predicates = [UseSSE41] in {
3170 // If the subtarget has SSE4.1 but not AVX, the vector insert
3171 // instruction is lowered into a X86insertps rather than a X86Movss.
3172 // When selecting SSE scalar single-precision fp arithmetic instructions,
3173 // make sure that we correctly match the X86insertps.
3175 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3176 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3177 FR32:$src))), (iPTR 0))),
3178 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3179 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3180 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3181 FR32:$src))), (iPTR 0))),
3182 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3183 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3184 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3185 FR32:$src))), (iPTR 0))),
3186 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3187 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3188 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3189 FR32:$src))), (iPTR 0))),
3190 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3193 let Predicates = [HasAVX] in {
3194 // The following patterns select AVX Scalar single/double precision fp
3195 // arithmetic instructions.
3197 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3198 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3200 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3201 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3202 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3204 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3205 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3206 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3208 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3209 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3210 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3212 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3213 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3214 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3215 FR32:$src))), (iPTR 0))),
3216 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3217 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3218 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3219 FR32:$src))), (iPTR 0))),
3220 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3221 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3222 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3223 FR32:$src))), (iPTR 0))),
3224 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3225 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3226 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3227 FR32:$src))), (iPTR 0))),
3228 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3231 // Patterns used to select SSE scalar fp arithmetic instructions from
3232 // a vector packed single/double fp operation followed by a vector insert.
3234 // The effect is that the backend converts the packed fp instruction
3235 // followed by a vector insert into a single SSE scalar fp instruction.
3237 // For example, given the following code:
3238 // __m128 foo(__m128 A, __m128 B) {
3239 // __m128 C = A + B;
3240 // return (__m128) {c[0], a[1], a[2], a[3]};
3243 // previously we generated:
3244 // addps %xmm0, %xmm1
3245 // movss %xmm1, %xmm0
3248 // addss %xmm1, %xmm0
3250 let Predicates = [UseSSE1] in {
3251 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3252 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3253 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3254 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3255 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3256 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3257 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3258 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3259 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3260 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3261 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3262 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3265 let Predicates = [UseSSE2] in {
3266 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3267 // from a packed double-precision fp instruction plus movsd.
3269 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3270 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3271 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3272 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3273 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3274 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3275 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3276 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3277 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3278 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3279 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3280 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3283 let Predicates = [HasAVX] in {
3284 // The following patterns select AVX Scalar single/double precision fp
3285 // arithmetic instructions from a packed single precision fp instruction
3286 // plus movss/movsd.
3288 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3289 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3290 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3291 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3292 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3293 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3294 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3295 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3296 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3297 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3298 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3299 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3300 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3301 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3302 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3303 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3304 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3305 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3306 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3307 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3308 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3309 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3310 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3311 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3315 /// In addition, we also have a special variant of the scalar form here to
3316 /// represent the associated intrinsic operation. This form is unlike the
3317 /// plain scalar form, in that it takes an entire vector (instead of a
3318 /// scalar) and leaves the top elements undefined.
3320 /// And, we have a special variant form for a full-vector intrinsic form.
3322 let Sched = WriteFSqrt in {
3323 def SSE_SQRTPS : OpndItins<
3324 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3327 def SSE_SQRTSS : OpndItins<
3328 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3331 def SSE_SQRTPD : OpndItins<
3332 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3335 def SSE_SQRTSD : OpndItins<
3336 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3340 let Sched = WriteFRcp in {
3341 def SSE_RCPP : OpndItins<
3342 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3345 def SSE_RCPS : OpndItins<
3346 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3350 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3351 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3352 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3353 let Predicates = [HasAVX], hasSideEffects = 0 in {
3354 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3355 (ins FR32:$src1, FR32:$src2),
3356 !strconcat("v", OpcodeStr,
3357 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3358 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3359 let mayLoad = 1 in {
3360 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3361 (ins FR32:$src1,f32mem:$src2),
3362 !strconcat("v", OpcodeStr,
3363 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3364 []>, VEX_4V, VEX_LIG,
3365 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3366 let isCodeGenOnly = 1 in
3367 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3368 (ins VR128:$src1, ssmem:$src2),
3369 !strconcat("v", OpcodeStr,
3370 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3371 []>, VEX_4V, VEX_LIG,
3372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3376 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3377 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3378 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3379 // For scalar unary operations, fold a load into the operation
3380 // only in OptForSize mode. It eliminates an instruction, but it also
3381 // eliminates a whole-register clobber (the load), so it introduces a
3382 // partial register update condition.
3383 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3384 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3385 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3386 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3387 let isCodeGenOnly = 1 in {
3388 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3389 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3390 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3391 Sched<[itins.Sched]>;
3392 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3393 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3394 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3395 Sched<[itins.Sched.Folded]>;
3399 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3400 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3402 let Predicates = [HasAVX], hasSideEffects = 0 in {
3403 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3404 (ins FR32:$src1, FR32:$src2),
3405 !strconcat("v", OpcodeStr,
3406 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3408 let mayLoad = 1 in {
3409 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3410 (ins FR32:$src1,f32mem:$src2),
3411 !strconcat("v", OpcodeStr,
3412 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3413 []>, VEX_4V, VEX_LIG,
3414 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3415 let isCodeGenOnly = 1 in
3416 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3417 (ins VR128:$src1, ssmem:$src2),
3418 !strconcat("v", OpcodeStr,
3419 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3420 []>, VEX_4V, VEX_LIG,
3421 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3425 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3426 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3427 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3428 // For scalar unary operations, fold a load into the operation
3429 // only in OptForSize mode. It eliminates an instruction, but it also
3430 // eliminates a whole-register clobber (the load), so it introduces a
3431 // partial register update condition.
3432 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3433 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3434 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3435 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3436 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3437 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3438 (ins VR128:$src1, VR128:$src2),
3439 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3440 [], itins.rr>, Sched<[itins.Sched]>;
3441 let mayLoad = 1, hasSideEffects = 0 in
3442 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3443 (ins VR128:$src1, ssmem:$src2),
3444 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3445 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3449 /// sse1_fp_unop_p - SSE1 unops in packed form.
3450 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3452 let Predicates = [HasAVX] in {
3453 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3454 !strconcat("v", OpcodeStr,
3455 "ps\t{$src, $dst|$dst, $src}"),
3456 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3457 itins.rr>, VEX, Sched<[itins.Sched]>;
3458 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3459 !strconcat("v", OpcodeStr,
3460 "ps\t{$src, $dst|$dst, $src}"),
3461 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3462 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3463 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3464 !strconcat("v", OpcodeStr,
3465 "ps\t{$src, $dst|$dst, $src}"),
3466 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3467 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3468 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3469 !strconcat("v", OpcodeStr,
3470 "ps\t{$src, $dst|$dst, $src}"),
3471 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3472 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3475 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3476 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3477 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3478 Sched<[itins.Sched]>;
3479 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3480 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3481 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3482 Sched<[itins.Sched.Folded]>;
3485 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3486 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3487 Intrinsic V4F32Int, Intrinsic V8F32Int,
3489 let isCodeGenOnly = 1 in {
3490 let Predicates = [HasAVX] in {
3491 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 !strconcat("v", OpcodeStr,
3493 "ps\t{$src, $dst|$dst, $src}"),
3494 [(set VR128:$dst, (V4F32Int VR128:$src))],
3495 itins.rr>, VEX, Sched<[itins.Sched]>;
3496 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3497 !strconcat("v", OpcodeStr,
3498 "ps\t{$src, $dst|$dst, $src}"),
3499 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3500 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3501 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3502 !strconcat("v", OpcodeStr,
3503 "ps\t{$src, $dst|$dst, $src}"),
3504 [(set VR256:$dst, (V8F32Int VR256:$src))],
3505 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3506 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3508 !strconcat("v", OpcodeStr,
3509 "ps\t{$src, $dst|$dst, $src}"),
3510 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3511 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3514 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3515 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3516 [(set VR128:$dst, (V4F32Int VR128:$src))],
3517 itins.rr>, Sched<[itins.Sched]>;
3518 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3519 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3520 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3521 itins.rm>, Sched<[itins.Sched.Folded]>;
3522 } // isCodeGenOnly = 1
3525 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3526 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3527 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3528 let Predicates = [HasAVX], hasSideEffects = 0 in {
3529 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3530 (ins FR64:$src1, FR64:$src2),
3531 !strconcat("v", OpcodeStr,
3532 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3533 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3534 let mayLoad = 1 in {
3535 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3536 (ins FR64:$src1,f64mem:$src2),
3537 !strconcat("v", OpcodeStr,
3538 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3539 []>, VEX_4V, VEX_LIG,
3540 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3541 let isCodeGenOnly = 1 in
3542 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3543 (ins VR128:$src1, sdmem:$src2),
3544 !strconcat("v", OpcodeStr,
3545 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3546 []>, VEX_4V, VEX_LIG,
3547 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3551 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3552 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3553 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3554 Sched<[itins.Sched]>;
3555 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3556 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3557 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3558 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3559 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3560 let isCodeGenOnly = 1 in {
3561 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3562 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3563 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3564 Sched<[itins.Sched]>;
3565 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3566 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3567 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3568 Sched<[itins.Sched.Folded]>;
3572 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3573 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3574 SDNode OpNode, OpndItins itins> {
3575 let Predicates = [HasAVX] in {
3576 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3577 !strconcat("v", OpcodeStr,
3578 "pd\t{$src, $dst|$dst, $src}"),
3579 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3580 itins.rr>, VEX, Sched<[itins.Sched]>;
3581 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3582 !strconcat("v", OpcodeStr,
3583 "pd\t{$src, $dst|$dst, $src}"),
3584 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3585 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3586 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3587 !strconcat("v", OpcodeStr,
3588 "pd\t{$src, $dst|$dst, $src}"),
3589 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3590 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3591 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3592 !strconcat("v", OpcodeStr,
3593 "pd\t{$src, $dst|$dst, $src}"),
3594 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3595 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3598 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3599 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3600 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3601 Sched<[itins.Sched]>;
3602 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3603 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3604 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3605 Sched<[itins.Sched.Folded]>;
3609 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3611 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3612 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3614 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3616 // Reciprocal approximations. Note that these typically require refinement
3617 // in order to obtain suitable precision.
3618 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3619 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3620 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3621 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3622 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3623 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3624 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3625 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3627 let Predicates = [UseAVX] in {
3628 def : Pat<(f32 (fsqrt FR32:$src)),
3629 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3630 def : Pat<(f32 (fsqrt (load addr:$src))),
3631 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3632 Requires<[HasAVX, OptForSize]>;
3633 def : Pat<(f64 (fsqrt FR64:$src)),
3634 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3635 def : Pat<(f64 (fsqrt (load addr:$src))),
3636 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3637 Requires<[HasAVX, OptForSize]>;
3639 def : Pat<(f32 (X86frsqrt FR32:$src)),
3640 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3641 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3642 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3643 Requires<[HasAVX, OptForSize]>;
3645 def : Pat<(f32 (X86frcp FR32:$src)),
3646 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3647 def : Pat<(f32 (X86frcp (load addr:$src))),
3648 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3649 Requires<[HasAVX, OptForSize]>;
3651 let Predicates = [UseAVX] in {
3652 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3653 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3654 (COPY_TO_REGCLASS VR128:$src, FR32)),
3656 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3657 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3659 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3660 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3661 (COPY_TO_REGCLASS VR128:$src, FR64)),
3663 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3664 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3667 let Predicates = [HasAVX] in {
3668 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3669 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3670 (COPY_TO_REGCLASS VR128:$src, FR32)),
3672 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3673 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3675 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3676 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3677 (COPY_TO_REGCLASS VR128:$src, FR32)),
3679 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3680 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3683 // Reciprocal approximations. Note that these typically require refinement
3684 // in order to obtain suitable precision.
3685 let Predicates = [UseSSE1] in {
3686 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3687 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3688 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3689 (RCPSSr_Int VR128:$src, VR128:$src)>;
3692 // There is no f64 version of the reciprocal approximation instructions.
3694 //===----------------------------------------------------------------------===//
3695 // SSE 1 & 2 - Non-temporal stores
3696 //===----------------------------------------------------------------------===//
3698 let AddedComplexity = 400 in { // Prefer non-temporal versions
3699 let SchedRW = [WriteStore] in {
3700 let Predicates = [HasAVX, NoVLX] in {
3701 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3702 (ins f128mem:$dst, VR128:$src),
3703 "movntps\t{$src, $dst|$dst, $src}",
3704 [(alignednontemporalstore (v4f32 VR128:$src),
3706 IIC_SSE_MOVNT>, VEX;
3707 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3708 (ins f128mem:$dst, VR128:$src),
3709 "movntpd\t{$src, $dst|$dst, $src}",
3710 [(alignednontemporalstore (v2f64 VR128:$src),
3712 IIC_SSE_MOVNT>, VEX;
3714 let ExeDomain = SSEPackedInt in
3715 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3716 (ins f128mem:$dst, VR128:$src),
3717 "movntdq\t{$src, $dst|$dst, $src}",
3718 [(alignednontemporalstore (v2i64 VR128:$src),
3720 IIC_SSE_MOVNT>, VEX;
3722 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3723 (ins f256mem:$dst, VR256:$src),
3724 "movntps\t{$src, $dst|$dst, $src}",
3725 [(alignednontemporalstore (v8f32 VR256:$src),
3727 IIC_SSE_MOVNT>, VEX, VEX_L;
3728 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3729 (ins f256mem:$dst, VR256:$src),
3730 "movntpd\t{$src, $dst|$dst, $src}",
3731 [(alignednontemporalstore (v4f64 VR256:$src),
3733 IIC_SSE_MOVNT>, VEX, VEX_L;
3734 let ExeDomain = SSEPackedInt in
3735 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3736 (ins f256mem:$dst, VR256:$src),
3737 "movntdq\t{$src, $dst|$dst, $src}",
3738 [(alignednontemporalstore (v4i64 VR256:$src),
3740 IIC_SSE_MOVNT>, VEX, VEX_L;
3743 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3744 "movntps\t{$src, $dst|$dst, $src}",
3745 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3747 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3748 "movntpd\t{$src, $dst|$dst, $src}",
3749 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3752 let ExeDomain = SSEPackedInt in
3753 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3754 "movntdq\t{$src, $dst|$dst, $src}",
3755 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3758 // There is no AVX form for instructions below this point
3759 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3760 "movnti{l}\t{$src, $dst|$dst, $src}",
3761 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3763 PS, Requires<[HasSSE2]>;
3764 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3765 "movnti{q}\t{$src, $dst|$dst, $src}",
3766 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3768 PS, Requires<[HasSSE2]>;
3769 } // SchedRW = [WriteStore]
3771 } // AddedComplexity
3773 //===----------------------------------------------------------------------===//
3774 // SSE 1 & 2 - Prefetch and memory fence
3775 //===----------------------------------------------------------------------===//
3777 // Prefetch intrinsic.
3778 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3779 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3780 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3781 IIC_SSE_PREFETCH>, TB;
3782 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3783 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3784 IIC_SSE_PREFETCH>, TB;
3785 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3786 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3787 IIC_SSE_PREFETCH>, TB;
3788 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3789 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3790 IIC_SSE_PREFETCH>, TB;
3793 // FIXME: How should flush instruction be modeled?
3794 let SchedRW = [WriteLoad] in {
3796 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3797 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3798 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3801 let SchedRW = [WriteNop] in {
3802 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3803 // was introduced with SSE2, it's backward compatible.
3804 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3805 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3806 OBXS, Requires<[HasSSE2]>;
3809 let SchedRW = [WriteFence] in {
3810 // Load, store, and memory fence
3811 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3812 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3813 TB, Requires<[HasSSE1]>;
3814 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3815 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3816 TB, Requires<[HasSSE2]>;
3817 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3818 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3819 TB, Requires<[HasSSE2]>;
3822 def : Pat<(X86SFence), (SFENCE)>;
3823 def : Pat<(X86LFence), (LFENCE)>;
3824 def : Pat<(X86MFence), (MFENCE)>;
3826 //===----------------------------------------------------------------------===//
3827 // SSE 1 & 2 - Load/Store XCSR register
3828 //===----------------------------------------------------------------------===//
3830 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3831 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3832 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3833 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3834 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3835 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3837 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3838 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3839 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3840 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3841 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3842 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3844 //===---------------------------------------------------------------------===//
3845 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3846 //===---------------------------------------------------------------------===//
3848 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3850 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3851 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3852 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3854 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3855 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3857 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3858 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3860 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3861 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3866 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3867 SchedRW = [WriteMove] in {
3868 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3869 "movdqa\t{$src, $dst|$dst, $src}", [],
3872 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3873 "movdqa\t{$src, $dst|$dst, $src}", [],
3874 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3875 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3876 "movdqu\t{$src, $dst|$dst, $src}", [],
3879 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3880 "movdqu\t{$src, $dst|$dst, $src}", [],
3881 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3884 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3885 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3886 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3887 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3889 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3890 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3892 let Predicates = [HasAVX] in {
3893 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3894 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3896 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3897 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3902 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3903 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3904 (ins i128mem:$dst, VR128:$src),
3905 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3907 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3908 (ins i256mem:$dst, VR256:$src),
3909 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3911 let Predicates = [HasAVX] in {
3912 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3913 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3915 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3916 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3921 let SchedRW = [WriteMove] in {
3922 let neverHasSideEffects = 1 in
3923 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3924 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3926 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3927 "movdqu\t{$src, $dst|$dst, $src}",
3928 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3931 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3932 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3933 "movdqa\t{$src, $dst|$dst, $src}", [],
3936 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3937 "movdqu\t{$src, $dst|$dst, $src}",
3938 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3942 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3943 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3944 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3945 "movdqa\t{$src, $dst|$dst, $src}",
3946 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3948 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3949 "movdqu\t{$src, $dst|$dst, $src}",
3950 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3952 XS, Requires<[UseSSE2]>;
3955 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3956 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3957 "movdqa\t{$src, $dst|$dst, $src}",
3958 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3960 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3961 "movdqu\t{$src, $dst|$dst, $src}",
3962 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3964 XS, Requires<[UseSSE2]>;
3967 } // ExeDomain = SSEPackedInt
3969 let Predicates = [HasAVX] in {
3970 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3971 (VMOVDQUmr addr:$dst, VR128:$src)>;
3972 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3973 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3975 let Predicates = [UseSSE2] in
3976 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3977 (MOVDQUmr addr:$dst, VR128:$src)>;
3979 //===---------------------------------------------------------------------===//
3980 // SSE2 - Packed Integer Arithmetic Instructions
3981 //===---------------------------------------------------------------------===//
3983 let Sched = WriteVecIMul in
3984 def SSE_PMADD : OpndItins<
3985 IIC_SSE_PMADD, IIC_SSE_PMADD
3988 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3990 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3991 RegisterClass RC, PatFrag memop_frag,
3992 X86MemOperand x86memop,
3994 bit IsCommutable = 0,
3996 let isCommutable = IsCommutable in
3997 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3998 (ins RC:$src1, RC:$src2),
4000 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4002 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4003 Sched<[itins.Sched]>;
4004 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4005 (ins RC:$src1, x86memop:$src2),
4007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4009 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4010 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4013 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4014 Intrinsic IntId256, OpndItins itins,
4015 bit IsCommutable = 0> {
4016 let Predicates = [HasAVX] in
4017 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4018 VR128, loadv2i64, i128mem, itins,
4019 IsCommutable, 0>, VEX_4V;
4021 let Constraints = "$src1 = $dst" in
4022 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4023 i128mem, itins, IsCommutable, 1>;
4025 let Predicates = [HasAVX2] in
4026 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4027 VR256, loadv4i64, i256mem, itins,
4028 IsCommutable, 0>, VEX_4V, VEX_L;
4031 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4032 string OpcodeStr, SDNode OpNode,
4033 SDNode OpNode2, RegisterClass RC,
4034 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4035 ShiftOpndItins itins,
4037 // src2 is always 128-bit
4038 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4039 (ins RC:$src1, VR128:$src2),
4041 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4042 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4043 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4044 itins.rr>, Sched<[WriteVecShift]>;
4045 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4046 (ins RC:$src1, i128mem:$src2),
4048 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4050 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4051 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4052 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4053 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4054 (ins RC:$src1, i8imm:$src2),
4056 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4057 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4058 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4059 Sched<[WriteVecShift]>;
4062 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4063 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4064 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4065 PatFrag memop_frag, X86MemOperand x86memop,
4067 bit IsCommutable = 0, bit Is2Addr = 1> {
4068 let isCommutable = IsCommutable in
4069 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4070 (ins RC:$src1, RC:$src2),
4072 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4073 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4074 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4075 Sched<[itins.Sched]>;
4076 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4077 (ins RC:$src1, x86memop:$src2),
4079 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4081 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4082 (bitconvert (memop_frag addr:$src2)))))]>,
4083 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4085 } // ExeDomain = SSEPackedInt
4087 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4088 SSE_INTALU_ITINS_P, 1>;
4089 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4090 SSE_INTALU_ITINS_P, 1>;
4091 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4092 SSE_INTALU_ITINS_P, 1>;
4093 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4094 SSE_INTALUQ_ITINS_P, 1>;
4095 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4096 SSE_INTMUL_ITINS_P, 1>;
4097 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4098 SSE_INTMUL_ITINS_P, 1>;
4099 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4100 SSE_INTMUL_ITINS_P, 1>;
4101 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4102 SSE_INTALU_ITINS_P, 0>;
4103 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4104 SSE_INTALU_ITINS_P, 0>;
4105 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4106 SSE_INTALU_ITINS_P, 0>;
4107 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4108 SSE_INTALUQ_ITINS_P, 0>;
4109 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4110 SSE_INTALU_ITINS_P, 0>;
4111 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4112 SSE_INTALU_ITINS_P, 0>;
4113 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4114 SSE_INTALU_ITINS_P, 1>;
4115 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4116 SSE_INTALU_ITINS_P, 1>;
4117 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4118 SSE_INTALU_ITINS_P, 1>;
4119 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4120 SSE_INTALU_ITINS_P, 1>;
4123 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4124 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4125 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4126 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4127 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4128 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4129 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4130 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4131 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4132 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4133 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4134 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4135 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4136 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4137 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4138 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4139 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4140 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4141 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4142 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4144 let Predicates = [HasAVX] in
4145 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4146 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4148 let Predicates = [HasAVX2] in
4149 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4150 VR256, loadv4i64, i256mem,
4151 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4152 let Constraints = "$src1 = $dst" in
4153 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4154 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4156 //===---------------------------------------------------------------------===//
4157 // SSE2 - Packed Integer Logical Instructions
4158 //===---------------------------------------------------------------------===//
4160 let Predicates = [HasAVX] in {
4161 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4162 VR128, v8i16, v8i16, bc_v8i16,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4164 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4165 VR128, v4i32, v4i32, bc_v4i32,
4166 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4167 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4168 VR128, v2i64, v2i64, bc_v2i64,
4169 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4171 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4172 VR128, v8i16, v8i16, bc_v8i16,
4173 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4174 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4175 VR128, v4i32, v4i32, bc_v4i32,
4176 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4177 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4178 VR128, v2i64, v2i64, bc_v2i64,
4179 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4181 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4182 VR128, v8i16, v8i16, bc_v8i16,
4183 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4184 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4185 VR128, v4i32, v4i32, bc_v4i32,
4186 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4188 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4189 // 128-bit logical shifts.
4190 def VPSLLDQri : PDIi8<0x73, MRM7r,
4191 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4192 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4194 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4196 def VPSRLDQri : PDIi8<0x73, MRM3r,
4197 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4198 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4200 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4202 // PSRADQri doesn't exist in SSE[1-3].
4204 } // Predicates = [HasAVX]
4206 let Predicates = [HasAVX2] in {
4207 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4208 VR256, v16i16, v8i16, bc_v8i16,
4209 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4210 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4211 VR256, v8i32, v4i32, bc_v4i32,
4212 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4213 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4214 VR256, v4i64, v2i64, bc_v2i64,
4215 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4217 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4218 VR256, v16i16, v8i16, bc_v8i16,
4219 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4220 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4221 VR256, v8i32, v4i32, bc_v4i32,
4222 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4223 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4224 VR256, v4i64, v2i64, bc_v2i64,
4225 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4227 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4228 VR256, v16i16, v8i16, bc_v8i16,
4229 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4230 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4231 VR256, v8i32, v4i32, bc_v4i32,
4232 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4234 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4235 // 256-bit logical shifts.
4236 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4237 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4238 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4240 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4242 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4243 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4244 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4246 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4248 // PSRADQYri doesn't exist in SSE[1-3].
4250 } // Predicates = [HasAVX2]
4252 let Constraints = "$src1 = $dst" in {
4253 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4254 VR128, v8i16, v8i16, bc_v8i16,
4255 SSE_INTSHIFT_ITINS_P>;
4256 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4257 VR128, v4i32, v4i32, bc_v4i32,
4258 SSE_INTSHIFT_ITINS_P>;
4259 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4260 VR128, v2i64, v2i64, bc_v2i64,
4261 SSE_INTSHIFT_ITINS_P>;
4263 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4264 VR128, v8i16, v8i16, bc_v8i16,
4265 SSE_INTSHIFT_ITINS_P>;
4266 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4267 VR128, v4i32, v4i32, bc_v4i32,
4268 SSE_INTSHIFT_ITINS_P>;
4269 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4270 VR128, v2i64, v2i64, bc_v2i64,
4271 SSE_INTSHIFT_ITINS_P>;
4273 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4274 VR128, v8i16, v8i16, bc_v8i16,
4275 SSE_INTSHIFT_ITINS_P>;
4276 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4277 VR128, v4i32, v4i32, bc_v4i32,
4278 SSE_INTSHIFT_ITINS_P>;
4280 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4281 // 128-bit logical shifts.
4282 def PSLLDQri : PDIi8<0x73, MRM7r,
4283 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4284 "pslldq\t{$src2, $dst|$dst, $src2}",
4286 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4287 IIC_SSE_INTSHDQ_P_RI>;
4288 def PSRLDQri : PDIi8<0x73, MRM3r,
4289 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4290 "psrldq\t{$src2, $dst|$dst, $src2}",
4292 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4293 IIC_SSE_INTSHDQ_P_RI>;
4294 // PSRADQri doesn't exist in SSE[1-3].
4296 } // Constraints = "$src1 = $dst"
4298 let Predicates = [HasAVX] in {
4299 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4300 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4301 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4302 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4303 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4304 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4306 // Shift up / down and insert zero's.
4307 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4308 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4309 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4310 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4313 let Predicates = [HasAVX2] in {
4314 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4315 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4316 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4317 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4320 let Predicates = [UseSSE2] in {
4321 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4322 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4323 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4324 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4325 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4326 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4328 // Shift up / down and insert zero's.
4329 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4330 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4331 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4332 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4335 //===---------------------------------------------------------------------===//
4336 // SSE2 - Packed Integer Comparison Instructions
4337 //===---------------------------------------------------------------------===//
4339 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4340 SSE_INTALU_ITINS_P, 1>;
4341 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4342 SSE_INTALU_ITINS_P, 1>;
4343 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4344 SSE_INTALU_ITINS_P, 1>;
4345 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4346 SSE_INTALU_ITINS_P, 0>;
4347 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4348 SSE_INTALU_ITINS_P, 0>;
4349 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4350 SSE_INTALU_ITINS_P, 0>;
4352 //===---------------------------------------------------------------------===//
4353 // SSE2 - Packed Integer Shuffle Instructions
4354 //===---------------------------------------------------------------------===//
4356 let ExeDomain = SSEPackedInt in {
4357 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4359 let Predicates = [HasAVX] in {
4360 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4361 (ins VR128:$src1, i8imm:$src2),
4362 !strconcat("v", OpcodeStr,
4363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4365 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4366 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4367 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4368 (ins i128mem:$src1, i8imm:$src2),
4369 !strconcat("v", OpcodeStr,
4370 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4372 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4373 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4374 Sched<[WriteShuffleLd]>;
4377 let Predicates = [HasAVX2] in {
4378 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4379 (ins VR256:$src1, i8imm:$src2),
4380 !strconcat("v", OpcodeStr,
4381 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4383 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4384 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4385 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4386 (ins i256mem:$src1, i8imm:$src2),
4387 !strconcat("v", OpcodeStr,
4388 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4390 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4391 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4392 Sched<[WriteShuffleLd]>;
4395 let Predicates = [UseSSE2] in {
4396 def ri : Ii8<0x70, MRMSrcReg,
4397 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4398 !strconcat(OpcodeStr,
4399 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4401 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4402 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4403 def mi : Ii8<0x70, MRMSrcMem,
4404 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4405 !strconcat(OpcodeStr,
4406 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4408 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4409 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4410 Sched<[WriteShuffleLd, ReadAfterLd]>;
4413 } // ExeDomain = SSEPackedInt
4415 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4416 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4417 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4419 let Predicates = [HasAVX] in {
4420 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4421 (VPSHUFDmi addr:$src1, imm:$imm)>;
4422 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4423 (VPSHUFDri VR128:$src1, imm:$imm)>;
4426 let Predicates = [UseSSE2] in {
4427 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4428 (PSHUFDmi addr:$src1, imm:$imm)>;
4429 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4430 (PSHUFDri VR128:$src1, imm:$imm)>;
4433 //===---------------------------------------------------------------------===//
4434 // Packed Integer Pack Instructions (SSE & AVX)
4435 //===---------------------------------------------------------------------===//
4437 let ExeDomain = SSEPackedInt in {
4438 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4439 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4441 def rr : PDI<opc, MRMSrcReg,
4442 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4444 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4445 !strconcat(OpcodeStr,
4446 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4448 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4449 Sched<[WriteShuffle]>;
4450 def rm : PDI<opc, MRMSrcMem,
4451 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4453 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4454 !strconcat(OpcodeStr,
4455 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4457 (OutVT (OpNode VR128:$src1,
4458 (bc_frag (memopv2i64 addr:$src2)))))]>,
4459 Sched<[WriteShuffleLd, ReadAfterLd]>;
4462 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4463 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4464 def Yrr : PDI<opc, MRMSrcReg,
4465 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4466 !strconcat(OpcodeStr,
4467 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4469 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4470 Sched<[WriteShuffle]>;
4471 def Yrm : PDI<opc, MRMSrcMem,
4472 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4473 !strconcat(OpcodeStr,
4474 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4476 (OutVT (OpNode VR256:$src1,
4477 (bc_frag (memopv4i64 addr:$src2)))))]>,
4478 Sched<[WriteShuffleLd, ReadAfterLd]>;
4481 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4482 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4484 def rr : SS48I<opc, MRMSrcReg,
4485 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4487 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4488 !strconcat(OpcodeStr,
4489 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4491 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4492 Sched<[WriteShuffle]>;
4493 def rm : SS48I<opc, MRMSrcMem,
4494 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4496 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4497 !strconcat(OpcodeStr,
4498 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4500 (OutVT (OpNode VR128:$src1,
4501 (bc_frag (memopv2i64 addr:$src2)))))]>,
4502 Sched<[WriteShuffleLd, ReadAfterLd]>;
4505 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4506 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4507 def Yrr : SS48I<opc, MRMSrcReg,
4508 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4509 !strconcat(OpcodeStr,
4510 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4512 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4513 Sched<[WriteShuffle]>;
4514 def Yrm : SS48I<opc, MRMSrcMem,
4515 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4516 !strconcat(OpcodeStr,
4517 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4519 (OutVT (OpNode VR256:$src1,
4520 (bc_frag (memopv4i64 addr:$src2)))))]>,
4521 Sched<[WriteShuffleLd, ReadAfterLd]>;
4524 let Predicates = [HasAVX] in {
4525 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4526 bc_v8i16, 0>, VEX_4V;
4527 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4528 bc_v4i32, 0>, VEX_4V;
4530 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4531 bc_v8i16, 0>, VEX_4V;
4532 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4533 bc_v4i32, 0>, VEX_4V;
4536 let Predicates = [HasAVX2] in {
4537 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4538 bc_v16i16>, VEX_4V, VEX_L;
4539 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4540 bc_v8i32>, VEX_4V, VEX_L;
4542 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4543 bc_v16i16>, VEX_4V, VEX_L;
4544 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4545 bc_v8i32>, VEX_4V, VEX_L;
4548 let Constraints = "$src1 = $dst" in {
4549 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4551 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4554 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4557 let Predicates = [HasSSE41] in
4558 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4561 } // ExeDomain = SSEPackedInt
4563 //===---------------------------------------------------------------------===//
4564 // SSE2 - Packed Integer Unpack Instructions
4565 //===---------------------------------------------------------------------===//
4567 let ExeDomain = SSEPackedInt in {
4568 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4569 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4570 def rr : PDI<opc, MRMSrcReg,
4571 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4573 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4574 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4575 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4576 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4577 def rm : PDI<opc, MRMSrcMem,
4578 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4580 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4581 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4582 [(set VR128:$dst, (OpNode VR128:$src1,
4583 (bc_frag (memopv2i64
4586 Sched<[WriteShuffleLd, ReadAfterLd]>;
4589 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4590 SDNode OpNode, PatFrag bc_frag> {
4591 def Yrr : PDI<opc, MRMSrcReg,
4592 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4593 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4594 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4595 Sched<[WriteShuffle]>;
4596 def Yrm : PDI<opc, MRMSrcMem,
4597 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4598 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4599 [(set VR256:$dst, (OpNode VR256:$src1,
4600 (bc_frag (memopv4i64 addr:$src2))))]>,
4601 Sched<[WriteShuffleLd, ReadAfterLd]>;
4604 let Predicates = [HasAVX] in {
4605 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4606 bc_v16i8, 0>, VEX_4V;
4607 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4608 bc_v8i16, 0>, VEX_4V;
4609 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4610 bc_v4i32, 0>, VEX_4V;
4611 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4612 bc_v2i64, 0>, VEX_4V;
4614 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4615 bc_v16i8, 0>, VEX_4V;
4616 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4617 bc_v8i16, 0>, VEX_4V;
4618 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4619 bc_v4i32, 0>, VEX_4V;
4620 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4621 bc_v2i64, 0>, VEX_4V;
4624 let Predicates = [HasAVX2] in {
4625 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4626 bc_v32i8>, VEX_4V, VEX_L;
4627 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4628 bc_v16i16>, VEX_4V, VEX_L;
4629 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4630 bc_v8i32>, VEX_4V, VEX_L;
4631 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4632 bc_v4i64>, VEX_4V, VEX_L;
4634 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4635 bc_v32i8>, VEX_4V, VEX_L;
4636 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4637 bc_v16i16>, VEX_4V, VEX_L;
4638 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4639 bc_v8i32>, VEX_4V, VEX_L;
4640 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4641 bc_v4i64>, VEX_4V, VEX_L;
4644 let Constraints = "$src1 = $dst" in {
4645 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4647 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4649 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4651 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4654 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4656 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4658 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4660 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4663 } // ExeDomain = SSEPackedInt
4665 //===---------------------------------------------------------------------===//
4666 // SSE2 - Packed Integer Extract and Insert
4667 //===---------------------------------------------------------------------===//
4669 let ExeDomain = SSEPackedInt in {
4670 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4671 def rri : Ii8<0xC4, MRMSrcReg,
4672 (outs VR128:$dst), (ins VR128:$src1,
4673 GR32orGR64:$src2, i32i8imm:$src3),
4675 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4676 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4678 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4679 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4680 def rmi : Ii8<0xC4, MRMSrcMem,
4681 (outs VR128:$dst), (ins VR128:$src1,
4682 i16mem:$src2, i32i8imm:$src3),
4684 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4685 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4687 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4688 imm:$src3))], IIC_SSE_PINSRW>,
4689 Sched<[WriteShuffleLd, ReadAfterLd]>;
4693 let Predicates = [HasAVX] in
4694 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4695 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4696 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4697 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4698 imm:$src2))]>, PD, VEX,
4699 Sched<[WriteShuffle]>;
4700 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4701 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4702 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4703 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4704 imm:$src2))], IIC_SSE_PEXTRW>,
4705 Sched<[WriteShuffleLd, ReadAfterLd]>;
4708 let Predicates = [HasAVX] in
4709 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4711 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4712 defm PINSRW : sse2_pinsrw, PD;
4714 } // ExeDomain = SSEPackedInt
4716 //===---------------------------------------------------------------------===//
4717 // SSE2 - Packed Mask Creation
4718 //===---------------------------------------------------------------------===//
4720 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4722 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4724 "pmovmskb\t{$src, $dst|$dst, $src}",
4725 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4726 IIC_SSE_MOVMSK>, VEX;
4728 let Predicates = [HasAVX2] in {
4729 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4731 "pmovmskb\t{$src, $dst|$dst, $src}",
4732 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4736 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4737 "pmovmskb\t{$src, $dst|$dst, $src}",
4738 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4741 } // ExeDomain = SSEPackedInt
4743 //===---------------------------------------------------------------------===//
4744 // SSE2 - Conditional Store
4745 //===---------------------------------------------------------------------===//
4747 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4749 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4750 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4751 (ins VR128:$src, VR128:$mask),
4752 "maskmovdqu\t{$mask, $src|$src, $mask}",
4753 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4754 IIC_SSE_MASKMOV>, VEX;
4755 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4756 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4757 (ins VR128:$src, VR128:$mask),
4758 "maskmovdqu\t{$mask, $src|$src, $mask}",
4759 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4760 IIC_SSE_MASKMOV>, VEX;
4762 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4763 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4764 "maskmovdqu\t{$mask, $src|$src, $mask}",
4765 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4767 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4768 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4769 "maskmovdqu\t{$mask, $src|$src, $mask}",
4770 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4773 } // ExeDomain = SSEPackedInt
4775 //===---------------------------------------------------------------------===//
4776 // SSE2 - Move Doubleword
4777 //===---------------------------------------------------------------------===//
4779 //===---------------------------------------------------------------------===//
4780 // Move Int Doubleword to Packed Double Int
4782 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4783 "movd\t{$src, $dst|$dst, $src}",
4785 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4786 VEX, Sched<[WriteMove]>;
4787 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4788 "movd\t{$src, $dst|$dst, $src}",
4790 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4792 VEX, Sched<[WriteLoad]>;
4793 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4794 "movq\t{$src, $dst|$dst, $src}",
4796 (v2i64 (scalar_to_vector GR64:$src)))],
4797 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4798 let isCodeGenOnly = 1 in
4799 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4800 "movq\t{$src, $dst|$dst, $src}",
4801 [(set FR64:$dst, (bitconvert GR64:$src))],
4802 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4804 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4805 "movd\t{$src, $dst|$dst, $src}",
4807 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4809 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4810 "movd\t{$src, $dst|$dst, $src}",
4812 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4813 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4814 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4815 "mov{d|q}\t{$src, $dst|$dst, $src}",
4817 (v2i64 (scalar_to_vector GR64:$src)))],
4818 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4819 let isCodeGenOnly = 1 in
4820 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4821 "mov{d|q}\t{$src, $dst|$dst, $src}",
4822 [(set FR64:$dst, (bitconvert GR64:$src))],
4823 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4825 //===---------------------------------------------------------------------===//
4826 // Move Int Doubleword to Single Scalar
4828 let isCodeGenOnly = 1 in {
4829 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4830 "movd\t{$src, $dst|$dst, $src}",
4831 [(set FR32:$dst, (bitconvert GR32:$src))],
4832 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4834 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4835 "movd\t{$src, $dst|$dst, $src}",
4836 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4838 VEX, Sched<[WriteLoad]>;
4839 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4840 "movd\t{$src, $dst|$dst, $src}",
4841 [(set FR32:$dst, (bitconvert GR32:$src))],
4842 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4844 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4845 "movd\t{$src, $dst|$dst, $src}",
4846 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4847 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4850 //===---------------------------------------------------------------------===//
4851 // Move Packed Doubleword Int to Packed Double Int
4853 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4854 "movd\t{$src, $dst|$dst, $src}",
4855 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4856 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4858 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4859 (ins i32mem:$dst, VR128:$src),
4860 "movd\t{$src, $dst|$dst, $src}",
4861 [(store (i32 (vector_extract (v4i32 VR128:$src),
4862 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4863 VEX, Sched<[WriteStore]>;
4864 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4865 "movd\t{$src, $dst|$dst, $src}",
4866 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4867 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4869 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4870 "movd\t{$src, $dst|$dst, $src}",
4871 [(store (i32 (vector_extract (v4i32 VR128:$src),
4872 (iPTR 0))), addr:$dst)],
4873 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4875 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4876 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4878 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4879 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4881 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4882 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4884 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4885 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4887 //===---------------------------------------------------------------------===//
4888 // Move Packed Doubleword Int first element to Doubleword Int
4890 let SchedRW = [WriteMove] in {
4891 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4892 "movq\t{$src, $dst|$dst, $src}",
4893 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4898 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4899 "mov{d|q}\t{$src, $dst|$dst, $src}",
4900 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4905 //===---------------------------------------------------------------------===//
4906 // Bitcast FR64 <-> GR64
4908 let isCodeGenOnly = 1 in {
4909 let Predicates = [UseAVX] in
4910 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4911 "movq\t{$src, $dst|$dst, $src}",
4912 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4913 VEX, Sched<[WriteLoad]>;
4914 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4915 "movq\t{$src, $dst|$dst, $src}",
4916 [(set GR64:$dst, (bitconvert FR64:$src))],
4917 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4918 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4919 "movq\t{$src, $dst|$dst, $src}",
4920 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4921 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4923 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4924 "movq\t{$src, $dst|$dst, $src}",
4925 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4926 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4927 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4928 "mov{d|q}\t{$src, $dst|$dst, $src}",
4929 [(set GR64:$dst, (bitconvert FR64:$src))],
4930 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4931 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4932 "movq\t{$src, $dst|$dst, $src}",
4933 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4934 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4937 //===---------------------------------------------------------------------===//
4938 // Move Scalar Single to Double Int
4940 let isCodeGenOnly = 1 in {
4941 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4942 "movd\t{$src, $dst|$dst, $src}",
4943 [(set GR32:$dst, (bitconvert FR32:$src))],
4944 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4945 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4946 "movd\t{$src, $dst|$dst, $src}",
4947 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4948 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4949 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4950 "movd\t{$src, $dst|$dst, $src}",
4951 [(set GR32:$dst, (bitconvert FR32:$src))],
4952 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4953 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4954 "movd\t{$src, $dst|$dst, $src}",
4955 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4956 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4959 //===---------------------------------------------------------------------===//
4960 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4962 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4963 let AddedComplexity = 15 in {
4964 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4965 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4966 [(set VR128:$dst, (v2i64 (X86vzmovl
4967 (v2i64 (scalar_to_vector GR64:$src)))))],
4970 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4971 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4972 [(set VR128:$dst, (v2i64 (X86vzmovl
4973 (v2i64 (scalar_to_vector GR64:$src)))))],
4976 } // isCodeGenOnly, SchedRW
4978 let Predicates = [UseAVX] in {
4979 let AddedComplexity = 15 in
4980 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4981 (VMOVDI2PDIrr GR32:$src)>;
4983 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4984 let AddedComplexity = 20 in {
4985 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4986 (VMOVDI2PDIrm addr:$src)>;
4987 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4988 (VMOVDI2PDIrm addr:$src)>;
4989 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4990 (VMOVDI2PDIrm addr:$src)>;
4992 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4993 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4994 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4995 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4996 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4997 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4998 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5001 let Predicates = [UseSSE2] in {
5002 let AddedComplexity = 15 in
5003 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5004 (MOVDI2PDIrr GR32:$src)>;
5006 let AddedComplexity = 20 in {
5007 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5008 (MOVDI2PDIrm addr:$src)>;
5009 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5010 (MOVDI2PDIrm addr:$src)>;
5011 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5012 (MOVDI2PDIrm addr:$src)>;
5016 // These are the correct encodings of the instructions so that we know how to
5017 // read correct assembly, even though we continue to emit the wrong ones for
5018 // compatibility with Darwin's buggy assembler.
5019 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5020 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5021 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5022 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5023 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5024 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5025 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5026 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5027 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5029 //===---------------------------------------------------------------------===//
5030 // SSE2 - Move Quadword
5031 //===---------------------------------------------------------------------===//
5033 //===---------------------------------------------------------------------===//
5034 // Move Quadword Int to Packed Quadword Int
5037 let SchedRW = [WriteLoad] in {
5038 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5039 "vmovq\t{$src, $dst|$dst, $src}",
5041 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5042 VEX, Requires<[UseAVX]>;
5043 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5044 "movq\t{$src, $dst|$dst, $src}",
5046 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5048 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5051 //===---------------------------------------------------------------------===//
5052 // Move Packed Quadword Int to Quadword Int
5054 let SchedRW = [WriteStore] in {
5055 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5056 "movq\t{$src, $dst|$dst, $src}",
5057 [(store (i64 (vector_extract (v2i64 VR128:$src),
5058 (iPTR 0))), addr:$dst)],
5059 IIC_SSE_MOVDQ>, VEX;
5060 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5061 "movq\t{$src, $dst|$dst, $src}",
5062 [(store (i64 (vector_extract (v2i64 VR128:$src),
5063 (iPTR 0))), addr:$dst)],
5067 // For disassembler only
5068 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5069 SchedRW = [WriteVecLogic] in {
5070 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5071 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5072 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5073 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5076 //===---------------------------------------------------------------------===//
5077 // Store / copy lower 64-bits of a XMM register.
5079 let Predicates = [UseAVX] in
5080 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5081 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5082 let Predicates = [UseSSE2] in
5083 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5084 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5086 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5087 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5088 "vmovq\t{$src, $dst|$dst, $src}",
5090 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5091 (loadi64 addr:$src))))))],
5093 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5095 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5096 "movq\t{$src, $dst|$dst, $src}",
5098 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5099 (loadi64 addr:$src))))))],
5101 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5104 let Predicates = [UseAVX], AddedComplexity = 20 in {
5105 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5106 (VMOVZQI2PQIrm addr:$src)>;
5107 def : Pat<(v2i64 (X86vzload addr:$src)),
5108 (VMOVZQI2PQIrm addr:$src)>;
5111 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5112 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5113 (MOVZQI2PQIrm addr:$src)>;
5114 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5117 let Predicates = [HasAVX] in {
5118 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5119 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5120 def : Pat<(v4i64 (X86vzload addr:$src)),
5121 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5124 //===---------------------------------------------------------------------===//
5125 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5126 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5128 let SchedRW = [WriteVecLogic] in {
5129 let AddedComplexity = 15 in
5130 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5131 "vmovq\t{$src, $dst|$dst, $src}",
5132 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5134 XS, VEX, Requires<[UseAVX]>;
5135 let AddedComplexity = 15 in
5136 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5137 "movq\t{$src, $dst|$dst, $src}",
5138 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5140 XS, Requires<[UseSSE2]>;
5143 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5144 let AddedComplexity = 20 in
5145 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5146 "vmovq\t{$src, $dst|$dst, $src}",
5147 [(set VR128:$dst, (v2i64 (X86vzmovl
5148 (loadv2i64 addr:$src))))],
5150 XS, VEX, Requires<[UseAVX]>;
5151 let AddedComplexity = 20 in {
5152 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5153 "movq\t{$src, $dst|$dst, $src}",
5154 [(set VR128:$dst, (v2i64 (X86vzmovl
5155 (loadv2i64 addr:$src))))],
5157 XS, Requires<[UseSSE2]>;
5159 } // isCodeGenOnly, SchedRW
5161 let AddedComplexity = 20 in {
5162 let Predicates = [UseAVX] in {
5163 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5164 (VMOVZPQILo2PQIrr VR128:$src)>;
5166 let Predicates = [UseSSE2] in {
5167 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5168 (MOVZPQILo2PQIrr VR128:$src)>;
5172 //===---------------------------------------------------------------------===//
5173 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5174 //===---------------------------------------------------------------------===//
5175 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5176 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5177 X86MemOperand x86memop> {
5178 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5179 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5180 [(set RC:$dst, (vt (OpNode RC:$src)))],
5181 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5182 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5184 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5185 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5188 let Predicates = [HasAVX] in {
5189 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5190 v4f32, VR128, loadv4f32, f128mem>, VEX;
5191 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5192 v4f32, VR128, loadv4f32, f128mem>, VEX;
5193 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5194 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5195 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5196 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5198 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5199 memopv4f32, f128mem>;
5200 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5201 memopv4f32, f128mem>;
5203 let Predicates = [HasAVX] in {
5204 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5205 (VMOVSHDUPrr VR128:$src)>;
5206 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5207 (VMOVSHDUPrm addr:$src)>;
5208 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5209 (VMOVSLDUPrr VR128:$src)>;
5210 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5211 (VMOVSLDUPrm addr:$src)>;
5212 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5213 (VMOVSHDUPYrr VR256:$src)>;
5214 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5215 (VMOVSHDUPYrm addr:$src)>;
5216 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5217 (VMOVSLDUPYrr VR256:$src)>;
5218 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5219 (VMOVSLDUPYrm addr:$src)>;
5222 let Predicates = [UseSSE3] in {
5223 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5224 (MOVSHDUPrr VR128:$src)>;
5225 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5226 (MOVSHDUPrm addr:$src)>;
5227 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5228 (MOVSLDUPrr VR128:$src)>;
5229 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5230 (MOVSLDUPrm addr:$src)>;
5233 //===---------------------------------------------------------------------===//
5234 // SSE3 - Replicate Double FP - MOVDDUP
5235 //===---------------------------------------------------------------------===//
5237 multiclass sse3_replicate_dfp<string OpcodeStr> {
5238 let neverHasSideEffects = 1 in
5239 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5241 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5242 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5246 (scalar_to_vector (loadf64 addr:$src)))))],
5247 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5250 // FIXME: Merge with above classe when there're patterns for the ymm version
5251 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5252 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5253 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5254 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5255 Sched<[WriteFShuffle]>;
5256 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5257 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5260 (scalar_to_vector (loadf64 addr:$src)))))]>,
5264 let Predicates = [HasAVX] in {
5265 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5266 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5269 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5271 let Predicates = [HasAVX] in {
5272 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5273 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5274 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5275 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5276 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5277 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5278 def : Pat<(X86Movddup (bc_v2f64
5279 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5280 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5283 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5284 (VMOVDDUPYrm addr:$src)>;
5285 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5286 (VMOVDDUPYrm addr:$src)>;
5287 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5288 (VMOVDDUPYrm addr:$src)>;
5289 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5290 (VMOVDDUPYrr VR256:$src)>;
5293 let Predicates = [UseSSE3] in {
5294 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5295 (MOVDDUPrm addr:$src)>;
5296 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5297 (MOVDDUPrm addr:$src)>;
5298 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5299 (MOVDDUPrm addr:$src)>;
5300 def : Pat<(X86Movddup (bc_v2f64
5301 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5302 (MOVDDUPrm addr:$src)>;
5305 //===---------------------------------------------------------------------===//
5306 // SSE3 - Move Unaligned Integer
5307 //===---------------------------------------------------------------------===//
5309 let SchedRW = [WriteLoad] in {
5310 let Predicates = [HasAVX] in {
5311 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5312 "vlddqu\t{$src, $dst|$dst, $src}",
5313 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5314 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5315 "vlddqu\t{$src, $dst|$dst, $src}",
5316 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5319 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5320 "lddqu\t{$src, $dst|$dst, $src}",
5321 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5325 //===---------------------------------------------------------------------===//
5326 // SSE3 - Arithmetic
5327 //===---------------------------------------------------------------------===//
5329 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5330 X86MemOperand x86memop, OpndItins itins,
5332 def rr : I<0xD0, MRMSrcReg,
5333 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5337 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5338 Sched<[itins.Sched]>;
5339 def rm : I<0xD0, MRMSrcMem,
5340 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5342 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5344 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5345 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5348 let Predicates = [HasAVX] in {
5349 let ExeDomain = SSEPackedSingle in {
5350 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5351 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5352 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5353 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5355 let ExeDomain = SSEPackedDouble in {
5356 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5357 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5358 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5359 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5362 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5363 let ExeDomain = SSEPackedSingle in
5364 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5365 f128mem, SSE_ALU_F32P>, XD;
5366 let ExeDomain = SSEPackedDouble in
5367 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5368 f128mem, SSE_ALU_F64P>, PD;
5371 // Patterns used to select 'addsub' instructions.
5372 let Predicates = [HasAVX] in {
5373 // Constant 170 corresponds to the binary mask '10101010'.
5374 // When used as a blend mask, it allows selecting eight elements from two
5375 // input vectors as follow:
5376 // - Even-numbered values in the destination are copied from
5377 // the corresponding elements in the first input vector;
5378 // - Odd-numbered values in the destination are copied from
5379 // the corresponding elements in the second input vector.
5381 def : Pat<(v8f32 (X86Blendi (v8f32 (fsub VR256:$lhs, VR256:$rhs)),
5382 (v8f32 (fadd VR256:$lhs, VR256:$rhs)), (i32 170))),
5383 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5385 // Constant 10 corresponds to the binary mask '1010'.
5386 // In the two pattens below, constant 10 is used as a blend mask to select
5387 // - the 1st and 3rd element from the first input vector (the 'fsub' node);
5388 // - the 2nd and 4th element from the second input vector (the 'fadd' node).
5390 def : Pat<(v4f64 (X86Blendi (v4f64 (fsub VR256:$lhs, VR256:$rhs)),
5391 (v4f64 (fadd VR256:$lhs, VR256:$rhs)), (i32 10))),
5392 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5393 def : Pat<(v4f64 (X86Blendi (v4f64 (fsub VR256:$lhs, VR256:$rhs)),
5394 (v4f64 (fadd VR256:$lhs, VR256:$rhs)), (i32 10))),
5395 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5396 def : Pat<(v4f32 (X86Blendi (v4f32 (fsub VR128:$lhs, VR128:$rhs)),
5397 (v4f32 (fadd VR128:$lhs, VR128:$rhs)), (i32 10))),
5398 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5399 def : Pat<(v2f64 (X86Blendi (v2f64 (fsub VR128:$lhs, VR128:$rhs)),
5400 (v2f64 (fadd VR128:$lhs, VR128:$rhs)), (i32 2))),
5401 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5402 def : Pat<(v2f64 (X86Movsd (v2f64 (fadd VR128:$lhs, VR128:$rhs)),
5403 (v2f64 (fsub VR128:$lhs, VR128:$rhs)))),
5404 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5407 let Predicates = [UseSSE3] in {
5408 // Constant 10 corresponds to the binary mask '1010'.
5409 // In the pattern below, it is used as a blend mask to select:
5410 // - the 1st and 3rd element from the first input vector (the fsub node);
5411 // - the 2nd and 4th element from the second input vector (the fadd node).
5413 def : Pat<(v4f32 (X86Blendi (v4f32 (fsub VR128:$lhs, VR128:$rhs)),
5414 (v4f32 (fadd VR128:$lhs, VR128:$rhs)), (i32 10))),
5415 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5417 def : Pat<(v2f64 (X86Blendi (v2f64 (fsub VR128:$lhs, VR128:$rhs)),
5418 (v2f64 (fadd VR128:$lhs, VR128:$rhs)), (i32 2))),
5419 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5420 def : Pat<(v2f64 (X86Movsd (v2f64 (fadd VR128:$lhs, VR128:$rhs)),
5421 (v2f64 (fsub VR128:$lhs, VR128:$rhs)))),
5422 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5425 //===---------------------------------------------------------------------===//
5426 // SSE3 Instructions
5427 //===---------------------------------------------------------------------===//
5430 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5431 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5432 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5434 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5435 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5436 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5439 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5441 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5443 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5444 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5446 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5447 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5448 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5450 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5451 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5452 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5455 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5457 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5458 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5459 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5460 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5463 let Predicates = [HasAVX] in {
5464 let ExeDomain = SSEPackedSingle in {
5465 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5466 X86fhadd, 0>, VEX_4V;
5467 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5468 X86fhsub, 0>, VEX_4V;
5469 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5470 X86fhadd, 0>, VEX_4V, VEX_L;
5471 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5472 X86fhsub, 0>, VEX_4V, VEX_L;
5474 let ExeDomain = SSEPackedDouble in {
5475 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5476 X86fhadd, 0>, VEX_4V;
5477 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5478 X86fhsub, 0>, VEX_4V;
5479 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5480 X86fhadd, 0>, VEX_4V, VEX_L;
5481 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5482 X86fhsub, 0>, VEX_4V, VEX_L;
5486 let Constraints = "$src1 = $dst" in {
5487 let ExeDomain = SSEPackedSingle in {
5488 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5489 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5491 let ExeDomain = SSEPackedDouble in {
5492 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5493 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5497 //===---------------------------------------------------------------------===//
5498 // SSSE3 - Packed Absolute Instructions
5499 //===---------------------------------------------------------------------===//
5502 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5503 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5504 Intrinsic IntId128> {
5505 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5507 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5508 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5509 Sched<[WriteVecALU]>;
5511 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5516 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5517 Sched<[WriteVecALULd]>;
5520 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5521 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5522 Intrinsic IntId256> {
5523 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5525 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5526 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5527 Sched<[WriteVecALU]>;
5529 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5531 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5534 (bitconvert (memopv4i64 addr:$src))))]>,
5535 Sched<[WriteVecALULd]>;
5538 // Helper fragments to match sext vXi1 to vXiY.
5539 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5541 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5542 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5543 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5545 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5546 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5548 let Predicates = [HasAVX] in {
5549 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5550 int_x86_ssse3_pabs_b_128>, VEX;
5551 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5552 int_x86_ssse3_pabs_w_128>, VEX;
5553 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5554 int_x86_ssse3_pabs_d_128>, VEX;
5557 (bc_v2i64 (v16i1sextv16i8)),
5558 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5559 (VPABSBrr128 VR128:$src)>;
5561 (bc_v2i64 (v8i1sextv8i16)),
5562 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5563 (VPABSWrr128 VR128:$src)>;
5565 (bc_v2i64 (v4i1sextv4i32)),
5566 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5567 (VPABSDrr128 VR128:$src)>;
5570 let Predicates = [HasAVX2] in {
5571 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5572 int_x86_avx2_pabs_b>, VEX, VEX_L;
5573 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5574 int_x86_avx2_pabs_w>, VEX, VEX_L;
5575 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5576 int_x86_avx2_pabs_d>, VEX, VEX_L;
5579 (bc_v4i64 (v32i1sextv32i8)),
5580 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5581 (VPABSBrr256 VR256:$src)>;
5583 (bc_v4i64 (v16i1sextv16i16)),
5584 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5585 (VPABSWrr256 VR256:$src)>;
5587 (bc_v4i64 (v8i1sextv8i32)),
5588 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5589 (VPABSDrr256 VR256:$src)>;
5592 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5593 int_x86_ssse3_pabs_b_128>;
5594 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5595 int_x86_ssse3_pabs_w_128>;
5596 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5597 int_x86_ssse3_pabs_d_128>;
5599 let Predicates = [HasSSSE3] in {
5601 (bc_v2i64 (v16i1sextv16i8)),
5602 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5603 (PABSBrr128 VR128:$src)>;
5605 (bc_v2i64 (v8i1sextv8i16)),
5606 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5607 (PABSWrr128 VR128:$src)>;
5609 (bc_v2i64 (v4i1sextv4i32)),
5610 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5611 (PABSDrr128 VR128:$src)>;
5614 //===---------------------------------------------------------------------===//
5615 // SSSE3 - Packed Binary Operator Instructions
5616 //===---------------------------------------------------------------------===//
5618 let Sched = WriteVecALU in {
5619 def SSE_PHADDSUBD : OpndItins<
5620 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5622 def SSE_PHADDSUBSW : OpndItins<
5623 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5625 def SSE_PHADDSUBW : OpndItins<
5626 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5629 let Sched = WriteShuffle in
5630 def SSE_PSHUFB : OpndItins<
5631 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5633 let Sched = WriteVecALU in
5634 def SSE_PSIGN : OpndItins<
5635 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5637 let Sched = WriteVecIMul in
5638 def SSE_PMULHRSW : OpndItins<
5639 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5642 /// SS3I_binop_rm - Simple SSSE3 bin op
5643 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5644 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5645 X86MemOperand x86memop, OpndItins itins,
5647 let isCommutable = 1 in
5648 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5649 (ins RC:$src1, RC:$src2),
5651 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5652 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5653 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5654 Sched<[itins.Sched]>;
5655 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5656 (ins RC:$src1, x86memop:$src2),
5658 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5659 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5661 (OpVT (OpNode RC:$src1,
5662 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5663 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5666 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5667 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5668 Intrinsic IntId128, OpndItins itins,
5670 let isCommutable = 1 in
5671 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5672 (ins VR128:$src1, VR128:$src2),
5674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5676 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5677 Sched<[itins.Sched]>;
5678 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5679 (ins VR128:$src1, i128mem:$src2),
5681 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5684 (IntId128 VR128:$src1,
5685 (bitconvert (memopv2i64 addr:$src2))))]>,
5686 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5689 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5691 X86FoldableSchedWrite Sched> {
5692 let isCommutable = 1 in
5693 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5694 (ins VR256:$src1, VR256:$src2),
5695 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5696 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5698 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5699 (ins VR256:$src1, i256mem:$src2),
5700 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5702 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5703 Sched<[Sched.Folded, ReadAfterLd]>;
5706 let ImmT = NoImm, Predicates = [HasAVX] in {
5707 let isCommutable = 0 in {
5708 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5710 SSE_PHADDSUBW, 0>, VEX_4V;
5711 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5713 SSE_PHADDSUBD, 0>, VEX_4V;
5714 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5716 SSE_PHADDSUBW, 0>, VEX_4V;
5717 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5719 SSE_PHADDSUBD, 0>, VEX_4V;
5720 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5722 SSE_PSIGN, 0>, VEX_4V;
5723 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5725 SSE_PSIGN, 0>, VEX_4V;
5726 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5728 SSE_PSIGN, 0>, VEX_4V;
5729 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5731 SSE_PSHUFB, 0>, VEX_4V;
5732 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5733 int_x86_ssse3_phadd_sw_128,
5734 SSE_PHADDSUBSW, 0>, VEX_4V;
5735 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5736 int_x86_ssse3_phsub_sw_128,
5737 SSE_PHADDSUBSW, 0>, VEX_4V;
5738 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5739 int_x86_ssse3_pmadd_ub_sw_128,
5740 SSE_PMADD, 0>, VEX_4V;
5742 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5743 int_x86_ssse3_pmul_hr_sw_128,
5744 SSE_PMULHRSW, 0>, VEX_4V;
5747 let ImmT = NoImm, Predicates = [HasAVX2] in {
5748 let isCommutable = 0 in {
5749 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5751 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5752 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5754 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5755 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5757 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5758 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5760 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5761 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5763 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5764 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5766 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5767 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5769 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5770 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5772 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5773 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5774 int_x86_avx2_phadd_sw,
5775 WriteVecALU>, VEX_4V, VEX_L;
5776 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5777 int_x86_avx2_phsub_sw,
5778 WriteVecALU>, VEX_4V, VEX_L;
5779 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5780 int_x86_avx2_pmadd_ub_sw,
5781 WriteVecIMul>, VEX_4V, VEX_L;
5783 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5784 int_x86_avx2_pmul_hr_sw,
5785 WriteVecIMul>, VEX_4V, VEX_L;
5788 // None of these have i8 immediate fields.
5789 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5790 let isCommutable = 0 in {
5791 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5792 memopv2i64, i128mem, SSE_PHADDSUBW>;
5793 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5794 memopv2i64, i128mem, SSE_PHADDSUBD>;
5795 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5796 memopv2i64, i128mem, SSE_PHADDSUBW>;
5797 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5798 memopv2i64, i128mem, SSE_PHADDSUBD>;
5799 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5800 memopv2i64, i128mem, SSE_PSIGN>;
5801 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5802 memopv2i64, i128mem, SSE_PSIGN>;
5803 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5804 memopv2i64, i128mem, SSE_PSIGN>;
5805 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5806 memopv2i64, i128mem, SSE_PSHUFB>;
5807 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5808 int_x86_ssse3_phadd_sw_128,
5810 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5811 int_x86_ssse3_phsub_sw_128,
5813 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5814 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5816 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5817 int_x86_ssse3_pmul_hr_sw_128,
5821 //===---------------------------------------------------------------------===//
5822 // SSSE3 - Packed Align Instruction Patterns
5823 //===---------------------------------------------------------------------===//
5825 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5826 let neverHasSideEffects = 1 in {
5827 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5828 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5830 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5832 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5833 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5835 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5836 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5838 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5840 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5841 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5845 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5846 let neverHasSideEffects = 1 in {
5847 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5848 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5850 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5851 []>, Sched<[WriteShuffle]>;
5853 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5854 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5856 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5857 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5861 let Predicates = [HasAVX] in
5862 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5863 let Predicates = [HasAVX2] in
5864 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5865 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5866 defm PALIGN : ssse3_palignr<"palignr">;
5868 let Predicates = [HasAVX2] in {
5869 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5870 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5871 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5872 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5873 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5874 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5875 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5876 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5879 let Predicates = [HasAVX] in {
5880 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5881 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5882 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5883 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5884 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5885 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5886 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5887 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5890 let Predicates = [UseSSSE3] in {
5891 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5892 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5893 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5894 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5895 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5896 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5897 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5898 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5901 //===---------------------------------------------------------------------===//
5902 // SSSE3 - Thread synchronization
5903 //===---------------------------------------------------------------------===//
5905 let SchedRW = [WriteSystem] in {
5906 let usesCustomInserter = 1 in {
5907 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5908 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5909 Requires<[HasSSE3]>;
5912 let Uses = [EAX, ECX, EDX] in
5913 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5914 TB, Requires<[HasSSE3]>;
5915 let Uses = [ECX, EAX] in
5916 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5917 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5918 TB, Requires<[HasSSE3]>;
5921 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5922 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5924 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5925 Requires<[Not64BitMode]>;
5926 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5927 Requires<[In64BitMode]>;
5929 //===----------------------------------------------------------------------===//
5930 // SSE4.1 - Packed Move with Sign/Zero Extend
5931 //===----------------------------------------------------------------------===//
5933 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5934 OpndItins itins = DEFAULT_ITINS> {
5935 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5936 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5937 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
5938 Sched<[itins.Sched]>;
5940 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5941 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5943 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5944 itins.rm>, Sched<[itins.Sched.Folded]>;
5947 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5948 Intrinsic IntId, X86FoldableSchedWrite Sched> {
5949 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5950 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5951 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
5953 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5954 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5955 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5956 Sched<[Sched.Folded]>;
5959 let Predicates = [HasAVX] in {
5960 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5961 int_x86_sse41_pmovsxbw,
5962 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5963 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5964 int_x86_sse41_pmovsxwd,
5965 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5966 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5967 int_x86_sse41_pmovsxdq,
5968 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5969 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5970 int_x86_sse41_pmovzxbw,
5971 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5972 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5973 int_x86_sse41_pmovzxwd,
5974 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5975 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5976 int_x86_sse41_pmovzxdq,
5977 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5980 let Predicates = [HasAVX2] in {
5981 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5982 int_x86_avx2_pmovsxbw,
5983 WriteShuffle>, VEX, VEX_L;
5984 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5985 int_x86_avx2_pmovsxwd,
5986 WriteShuffle>, VEX, VEX_L;
5987 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5988 int_x86_avx2_pmovsxdq,
5989 WriteShuffle>, VEX, VEX_L;
5990 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5991 int_x86_avx2_pmovzxbw,
5992 WriteShuffle>, VEX, VEX_L;
5993 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5994 int_x86_avx2_pmovzxwd,
5995 WriteShuffle>, VEX, VEX_L;
5996 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5997 int_x86_avx2_pmovzxdq,
5998 WriteShuffle>, VEX, VEX_L;
6001 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw,
6002 SSE_INTALU_ITINS_SHUFF_P>;
6003 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd,
6004 SSE_INTALU_ITINS_SHUFF_P>;
6005 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq,
6006 SSE_INTALU_ITINS_SHUFF_P>;
6007 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw,
6008 SSE_INTALU_ITINS_SHUFF_P>;
6009 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd,
6010 SSE_INTALU_ITINS_SHUFF_P>;
6011 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq,
6012 SSE_INTALU_ITINS_SHUFF_P>;
6014 let Predicates = [HasAVX] in {
6015 // Common patterns involving scalar load.
6016 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6017 (VPMOVSXBWrm addr:$src)>;
6018 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6019 (VPMOVSXBWrm addr:$src)>;
6020 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6021 (VPMOVSXBWrm addr:$src)>;
6023 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6024 (VPMOVSXWDrm addr:$src)>;
6025 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6026 (VPMOVSXWDrm addr:$src)>;
6027 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6028 (VPMOVSXWDrm addr:$src)>;
6030 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6031 (VPMOVSXDQrm addr:$src)>;
6032 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6033 (VPMOVSXDQrm addr:$src)>;
6034 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6035 (VPMOVSXDQrm addr:$src)>;
6037 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6038 (VPMOVZXBWrm addr:$src)>;
6039 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6040 (VPMOVZXBWrm addr:$src)>;
6041 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6042 (VPMOVZXBWrm addr:$src)>;
6044 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6045 (VPMOVZXWDrm addr:$src)>;
6046 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6047 (VPMOVZXWDrm addr:$src)>;
6048 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6049 (VPMOVZXWDrm addr:$src)>;
6051 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6052 (VPMOVZXDQrm addr:$src)>;
6053 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6054 (VPMOVZXDQrm addr:$src)>;
6055 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6056 (VPMOVZXDQrm addr:$src)>;
6059 let Predicates = [UseSSE41] in {
6060 // Common patterns involving scalar load.
6061 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6062 (PMOVSXBWrm addr:$src)>;
6063 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6064 (PMOVSXBWrm addr:$src)>;
6065 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6066 (PMOVSXBWrm addr:$src)>;
6068 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6069 (PMOVSXWDrm addr:$src)>;
6070 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6071 (PMOVSXWDrm addr:$src)>;
6072 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6073 (PMOVSXWDrm addr:$src)>;
6075 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6076 (PMOVSXDQrm addr:$src)>;
6077 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6078 (PMOVSXDQrm addr:$src)>;
6079 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6080 (PMOVSXDQrm addr:$src)>;
6082 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6083 (PMOVZXBWrm addr:$src)>;
6084 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6085 (PMOVZXBWrm addr:$src)>;
6086 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6087 (PMOVZXBWrm addr:$src)>;
6089 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6090 (PMOVZXWDrm addr:$src)>;
6091 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6092 (PMOVZXWDrm addr:$src)>;
6093 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6094 (PMOVZXWDrm addr:$src)>;
6096 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6097 (PMOVZXDQrm addr:$src)>;
6098 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6099 (PMOVZXDQrm addr:$src)>;
6100 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6101 (PMOVZXDQrm addr:$src)>;
6104 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6105 OpndItins itins = DEFAULT_ITINS> {
6106 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6107 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6108 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6109 Sched<[itins.Sched]>;
6111 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
6112 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6114 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
6115 itins.rm>, Sched<[itins.Sched.Folded]>;
6118 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
6119 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6120 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6121 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6122 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6124 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
6125 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6127 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
6128 Sched<[Sched.Folded]>;
6131 let Predicates = [HasAVX] in {
6132 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd,
6133 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6134 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq,
6135 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6136 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd,
6137 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6138 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq,
6139 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6142 let Predicates = [HasAVX2] in {
6143 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
6144 int_x86_avx2_pmovsxbd, WriteShuffle>,
6146 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
6147 int_x86_avx2_pmovsxwq, WriteShuffle>,
6149 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
6150 int_x86_avx2_pmovzxbd, WriteShuffle>,
6152 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
6153 int_x86_avx2_pmovzxwq, WriteShuffle>,
6157 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
6158 SSE_INTALU_ITINS_SHUFF_P>;
6159 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
6160 SSE_INTALU_ITINS_SHUFF_P>;
6161 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
6162 SSE_INTALU_ITINS_SHUFF_P>;
6163 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
6164 SSE_INTALU_ITINS_SHUFF_P>;
6166 let Predicates = [HasAVX] in {
6167 // Common patterns involving scalar load
6168 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6169 (VPMOVSXBDrm addr:$src)>;
6170 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6171 (VPMOVSXWQrm addr:$src)>;
6173 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6174 (VPMOVZXBDrm addr:$src)>;
6175 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6176 (VPMOVZXWQrm addr:$src)>;
6179 let Predicates = [UseSSE41] in {
6180 // Common patterns involving scalar load
6181 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6182 (PMOVSXBDrm addr:$src)>;
6183 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6184 (PMOVSXWQrm addr:$src)>;
6186 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6187 (PMOVZXBDrm addr:$src)>;
6188 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6189 (PMOVZXWQrm addr:$src)>;
6192 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6193 X86FoldableSchedWrite Sched> {
6194 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6195 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6196 [(set VR128:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6198 // Expecting a i16 load any extended to i32 value.
6199 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
6200 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6201 [(set VR128:$dst, (IntId (bitconvert
6202 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
6203 Sched<[Sched.Folded]>;
6206 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
6207 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6208 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6209 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6210 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6212 // Expecting a i16 load any extended to i32 value.
6213 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
6214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6215 [(set VR256:$dst, (IntId (bitconvert
6216 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
6217 Sched<[Sched.Folded]>;
6220 let Predicates = [HasAVX] in {
6221 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq,
6223 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq,
6226 let Predicates = [HasAVX2] in {
6227 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq", int_x86_avx2_pmovsxbq,
6228 WriteShuffle>, VEX, VEX_L;
6229 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq", int_x86_avx2_pmovzxbq,
6230 WriteShuffle>, VEX, VEX_L;
6232 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
6234 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
6237 let Predicates = [HasAVX2] in {
6238 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
6239 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
6240 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6242 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6243 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6245 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6247 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6248 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6249 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6250 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6251 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6252 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6254 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6255 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6256 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6257 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6259 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6260 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6262 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6263 (VPMOVSXWDYrm addr:$src)>;
6264 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6265 (VPMOVSXDQYrm addr:$src)>;
6267 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6268 (scalar_to_vector (loadi64 addr:$src))))))),
6269 (VPMOVSXBDYrm addr:$src)>;
6270 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6271 (scalar_to_vector (loadf64 addr:$src))))))),
6272 (VPMOVSXBDYrm addr:$src)>;
6274 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6275 (scalar_to_vector (loadi64 addr:$src))))))),
6276 (VPMOVSXWQYrm addr:$src)>;
6277 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6278 (scalar_to_vector (loadf64 addr:$src))))))),
6279 (VPMOVSXWQYrm addr:$src)>;
6281 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6282 (scalar_to_vector (loadi32 addr:$src))))))),
6283 (VPMOVSXBQYrm addr:$src)>;
6286 let Predicates = [HasAVX] in {
6287 // Common patterns involving scalar load
6288 def : Pat<(int_x86_sse41_pmovsxbq
6289 (bitconvert (v4i32 (X86vzmovl
6290 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6291 (VPMOVSXBQrm addr:$src)>;
6293 def : Pat<(int_x86_sse41_pmovzxbq
6294 (bitconvert (v4i32 (X86vzmovl
6295 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6296 (VPMOVZXBQrm addr:$src)>;
6299 let Predicates = [UseSSE41] in {
6300 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6301 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6302 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6304 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6305 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6307 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6309 // Common patterns involving scalar load
6310 def : Pat<(int_x86_sse41_pmovsxbq
6311 (bitconvert (v4i32 (X86vzmovl
6312 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6313 (PMOVSXBQrm addr:$src)>;
6315 def : Pat<(int_x86_sse41_pmovzxbq
6316 (bitconvert (v4i32 (X86vzmovl
6317 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6318 (PMOVZXBQrm addr:$src)>;
6320 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6321 (scalar_to_vector (loadi64 addr:$src))))))),
6322 (PMOVSXWDrm addr:$src)>;
6323 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6324 (scalar_to_vector (loadf64 addr:$src))))))),
6325 (PMOVSXWDrm addr:$src)>;
6326 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6327 (scalar_to_vector (loadi32 addr:$src))))))),
6328 (PMOVSXBDrm addr:$src)>;
6329 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6330 (scalar_to_vector (loadi32 addr:$src))))))),
6331 (PMOVSXWQrm addr:$src)>;
6332 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6333 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6334 (PMOVSXBQrm addr:$src)>;
6335 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6336 (scalar_to_vector (loadi64 addr:$src))))))),
6337 (PMOVSXDQrm addr:$src)>;
6338 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6339 (scalar_to_vector (loadf64 addr:$src))))))),
6340 (PMOVSXDQrm addr:$src)>;
6341 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6342 (scalar_to_vector (loadi64 addr:$src))))))),
6343 (PMOVSXBWrm addr:$src)>;
6344 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6345 (scalar_to_vector (loadf64 addr:$src))))))),
6346 (PMOVSXBWrm addr:$src)>;
6349 let Predicates = [HasAVX2] in {
6350 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6351 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6352 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6354 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6355 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6357 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6359 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6360 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6361 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6362 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6363 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6364 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6366 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6367 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6368 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6369 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6371 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6372 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6375 let Predicates = [HasAVX] in {
6376 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6377 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6378 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6380 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6381 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6383 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6385 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6386 (VPMOVZXBWrm addr:$src)>;
6387 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6388 (VPMOVZXBWrm addr:$src)>;
6389 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6390 (VPMOVZXBDrm addr:$src)>;
6391 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6392 (VPMOVZXBQrm addr:$src)>;
6394 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6395 (VPMOVZXWDrm addr:$src)>;
6396 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6397 (VPMOVZXWDrm addr:$src)>;
6398 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6399 (VPMOVZXWQrm addr:$src)>;
6401 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6402 (VPMOVZXDQrm addr:$src)>;
6403 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6404 (VPMOVZXDQrm addr:$src)>;
6405 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6406 (VPMOVZXDQrm addr:$src)>;
6408 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6409 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6410 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6412 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6413 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6415 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6417 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6418 (scalar_to_vector (loadi64 addr:$src))))))),
6419 (VPMOVSXWDrm addr:$src)>;
6420 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6421 (scalar_to_vector (loadi64 addr:$src))))))),
6422 (VPMOVSXDQrm addr:$src)>;
6423 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6424 (scalar_to_vector (loadf64 addr:$src))))))),
6425 (VPMOVSXWDrm addr:$src)>;
6426 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6427 (scalar_to_vector (loadf64 addr:$src))))))),
6428 (VPMOVSXDQrm addr:$src)>;
6429 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6430 (scalar_to_vector (loadi64 addr:$src))))))),
6431 (VPMOVSXBWrm addr:$src)>;
6432 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6433 (scalar_to_vector (loadf64 addr:$src))))))),
6434 (VPMOVSXBWrm addr:$src)>;
6436 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6437 (scalar_to_vector (loadi32 addr:$src))))))),
6438 (VPMOVSXBDrm addr:$src)>;
6439 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6440 (scalar_to_vector (loadi32 addr:$src))))))),
6441 (VPMOVSXWQrm addr:$src)>;
6442 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6443 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6444 (VPMOVSXBQrm addr:$src)>;
6447 let Predicates = [UseSSE41] in {
6448 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6449 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6450 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6452 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6453 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6455 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6457 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6458 (PMOVZXBWrm addr:$src)>;
6459 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6460 (PMOVZXBWrm addr:$src)>;
6461 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6462 (PMOVZXBDrm addr:$src)>;
6463 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6464 (PMOVZXBQrm addr:$src)>;
6466 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6467 (PMOVZXWDrm addr:$src)>;
6468 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6469 (PMOVZXWDrm addr:$src)>;
6470 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6471 (PMOVZXWQrm addr:$src)>;
6473 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6474 (PMOVZXDQrm addr:$src)>;
6475 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6476 (PMOVZXDQrm addr:$src)>;
6477 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6478 (PMOVZXDQrm addr:$src)>;
6481 //===----------------------------------------------------------------------===//
6482 // SSE4.1 - Extract Instructions
6483 //===----------------------------------------------------------------------===//
6485 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6486 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6487 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6488 (ins VR128:$src1, i32i8imm:$src2),
6489 !strconcat(OpcodeStr,
6490 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6491 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6493 Sched<[WriteShuffle]>;
6494 let neverHasSideEffects = 1, mayStore = 1,
6495 SchedRW = [WriteShuffleLd, WriteRMW] in
6496 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6497 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6498 !strconcat(OpcodeStr,
6499 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6500 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6501 imm:$src2)))), addr:$dst)]>;
6504 let Predicates = [HasAVX] in
6505 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6507 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6510 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6511 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6512 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6513 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6514 (ins VR128:$src1, i32i8imm:$src2),
6515 !strconcat(OpcodeStr,
6516 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6517 []>, Sched<[WriteShuffle]>;
6519 let neverHasSideEffects = 1, mayStore = 1,
6520 SchedRW = [WriteShuffleLd, WriteRMW] in
6521 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6522 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6523 !strconcat(OpcodeStr,
6524 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6525 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6526 imm:$src2)))), addr:$dst)]>;
6529 let Predicates = [HasAVX] in
6530 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6532 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6535 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6536 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6537 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6538 (ins VR128:$src1, i32i8imm:$src2),
6539 !strconcat(OpcodeStr,
6540 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6542 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6543 Sched<[WriteShuffle]>;
6544 let SchedRW = [WriteShuffleLd, WriteRMW] in
6545 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6546 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6547 !strconcat(OpcodeStr,
6548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6549 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6553 let Predicates = [HasAVX] in
6554 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6556 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6558 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6559 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6560 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6561 (ins VR128:$src1, i32i8imm:$src2),
6562 !strconcat(OpcodeStr,
6563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6565 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6566 Sched<[WriteShuffle]>, REX_W;
6567 let SchedRW = [WriteShuffleLd, WriteRMW] in
6568 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6569 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6570 !strconcat(OpcodeStr,
6571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6572 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6573 addr:$dst)]>, REX_W;
6576 let Predicates = [HasAVX] in
6577 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6579 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6581 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6583 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6584 OpndItins itins = DEFAULT_ITINS> {
6585 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6586 (ins VR128:$src1, i32i8imm:$src2),
6587 !strconcat(OpcodeStr,
6588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6589 [(set GR32orGR64:$dst,
6590 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6591 itins.rr>, Sched<[WriteFBlend]>;
6592 let SchedRW = [WriteFBlendLd, WriteRMW] in
6593 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6594 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6595 !strconcat(OpcodeStr,
6596 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6597 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6598 addr:$dst)], itins.rm>;
6601 let ExeDomain = SSEPackedSingle in {
6602 let Predicates = [UseAVX] in
6603 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6604 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6607 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6608 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6611 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6613 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6616 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6617 Requires<[UseSSE41]>;
6619 //===----------------------------------------------------------------------===//
6620 // SSE4.1 - Insert Instructions
6621 //===----------------------------------------------------------------------===//
6623 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6624 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6625 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6627 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6629 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6631 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6632 Sched<[WriteShuffle]>;
6633 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6634 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6636 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6638 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6640 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6641 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6644 let Predicates = [HasAVX] in
6645 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6646 let Constraints = "$src1 = $dst" in
6647 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6649 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6650 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6651 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6653 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6655 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6657 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6658 Sched<[WriteShuffle]>;
6659 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6660 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6662 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6664 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6666 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6667 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6670 let Predicates = [HasAVX] in
6671 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6672 let Constraints = "$src1 = $dst" in
6673 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6675 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6676 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6677 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6679 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6681 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6683 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6684 Sched<[WriteShuffle]>;
6685 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6686 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6688 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6690 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6692 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6693 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6696 let Predicates = [HasAVX] in
6697 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6698 let Constraints = "$src1 = $dst" in
6699 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6701 // insertps has a few different modes, there's the first two here below which
6702 // are optimized inserts that won't zero arbitrary elements in the destination
6703 // vector. The next one matches the intrinsic and could zero arbitrary elements
6704 // in the target vector.
6705 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6706 OpndItins itins = DEFAULT_ITINS> {
6707 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6708 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6710 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6712 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6714 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6715 Sched<[WriteFShuffle]>;
6716 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6717 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6719 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6721 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6723 (X86insertps VR128:$src1,
6724 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6725 imm:$src3))], itins.rm>,
6726 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6729 let ExeDomain = SSEPackedSingle in {
6730 let Predicates = [UseAVX] in
6731 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6732 let Constraints = "$src1 = $dst" in
6733 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6736 let Predicates = [UseSSE41] in {
6737 // If we're inserting an element from a load or a null pshuf of a load,
6738 // fold the load into the insertps instruction.
6739 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6740 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6742 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6743 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6744 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6745 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6748 let Predicates = [UseAVX] in {
6749 // If we're inserting an element from a vbroadcast of a load, fold the
6750 // load into the X86insertps instruction.
6751 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6752 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6753 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6754 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6755 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6756 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6759 //===----------------------------------------------------------------------===//
6760 // SSE4.1 - Round Instructions
6761 //===----------------------------------------------------------------------===//
6763 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6764 X86MemOperand x86memop, RegisterClass RC,
6765 PatFrag mem_frag32, PatFrag mem_frag64,
6766 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6767 let ExeDomain = SSEPackedSingle in {
6768 // Intrinsic operation, reg.
6769 // Vector intrinsic operation, reg
6770 def PSr : SS4AIi8<opcps, MRMSrcReg,
6771 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6772 !strconcat(OpcodeStr,
6773 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6774 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6775 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6777 // Vector intrinsic operation, mem
6778 def PSm : SS4AIi8<opcps, MRMSrcMem,
6779 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6780 !strconcat(OpcodeStr,
6781 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6783 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6784 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6785 } // ExeDomain = SSEPackedSingle
6787 let ExeDomain = SSEPackedDouble in {
6788 // Vector intrinsic operation, reg
6789 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6790 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6791 !strconcat(OpcodeStr,
6792 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6793 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6794 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6796 // Vector intrinsic operation, mem
6797 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6798 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6799 !strconcat(OpcodeStr,
6800 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6802 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6803 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6804 } // ExeDomain = SSEPackedDouble
6807 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6810 Intrinsic F64Int, bit Is2Addr = 1> {
6811 let ExeDomain = GenericDomain in {
6813 let hasSideEffects = 0 in
6814 def SSr : SS4AIi8<opcss, MRMSrcReg,
6815 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6817 !strconcat(OpcodeStr,
6818 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6819 !strconcat(OpcodeStr,
6820 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6821 []>, Sched<[WriteFAdd]>;
6823 // Intrinsic operation, reg.
6824 let isCodeGenOnly = 1 in
6825 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6826 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6828 !strconcat(OpcodeStr,
6829 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6830 !strconcat(OpcodeStr,
6831 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6832 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6835 // Intrinsic operation, mem.
6836 def SSm : SS4AIi8<opcss, MRMSrcMem,
6837 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6839 !strconcat(OpcodeStr,
6840 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6841 !strconcat(OpcodeStr,
6842 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6844 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6845 Sched<[WriteFAddLd, ReadAfterLd]>;
6848 let hasSideEffects = 0 in
6849 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6850 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6852 !strconcat(OpcodeStr,
6853 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6854 !strconcat(OpcodeStr,
6855 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6856 []>, Sched<[WriteFAdd]>;
6858 // Intrinsic operation, reg.
6859 let isCodeGenOnly = 1 in
6860 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6861 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6863 !strconcat(OpcodeStr,
6864 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6865 !strconcat(OpcodeStr,
6866 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6867 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6870 // Intrinsic operation, mem.
6871 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6872 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6874 !strconcat(OpcodeStr,
6875 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6876 !strconcat(OpcodeStr,
6877 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6879 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6880 Sched<[WriteFAddLd, ReadAfterLd]>;
6881 } // ExeDomain = GenericDomain
6884 // FP round - roundss, roundps, roundsd, roundpd
6885 let Predicates = [HasAVX] in {
6887 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6888 loadv4f32, loadv2f64,
6889 int_x86_sse41_round_ps,
6890 int_x86_sse41_round_pd>, VEX;
6891 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6892 loadv8f32, loadv4f64,
6893 int_x86_avx_round_ps_256,
6894 int_x86_avx_round_pd_256>, VEX, VEX_L;
6895 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6896 int_x86_sse41_round_ss,
6897 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6899 def : Pat<(ffloor FR32:$src),
6900 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6901 def : Pat<(f64 (ffloor FR64:$src)),
6902 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6903 def : Pat<(f32 (fnearbyint FR32:$src)),
6904 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6905 def : Pat<(f64 (fnearbyint FR64:$src)),
6906 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6907 def : Pat<(f32 (fceil FR32:$src)),
6908 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6909 def : Pat<(f64 (fceil FR64:$src)),
6910 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6911 def : Pat<(f32 (frint FR32:$src)),
6912 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6913 def : Pat<(f64 (frint FR64:$src)),
6914 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6915 def : Pat<(f32 (ftrunc FR32:$src)),
6916 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6917 def : Pat<(f64 (ftrunc FR64:$src)),
6918 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6920 def : Pat<(v4f32 (ffloor VR128:$src)),
6921 (VROUNDPSr VR128:$src, (i32 0x1))>;
6922 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6923 (VROUNDPSr VR128:$src, (i32 0xC))>;
6924 def : Pat<(v4f32 (fceil VR128:$src)),
6925 (VROUNDPSr VR128:$src, (i32 0x2))>;
6926 def : Pat<(v4f32 (frint VR128:$src)),
6927 (VROUNDPSr VR128:$src, (i32 0x4))>;
6928 def : Pat<(v4f32 (ftrunc VR128:$src)),
6929 (VROUNDPSr VR128:$src, (i32 0x3))>;
6931 def : Pat<(v2f64 (ffloor VR128:$src)),
6932 (VROUNDPDr VR128:$src, (i32 0x1))>;
6933 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6934 (VROUNDPDr VR128:$src, (i32 0xC))>;
6935 def : Pat<(v2f64 (fceil VR128:$src)),
6936 (VROUNDPDr VR128:$src, (i32 0x2))>;
6937 def : Pat<(v2f64 (frint VR128:$src)),
6938 (VROUNDPDr VR128:$src, (i32 0x4))>;
6939 def : Pat<(v2f64 (ftrunc VR128:$src)),
6940 (VROUNDPDr VR128:$src, (i32 0x3))>;
6942 def : Pat<(v8f32 (ffloor VR256:$src)),
6943 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6944 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6945 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6946 def : Pat<(v8f32 (fceil VR256:$src)),
6947 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6948 def : Pat<(v8f32 (frint VR256:$src)),
6949 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6950 def : Pat<(v8f32 (ftrunc VR256:$src)),
6951 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6953 def : Pat<(v4f64 (ffloor VR256:$src)),
6954 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6955 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6956 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6957 def : Pat<(v4f64 (fceil VR256:$src)),
6958 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6959 def : Pat<(v4f64 (frint VR256:$src)),
6960 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6961 def : Pat<(v4f64 (ftrunc VR256:$src)),
6962 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6965 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6966 memopv4f32, memopv2f64,
6967 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6968 let Constraints = "$src1 = $dst" in
6969 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6970 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6972 let Predicates = [UseSSE41] in {
6973 def : Pat<(ffloor FR32:$src),
6974 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6975 def : Pat<(f64 (ffloor FR64:$src)),
6976 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6977 def : Pat<(f32 (fnearbyint FR32:$src)),
6978 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6979 def : Pat<(f64 (fnearbyint FR64:$src)),
6980 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6981 def : Pat<(f32 (fceil FR32:$src)),
6982 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6983 def : Pat<(f64 (fceil FR64:$src)),
6984 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6985 def : Pat<(f32 (frint FR32:$src)),
6986 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6987 def : Pat<(f64 (frint FR64:$src)),
6988 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6989 def : Pat<(f32 (ftrunc FR32:$src)),
6990 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6991 def : Pat<(f64 (ftrunc FR64:$src)),
6992 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6994 def : Pat<(v4f32 (ffloor VR128:$src)),
6995 (ROUNDPSr VR128:$src, (i32 0x1))>;
6996 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6997 (ROUNDPSr VR128:$src, (i32 0xC))>;
6998 def : Pat<(v4f32 (fceil VR128:$src)),
6999 (ROUNDPSr VR128:$src, (i32 0x2))>;
7000 def : Pat<(v4f32 (frint VR128:$src)),
7001 (ROUNDPSr VR128:$src, (i32 0x4))>;
7002 def : Pat<(v4f32 (ftrunc VR128:$src)),
7003 (ROUNDPSr VR128:$src, (i32 0x3))>;
7005 def : Pat<(v2f64 (ffloor VR128:$src)),
7006 (ROUNDPDr VR128:$src, (i32 0x1))>;
7007 def : Pat<(v2f64 (fnearbyint VR128:$src)),
7008 (ROUNDPDr VR128:$src, (i32 0xC))>;
7009 def : Pat<(v2f64 (fceil VR128:$src)),
7010 (ROUNDPDr VR128:$src, (i32 0x2))>;
7011 def : Pat<(v2f64 (frint VR128:$src)),
7012 (ROUNDPDr VR128:$src, (i32 0x4))>;
7013 def : Pat<(v2f64 (ftrunc VR128:$src)),
7014 (ROUNDPDr VR128:$src, (i32 0x3))>;
7017 //===----------------------------------------------------------------------===//
7018 // SSE4.1 - Packed Bit Test
7019 //===----------------------------------------------------------------------===//
7021 // ptest instruction we'll lower to this in X86ISelLowering primarily from
7022 // the intel intrinsic that corresponds to this.
7023 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7024 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7025 "vptest\t{$src2, $src1|$src1, $src2}",
7026 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7027 Sched<[WriteVecLogic]>, VEX;
7028 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7029 "vptest\t{$src2, $src1|$src1, $src2}",
7030 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
7031 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7033 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
7034 "vptest\t{$src2, $src1|$src1, $src2}",
7035 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
7036 Sched<[WriteVecLogic]>, VEX, VEX_L;
7037 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
7038 "vptest\t{$src2, $src1|$src1, $src2}",
7039 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
7040 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
7043 let Defs = [EFLAGS] in {
7044 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7045 "ptest\t{$src2, $src1|$src1, $src2}",
7046 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7047 Sched<[WriteVecLogic]>;
7048 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7049 "ptest\t{$src2, $src1|$src1, $src2}",
7050 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
7051 Sched<[WriteVecLogicLd, ReadAfterLd]>;
7054 // The bit test instructions below are AVX only
7055 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
7056 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
7057 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
7058 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7059 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
7060 Sched<[WriteVecLogic]>, VEX;
7061 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
7062 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7063 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
7064 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7067 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7068 let ExeDomain = SSEPackedSingle in {
7069 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
7070 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
7073 let ExeDomain = SSEPackedDouble in {
7074 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
7075 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
7080 //===----------------------------------------------------------------------===//
7081 // SSE4.1 - Misc Instructions
7082 //===----------------------------------------------------------------------===//
7084 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
7085 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
7086 "popcnt{w}\t{$src, $dst|$dst, $src}",
7087 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
7088 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7090 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
7091 "popcnt{w}\t{$src, $dst|$dst, $src}",
7092 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
7093 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7094 Sched<[WriteFAddLd]>, OpSize16, XS;
7096 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
7097 "popcnt{l}\t{$src, $dst|$dst, $src}",
7098 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
7099 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7102 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
7103 "popcnt{l}\t{$src, $dst|$dst, $src}",
7104 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
7105 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7106 Sched<[WriteFAddLd]>, OpSize32, XS;
7108 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
7109 "popcnt{q}\t{$src, $dst|$dst, $src}",
7110 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7111 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7112 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7113 "popcnt{q}\t{$src, $dst|$dst, $src}",
7114 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7115 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7116 Sched<[WriteFAddLd]>, XS;
7121 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7122 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7124 X86FoldableSchedWrite Sched> {
7125 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7127 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7128 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7130 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7134 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7135 Sched<[Sched.Folded]>;
7138 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7139 // model, although the naming is misleading.
7140 let Predicates = [HasAVX] in
7141 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7142 int_x86_sse41_phminposuw,
7144 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7145 int_x86_sse41_phminposuw,
7148 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7149 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7150 Intrinsic IntId128, bit Is2Addr = 1,
7151 OpndItins itins = DEFAULT_ITINS> {
7152 let isCommutable = 1 in
7153 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7154 (ins VR128:$src1, VR128:$src2),
7156 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7157 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7158 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7159 itins.rr>, Sched<[itins.Sched]>;
7160 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7161 (ins VR128:$src1, i128mem:$src2),
7163 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7164 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7166 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7167 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7170 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7171 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7173 X86FoldableSchedWrite Sched> {
7174 let isCommutable = 1 in
7175 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7176 (ins VR256:$src1, VR256:$src2),
7177 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7178 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7180 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7181 (ins VR256:$src1, i256mem:$src2),
7182 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7184 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7185 Sched<[Sched.Folded, ReadAfterLd]>;
7189 /// SS48I_binop_rm - Simple SSE41 binary operator.
7190 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7191 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7192 X86MemOperand x86memop, bit Is2Addr = 1,
7193 OpndItins itins = SSE_INTALU_ITINS_P> {
7194 let isCommutable = 1 in
7195 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7196 (ins RC:$src1, RC:$src2),
7198 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7199 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7200 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7201 Sched<[itins.Sched]>;
7202 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7203 (ins RC:$src1, x86memop:$src2),
7205 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7208 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7209 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7212 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7214 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7215 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7216 PatFrag memop_frag, X86MemOperand x86memop,
7218 bit IsCommutable = 0, bit Is2Addr = 1> {
7219 let isCommutable = IsCommutable in
7220 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7221 (ins RC:$src1, RC:$src2),
7223 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7224 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7225 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7226 Sched<[itins.Sched]>;
7227 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7228 (ins RC:$src1, x86memop:$src2),
7230 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7231 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7232 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7233 (bitconvert (memop_frag addr:$src2)))))]>,
7234 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7237 let Predicates = [HasAVX] in {
7238 let isCommutable = 0 in
7239 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7240 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7242 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7243 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7245 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7246 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7248 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7249 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7251 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7252 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7254 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7255 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7257 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7258 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7260 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7261 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7263 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7264 VR128, loadv2i64, i128mem,
7265 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7268 let Predicates = [HasAVX2] in {
7269 let isCommutable = 0 in
7270 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7271 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7273 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7274 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7276 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7277 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7279 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7280 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7282 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7283 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7285 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7286 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7288 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7289 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7291 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7292 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7294 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7295 VR256, loadv4i64, i256mem,
7296 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7299 let Constraints = "$src1 = $dst" in {
7300 let isCommutable = 0 in
7301 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7302 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7303 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7304 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7305 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7306 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7307 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7308 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7309 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7310 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7311 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7312 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7313 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7314 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7315 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7316 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7317 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7318 VR128, memopv2i64, i128mem,
7319 SSE_INTMUL_ITINS_P, 1>;
7322 let Predicates = [HasAVX] in {
7323 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7324 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7326 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7327 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7330 let Predicates = [HasAVX2] in {
7331 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7332 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7334 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7335 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7339 let Constraints = "$src1 = $dst" in {
7340 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7341 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7342 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7343 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7346 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7347 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7348 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7349 X86MemOperand x86memop, bit Is2Addr = 1,
7350 OpndItins itins = DEFAULT_ITINS> {
7351 let isCommutable = 1 in
7352 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7353 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7355 !strconcat(OpcodeStr,
7356 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7357 !strconcat(OpcodeStr,
7358 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7359 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7360 Sched<[itins.Sched]>;
7361 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7362 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7364 !strconcat(OpcodeStr,
7365 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7366 !strconcat(OpcodeStr,
7367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7370 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7371 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7374 let Predicates = [HasAVX] in {
7375 let isCommutable = 0 in {
7376 let ExeDomain = SSEPackedSingle in {
7377 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7378 VR128, loadv4f32, f128mem, 0,
7379 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7380 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7381 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7382 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7385 let ExeDomain = SSEPackedDouble in {
7386 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7387 VR128, loadv2f64, f128mem, 0,
7388 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7389 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7390 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7391 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7394 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7395 VR128, loadv2i64, i128mem, 0,
7396 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7397 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7398 VR128, loadv2i64, i128mem, 0,
7399 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7401 let ExeDomain = SSEPackedSingle in
7402 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7403 VR128, loadv4f32, f128mem, 0,
7404 SSE_DPPS_ITINS>, VEX_4V;
7405 let ExeDomain = SSEPackedDouble in
7406 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7407 VR128, loadv2f64, f128mem, 0,
7408 SSE_DPPS_ITINS>, VEX_4V;
7409 let ExeDomain = SSEPackedSingle in
7410 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7411 VR256, loadv8f32, i256mem, 0,
7412 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7415 let Predicates = [HasAVX2] in {
7416 let isCommutable = 0 in {
7417 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7418 VR256, loadv4i64, i256mem, 0,
7419 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7420 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7421 VR256, loadv4i64, i256mem, 0,
7422 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7426 let Constraints = "$src1 = $dst" in {
7427 let isCommutable = 0 in {
7428 let ExeDomain = SSEPackedSingle in
7429 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7430 VR128, memopv4f32, f128mem,
7431 1, SSE_INTALU_ITINS_FBLEND_P>;
7432 let ExeDomain = SSEPackedDouble in
7433 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7434 VR128, memopv2f64, f128mem,
7435 1, SSE_INTALU_ITINS_FBLEND_P>;
7436 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7437 VR128, memopv2i64, i128mem,
7438 1, SSE_INTALU_ITINS_BLEND_P>;
7439 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7440 VR128, memopv2i64, i128mem,
7441 1, SSE_MPSADBW_ITINS>;
7443 let ExeDomain = SSEPackedSingle in
7444 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7445 VR128, memopv4f32, f128mem, 1,
7447 let ExeDomain = SSEPackedDouble in
7448 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7449 VR128, memopv2f64, f128mem, 1,
7453 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7454 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7455 RegisterClass RC, X86MemOperand x86memop,
7456 PatFrag mem_frag, Intrinsic IntId,
7457 X86FoldableSchedWrite Sched> {
7458 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7459 (ins RC:$src1, RC:$src2, RC:$src3),
7460 !strconcat(OpcodeStr,
7461 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7462 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7463 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7466 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7467 (ins RC:$src1, x86memop:$src2, RC:$src3),
7468 !strconcat(OpcodeStr,
7469 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7471 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7473 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7474 Sched<[Sched.Folded, ReadAfterLd]>;
7477 let Predicates = [HasAVX] in {
7478 let ExeDomain = SSEPackedDouble in {
7479 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7480 loadv2f64, int_x86_sse41_blendvpd,
7482 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7483 loadv4f64, int_x86_avx_blendv_pd_256,
7484 WriteFVarBlend>, VEX_L;
7485 } // ExeDomain = SSEPackedDouble
7486 let ExeDomain = SSEPackedSingle in {
7487 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7488 loadv4f32, int_x86_sse41_blendvps,
7490 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7491 loadv8f32, int_x86_avx_blendv_ps_256,
7492 WriteFVarBlend>, VEX_L;
7493 } // ExeDomain = SSEPackedSingle
7494 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7495 loadv2i64, int_x86_sse41_pblendvb,
7499 let Predicates = [HasAVX2] in {
7500 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7501 loadv4i64, int_x86_avx2_pblendvb,
7502 WriteVarBlend>, VEX_L;
7505 let Predicates = [HasAVX] in {
7506 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7507 (v16i8 VR128:$src2))),
7508 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7509 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7510 (v4i32 VR128:$src2))),
7511 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7512 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7513 (v4f32 VR128:$src2))),
7514 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7515 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7516 (v2i64 VR128:$src2))),
7517 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7518 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7519 (v2f64 VR128:$src2))),
7520 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7521 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7522 (v8i32 VR256:$src2))),
7523 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7524 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7525 (v8f32 VR256:$src2))),
7526 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7527 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7528 (v4i64 VR256:$src2))),
7529 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7530 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7531 (v4f64 VR256:$src2))),
7532 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7534 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7536 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7537 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7539 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7541 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7543 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7544 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7546 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7547 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7549 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7552 let Predicates = [HasAVX2] in {
7553 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7554 (v32i8 VR256:$src2))),
7555 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7556 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7558 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7561 /// SS41I_ternary_int - SSE 4.1 ternary operator
7562 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7563 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7564 X86MemOperand x86memop, Intrinsic IntId,
7565 OpndItins itins = DEFAULT_ITINS> {
7566 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7567 (ins VR128:$src1, VR128:$src2),
7568 !strconcat(OpcodeStr,
7569 "\t{$src2, $dst|$dst, $src2}"),
7570 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7571 itins.rr>, Sched<[itins.Sched]>;
7573 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7574 (ins VR128:$src1, x86memop:$src2),
7575 !strconcat(OpcodeStr,
7576 "\t{$src2, $dst|$dst, $src2}"),
7579 (bitconvert (mem_frag addr:$src2)), XMM0))],
7580 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7584 let ExeDomain = SSEPackedDouble in
7585 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7586 int_x86_sse41_blendvpd,
7587 DEFAULT_ITINS_FBLENDSCHED>;
7588 let ExeDomain = SSEPackedSingle in
7589 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7590 int_x86_sse41_blendvps,
7591 DEFAULT_ITINS_FBLENDSCHED>;
7592 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7593 int_x86_sse41_pblendvb,
7594 DEFAULT_ITINS_VARBLENDSCHED>;
7596 // Aliases with the implicit xmm0 argument
7597 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7598 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7599 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7600 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7601 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7602 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7603 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7604 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7605 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7606 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7607 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7608 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7610 let Predicates = [UseSSE41] in {
7611 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7612 (v16i8 VR128:$src2))),
7613 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7614 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7615 (v4i32 VR128:$src2))),
7616 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7617 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7618 (v4f32 VR128:$src2))),
7619 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7620 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7621 (v2i64 VR128:$src2))),
7622 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7623 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7624 (v2f64 VR128:$src2))),
7625 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7627 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7629 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7630 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7632 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7633 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7635 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7639 let SchedRW = [WriteLoad] in {
7640 let Predicates = [HasAVX] in
7641 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7642 "vmovntdqa\t{$src, $dst|$dst, $src}",
7643 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7645 let Predicates = [HasAVX2] in
7646 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7647 "vmovntdqa\t{$src, $dst|$dst, $src}",
7648 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7650 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7651 "movntdqa\t{$src, $dst|$dst, $src}",
7652 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7655 //===----------------------------------------------------------------------===//
7656 // SSE4.2 - Compare Instructions
7657 //===----------------------------------------------------------------------===//
7659 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7660 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7661 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7662 X86MemOperand x86memop, bit Is2Addr = 1> {
7663 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7664 (ins RC:$src1, RC:$src2),
7666 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7668 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7669 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7670 (ins RC:$src1, x86memop:$src2),
7672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7673 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7675 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7678 let Predicates = [HasAVX] in
7679 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7680 loadv2i64, i128mem, 0>, VEX_4V;
7682 let Predicates = [HasAVX2] in
7683 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7684 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7686 let Constraints = "$src1 = $dst" in
7687 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7688 memopv2i64, i128mem>;
7690 //===----------------------------------------------------------------------===//
7691 // SSE4.2 - String/text Processing Instructions
7692 //===----------------------------------------------------------------------===//
7694 // Packed Compare Implicit Length Strings, Return Mask
7695 multiclass pseudo_pcmpistrm<string asm> {
7696 def REG : PseudoI<(outs VR128:$dst),
7697 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7698 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7700 def MEM : PseudoI<(outs VR128:$dst),
7701 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7702 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7703 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7706 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7707 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7708 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7711 multiclass pcmpistrm_SS42AI<string asm> {
7712 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7713 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7714 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7715 []>, Sched<[WritePCmpIStrM]>;
7717 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7718 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7719 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7720 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7723 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7724 let Predicates = [HasAVX] in
7725 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7726 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7729 // Packed Compare Explicit Length Strings, Return Mask
7730 multiclass pseudo_pcmpestrm<string asm> {
7731 def REG : PseudoI<(outs VR128:$dst),
7732 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7733 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7734 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7735 def MEM : PseudoI<(outs VR128:$dst),
7736 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7737 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7738 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7741 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7742 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7743 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7746 multiclass SS42AI_pcmpestrm<string asm> {
7747 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7748 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7749 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7750 []>, Sched<[WritePCmpEStrM]>;
7752 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7753 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7754 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7755 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7758 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7759 let Predicates = [HasAVX] in
7760 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7761 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7764 // Packed Compare Implicit Length Strings, Return Index
7765 multiclass pseudo_pcmpistri<string asm> {
7766 def REG : PseudoI<(outs GR32:$dst),
7767 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7768 [(set GR32:$dst, EFLAGS,
7769 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7770 def MEM : PseudoI<(outs GR32:$dst),
7771 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7772 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7773 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7776 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7777 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7778 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7781 multiclass SS42AI_pcmpistri<string asm> {
7782 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7783 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7784 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7785 []>, Sched<[WritePCmpIStrI]>;
7787 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7788 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7789 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7790 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7793 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7794 let Predicates = [HasAVX] in
7795 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7796 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7799 // Packed Compare Explicit Length Strings, Return Index
7800 multiclass pseudo_pcmpestri<string asm> {
7801 def REG : PseudoI<(outs GR32:$dst),
7802 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7803 [(set GR32:$dst, EFLAGS,
7804 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7805 def MEM : PseudoI<(outs GR32:$dst),
7806 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7807 [(set GR32:$dst, EFLAGS,
7808 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7812 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7813 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7814 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7817 multiclass SS42AI_pcmpestri<string asm> {
7818 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7819 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7820 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7821 []>, Sched<[WritePCmpEStrI]>;
7823 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7824 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7825 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7826 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7829 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7830 let Predicates = [HasAVX] in
7831 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7832 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7835 //===----------------------------------------------------------------------===//
7836 // SSE4.2 - CRC Instructions
7837 //===----------------------------------------------------------------------===//
7839 // No CRC instructions have AVX equivalents
7841 // crc intrinsic instruction
7842 // This set of instructions are only rm, the only difference is the size
7844 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7845 RegisterClass RCIn, SDPatternOperator Int> :
7846 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7847 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7848 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7851 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7852 X86MemOperand x86memop, SDPatternOperator Int> :
7853 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7854 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7855 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7856 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7858 let Constraints = "$src1 = $dst" in {
7859 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7860 int_x86_sse42_crc32_32_8>;
7861 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7862 int_x86_sse42_crc32_32_8>;
7863 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7864 int_x86_sse42_crc32_32_16>, OpSize16;
7865 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7866 int_x86_sse42_crc32_32_16>, OpSize16;
7867 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7868 int_x86_sse42_crc32_32_32>, OpSize32;
7869 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7870 int_x86_sse42_crc32_32_32>, OpSize32;
7871 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7872 int_x86_sse42_crc32_64_64>, REX_W;
7873 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7874 int_x86_sse42_crc32_64_64>, REX_W;
7875 let hasSideEffects = 0 in {
7877 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7879 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7884 //===----------------------------------------------------------------------===//
7885 // SHA-NI Instructions
7886 //===----------------------------------------------------------------------===//
7888 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7890 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7891 (ins VR128:$src1, VR128:$src2),
7892 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7894 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7895 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7897 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7898 (ins VR128:$src1, i128mem:$src2),
7899 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7901 (set VR128:$dst, (IntId VR128:$src1,
7902 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7903 (set VR128:$dst, (IntId VR128:$src1,
7904 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7907 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7908 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7909 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7910 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7912 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7913 (i8 imm:$src3)))]>, TA;
7914 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7915 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7916 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7918 (int_x86_sha1rnds4 VR128:$src1,
7919 (bc_v4i32 (memopv2i64 addr:$src2)),
7920 (i8 imm:$src3)))]>, TA;
7922 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7923 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7924 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7927 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7929 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7930 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7933 // Aliases with explicit %xmm0
7934 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7935 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7936 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7937 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7939 //===----------------------------------------------------------------------===//
7940 // AES-NI Instructions
7941 //===----------------------------------------------------------------------===//
7943 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7944 Intrinsic IntId128, bit Is2Addr = 1> {
7945 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7946 (ins VR128:$src1, VR128:$src2),
7948 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7950 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7951 Sched<[WriteAESDecEnc]>;
7952 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7953 (ins VR128:$src1, i128mem:$src2),
7955 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7958 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7959 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7962 // Perform One Round of an AES Encryption/Decryption Flow
7963 let Predicates = [HasAVX, HasAES] in {
7964 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7965 int_x86_aesni_aesenc, 0>, VEX_4V;
7966 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7967 int_x86_aesni_aesenclast, 0>, VEX_4V;
7968 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7969 int_x86_aesni_aesdec, 0>, VEX_4V;
7970 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7971 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7974 let Constraints = "$src1 = $dst" in {
7975 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7976 int_x86_aesni_aesenc>;
7977 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7978 int_x86_aesni_aesenclast>;
7979 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7980 int_x86_aesni_aesdec>;
7981 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7982 int_x86_aesni_aesdeclast>;
7985 // Perform the AES InvMixColumn Transformation
7986 let Predicates = [HasAVX, HasAES] in {
7987 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7989 "vaesimc\t{$src1, $dst|$dst, $src1}",
7991 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7993 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7994 (ins i128mem:$src1),
7995 "vaesimc\t{$src1, $dst|$dst, $src1}",
7996 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7997 Sched<[WriteAESIMCLd]>, VEX;
7999 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8001 "aesimc\t{$src1, $dst|$dst, $src1}",
8003 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
8004 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8005 (ins i128mem:$src1),
8006 "aesimc\t{$src1, $dst|$dst, $src1}",
8007 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
8008 Sched<[WriteAESIMCLd]>;
8010 // AES Round Key Generation Assist
8011 let Predicates = [HasAVX, HasAES] in {
8012 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8013 (ins VR128:$src1, i8imm:$src2),
8014 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8016 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8017 Sched<[WriteAESKeyGen]>, VEX;
8018 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8019 (ins i128mem:$src1, i8imm:$src2),
8020 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8022 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
8023 Sched<[WriteAESKeyGenLd]>, VEX;
8025 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8026 (ins VR128:$src1, i8imm:$src2),
8027 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8029 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8030 Sched<[WriteAESKeyGen]>;
8031 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8032 (ins i128mem:$src1, i8imm:$src2),
8033 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8035 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
8036 Sched<[WriteAESKeyGenLd]>;
8038 //===----------------------------------------------------------------------===//
8039 // PCLMUL Instructions
8040 //===----------------------------------------------------------------------===//
8042 // AVX carry-less Multiplication instructions
8043 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8044 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8045 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8047 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
8048 Sched<[WriteCLMul]>;
8050 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8051 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8052 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8053 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8054 (loadv2i64 addr:$src2), imm:$src3))]>,
8055 Sched<[WriteCLMulLd, ReadAfterLd]>;
8057 // Carry-less Multiplication instructions
8058 let Constraints = "$src1 = $dst" in {
8059 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8060 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8061 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8063 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8064 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8066 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8067 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8068 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8069 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8070 (memopv2i64 addr:$src2), imm:$src3))],
8071 IIC_SSE_PCLMULQDQ_RM>,
8072 Sched<[WriteCLMulLd, ReadAfterLd]>;
8073 } // Constraints = "$src1 = $dst"
8076 multiclass pclmul_alias<string asm, int immop> {
8077 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8078 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8080 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8081 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8083 def : InstAlias<!strconcat("vpclmul", asm,
8084 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8085 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8088 def : InstAlias<!strconcat("vpclmul", asm,
8089 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8090 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8093 defm : pclmul_alias<"hqhq", 0x11>;
8094 defm : pclmul_alias<"hqlq", 0x01>;
8095 defm : pclmul_alias<"lqhq", 0x10>;
8096 defm : pclmul_alias<"lqlq", 0x00>;
8098 //===----------------------------------------------------------------------===//
8099 // SSE4A Instructions
8100 //===----------------------------------------------------------------------===//
8102 let Predicates = [HasSSE4A] in {
8104 let Constraints = "$src = $dst" in {
8105 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8106 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8107 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8108 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8110 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8111 (ins VR128:$src, VR128:$mask),
8112 "extrq\t{$mask, $src|$src, $mask}",
8113 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8114 VR128:$mask))]>, PD;
8116 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8117 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8118 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8119 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8120 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8121 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8122 (ins VR128:$src, VR128:$mask),
8123 "insertq\t{$mask, $src|$src, $mask}",
8124 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8125 VR128:$mask))]>, XD;
8128 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8129 "movntss\t{$src, $dst|$dst, $src}",
8130 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8132 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8133 "movntsd\t{$src, $dst|$dst, $src}",
8134 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8137 //===----------------------------------------------------------------------===//
8139 //===----------------------------------------------------------------------===//
8141 //===----------------------------------------------------------------------===//
8142 // VBROADCAST - Load from memory and broadcast to all elements of the
8143 // destination operand
8145 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8146 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8147 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8148 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8149 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8151 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8152 X86MemOperand x86memop, ValueType VT,
8153 PatFrag ld_frag, SchedWrite Sched> :
8154 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8155 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8156 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8157 Sched<[Sched]>, VEX {
8161 // AVX2 adds register forms
8162 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8163 Intrinsic Int, SchedWrite Sched> :
8164 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8166 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8168 let ExeDomain = SSEPackedSingle in {
8169 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8170 f32mem, v4f32, loadf32, WriteLoad>;
8171 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8172 f32mem, v8f32, loadf32,
8173 WriteFShuffleLd>, VEX_L;
8175 let ExeDomain = SSEPackedDouble in
8176 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8177 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8178 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8179 int_x86_avx_vbroadcastf128_pd_256,
8180 WriteFShuffleLd>, VEX_L;
8182 let ExeDomain = SSEPackedSingle in {
8183 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8184 int_x86_avx2_vbroadcast_ss_ps,
8186 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8187 int_x86_avx2_vbroadcast_ss_ps_256,
8188 WriteFShuffle256>, VEX_L;
8190 let ExeDomain = SSEPackedDouble in
8191 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8192 int_x86_avx2_vbroadcast_sd_pd_256,
8193 WriteFShuffle256>, VEX_L;
8195 let Predicates = [HasAVX2] in
8196 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8197 int_x86_avx2_vbroadcasti128, WriteLoad>,
8200 let Predicates = [HasAVX] in
8201 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8202 (VBROADCASTF128 addr:$src)>;
8205 //===----------------------------------------------------------------------===//
8206 // VINSERTF128 - Insert packed floating-point values
8208 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8209 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8210 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8211 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8212 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8214 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8215 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8216 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8217 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8220 let Predicates = [HasAVX] in {
8221 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8223 (VINSERTF128rr VR256:$src1, VR128:$src2,
8224 (INSERT_get_vinsert128_imm VR256:$ins))>;
8225 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8227 (VINSERTF128rr VR256:$src1, VR128:$src2,
8228 (INSERT_get_vinsert128_imm VR256:$ins))>;
8230 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8232 (VINSERTF128rm VR256:$src1, addr:$src2,
8233 (INSERT_get_vinsert128_imm VR256:$ins))>;
8234 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8236 (VINSERTF128rm VR256:$src1, addr:$src2,
8237 (INSERT_get_vinsert128_imm VR256:$ins))>;
8240 let Predicates = [HasAVX1Only] in {
8241 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8243 (VINSERTF128rr VR256:$src1, VR128:$src2,
8244 (INSERT_get_vinsert128_imm VR256:$ins))>;
8245 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8247 (VINSERTF128rr VR256:$src1, VR128:$src2,
8248 (INSERT_get_vinsert128_imm VR256:$ins))>;
8249 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8251 (VINSERTF128rr VR256:$src1, VR128:$src2,
8252 (INSERT_get_vinsert128_imm VR256:$ins))>;
8253 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8255 (VINSERTF128rr VR256:$src1, VR128:$src2,
8256 (INSERT_get_vinsert128_imm VR256:$ins))>;
8258 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8260 (VINSERTF128rm VR256:$src1, addr:$src2,
8261 (INSERT_get_vinsert128_imm VR256:$ins))>;
8262 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8263 (bc_v4i32 (loadv2i64 addr:$src2)),
8265 (VINSERTF128rm VR256:$src1, addr:$src2,
8266 (INSERT_get_vinsert128_imm VR256:$ins))>;
8267 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8268 (bc_v16i8 (loadv2i64 addr:$src2)),
8270 (VINSERTF128rm VR256:$src1, addr:$src2,
8271 (INSERT_get_vinsert128_imm VR256:$ins))>;
8272 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8273 (bc_v8i16 (loadv2i64 addr:$src2)),
8275 (VINSERTF128rm VR256:$src1, addr:$src2,
8276 (INSERT_get_vinsert128_imm VR256:$ins))>;
8279 //===----------------------------------------------------------------------===//
8280 // VEXTRACTF128 - Extract packed floating-point values
8282 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8283 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8284 (ins VR256:$src1, i8imm:$src2),
8285 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8286 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8288 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8289 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8290 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8291 []>, Sched<[WriteStore]>, VEX, VEX_L;
8295 let Predicates = [HasAVX] in {
8296 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8297 (v4f32 (VEXTRACTF128rr
8298 (v8f32 VR256:$src1),
8299 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8300 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8301 (v2f64 (VEXTRACTF128rr
8302 (v4f64 VR256:$src1),
8303 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8305 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8306 (iPTR imm))), addr:$dst),
8307 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8308 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8309 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8310 (iPTR imm))), addr:$dst),
8311 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8312 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8315 let Predicates = [HasAVX1Only] in {
8316 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8317 (v2i64 (VEXTRACTF128rr
8318 (v4i64 VR256:$src1),
8319 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8320 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8321 (v4i32 (VEXTRACTF128rr
8322 (v8i32 VR256:$src1),
8323 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8324 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8325 (v8i16 (VEXTRACTF128rr
8326 (v16i16 VR256:$src1),
8327 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8328 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8329 (v16i8 (VEXTRACTF128rr
8330 (v32i8 VR256:$src1),
8331 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8333 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8334 (iPTR imm))), addr:$dst),
8335 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8336 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8337 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8338 (iPTR imm))), addr:$dst),
8339 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8340 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8341 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8342 (iPTR imm))), addr:$dst),
8343 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8344 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8345 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8346 (iPTR imm))), addr:$dst),
8347 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8348 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8351 //===----------------------------------------------------------------------===//
8352 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8354 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8355 Intrinsic IntLd, Intrinsic IntLd256,
8356 Intrinsic IntSt, Intrinsic IntSt256> {
8357 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8358 (ins VR128:$src1, f128mem:$src2),
8359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8360 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8362 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8363 (ins VR256:$src1, f256mem:$src2),
8364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8365 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8367 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8368 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8370 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8371 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8372 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8374 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8377 let ExeDomain = SSEPackedSingle in
8378 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8379 int_x86_avx_maskload_ps,
8380 int_x86_avx_maskload_ps_256,
8381 int_x86_avx_maskstore_ps,
8382 int_x86_avx_maskstore_ps_256>;
8383 let ExeDomain = SSEPackedDouble in
8384 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8385 int_x86_avx_maskload_pd,
8386 int_x86_avx_maskload_pd_256,
8387 int_x86_avx_maskstore_pd,
8388 int_x86_avx_maskstore_pd_256>;
8390 //===----------------------------------------------------------------------===//
8391 // VPERMIL - Permute Single and Double Floating-Point Values
8393 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8394 RegisterClass RC, X86MemOperand x86memop_f,
8395 X86MemOperand x86memop_i, PatFrag i_frag,
8396 Intrinsic IntVar, ValueType vt> {
8397 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8398 (ins RC:$src1, RC:$src2),
8399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8400 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8401 Sched<[WriteFShuffle]>;
8402 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8403 (ins RC:$src1, x86memop_i:$src2),
8404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8405 [(set RC:$dst, (IntVar RC:$src1,
8406 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8407 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8409 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8410 (ins RC:$src1, i8imm:$src2),
8411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8412 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX,
8413 Sched<[WriteFShuffle]>;
8414 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8415 (ins x86memop_f:$src1, i8imm:$src2),
8416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8418 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8419 Sched<[WriteFShuffleLd]>;
8422 let ExeDomain = SSEPackedSingle in {
8423 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8424 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8425 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8426 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8428 let ExeDomain = SSEPackedDouble in {
8429 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8430 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8431 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8432 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8435 let Predicates = [HasAVX] in {
8436 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8437 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8438 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8439 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8440 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
8442 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8443 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
8444 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8446 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
8447 (VPERMILPDri VR128:$src1, imm:$imm)>;
8448 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
8449 (VPERMILPDmi addr:$src1, imm:$imm)>;
8452 //===----------------------------------------------------------------------===//
8453 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8455 let ExeDomain = SSEPackedSingle in {
8456 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8457 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8458 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8459 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8460 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8461 Sched<[WriteFShuffle]>;
8462 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8463 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8464 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8465 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8466 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8467 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8470 let Predicates = [HasAVX] in {
8471 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8472 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8473 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8474 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8475 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8478 let Predicates = [HasAVX1Only] in {
8479 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8480 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8481 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8482 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8483 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8484 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8485 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8486 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8488 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8489 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8490 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8491 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8492 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8493 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8494 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8495 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8496 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8497 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8498 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8499 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8502 //===----------------------------------------------------------------------===//
8503 // VZERO - Zero YMM registers
8505 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8506 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8507 // Zero All YMM registers
8508 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8509 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8511 // Zero Upper bits of YMM registers
8512 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8513 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8516 //===----------------------------------------------------------------------===//
8517 // Half precision conversion instructions
8518 //===----------------------------------------------------------------------===//
8519 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8520 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8521 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8522 [(set RC:$dst, (Int VR128:$src))]>,
8523 T8PD, VEX, Sched<[WriteCvtF2F]>;
8524 let neverHasSideEffects = 1, mayLoad = 1 in
8525 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8526 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8527 Sched<[WriteCvtF2FLd]>;
8530 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8531 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8532 (ins RC:$src1, i32i8imm:$src2),
8533 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8534 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8535 TAPD, VEX, Sched<[WriteCvtF2F]>;
8536 let neverHasSideEffects = 1, mayStore = 1,
8537 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8538 def mr : Ii8<0x1D, MRMDestMem, (outs),
8539 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8540 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8544 let Predicates = [HasF16C] in {
8545 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8546 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8547 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8548 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8550 // Pattern match vcvtph2ps of a scalar i64 load.
8551 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8552 (VCVTPH2PSrm addr:$src)>;
8553 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8554 (VCVTPH2PSrm addr:$src)>;
8557 // Patterns for matching conversions from float to half-float and vice versa.
8558 let Predicates = [HasF16C] in {
8559 def : Pat<(fp_to_f16 FR32:$src),
8560 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8561 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8563 def : Pat<(f16_to_fp GR16:$src),
8564 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8565 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8567 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8568 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8569 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8572 //===----------------------------------------------------------------------===//
8573 // AVX2 Instructions
8574 //===----------------------------------------------------------------------===//
8576 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8577 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8578 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8579 X86MemOperand x86memop> {
8580 let isCommutable = 1 in
8581 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8582 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8583 !strconcat(OpcodeStr,
8584 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8585 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8586 Sched<[WriteBlend]>, VEX_4V;
8587 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8588 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8589 !strconcat(OpcodeStr,
8590 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8593 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8594 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8597 let isCommutable = 0 in {
8598 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8599 VR128, loadv2i64, i128mem>;
8600 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8601 VR256, loadv4i64, i256mem>, VEX_L;
8604 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8606 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8607 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8609 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8611 //===----------------------------------------------------------------------===//
8612 // VPBROADCAST - Load from memory and broadcast to all elements of the
8613 // destination operand
8615 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8616 X86MemOperand x86memop, PatFrag ld_frag,
8617 Intrinsic Int128, Intrinsic Int256> {
8618 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8620 [(set VR128:$dst, (Int128 VR128:$src))]>,
8621 Sched<[WriteShuffle]>, VEX;
8622 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8625 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8626 Sched<[WriteLoad]>, VEX;
8627 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8629 [(set VR256:$dst, (Int256 VR128:$src))]>,
8630 Sched<[WriteShuffle256]>, VEX, VEX_L;
8631 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8634 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8635 Sched<[WriteLoad]>, VEX, VEX_L;
8638 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8639 int_x86_avx2_pbroadcastb_128,
8640 int_x86_avx2_pbroadcastb_256>;
8641 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8642 int_x86_avx2_pbroadcastw_128,
8643 int_x86_avx2_pbroadcastw_256>;
8644 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8645 int_x86_avx2_pbroadcastd_128,
8646 int_x86_avx2_pbroadcastd_256>;
8647 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8648 int_x86_avx2_pbroadcastq_128,
8649 int_x86_avx2_pbroadcastq_256>;
8651 let Predicates = [HasAVX2] in {
8652 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8653 (VPBROADCASTBrm addr:$src)>;
8654 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8655 (VPBROADCASTBYrm addr:$src)>;
8656 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8657 (VPBROADCASTWrm addr:$src)>;
8658 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8659 (VPBROADCASTWYrm addr:$src)>;
8660 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8661 (VPBROADCASTDrm addr:$src)>;
8662 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8663 (VPBROADCASTDYrm addr:$src)>;
8664 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8665 (VPBROADCASTQrm addr:$src)>;
8666 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8667 (VPBROADCASTQYrm addr:$src)>;
8669 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8670 (VPBROADCASTBrr VR128:$src)>;
8671 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8672 (VPBROADCASTBYrr VR128:$src)>;
8673 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8674 (VPBROADCASTWrr VR128:$src)>;
8675 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8676 (VPBROADCASTWYrr VR128:$src)>;
8677 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8678 (VPBROADCASTDrr VR128:$src)>;
8679 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8680 (VPBROADCASTDYrr VR128:$src)>;
8681 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8682 (VPBROADCASTQrr VR128:$src)>;
8683 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8684 (VPBROADCASTQYrr VR128:$src)>;
8685 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8686 (VBROADCASTSSrr VR128:$src)>;
8687 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8688 (VBROADCASTSSYrr VR128:$src)>;
8689 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8690 (VPBROADCASTQrr VR128:$src)>;
8691 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8692 (VBROADCASTSDYrr VR128:$src)>;
8694 // Provide fallback in case the load node that is used in the patterns above
8695 // is used by additional users, which prevents the pattern selection.
8696 let AddedComplexity = 20 in {
8697 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8698 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8699 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8700 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8701 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8702 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8704 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8705 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8706 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8707 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8708 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8709 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8711 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8712 (VPBROADCASTBrr (COPY_TO_REGCLASS
8713 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8715 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8716 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8717 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8720 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8721 (VPBROADCASTWrr (COPY_TO_REGCLASS
8722 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8724 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8725 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8726 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8729 // The patterns for VPBROADCASTD are not needed because they would match
8730 // the exact same thing as VBROADCASTSS patterns.
8732 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8733 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8734 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8738 // AVX1 broadcast patterns
8739 let Predicates = [HasAVX1Only] in {
8740 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8741 (VBROADCASTSSYrm addr:$src)>;
8742 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8743 (VBROADCASTSDYrm addr:$src)>;
8744 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8745 (VBROADCASTSSrm addr:$src)>;
8748 let Predicates = [HasAVX] in {
8749 // Provide fallback in case the load node that is used in the patterns above
8750 // is used by additional users, which prevents the pattern selection.
8751 let AddedComplexity = 20 in {
8752 // 128bit broadcasts:
8753 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8754 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8755 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8756 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8757 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8758 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8759 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8760 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8761 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8762 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8764 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8765 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8766 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8767 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8768 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8769 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8770 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8771 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8772 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8773 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8777 //===----------------------------------------------------------------------===//
8778 // VPERM - Permute instructions
8781 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8782 ValueType OpVT, X86FoldableSchedWrite Sched> {
8783 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8784 (ins VR256:$src1, VR256:$src2),
8785 !strconcat(OpcodeStr,
8786 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8788 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8789 Sched<[Sched]>, VEX_4V, VEX_L;
8790 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8791 (ins VR256:$src1, i256mem:$src2),
8792 !strconcat(OpcodeStr,
8793 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8795 (OpVT (X86VPermv VR256:$src1,
8796 (bitconvert (mem_frag addr:$src2)))))]>,
8797 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8800 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8801 let ExeDomain = SSEPackedSingle in
8802 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8804 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8805 ValueType OpVT, X86FoldableSchedWrite Sched> {
8806 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8807 (ins VR256:$src1, i8imm:$src2),
8808 !strconcat(OpcodeStr,
8809 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8811 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8812 Sched<[Sched]>, VEX, VEX_L;
8813 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8814 (ins i256mem:$src1, i8imm:$src2),
8815 !strconcat(OpcodeStr,
8816 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8818 (OpVT (X86VPermi (mem_frag addr:$src1),
8819 (i8 imm:$src2))))]>,
8820 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8823 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8824 WriteShuffle256>, VEX_W;
8825 let ExeDomain = SSEPackedDouble in
8826 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8827 WriteFShuffle256>, VEX_W;
8829 //===----------------------------------------------------------------------===//
8830 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8832 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8833 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8834 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8835 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8836 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8838 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8839 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8840 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8841 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8843 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8845 let Predicates = [HasAVX2] in {
8846 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8847 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8848 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8849 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8850 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8851 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8853 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8855 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8856 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8857 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8858 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8859 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8861 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8865 //===----------------------------------------------------------------------===//
8866 // VINSERTI128 - Insert packed integer values
8868 let neverHasSideEffects = 1 in {
8869 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8870 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8871 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8872 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8874 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8875 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8876 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8877 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8880 let Predicates = [HasAVX2] in {
8881 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8883 (VINSERTI128rr VR256:$src1, VR128:$src2,
8884 (INSERT_get_vinsert128_imm VR256:$ins))>;
8885 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8887 (VINSERTI128rr VR256:$src1, VR128:$src2,
8888 (INSERT_get_vinsert128_imm VR256:$ins))>;
8889 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8891 (VINSERTI128rr VR256:$src1, VR128:$src2,
8892 (INSERT_get_vinsert128_imm VR256:$ins))>;
8893 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8895 (VINSERTI128rr VR256:$src1, VR128:$src2,
8896 (INSERT_get_vinsert128_imm VR256:$ins))>;
8898 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8900 (VINSERTI128rm VR256:$src1, addr:$src2,
8901 (INSERT_get_vinsert128_imm VR256:$ins))>;
8902 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8903 (bc_v4i32 (loadv2i64 addr:$src2)),
8905 (VINSERTI128rm VR256:$src1, addr:$src2,
8906 (INSERT_get_vinsert128_imm VR256:$ins))>;
8907 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8908 (bc_v16i8 (loadv2i64 addr:$src2)),
8910 (VINSERTI128rm VR256:$src1, addr:$src2,
8911 (INSERT_get_vinsert128_imm VR256:$ins))>;
8912 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8913 (bc_v8i16 (loadv2i64 addr:$src2)),
8915 (VINSERTI128rm VR256:$src1, addr:$src2,
8916 (INSERT_get_vinsert128_imm VR256:$ins))>;
8919 //===----------------------------------------------------------------------===//
8920 // VEXTRACTI128 - Extract packed integer values
8922 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8923 (ins VR256:$src1, i8imm:$src2),
8924 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8926 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8927 Sched<[WriteShuffle256]>, VEX, VEX_L;
8928 let neverHasSideEffects = 1, mayStore = 1 in
8929 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8930 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8931 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8932 Sched<[WriteStore]>, VEX, VEX_L;
8934 let Predicates = [HasAVX2] in {
8935 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8936 (v2i64 (VEXTRACTI128rr
8937 (v4i64 VR256:$src1),
8938 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8939 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8940 (v4i32 (VEXTRACTI128rr
8941 (v8i32 VR256:$src1),
8942 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8943 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8944 (v8i16 (VEXTRACTI128rr
8945 (v16i16 VR256:$src1),
8946 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8947 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8948 (v16i8 (VEXTRACTI128rr
8949 (v32i8 VR256:$src1),
8950 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8952 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8953 (iPTR imm))), addr:$dst),
8954 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8955 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8956 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8957 (iPTR imm))), addr:$dst),
8958 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8959 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8960 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8961 (iPTR imm))), addr:$dst),
8962 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8963 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8964 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8965 (iPTR imm))), addr:$dst),
8966 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8967 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8970 //===----------------------------------------------------------------------===//
8971 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8973 multiclass avx2_pmovmask<string OpcodeStr,
8974 Intrinsic IntLd128, Intrinsic IntLd256,
8975 Intrinsic IntSt128, Intrinsic IntSt256> {
8976 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8977 (ins VR128:$src1, i128mem:$src2),
8978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8979 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8980 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8981 (ins VR256:$src1, i256mem:$src2),
8982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8983 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8985 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8986 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8988 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8989 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8990 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8991 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8992 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8995 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8996 int_x86_avx2_maskload_d,
8997 int_x86_avx2_maskload_d_256,
8998 int_x86_avx2_maskstore_d,
8999 int_x86_avx2_maskstore_d_256>;
9000 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
9001 int_x86_avx2_maskload_q,
9002 int_x86_avx2_maskload_q_256,
9003 int_x86_avx2_maskstore_q,
9004 int_x86_avx2_maskstore_q_256>, VEX_W;
9007 //===----------------------------------------------------------------------===//
9008 // Variable Bit Shifts
9010 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9011 ValueType vt128, ValueType vt256> {
9012 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9013 (ins VR128:$src1, VR128:$src2),
9014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9016 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9017 VEX_4V, Sched<[WriteVarVecShift]>;
9018 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9019 (ins VR128:$src1, i128mem:$src2),
9020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9022 (vt128 (OpNode VR128:$src1,
9023 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9024 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9025 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9026 (ins VR256:$src1, VR256:$src2),
9027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9029 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9030 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9031 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9032 (ins VR256:$src1, i256mem:$src2),
9033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9035 (vt256 (OpNode VR256:$src1,
9036 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9037 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9040 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9041 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9042 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9043 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9044 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9046 //===----------------------------------------------------------------------===//
9047 // VGATHER - GATHER Operations
9048 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9049 X86MemOperand memop128, X86MemOperand memop256> {
9050 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9051 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9052 !strconcat(OpcodeStr,
9053 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9055 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9056 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9057 !strconcat(OpcodeStr,
9058 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9059 []>, VEX_4VOp3, VEX_L;
9062 let mayLoad = 1, Constraints
9063 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9065 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9066 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9067 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9068 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9070 let ExeDomain = SSEPackedDouble in {
9071 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9072 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9075 let ExeDomain = SSEPackedSingle in {
9076 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9077 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;