1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (COPY_TO_REGCLASS FR32:$src, VR128)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (COPY_TO_REGCLASS FR64:$src, VR128)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
566 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
567 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
568 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
569 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
571 // Move low f32 and clear high bits.
572 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
573 (SUBREG_TO_REG (i32 0),
574 (VMOVSSrr (v4f32 (V_SET0)),
575 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
576 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
577 (SUBREG_TO_REG (i32 0),
578 (VMOVSSrr (v4i32 (V_SET0)),
579 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
582 let AddedComplexity = 20 in {
583 // MOVSSrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
587 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
589 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
592 // MOVSDrm zeros the high parts of the register; represent this
593 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
594 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
595 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
596 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
597 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
598 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
599 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
600 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
601 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
602 def : Pat<(v2f64 (X86vzload addr:$src)),
603 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
605 // Represent the same patterns above but in the form they appear for
607 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
608 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
609 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
610 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
611 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
612 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
615 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
617 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
618 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
619 (SUBREG_TO_REG (i32 0),
620 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
622 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
623 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
624 (SUBREG_TO_REG (i64 0),
625 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
627 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
628 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
629 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
631 // Move low f64 and clear high bits.
632 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
633 (SUBREG_TO_REG (i32 0),
634 (VMOVSDrr (v2f64 (V_SET0)),
635 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
637 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
638 (SUBREG_TO_REG (i32 0),
639 (VMOVSDrr (v2i64 (V_SET0)),
640 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
642 // Extract and store.
643 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
645 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
646 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
648 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
650 // Shuffle with VMOVSS
651 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
652 (VMOVSSrr (v4i32 VR128:$src1),
653 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
654 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
655 (VMOVSSrr (v4f32 VR128:$src1),
656 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
659 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
660 (SUBREG_TO_REG (i32 0),
661 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
662 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
664 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
665 (SUBREG_TO_REG (i32 0),
666 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
667 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
670 // Shuffle with VMOVSD
671 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
672 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
673 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
675 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
676 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
677 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
678 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
681 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
682 (SUBREG_TO_REG (i32 0),
683 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
684 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
686 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
687 (SUBREG_TO_REG (i32 0),
688 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
689 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
693 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
694 // is during lowering, where it's not possible to recognize the fold cause
695 // it has two uses through a bitcast. One use disappears at isel time and the
696 // fold opportunity reappears.
697 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
698 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
699 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
700 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
701 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
703 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
704 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
707 let Predicates = [HasSSE1] in {
708 let AddedComplexity = 15 in {
709 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
710 // MOVSS to the lower bits.
711 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
712 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
713 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
714 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
715 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
716 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
719 let AddedComplexity = 20 in {
720 // MOVSSrm already zeros the high parts of the register.
721 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
722 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
723 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
724 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
725 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
726 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
729 // Extract and store.
730 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
732 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
734 // Shuffle with MOVSS
735 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
736 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
737 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
738 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
741 let Predicates = [HasSSE2] in {
742 let AddedComplexity = 15 in {
743 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
744 // MOVSD to the lower bits.
745 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
746 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
749 let AddedComplexity = 20 in {
750 // MOVSDrm already zeros the high parts of the register.
751 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
752 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
753 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
754 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
755 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
756 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
757 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
758 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
759 def : Pat<(v2f64 (X86vzload addr:$src)),
760 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
763 // Extract and store.
764 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
766 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
768 // Shuffle with MOVSD
769 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
770 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
771 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
772 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
773 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
778 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
779 // is during lowering, where it's not possible to recognize the fold cause
780 // it has two uses through a bitcast. One use disappears at isel time and the
781 // fold opportunity reappears.
782 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
788 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
789 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
792 //===----------------------------------------------------------------------===//
793 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
794 //===----------------------------------------------------------------------===//
796 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
797 X86MemOperand x86memop, PatFrag ld_frag,
798 string asm, Domain d,
800 bit IsReMaterializable = 1> {
801 let neverHasSideEffects = 1 in
802 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
803 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
810 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
811 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
813 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
814 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
816 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
817 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
819 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
820 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
823 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
824 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
826 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
827 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
830 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
832 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
833 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
848 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
849 "movaps\t{$src, $dst|$dst, $src}",
850 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
851 IIC_SSE_MOVA_P_MR>, VEX;
852 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
853 "movapd\t{$src, $dst|$dst, $src}",
854 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
855 IIC_SSE_MOVA_P_MR>, VEX;
856 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
857 "movups\t{$src, $dst|$dst, $src}",
858 [(store (v4f32 VR128:$src), addr:$dst)],
859 IIC_SSE_MOVU_P_MR>, VEX;
860 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
861 "movupd\t{$src, $dst|$dst, $src}",
862 [(store (v2f64 VR128:$src), addr:$dst)],
863 IIC_SSE_MOVU_P_MR>, VEX;
864 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
865 "movaps\t{$src, $dst|$dst, $src}",
866 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
867 IIC_SSE_MOVA_P_MR>, VEX;
868 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
869 "movapd\t{$src, $dst|$dst, $src}",
870 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
871 IIC_SSE_MOVA_P_MR>, VEX;
872 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
873 "movups\t{$src, $dst|$dst, $src}",
874 [(store (v8f32 VR256:$src), addr:$dst)],
875 IIC_SSE_MOVU_P_MR>, VEX;
876 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
877 "movupd\t{$src, $dst|$dst, $src}",
878 [(store (v4f64 VR256:$src), addr:$dst)],
879 IIC_SSE_MOVU_P_MR>, VEX;
882 let isCodeGenOnly = 1 in {
883 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
885 "movaps\t{$src, $dst|$dst, $src}", [],
886 IIC_SSE_MOVA_P_RR>, VEX;
887 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
889 "movapd\t{$src, $dst|$dst, $src}", [],
890 IIC_SSE_MOVA_P_RR>, VEX;
891 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
893 "movups\t{$src, $dst|$dst, $src}", [],
894 IIC_SSE_MOVU_P_RR>, VEX;
895 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
897 "movupd\t{$src, $dst|$dst, $src}", [],
898 IIC_SSE_MOVU_P_RR>, VEX;
899 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
901 "movaps\t{$src, $dst|$dst, $src}", [],
902 IIC_SSE_MOVA_P_RR>, VEX;
903 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
905 "movapd\t{$src, $dst|$dst, $src}", [],
906 IIC_SSE_MOVA_P_RR>, VEX;
907 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
909 "movups\t{$src, $dst|$dst, $src}", [],
910 IIC_SSE_MOVU_P_RR>, VEX;
911 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
913 "movupd\t{$src, $dst|$dst, $src}", [],
914 IIC_SSE_MOVU_P_RR>, VEX;
917 let Predicates = [HasAVX] in {
918 def : Pat<(v8i32 (X86vzmovl
919 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
921 def : Pat<(v4i64 (X86vzmovl
922 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v8f32 (X86vzmovl
925 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v4f64 (X86vzmovl
928 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
933 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
934 (VMOVUPSYmr addr:$dst, VR256:$src)>;
935 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
936 (VMOVUPDYmr addr:$dst, VR256:$src)>;
938 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
939 "movaps\t{$src, $dst|$dst, $src}",
940 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
942 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movapd\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
946 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movups\t{$src, $dst|$dst, $src}",
948 [(store (v4f32 VR128:$src), addr:$dst)],
950 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movupd\t{$src, $dst|$dst, $src}",
952 [(store (v2f64 VR128:$src), addr:$dst)],
956 let isCodeGenOnly = 1 in {
957 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movaps\t{$src, $dst|$dst, $src}", [],
960 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}", [],
963 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
964 "movups\t{$src, $dst|$dst, $src}", [],
966 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
967 "movupd\t{$src, $dst|$dst, $src}", [],
971 let Predicates = [HasAVX] in {
972 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
973 (VMOVUPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
975 (VMOVUPDmr addr:$dst, VR128:$src)>;
978 let Predicates = [HasSSE1] in
979 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
980 (MOVUPSmr addr:$dst, VR128:$src)>;
981 let Predicates = [HasSSE2] in
982 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
983 (MOVUPDmr addr:$dst, VR128:$src)>;
985 // Use vmovaps/vmovups for AVX integer load/store.
986 let Predicates = [HasAVX] in {
987 // 128-bit load/store
988 def : Pat<(alignedloadv2i64 addr:$src),
989 (VMOVAPSrm addr:$src)>;
990 def : Pat<(loadv2i64 addr:$src),
991 (VMOVUPSrm addr:$src)>;
993 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
994 (VMOVAPSmr addr:$dst, VR128:$src)>;
995 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
996 (VMOVAPSmr addr:$dst, VR128:$src)>;
997 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
998 (VMOVAPSmr addr:$dst, VR128:$src)>;
999 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1000 (VMOVAPSmr addr:$dst, VR128:$src)>;
1001 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1002 (VMOVUPSmr addr:$dst, VR128:$src)>;
1003 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1004 (VMOVUPSmr addr:$dst, VR128:$src)>;
1005 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1006 (VMOVUPSmr addr:$dst, VR128:$src)>;
1007 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1008 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 // 256-bit load/store
1011 def : Pat<(alignedloadv4i64 addr:$src),
1012 (VMOVAPSYrm addr:$src)>;
1013 def : Pat<(loadv4i64 addr:$src),
1014 (VMOVUPSYrm addr:$src)>;
1015 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1016 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1017 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1018 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1019 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1020 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1021 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1022 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1023 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1024 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1025 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1026 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1027 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1028 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1029 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1030 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1033 // Use movaps / movups for SSE integer load / store (one byte shorter).
1034 // The instructions selected below are then converted to MOVDQA/MOVDQU
1035 // during the SSE domain pass.
1036 let Predicates = [HasSSE1] in {
1037 def : Pat<(alignedloadv2i64 addr:$src),
1038 (MOVAPSrm addr:$src)>;
1039 def : Pat<(loadv2i64 addr:$src),
1040 (MOVUPSrm addr:$src)>;
1042 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1043 (MOVAPSmr addr:$dst, VR128:$src)>;
1044 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1045 (MOVAPSmr addr:$dst, VR128:$src)>;
1046 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1047 (MOVAPSmr addr:$dst, VR128:$src)>;
1048 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1049 (MOVAPSmr addr:$dst, VR128:$src)>;
1050 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1051 (MOVUPSmr addr:$dst, VR128:$src)>;
1052 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1053 (MOVUPSmr addr:$dst, VR128:$src)>;
1054 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1055 (MOVUPSmr addr:$dst, VR128:$src)>;
1056 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1057 (MOVUPSmr addr:$dst, VR128:$src)>;
1060 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1061 // bits are disregarded. FIXME: Set encoding to pseudo!
1062 let neverHasSideEffects = 1 in {
1063 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1064 "movaps\t{$src, $dst|$dst, $src}", [],
1065 IIC_SSE_MOVA_P_RR>, VEX;
1066 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1067 "movapd\t{$src, $dst|$dst, $src}", [],
1068 IIC_SSE_MOVA_P_RR>, VEX;
1069 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1070 "movaps\t{$src, $dst|$dst, $src}", [],
1072 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1073 "movapd\t{$src, $dst|$dst, $src}", [],
1077 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1078 // bits are disregarded. FIXME: Set encoding to pseudo!
1079 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1080 let isCodeGenOnly = 1 in {
1081 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1082 "movaps\t{$src, $dst|$dst, $src}",
1083 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1084 IIC_SSE_MOVA_P_RM>, VEX;
1085 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1086 "movapd\t{$src, $dst|$dst, $src}",
1087 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1088 IIC_SSE_MOVA_P_RM>, VEX;
1090 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1091 "movaps\t{$src, $dst|$dst, $src}",
1092 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1094 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1095 "movapd\t{$src, $dst|$dst, $src}",
1096 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1100 //===----------------------------------------------------------------------===//
1101 // SSE 1 & 2 - Move Low packed FP Instructions
1102 //===----------------------------------------------------------------------===//
1104 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1105 SDNode psnode, SDNode pdnode, string base_opc,
1106 string asm_opr, InstrItinClass itin> {
1107 def PSrm : PI<opc, MRMSrcMem,
1108 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1109 !strconcat(base_opc, "s", asm_opr),
1112 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1113 itin, SSEPackedSingle>, TB;
1115 def PDrm : PI<opc, MRMSrcMem,
1116 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1117 !strconcat(base_opc, "d", asm_opr),
1118 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1119 (scalar_to_vector (loadf64 addr:$src2)))))],
1120 itin, SSEPackedDouble>, TB, OpSize;
1123 let AddedComplexity = 20 in {
1124 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1126 IIC_SSE_MOV_LH>, VEX_4V;
1128 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1129 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1130 "\t{$src2, $dst|$dst, $src2}",
1134 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movlps\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1137 (iPTR 0))), addr:$dst)],
1138 IIC_SSE_MOV_LH>, VEX;
1139 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1140 "movlpd\t{$src, $dst|$dst, $src}",
1141 [(store (f64 (vector_extract (v2f64 VR128:$src),
1142 (iPTR 0))), addr:$dst)],
1143 IIC_SSE_MOV_LH>, VEX;
1144 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1145 "movlps\t{$src, $dst|$dst, $src}",
1146 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1147 (iPTR 0))), addr:$dst)],
1149 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1150 "movlpd\t{$src, $dst|$dst, $src}",
1151 [(store (f64 (vector_extract (v2f64 VR128:$src),
1152 (iPTR 0))), addr:$dst)],
1155 let Predicates = [HasAVX] in {
1156 // Shuffle with VMOVLPS
1157 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1158 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1159 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1160 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1162 // Shuffle with VMOVLPD
1163 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1164 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1165 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1166 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1169 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1171 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1172 def : Pat<(store (v4i32 (X86Movlps
1173 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1174 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1175 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1177 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1178 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1180 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1183 let Predicates = [HasSSE1] in {
1184 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1185 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1186 (iPTR 0))), addr:$src1),
1187 (MOVLPSmr addr:$src1, VR128:$src2)>;
1189 // Shuffle with MOVLPS
1190 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (MOVLPSrm VR128:$src1, addr:$src2)>;
1192 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1193 (MOVLPSrm VR128:$src1, addr:$src2)>;
1194 def : Pat<(X86Movlps VR128:$src1,
1195 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1196 (MOVLPSrm VR128:$src1, addr:$src2)>;
1199 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1201 (MOVLPSmr addr:$src1, VR128:$src2)>;
1202 def : Pat<(store (v4i32 (X86Movlps
1203 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1208 let Predicates = [HasSSE2] in {
1209 // Shuffle with MOVLPD
1210 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1211 (MOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1213 (MOVLPDrm VR128:$src1, addr:$src2)>;
1216 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1218 (MOVLPDmr addr:$src1, VR128:$src2)>;
1219 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1221 (MOVLPDmr addr:$src1, VR128:$src2)>;
1224 //===----------------------------------------------------------------------===//
1225 // SSE 1 & 2 - Move Hi packed FP Instructions
1226 //===----------------------------------------------------------------------===//
1228 let AddedComplexity = 20 in {
1229 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1230 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1231 IIC_SSE_MOV_LH>, VEX_4V;
1233 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1234 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1235 "\t{$src2, $dst|$dst, $src2}",
1239 // v2f64 extract element 1 is always custom lowered to unpack high to low
1240 // and extract element 0 so the non-store version isn't too horrible.
1241 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1242 "movhps\t{$src, $dst|$dst, $src}",
1243 [(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))),
1246 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1247 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1248 "movhpd\t{$src, $dst|$dst, $src}",
1249 [(store (f64 (vector_extract
1250 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1251 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1252 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1253 "movhps\t{$src, $dst|$dst, $src}",
1254 [(store (f64 (vector_extract
1255 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1256 (bc_v2f64 (v4f32 VR128:$src))),
1257 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1258 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1259 "movhpd\t{$src, $dst|$dst, $src}",
1260 [(store (f64 (vector_extract
1261 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1262 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1264 let Predicates = [HasAVX] in {
1266 def : Pat<(X86Movlhps VR128:$src1,
1267 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1268 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1269 def : Pat<(X86Movlhps VR128:$src1,
1270 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1271 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1273 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1274 // is during lowering, where it's not possible to recognize the load fold
1275 // cause it has two uses through a bitcast. One use disappears at isel time
1276 // and the fold opportunity reappears.
1277 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1278 (scalar_to_vector (loadf64 addr:$src2)))),
1279 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1282 let Predicates = [HasSSE1] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (MOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1289 (MOVHPSrm VR128:$src1, addr:$src2)>;
1292 let Predicates = [HasSSE2] in {
1293 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1294 // is during lowering, where it's not possible to recognize the load fold
1295 // cause it has two uses through a bitcast. One use disappears at isel time
1296 // and the fold opportunity reappears.
1297 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1298 (scalar_to_vector (loadf64 addr:$src2)))),
1299 (MOVHPDrm VR128:$src1, addr:$src2)>;
1302 //===----------------------------------------------------------------------===//
1303 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1304 //===----------------------------------------------------------------------===//
1306 let AddedComplexity = 20 in {
1307 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1308 (ins VR128:$src1, VR128:$src2),
1309 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1311 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1314 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1315 (ins VR128:$src1, VR128:$src2),
1316 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1318 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1322 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1323 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1324 (ins VR128:$src1, VR128:$src2),
1325 "movlhps\t{$src2, $dst|$dst, $src2}",
1327 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1329 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1330 (ins VR128:$src1, VR128:$src2),
1331 "movhlps\t{$src2, $dst|$dst, $src2}",
1333 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1337 let Predicates = [HasAVX] in {
1339 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1340 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1341 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1342 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1345 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1346 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1349 let Predicates = [HasSSE1] in {
1351 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1352 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1353 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1354 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1357 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1358 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1361 //===----------------------------------------------------------------------===//
1362 // SSE 1 & 2 - Conversion Instructions
1363 //===----------------------------------------------------------------------===//
1365 def SSE_CVT_PD : OpndItins<
1366 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1369 def SSE_CVT_PS : OpndItins<
1370 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1373 def SSE_CVT_Scalar : OpndItins<
1374 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1377 def SSE_CVT_SS2SI_32 : OpndItins<
1378 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1381 def SSE_CVT_SS2SI_64 : OpndItins<
1382 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1385 def SSE_CVT_SD2SI : OpndItins<
1386 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1389 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1390 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1391 string asm, OpndItins itins> {
1392 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1393 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1395 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1396 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1400 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1401 X86MemOperand x86memop, string asm, Domain d,
1403 let neverHasSideEffects = 1 in {
1404 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1407 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1412 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1413 X86MemOperand x86memop, string asm> {
1414 let neverHasSideEffects = 1 in {
1415 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1416 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1418 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1419 (ins DstRC:$src1, x86memop:$src),
1420 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1421 } // neverHasSideEffects = 1
1424 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1425 "cvttss2si\t{$src, $dst|$dst, $src}",
1428 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1429 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1431 XS, VEX, VEX_W, VEX_LIG;
1432 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1433 "cvttsd2si\t{$src, $dst|$dst, $src}",
1436 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1437 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1439 XD, VEX, VEX_W, VEX_LIG;
1441 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1442 // register, but the same isn't true when only using memory operands,
1443 // provide other assembly "l" and "q" forms to address this explicitly
1444 // where appropriate to do so.
1445 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1446 XS, VEX_4V, VEX_LIG;
1447 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1448 XS, VEX_4V, VEX_W, VEX_LIG;
1449 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1450 XD, VEX_4V, VEX_LIG;
1451 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1452 XD, VEX_4V, VEX_W, VEX_LIG;
1454 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1455 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1456 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1457 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1459 let Predicates = [HasAVX], AddedComplexity = 1 in {
1460 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1461 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1462 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1463 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1464 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1465 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1466 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1467 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1469 def : Pat<(f32 (sint_to_fp GR32:$src)),
1470 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1471 def : Pat<(f32 (sint_to_fp GR64:$src)),
1472 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1473 def : Pat<(f64 (sint_to_fp GR32:$src)),
1474 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1475 def : Pat<(f64 (sint_to_fp GR64:$src)),
1476 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1479 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1480 "cvttss2si\t{$src, $dst|$dst, $src}",
1481 SSE_CVT_SS2SI_32>, XS;
1482 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1483 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1484 SSE_CVT_SS2SI_64>, XS, REX_W;
1485 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1486 "cvttsd2si\t{$src, $dst|$dst, $src}",
1488 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1489 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1490 SSE_CVT_SD2SI>, XD, REX_W;
1491 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1492 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1493 SSE_CVT_Scalar>, XS;
1494 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1495 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1496 SSE_CVT_Scalar>, XS, REX_W;
1497 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1498 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1499 SSE_CVT_Scalar>, XD;
1500 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1501 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1502 SSE_CVT_Scalar>, XD, REX_W;
1504 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1505 // and/or XMM operand(s).
1507 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1508 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1509 string asm, OpndItins itins> {
1510 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1511 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1512 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1513 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1514 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1515 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1518 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1519 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1520 PatFrag ld_frag, string asm, OpndItins itins,
1522 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1524 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1525 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1526 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1528 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1529 (ins DstRC:$src1, x86memop:$src2),
1531 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1532 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1533 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1537 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1538 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1539 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1540 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1541 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1542 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1544 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1545 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1546 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1547 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1550 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1551 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1552 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1553 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1554 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1555 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1557 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1558 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1559 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1560 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1561 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1562 SSE_CVT_Scalar, 0>, XD,
1565 let Constraints = "$src1 = $dst" in {
1566 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1567 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1568 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1569 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1570 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1571 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1572 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1573 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1574 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1575 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1576 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1577 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1582 // Aliases for intrinsics
1583 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1584 ssmem, sse_load_f32, "cvttss2si",
1585 SSE_CVT_SS2SI_32>, XS, VEX;
1586 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1587 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1588 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1590 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1591 sdmem, sse_load_f64, "cvttsd2si",
1592 SSE_CVT_SD2SI>, XD, VEX;
1593 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1594 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1595 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1597 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1598 ssmem, sse_load_f32, "cvttss2si",
1599 SSE_CVT_SS2SI_32>, XS;
1600 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1601 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1602 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1603 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 sdmem, sse_load_f64, "cvttsd2si",
1606 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1608 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1610 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1611 ssmem, sse_load_f32, "cvtss2si{l}",
1612 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1613 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1614 ssmem, sse_load_f32, "cvtss2si{q}",
1615 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1617 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1618 ssmem, sse_load_f32, "cvtss2si{l}",
1619 SSE_CVT_SS2SI_32>, XS;
1620 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1621 ssmem, sse_load_f32, "cvtss2si{q}",
1622 SSE_CVT_SS2SI_64>, XS, REX_W;
1624 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1625 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1626 SSEPackedSingle, SSE_CVT_PS>,
1627 TB, VEX, Requires<[HasAVX]>;
1628 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1629 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1630 SSEPackedSingle, SSE_CVT_PS>,
1631 TB, VEX, Requires<[HasAVX]>;
1633 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1634 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1635 SSEPackedSingle, SSE_CVT_PS>,
1636 TB, Requires<[HasSSE2]>;
1640 // Convert scalar double to scalar single
1641 let neverHasSideEffects = 1 in {
1642 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1643 (ins FR64:$src1, FR64:$src2),
1644 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1645 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1647 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1648 (ins FR64:$src1, f64mem:$src2),
1649 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1650 [], IIC_SSE_CVT_Scalar_RM>,
1651 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1654 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1657 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1658 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1659 [(set FR32:$dst, (fround FR64:$src))],
1660 IIC_SSE_CVT_Scalar_RR>;
1661 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1662 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1663 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1664 IIC_SSE_CVT_Scalar_RM>,
1666 Requires<[HasSSE2, OptForSize]>;
1668 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1669 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1670 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1673 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1674 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1675 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1676 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1677 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1678 VR128:$src1, sse_load_f64:$src2))],
1679 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1681 let Constraints = "$src1 = $dst" in {
1682 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1683 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1684 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1687 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[HasSSE2]>;
1688 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1689 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1690 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1692 VR128:$src1, sse_load_f64:$src2))],
1693 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[HasSSE2]>;
1696 // Convert scalar single to scalar double
1697 // SSE2 instructions with XS prefix
1698 let neverHasSideEffects = 1 in {
1699 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1700 (ins FR32:$src1, FR32:$src2),
1701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1702 [], IIC_SSE_CVT_Scalar_RR>,
1703 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1705 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1706 (ins FR32:$src1, f32mem:$src2),
1707 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [], IIC_SSE_CVT_Scalar_RM>,
1709 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1712 let AddedComplexity = 1 in { // give AVX priority
1713 def : Pat<(f64 (fextend FR32:$src)),
1714 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1715 def : Pat<(fextend (loadf32 addr:$src)),
1716 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1718 def : Pat<(extloadf32 addr:$src),
1719 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1720 Requires<[HasAVX, OptForSize]>;
1721 def : Pat<(extloadf32 addr:$src),
1722 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1723 Requires<[HasAVX, OptForSpeed]>;
1724 } // AddedComplexity = 1
1726 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1727 "cvtss2sd\t{$src, $dst|$dst, $src}",
1728 [(set FR64:$dst, (fextend FR32:$src))],
1729 IIC_SSE_CVT_Scalar_RR>, XS,
1730 Requires<[HasSSE2]>;
1731 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1732 "cvtss2sd\t{$src, $dst|$dst, $src}",
1733 [(set FR64:$dst, (extloadf32 addr:$src))],
1734 IIC_SSE_CVT_Scalar_RM>, XS,
1735 Requires<[HasSSE2, OptForSize]>;
1737 // extload f32 -> f64. This matches load+fextend because we have a hack in
1738 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1740 // Since these loads aren't folded into the fextend, we have to match it
1742 def : Pat<(fextend (loadf32 addr:$src)),
1743 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1744 def : Pat<(extloadf32 addr:$src),
1745 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1747 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1751 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1752 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1753 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1754 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1755 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1757 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1758 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1759 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1760 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1764 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1765 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[HasSSE2]>;
1766 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1767 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1768 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1770 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1771 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[HasSSE2]>;
1774 // Convert packed single/double fp to doubleword
1775 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1776 "cvtps2dq\t{$src, $dst|$dst, $src}",
1777 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1778 IIC_SSE_CVT_PS_RR>, VEX;
1779 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1780 "cvtps2dq\t{$src, $dst|$dst, $src}",
1782 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1783 IIC_SSE_CVT_PS_RM>, VEX;
1784 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1785 "cvtps2dq\t{$src, $dst|$dst, $src}",
1787 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1788 IIC_SSE_CVT_PS_RR>, VEX;
1789 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1790 "cvtps2dq\t{$src, $dst|$dst, $src}",
1792 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1793 IIC_SSE_CVT_PS_RM>, VEX;
1794 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 "cvtps2dq\t{$src, $dst|$dst, $src}",
1796 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1798 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1799 "cvtps2dq\t{$src, $dst|$dst, $src}",
1801 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1805 // Convert Packed Double FP to Packed DW Integers
1806 let Predicates = [HasAVX] in {
1807 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1808 // register, but the same isn't true when using memory operands instead.
1809 // Provide other assembly rr and rm forms to address this explicitly.
1810 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1811 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1812 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1816 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1817 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1818 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1819 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1821 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1824 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1825 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1827 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX;
1828 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1829 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1831 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1833 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1834 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1837 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1838 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1840 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1842 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1843 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1844 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1847 // Convert with truncation packed single/double fp to doubleword
1848 // SSE2 packed instructions with XS prefix
1849 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "cvttps2dq\t{$src, $dst|$dst, $src}",
1852 (int_x86_sse2_cvttps2dq VR128:$src))],
1853 IIC_SSE_CVT_PS_RR>, VEX;
1854 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1855 "cvttps2dq\t{$src, $dst|$dst, $src}",
1856 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1857 (memopv4f32 addr:$src)))],
1858 IIC_SSE_CVT_PS_RM>, VEX;
1859 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1860 "cvttps2dq\t{$src, $dst|$dst, $src}",
1862 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1863 IIC_SSE_CVT_PS_RR>, VEX;
1864 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1865 "cvttps2dq\t{$src, $dst|$dst, $src}",
1866 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1867 (memopv8f32 addr:$src)))],
1868 IIC_SSE_CVT_PS_RM>, VEX;
1870 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 "cvttps2dq\t{$src, $dst|$dst, $src}",
1872 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1874 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1875 "cvttps2dq\t{$src, $dst|$dst, $src}",
1877 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1880 let Predicates = [HasAVX] in {
1881 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1882 (VCVTDQ2PSrr VR128:$src)>;
1883 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1884 (VCVTDQ2PSrm addr:$src)>;
1886 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1887 (VCVTDQ2PSrr VR128:$src)>;
1888 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1889 (VCVTDQ2PSrm addr:$src)>;
1891 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1892 (VCVTTPS2DQrr VR128:$src)>;
1893 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1894 (VCVTTPS2DQrm addr:$src)>;
1896 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1897 (VCVTDQ2PSYrr VR256:$src)>;
1898 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1899 (VCVTDQ2PSYrm addr:$src)>;
1901 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1902 (VCVTTPS2DQYrr VR256:$src)>;
1903 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1904 (VCVTTPS2DQYrm addr:$src)>;
1907 let Predicates = [HasSSE2] in {
1908 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1909 (CVTDQ2PSrr VR128:$src)>;
1910 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1911 (CVTDQ2PSrm addr:$src)>;
1913 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1914 (CVTDQ2PSrr VR128:$src)>;
1915 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1916 (CVTDQ2PSrm addr:$src)>;
1918 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1919 (CVTTPS2DQrr VR128:$src)>;
1920 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1921 (CVTTPS2DQrm addr:$src)>;
1924 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1925 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1927 (int_x86_sse2_cvttpd2dq VR128:$src))],
1928 IIC_SSE_CVT_PD_RR>, VEX;
1930 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1931 // register, but the same isn't true when using memory operands instead.
1932 // Provide other assembly rr and rm forms to address this explicitly.
1935 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1936 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1937 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1938 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1939 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1940 (memopv2f64 addr:$src)))],
1941 IIC_SSE_CVT_PD_RM>, VEX;
1944 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1945 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1947 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1948 IIC_SSE_CVT_PD_RR>, VEX;
1949 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1950 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1952 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1953 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1954 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1955 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1957 let Predicates = [HasAVX] in {
1958 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1959 (VCVTTPD2DQYrr VR256:$src)>;
1960 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1961 (VCVTTPD2DQYrm addr:$src)>;
1962 } // Predicates = [HasAVX]
1964 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1965 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1966 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1968 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1969 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1970 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1971 (memopv2f64 addr:$src)))],
1974 // Convert packed single to packed double
1975 let Predicates = [HasAVX] in {
1976 // SSE2 instructions without OpSize prefix
1977 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1978 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1979 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
1980 IIC_SSE_CVT_PD_RR>, TB, VEX;
1981 let neverHasSideEffects = 1, mayLoad = 1 in
1982 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1983 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
1984 IIC_SSE_CVT_PD_RM>, TB, VEX;
1985 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1986 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1988 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
1989 IIC_SSE_CVT_PD_RR>, TB, VEX;
1990 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1991 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1993 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PD_RM>, TB, VEX;
1997 let Predicates = [HasSSE2] in {
1998 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1999 "cvtps2pd\t{$src, $dst|$dst, $src}",
2000 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2001 IIC_SSE_CVT_PD_RR>, TB;
2002 let neverHasSideEffects = 1, mayLoad = 1 in
2003 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2004 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2005 IIC_SSE_CVT_PD_RM>, TB;
2008 // Convert Packed DW Integers to Packed Double FP
2009 let Predicates = [HasAVX] in {
2010 let neverHasSideEffects = 1, mayLoad = 1 in
2011 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2012 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2014 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2015 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2017 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2018 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2019 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2021 (int_x86_avx_cvtdq2_pd_256
2022 (bitconvert (memopv2i64 addr:$src))))]>, VEX;
2023 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2024 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2026 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
2029 let neverHasSideEffects = 1, mayLoad = 1 in
2030 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2031 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2033 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2034 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2035 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2038 // AVX 256-bit register conversion intrinsics
2039 let Predicates = [HasAVX] in {
2040 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2041 (VCVTDQ2PDYrr VR128:$src)>;
2042 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2043 (VCVTDQ2PDYrm addr:$src)>;
2044 } // Predicates = [HasAVX]
2046 // Convert packed double to packed single
2047 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2048 // register, but the same isn't true when using memory operands instead.
2049 // Provide other assembly rr and rm forms to address this explicitly.
2050 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2051 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2052 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2053 IIC_SSE_CVT_PD_RR>, VEX;
2056 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2057 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2058 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2059 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2061 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2062 IIC_SSE_CVT_PD_RM>, VEX;
2065 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2066 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2068 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2069 IIC_SSE_CVT_PD_RR>, VEX;
2070 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2071 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2073 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2074 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2075 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2076 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2078 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2079 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2080 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2082 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2083 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2085 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2089 // AVX 256-bit register conversion intrinsics
2090 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2091 // whenever possible to avoid declaring two versions of each one.
2092 let Predicates = [HasAVX] in {
2093 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 // Match fround and fextend for 128/256-bit conversions
2099 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2100 (VCVTPD2PSYrr VR256:$src)>;
2101 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2102 (VCVTPD2PSYrm addr:$src)>;
2104 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2105 (VCVTPS2PDrr VR128:$src)>;
2106 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2107 (VCVTPS2PDYrr VR128:$src)>;
2108 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2109 (VCVTPS2PDYrm addr:$src)>;
2112 let Predicates = [HasSSE2] in {
2113 // Match fextend for 128 conversions
2114 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2115 (CVTPS2PDrr VR128:$src)>;
2118 //===----------------------------------------------------------------------===//
2119 // SSE 1 & 2 - Compare Instructions
2120 //===----------------------------------------------------------------------===//
2122 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2123 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2124 Operand CC, SDNode OpNode, ValueType VT,
2125 PatFrag ld_frag, string asm, string asm_alt,
2127 def rr : SIi8<0xC2, MRMSrcReg,
2128 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2129 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2131 def rm : SIi8<0xC2, MRMSrcMem,
2132 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2133 [(set RC:$dst, (OpNode (VT RC:$src1),
2134 (ld_frag addr:$src2), imm:$cc))],
2137 // Accept explicit immediate argument form instead of comparison code.
2138 let neverHasSideEffects = 1 in {
2139 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2140 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2141 IIC_SSE_ALU_F32S_RR>;
2143 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2144 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2145 IIC_SSE_ALU_F32S_RM>;
2149 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2150 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2151 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2153 XS, VEX_4V, VEX_LIG;
2154 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2155 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2156 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2157 SSE_ALU_F32S>, // same latency as 32 bit compare
2158 XD, VEX_4V, VEX_LIG;
2160 let Constraints = "$src1 = $dst" in {
2161 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2162 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2163 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2165 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2166 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2167 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2168 SSE_ALU_F32S>, // same latency as 32 bit compare
2172 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2173 Intrinsic Int, string asm, OpndItins itins> {
2174 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2175 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2176 [(set VR128:$dst, (Int VR128:$src1,
2177 VR128:$src, imm:$cc))],
2179 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2180 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2181 [(set VR128:$dst, (Int VR128:$src1,
2182 (load addr:$src), imm:$cc))],
2186 // Aliases to match intrinsics which expect XMM operand(s).
2187 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2188 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2191 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2192 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2193 SSE_ALU_F32S>, // same latency as f32
2195 let Constraints = "$src1 = $dst" in {
2196 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2197 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2199 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2200 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2201 SSE_ALU_F32S>, // same latency as f32
2206 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2207 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2208 ValueType vt, X86MemOperand x86memop,
2209 PatFrag ld_frag, string OpcodeStr, Domain d> {
2210 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2211 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2212 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2213 IIC_SSE_COMIS_RR, d>;
2214 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2215 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2216 [(set EFLAGS, (OpNode (vt RC:$src1),
2217 (ld_frag addr:$src2)))],
2218 IIC_SSE_COMIS_RM, d>;
2221 let Defs = [EFLAGS] in {
2222 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2223 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2224 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2225 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2227 let Pattern = []<dag> in {
2228 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2229 "comiss", SSEPackedSingle>, TB, VEX,
2231 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2232 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2236 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2237 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2238 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2239 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2241 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2242 load, "comiss", SSEPackedSingle>, TB, VEX;
2243 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2244 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2245 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2246 "ucomiss", SSEPackedSingle>, TB;
2247 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2248 "ucomisd", SSEPackedDouble>, TB, OpSize;
2250 let Pattern = []<dag> in {
2251 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2252 "comiss", SSEPackedSingle>, TB;
2253 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2254 "comisd", SSEPackedDouble>, TB, OpSize;
2257 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2258 load, "ucomiss", SSEPackedSingle>, TB;
2259 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2260 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2262 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2263 "comiss", SSEPackedSingle>, TB;
2264 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2265 "comisd", SSEPackedDouble>, TB, OpSize;
2266 } // Defs = [EFLAGS]
2268 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2269 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2270 Operand CC, Intrinsic Int, string asm,
2271 string asm_alt, Domain d> {
2272 def rri : PIi8<0xC2, MRMSrcReg,
2273 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2274 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2275 IIC_SSE_CMPP_RR, d>;
2276 def rmi : PIi8<0xC2, MRMSrcMem,
2277 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2278 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2279 IIC_SSE_CMPP_RM, d>;
2281 // Accept explicit immediate argument form instead of comparison code.
2282 let neverHasSideEffects = 1 in {
2283 def rri_alt : PIi8<0xC2, MRMSrcReg,
2284 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2285 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2286 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2287 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2288 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2292 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2293 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2294 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2295 SSEPackedSingle>, TB, VEX_4V;
2296 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2297 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2298 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2299 SSEPackedDouble>, TB, OpSize, VEX_4V;
2300 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2301 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2302 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2303 SSEPackedSingle>, TB, VEX_4V;
2304 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2305 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2306 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2307 SSEPackedDouble>, TB, OpSize, VEX_4V;
2308 let Constraints = "$src1 = $dst" in {
2309 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2310 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2311 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2312 SSEPackedSingle>, TB;
2313 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2314 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2315 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2316 SSEPackedDouble>, TB, OpSize;
2319 let Predicates = [HasAVX] in {
2320 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2321 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2322 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2323 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2324 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2325 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2326 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2327 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2329 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2330 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2331 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2332 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2333 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2334 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2335 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2336 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2339 let Predicates = [HasSSE1] in {
2340 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2341 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2342 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2343 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2346 let Predicates = [HasSSE2] in {
2347 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2348 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2349 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2350 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2353 //===----------------------------------------------------------------------===//
2354 // SSE 1 & 2 - Shuffle Instructions
2355 //===----------------------------------------------------------------------===//
2357 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2358 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2359 ValueType vt, string asm, PatFrag mem_frag,
2360 Domain d, bit IsConvertibleToThreeAddress = 0> {
2361 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2362 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2363 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2364 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2365 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2366 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2367 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2368 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2369 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2372 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2373 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2374 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2375 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2376 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2377 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2378 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2379 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2380 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2381 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2382 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2383 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2385 let Constraints = "$src1 = $dst" in {
2386 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2387 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2388 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2390 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2391 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2392 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2396 let Predicates = [HasAVX] in {
2397 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2398 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2399 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2400 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2401 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2403 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2404 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2405 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2406 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2407 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2410 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2411 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2412 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2413 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2414 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2416 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2417 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2418 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2419 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2420 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2423 let Predicates = [HasSSE1] in {
2424 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2425 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2426 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2427 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2428 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2431 let Predicates = [HasSSE2] in {
2432 // Generic SHUFPD patterns
2433 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2434 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2435 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2436 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2437 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2440 //===----------------------------------------------------------------------===//
2441 // SSE 1 & 2 - Unpack Instructions
2442 //===----------------------------------------------------------------------===//
2444 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2445 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2446 PatFrag mem_frag, RegisterClass RC,
2447 X86MemOperand x86memop, string asm,
2449 def rr : PI<opc, MRMSrcReg,
2450 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2452 (vt (OpNode RC:$src1, RC:$src2)))],
2454 def rm : PI<opc, MRMSrcMem,
2455 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2457 (vt (OpNode RC:$src1,
2458 (mem_frag addr:$src2))))],
2462 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2463 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 SSEPackedSingle>, TB, VEX_4V;
2465 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2466 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2467 SSEPackedDouble>, TB, OpSize, VEX_4V;
2468 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2469 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2470 SSEPackedSingle>, TB, VEX_4V;
2471 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2472 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2473 SSEPackedDouble>, TB, OpSize, VEX_4V;
2475 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2476 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2477 SSEPackedSingle>, TB, VEX_4V;
2478 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2479 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2480 SSEPackedDouble>, TB, OpSize, VEX_4V;
2481 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2482 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2483 SSEPackedSingle>, TB, VEX_4V;
2484 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2485 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2486 SSEPackedDouble>, TB, OpSize, VEX_4V;
2488 let Constraints = "$src1 = $dst" in {
2489 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2490 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2491 SSEPackedSingle>, TB;
2492 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2493 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2494 SSEPackedDouble>, TB, OpSize;
2495 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2496 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2497 SSEPackedSingle>, TB;
2498 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2499 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2500 SSEPackedDouble>, TB, OpSize;
2501 } // Constraints = "$src1 = $dst"
2503 let Predicates = [HasAVX], AddedComplexity = 1 in {
2504 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2505 // problem is during lowering, where it's not possible to recognize the load
2506 // fold cause it has two uses through a bitcast. One use disappears at isel
2507 // time and the fold opportunity reappears.
2508 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2509 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2512 let Predicates = [HasSSE2] in {
2513 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2514 // problem is during lowering, where it's not possible to recognize the load
2515 // fold cause it has two uses through a bitcast. One use disappears at isel
2516 // time and the fold opportunity reappears.
2517 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2518 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2521 //===----------------------------------------------------------------------===//
2522 // SSE 1 & 2 - Extract Floating-Point Sign mask
2523 //===----------------------------------------------------------------------===//
2525 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2526 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2528 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2529 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2530 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2531 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2532 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2533 IIC_SSE_MOVMSK, d>, REX_W;
2536 let Predicates = [HasAVX] in {
2537 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2538 "movmskps", SSEPackedSingle>, TB, VEX;
2539 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2540 "movmskpd", SSEPackedDouble>, TB,
2542 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2543 "movmskps", SSEPackedSingle>, TB, VEX;
2544 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2545 "movmskpd", SSEPackedDouble>, TB,
2548 def : Pat<(i32 (X86fgetsign FR32:$src)),
2549 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2550 def : Pat<(i64 (X86fgetsign FR32:$src)),
2551 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2552 def : Pat<(i32 (X86fgetsign FR64:$src)),
2553 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2554 def : Pat<(i64 (X86fgetsign FR64:$src)),
2555 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2558 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2559 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2560 SSEPackedSingle>, TB, VEX;
2561 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2562 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2563 SSEPackedDouble>, TB,
2565 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2566 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2567 SSEPackedSingle>, TB, VEX;
2568 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2569 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2570 SSEPackedDouble>, TB,
2574 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2575 SSEPackedSingle>, TB;
2576 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2577 SSEPackedDouble>, TB, OpSize;
2579 def : Pat<(i32 (X86fgetsign FR32:$src)),
2580 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2581 Requires<[HasSSE1]>;
2582 def : Pat<(i64 (X86fgetsign FR32:$src)),
2583 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2584 Requires<[HasSSE1]>;
2585 def : Pat<(i32 (X86fgetsign FR64:$src)),
2586 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2587 Requires<[HasSSE2]>;
2588 def : Pat<(i64 (X86fgetsign FR64:$src)),
2589 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2590 Requires<[HasSSE2]>;
2592 //===---------------------------------------------------------------------===//
2593 // SSE2 - Packed Integer Logical Instructions
2594 //===---------------------------------------------------------------------===//
2596 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2598 /// PDI_binop_rm - Simple SSE2 binary operator.
2599 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2600 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2601 X86MemOperand x86memop,
2603 bit IsCommutable = 0,
2605 let isCommutable = IsCommutable in
2606 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2607 (ins RC:$src1, RC:$src2),
2609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2611 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2612 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2613 (ins RC:$src1, x86memop:$src2),
2615 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2617 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2618 (bitconvert (memop_frag addr:$src2)))))],
2621 } // ExeDomain = SSEPackedInt
2623 // These are ordered here for pattern ordering requirements with the fp versions
2625 let Predicates = [HasAVX] in {
2626 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2627 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2628 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2629 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2630 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2631 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2632 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2633 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2636 let Constraints = "$src1 = $dst" in {
2637 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2638 i128mem, SSE_BIT_ITINS_P, 1>;
2639 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2640 i128mem, SSE_BIT_ITINS_P, 1>;
2641 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2642 i128mem, SSE_BIT_ITINS_P, 1>;
2643 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2644 i128mem, SSE_BIT_ITINS_P, 0>;
2645 } // Constraints = "$src1 = $dst"
2647 let Predicates = [HasAVX2] in {
2648 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2649 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2650 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2651 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2652 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2653 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2654 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2655 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2658 //===----------------------------------------------------------------------===//
2659 // SSE 1 & 2 - Logical Instructions
2660 //===----------------------------------------------------------------------===//
2662 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2664 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2665 SDNode OpNode, OpndItins itins> {
2666 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2667 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2670 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2671 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2674 let Constraints = "$src1 = $dst" in {
2675 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2676 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2679 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2680 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2685 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2686 let mayLoad = 0 in {
2687 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2689 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2691 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2695 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2696 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2699 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2701 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2703 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2704 // are all promoted to v2i64, and the patterns are covered by the int
2705 // version. This is needed in SSE only, because v2i64 isn't supported on
2706 // SSE1, but only on SSE2.
2707 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2708 !strconcat(OpcodeStr, "ps"), f128mem, [],
2709 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2710 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2712 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2713 !strconcat(OpcodeStr, "pd"), f128mem,
2714 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2715 (bc_v2i64 (v2f64 VR128:$src2))))],
2716 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2717 (memopv2i64 addr:$src2)))], 0>,
2719 let Constraints = "$src1 = $dst" in {
2720 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2721 !strconcat(OpcodeStr, "ps"), f128mem,
2722 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2723 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2724 (memopv2i64 addr:$src2)))]>, TB;
2726 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2727 !strconcat(OpcodeStr, "pd"), f128mem,
2728 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2729 (bc_v2i64 (v2f64 VR128:$src2))))],
2730 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2731 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2735 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2737 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2739 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2740 !strconcat(OpcodeStr, "ps"), f256mem,
2741 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2742 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2743 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2745 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2746 !strconcat(OpcodeStr, "pd"), f256mem,
2747 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2748 (bc_v4i64 (v4f64 VR256:$src2))))],
2749 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2750 (memopv4i64 addr:$src2)))], 0>,
2754 // AVX 256-bit packed logical ops forms
2755 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2756 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2757 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2758 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2760 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2761 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2762 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2763 let isCommutable = 0 in
2764 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2766 //===----------------------------------------------------------------------===//
2767 // SSE 1 & 2 - Arithmetic Instructions
2768 //===----------------------------------------------------------------------===//
2770 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2773 /// In addition, we also have a special variant of the scalar form here to
2774 /// represent the associated intrinsic operation. This form is unlike the
2775 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2776 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2778 /// These three forms can each be reg+reg or reg+mem.
2781 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2783 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2786 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2787 OpNode, FR32, f32mem,
2788 itins.s, Is2Addr>, XS;
2789 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2790 OpNode, FR64, f64mem,
2791 itins.d, Is2Addr>, XD;
2794 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2797 let mayLoad = 0 in {
2798 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2799 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2801 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2802 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2807 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2810 let mayLoad = 0 in {
2811 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2812 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2814 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2815 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2820 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2823 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2824 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2825 itins.s, Is2Addr>, XS;
2826 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2827 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2828 itins.d, Is2Addr>, XD;
2831 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2834 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2835 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2836 SSEPackedSingle, itins.s, Is2Addr>,
2839 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2840 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2841 SSEPackedDouble, itins.d, Is2Addr>,
2845 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2847 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2848 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2849 SSEPackedSingle, itins.s, 0>, TB;
2851 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2852 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2853 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2856 // Binary Arithmetic instructions
2857 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2858 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2860 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2861 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2863 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2864 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2866 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2867 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2870 let isCommutable = 0 in {
2871 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2872 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2874 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2875 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2877 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2878 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2880 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2881 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2883 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2884 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2886 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2887 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2888 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2889 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2891 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2892 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2894 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2895 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2896 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2897 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2901 let Constraints = "$src1 = $dst" in {
2902 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2903 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2904 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2905 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2906 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2907 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2909 let isCommutable = 0 in {
2910 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2911 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2912 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2913 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2914 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2915 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2916 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2917 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2918 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2919 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2920 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2921 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2922 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2923 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2927 let isCommutable = 1, isCodeGenOnly = 1 in {
2928 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2930 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2931 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2932 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2934 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2935 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2936 let Constraints = "$src1 = $dst" in {
2937 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2938 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2939 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2940 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2945 /// In addition, we also have a special variant of the scalar form here to
2946 /// represent the associated intrinsic operation. This form is unlike the
2947 /// plain scalar form, in that it takes an entire vector (instead of a
2948 /// scalar) and leaves the top elements undefined.
2950 /// And, we have a special variant form for a full-vector intrinsic form.
2952 def SSE_SQRTP : OpndItins<
2953 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2956 def SSE_SQRTS : OpndItins<
2957 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2960 def SSE_RCPP : OpndItins<
2961 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2964 def SSE_RCPS : OpndItins<
2965 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2968 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2969 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2970 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2971 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2972 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2973 [(set FR32:$dst, (OpNode FR32:$src))]>;
2974 // For scalar unary operations, fold a load into the operation
2975 // only in OptForSize mode. It eliminates an instruction, but it also
2976 // eliminates a whole-register clobber (the load), so it introduces a
2977 // partial register update condition.
2978 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2979 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2980 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
2981 Requires<[HasSSE1, OptForSize]>;
2982 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2983 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2984 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
2985 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2986 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2987 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
2990 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2991 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2992 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2993 !strconcat(OpcodeStr,
2994 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2996 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2997 !strconcat(OpcodeStr,
2998 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2999 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3000 (ins VR128:$src1, ssmem:$src2),
3001 !strconcat(OpcodeStr,
3002 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3005 /// sse1_fp_unop_p - SSE1 unops in packed form.
3006 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3008 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3009 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3010 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3011 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3012 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3013 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3016 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3017 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3019 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3020 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3021 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3023 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3024 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3025 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3029 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3030 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3031 Intrinsic V4F32Int, OpndItins itins> {
3032 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3033 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3034 [(set VR128:$dst, (V4F32Int VR128:$src))],
3036 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3037 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3038 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3042 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3043 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3044 Intrinsic V4F32Int, OpndItins itins> {
3045 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3046 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3047 [(set VR256:$dst, (V4F32Int VR256:$src))],
3049 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3050 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3051 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3055 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3056 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3057 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3058 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3059 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3060 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3061 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3062 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3063 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3064 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3065 Requires<[HasSSE2, OptForSize]>;
3066 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3067 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3068 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3069 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3070 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3071 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3074 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3075 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3076 let neverHasSideEffects = 1 in {
3077 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3078 !strconcat(OpcodeStr,
3079 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3081 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3082 !strconcat(OpcodeStr,
3083 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3085 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3086 (ins VR128:$src1, sdmem:$src2),
3087 !strconcat(OpcodeStr,
3088 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3091 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3092 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3093 SDNode OpNode, OpndItins itins> {
3094 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3095 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3096 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3097 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3098 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3099 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3102 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3103 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3105 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3106 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3107 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3109 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3110 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3111 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3115 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3116 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3117 Intrinsic V2F64Int, OpndItins itins> {
3118 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3119 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3120 [(set VR128:$dst, (V2F64Int VR128:$src))],
3122 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3123 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3124 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3128 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3129 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3130 Intrinsic V2F64Int, OpndItins itins> {
3131 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3132 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3133 [(set VR256:$dst, (V2F64Int VR256:$src))],
3135 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3137 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3141 let Predicates = [HasAVX] in {
3143 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3144 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3146 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3147 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3148 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3149 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3150 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3152 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3154 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3156 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3160 // Reciprocal approximations. Note that these typically require refinement
3161 // in order to obtain suitable precision.
3162 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3163 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3164 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3165 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3167 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3170 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3171 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3172 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3173 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3175 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3179 let AddedComplexity = 1 in {
3180 def : Pat<(f32 (fsqrt FR32:$src)),
3181 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3182 def : Pat<(f32 (fsqrt (load addr:$src))),
3183 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3184 Requires<[HasAVX, OptForSize]>;
3185 def : Pat<(f64 (fsqrt FR64:$src)),
3186 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3187 def : Pat<(f64 (fsqrt (load addr:$src))),
3188 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3189 Requires<[HasAVX, OptForSize]>;
3191 def : Pat<(f32 (X86frsqrt FR32:$src)),
3192 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3193 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3194 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3195 Requires<[HasAVX, OptForSize]>;
3197 def : Pat<(f32 (X86frcp FR32:$src)),
3198 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3199 def : Pat<(f32 (X86frcp (load addr:$src))),
3200 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3201 Requires<[HasAVX, OptForSize]>;
3204 let Predicates = [HasAVX], AddedComplexity = 1 in {
3205 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3206 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3207 (COPY_TO_REGCLASS VR128:$src, FR32)),
3209 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3210 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3212 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3213 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3214 (COPY_TO_REGCLASS VR128:$src, FR64)),
3216 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3217 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3219 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3220 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3221 (COPY_TO_REGCLASS VR128:$src, FR32)),
3223 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3224 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3226 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3227 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3228 (COPY_TO_REGCLASS VR128:$src, FR32)),
3230 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3231 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3235 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3237 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3238 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3239 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3241 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3242 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3244 // Reciprocal approximations. Note that these typically require refinement
3245 // in order to obtain suitable precision.
3246 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3248 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3249 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3251 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3253 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3254 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3256 // There is no f64 version of the reciprocal approximation instructions.
3258 //===----------------------------------------------------------------------===//
3259 // SSE 1 & 2 - Non-temporal stores
3260 //===----------------------------------------------------------------------===//
3262 let AddedComplexity = 400 in { // Prefer non-temporal versions
3263 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3264 (ins f128mem:$dst, VR128:$src),
3265 "movntps\t{$src, $dst|$dst, $src}",
3266 [(alignednontemporalstore (v4f32 VR128:$src),
3268 IIC_SSE_MOVNT>, VEX;
3269 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3270 (ins f128mem:$dst, VR128:$src),
3271 "movntpd\t{$src, $dst|$dst, $src}",
3272 [(alignednontemporalstore (v2f64 VR128:$src),
3274 IIC_SSE_MOVNT>, VEX;
3276 let ExeDomain = SSEPackedInt in
3277 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3278 (ins f128mem:$dst, VR128:$src),
3279 "movntdq\t{$src, $dst|$dst, $src}",
3280 [(alignednontemporalstore (v2i64 VR128:$src),
3282 IIC_SSE_MOVNT>, VEX;
3284 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3285 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3287 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3288 (ins f256mem:$dst, VR256:$src),
3289 "movntps\t{$src, $dst|$dst, $src}",
3290 [(alignednontemporalstore (v8f32 VR256:$src),
3292 IIC_SSE_MOVNT>, VEX;
3293 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3294 (ins f256mem:$dst, VR256:$src),
3295 "movntpd\t{$src, $dst|$dst, $src}",
3296 [(alignednontemporalstore (v4f64 VR256:$src),
3298 IIC_SSE_MOVNT>, VEX;
3299 let ExeDomain = SSEPackedInt in
3300 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3301 (ins f256mem:$dst, VR256:$src),
3302 "movntdq\t{$src, $dst|$dst, $src}",
3303 [(alignednontemporalstore (v4i64 VR256:$src),
3305 IIC_SSE_MOVNT>, VEX;
3308 let AddedComplexity = 400 in { // Prefer non-temporal versions
3309 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3310 "movntps\t{$src, $dst|$dst, $src}",
3311 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3313 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3314 "movntpd\t{$src, $dst|$dst, $src}",
3315 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3318 let ExeDomain = SSEPackedInt in
3319 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3320 "movntdq\t{$src, $dst|$dst, $src}",
3321 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3324 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3325 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3327 // There is no AVX form for instructions below this point
3328 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3329 "movnti{l}\t{$src, $dst|$dst, $src}",
3330 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3332 TB, Requires<[HasSSE2]>;
3333 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3334 "movnti{q}\t{$src, $dst|$dst, $src}",
3335 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3337 TB, Requires<[HasSSE2]>;
3340 //===----------------------------------------------------------------------===//
3341 // SSE 1 & 2 - Prefetch and memory fence
3342 //===----------------------------------------------------------------------===//
3344 // Prefetch intrinsic.
3345 let Predicates = [HasSSE1] in {
3346 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3347 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3348 IIC_SSE_PREFETCH>, TB;
3349 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3350 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3351 IIC_SSE_PREFETCH>, TB;
3352 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3353 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3354 IIC_SSE_PREFETCH>, TB;
3355 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3356 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3357 IIC_SSE_PREFETCH>, TB;
3361 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3362 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3363 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3365 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3366 // was introduced with SSE2, it's backward compatible.
3367 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3369 // Load, store, and memory fence
3370 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3371 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3372 TB, Requires<[HasSSE1]>;
3373 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3374 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3375 TB, Requires<[HasSSE2]>;
3376 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3377 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3378 TB, Requires<[HasSSE2]>;
3380 def : Pat<(X86SFence), (SFENCE)>;
3381 def : Pat<(X86LFence), (LFENCE)>;
3382 def : Pat<(X86MFence), (MFENCE)>;
3384 //===----------------------------------------------------------------------===//
3385 // SSE 1 & 2 - Load/Store XCSR register
3386 //===----------------------------------------------------------------------===//
3388 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3389 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3390 IIC_SSE_LDMXCSR>, VEX;
3391 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3392 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3393 IIC_SSE_STMXCSR>, VEX;
3395 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3396 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3398 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3399 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3402 //===---------------------------------------------------------------------===//
3403 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3404 //===---------------------------------------------------------------------===//
3406 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3408 let neverHasSideEffects = 1 in {
3409 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3410 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3412 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3413 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3416 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3417 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3419 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3420 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3424 let isCodeGenOnly = 1 in {
3425 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3426 "movdqa\t{$src, $dst|$dst, $src}", [],
3429 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3430 "movdqa\t{$src, $dst|$dst, $src}", [],
3433 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3434 "movdqu\t{$src, $dst|$dst, $src}", [],
3437 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3438 "movdqu\t{$src, $dst|$dst, $src}", [],
3443 let canFoldAsLoad = 1, mayLoad = 1 in {
3444 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3445 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3447 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3448 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3450 let Predicates = [HasAVX] in {
3451 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3452 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3454 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3455 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3460 let mayStore = 1 in {
3461 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3462 (ins i128mem:$dst, VR128:$src),
3463 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3465 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3466 (ins i256mem:$dst, VR256:$src),
3467 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3469 let Predicates = [HasAVX] in {
3470 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3471 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3473 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3474 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3479 let neverHasSideEffects = 1 in
3480 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3481 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3483 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3484 "movdqu\t{$src, $dst|$dst, $src}",
3485 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3488 let isCodeGenOnly = 1 in {
3489 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3490 "movdqa\t{$src, $dst|$dst, $src}", [],
3493 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3494 "movdqu\t{$src, $dst|$dst, $src}",
3495 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3498 let canFoldAsLoad = 1, mayLoad = 1 in {
3499 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3500 "movdqa\t{$src, $dst|$dst, $src}",
3501 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3503 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3504 "movdqu\t{$src, $dst|$dst, $src}",
3505 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3507 XS, Requires<[HasSSE2]>;
3510 let mayStore = 1 in {
3511 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3512 "movdqa\t{$src, $dst|$dst, $src}",
3513 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3515 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3516 "movdqu\t{$src, $dst|$dst, $src}",
3517 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3519 XS, Requires<[HasSSE2]>;
3522 // Intrinsic forms of MOVDQU load and store
3523 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3524 "vmovdqu\t{$src, $dst|$dst, $src}",
3525 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3527 XS, VEX, Requires<[HasAVX]>;
3529 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3530 "movdqu\t{$src, $dst|$dst, $src}",
3531 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3533 XS, Requires<[HasSSE2]>;
3535 } // ExeDomain = SSEPackedInt
3537 let Predicates = [HasAVX] in {
3538 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3539 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3542 //===---------------------------------------------------------------------===//
3543 // SSE2 - Packed Integer Arithmetic Instructions
3544 //===---------------------------------------------------------------------===//
3546 def SSE_PMADD : OpndItins<
3547 IIC_SSE_PMADD, IIC_SSE_PMADD
3550 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3552 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3553 RegisterClass RC, PatFrag memop_frag,
3554 X86MemOperand x86memop,
3556 bit IsCommutable = 0,
3558 let isCommutable = IsCommutable in
3559 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3560 (ins RC:$src1, RC:$src2),
3562 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3564 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3565 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3566 (ins RC:$src1, x86memop:$src2),
3568 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3569 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3570 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3574 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3575 string OpcodeStr, SDNode OpNode,
3576 SDNode OpNode2, RegisterClass RC,
3577 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3578 ShiftOpndItins itins,
3580 // src2 is always 128-bit
3581 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3582 (ins RC:$src1, VR128:$src2),
3584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3585 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3586 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3588 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3589 (ins RC:$src1, i128mem:$src2),
3591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3593 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3594 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3595 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3596 (ins RC:$src1, i32i8imm:$src2),
3598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3600 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3603 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3604 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3605 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3606 PatFrag memop_frag, X86MemOperand x86memop,
3608 bit IsCommutable = 0, bit Is2Addr = 1> {
3609 let isCommutable = IsCommutable in
3610 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3611 (ins RC:$src1, RC:$src2),
3613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3615 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3616 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3617 (ins RC:$src1, x86memop:$src2),
3619 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3620 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3621 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3622 (bitconvert (memop_frag addr:$src2)))))]>;
3624 } // ExeDomain = SSEPackedInt
3626 // 128-bit Integer Arithmetic
3628 let Predicates = [HasAVX] in {
3629 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3630 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3632 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3633 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3634 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3635 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3636 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3637 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3638 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3639 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3640 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3641 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3642 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3643 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3644 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3645 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3646 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3647 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3648 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3649 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3653 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3654 VR128, memopv2i64, i128mem,
3655 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3656 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3657 VR128, memopv2i64, i128mem,
3658 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3659 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3660 VR128, memopv2i64, i128mem,
3661 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3662 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3663 VR128, memopv2i64, i128mem,
3664 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3665 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3666 VR128, memopv2i64, i128mem,
3667 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3668 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3669 VR128, memopv2i64, i128mem,
3670 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3671 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3672 VR128, memopv2i64, i128mem,
3673 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3674 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3675 VR128, memopv2i64, i128mem,
3676 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3677 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3678 VR128, memopv2i64, i128mem,
3679 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3680 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3681 VR128, memopv2i64, i128mem,
3682 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3683 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3684 VR128, memopv2i64, i128mem,
3685 SSE_PMADD, 1, 0>, VEX_4V;
3686 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3687 VR128, memopv2i64, i128mem,
3688 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3689 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3690 VR128, memopv2i64, i128mem,
3691 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3692 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3693 VR128, memopv2i64, i128mem,
3694 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3695 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3696 VR128, memopv2i64, i128mem,
3697 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3698 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3699 VR128, memopv2i64, i128mem,
3700 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3701 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3702 VR128, memopv2i64, i128mem,
3703 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3704 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3705 VR128, memopv2i64, i128mem,
3706 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3709 let Predicates = [HasAVX2] in {
3710 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3711 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3712 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3713 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3714 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3715 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3716 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3717 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3718 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3719 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3720 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3721 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3722 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3723 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3724 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3725 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3726 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3727 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3728 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3729 VR256, memopv4i64, i256mem,
3730 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3733 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3734 VR256, memopv4i64, i256mem,
3735 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3736 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3737 VR256, memopv4i64, i256mem,
3738 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3739 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3740 VR256, memopv4i64, i256mem,
3741 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3742 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3743 VR256, memopv4i64, i256mem,
3744 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3745 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3746 VR256, memopv4i64, i256mem,
3747 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3748 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3749 VR256, memopv4i64, i256mem,
3750 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3751 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3752 VR256, memopv4i64, i256mem,
3753 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3754 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3755 VR256, memopv4i64, i256mem,
3756 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3757 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3758 VR256, memopv4i64, i256mem,
3759 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3760 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3761 VR256, memopv4i64, i256mem,
3762 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3763 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3764 VR256, memopv4i64, i256mem,
3765 SSE_PMADD, 1, 0>, VEX_4V;
3766 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3767 VR256, memopv4i64, i256mem,
3768 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3769 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3770 VR256, memopv4i64, i256mem,
3771 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3772 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3773 VR256, memopv4i64, i256mem,
3774 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3775 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3776 VR256, memopv4i64, i256mem,
3777 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3778 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3779 VR256, memopv4i64, i256mem,
3780 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3781 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3782 VR256, memopv4i64, i256mem,
3783 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3784 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3785 VR256, memopv4i64, i256mem,
3786 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3789 let Constraints = "$src1 = $dst" in {
3790 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3791 i128mem, SSE_INTALU_ITINS_P, 1>;
3792 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3793 i128mem, SSE_INTALU_ITINS_P, 1>;
3794 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3795 i128mem, SSE_INTALU_ITINS_P, 1>;
3796 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3797 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3798 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3799 i128mem, SSE_INTMUL_ITINS_P, 1>;
3800 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3801 i128mem, SSE_INTALU_ITINS_P>;
3802 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3803 i128mem, SSE_INTALU_ITINS_P>;
3804 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3805 i128mem, SSE_INTALU_ITINS_P>;
3806 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3807 i128mem, SSE_INTALUQ_ITINS_P>;
3808 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3809 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3812 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3813 VR128, memopv2i64, i128mem,
3814 SSE_INTALU_ITINS_P>;
3815 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3816 VR128, memopv2i64, i128mem,
3817 SSE_INTALU_ITINS_P>;
3818 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3819 VR128, memopv2i64, i128mem,
3820 SSE_INTALU_ITINS_P>;
3821 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3822 VR128, memopv2i64, i128mem,
3823 SSE_INTALU_ITINS_P>;
3824 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3825 VR128, memopv2i64, i128mem,
3826 SSE_INTALU_ITINS_P, 1>;
3827 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3828 VR128, memopv2i64, i128mem,
3829 SSE_INTALU_ITINS_P, 1>;
3830 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3831 VR128, memopv2i64, i128mem,
3832 SSE_INTALU_ITINS_P, 1>;
3833 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3834 VR128, memopv2i64, i128mem,
3835 SSE_INTALU_ITINS_P, 1>;
3836 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3837 VR128, memopv2i64, i128mem,
3838 SSE_INTMUL_ITINS_P, 1>;
3839 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3840 VR128, memopv2i64, i128mem,
3841 SSE_INTMUL_ITINS_P, 1>;
3842 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3843 VR128, memopv2i64, i128mem,
3845 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3846 VR128, memopv2i64, i128mem,
3847 SSE_INTALU_ITINS_P, 1>;
3848 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3849 VR128, memopv2i64, i128mem,
3850 SSE_INTALU_ITINS_P, 1>;
3851 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3852 VR128, memopv2i64, i128mem,
3853 SSE_INTALU_ITINS_P, 1>;
3854 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3855 VR128, memopv2i64, i128mem,
3856 SSE_INTALU_ITINS_P, 1>;
3857 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3858 VR128, memopv2i64, i128mem,
3859 SSE_INTALU_ITINS_P, 1>;
3860 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3861 VR128, memopv2i64, i128mem,
3862 SSE_INTALU_ITINS_P, 1>;
3863 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3864 VR128, memopv2i64, i128mem,
3865 SSE_INTALU_ITINS_P, 1>;
3867 } // Constraints = "$src1 = $dst"
3869 //===---------------------------------------------------------------------===//
3870 // SSE2 - Packed Integer Logical Instructions
3871 //===---------------------------------------------------------------------===//
3873 let Predicates = [HasAVX] in {
3874 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3875 VR128, v8i16, v8i16, bc_v8i16,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3877 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3878 VR128, v4i32, v4i32, bc_v4i32,
3879 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3880 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3881 VR128, v2i64, v2i64, bc_v2i64,
3882 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3885 VR128, v8i16, v8i16, bc_v8i16,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3888 VR128, v4i32, v4i32, bc_v4i32,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3890 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3891 VR128, v2i64, v2i64, bc_v2i64,
3892 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3894 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3895 VR128, v8i16, v8i16, bc_v8i16,
3896 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3897 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3898 VR128, v4i32, v4i32, bc_v4i32,
3899 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3901 let ExeDomain = SSEPackedInt in {
3902 // 128-bit logical shifts.
3903 def VPSLLDQri : PDIi8<0x73, MRM7r,
3904 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3905 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3907 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3909 def VPSRLDQri : PDIi8<0x73, MRM3r,
3910 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3911 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3913 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3915 // PSRADQri doesn't exist in SSE[1-3].
3917 } // Predicates = [HasAVX]
3919 let Predicates = [HasAVX2] in {
3920 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3921 VR256, v16i16, v8i16, bc_v8i16,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3923 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3924 VR256, v8i32, v4i32, bc_v4i32,
3925 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3926 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3927 VR256, v4i64, v2i64, bc_v2i64,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3930 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3931 VR256, v16i16, v8i16, bc_v8i16,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3933 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3934 VR256, v8i32, v4i32, bc_v4i32,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3936 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3937 VR256, v4i64, v2i64, bc_v2i64,
3938 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3940 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3941 VR256, v16i16, v8i16, bc_v8i16,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3943 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3944 VR256, v8i32, v4i32, bc_v4i32,
3945 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3947 let ExeDomain = SSEPackedInt in {
3948 // 256-bit logical shifts.
3949 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3950 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3951 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3955 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3956 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3957 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3959 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3961 // PSRADQYri doesn't exist in SSE[1-3].
3963 } // Predicates = [HasAVX2]
3965 let Constraints = "$src1 = $dst" in {
3966 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3967 VR128, v8i16, v8i16, bc_v8i16,
3968 SSE_INTSHIFT_ITINS_P>;
3969 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3970 VR128, v4i32, v4i32, bc_v4i32,
3971 SSE_INTSHIFT_ITINS_P>;
3972 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3973 VR128, v2i64, v2i64, bc_v2i64,
3974 SSE_INTSHIFT_ITINS_P>;
3976 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3977 VR128, v8i16, v8i16, bc_v8i16,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3980 VR128, v4i32, v4i32, bc_v4i32,
3981 SSE_INTSHIFT_ITINS_P>;
3982 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3983 VR128, v2i64, v2i64, bc_v2i64,
3984 SSE_INTSHIFT_ITINS_P>;
3986 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3987 VR128, v8i16, v8i16, bc_v8i16,
3988 SSE_INTSHIFT_ITINS_P>;
3989 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3990 VR128, v4i32, v4i32, bc_v4i32,
3991 SSE_INTSHIFT_ITINS_P>;
3993 let ExeDomain = SSEPackedInt in {
3994 // 128-bit logical shifts.
3995 def PSLLDQri : PDIi8<0x73, MRM7r,
3996 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3997 "pslldq\t{$src2, $dst|$dst, $src2}",
3999 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4000 def PSRLDQri : PDIi8<0x73, MRM3r,
4001 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4002 "psrldq\t{$src2, $dst|$dst, $src2}",
4004 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4005 // PSRADQri doesn't exist in SSE[1-3].
4007 } // Constraints = "$src1 = $dst"
4009 let Predicates = [HasAVX] in {
4010 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4011 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4012 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4013 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4014 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4015 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4017 // Shift up / down and insert zero's.
4018 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4019 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4020 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4021 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4024 let Predicates = [HasAVX2] in {
4025 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4026 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4027 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4028 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4031 let Predicates = [HasSSE2] in {
4032 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4033 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4034 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4035 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4036 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4037 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4039 // Shift up / down and insert zero's.
4040 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4041 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4042 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4043 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4046 //===---------------------------------------------------------------------===//
4047 // SSE2 - Packed Integer Comparison Instructions
4048 //===---------------------------------------------------------------------===//
4050 let Predicates = [HasAVX] in {
4051 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4052 VR128, memopv2i64, i128mem,
4053 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4054 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4055 VR128, memopv2i64, i128mem,
4056 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4057 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4058 VR128, memopv2i64, i128mem,
4059 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4060 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4061 VR128, memopv2i64, i128mem,
4062 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4063 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4064 VR128, memopv2i64, i128mem,
4065 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4066 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4067 VR128, memopv2i64, i128mem,
4068 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4071 let Predicates = [HasAVX2] in {
4072 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4073 VR256, memopv4i64, i256mem,
4074 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4075 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4076 VR256, memopv4i64, i256mem,
4077 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4078 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4079 VR256, memopv4i64, i256mem,
4080 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4081 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4082 VR256, memopv4i64, i256mem,
4083 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4084 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4085 VR256, memopv4i64, i256mem,
4086 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4087 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4088 VR256, memopv4i64, i256mem,
4089 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4092 let Constraints = "$src1 = $dst" in {
4093 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4094 VR128, memopv2i64, i128mem,
4095 SSE_INTALU_ITINS_P, 1>;
4096 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4097 VR128, memopv2i64, i128mem,
4098 SSE_INTALU_ITINS_P, 1>;
4099 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4100 VR128, memopv2i64, i128mem,
4101 SSE_INTALU_ITINS_P, 1>;
4102 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4103 VR128, memopv2i64, i128mem,
4104 SSE_INTALU_ITINS_P>;
4105 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4106 VR128, memopv2i64, i128mem,
4107 SSE_INTALU_ITINS_P>;
4108 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4109 VR128, memopv2i64, i128mem,
4110 SSE_INTALU_ITINS_P>;
4111 } // Constraints = "$src1 = $dst"
4113 //===---------------------------------------------------------------------===//
4114 // SSE2 - Packed Integer Pack Instructions
4115 //===---------------------------------------------------------------------===//
4117 let Predicates = [HasAVX] in {
4118 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4119 VR128, memopv2i64, i128mem,
4120 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4121 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4122 VR128, memopv2i64, i128mem,
4123 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4124 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4125 VR128, memopv2i64, i128mem,
4126 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4129 let Predicates = [HasAVX2] in {
4130 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4131 VR256, memopv4i64, i256mem,
4132 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4133 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4134 VR256, memopv4i64, i256mem,
4135 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4136 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4137 VR256, memopv4i64, i256mem,
4138 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4141 let Constraints = "$src1 = $dst" in {
4142 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4143 VR128, memopv2i64, i128mem,
4144 SSE_INTALU_ITINS_P>;
4145 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4146 VR128, memopv2i64, i128mem,
4147 SSE_INTALU_ITINS_P>;
4148 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4149 VR128, memopv2i64, i128mem,
4150 SSE_INTALU_ITINS_P>;
4151 } // Constraints = "$src1 = $dst"
4153 //===---------------------------------------------------------------------===//
4154 // SSE2 - Packed Integer Shuffle Instructions
4155 //===---------------------------------------------------------------------===//
4157 let ExeDomain = SSEPackedInt in {
4158 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4159 def ri : Ii8<0x70, MRMSrcReg,
4160 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4161 !strconcat(OpcodeStr,
4162 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4163 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4165 def mi : Ii8<0x70, MRMSrcMem,
4166 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4167 !strconcat(OpcodeStr,
4168 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4170 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4175 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4176 def Yri : Ii8<0x70, MRMSrcReg,
4177 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4178 !strconcat(OpcodeStr,
4179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4180 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4181 def Ymi : Ii8<0x70, MRMSrcMem,
4182 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4183 !strconcat(OpcodeStr,
4184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4186 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4187 (i8 imm:$src2))))]>;
4189 } // ExeDomain = SSEPackedInt
4191 let Predicates = [HasAVX] in {
4192 let AddedComplexity = 5 in
4193 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4195 // SSE2 with ImmT == Imm8 and XS prefix.
4196 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4198 // SSE2 with ImmT == Imm8 and XD prefix.
4199 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4201 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4202 (VPSHUFDmi addr:$src1, imm:$imm)>;
4203 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4204 (VPSHUFDri VR128:$src1, imm:$imm)>;
4207 let Predicates = [HasAVX2] in {
4208 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4209 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4210 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4213 let Predicates = [HasSSE2] in {
4214 let AddedComplexity = 5 in
4215 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4217 // SSE2 with ImmT == Imm8 and XS prefix.
4218 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4220 // SSE2 with ImmT == Imm8 and XD prefix.
4221 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4223 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4224 (PSHUFDmi addr:$src1, imm:$imm)>;
4225 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4226 (PSHUFDri VR128:$src1, imm:$imm)>;
4229 //===---------------------------------------------------------------------===//
4230 // SSE2 - Packed Integer Unpack Instructions
4231 //===---------------------------------------------------------------------===//
4233 let ExeDomain = SSEPackedInt in {
4234 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4235 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4236 def rr : PDI<opc, MRMSrcReg,
4237 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4239 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4240 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4241 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4243 def rm : PDI<opc, MRMSrcMem,
4244 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4246 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4247 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4248 [(set VR128:$dst, (OpNode VR128:$src1,
4249 (bc_frag (memopv2i64
4254 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4255 SDNode OpNode, PatFrag bc_frag> {
4256 def Yrr : PDI<opc, MRMSrcReg,
4257 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4258 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4259 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4260 def Yrm : PDI<opc, MRMSrcMem,
4261 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4262 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4263 [(set VR256:$dst, (OpNode VR256:$src1,
4264 (bc_frag (memopv4i64 addr:$src2))))]>;
4267 let Predicates = [HasAVX] in {
4268 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4269 bc_v16i8, 0>, VEX_4V;
4270 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4271 bc_v8i16, 0>, VEX_4V;
4272 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4273 bc_v4i32, 0>, VEX_4V;
4274 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4275 bc_v2i64, 0>, VEX_4V;
4277 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4278 bc_v16i8, 0>, VEX_4V;
4279 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4280 bc_v8i16, 0>, VEX_4V;
4281 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4282 bc_v4i32, 0>, VEX_4V;
4283 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4284 bc_v2i64, 0>, VEX_4V;
4287 let Predicates = [HasAVX2] in {
4288 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4290 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4292 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4294 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4297 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4299 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4301 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4303 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4307 let Constraints = "$src1 = $dst" in {
4308 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4310 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4312 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4314 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4317 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4319 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4321 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4323 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4326 } // ExeDomain = SSEPackedInt
4328 // Patterns for using AVX1 instructions with integer vectors
4329 // Here to give AVX2 priority
4330 let Predicates = [HasAVX] in {
4331 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4332 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4333 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4334 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4335 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4336 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4337 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4338 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4340 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4341 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4342 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4343 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4344 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4345 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4346 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4347 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4350 //===---------------------------------------------------------------------===//
4351 // SSE2 - Packed Integer Extract and Insert
4352 //===---------------------------------------------------------------------===//
4354 let ExeDomain = SSEPackedInt in {
4355 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4356 def rri : Ii8<0xC4, MRMSrcReg,
4357 (outs VR128:$dst), (ins VR128:$src1,
4358 GR32:$src2, i32i8imm:$src3),
4360 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4361 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4363 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4364 def rmi : Ii8<0xC4, MRMSrcMem,
4365 (outs VR128:$dst), (ins VR128:$src1,
4366 i16mem:$src2, i32i8imm:$src3),
4368 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4369 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4371 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4372 imm:$src3))], IIC_SSE_PINSRW>;
4376 let Predicates = [HasAVX] in
4377 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4378 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4379 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4380 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4381 imm:$src2))]>, TB, OpSize, VEX;
4382 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4383 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4384 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4385 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4386 imm:$src2))], IIC_SSE_PEXTRW>;
4389 let Predicates = [HasAVX] in {
4390 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4391 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4392 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4393 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4394 []>, TB, OpSize, VEX_4V;
4397 let Constraints = "$src1 = $dst" in
4398 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4400 } // ExeDomain = SSEPackedInt
4402 //===---------------------------------------------------------------------===//
4403 // SSE2 - Packed Mask Creation
4404 //===---------------------------------------------------------------------===//
4406 let ExeDomain = SSEPackedInt in {
4408 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4409 "pmovmskb\t{$src, $dst|$dst, $src}",
4410 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4411 IIC_SSE_MOVMSK>, VEX;
4412 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4413 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4415 let Predicates = [HasAVX2] in {
4416 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4417 "pmovmskb\t{$src, $dst|$dst, $src}",
4418 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4419 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4420 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4423 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4424 "pmovmskb\t{$src, $dst|$dst, $src}",
4425 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4428 } // ExeDomain = SSEPackedInt
4430 //===---------------------------------------------------------------------===//
4431 // SSE2 - Conditional Store
4432 //===---------------------------------------------------------------------===//
4434 let ExeDomain = SSEPackedInt in {
4437 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4438 (ins VR128:$src, VR128:$mask),
4439 "maskmovdqu\t{$mask, $src|$src, $mask}",
4440 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4441 IIC_SSE_MASKMOV>, VEX;
4443 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4444 (ins VR128:$src, VR128:$mask),
4445 "maskmovdqu\t{$mask, $src|$src, $mask}",
4446 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4447 IIC_SSE_MASKMOV>, VEX;
4450 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4451 "maskmovdqu\t{$mask, $src|$src, $mask}",
4452 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4455 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4456 "maskmovdqu\t{$mask, $src|$src, $mask}",
4457 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4460 } // ExeDomain = SSEPackedInt
4462 //===---------------------------------------------------------------------===//
4463 // SSE2 - Move Doubleword
4464 //===---------------------------------------------------------------------===//
4466 //===---------------------------------------------------------------------===//
4467 // Move Int Doubleword to Packed Double Int
4469 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4470 "movd\t{$src, $dst|$dst, $src}",
4472 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4474 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4475 "movd\t{$src, $dst|$dst, $src}",
4477 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4480 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4481 "mov{d|q}\t{$src, $dst|$dst, $src}",
4483 (v2i64 (scalar_to_vector GR64:$src)))],
4484 IIC_SSE_MOVDQ>, VEX;
4485 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4486 "mov{d|q}\t{$src, $dst|$dst, $src}",
4487 [(set FR64:$dst, (bitconvert GR64:$src))],
4488 IIC_SSE_MOVDQ>, VEX;
4490 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4491 "movd\t{$src, $dst|$dst, $src}",
4493 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4494 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4495 "movd\t{$src, $dst|$dst, $src}",
4497 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4499 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4500 "mov{d|q}\t{$src, $dst|$dst, $src}",
4502 (v2i64 (scalar_to_vector GR64:$src)))],
4504 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4505 "mov{d|q}\t{$src, $dst|$dst, $src}",
4506 [(set FR64:$dst, (bitconvert GR64:$src))],
4509 //===---------------------------------------------------------------------===//
4510 // Move Int Doubleword to Single Scalar
4512 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4513 "movd\t{$src, $dst|$dst, $src}",
4514 [(set FR32:$dst, (bitconvert GR32:$src))],
4515 IIC_SSE_MOVDQ>, VEX;
4517 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4518 "movd\t{$src, $dst|$dst, $src}",
4519 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4522 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4523 "movd\t{$src, $dst|$dst, $src}",
4524 [(set FR32:$dst, (bitconvert GR32:$src))],
4527 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4528 "movd\t{$src, $dst|$dst, $src}",
4529 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4532 //===---------------------------------------------------------------------===//
4533 // Move Packed Doubleword Int to Packed Double Int
4535 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4536 "movd\t{$src, $dst|$dst, $src}",
4537 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4538 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4539 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4540 (ins i32mem:$dst, VR128:$src),
4541 "movd\t{$src, $dst|$dst, $src}",
4542 [(store (i32 (vector_extract (v4i32 VR128:$src),
4543 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4545 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4546 "movd\t{$src, $dst|$dst, $src}",
4547 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4548 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4549 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4550 "movd\t{$src, $dst|$dst, $src}",
4551 [(store (i32 (vector_extract (v4i32 VR128:$src),
4552 (iPTR 0))), addr:$dst)],
4555 //===---------------------------------------------------------------------===//
4556 // Move Packed Doubleword Int first element to Doubleword Int
4558 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4559 "mov{d|q}\t{$src, $dst|$dst, $src}",
4560 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4563 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4565 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4566 "mov{d|q}\t{$src, $dst|$dst, $src}",
4567 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4571 //===---------------------------------------------------------------------===//
4572 // Bitcast FR64 <-> GR64
4574 let Predicates = [HasAVX] in
4575 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4576 "vmovq\t{$src, $dst|$dst, $src}",
4577 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4579 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4580 "mov{d|q}\t{$src, $dst|$dst, $src}",
4581 [(set GR64:$dst, (bitconvert FR64:$src))],
4582 IIC_SSE_MOVDQ>, VEX;
4583 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4584 "movq\t{$src, $dst|$dst, $src}",
4585 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4586 IIC_SSE_MOVDQ>, VEX;
4588 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4589 "movq\t{$src, $dst|$dst, $src}",
4590 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4592 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4593 "mov{d|q}\t{$src, $dst|$dst, $src}",
4594 [(set GR64:$dst, (bitconvert FR64:$src))],
4596 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4597 "movq\t{$src, $dst|$dst, $src}",
4598 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4601 //===---------------------------------------------------------------------===//
4602 // Move Scalar Single to Double Int
4604 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4605 "movd\t{$src, $dst|$dst, $src}",
4606 [(set GR32:$dst, (bitconvert FR32:$src))],
4607 IIC_SSE_MOVD_ToGP>, VEX;
4608 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4609 "movd\t{$src, $dst|$dst, $src}",
4610 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4611 IIC_SSE_MOVDQ>, VEX;
4612 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4613 "movd\t{$src, $dst|$dst, $src}",
4614 [(set GR32:$dst, (bitconvert FR32:$src))],
4616 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4617 "movd\t{$src, $dst|$dst, $src}",
4618 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4621 //===---------------------------------------------------------------------===//
4622 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4624 let AddedComplexity = 15 in {
4625 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4626 "movd\t{$src, $dst|$dst, $src}",
4627 [(set VR128:$dst, (v4i32 (X86vzmovl
4628 (v4i32 (scalar_to_vector GR32:$src)))))],
4629 IIC_SSE_MOVDQ>, VEX;
4630 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4631 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4632 [(set VR128:$dst, (v2i64 (X86vzmovl
4633 (v2i64 (scalar_to_vector GR64:$src)))))],
4637 let AddedComplexity = 15 in {
4638 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4639 "movd\t{$src, $dst|$dst, $src}",
4640 [(set VR128:$dst, (v4i32 (X86vzmovl
4641 (v4i32 (scalar_to_vector GR32:$src)))))],
4643 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4644 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4645 [(set VR128:$dst, (v2i64 (X86vzmovl
4646 (v2i64 (scalar_to_vector GR64:$src)))))],
4650 let AddedComplexity = 20 in {
4651 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4652 "movd\t{$src, $dst|$dst, $src}",
4654 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4655 (loadi32 addr:$src))))))],
4656 IIC_SSE_MOVDQ>, VEX;
4657 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4658 "movd\t{$src, $dst|$dst, $src}",
4660 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4661 (loadi32 addr:$src))))))],
4665 let Predicates = [HasAVX] in {
4666 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4667 let AddedComplexity = 20 in {
4668 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4669 (VMOVZDI2PDIrm addr:$src)>;
4670 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4671 (VMOVZDI2PDIrm addr:$src)>;
4673 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4674 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4675 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4676 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4677 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4678 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4679 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4682 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4683 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4684 (MOVZDI2PDIrm addr:$src)>;
4685 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4686 (MOVZDI2PDIrm addr:$src)>;
4689 // These are the correct encodings of the instructions so that we know how to
4690 // read correct assembly, even though we continue to emit the wrong ones for
4691 // compatibility with Darwin's buggy assembler.
4692 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4693 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4694 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4695 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4696 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4697 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4698 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4699 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4700 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4701 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4702 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4703 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4705 //===---------------------------------------------------------------------===//
4706 // SSE2 - Move Quadword
4707 //===---------------------------------------------------------------------===//
4709 //===---------------------------------------------------------------------===//
4710 // Move Quadword Int to Packed Quadword Int
4712 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4713 "vmovq\t{$src, $dst|$dst, $src}",
4715 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4716 VEX, Requires<[HasAVX]>;
4717 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4718 "movq\t{$src, $dst|$dst, $src}",
4720 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4722 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4724 //===---------------------------------------------------------------------===//
4725 // Move Packed Quadword Int to Quadword Int
4727 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4728 "movq\t{$src, $dst|$dst, $src}",
4729 [(store (i64 (vector_extract (v2i64 VR128:$src),
4730 (iPTR 0))), addr:$dst)],
4731 IIC_SSE_MOVDQ>, VEX;
4732 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4733 "movq\t{$src, $dst|$dst, $src}",
4734 [(store (i64 (vector_extract (v2i64 VR128:$src),
4735 (iPTR 0))), addr:$dst)],
4738 //===---------------------------------------------------------------------===//
4739 // Store / copy lower 64-bits of a XMM register.
4741 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4742 "movq\t{$src, $dst|$dst, $src}",
4743 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4744 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4745 "movq\t{$src, $dst|$dst, $src}",
4746 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4749 let AddedComplexity = 20 in
4750 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4751 "vmovq\t{$src, $dst|$dst, $src}",
4753 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4754 (loadi64 addr:$src))))))],
4756 XS, VEX, Requires<[HasAVX]>;
4758 let AddedComplexity = 20 in
4759 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4760 "movq\t{$src, $dst|$dst, $src}",
4762 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4763 (loadi64 addr:$src))))))],
4765 XS, Requires<[HasSSE2]>;
4767 let Predicates = [HasAVX], AddedComplexity = 20 in {
4768 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4769 (VMOVZQI2PQIrm addr:$src)>;
4770 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4771 (VMOVZQI2PQIrm addr:$src)>;
4772 def : Pat<(v2i64 (X86vzload addr:$src)),
4773 (VMOVZQI2PQIrm addr:$src)>;
4776 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4777 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4778 (MOVZQI2PQIrm addr:$src)>;
4779 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4780 (MOVZQI2PQIrm addr:$src)>;
4781 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4784 let Predicates = [HasAVX] in {
4785 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4786 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4787 def : Pat<(v4i64 (X86vzload addr:$src)),
4788 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4791 //===---------------------------------------------------------------------===//
4792 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4793 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4795 let AddedComplexity = 15 in
4796 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4797 "vmovq\t{$src, $dst|$dst, $src}",
4798 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4800 XS, VEX, Requires<[HasAVX]>;
4801 let AddedComplexity = 15 in
4802 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4803 "movq\t{$src, $dst|$dst, $src}",
4804 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4806 XS, Requires<[HasSSE2]>;
4808 let AddedComplexity = 20 in
4809 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4810 "vmovq\t{$src, $dst|$dst, $src}",
4811 [(set VR128:$dst, (v2i64 (X86vzmovl
4812 (loadv2i64 addr:$src))))],
4814 XS, VEX, Requires<[HasAVX]>;
4815 let AddedComplexity = 20 in {
4816 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4817 "movq\t{$src, $dst|$dst, $src}",
4818 [(set VR128:$dst, (v2i64 (X86vzmovl
4819 (loadv2i64 addr:$src))))],
4821 XS, Requires<[HasSSE2]>;
4824 let AddedComplexity = 20 in {
4825 let Predicates = [HasAVX] in {
4826 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4827 (VMOVZPQILo2PQIrm addr:$src)>;
4828 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4829 (VMOVZPQILo2PQIrr VR128:$src)>;
4831 let Predicates = [HasSSE2] in {
4832 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4833 (MOVZPQILo2PQIrm addr:$src)>;
4834 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4835 (MOVZPQILo2PQIrr VR128:$src)>;
4839 // Instructions to match in the assembler
4840 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4841 "movq\t{$src, $dst|$dst, $src}", [],
4842 IIC_SSE_MOVDQ>, VEX, VEX_W;
4843 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4844 "movq\t{$src, $dst|$dst, $src}", [],
4845 IIC_SSE_MOVDQ>, VEX, VEX_W;
4846 // Recognize "movd" with GR64 destination, but encode as a "movq"
4847 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4848 "movd\t{$src, $dst|$dst, $src}", [],
4849 IIC_SSE_MOVDQ>, VEX, VEX_W;
4851 // Instructions for the disassembler
4852 // xr = XMM register
4855 let Predicates = [HasAVX] in
4856 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4857 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4858 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4859 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4861 //===---------------------------------------------------------------------===//
4862 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4863 //===---------------------------------------------------------------------===//
4864 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4865 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4866 X86MemOperand x86memop> {
4867 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4868 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4869 [(set RC:$dst, (vt (OpNode RC:$src)))],
4871 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4872 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4873 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4877 let Predicates = [HasAVX] in {
4878 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4879 v4f32, VR128, memopv4f32, f128mem>, VEX;
4880 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4881 v4f32, VR128, memopv4f32, f128mem>, VEX;
4882 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4883 v8f32, VR256, memopv8f32, f256mem>, VEX;
4884 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4885 v8f32, VR256, memopv8f32, f256mem>, VEX;
4887 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4888 memopv4f32, f128mem>;
4889 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4890 memopv4f32, f128mem>;
4892 let Predicates = [HasAVX] in {
4893 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4894 (VMOVSHDUPrr VR128:$src)>;
4895 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4896 (VMOVSHDUPrm addr:$src)>;
4897 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4898 (VMOVSLDUPrr VR128:$src)>;
4899 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4900 (VMOVSLDUPrm addr:$src)>;
4901 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4902 (VMOVSHDUPYrr VR256:$src)>;
4903 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4904 (VMOVSHDUPYrm addr:$src)>;
4905 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4906 (VMOVSLDUPYrr VR256:$src)>;
4907 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4908 (VMOVSLDUPYrm addr:$src)>;
4911 let Predicates = [HasSSE3] in {
4912 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4913 (MOVSHDUPrr VR128:$src)>;
4914 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4915 (MOVSHDUPrm addr:$src)>;
4916 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4917 (MOVSLDUPrr VR128:$src)>;
4918 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4919 (MOVSLDUPrm addr:$src)>;
4922 //===---------------------------------------------------------------------===//
4923 // SSE3 - Replicate Double FP - MOVDDUP
4924 //===---------------------------------------------------------------------===//
4926 multiclass sse3_replicate_dfp<string OpcodeStr> {
4927 let neverHasSideEffects = 1 in
4928 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4929 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4930 [], IIC_SSE_MOV_LH>;
4931 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4935 (scalar_to_vector (loadf64 addr:$src)))))],
4939 // FIXME: Merge with above classe when there're patterns for the ymm version
4940 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4941 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4943 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4944 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4945 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4948 (scalar_to_vector (loadf64 addr:$src)))))]>;
4951 let Predicates = [HasAVX] in {
4952 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4953 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4956 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4958 let Predicates = [HasAVX] in {
4959 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4960 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4961 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4962 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4963 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4964 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4965 def : Pat<(X86Movddup (bc_v2f64
4966 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4967 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4970 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4971 (VMOVDDUPYrm addr:$src)>;
4972 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4973 (VMOVDDUPYrm addr:$src)>;
4974 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4975 (VMOVDDUPYrm addr:$src)>;
4976 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4977 (VMOVDDUPYrr VR256:$src)>;
4980 let Predicates = [HasSSE3] in {
4981 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4982 (MOVDDUPrm addr:$src)>;
4983 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4984 (MOVDDUPrm addr:$src)>;
4985 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4986 (MOVDDUPrm addr:$src)>;
4987 def : Pat<(X86Movddup (bc_v2f64
4988 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4989 (MOVDDUPrm addr:$src)>;
4992 //===---------------------------------------------------------------------===//
4993 // SSE3 - Move Unaligned Integer
4994 //===---------------------------------------------------------------------===//
4996 let Predicates = [HasAVX] in {
4997 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4998 "vlddqu\t{$src, $dst|$dst, $src}",
4999 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5000 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5001 "vlddqu\t{$src, $dst|$dst, $src}",
5002 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5004 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5005 "lddqu\t{$src, $dst|$dst, $src}",
5006 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5009 //===---------------------------------------------------------------------===//
5010 // SSE3 - Arithmetic
5011 //===---------------------------------------------------------------------===//
5013 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5014 X86MemOperand x86memop, OpndItins itins,
5016 def rr : I<0xD0, MRMSrcReg,
5017 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5019 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5021 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5022 def rm : I<0xD0, MRMSrcMem,
5023 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5025 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5027 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5030 let Predicates = [HasAVX] in {
5031 let ExeDomain = SSEPackedSingle in {
5032 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5033 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5034 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5035 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5037 let ExeDomain = SSEPackedDouble in {
5038 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5039 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5040 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5041 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5044 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5045 let ExeDomain = SSEPackedSingle in
5046 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5047 f128mem, SSE_ALU_F32P>, TB, XD;
5048 let ExeDomain = SSEPackedDouble in
5049 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5050 f128mem, SSE_ALU_F64P>, TB, OpSize;
5053 //===---------------------------------------------------------------------===//
5054 // SSE3 Instructions
5055 //===---------------------------------------------------------------------===//
5058 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5059 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5060 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5062 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5063 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5064 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5066 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5068 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5070 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5071 IIC_SSE_HADDSUB_RM>;
5073 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5074 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5075 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5077 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5078 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5079 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5081 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5083 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5085 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5086 IIC_SSE_HADDSUB_RM>;
5089 let Predicates = [HasAVX] in {
5090 let ExeDomain = SSEPackedSingle in {
5091 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5092 X86fhadd, 0>, VEX_4V;
5093 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5094 X86fhsub, 0>, VEX_4V;
5095 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5096 X86fhadd, 0>, VEX_4V;
5097 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5098 X86fhsub, 0>, VEX_4V;
5100 let ExeDomain = SSEPackedDouble in {
5101 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5102 X86fhadd, 0>, VEX_4V;
5103 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5104 X86fhsub, 0>, VEX_4V;
5105 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5106 X86fhadd, 0>, VEX_4V;
5107 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5108 X86fhsub, 0>, VEX_4V;
5112 let Constraints = "$src1 = $dst" in {
5113 let ExeDomain = SSEPackedSingle in {
5114 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5115 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5117 let ExeDomain = SSEPackedDouble in {
5118 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5119 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5123 //===---------------------------------------------------------------------===//
5124 // SSSE3 - Packed Absolute Instructions
5125 //===---------------------------------------------------------------------===//
5128 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5129 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5130 Intrinsic IntId128> {
5131 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5133 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5134 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5137 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5142 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5146 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5147 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5148 Intrinsic IntId256> {
5149 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5151 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5152 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5155 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5160 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5163 let Predicates = [HasAVX] in {
5164 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5165 int_x86_ssse3_pabs_b_128>, VEX;
5166 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5167 int_x86_ssse3_pabs_w_128>, VEX;
5168 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5169 int_x86_ssse3_pabs_d_128>, VEX;
5172 let Predicates = [HasAVX2] in {
5173 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5174 int_x86_avx2_pabs_b>, VEX;
5175 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5176 int_x86_avx2_pabs_w>, VEX;
5177 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5178 int_x86_avx2_pabs_d>, VEX;
5181 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5182 int_x86_ssse3_pabs_b_128>;
5183 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5184 int_x86_ssse3_pabs_w_128>;
5185 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5186 int_x86_ssse3_pabs_d_128>;
5188 //===---------------------------------------------------------------------===//
5189 // SSSE3 - Packed Binary Operator Instructions
5190 //===---------------------------------------------------------------------===//
5192 def SSE_PHADDSUBD : OpndItins<
5193 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5195 def SSE_PHADDSUBSW : OpndItins<
5196 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5198 def SSE_PHADDSUBW : OpndItins<
5199 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5201 def SSE_PSHUFB : OpndItins<
5202 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5204 def SSE_PSIGN : OpndItins<
5205 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5207 def SSE_PMULHRSW : OpndItins<
5208 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5211 /// SS3I_binop_rm - Simple SSSE3 bin op
5212 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5213 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5214 X86MemOperand x86memop, OpndItins itins,
5216 let isCommutable = 1 in
5217 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5218 (ins RC:$src1, RC:$src2),
5220 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5222 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5224 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5225 (ins RC:$src1, x86memop:$src2),
5227 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5230 (OpVT (OpNode RC:$src1,
5231 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5234 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5235 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5236 Intrinsic IntId128, OpndItins itins,
5238 let isCommutable = 1 in
5239 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5240 (ins VR128:$src1, VR128:$src2),
5242 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5244 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5246 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5247 (ins VR128:$src1, i128mem:$src2),
5249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5252 (IntId128 VR128:$src1,
5253 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5256 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5257 Intrinsic IntId256> {
5258 let isCommutable = 1 in
5259 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5260 (ins VR256:$src1, VR256:$src2),
5261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5262 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5264 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5265 (ins VR256:$src1, i256mem:$src2),
5266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5268 (IntId256 VR256:$src1,
5269 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5272 let ImmT = NoImm, Predicates = [HasAVX] in {
5273 let isCommutable = 0 in {
5274 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5275 memopv2i64, i128mem,
5276 SSE_PHADDSUBW, 0>, VEX_4V;
5277 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5278 memopv2i64, i128mem,
5279 SSE_PHADDSUBD, 0>, VEX_4V;
5280 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5281 memopv2i64, i128mem,
5282 SSE_PHADDSUBW, 0>, VEX_4V;
5283 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5284 memopv2i64, i128mem,
5285 SSE_PHADDSUBD, 0>, VEX_4V;
5286 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5287 memopv2i64, i128mem,
5288 SSE_PSIGN, 0>, VEX_4V;
5289 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5290 memopv2i64, i128mem,
5291 SSE_PSIGN, 0>, VEX_4V;
5292 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5293 memopv2i64, i128mem,
5294 SSE_PSIGN, 0>, VEX_4V;
5295 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5296 memopv2i64, i128mem,
5297 SSE_PSHUFB, 0>, VEX_4V;
5298 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5299 int_x86_ssse3_phadd_sw_128,
5300 SSE_PHADDSUBSW, 0>, VEX_4V;
5301 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5302 int_x86_ssse3_phsub_sw_128,
5303 SSE_PHADDSUBSW, 0>, VEX_4V;
5304 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5305 int_x86_ssse3_pmadd_ub_sw_128,
5306 SSE_PMADD, 0>, VEX_4V;
5308 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5309 int_x86_ssse3_pmul_hr_sw_128,
5310 SSE_PMULHRSW, 0>, VEX_4V;
5313 let ImmT = NoImm, Predicates = [HasAVX2] in {
5314 let isCommutable = 0 in {
5315 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5316 memopv4i64, i256mem,
5317 SSE_PHADDSUBW, 0>, VEX_4V;
5318 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5319 memopv4i64, i256mem,
5320 SSE_PHADDSUBW, 0>, VEX_4V;
5321 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5322 memopv4i64, i256mem,
5323 SSE_PHADDSUBW, 0>, VEX_4V;
5324 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5325 memopv4i64, i256mem,
5326 SSE_PHADDSUBW, 0>, VEX_4V;
5327 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5328 memopv4i64, i256mem,
5329 SSE_PHADDSUBW, 0>, VEX_4V;
5330 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5331 memopv4i64, i256mem,
5332 SSE_PHADDSUBW, 0>, VEX_4V;
5333 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5334 memopv4i64, i256mem,
5335 SSE_PHADDSUBW, 0>, VEX_4V;
5336 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5337 memopv4i64, i256mem,
5338 SSE_PHADDSUBW, 0>, VEX_4V;
5339 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5340 int_x86_avx2_phadd_sw>, VEX_4V;
5341 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5342 int_x86_avx2_phsub_sw>, VEX_4V;
5343 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5344 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5346 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5347 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5350 // None of these have i8 immediate fields.
5351 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5352 let isCommutable = 0 in {
5353 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5354 memopv2i64, i128mem, SSE_PHADDSUBW>;
5355 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5356 memopv2i64, i128mem, SSE_PHADDSUBD>;
5357 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5358 memopv2i64, i128mem, SSE_PHADDSUBW>;
5359 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5360 memopv2i64, i128mem, SSE_PHADDSUBD>;
5361 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5362 memopv2i64, i128mem, SSE_PSIGN>;
5363 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5364 memopv2i64, i128mem, SSE_PSIGN>;
5365 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5366 memopv2i64, i128mem, SSE_PSIGN>;
5367 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5368 memopv2i64, i128mem, SSE_PSHUFB>;
5369 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5370 int_x86_ssse3_phadd_sw_128,
5372 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5373 int_x86_ssse3_phsub_sw_128,
5375 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5376 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5378 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5379 int_x86_ssse3_pmul_hr_sw_128,
5383 //===---------------------------------------------------------------------===//
5384 // SSSE3 - Packed Align Instruction Patterns
5385 //===---------------------------------------------------------------------===//
5387 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5388 let neverHasSideEffects = 1 in {
5389 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5390 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5392 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5395 [], IIC_SSE_PALIGNR>, OpSize;
5397 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5398 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5400 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5402 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5403 [], IIC_SSE_PALIGNR>, OpSize;
5407 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5408 let neverHasSideEffects = 1 in {
5409 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5410 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5412 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5415 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5416 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5418 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5423 let Predicates = [HasAVX] in
5424 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5425 let Predicates = [HasAVX2] in
5426 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5427 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5428 defm PALIGN : ssse3_palign<"palignr">;
5430 let Predicates = [HasAVX2] in {
5431 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5432 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5433 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5434 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5435 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5436 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5437 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5438 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5441 let Predicates = [HasAVX] in {
5442 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5443 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5444 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5445 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5446 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5447 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5448 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5449 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5452 let Predicates = [HasSSSE3] in {
5453 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5454 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5455 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5456 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5457 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5458 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5459 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5460 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5463 //===---------------------------------------------------------------------===//
5464 // SSSE3 - Thread synchronization
5465 //===---------------------------------------------------------------------===//
5467 let usesCustomInserter = 1 in {
5468 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5469 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5470 Requires<[HasSSE3]>;
5473 let Uses = [EAX, ECX, EDX] in
5474 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5475 TB, Requires<[HasSSE3]>;
5476 let Uses = [ECX, EAX] in
5477 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5478 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5479 TB, Requires<[HasSSE3]>;
5481 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5482 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5484 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5485 Requires<[In32BitMode]>;
5486 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5487 Requires<[In64BitMode]>;
5489 //===----------------------------------------------------------------------===//
5490 // SSE4.1 - Packed Move with Sign/Zero Extend
5491 //===----------------------------------------------------------------------===//
5493 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5494 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5495 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5496 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5498 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5499 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5501 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5505 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5507 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5509 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5511 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5513 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5516 let Predicates = [HasAVX] in {
5517 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5519 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5521 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5523 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5525 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5527 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5531 let Predicates = [HasAVX2] in {
5532 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5533 int_x86_avx2_pmovsxbw>, VEX;
5534 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5535 int_x86_avx2_pmovsxwd>, VEX;
5536 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5537 int_x86_avx2_pmovsxdq>, VEX;
5538 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5539 int_x86_avx2_pmovzxbw>, VEX;
5540 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5541 int_x86_avx2_pmovzxwd>, VEX;
5542 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5543 int_x86_avx2_pmovzxdq>, VEX;
5546 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5547 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5548 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5549 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5550 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5551 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5553 let Predicates = [HasAVX] in {
5554 // Common patterns involving scalar load.
5555 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5556 (VPMOVSXBWrm addr:$src)>;
5557 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5558 (VPMOVSXBWrm addr:$src)>;
5560 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5561 (VPMOVSXWDrm addr:$src)>;
5562 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5563 (VPMOVSXWDrm addr:$src)>;
5565 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5566 (VPMOVSXDQrm addr:$src)>;
5567 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5568 (VPMOVSXDQrm addr:$src)>;
5570 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5571 (VPMOVZXBWrm addr:$src)>;
5572 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5573 (VPMOVZXBWrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5576 (VPMOVZXWDrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5578 (VPMOVZXWDrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5581 (VPMOVZXDQrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5583 (VPMOVZXDQrm addr:$src)>;
5586 let Predicates = [HasSSE41] in {
5587 // Common patterns involving scalar load.
5588 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5589 (PMOVSXBWrm addr:$src)>;
5590 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5591 (PMOVSXBWrm addr:$src)>;
5593 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5594 (PMOVSXWDrm addr:$src)>;
5595 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5596 (PMOVSXWDrm addr:$src)>;
5598 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5599 (PMOVSXDQrm addr:$src)>;
5600 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5601 (PMOVSXDQrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5604 (PMOVZXBWrm addr:$src)>;
5605 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5606 (PMOVZXBWrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5609 (PMOVZXWDrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5611 (PMOVZXWDrm addr:$src)>;
5613 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5614 (PMOVZXDQrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5616 (PMOVZXDQrm addr:$src)>;
5619 let Predicates = [HasAVX2] in {
5620 let AddedComplexity = 15 in {
5621 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5622 (VPMOVZXDQYrr VR128:$src)>;
5623 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5624 (VPMOVZXWDYrr VR128:$src)>;
5627 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5628 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5631 let Predicates = [HasAVX] in {
5632 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5633 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5636 let Predicates = [HasSSE41] in {
5637 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5638 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5642 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5643 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5645 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5647 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5650 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5654 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5656 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5657 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5658 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5660 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5661 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5663 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5667 let Predicates = [HasAVX] in {
5668 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5670 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5672 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5674 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5678 let Predicates = [HasAVX2] in {
5679 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5680 int_x86_avx2_pmovsxbd>, VEX;
5681 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5682 int_x86_avx2_pmovsxwq>, VEX;
5683 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5684 int_x86_avx2_pmovzxbd>, VEX;
5685 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5686 int_x86_avx2_pmovzxwq>, VEX;
5689 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5690 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5691 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5692 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5694 let Predicates = [HasAVX] in {
5695 // Common patterns involving scalar load
5696 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5697 (VPMOVSXBDrm addr:$src)>;
5698 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5699 (VPMOVSXWQrm addr:$src)>;
5701 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5702 (VPMOVZXBDrm addr:$src)>;
5703 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5704 (VPMOVZXWQrm addr:$src)>;
5707 let Predicates = [HasSSE41] in {
5708 // Common patterns involving scalar load
5709 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5710 (PMOVSXBDrm addr:$src)>;
5711 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5712 (PMOVSXWQrm addr:$src)>;
5714 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5715 (PMOVZXBDrm addr:$src)>;
5716 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5717 (PMOVZXWQrm addr:$src)>;
5720 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5721 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5723 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5725 // Expecting a i16 load any extended to i32 value.
5726 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5727 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5728 [(set VR128:$dst, (IntId (bitconvert
5729 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5733 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5735 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5736 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5737 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5739 // Expecting a i16 load any extended to i32 value.
5740 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5741 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5742 [(set VR256:$dst, (IntId (bitconvert
5743 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5747 let Predicates = [HasAVX] in {
5748 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5750 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5753 let Predicates = [HasAVX2] in {
5754 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5755 int_x86_avx2_pmovsxbq>, VEX;
5756 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5757 int_x86_avx2_pmovzxbq>, VEX;
5759 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5760 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5762 let Predicates = [HasAVX] in {
5763 // Common patterns involving scalar load
5764 def : Pat<(int_x86_sse41_pmovsxbq
5765 (bitconvert (v4i32 (X86vzmovl
5766 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5767 (VPMOVSXBQrm addr:$src)>;
5769 def : Pat<(int_x86_sse41_pmovzxbq
5770 (bitconvert (v4i32 (X86vzmovl
5771 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5772 (VPMOVZXBQrm addr:$src)>;
5775 let Predicates = [HasSSE41] in {
5776 // Common patterns involving scalar load
5777 def : Pat<(int_x86_sse41_pmovsxbq
5778 (bitconvert (v4i32 (X86vzmovl
5779 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5780 (PMOVSXBQrm addr:$src)>;
5782 def : Pat<(int_x86_sse41_pmovzxbq
5783 (bitconvert (v4i32 (X86vzmovl
5784 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5785 (PMOVZXBQrm addr:$src)>;
5788 //===----------------------------------------------------------------------===//
5789 // SSE4.1 - Extract Instructions
5790 //===----------------------------------------------------------------------===//
5792 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5793 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5794 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5795 (ins VR128:$src1, i32i8imm:$src2),
5796 !strconcat(OpcodeStr,
5797 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5798 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5800 let neverHasSideEffects = 1, mayStore = 1 in
5801 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5802 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5803 !strconcat(OpcodeStr,
5804 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5807 // There's an AssertZext in the way of writing the store pattern
5808 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5811 let Predicates = [HasAVX] in {
5812 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5813 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5814 (ins VR128:$src1, i32i8imm:$src2),
5815 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5818 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5821 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5822 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5823 let neverHasSideEffects = 1, mayStore = 1 in
5824 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5825 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5826 !strconcat(OpcodeStr,
5827 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5830 // There's an AssertZext in the way of writing the store pattern
5831 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5834 let Predicates = [HasAVX] in
5835 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5837 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5840 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5841 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5842 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5843 (ins VR128:$src1, i32i8imm:$src2),
5844 !strconcat(OpcodeStr,
5845 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5847 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5848 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5849 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5850 !strconcat(OpcodeStr,
5851 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5852 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5853 addr:$dst)]>, OpSize;
5856 let Predicates = [HasAVX] in
5857 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5859 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5861 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5862 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5863 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5864 (ins VR128:$src1, i32i8imm:$src2),
5865 !strconcat(OpcodeStr,
5866 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5868 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5869 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5870 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5871 !strconcat(OpcodeStr,
5872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5873 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5874 addr:$dst)]>, OpSize, REX_W;
5877 let Predicates = [HasAVX] in
5878 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5880 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5882 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5884 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5885 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5886 (ins VR128:$src1, i32i8imm:$src2),
5887 !strconcat(OpcodeStr,
5888 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5890 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5892 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5893 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5894 !strconcat(OpcodeStr,
5895 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5896 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5897 addr:$dst)]>, OpSize;
5900 let ExeDomain = SSEPackedSingle in {
5901 let Predicates = [HasAVX] in {
5902 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5903 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5904 (ins VR128:$src1, i32i8imm:$src2),
5905 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5908 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5911 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5912 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5915 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5917 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5920 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5921 Requires<[HasSSE41]>;
5923 //===----------------------------------------------------------------------===//
5924 // SSE4.1 - Insert Instructions
5925 //===----------------------------------------------------------------------===//
5927 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5928 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5929 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5931 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5933 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5935 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5936 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5937 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5939 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5941 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5943 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5944 imm:$src3))]>, OpSize;
5947 let Predicates = [HasAVX] in
5948 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5949 let Constraints = "$src1 = $dst" in
5950 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5952 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5953 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5954 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5956 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5958 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5960 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5962 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5963 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5965 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5967 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5969 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5970 imm:$src3)))]>, OpSize;
5973 let Predicates = [HasAVX] in
5974 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5975 let Constraints = "$src1 = $dst" in
5976 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5978 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5979 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5980 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5982 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5984 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5986 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5988 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5989 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5991 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5993 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5995 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5996 imm:$src3)))]>, OpSize;
5999 let Predicates = [HasAVX] in
6000 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6001 let Constraints = "$src1 = $dst" in
6002 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6004 // insertps has a few different modes, there's the first two here below which
6005 // are optimized inserts that won't zero arbitrary elements in the destination
6006 // vector. The next one matches the intrinsic and could zero arbitrary elements
6007 // in the target vector.
6008 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6009 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6010 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6012 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6014 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6016 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6018 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6019 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6021 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6023 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6025 (X86insrtps VR128:$src1,
6026 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6027 imm:$src3))]>, OpSize;
6030 let ExeDomain = SSEPackedSingle in {
6031 let Predicates = [HasAVX] in
6032 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6033 let Constraints = "$src1 = $dst" in
6034 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6037 //===----------------------------------------------------------------------===//
6038 // SSE4.1 - Round Instructions
6039 //===----------------------------------------------------------------------===//
6041 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6042 X86MemOperand x86memop, RegisterClass RC,
6043 PatFrag mem_frag32, PatFrag mem_frag64,
6044 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6045 let ExeDomain = SSEPackedSingle in {
6046 // Intrinsic operation, reg.
6047 // Vector intrinsic operation, reg
6048 def PSr : SS4AIi8<opcps, MRMSrcReg,
6049 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6050 !strconcat(OpcodeStr,
6051 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6052 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6055 // Vector intrinsic operation, mem
6056 def PSm : SS4AIi8<opcps, MRMSrcMem,
6057 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6058 !strconcat(OpcodeStr,
6059 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6061 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6063 } // ExeDomain = SSEPackedSingle
6065 let ExeDomain = SSEPackedDouble in {
6066 // Vector intrinsic operation, reg
6067 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6068 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6069 !strconcat(OpcodeStr,
6070 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6071 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6074 // Vector intrinsic operation, mem
6075 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6076 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6077 !strconcat(OpcodeStr,
6078 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6080 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6082 } // ExeDomain = SSEPackedDouble
6085 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6088 Intrinsic F64Int, bit Is2Addr = 1> {
6089 let ExeDomain = GenericDomain in {
6091 def SSr : SS4AIi8<opcss, MRMSrcReg,
6092 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6094 !strconcat(OpcodeStr,
6095 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6096 !strconcat(OpcodeStr,
6097 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6100 // Intrinsic operation, reg.
6101 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6102 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6104 !strconcat(OpcodeStr,
6105 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6106 !strconcat(OpcodeStr,
6107 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6108 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6111 // Intrinsic operation, mem.
6112 def SSm : SS4AIi8<opcss, MRMSrcMem,
6113 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6115 !strconcat(OpcodeStr,
6116 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6117 !strconcat(OpcodeStr,
6118 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6120 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6124 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6125 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6127 !strconcat(OpcodeStr,
6128 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6129 !strconcat(OpcodeStr,
6130 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6133 // Intrinsic operation, reg.
6134 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6135 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6137 !strconcat(OpcodeStr,
6138 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6139 !strconcat(OpcodeStr,
6140 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6141 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6144 // Intrinsic operation, mem.
6145 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6146 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6148 !strconcat(OpcodeStr,
6149 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6150 !strconcat(OpcodeStr,
6151 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6153 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6155 } // ExeDomain = GenericDomain
6158 // FP round - roundss, roundps, roundsd, roundpd
6159 let Predicates = [HasAVX] in {
6161 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6162 memopv4f32, memopv2f64,
6163 int_x86_sse41_round_ps,
6164 int_x86_sse41_round_pd>, VEX;
6165 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6166 memopv8f32, memopv4f64,
6167 int_x86_avx_round_ps_256,
6168 int_x86_avx_round_pd_256>, VEX;
6169 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6170 int_x86_sse41_round_ss,
6171 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6173 def : Pat<(ffloor FR32:$src),
6174 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6175 def : Pat<(f64 (ffloor FR64:$src)),
6176 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6177 def : Pat<(f32 (fnearbyint FR32:$src)),
6178 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6179 def : Pat<(f64 (fnearbyint FR64:$src)),
6180 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6181 def : Pat<(f32 (fceil FR32:$src)),
6182 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6183 def : Pat<(f64 (fceil FR64:$src)),
6184 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6185 def : Pat<(f32 (frint FR32:$src)),
6186 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6187 def : Pat<(f64 (frint FR64:$src)),
6188 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6189 def : Pat<(f32 (ftrunc FR32:$src)),
6190 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6191 def : Pat<(f64 (ftrunc FR64:$src)),
6192 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6195 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6196 memopv4f32, memopv2f64,
6197 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6198 let Constraints = "$src1 = $dst" in
6199 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6200 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6202 def : Pat<(ffloor FR32:$src),
6203 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6204 def : Pat<(f64 (ffloor FR64:$src)),
6205 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6206 def : Pat<(f32 (fnearbyint FR32:$src)),
6207 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6208 def : Pat<(f64 (fnearbyint FR64:$src)),
6209 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6210 def : Pat<(f32 (fceil FR32:$src)),
6211 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6212 def : Pat<(f64 (fceil FR64:$src)),
6213 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6214 def : Pat<(f32 (frint FR32:$src)),
6215 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6216 def : Pat<(f64 (frint FR64:$src)),
6217 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6218 def : Pat<(f32 (ftrunc FR32:$src)),
6219 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6220 def : Pat<(f64 (ftrunc FR64:$src)),
6221 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6223 //===----------------------------------------------------------------------===//
6224 // SSE4.1 - Packed Bit Test
6225 //===----------------------------------------------------------------------===//
6227 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6228 // the intel intrinsic that corresponds to this.
6229 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6230 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6231 "vptest\t{$src2, $src1|$src1, $src2}",
6232 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6234 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6235 "vptest\t{$src2, $src1|$src1, $src2}",
6236 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6239 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6240 "vptest\t{$src2, $src1|$src1, $src2}",
6241 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6243 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6244 "vptest\t{$src2, $src1|$src1, $src2}",
6245 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6249 let Defs = [EFLAGS] in {
6250 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6251 "ptest\t{$src2, $src1|$src1, $src2}",
6252 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6254 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6255 "ptest\t{$src2, $src1|$src1, $src2}",
6256 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6260 // The bit test instructions below are AVX only
6261 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6262 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6263 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6264 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6265 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6266 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6267 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6268 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6272 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6273 let ExeDomain = SSEPackedSingle in {
6274 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6275 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6277 let ExeDomain = SSEPackedDouble in {
6278 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6279 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6283 //===----------------------------------------------------------------------===//
6284 // SSE4.1 - Misc Instructions
6285 //===----------------------------------------------------------------------===//
6287 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6288 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6289 "popcnt{w}\t{$src, $dst|$dst, $src}",
6290 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6292 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6293 "popcnt{w}\t{$src, $dst|$dst, $src}",
6294 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6295 (implicit EFLAGS)]>, OpSize, XS;
6297 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6298 "popcnt{l}\t{$src, $dst|$dst, $src}",
6299 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6301 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6302 "popcnt{l}\t{$src, $dst|$dst, $src}",
6303 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6304 (implicit EFLAGS)]>, XS;
6306 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6307 "popcnt{q}\t{$src, $dst|$dst, $src}",
6308 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6310 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6311 "popcnt{q}\t{$src, $dst|$dst, $src}",
6312 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6313 (implicit EFLAGS)]>, XS;
6318 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6319 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6320 Intrinsic IntId128> {
6321 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6324 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6325 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6327 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6330 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6333 let Predicates = [HasAVX] in
6334 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6335 int_x86_sse41_phminposuw>, VEX;
6336 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6337 int_x86_sse41_phminposuw>;
6339 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6340 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6341 Intrinsic IntId128, bit Is2Addr = 1> {
6342 let isCommutable = 1 in
6343 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6344 (ins VR128:$src1, VR128:$src2),
6346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6348 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6349 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6350 (ins VR128:$src1, i128mem:$src2),
6352 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6353 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6355 (IntId128 VR128:$src1,
6356 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6359 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6360 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6361 Intrinsic IntId256> {
6362 let isCommutable = 1 in
6363 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6364 (ins VR256:$src1, VR256:$src2),
6365 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6366 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6367 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6368 (ins VR256:$src1, i256mem:$src2),
6369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6371 (IntId256 VR256:$src1,
6372 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6375 let Predicates = [HasAVX] in {
6376 let isCommutable = 0 in
6377 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6379 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6381 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6383 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6385 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6387 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6389 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6391 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6393 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6395 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6399 let Predicates = [HasAVX2] in {
6400 let isCommutable = 0 in
6401 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6402 int_x86_avx2_packusdw>, VEX_4V;
6403 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6404 int_x86_avx2_pmins_b>, VEX_4V;
6405 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6406 int_x86_avx2_pmins_d>, VEX_4V;
6407 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6408 int_x86_avx2_pminu_d>, VEX_4V;
6409 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6410 int_x86_avx2_pminu_w>, VEX_4V;
6411 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6412 int_x86_avx2_pmaxs_b>, VEX_4V;
6413 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6414 int_x86_avx2_pmaxs_d>, VEX_4V;
6415 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6416 int_x86_avx2_pmaxu_d>, VEX_4V;
6417 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6418 int_x86_avx2_pmaxu_w>, VEX_4V;
6419 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6420 int_x86_avx2_pmul_dq>, VEX_4V;
6423 let Constraints = "$src1 = $dst" in {
6424 let isCommutable = 0 in
6425 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6426 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6427 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6428 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6429 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6430 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6431 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6432 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6433 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6434 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6437 /// SS48I_binop_rm - Simple SSE41 binary operator.
6438 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6439 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6440 X86MemOperand x86memop, bit Is2Addr = 1> {
6441 let isCommutable = 1 in
6442 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6443 (ins RC:$src1, RC:$src2),
6445 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6446 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6447 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6448 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6449 (ins RC:$src1, x86memop:$src2),
6451 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6454 (OpVT (OpNode RC:$src1,
6455 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6458 let Predicates = [HasAVX] in {
6459 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6460 memopv2i64, i128mem, 0>, VEX_4V;
6461 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6462 memopv2i64, i128mem, 0>, VEX_4V;
6464 let Predicates = [HasAVX2] in {
6465 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6466 memopv4i64, i256mem, 0>, VEX_4V;
6467 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6468 memopv4i64, i256mem, 0>, VEX_4V;
6471 let Constraints = "$src1 = $dst" in {
6472 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6473 memopv2i64, i128mem>;
6474 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6475 memopv2i64, i128mem>;
6478 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6479 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6480 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6481 X86MemOperand x86memop, bit Is2Addr = 1> {
6482 let isCommutable = 1 in
6483 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6484 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6486 !strconcat(OpcodeStr,
6487 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6488 !strconcat(OpcodeStr,
6489 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6490 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6492 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6493 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6495 !strconcat(OpcodeStr,
6496 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6497 !strconcat(OpcodeStr,
6498 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6501 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6505 let Predicates = [HasAVX] in {
6506 let isCommutable = 0 in {
6507 let ExeDomain = SSEPackedSingle in {
6508 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6509 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6510 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6511 int_x86_avx_blend_ps_256, VR256, memopv8f32, f256mem, 0>, VEX_4V;
6513 let ExeDomain = SSEPackedDouble in {
6514 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6515 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6516 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6517 int_x86_avx_blend_pd_256, VR256, memopv4f64, f256mem, 0>, VEX_4V;
6519 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6520 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6521 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6522 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6524 let ExeDomain = SSEPackedSingle in
6525 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6526 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6527 let ExeDomain = SSEPackedDouble in
6528 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6529 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6530 let ExeDomain = SSEPackedSingle in
6531 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6532 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6535 let Predicates = [HasAVX2] in {
6536 let isCommutable = 0 in {
6537 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6538 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6539 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6540 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6544 let Constraints = "$src1 = $dst" in {
6545 let isCommutable = 0 in {
6546 let ExeDomain = SSEPackedSingle in
6547 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6548 VR128, memopv4f32, f128mem>;
6549 let ExeDomain = SSEPackedDouble in
6550 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6551 VR128, memopv2f64, f128mem>;
6552 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6553 VR128, memopv2i64, i128mem>;
6554 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6555 VR128, memopv2i64, i128mem>;
6557 let ExeDomain = SSEPackedSingle in
6558 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6559 VR128, memopv4f32, f128mem>;
6560 let ExeDomain = SSEPackedDouble in
6561 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6562 VR128, memopv2f64, f128mem>;
6565 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6566 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6567 RegisterClass RC, X86MemOperand x86memop,
6568 PatFrag mem_frag, Intrinsic IntId> {
6569 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6570 (ins RC:$src1, RC:$src2, RC:$src3),
6571 !strconcat(OpcodeStr,
6572 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6573 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6574 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6576 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6577 (ins RC:$src1, x86memop:$src2, RC:$src3),
6578 !strconcat(OpcodeStr,
6579 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6581 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6583 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6586 let Predicates = [HasAVX] in {
6587 let ExeDomain = SSEPackedDouble in {
6588 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6589 memopv2f64, int_x86_sse41_blendvpd>;
6590 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6591 memopv4f64, int_x86_avx_blendv_pd_256>;
6592 } // ExeDomain = SSEPackedDouble
6593 let ExeDomain = SSEPackedSingle in {
6594 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6595 memopv4f32, int_x86_sse41_blendvps>;
6596 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6597 memopv8f32, int_x86_avx_blendv_ps_256>;
6598 } // ExeDomain = SSEPackedSingle
6599 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6600 memopv2i64, int_x86_sse41_pblendvb>;
6603 let Predicates = [HasAVX2] in {
6604 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6605 memopv4i64, int_x86_avx2_pblendvb>;
6608 let Predicates = [HasAVX] in {
6609 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6610 (v16i8 VR128:$src2))),
6611 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6612 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6613 (v4i32 VR128:$src2))),
6614 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6615 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6616 (v4f32 VR128:$src2))),
6617 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6618 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6619 (v2i64 VR128:$src2))),
6620 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6621 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6622 (v2f64 VR128:$src2))),
6623 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6624 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6625 (v8i32 VR256:$src2))),
6626 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6627 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6628 (v8f32 VR256:$src2))),
6629 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6630 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6631 (v4i64 VR256:$src2))),
6632 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6633 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6634 (v4f64 VR256:$src2))),
6635 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6637 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6639 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6640 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6642 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6644 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6646 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6647 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6649 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6650 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6652 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6655 let Predicates = [HasAVX2] in {
6656 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6657 (v32i8 VR256:$src2))),
6658 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6659 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6661 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6664 /// SS41I_ternary_int - SSE 4.1 ternary operator
6665 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6666 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6667 X86MemOperand x86memop, Intrinsic IntId> {
6668 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6669 (ins VR128:$src1, VR128:$src2),
6670 !strconcat(OpcodeStr,
6671 "\t{$src2, $dst|$dst, $src2}"),
6672 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6675 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6676 (ins VR128:$src1, x86memop:$src2),
6677 !strconcat(OpcodeStr,
6678 "\t{$src2, $dst|$dst, $src2}"),
6681 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6685 let ExeDomain = SSEPackedDouble in
6686 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6687 int_x86_sse41_blendvpd>;
6688 let ExeDomain = SSEPackedSingle in
6689 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6690 int_x86_sse41_blendvps>;
6691 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6692 int_x86_sse41_pblendvb>;
6694 // Aliases with the implicit xmm0 argument
6695 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6696 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6697 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6698 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6699 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6700 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6701 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6702 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6703 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6704 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6705 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6706 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6708 let Predicates = [HasSSE41] in {
6709 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6710 (v16i8 VR128:$src2))),
6711 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6712 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6713 (v4i32 VR128:$src2))),
6714 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6715 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6716 (v4f32 VR128:$src2))),
6717 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6718 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6719 (v2i64 VR128:$src2))),
6720 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6721 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6722 (v2f64 VR128:$src2))),
6723 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6725 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6727 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6728 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6730 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6731 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6733 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6737 let Predicates = [HasAVX] in
6738 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6739 "vmovntdqa\t{$src, $dst|$dst, $src}",
6740 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6742 let Predicates = [HasAVX2] in
6743 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6744 "vmovntdqa\t{$src, $dst|$dst, $src}",
6745 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6747 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6748 "movntdqa\t{$src, $dst|$dst, $src}",
6749 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6752 //===----------------------------------------------------------------------===//
6753 // SSE4.2 - Compare Instructions
6754 //===----------------------------------------------------------------------===//
6756 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6757 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6758 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6759 X86MemOperand x86memop, bit Is2Addr = 1> {
6760 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6761 (ins RC:$src1, RC:$src2),
6763 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6764 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6765 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6767 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6768 (ins RC:$src1, x86memop:$src2),
6770 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6771 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6773 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6776 let Predicates = [HasAVX] in
6777 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6778 memopv2i64, i128mem, 0>, VEX_4V;
6780 let Predicates = [HasAVX2] in
6781 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6782 memopv4i64, i256mem, 0>, VEX_4V;
6784 let Constraints = "$src1 = $dst" in
6785 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6786 memopv2i64, i128mem>;
6788 //===----------------------------------------------------------------------===//
6789 // SSE4.2 - String/text Processing Instructions
6790 //===----------------------------------------------------------------------===//
6792 // Packed Compare Implicit Length Strings, Return Mask
6793 multiclass pseudo_pcmpistrm<string asm> {
6794 def REG : PseudoI<(outs VR128:$dst),
6795 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6796 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6798 def MEM : PseudoI<(outs VR128:$dst),
6799 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6800 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6801 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6804 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6805 let AddedComplexity = 1 in
6806 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6807 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6810 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6811 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6812 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6813 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6815 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6816 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6817 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6820 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6821 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6822 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6823 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6825 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6826 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6827 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6830 // Packed Compare Explicit Length Strings, Return Mask
6831 multiclass pseudo_pcmpestrm<string asm> {
6832 def REG : PseudoI<(outs VR128:$dst),
6833 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6834 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6835 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6836 def MEM : PseudoI<(outs VR128:$dst),
6837 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6838 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6839 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6842 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6843 let AddedComplexity = 1 in
6844 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6845 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6848 let Predicates = [HasAVX],
6849 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6850 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6851 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6852 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6854 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6855 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6856 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6859 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6860 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6861 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6862 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6864 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6865 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6866 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6869 // Packed Compare Implicit Length Strings, Return Index
6870 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6871 multiclass SS42AI_pcmpistri<string asm> {
6872 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6873 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6874 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6877 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6878 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6879 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6884 let Predicates = [HasAVX] in
6885 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6886 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6888 // Packed Compare Explicit Length Strings, Return Index
6889 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6890 multiclass SS42AI_pcmpestri<string asm> {
6891 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6892 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6893 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6896 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6897 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6898 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6903 let Predicates = [HasAVX] in
6904 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
6905 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
6907 //===----------------------------------------------------------------------===//
6908 // SSE4.2 - CRC Instructions
6909 //===----------------------------------------------------------------------===//
6911 // No CRC instructions have AVX equivalents
6913 // crc intrinsic instruction
6914 // This set of instructions are only rm, the only difference is the size
6916 let Constraints = "$src1 = $dst" in {
6917 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6918 (ins GR32:$src1, i8mem:$src2),
6919 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6921 (int_x86_sse42_crc32_32_8 GR32:$src1,
6922 (load addr:$src2)))]>;
6923 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6924 (ins GR32:$src1, GR8:$src2),
6925 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6927 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6928 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6929 (ins GR32:$src1, i16mem:$src2),
6930 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6932 (int_x86_sse42_crc32_32_16 GR32:$src1,
6933 (load addr:$src2)))]>,
6935 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6936 (ins GR32:$src1, GR16:$src2),
6937 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6939 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6941 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6942 (ins GR32:$src1, i32mem:$src2),
6943 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6945 (int_x86_sse42_crc32_32_32 GR32:$src1,
6946 (load addr:$src2)))]>;
6947 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6948 (ins GR32:$src1, GR32:$src2),
6949 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6951 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6952 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6953 (ins GR64:$src1, i8mem:$src2),
6954 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6956 (int_x86_sse42_crc32_64_8 GR64:$src1,
6957 (load addr:$src2)))]>,
6959 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6960 (ins GR64:$src1, GR8:$src2),
6961 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6963 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6965 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6966 (ins GR64:$src1, i64mem:$src2),
6967 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6969 (int_x86_sse42_crc32_64_64 GR64:$src1,
6970 (load addr:$src2)))]>,
6972 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6973 (ins GR64:$src1, GR64:$src2),
6974 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6976 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6980 //===----------------------------------------------------------------------===//
6981 // AES-NI Instructions
6982 //===----------------------------------------------------------------------===//
6984 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6985 Intrinsic IntId128, bit Is2Addr = 1> {
6986 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6987 (ins VR128:$src1, VR128:$src2),
6989 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6990 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6991 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6993 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6994 (ins VR128:$src1, i128mem:$src2),
6996 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6999 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7002 // Perform One Round of an AES Encryption/Decryption Flow
7003 let Predicates = [HasAVX, HasAES] in {
7004 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7005 int_x86_aesni_aesenc, 0>, VEX_4V;
7006 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7007 int_x86_aesni_aesenclast, 0>, VEX_4V;
7008 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7009 int_x86_aesni_aesdec, 0>, VEX_4V;
7010 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7011 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7014 let Constraints = "$src1 = $dst" in {
7015 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7016 int_x86_aesni_aesenc>;
7017 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7018 int_x86_aesni_aesenclast>;
7019 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7020 int_x86_aesni_aesdec>;
7021 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7022 int_x86_aesni_aesdeclast>;
7025 // Perform the AES InvMixColumn Transformation
7026 let Predicates = [HasAVX, HasAES] in {
7027 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7029 "vaesimc\t{$src1, $dst|$dst, $src1}",
7031 (int_x86_aesni_aesimc VR128:$src1))]>,
7033 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7034 (ins i128mem:$src1),
7035 "vaesimc\t{$src1, $dst|$dst, $src1}",
7036 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7039 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7041 "aesimc\t{$src1, $dst|$dst, $src1}",
7043 (int_x86_aesni_aesimc VR128:$src1))]>,
7045 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7046 (ins i128mem:$src1),
7047 "aesimc\t{$src1, $dst|$dst, $src1}",
7048 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7051 // AES Round Key Generation Assist
7052 let Predicates = [HasAVX, HasAES] in {
7053 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7054 (ins VR128:$src1, i8imm:$src2),
7055 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7057 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7059 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7060 (ins i128mem:$src1, i8imm:$src2),
7061 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7063 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7066 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7067 (ins VR128:$src1, i8imm:$src2),
7068 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7070 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7072 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7073 (ins i128mem:$src1, i8imm:$src2),
7074 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7076 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7079 //===----------------------------------------------------------------------===//
7080 // PCLMUL Instructions
7081 //===----------------------------------------------------------------------===//
7083 // AVX carry-less Multiplication instructions
7084 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7085 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7086 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7088 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7090 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7091 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7092 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7093 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7094 (memopv2i64 addr:$src2), imm:$src3))]>;
7096 // Carry-less Multiplication instructions
7097 let Constraints = "$src1 = $dst" in {
7098 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7099 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7100 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7102 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7104 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7105 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7106 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7107 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7108 (memopv2i64 addr:$src2), imm:$src3))]>;
7109 } // Constraints = "$src1 = $dst"
7112 multiclass pclmul_alias<string asm, int immop> {
7113 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7114 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7116 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7117 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7119 def : InstAlias<!strconcat("vpclmul", asm,
7120 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7121 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7123 def : InstAlias<!strconcat("vpclmul", asm,
7124 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7125 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7127 defm : pclmul_alias<"hqhq", 0x11>;
7128 defm : pclmul_alias<"hqlq", 0x01>;
7129 defm : pclmul_alias<"lqhq", 0x10>;
7130 defm : pclmul_alias<"lqlq", 0x00>;
7132 //===----------------------------------------------------------------------===//
7133 // SSE4A Instructions
7134 //===----------------------------------------------------------------------===//
7136 let Predicates = [HasSSE4A] in {
7138 let Constraints = "$src = $dst" in {
7139 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7140 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7141 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7142 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7143 imm:$idx))]>, TB, OpSize;
7144 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7145 (ins VR128:$src, VR128:$mask),
7146 "extrq\t{$mask, $src|$src, $mask}",
7147 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7148 VR128:$mask))]>, TB, OpSize;
7150 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7151 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7152 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7153 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7154 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7155 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7156 (ins VR128:$src, VR128:$mask),
7157 "insertq\t{$mask, $src|$src, $mask}",
7158 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7159 VR128:$mask))]>, XD;
7162 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7163 "movntss\t{$src, $dst|$dst, $src}",
7164 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7166 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7167 "movntsd\t{$src, $dst|$dst, $src}",
7168 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7171 //===----------------------------------------------------------------------===//
7173 //===----------------------------------------------------------------------===//
7175 //===----------------------------------------------------------------------===//
7176 // VBROADCAST - Load from memory and broadcast to all elements of the
7177 // destination operand
7179 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7180 X86MemOperand x86memop, Intrinsic Int> :
7181 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7182 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7183 [(set RC:$dst, (Int addr:$src))]>, VEX;
7185 // AVX2 adds register forms
7186 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7188 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7189 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7190 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7192 let ExeDomain = SSEPackedSingle in {
7193 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7194 int_x86_avx_vbroadcast_ss>;
7195 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7196 int_x86_avx_vbroadcast_ss_256>;
7198 let ExeDomain = SSEPackedDouble in
7199 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7200 int_x86_avx_vbroadcast_sd_256>;
7201 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7202 int_x86_avx_vbroadcastf128_pd_256>;
7204 let ExeDomain = SSEPackedSingle in {
7205 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7206 int_x86_avx2_vbroadcast_ss_ps>;
7207 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7208 int_x86_avx2_vbroadcast_ss_ps_256>;
7210 let ExeDomain = SSEPackedDouble in
7211 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7212 int_x86_avx2_vbroadcast_sd_pd_256>;
7214 let Predicates = [HasAVX2] in
7215 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7216 int_x86_avx2_vbroadcasti128>;
7218 let Predicates = [HasAVX] in
7219 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7220 (VBROADCASTF128 addr:$src)>;
7223 //===----------------------------------------------------------------------===//
7224 // VINSERTF128 - Insert packed floating-point values
7226 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7227 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7228 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7229 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7232 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7233 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7234 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7238 let Predicates = [HasAVX] in {
7239 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7241 (VINSERTF128rr VR256:$src1, VR128:$src2,
7242 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7243 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7245 (VINSERTF128rr VR256:$src1, VR128:$src2,
7246 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7247 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7249 (VINSERTF128rr VR256:$src1, VR128:$src2,
7250 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7251 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7253 (VINSERTF128rr VR256:$src1, VR128:$src2,
7254 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7255 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7257 (VINSERTF128rr VR256:$src1, VR128:$src2,
7258 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7259 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7261 (VINSERTF128rr VR256:$src1, VR128:$src2,
7262 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7264 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7266 (VINSERTF128rm VR256:$src1, addr:$src2,
7267 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7268 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7270 (VINSERTF128rm VR256:$src1, addr:$src2,
7271 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7272 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7274 (VINSERTF128rm VR256:$src1, addr:$src2,
7275 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7278 //===----------------------------------------------------------------------===//
7279 // VEXTRACTF128 - Extract packed floating-point values
7281 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7282 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7283 (ins VR256:$src1, i8imm:$src2),
7284 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7287 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7288 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7289 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7293 // Extract and store.
7294 let Predicates = [HasAVX] in {
7295 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7296 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7297 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7298 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7299 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7300 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7302 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7303 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7304 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7305 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7306 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7307 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7311 let Predicates = [HasAVX] in {
7312 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7313 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7314 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7315 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7316 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7317 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7319 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7320 (v4f32 (VEXTRACTF128rr
7321 (v8f32 VR256:$src1),
7322 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7323 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7324 (v2f64 (VEXTRACTF128rr
7325 (v4f64 VR256:$src1),
7326 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7327 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7328 (v2i64 (VEXTRACTF128rr
7329 (v4i64 VR256:$src1),
7330 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7331 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7332 (v4i32 (VEXTRACTF128rr
7333 (v8i32 VR256:$src1),
7334 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7335 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7336 (v8i16 (VEXTRACTF128rr
7337 (v16i16 VR256:$src1),
7338 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7339 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7340 (v16i8 (VEXTRACTF128rr
7341 (v32i8 VR256:$src1),
7342 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7345 //===----------------------------------------------------------------------===//
7346 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7348 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7349 Intrinsic IntLd, Intrinsic IntLd256,
7350 Intrinsic IntSt, Intrinsic IntSt256> {
7351 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7352 (ins VR128:$src1, f128mem:$src2),
7353 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7354 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7356 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7357 (ins VR256:$src1, f256mem:$src2),
7358 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7359 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7361 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7362 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7364 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7365 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7366 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7368 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7371 let ExeDomain = SSEPackedSingle in
7372 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7373 int_x86_avx_maskload_ps,
7374 int_x86_avx_maskload_ps_256,
7375 int_x86_avx_maskstore_ps,
7376 int_x86_avx_maskstore_ps_256>;
7377 let ExeDomain = SSEPackedDouble in
7378 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7379 int_x86_avx_maskload_pd,
7380 int_x86_avx_maskload_pd_256,
7381 int_x86_avx_maskstore_pd,
7382 int_x86_avx_maskstore_pd_256>;
7384 //===----------------------------------------------------------------------===//
7385 // VPERMIL - Permute Single and Double Floating-Point Values
7387 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7388 RegisterClass RC, X86MemOperand x86memop_f,
7389 X86MemOperand x86memop_i, PatFrag i_frag,
7390 Intrinsic IntVar, ValueType vt> {
7391 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7392 (ins RC:$src1, RC:$src2),
7393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7394 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7395 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7396 (ins RC:$src1, x86memop_i:$src2),
7397 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7398 [(set RC:$dst, (IntVar RC:$src1,
7399 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7401 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7402 (ins RC:$src1, i8imm:$src2),
7403 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7404 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7405 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7406 (ins x86memop_f:$src1, i8imm:$src2),
7407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7409 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7412 let ExeDomain = SSEPackedSingle in {
7413 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7414 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7415 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7416 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7418 let ExeDomain = SSEPackedDouble in {
7419 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7420 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7421 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7422 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7425 let Predicates = [HasAVX] in {
7426 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7427 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7428 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7429 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7430 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7432 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7433 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7434 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7436 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7437 (VPERMILPDri VR128:$src1, imm:$imm)>;
7438 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7439 (VPERMILPDmi addr:$src1, imm:$imm)>;
7442 //===----------------------------------------------------------------------===//
7443 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7445 let ExeDomain = SSEPackedSingle in {
7446 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7447 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7448 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7449 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7450 (i8 imm:$src3))))]>, VEX_4V;
7451 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7452 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7453 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7454 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7455 (i8 imm:$src3)))]>, VEX_4V;
7458 let Predicates = [HasAVX] in {
7459 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7460 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7461 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7462 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7463 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7464 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7465 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7466 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7467 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7468 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7470 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7471 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7472 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7473 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7474 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7475 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7476 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7477 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7478 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7479 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7480 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7481 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7482 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7483 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7484 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7485 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7486 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7487 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7490 //===----------------------------------------------------------------------===//
7491 // VZERO - Zero YMM registers
7493 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7494 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7495 // Zero All YMM registers
7496 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7497 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7499 // Zero Upper bits of YMM registers
7500 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7501 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7504 //===----------------------------------------------------------------------===//
7505 // Half precision conversion instructions
7506 //===----------------------------------------------------------------------===//
7507 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7508 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7509 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7510 [(set RC:$dst, (Int VR128:$src))]>,
7512 let neverHasSideEffects = 1, mayLoad = 1 in
7513 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7514 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7517 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7518 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7519 (ins RC:$src1, i32i8imm:$src2),
7520 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7521 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7523 let neverHasSideEffects = 1, mayStore = 1 in
7524 def mr : Ii8<0x1D, MRMDestMem, (outs),
7525 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7526 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7530 let Predicates = [HasAVX, HasF16C] in {
7531 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7532 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7533 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7534 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7537 //===----------------------------------------------------------------------===//
7538 // AVX2 Instructions
7539 //===----------------------------------------------------------------------===//
7541 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7542 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7543 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7544 X86MemOperand x86memop> {
7545 let isCommutable = 1 in
7546 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7547 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7548 !strconcat(OpcodeStr,
7549 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7550 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7552 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7553 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7554 !strconcat(OpcodeStr,
7555 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7558 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7562 let isCommutable = 0 in {
7563 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7564 VR128, memopv2i64, i128mem>;
7565 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7566 VR256, memopv4i64, i256mem>;
7569 //===----------------------------------------------------------------------===//
7570 // VPBROADCAST - Load from memory and broadcast to all elements of the
7571 // destination operand
7573 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7574 X86MemOperand x86memop, PatFrag ld_frag,
7575 Intrinsic Int128, Intrinsic Int256> {
7576 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7577 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7578 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7579 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7582 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7583 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7585 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7586 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7589 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7592 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7593 int_x86_avx2_pbroadcastb_128,
7594 int_x86_avx2_pbroadcastb_256>;
7595 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7596 int_x86_avx2_pbroadcastw_128,
7597 int_x86_avx2_pbroadcastw_256>;
7598 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7599 int_x86_avx2_pbroadcastd_128,
7600 int_x86_avx2_pbroadcastd_256>;
7601 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7602 int_x86_avx2_pbroadcastq_128,
7603 int_x86_avx2_pbroadcastq_256>;
7605 let Predicates = [HasAVX2] in {
7606 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7607 (VPBROADCASTBrm addr:$src)>;
7608 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7609 (VPBROADCASTBYrm addr:$src)>;
7610 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7611 (VPBROADCASTWrm addr:$src)>;
7612 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7613 (VPBROADCASTWYrm addr:$src)>;
7614 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7615 (VPBROADCASTDrm addr:$src)>;
7616 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7617 (VPBROADCASTDYrm addr:$src)>;
7618 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7619 (VPBROADCASTQrm addr:$src)>;
7620 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7621 (VPBROADCASTQYrm addr:$src)>;
7623 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7624 (VPBROADCASTBrr VR128:$src)>;
7625 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7626 (VPBROADCASTBYrr VR128:$src)>;
7627 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7628 (VPBROADCASTWrr VR128:$src)>;
7629 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7630 (VPBROADCASTWYrr VR128:$src)>;
7631 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7632 (VPBROADCASTDrr VR128:$src)>;
7633 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7634 (VPBROADCASTDYrr VR128:$src)>;
7635 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7636 (VPBROADCASTQrr VR128:$src)>;
7637 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7638 (VPBROADCASTQYrr VR128:$src)>;
7639 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7640 (VBROADCASTSSrr VR128:$src)>;
7641 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7642 (VBROADCASTSSYrr VR128:$src)>;
7643 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7644 (VPBROADCASTQrr VR128:$src)>;
7645 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7646 (VBROADCASTSDYrr VR128:$src)>;
7648 // Provide fallback in case the load node that is used in the patterns above
7649 // is used by additional users, which prevents the pattern selection.
7650 let AddedComplexity = 20 in {
7651 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7652 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7653 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7654 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7655 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7656 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7658 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7659 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7660 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7661 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7662 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7663 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7667 // AVX1 broadcast patterns
7668 let Predicates = [HasAVX] in {
7669 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7670 (VBROADCASTSSYrm addr:$src)>;
7671 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7672 (VBROADCASTSDYrm addr:$src)>;
7673 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7674 (VBROADCASTSSYrm addr:$src)>;
7675 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7676 (VBROADCASTSDYrm addr:$src)>;
7677 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7678 (VBROADCASTSSrm addr:$src)>;
7679 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7680 (VBROADCASTSSrm addr:$src)>;
7682 // Provide fallback in case the load node that is used in the patterns above
7683 // is used by additional users, which prevents the pattern selection.
7684 let AddedComplexity = 20 in {
7685 // 128bit broadcasts:
7686 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7687 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7688 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7689 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7690 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7691 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7692 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7693 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7694 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7695 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7697 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7698 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7699 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7700 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7701 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7702 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7703 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7704 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7705 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7706 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7710 //===----------------------------------------------------------------------===//
7711 // VPERM - Permute instructions
7714 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7716 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7717 (ins VR256:$src1, VR256:$src2),
7718 !strconcat(OpcodeStr,
7719 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7721 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7722 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7723 (ins VR256:$src1, i256mem:$src2),
7724 !strconcat(OpcodeStr,
7725 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7727 (OpVT (X86VPermv VR256:$src1,
7728 (bitconvert (mem_frag addr:$src2)))))]>,
7732 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7733 let ExeDomain = SSEPackedSingle in
7734 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7736 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7738 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7739 (ins VR256:$src1, i8imm:$src2),
7740 !strconcat(OpcodeStr,
7741 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7743 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7744 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7745 (ins i256mem:$src1, i8imm:$src2),
7746 !strconcat(OpcodeStr,
7747 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7749 (OpVT (X86VPermi (mem_frag addr:$src1),
7750 (i8 imm:$src2))))]>, VEX;
7753 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7754 let ExeDomain = SSEPackedDouble in
7755 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7757 //===----------------------------------------------------------------------===//
7758 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7760 let AddedComplexity = 1 in {
7761 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7762 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7763 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7764 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7765 (i8 imm:$src3))))]>, VEX_4V;
7766 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7767 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7768 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7769 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7770 (i8 imm:$src3)))]>, VEX_4V;
7773 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7774 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7775 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7776 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7777 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7778 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7779 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7781 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7783 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7784 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7785 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7786 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7787 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7789 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7793 //===----------------------------------------------------------------------===//
7794 // VINSERTI128 - Insert packed integer values
7796 let neverHasSideEffects = 1 in {
7797 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7798 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7799 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7802 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7803 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7804 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7808 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7809 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7811 (VINSERTI128rr VR256:$src1, VR128:$src2,
7812 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7813 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7815 (VINSERTI128rr VR256:$src1, VR128:$src2,
7816 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7817 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7819 (VINSERTI128rr VR256:$src1, VR128:$src2,
7820 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7821 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7823 (VINSERTI128rr VR256:$src1, VR128:$src2,
7824 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7827 //===----------------------------------------------------------------------===//
7828 // VEXTRACTI128 - Extract packed integer values
7830 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7831 (ins VR256:$src1, i8imm:$src2),
7832 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7834 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7836 let neverHasSideEffects = 1, mayStore = 1 in
7837 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7838 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7839 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7841 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7842 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7843 (v2i64 (VEXTRACTI128rr
7844 (v4i64 VR256:$src1),
7845 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7846 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7847 (v4i32 (VEXTRACTI128rr
7848 (v8i32 VR256:$src1),
7849 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7850 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7851 (v8i16 (VEXTRACTI128rr
7852 (v16i16 VR256:$src1),
7853 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7854 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7855 (v16i8 (VEXTRACTI128rr
7856 (v32i8 VR256:$src1),
7857 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7860 //===----------------------------------------------------------------------===//
7861 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7863 multiclass avx2_pmovmask<string OpcodeStr,
7864 Intrinsic IntLd128, Intrinsic IntLd256,
7865 Intrinsic IntSt128, Intrinsic IntSt256> {
7866 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7867 (ins VR128:$src1, i128mem:$src2),
7868 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7869 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7870 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7871 (ins VR256:$src1, i256mem:$src2),
7872 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7873 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7874 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7875 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7876 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7877 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7878 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7879 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7881 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7884 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7885 int_x86_avx2_maskload_d,
7886 int_x86_avx2_maskload_d_256,
7887 int_x86_avx2_maskstore_d,
7888 int_x86_avx2_maskstore_d_256>;
7889 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7890 int_x86_avx2_maskload_q,
7891 int_x86_avx2_maskload_q_256,
7892 int_x86_avx2_maskstore_q,
7893 int_x86_avx2_maskstore_q_256>, VEX_W;
7896 //===----------------------------------------------------------------------===//
7897 // Variable Bit Shifts
7899 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7900 ValueType vt128, ValueType vt256> {
7901 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7902 (ins VR128:$src1, VR128:$src2),
7903 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7905 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7907 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7908 (ins VR128:$src1, i128mem:$src2),
7909 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7911 (vt128 (OpNode VR128:$src1,
7912 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7914 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7915 (ins VR256:$src1, VR256:$src2),
7916 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7918 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7920 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7921 (ins VR256:$src1, i256mem:$src2),
7922 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7924 (vt256 (OpNode VR256:$src1,
7925 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7929 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7930 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7931 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7932 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7933 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
7935 //===----------------------------------------------------------------------===//
7936 // VGATHER - GATHER Operations
7937 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
7938 X86MemOperand memop128, X86MemOperand memop256> {
7939 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
7940 (ins VR128:$src1, memop128:$src2, VR128:$mask),
7941 !strconcat(OpcodeStr,
7942 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7944 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
7945 (ins RC256:$src1, memop256:$src2, RC256:$mask),
7946 !strconcat(OpcodeStr,
7947 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7948 []>, VEX_4VOp3, VEX_L;
7951 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
7952 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
7953 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
7954 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
7955 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
7956 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
7957 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
7958 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
7959 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;