1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (store node:$val, node:$ptr), [{
102 return cast<StoreSDNode>(N)->getAlignment() >= 16;
105 // Like 'load', but always requires vector alignment.
106 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
107 return cast<LoadSDNode>(N)->getAlignment() >= 16;
110 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
111 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
112 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
113 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
114 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
115 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
117 // Like 'load', but uses special alignment checks suitable for use in
118 // memory operands in most SSE instructions, which are required to
119 // be naturally aligned on some targets but not on others.
120 // FIXME: Actually implement support for targets that don't require the
121 // alignment. This probably wants a subtarget predicate.
122 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAlignment() >= 16;
126 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
127 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
128 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
129 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
130 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
131 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
132 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 // FIXME: 8 byte alignment for mmx reads is not required
137 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
138 return cast<LoadSDNode>(N)->getAlignment() >= 8;
141 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
142 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
143 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
144 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
146 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
147 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
148 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
149 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
150 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
151 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
153 def vzmovl_v2i64 : PatFrag<(ops node:$src),
154 (bitconvert (v2i64 (X86vzmovl
155 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
156 def vzmovl_v4i32 : PatFrag<(ops node:$src),
157 (bitconvert (v4i32 (X86vzmovl
158 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
160 def vzload_v2i64 : PatFrag<(ops node:$src),
161 (bitconvert (v2i64 (X86vzload node:$src)))>;
164 def fp32imm0 : PatLeaf<(f32 fpimm), [{
165 return N->isExactlyValue(+0.0);
168 def PSxLDQ_imm : SDNodeXForm<imm, [{
169 // Transformation function: imm >> 3
170 return getI32Imm(N->getZExtValue() >> 3);
173 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
175 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
176 return getI8Imm(X86::getShuffleSHUFImmediate(N));
179 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
181 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
182 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
185 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
187 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
191 def SSE_splat_mask : PatLeaf<(build_vector), [{
192 return X86::isSplatMask(N);
193 }], SHUFFLE_get_shuf_imm>;
195 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
196 return X86::isSplatLoMask(N);
199 def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
200 return X86::isMOVDDUPMask(N);
203 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
204 return X86::isMOVHLPSMask(N);
207 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
208 return X86::isMOVHLPS_v_undef_Mask(N);
211 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHPMask(N);
215 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVLPMask(N);
219 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVLMask(N);
223 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVSHDUPMask(N);
227 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVSLDUPMask(N);
231 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isUNPCKLMask(N);
235 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isUNPCKHMask(N);
239 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKL_v_undef_Mask(N);
243 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKH_v_undef_Mask(N);
247 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isPSHUFDMask(N);
249 }], SHUFFLE_get_shuf_imm>;
251 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isPSHUFHWMask(N);
253 }], SHUFFLE_get_pshufhw_imm>;
255 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFLWMask(N);
257 }], SHUFFLE_get_pshuflw_imm>;
259 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isSHUFPMask(N);
265 }], SHUFFLE_get_shuf_imm>;
267 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isSHUFPMask(N);
269 }], SHUFFLE_get_shuf_imm>;
272 //===----------------------------------------------------------------------===//
273 // SSE scalar FP Instructions
274 //===----------------------------------------------------------------------===//
276 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
277 // scheduler into a branch sequence.
278 // These are expanded by the scheduler.
279 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
280 def CMOV_FR32 : I<0, Pseudo,
281 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
282 "#CMOV_FR32 PSEUDO!",
283 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
285 def CMOV_FR64 : I<0, Pseudo,
286 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
287 "#CMOV_FR64 PSEUDO!",
288 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
290 def CMOV_V4F32 : I<0, Pseudo,
291 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V4F32 PSEUDO!",
294 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
296 def CMOV_V2F64 : I<0, Pseudo,
297 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
298 "#CMOV_V2F64 PSEUDO!",
300 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
302 def CMOV_V2I64 : I<0, Pseudo,
303 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
304 "#CMOV_V2I64 PSEUDO!",
306 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 let neverHasSideEffects = 1 in
316 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
317 "movss\t{$src, $dst|$dst, $src}", []>;
318 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
319 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
320 "movss\t{$src, $dst|$dst, $src}",
321 [(set FR32:$dst, (loadf32 addr:$src))]>;
322 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
323 "movss\t{$src, $dst|$dst, $src}",
324 [(store FR32:$src, addr:$dst)]>;
326 // Conversion instructions
327 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
328 "cvttss2si\t{$src, $dst|$dst, $src}",
329 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
330 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
331 "cvttss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
333 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
334 "cvtsi2ss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
336 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
337 "cvtsi2ss\t{$src, $dst|$dst, $src}",
338 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
340 // Match intrinsics which expect XMM operand(s).
341 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
342 "cvtss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
344 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
345 "cvtss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (int_x86_sse_cvtss2si
347 (load addr:$src)))]>;
349 // Match intrinisics which expect MM and XMM operand(s).
350 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
351 "cvtps2pi\t{$src, $dst|$dst, $src}",
352 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
353 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
354 "cvtps2pi\t{$src, $dst|$dst, $src}",
355 [(set VR64:$dst, (int_x86_sse_cvtps2pi
356 (load addr:$src)))]>;
357 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
358 "cvttps2pi\t{$src, $dst|$dst, $src}",
359 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
360 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
361 "cvttps2pi\t{$src, $dst|$dst, $src}",
362 [(set VR64:$dst, (int_x86_sse_cvttps2pi
363 (load addr:$src)))]>;
364 let Constraints = "$src1 = $dst" in {
365 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
366 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
367 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
368 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
370 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
371 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
372 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
374 (load addr:$src2)))]>;
377 // Aliases for intrinsics
378 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
379 "cvttss2si\t{$src, $dst|$dst, $src}",
381 (int_x86_sse_cvttss2si VR128:$src))]>;
382 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
383 "cvttss2si\t{$src, $dst|$dst, $src}",
385 (int_x86_sse_cvttss2si(load addr:$src)))]>;
387 let Constraints = "$src1 = $dst" in {
388 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
389 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
390 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
391 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
393 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
394 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
395 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
396 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
397 (loadi32 addr:$src2)))]>;
400 // Comparison instructions
401 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
402 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
403 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
404 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
406 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
407 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
408 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
411 let Defs = [EFLAGS] in {
412 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
413 "ucomiss\t{$src2, $src1|$src1, $src2}",
414 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
415 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
416 "ucomiss\t{$src2, $src1|$src1, $src2}",
417 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
421 // Aliases to match intrinsics which expect XMM operand(s).
422 let Constraints = "$src1 = $dst" in {
423 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
424 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
425 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
426 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
427 VR128:$src, imm:$cc))]>;
428 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
429 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
430 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
431 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
432 (load addr:$src), imm:$cc))]>;
435 let Defs = [EFLAGS] in {
436 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
437 "ucomiss\t{$src2, $src1|$src1, $src2}",
438 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
440 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
441 "ucomiss\t{$src2, $src1|$src1, $src2}",
442 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
445 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
446 "comiss\t{$src2, $src1|$src1, $src2}",
447 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
449 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
450 "comiss\t{$src2, $src1|$src1, $src2}",
451 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
455 // Aliases of packed SSE1 instructions for scalar use. These all have names that
458 // Alias instructions that map fld0 to pxor for sse.
459 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
460 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
461 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
462 Requires<[HasSSE1]>, TB, OpSize;
464 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
466 let neverHasSideEffects = 1 in
467 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
468 "movaps\t{$src, $dst|$dst, $src}", []>;
470 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
472 let canFoldAsLoad = 1 in
473 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
474 "movaps\t{$src, $dst|$dst, $src}",
475 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
477 // Alias bitwise logical operations using SSE logical ops on packed FP values.
478 let Constraints = "$src1 = $dst" in {
479 let isCommutable = 1 in {
480 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
481 (ins FR32:$src1, FR32:$src2),
482 "andps\t{$src2, $dst|$dst, $src2}",
483 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
484 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
485 (ins FR32:$src1, FR32:$src2),
486 "orps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
488 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
489 (ins FR32:$src1, FR32:$src2),
490 "xorps\t{$src2, $dst|$dst, $src2}",
491 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
494 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
495 (ins FR32:$src1, f128mem:$src2),
496 "andps\t{$src2, $dst|$dst, $src2}",
497 [(set FR32:$dst, (X86fand FR32:$src1,
498 (memopfsf32 addr:$src2)))]>;
499 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
500 (ins FR32:$src1, f128mem:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1,
503 (memopfsf32 addr:$src2)))]>;
504 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
505 (ins FR32:$src1, f128mem:$src2),
506 "xorps\t{$src2, $dst|$dst, $src2}",
507 [(set FR32:$dst, (X86fxor FR32:$src1,
508 (memopfsf32 addr:$src2)))]>;
510 let neverHasSideEffects = 1 in {
511 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
512 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
513 "andnps\t{$src2, $dst|$dst, $src2}", []>;
515 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
516 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
517 "andnps\t{$src2, $dst|$dst, $src2}", []>;
521 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
523 /// In addition, we also have a special variant of the scalar form here to
524 /// represent the associated intrinsic operation. This form is unlike the
525 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
526 /// and leaves the top elements undefined.
528 /// These three forms can each be reg+reg or reg+mem, so there are a total of
529 /// six "instructions".
531 let Constraints = "$src1 = $dst" in {
532 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
533 SDNode OpNode, Intrinsic F32Int,
534 bit Commutable = 0> {
535 // Scalar operation, reg+reg.
536 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
537 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
538 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
539 let isCommutable = Commutable;
542 // Scalar operation, reg+mem.
543 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
544 (ins FR32:$src1, f32mem:$src2),
545 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
546 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
548 // Vector operation, reg+reg.
549 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
550 (ins VR128:$src1, VR128:$src2),
551 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
552 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
553 let isCommutable = Commutable;
556 // Vector operation, reg+mem.
557 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
558 (ins VR128:$src1, f128mem:$src2),
559 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
562 // Intrinsic operation, reg+reg.
563 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
564 (ins VR128:$src1, VR128:$src2),
565 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
566 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
567 let isCommutable = Commutable;
570 // Intrinsic operation, reg+mem.
571 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
572 (ins VR128:$src1, ssmem:$src2),
573 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
574 [(set VR128:$dst, (F32Int VR128:$src1,
575 sse_load_f32:$src2))]>;
579 // Arithmetic instructions
580 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
581 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
582 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
583 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
585 /// sse1_fp_binop_rm - Other SSE1 binops
587 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
588 /// instructions for a full-vector intrinsic form. Operations that map
589 /// onto C operators don't use this form since they just use the plain
590 /// vector form instead of having a separate vector intrinsic form.
592 /// This provides a total of eight "instructions".
594 let Constraints = "$src1 = $dst" in {
595 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
599 bit Commutable = 0> {
601 // Scalar operation, reg+reg.
602 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
603 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
604 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
605 let isCommutable = Commutable;
608 // Scalar operation, reg+mem.
609 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
610 (ins FR32:$src1, f32mem:$src2),
611 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
612 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
614 // Vector operation, reg+reg.
615 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
616 (ins VR128:$src1, VR128:$src2),
617 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
618 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
619 let isCommutable = Commutable;
622 // Vector operation, reg+mem.
623 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
624 (ins VR128:$src1, f128mem:$src2),
625 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
626 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
628 // Intrinsic operation, reg+reg.
629 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
630 (ins VR128:$src1, VR128:$src2),
631 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
633 let isCommutable = Commutable;
636 // Intrinsic operation, reg+mem.
637 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
638 (ins VR128:$src1, ssmem:$src2),
639 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
640 [(set VR128:$dst, (F32Int VR128:$src1,
641 sse_load_f32:$src2))]>;
643 // Vector intrinsic operation, reg+reg.
644 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
645 (ins VR128:$src1, VR128:$src2),
646 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
647 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
648 let isCommutable = Commutable;
651 // Vector intrinsic operation, reg+mem.
652 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
653 (ins VR128:$src1, f128mem:$src2),
654 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
655 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
659 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
660 int_x86_sse_max_ss, int_x86_sse_max_ps>;
661 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
662 int_x86_sse_min_ss, int_x86_sse_min_ps>;
664 //===----------------------------------------------------------------------===//
665 // SSE packed FP Instructions
668 let neverHasSideEffects = 1 in
669 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
670 "movaps\t{$src, $dst|$dst, $src}", []>;
671 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
672 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
673 "movaps\t{$src, $dst|$dst, $src}",
674 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
676 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
677 "movaps\t{$src, $dst|$dst, $src}",
678 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
680 let neverHasSideEffects = 1 in
681 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
682 "movups\t{$src, $dst|$dst, $src}", []>;
683 let canFoldAsLoad = 1 in
684 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
685 "movups\t{$src, $dst|$dst, $src}",
686 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
687 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
688 "movups\t{$src, $dst|$dst, $src}",
689 [(store (v4f32 VR128:$src), addr:$dst)]>;
691 // Intrinsic forms of MOVUPS load and store
692 let canFoldAsLoad = 1 in
693 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
694 "movups\t{$src, $dst|$dst, $src}",
695 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
696 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
697 "movups\t{$src, $dst|$dst, $src}",
698 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
700 let Constraints = "$src1 = $dst" in {
701 let AddedComplexity = 20 in {
702 def MOVLPSrm : PSI<0x12, MRMSrcMem,
703 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
704 "movlps\t{$src2, $dst|$dst, $src2}",
706 (v4f32 (vector_shuffle VR128:$src1,
707 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
708 MOVLP_shuffle_mask)))]>;
709 def MOVHPSrm : PSI<0x16, MRMSrcMem,
710 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
711 "movhps\t{$src2, $dst|$dst, $src2}",
713 (v4f32 (vector_shuffle VR128:$src1,
714 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
715 MOVHP_shuffle_mask)))]>;
717 } // Constraints = "$src1 = $dst"
720 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
721 "movlps\t{$src, $dst|$dst, $src}",
722 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
723 (iPTR 0))), addr:$dst)]>;
725 // v2f64 extract element 1 is always custom lowered to unpack high to low
726 // and extract element 0 so the non-store version isn't too horrible.
727 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
728 "movhps\t{$src, $dst|$dst, $src}",
729 [(store (f64 (vector_extract
730 (v2f64 (vector_shuffle
731 (bc_v2f64 (v4f32 VR128:$src)), (undef),
732 UNPCKH_shuffle_mask)), (iPTR 0))),
735 let Constraints = "$src1 = $dst" in {
736 let AddedComplexity = 20 in {
737 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
738 "movlhps\t{$src2, $dst|$dst, $src2}",
740 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
741 MOVHP_shuffle_mask)))]>;
743 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "movhlps\t{$src2, $dst|$dst, $src2}",
746 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
747 MOVHLPS_shuffle_mask)))]>;
749 } // Constraints = "$src1 = $dst"
751 let AddedComplexity = 20 in
752 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
753 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
760 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
762 /// In addition, we also have a special variant of the scalar form here to
763 /// represent the associated intrinsic operation. This form is unlike the
764 /// plain scalar form, in that it takes an entire vector (instead of a
765 /// scalar) and leaves the top elements undefined.
767 /// And, we have a special variant form for a full-vector intrinsic form.
769 /// These four forms can each have a reg or a mem operand, so there are a
770 /// total of eight "instructions".
772 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
776 bit Commutable = 0> {
777 // Scalar operation, reg.
778 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
779 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
780 [(set FR32:$dst, (OpNode FR32:$src))]> {
781 let isCommutable = Commutable;
784 // Scalar operation, mem.
785 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
786 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
787 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
789 // Vector operation, reg.
790 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
792 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
793 let isCommutable = Commutable;
796 // Vector operation, mem.
797 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
798 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
799 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
801 // Intrinsic operation, reg.
802 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
803 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
804 [(set VR128:$dst, (F32Int VR128:$src))]> {
805 let isCommutable = Commutable;
808 // Intrinsic operation, mem.
809 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
810 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
811 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
813 // Vector intrinsic operation, reg
814 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
815 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
816 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
817 let isCommutable = Commutable;
820 // Vector intrinsic operation, mem
821 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
822 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
823 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
827 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
828 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
830 // Reciprocal approximations. Note that these typically require refinement
831 // in order to obtain suitable precision.
832 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
833 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
834 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
835 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
838 let Constraints = "$src1 = $dst" in {
839 let isCommutable = 1 in {
840 def ANDPSrr : PSI<0x54, MRMSrcReg,
841 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
842 "andps\t{$src2, $dst|$dst, $src2}",
843 [(set VR128:$dst, (v2i64
844 (and VR128:$src1, VR128:$src2)))]>;
845 def ORPSrr : PSI<0x56, MRMSrcReg,
846 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
847 "orps\t{$src2, $dst|$dst, $src2}",
848 [(set VR128:$dst, (v2i64
849 (or VR128:$src1, VR128:$src2)))]>;
850 def XORPSrr : PSI<0x57, MRMSrcReg,
851 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
852 "xorps\t{$src2, $dst|$dst, $src2}",
853 [(set VR128:$dst, (v2i64
854 (xor VR128:$src1, VR128:$src2)))]>;
857 def ANDPSrm : PSI<0x54, MRMSrcMem,
858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
859 "andps\t{$src2, $dst|$dst, $src2}",
860 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
861 (memopv2i64 addr:$src2)))]>;
862 def ORPSrm : PSI<0x56, MRMSrcMem,
863 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
864 "orps\t{$src2, $dst|$dst, $src2}",
865 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
866 (memopv2i64 addr:$src2)))]>;
867 def XORPSrm : PSI<0x57, MRMSrcMem,
868 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
869 "xorps\t{$src2, $dst|$dst, $src2}",
870 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
871 (memopv2i64 addr:$src2)))]>;
872 def ANDNPSrr : PSI<0x55, MRMSrcReg,
873 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
874 "andnps\t{$src2, $dst|$dst, $src2}",
876 (v2i64 (and (xor VR128:$src1,
877 (bc_v2i64 (v4i32 immAllOnesV))),
879 def ANDNPSrm : PSI<0x55, MRMSrcMem,
880 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
881 "andnps\t{$src2, $dst|$dst, $src2}",
883 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
884 (bc_v2i64 (v4i32 immAllOnesV))),
885 (memopv2i64 addr:$src2))))]>;
888 let Constraints = "$src1 = $dst" in {
889 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
890 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
891 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
892 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
893 VR128:$src, imm:$cc))]>;
894 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
895 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
896 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
898 (memop addr:$src), imm:$cc))]>;
900 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
901 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
902 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
903 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
905 // Shuffle and unpack instructions
906 let Constraints = "$src1 = $dst" in {
907 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
908 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
909 (outs VR128:$dst), (ins VR128:$src1,
910 VR128:$src2, i32i8imm:$src3),
911 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
913 (v4f32 (vector_shuffle
914 VR128:$src1, VR128:$src2,
915 SHUFP_shuffle_mask:$src3)))]>;
916 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
917 (outs VR128:$dst), (ins VR128:$src1,
918 f128mem:$src2, i32i8imm:$src3),
919 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
921 (v4f32 (vector_shuffle
922 VR128:$src1, (memopv4f32 addr:$src2),
923 SHUFP_shuffle_mask:$src3)))]>;
925 let AddedComplexity = 10 in {
926 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
927 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
928 "unpckhps\t{$src2, $dst|$dst, $src2}",
930 (v4f32 (vector_shuffle
931 VR128:$src1, VR128:$src2,
932 UNPCKH_shuffle_mask)))]>;
933 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
934 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
935 "unpckhps\t{$src2, $dst|$dst, $src2}",
937 (v4f32 (vector_shuffle
938 VR128:$src1, (memopv4f32 addr:$src2),
939 UNPCKH_shuffle_mask)))]>;
941 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
942 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
943 "unpcklps\t{$src2, $dst|$dst, $src2}",
945 (v4f32 (vector_shuffle
946 VR128:$src1, VR128:$src2,
947 UNPCKL_shuffle_mask)))]>;
948 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
949 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
950 "unpcklps\t{$src2, $dst|$dst, $src2}",
952 (v4f32 (vector_shuffle
953 VR128:$src1, (memopv4f32 addr:$src2),
954 UNPCKL_shuffle_mask)))]>;
956 } // Constraints = "$src1 = $dst"
959 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
960 "movmskps\t{$src, $dst|$dst, $src}",
961 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
962 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
963 "movmskpd\t{$src, $dst|$dst, $src}",
964 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
966 // Prefetch intrinsic.
967 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
968 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
969 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
970 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
971 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
972 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
973 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
974 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
976 // Non-temporal stores
977 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
978 "movntps\t{$src, $dst|$dst, $src}",
979 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
981 // Load, store, and memory fence
982 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
985 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
986 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
987 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
988 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
990 // Alias instructions that map zero vector to pxor / xorp* for sse.
991 // We set canFoldAsLoad because this can be converted to a constant-pool
992 // load of an all-zeros value if folding it would be beneficial.
993 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
994 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
996 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
998 let Predicates = [HasSSE1] in {
999 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1001 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1003 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1006 // FR32 to 128-bit vector conversion.
1007 let isAsCheapAsAMove = 1 in
1008 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1009 "movss\t{$src, $dst|$dst, $src}",
1011 (v4f32 (scalar_to_vector FR32:$src)))]>;
1012 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1013 "movss\t{$src, $dst|$dst, $src}",
1015 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1017 // FIXME: may not be able to eliminate this movss with coalescing the src and
1018 // dest register classes are different. We really want to write this pattern
1020 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1021 // (f32 FR32:$src)>;
1022 let isAsCheapAsAMove = 1 in
1023 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1024 "movss\t{$src, $dst|$dst, $src}",
1025 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1027 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1028 "movss\t{$src, $dst|$dst, $src}",
1029 [(store (f32 (vector_extract (v4f32 VR128:$src),
1030 (iPTR 0))), addr:$dst)]>;
1033 // Move to lower bits of a VR128, leaving upper bits alone.
1034 // Three operand (but two address) aliases.
1035 let Constraints = "$src1 = $dst" in {
1036 let neverHasSideEffects = 1 in
1037 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1038 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1039 "movss\t{$src2, $dst|$dst, $src2}", []>;
1041 let AddedComplexity = 15 in
1042 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1043 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1044 "movss\t{$src2, $dst|$dst, $src2}",
1046 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1047 MOVL_shuffle_mask)))]>;
1050 // Move to lower bits of a VR128 and zeroing upper bits.
1051 // Loading from memory automatically zeroing upper bits.
1052 let AddedComplexity = 20 in
1053 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1054 "movss\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1056 (loadf32 addr:$src))))))]>;
1058 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1059 (MOVZSS2PSrm addr:$src)>;
1061 //===----------------------------------------------------------------------===//
1062 // SSE2 Instructions
1063 //===----------------------------------------------------------------------===//
1065 // Move Instructions
1066 let neverHasSideEffects = 1 in
1067 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1068 "movsd\t{$src, $dst|$dst, $src}", []>;
1069 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1070 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1071 "movsd\t{$src, $dst|$dst, $src}",
1072 [(set FR64:$dst, (loadf64 addr:$src))]>;
1073 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1074 "movsd\t{$src, $dst|$dst, $src}",
1075 [(store FR64:$src, addr:$dst)]>;
1077 // Conversion instructions
1078 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1079 "cvttsd2si\t{$src, $dst|$dst, $src}",
1080 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1081 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1082 "cvttsd2si\t{$src, $dst|$dst, $src}",
1083 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1084 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1085 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1086 [(set FR32:$dst, (fround FR64:$src))]>;
1087 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1088 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1089 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1090 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1091 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1092 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1093 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1094 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1095 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1097 // SSE2 instructions with XS prefix
1098 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1099 "cvtss2sd\t{$src, $dst|$dst, $src}",
1100 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1101 Requires<[HasSSE2]>;
1102 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1103 "cvtss2sd\t{$src, $dst|$dst, $src}",
1104 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1105 Requires<[HasSSE2]>;
1107 // Match intrinsics which expect XMM operand(s).
1108 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1109 "cvtsd2si\t{$src, $dst|$dst, $src}",
1110 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1111 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1112 "cvtsd2si\t{$src, $dst|$dst, $src}",
1113 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1114 (load addr:$src)))]>;
1116 // Match intrinisics which expect MM and XMM operand(s).
1117 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1118 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1119 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1120 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1121 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1122 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1123 (memop addr:$src)))]>;
1124 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1125 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1126 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1127 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1128 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1129 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1130 (memop addr:$src)))]>;
1131 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1132 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1133 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1134 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1135 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1137 (load addr:$src)))]>;
1139 // Aliases for intrinsics
1140 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1141 "cvttsd2si\t{$src, $dst|$dst, $src}",
1143 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1144 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1145 "cvttsd2si\t{$src, $dst|$dst, $src}",
1146 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1147 (load addr:$src)))]>;
1149 // Comparison instructions
1150 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1151 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1152 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1153 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1155 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1156 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1157 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1160 let Defs = [EFLAGS] in {
1161 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1162 "ucomisd\t{$src2, $src1|$src1, $src2}",
1163 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1164 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1165 "ucomisd\t{$src2, $src1|$src1, $src2}",
1166 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1167 (implicit EFLAGS)]>;
1168 } // Defs = [EFLAGS]
1170 // Aliases to match intrinsics which expect XMM operand(s).
1171 let Constraints = "$src1 = $dst" in {
1172 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1173 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1174 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1175 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1176 VR128:$src, imm:$cc))]>;
1177 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1178 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1179 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1180 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1181 (load addr:$src), imm:$cc))]>;
1184 let Defs = [EFLAGS] in {
1185 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1186 "ucomisd\t{$src2, $src1|$src1, $src2}",
1187 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1188 (implicit EFLAGS)]>;
1189 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1190 "ucomisd\t{$src2, $src1|$src1, $src2}",
1191 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1192 (implicit EFLAGS)]>;
1194 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1195 "comisd\t{$src2, $src1|$src1, $src2}",
1196 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1197 (implicit EFLAGS)]>;
1198 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1199 "comisd\t{$src2, $src1|$src1, $src2}",
1200 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1201 (implicit EFLAGS)]>;
1202 } // Defs = [EFLAGS]
1204 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1207 // Alias instructions that map fld0 to pxor for sse.
1208 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1209 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1210 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1211 Requires<[HasSSE2]>, TB, OpSize;
1213 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1215 let neverHasSideEffects = 1 in
1216 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1217 "movapd\t{$src, $dst|$dst, $src}", []>;
1219 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1221 let canFoldAsLoad = 1 in
1222 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1223 "movapd\t{$src, $dst|$dst, $src}",
1224 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1226 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1227 let Constraints = "$src1 = $dst" in {
1228 let isCommutable = 1 in {
1229 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1230 (ins FR64:$src1, FR64:$src2),
1231 "andpd\t{$src2, $dst|$dst, $src2}",
1232 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1233 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1234 (ins FR64:$src1, FR64:$src2),
1235 "orpd\t{$src2, $dst|$dst, $src2}",
1236 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1237 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1238 (ins FR64:$src1, FR64:$src2),
1239 "xorpd\t{$src2, $dst|$dst, $src2}",
1240 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1243 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1244 (ins FR64:$src1, f128mem:$src2),
1245 "andpd\t{$src2, $dst|$dst, $src2}",
1246 [(set FR64:$dst, (X86fand FR64:$src1,
1247 (memopfsf64 addr:$src2)))]>;
1248 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1249 (ins FR64:$src1, f128mem:$src2),
1250 "orpd\t{$src2, $dst|$dst, $src2}",
1251 [(set FR64:$dst, (X86for FR64:$src1,
1252 (memopfsf64 addr:$src2)))]>;
1253 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1254 (ins FR64:$src1, f128mem:$src2),
1255 "xorpd\t{$src2, $dst|$dst, $src2}",
1256 [(set FR64:$dst, (X86fxor FR64:$src1,
1257 (memopfsf64 addr:$src2)))]>;
1259 let neverHasSideEffects = 1 in {
1260 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1261 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1262 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1264 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1265 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1266 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1270 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1272 /// In addition, we also have a special variant of the scalar form here to
1273 /// represent the associated intrinsic operation. This form is unlike the
1274 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1275 /// and leaves the top elements undefined.
1277 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1278 /// six "instructions".
1280 let Constraints = "$src1 = $dst" in {
1281 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1282 SDNode OpNode, Intrinsic F64Int,
1283 bit Commutable = 0> {
1284 // Scalar operation, reg+reg.
1285 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1286 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1287 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1288 let isCommutable = Commutable;
1291 // Scalar operation, reg+mem.
1292 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1293 (ins FR64:$src1, f64mem:$src2),
1294 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1295 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1297 // Vector operation, reg+reg.
1298 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1299 (ins VR128:$src1, VR128:$src2),
1300 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1301 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1302 let isCommutable = Commutable;
1305 // Vector operation, reg+mem.
1306 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1307 (ins VR128:$src1, f128mem:$src2),
1308 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1309 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1311 // Intrinsic operation, reg+reg.
1312 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1315 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1316 let isCommutable = Commutable;
1319 // Intrinsic operation, reg+mem.
1320 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1321 (ins VR128:$src1, sdmem:$src2),
1322 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1323 [(set VR128:$dst, (F64Int VR128:$src1,
1324 sse_load_f64:$src2))]>;
1328 // Arithmetic instructions
1329 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1330 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1331 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1332 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1334 /// sse2_fp_binop_rm - Other SSE2 binops
1336 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1337 /// instructions for a full-vector intrinsic form. Operations that map
1338 /// onto C operators don't use this form since they just use the plain
1339 /// vector form instead of having a separate vector intrinsic form.
1341 /// This provides a total of eight "instructions".
1343 let Constraints = "$src1 = $dst" in {
1344 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1348 bit Commutable = 0> {
1350 // Scalar operation, reg+reg.
1351 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1352 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1353 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1354 let isCommutable = Commutable;
1357 // Scalar operation, reg+mem.
1358 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1359 (ins FR64:$src1, f64mem:$src2),
1360 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1361 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1363 // Vector operation, reg+reg.
1364 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1367 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1368 let isCommutable = Commutable;
1371 // Vector operation, reg+mem.
1372 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1373 (ins VR128:$src1, f128mem:$src2),
1374 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1375 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1377 // Intrinsic operation, reg+reg.
1378 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1379 (ins VR128:$src1, VR128:$src2),
1380 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1381 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1382 let isCommutable = Commutable;
1385 // Intrinsic operation, reg+mem.
1386 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1387 (ins VR128:$src1, sdmem:$src2),
1388 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1389 [(set VR128:$dst, (F64Int VR128:$src1,
1390 sse_load_f64:$src2))]>;
1392 // Vector intrinsic operation, reg+reg.
1393 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1396 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1397 let isCommutable = Commutable;
1400 // Vector intrinsic operation, reg+mem.
1401 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1402 (ins VR128:$src1, f128mem:$src2),
1403 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1404 [(set VR128:$dst, (V2F64Int VR128:$src1,
1405 (memopv2f64 addr:$src2)))]>;
1409 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1410 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1411 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1412 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1414 //===----------------------------------------------------------------------===//
1415 // SSE packed FP Instructions
1417 // Move Instructions
1418 let neverHasSideEffects = 1 in
1419 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1420 "movapd\t{$src, $dst|$dst, $src}", []>;
1421 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1422 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1423 "movapd\t{$src, $dst|$dst, $src}",
1424 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1426 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1427 "movapd\t{$src, $dst|$dst, $src}",
1428 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1430 let neverHasSideEffects = 1 in
1431 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1432 "movupd\t{$src, $dst|$dst, $src}", []>;
1433 let canFoldAsLoad = 1 in
1434 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1435 "movupd\t{$src, $dst|$dst, $src}",
1436 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1437 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1438 "movupd\t{$src, $dst|$dst, $src}",
1439 [(store (v2f64 VR128:$src), addr:$dst)]>;
1441 // Intrinsic forms of MOVUPD load and store
1442 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1443 "movupd\t{$src, $dst|$dst, $src}",
1444 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1445 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1446 "movupd\t{$src, $dst|$dst, $src}",
1447 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1449 let Constraints = "$src1 = $dst" in {
1450 let AddedComplexity = 20 in {
1451 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1452 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1453 "movlpd\t{$src2, $dst|$dst, $src2}",
1455 (v2f64 (vector_shuffle VR128:$src1,
1456 (scalar_to_vector (loadf64 addr:$src2)),
1457 MOVLP_shuffle_mask)))]>;
1458 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1459 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1460 "movhpd\t{$src2, $dst|$dst, $src2}",
1462 (v2f64 (vector_shuffle VR128:$src1,
1463 (scalar_to_vector (loadf64 addr:$src2)),
1464 MOVHP_shuffle_mask)))]>;
1465 } // AddedComplexity
1466 } // Constraints = "$src1 = $dst"
1468 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1469 "movlpd\t{$src, $dst|$dst, $src}",
1470 [(store (f64 (vector_extract (v2f64 VR128:$src),
1471 (iPTR 0))), addr:$dst)]>;
1473 // v2f64 extract element 1 is always custom lowered to unpack high to low
1474 // and extract element 0 so the non-store version isn't too horrible.
1475 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1476 "movhpd\t{$src, $dst|$dst, $src}",
1477 [(store (f64 (vector_extract
1478 (v2f64 (vector_shuffle VR128:$src, (undef),
1479 UNPCKH_shuffle_mask)), (iPTR 0))),
1482 // SSE2 instructions without OpSize prefix
1483 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1484 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1485 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1486 TB, Requires<[HasSSE2]>;
1487 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1488 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1489 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1490 (bitconvert (memopv2i64 addr:$src))))]>,
1491 TB, Requires<[HasSSE2]>;
1493 // SSE2 instructions with XS prefix
1494 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1495 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1496 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1497 XS, Requires<[HasSSE2]>;
1498 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1499 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1500 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1501 (bitconvert (memopv2i64 addr:$src))))]>,
1502 XS, Requires<[HasSSE2]>;
1504 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1505 "cvtps2dq\t{$src, $dst|$dst, $src}",
1506 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1507 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1508 "cvtps2dq\t{$src, $dst|$dst, $src}",
1509 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1510 (memop addr:$src)))]>;
1511 // SSE2 packed instructions with XS prefix
1512 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1513 "cvttps2dq\t{$src, $dst|$dst, $src}",
1514 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1515 XS, Requires<[HasSSE2]>;
1516 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1517 "cvttps2dq\t{$src, $dst|$dst, $src}",
1518 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1519 (memop addr:$src)))]>,
1520 XS, Requires<[HasSSE2]>;
1522 // SSE2 packed instructions with XD prefix
1523 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1524 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1525 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1526 XD, Requires<[HasSSE2]>;
1527 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1528 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1529 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1530 (memop addr:$src)))]>,
1531 XD, Requires<[HasSSE2]>;
1533 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1534 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1535 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1536 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1537 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1538 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1539 (memop addr:$src)))]>;
1541 // SSE2 instructions without OpSize prefix
1542 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1543 "cvtps2pd\t{$src, $dst|$dst, $src}",
1544 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1545 TB, Requires<[HasSSE2]>;
1546 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1547 "cvtps2pd\t{$src, $dst|$dst, $src}",
1548 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1549 (load addr:$src)))]>,
1550 TB, Requires<[HasSSE2]>;
1552 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1553 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1554 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1555 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1556 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1557 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1558 (memop addr:$src)))]>;
1560 // Match intrinsics which expect XMM operand(s).
1561 // Aliases for intrinsics
1562 let Constraints = "$src1 = $dst" in {
1563 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1564 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1565 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1566 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1568 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1569 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1570 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1571 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1572 (loadi32 addr:$src2)))]>;
1573 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1575 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1576 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1578 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1579 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1580 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1581 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1582 (load addr:$src2)))]>;
1583 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1584 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1585 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1586 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1587 VR128:$src2))]>, XS,
1588 Requires<[HasSSE2]>;
1589 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1590 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1591 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1592 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1593 (load addr:$src2)))]>, XS,
1594 Requires<[HasSSE2]>;
1599 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1601 /// In addition, we also have a special variant of the scalar form here to
1602 /// represent the associated intrinsic operation. This form is unlike the
1603 /// plain scalar form, in that it takes an entire vector (instead of a
1604 /// scalar) and leaves the top elements undefined.
1606 /// And, we have a special variant form for a full-vector intrinsic form.
1608 /// These four forms can each have a reg or a mem operand, so there are a
1609 /// total of eight "instructions".
1611 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1615 bit Commutable = 0> {
1616 // Scalar operation, reg.
1617 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1618 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1619 [(set FR64:$dst, (OpNode FR64:$src))]> {
1620 let isCommutable = Commutable;
1623 // Scalar operation, mem.
1624 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1625 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1626 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1628 // Vector operation, reg.
1629 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1630 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1631 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1632 let isCommutable = Commutable;
1635 // Vector operation, mem.
1636 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1637 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1638 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1640 // Intrinsic operation, reg.
1641 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1642 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1643 [(set VR128:$dst, (F64Int VR128:$src))]> {
1644 let isCommutable = Commutable;
1647 // Intrinsic operation, mem.
1648 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1649 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1650 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1652 // Vector intrinsic operation, reg
1653 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1654 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1655 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1656 let isCommutable = Commutable;
1659 // Vector intrinsic operation, mem
1660 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1661 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1662 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1666 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1667 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1669 // There is no f64 version of the reciprocal approximation instructions.
1672 let Constraints = "$src1 = $dst" in {
1673 let isCommutable = 1 in {
1674 def ANDPDrr : PDI<0x54, MRMSrcReg,
1675 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1676 "andpd\t{$src2, $dst|$dst, $src2}",
1678 (and (bc_v2i64 (v2f64 VR128:$src1)),
1679 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1680 def ORPDrr : PDI<0x56, MRMSrcReg,
1681 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1682 "orpd\t{$src2, $dst|$dst, $src2}",
1684 (or (bc_v2i64 (v2f64 VR128:$src1)),
1685 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1686 def XORPDrr : PDI<0x57, MRMSrcReg,
1687 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1688 "xorpd\t{$src2, $dst|$dst, $src2}",
1690 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1691 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1694 def ANDPDrm : PDI<0x54, MRMSrcMem,
1695 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1696 "andpd\t{$src2, $dst|$dst, $src2}",
1698 (and (bc_v2i64 (v2f64 VR128:$src1)),
1699 (memopv2i64 addr:$src2)))]>;
1700 def ORPDrm : PDI<0x56, MRMSrcMem,
1701 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1702 "orpd\t{$src2, $dst|$dst, $src2}",
1704 (or (bc_v2i64 (v2f64 VR128:$src1)),
1705 (memopv2i64 addr:$src2)))]>;
1706 def XORPDrm : PDI<0x57, MRMSrcMem,
1707 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1708 "xorpd\t{$src2, $dst|$dst, $src2}",
1710 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1711 (memopv2i64 addr:$src2)))]>;
1712 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1713 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1714 "andnpd\t{$src2, $dst|$dst, $src2}",
1716 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1717 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1718 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1719 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1720 "andnpd\t{$src2, $dst|$dst, $src2}",
1722 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1723 (memopv2i64 addr:$src2)))]>;
1726 let Constraints = "$src1 = $dst" in {
1727 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1729 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1730 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1731 VR128:$src, imm:$cc))]>;
1732 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1733 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1734 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1735 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1736 (memop addr:$src), imm:$cc))]>;
1738 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1739 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1740 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1741 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1743 // Shuffle and unpack instructions
1744 let Constraints = "$src1 = $dst" in {
1745 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1746 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1747 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1748 [(set VR128:$dst, (v2f64 (vector_shuffle
1749 VR128:$src1, VR128:$src2,
1750 SHUFP_shuffle_mask:$src3)))]>;
1751 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1752 (outs VR128:$dst), (ins VR128:$src1,
1753 f128mem:$src2, i8imm:$src3),
1754 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1756 (v2f64 (vector_shuffle
1757 VR128:$src1, (memopv2f64 addr:$src2),
1758 SHUFP_shuffle_mask:$src3)))]>;
1760 let AddedComplexity = 10 in {
1761 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1762 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1763 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1765 (v2f64 (vector_shuffle
1766 VR128:$src1, VR128:$src2,
1767 UNPCKH_shuffle_mask)))]>;
1768 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1769 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1770 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1772 (v2f64 (vector_shuffle
1773 VR128:$src1, (memopv2f64 addr:$src2),
1774 UNPCKH_shuffle_mask)))]>;
1776 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1780 (v2f64 (vector_shuffle
1781 VR128:$src1, VR128:$src2,
1782 UNPCKL_shuffle_mask)))]>;
1783 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1784 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1785 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1787 (v2f64 (vector_shuffle
1788 VR128:$src1, (memopv2f64 addr:$src2),
1789 UNPCKL_shuffle_mask)))]>;
1790 } // AddedComplexity
1791 } // Constraints = "$src1 = $dst"
1794 //===----------------------------------------------------------------------===//
1795 // SSE integer instructions
1797 // Move Instructions
1798 let neverHasSideEffects = 1 in
1799 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1800 "movdqa\t{$src, $dst|$dst, $src}", []>;
1801 let canFoldAsLoad = 1, mayLoad = 1 in
1802 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1803 "movdqa\t{$src, $dst|$dst, $src}",
1804 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1806 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1807 "movdqa\t{$src, $dst|$dst, $src}",
1808 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1809 let canFoldAsLoad = 1, mayLoad = 1 in
1810 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1811 "movdqu\t{$src, $dst|$dst, $src}",
1812 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1813 XS, Requires<[HasSSE2]>;
1815 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1816 "movdqu\t{$src, $dst|$dst, $src}",
1817 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1818 XS, Requires<[HasSSE2]>;
1820 // Intrinsic forms of MOVDQU load and store
1821 let canFoldAsLoad = 1 in
1822 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1823 "movdqu\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1825 XS, Requires<[HasSSE2]>;
1826 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1827 "movdqu\t{$src, $dst|$dst, $src}",
1828 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1829 XS, Requires<[HasSSE2]>;
1831 let Constraints = "$src1 = $dst" in {
1833 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1834 bit Commutable = 0> {
1835 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1837 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1838 let isCommutable = Commutable;
1840 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1842 [(set VR128:$dst, (IntId VR128:$src1,
1843 (bitconvert (memopv2i64 addr:$src2))))]>;
1846 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1848 Intrinsic IntId, Intrinsic IntId2> {
1849 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1850 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1851 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1852 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1854 [(set VR128:$dst, (IntId VR128:$src1,
1855 (bitconvert (memopv2i64 addr:$src2))))]>;
1856 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1857 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1858 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1861 /// PDI_binop_rm - Simple SSE2 binary operator.
1862 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1863 ValueType OpVT, bit Commutable = 0> {
1864 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1865 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1866 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1867 let isCommutable = Commutable;
1869 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1870 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1871 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1872 (bitconvert (memopv2i64 addr:$src2)))))]>;
1875 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1877 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1878 /// to collapse (bitconvert VT to VT) into its operand.
1880 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1881 bit Commutable = 0> {
1882 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1883 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1884 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1885 let isCommutable = Commutable;
1887 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1888 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1889 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1892 } // Constraints = "$src1 = $dst"
1894 // 128-bit Integer Arithmetic
1896 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1897 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1898 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1899 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1901 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1902 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1903 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1904 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1906 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1907 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1908 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1909 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1911 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1912 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1913 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1914 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1916 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1918 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1919 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1920 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1922 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1924 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1925 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1928 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1929 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1930 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1931 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1932 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1935 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1936 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1937 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1938 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1939 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1940 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1942 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1943 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1944 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1945 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1946 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1947 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1949 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1950 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1951 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1952 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1954 // 128-bit logical shifts.
1955 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1956 def PSLLDQri : PDIi8<0x73, MRM7r,
1957 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1958 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1959 def PSRLDQri : PDIi8<0x73, MRM3r,
1960 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1961 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1962 // PSRADQri doesn't exist in SSE[1-3].
1965 let Predicates = [HasSSE2] in {
1966 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1967 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1968 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1969 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1970 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1971 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1972 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1973 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1974 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1975 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1977 // Shift up / down and insert zero's.
1978 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1979 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1980 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1981 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1985 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1986 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1987 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1989 let Constraints = "$src1 = $dst" in {
1990 def PANDNrr : PDI<0xDF, MRMSrcReg,
1991 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1992 "pandn\t{$src2, $dst|$dst, $src2}",
1993 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1996 def PANDNrm : PDI<0xDF, MRMSrcMem,
1997 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1998 "pandn\t{$src2, $dst|$dst, $src2}",
1999 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2000 (memopv2i64 addr:$src2))))]>;
2003 // SSE2 Integer comparison
2004 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2005 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2006 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2007 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2008 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2009 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2011 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2012 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2013 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2014 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2015 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2016 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2017 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2018 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2019 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2020 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2021 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2022 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2024 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2025 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2026 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2027 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2028 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2029 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2030 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2031 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2032 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2033 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2034 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2035 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2038 // Pack instructions
2039 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2040 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2041 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2043 // Shuffle and unpack instructions
2044 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2045 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2046 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2047 [(set VR128:$dst, (v4i32 (vector_shuffle
2048 VR128:$src1, (undef),
2049 PSHUFD_shuffle_mask:$src2)))]>;
2050 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2051 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2052 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2053 [(set VR128:$dst, (v4i32 (vector_shuffle
2054 (bc_v4i32(memopv2i64 addr:$src1)),
2056 PSHUFD_shuffle_mask:$src2)))]>;
2058 // SSE2 with ImmT == Imm8 and XS prefix.
2059 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2060 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2061 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set VR128:$dst, (v8i16 (vector_shuffle
2063 VR128:$src1, (undef),
2064 PSHUFHW_shuffle_mask:$src2)))]>,
2065 XS, Requires<[HasSSE2]>;
2066 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2067 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2068 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2069 [(set VR128:$dst, (v8i16 (vector_shuffle
2070 (bc_v8i16 (memopv2i64 addr:$src1)),
2072 PSHUFHW_shuffle_mask:$src2)))]>,
2073 XS, Requires<[HasSSE2]>;
2075 // SSE2 with ImmT == Imm8 and XD prefix.
2076 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2077 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2078 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2079 [(set VR128:$dst, (v8i16 (vector_shuffle
2080 VR128:$src1, (undef),
2081 PSHUFLW_shuffle_mask:$src2)))]>,
2082 XD, Requires<[HasSSE2]>;
2083 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2084 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2085 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2086 [(set VR128:$dst, (v8i16 (vector_shuffle
2087 (bc_v8i16 (memopv2i64 addr:$src1)),
2089 PSHUFLW_shuffle_mask:$src2)))]>,
2090 XD, Requires<[HasSSE2]>;
2093 let Constraints = "$src1 = $dst" in {
2094 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2095 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2096 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2098 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2099 UNPCKL_shuffle_mask)))]>;
2100 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2101 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2102 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2104 (v16i8 (vector_shuffle VR128:$src1,
2105 (bc_v16i8 (memopv2i64 addr:$src2)),
2106 UNPCKL_shuffle_mask)))]>;
2107 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2108 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2109 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2111 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2112 UNPCKL_shuffle_mask)))]>;
2113 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2114 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2115 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2117 (v8i16 (vector_shuffle VR128:$src1,
2118 (bc_v8i16 (memopv2i64 addr:$src2)),
2119 UNPCKL_shuffle_mask)))]>;
2120 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2121 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2122 "punpckldq\t{$src2, $dst|$dst, $src2}",
2124 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2125 UNPCKL_shuffle_mask)))]>;
2126 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2127 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2128 "punpckldq\t{$src2, $dst|$dst, $src2}",
2130 (v4i32 (vector_shuffle VR128:$src1,
2131 (bc_v4i32 (memopv2i64 addr:$src2)),
2132 UNPCKL_shuffle_mask)))]>;
2133 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2134 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2135 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2137 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2138 UNPCKL_shuffle_mask)))]>;
2139 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2140 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2141 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2143 (v2i64 (vector_shuffle VR128:$src1,
2144 (memopv2i64 addr:$src2),
2145 UNPCKL_shuffle_mask)))]>;
2147 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2148 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2149 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2151 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2152 UNPCKH_shuffle_mask)))]>;
2153 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2154 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2155 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2157 (v16i8 (vector_shuffle VR128:$src1,
2158 (bc_v16i8 (memopv2i64 addr:$src2)),
2159 UNPCKH_shuffle_mask)))]>;
2160 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2161 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2162 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2164 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2165 UNPCKH_shuffle_mask)))]>;
2166 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2167 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2168 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2170 (v8i16 (vector_shuffle VR128:$src1,
2171 (bc_v8i16 (memopv2i64 addr:$src2)),
2172 UNPCKH_shuffle_mask)))]>;
2173 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2174 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2175 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2177 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2178 UNPCKH_shuffle_mask)))]>;
2179 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2180 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2181 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2183 (v4i32 (vector_shuffle VR128:$src1,
2184 (bc_v4i32 (memopv2i64 addr:$src2)),
2185 UNPCKH_shuffle_mask)))]>;
2186 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2187 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2188 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2190 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2191 UNPCKH_shuffle_mask)))]>;
2192 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2193 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2194 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2196 (v2i64 (vector_shuffle VR128:$src1,
2197 (memopv2i64 addr:$src2),
2198 UNPCKH_shuffle_mask)))]>;
2202 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2203 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2204 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2205 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2207 let Constraints = "$src1 = $dst" in {
2208 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2209 (outs VR128:$dst), (ins VR128:$src1,
2210 GR32:$src2, i32i8imm:$src3),
2211 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2213 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2214 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2215 (outs VR128:$dst), (ins VR128:$src1,
2216 i16mem:$src2, i32i8imm:$src3),
2217 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2219 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2224 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2225 "pmovmskb\t{$src, $dst|$dst, $src}",
2226 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2228 // Conditional store
2230 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2231 "maskmovdqu\t{$mask, $src|$src, $mask}",
2232 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2235 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2236 "maskmovdqu\t{$mask, $src|$src, $mask}",
2237 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2239 // Non-temporal stores
2240 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2241 "movntpd\t{$src, $dst|$dst, $src}",
2242 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2243 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2244 "movntdq\t{$src, $dst|$dst, $src}",
2245 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2246 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2247 "movnti\t{$src, $dst|$dst, $src}",
2248 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2249 TB, Requires<[HasSSE2]>;
2252 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2253 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2254 TB, Requires<[HasSSE2]>;
2256 // Load, store, and memory fence
2257 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2258 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2259 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2260 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2262 //TODO: custom lower this so as to never even generate the noop
2263 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2265 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2266 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2267 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2270 // Alias instructions that map zero vector to pxor / xorp* for sse.
2271 // We set canFoldAsLoad because this can be converted to a constant-pool
2272 // load of an all-ones value if folding it would be beneficial.
2273 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2274 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2275 "pcmpeqd\t$dst, $dst",
2276 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2278 // FR64 to 128-bit vector conversion.
2279 let isAsCheapAsAMove = 1 in
2280 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2281 "movsd\t{$src, $dst|$dst, $src}",
2283 (v2f64 (scalar_to_vector FR64:$src)))]>;
2284 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2285 "movsd\t{$src, $dst|$dst, $src}",
2287 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2289 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2290 "movd\t{$src, $dst|$dst, $src}",
2292 (v4i32 (scalar_to_vector GR32:$src)))]>;
2293 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2294 "movd\t{$src, $dst|$dst, $src}",
2296 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2298 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2299 "movd\t{$src, $dst|$dst, $src}",
2300 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2302 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2303 "movd\t{$src, $dst|$dst, $src}",
2304 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2306 // SSE2 instructions with XS prefix
2307 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2308 "movq\t{$src, $dst|$dst, $src}",
2310 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2311 Requires<[HasSSE2]>;
2312 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2313 "movq\t{$src, $dst|$dst, $src}",
2314 [(store (i64 (vector_extract (v2i64 VR128:$src),
2315 (iPTR 0))), addr:$dst)]>;
2317 // FIXME: may not be able to eliminate this movss with coalescing the src and
2318 // dest register classes are different. We really want to write this pattern
2320 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2321 // (f32 FR32:$src)>;
2322 let isAsCheapAsAMove = 1 in
2323 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2324 "movsd\t{$src, $dst|$dst, $src}",
2325 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2327 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2328 "movsd\t{$src, $dst|$dst, $src}",
2329 [(store (f64 (vector_extract (v2f64 VR128:$src),
2330 (iPTR 0))), addr:$dst)]>;
2331 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2332 "movd\t{$src, $dst|$dst, $src}",
2333 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2335 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2336 "movd\t{$src, $dst|$dst, $src}",
2337 [(store (i32 (vector_extract (v4i32 VR128:$src),
2338 (iPTR 0))), addr:$dst)]>;
2340 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2341 "movd\t{$src, $dst|$dst, $src}",
2342 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2343 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2344 "movd\t{$src, $dst|$dst, $src}",
2345 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2348 // Move to lower bits of a VR128, leaving upper bits alone.
2349 // Three operand (but two address) aliases.
2350 let Constraints = "$src1 = $dst" in {
2351 let neverHasSideEffects = 1 in
2352 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2353 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2354 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2356 let AddedComplexity = 15 in
2357 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2358 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2359 "movsd\t{$src2, $dst|$dst, $src2}",
2361 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2362 MOVL_shuffle_mask)))]>;
2365 // Store / copy lower 64-bits of a XMM register.
2366 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2367 "movq\t{$src, $dst|$dst, $src}",
2368 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2370 // Move to lower bits of a VR128 and zeroing upper bits.
2371 // Loading from memory automatically zeroing upper bits.
2372 let AddedComplexity = 20 in {
2373 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2374 "movsd\t{$src, $dst|$dst, $src}",
2376 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2377 (loadf64 addr:$src))))))]>;
2379 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2380 (MOVZSD2PDrm addr:$src)>;
2381 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2382 (MOVZSD2PDrm addr:$src)>;
2383 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2386 // movd / movq to XMM register zero-extends
2387 let AddedComplexity = 15 in {
2388 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2389 "movd\t{$src, $dst|$dst, $src}",
2390 [(set VR128:$dst, (v4i32 (X86vzmovl
2391 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2392 // This is X86-64 only.
2393 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2394 "mov{d|q}\t{$src, $dst|$dst, $src}",
2395 [(set VR128:$dst, (v2i64 (X86vzmovl
2396 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2399 let AddedComplexity = 20 in {
2400 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2401 "movd\t{$src, $dst|$dst, $src}",
2403 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2404 (loadi32 addr:$src))))))]>;
2406 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2407 (MOVZDI2PDIrm addr:$src)>;
2408 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2409 (MOVZDI2PDIrm addr:$src)>;
2410 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2411 (MOVZDI2PDIrm addr:$src)>;
2413 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2414 "movq\t{$src, $dst|$dst, $src}",
2416 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2417 (loadi64 addr:$src))))))]>, XS,
2418 Requires<[HasSSE2]>;
2420 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2421 (MOVZQI2PQIrm addr:$src)>;
2422 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2423 (MOVZQI2PQIrm addr:$src)>;
2424 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2427 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2428 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2429 let AddedComplexity = 15 in
2430 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2431 "movq\t{$src, $dst|$dst, $src}",
2432 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2433 XS, Requires<[HasSSE2]>;
2435 let AddedComplexity = 20 in {
2436 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2437 "movq\t{$src, $dst|$dst, $src}",
2438 [(set VR128:$dst, (v2i64 (X86vzmovl
2439 (loadv2i64 addr:$src))))]>,
2440 XS, Requires<[HasSSE2]>;
2442 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2443 (MOVZPQILo2PQIrm addr:$src)>;
2446 //===----------------------------------------------------------------------===//
2447 // SSE3 Instructions
2448 //===----------------------------------------------------------------------===//
2450 // Move Instructions
2451 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2452 "movshdup\t{$src, $dst|$dst, $src}",
2453 [(set VR128:$dst, (v4f32 (vector_shuffle
2454 VR128:$src, (undef),
2455 MOVSHDUP_shuffle_mask)))]>;
2456 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2457 "movshdup\t{$src, $dst|$dst, $src}",
2458 [(set VR128:$dst, (v4f32 (vector_shuffle
2459 (memopv4f32 addr:$src), (undef),
2460 MOVSHDUP_shuffle_mask)))]>;
2462 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2463 "movsldup\t{$src, $dst|$dst, $src}",
2464 [(set VR128:$dst, (v4f32 (vector_shuffle
2465 VR128:$src, (undef),
2466 MOVSLDUP_shuffle_mask)))]>;
2467 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2468 "movsldup\t{$src, $dst|$dst, $src}",
2469 [(set VR128:$dst, (v4f32 (vector_shuffle
2470 (memopv4f32 addr:$src), (undef),
2471 MOVSLDUP_shuffle_mask)))]>;
2473 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2474 "movddup\t{$src, $dst|$dst, $src}",
2476 (v2f64 (vector_shuffle VR128:$src, (undef),
2477 MOVDDUP_shuffle_mask)))]>;
2478 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2479 "movddup\t{$src, $dst|$dst, $src}",
2481 (v2f64 (vector_shuffle
2482 (scalar_to_vector (loadf64 addr:$src)),
2483 (undef), MOVDDUP_shuffle_mask)))]>;
2485 def : Pat<(vector_shuffle
2486 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2487 (undef), MOVDDUP_shuffle_mask),
2488 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2489 def : Pat<(vector_shuffle
2490 (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
2491 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2495 let Constraints = "$src1 = $dst" in {
2496 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2497 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2498 "addsubps\t{$src2, $dst|$dst, $src2}",
2499 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2501 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2502 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2503 "addsubps\t{$src2, $dst|$dst, $src2}",
2504 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2505 (memop addr:$src2)))]>;
2506 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2507 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2508 "addsubpd\t{$src2, $dst|$dst, $src2}",
2509 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2511 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2512 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2513 "addsubpd\t{$src2, $dst|$dst, $src2}",
2514 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2515 (memop addr:$src2)))]>;
2518 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2519 "lddqu\t{$src, $dst|$dst, $src}",
2520 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2523 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2524 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2525 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2526 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2527 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2528 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2529 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2530 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2531 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2532 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2533 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2534 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2535 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2536 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2537 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2538 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2540 let Constraints = "$src1 = $dst" in {
2541 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2542 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2543 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2544 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2545 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2546 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2547 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2548 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2551 // Thread synchronization
2552 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2553 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2554 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2555 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2557 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2558 let AddedComplexity = 15 in
2559 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2560 MOVSHDUP_shuffle_mask)),
2561 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2562 let AddedComplexity = 20 in
2563 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2564 MOVSHDUP_shuffle_mask)),
2565 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2567 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2568 let AddedComplexity = 15 in
2569 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2570 MOVSLDUP_shuffle_mask)),
2571 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2572 let AddedComplexity = 20 in
2573 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2574 MOVSLDUP_shuffle_mask)),
2575 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2577 //===----------------------------------------------------------------------===//
2578 // SSSE3 Instructions
2579 //===----------------------------------------------------------------------===//
2581 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2582 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2583 Intrinsic IntId64, Intrinsic IntId128> {
2584 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2586 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2588 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2591 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2593 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2595 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2596 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2599 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2604 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2607 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2608 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2609 Intrinsic IntId64, Intrinsic IntId128> {
2610 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2612 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2613 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2615 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2617 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2620 (bitconvert (memopv4i16 addr:$src))))]>;
2622 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2625 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2628 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2633 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2636 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2637 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2638 Intrinsic IntId64, Intrinsic IntId128> {
2639 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2642 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2644 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2646 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2649 (bitconvert (memopv2i32 addr:$src))))]>;
2651 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2653 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2654 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2657 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2659 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2662 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2665 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2666 int_x86_ssse3_pabs_b,
2667 int_x86_ssse3_pabs_b_128>;
2668 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2669 int_x86_ssse3_pabs_w,
2670 int_x86_ssse3_pabs_w_128>;
2671 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2672 int_x86_ssse3_pabs_d,
2673 int_x86_ssse3_pabs_d_128>;
2675 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2676 let Constraints = "$src1 = $dst" in {
2677 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2678 Intrinsic IntId64, Intrinsic IntId128,
2679 bit Commutable = 0> {
2680 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2681 (ins VR64:$src1, VR64:$src2),
2682 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2683 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2684 let isCommutable = Commutable;
2686 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2687 (ins VR64:$src1, i64mem:$src2),
2688 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2690 (IntId64 VR64:$src1,
2691 (bitconvert (memopv8i8 addr:$src2))))]>;
2693 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2694 (ins VR128:$src1, VR128:$src2),
2695 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2696 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2698 let isCommutable = Commutable;
2700 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2701 (ins VR128:$src1, i128mem:$src2),
2702 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2704 (IntId128 VR128:$src1,
2705 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2709 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2710 let Constraints = "$src1 = $dst" in {
2711 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2712 Intrinsic IntId64, Intrinsic IntId128,
2713 bit Commutable = 0> {
2714 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2715 (ins VR64:$src1, VR64:$src2),
2716 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2717 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2718 let isCommutable = Commutable;
2720 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2721 (ins VR64:$src1, i64mem:$src2),
2722 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2724 (IntId64 VR64:$src1,
2725 (bitconvert (memopv4i16 addr:$src2))))]>;
2727 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2728 (ins VR128:$src1, VR128:$src2),
2729 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2730 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2732 let isCommutable = Commutable;
2734 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2735 (ins VR128:$src1, i128mem:$src2),
2736 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2738 (IntId128 VR128:$src1,
2739 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2743 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2744 let Constraints = "$src1 = $dst" in {
2745 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2746 Intrinsic IntId64, Intrinsic IntId128,
2747 bit Commutable = 0> {
2748 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2749 (ins VR64:$src1, VR64:$src2),
2750 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2751 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2752 let isCommutable = Commutable;
2754 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2755 (ins VR64:$src1, i64mem:$src2),
2756 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2758 (IntId64 VR64:$src1,
2759 (bitconvert (memopv2i32 addr:$src2))))]>;
2761 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2762 (ins VR128:$src1, VR128:$src2),
2763 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2764 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2766 let isCommutable = Commutable;
2768 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2769 (ins VR128:$src1, i128mem:$src2),
2770 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2772 (IntId128 VR128:$src1,
2773 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2777 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2778 int_x86_ssse3_phadd_w,
2779 int_x86_ssse3_phadd_w_128>;
2780 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2781 int_x86_ssse3_phadd_d,
2782 int_x86_ssse3_phadd_d_128>;
2783 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2784 int_x86_ssse3_phadd_sw,
2785 int_x86_ssse3_phadd_sw_128>;
2786 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2787 int_x86_ssse3_phsub_w,
2788 int_x86_ssse3_phsub_w_128>;
2789 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2790 int_x86_ssse3_phsub_d,
2791 int_x86_ssse3_phsub_d_128>;
2792 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2793 int_x86_ssse3_phsub_sw,
2794 int_x86_ssse3_phsub_sw_128>;
2795 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2796 int_x86_ssse3_pmadd_ub_sw,
2797 int_x86_ssse3_pmadd_ub_sw_128>;
2798 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2799 int_x86_ssse3_pmul_hr_sw,
2800 int_x86_ssse3_pmul_hr_sw_128, 1>;
2801 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2802 int_x86_ssse3_pshuf_b,
2803 int_x86_ssse3_pshuf_b_128>;
2804 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2805 int_x86_ssse3_psign_b,
2806 int_x86_ssse3_psign_b_128>;
2807 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2808 int_x86_ssse3_psign_w,
2809 int_x86_ssse3_psign_w_128>;
2810 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2811 int_x86_ssse3_psign_d,
2812 int_x86_ssse3_psign_d_128>;
2814 let Constraints = "$src1 = $dst" in {
2815 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2816 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2817 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2819 (int_x86_ssse3_palign_r
2820 VR64:$src1, VR64:$src2,
2822 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2823 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2824 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2826 (int_x86_ssse3_palign_r
2828 (bitconvert (memopv2i32 addr:$src2)),
2831 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2832 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2833 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2835 (int_x86_ssse3_palign_r_128
2836 VR128:$src1, VR128:$src2,
2837 imm:$src3))]>, OpSize;
2838 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2839 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2840 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2842 (int_x86_ssse3_palign_r_128
2844 (bitconvert (memopv4i32 addr:$src2)),
2845 imm:$src3))]>, OpSize;
2848 //===----------------------------------------------------------------------===//
2849 // Non-Instruction Patterns
2850 //===----------------------------------------------------------------------===//
2852 // extload f32 -> f64. This matches load+fextend because we have a hack in
2853 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2854 // Since these loads aren't folded into the fextend, we have to match it
2856 let Predicates = [HasSSE2] in
2857 def : Pat<(fextend (loadf32 addr:$src)),
2858 (CVTSS2SDrm addr:$src)>;
2861 let Predicates = [HasSSE2] in {
2862 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2863 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2864 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2865 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2866 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2867 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2868 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2869 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2870 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2871 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2872 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2873 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2874 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2875 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2876 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2877 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2878 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2879 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2880 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2881 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2882 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2883 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2884 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2885 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2886 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2887 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2888 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2889 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2890 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2891 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2894 // Move scalar to XMM zero-extended
2895 // movd to XMM register zero-extends
2896 let AddedComplexity = 15 in {
2897 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2898 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2899 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2900 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2901 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2902 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2903 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2904 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2905 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2908 // Splat v2f64 / v2i64
2909 let AddedComplexity = 10 in {
2910 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2911 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2912 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2913 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2914 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2915 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2916 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2917 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2920 // Special unary SHUFPSrri case.
2921 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2922 SHUFP_unary_shuffle_mask:$sm)),
2923 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2924 Requires<[HasSSE1]>;
2925 // Special unary SHUFPDrri case.
2926 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2927 SHUFP_unary_shuffle_mask:$sm)),
2928 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2929 Requires<[HasSSE2]>;
2930 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2931 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2932 SHUFP_unary_shuffle_mask:$sm),
2933 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2934 Requires<[HasSSE2]>;
2936 // Special binary v4i32 shuffle cases with SHUFPS.
2937 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2938 PSHUFD_binary_shuffle_mask:$sm)),
2939 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2940 Requires<[HasSSE2]>;
2941 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2942 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2943 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2944 Requires<[HasSSE2]>;
2945 // Special binary v2i64 shuffle cases using SHUFPDrri.
2946 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2947 SHUFP_shuffle_mask:$sm)),
2948 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2949 Requires<[HasSSE2]>;
2950 // Special unary SHUFPDrri case.
2951 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2952 SHUFP_unary_shuffle_mask:$sm)),
2953 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2954 Requires<[HasSSE2]>;
2956 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2957 let AddedComplexity = 15 in {
2958 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2959 UNPCKL_v_undef_shuffle_mask:$sm)),
2960 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2961 Requires<[OptForSpeed, HasSSE2]>;
2962 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2963 UNPCKL_v_undef_shuffle_mask:$sm)),
2964 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2965 Requires<[OptForSpeed, HasSSE2]>;
2967 let AddedComplexity = 10 in {
2968 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2969 UNPCKL_v_undef_shuffle_mask)),
2970 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2971 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2972 UNPCKL_v_undef_shuffle_mask)),
2973 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2974 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2975 UNPCKL_v_undef_shuffle_mask)),
2976 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2977 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2978 UNPCKL_v_undef_shuffle_mask)),
2979 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2982 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2983 let AddedComplexity = 15 in {
2984 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2985 UNPCKH_v_undef_shuffle_mask:$sm)),
2986 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2987 Requires<[OptForSpeed, HasSSE2]>;
2988 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2989 UNPCKH_v_undef_shuffle_mask:$sm)),
2990 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2991 Requires<[OptForSpeed, HasSSE2]>;
2993 let AddedComplexity = 10 in {
2994 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2995 UNPCKH_v_undef_shuffle_mask)),
2996 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2997 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2998 UNPCKH_v_undef_shuffle_mask)),
2999 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3000 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
3001 UNPCKH_v_undef_shuffle_mask)),
3002 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3003 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
3004 UNPCKH_v_undef_shuffle_mask)),
3005 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3008 let AddedComplexity = 20 in {
3009 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3010 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3011 MOVHP_shuffle_mask)),
3012 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3014 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3015 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3016 MOVHLPS_shuffle_mask)),
3017 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3019 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3020 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
3021 MOVHLPS_v_undef_shuffle_mask)),
3022 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3023 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
3024 MOVHLPS_v_undef_shuffle_mask)),
3025 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3028 let AddedComplexity = 20 in {
3029 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3030 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
3031 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
3032 MOVLP_shuffle_mask)),
3033 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3034 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
3035 MOVLP_shuffle_mask)),
3036 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3037 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
3038 MOVHP_shuffle_mask)),
3039 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3040 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
3041 MOVHP_shuffle_mask)),
3042 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3044 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
3045 MOVLP_shuffle_mask)),
3046 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3047 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
3048 MOVLP_shuffle_mask)),
3049 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3050 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
3051 MOVHP_shuffle_mask)),
3052 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3053 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
3054 MOVHP_shuffle_mask)),
3055 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3058 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3059 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3060 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
3061 MOVLP_shuffle_mask)), addr:$src1),
3062 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3063 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
3064 MOVLP_shuffle_mask)), addr:$src1),
3065 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3066 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
3067 MOVHP_shuffle_mask)), addr:$src1),
3068 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3069 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
3070 MOVHP_shuffle_mask)), addr:$src1),
3071 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3073 def : Pat<(store (v4i32 (vector_shuffle
3074 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
3075 MOVLP_shuffle_mask)), addr:$src1),
3076 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3077 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
3078 MOVLP_shuffle_mask)), addr:$src1),
3079 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3080 def : Pat<(store (v4i32 (vector_shuffle
3081 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
3082 MOVHP_shuffle_mask)), addr:$src1),
3083 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3084 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
3085 MOVHP_shuffle_mask)), addr:$src1),
3086 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3089 let AddedComplexity = 15 in {
3090 // Setting the lowest element in the vector.
3091 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3092 MOVL_shuffle_mask)),
3093 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3094 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3095 MOVL_shuffle_mask)),
3096 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3098 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3099 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3100 MOVLP_shuffle_mask)),
3101 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3102 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3103 MOVLP_shuffle_mask)),
3104 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3107 // Set lowest element and zero upper elements.
3108 let AddedComplexity = 15 in
3109 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3110 MOVL_shuffle_mask)),
3111 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3112 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3113 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3115 // Some special case pandn patterns.
3116 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3118 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3119 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3121 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3122 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3124 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3126 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3127 (memop addr:$src2))),
3128 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3129 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3130 (memop addr:$src2))),
3131 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3132 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3133 (memop addr:$src2))),
3134 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3136 // vector -> vector casts
3137 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3138 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3139 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3140 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3141 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3142 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3143 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3144 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3146 // Use movaps / movups for SSE integer load / store (one byte shorter).
3147 def : Pat<(alignedloadv4i32 addr:$src),
3148 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3149 def : Pat<(loadv4i32 addr:$src),
3150 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3151 def : Pat<(alignedloadv2i64 addr:$src),
3152 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3153 def : Pat<(loadv2i64 addr:$src),
3154 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3156 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3157 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3158 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3159 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3160 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3161 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3162 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3163 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3164 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3165 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3166 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3167 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3168 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3169 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3170 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3171 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3173 //===----------------------------------------------------------------------===//
3174 // SSE4.1 Instructions
3175 //===----------------------------------------------------------------------===//
3177 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3180 Intrinsic V2F64Int> {
3181 // Intrinsic operation, reg.
3182 // Vector intrinsic operation, reg
3183 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3184 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3185 !strconcat(OpcodeStr,
3186 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3187 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3190 // Vector intrinsic operation, mem
3191 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3192 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3193 !strconcat(OpcodeStr,
3194 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3196 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3199 // Vector intrinsic operation, reg
3200 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3201 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3202 !strconcat(OpcodeStr,
3203 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3204 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3207 // Vector intrinsic operation, mem
3208 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3209 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3210 !strconcat(OpcodeStr,
3211 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3213 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3217 let Constraints = "$src1 = $dst" in {
3218 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3222 // Intrinsic operation, reg.
3223 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3225 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3226 !strconcat(OpcodeStr,
3227 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3229 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3232 // Intrinsic operation, mem.
3233 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3235 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3236 !strconcat(OpcodeStr,
3237 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3239 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3242 // Intrinsic operation, reg.
3243 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3245 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3246 !strconcat(OpcodeStr,
3247 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3249 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3252 // Intrinsic operation, mem.
3253 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3255 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3256 !strconcat(OpcodeStr,
3257 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3259 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3264 // FP round - roundss, roundps, roundsd, roundpd
3265 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3266 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3267 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3268 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3270 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3271 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3272 Intrinsic IntId128> {
3273 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3275 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3276 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3277 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3279 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3282 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3285 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3286 int_x86_sse41_phminposuw>;
3288 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3289 let Constraints = "$src1 = $dst" in {
3290 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3291 Intrinsic IntId128, bit Commutable = 0> {
3292 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3293 (ins VR128:$src1, VR128:$src2),
3294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3295 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3297 let isCommutable = Commutable;
3299 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3300 (ins VR128:$src1, i128mem:$src2),
3301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3303 (IntId128 VR128:$src1,
3304 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3308 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3309 int_x86_sse41_pcmpeqq, 1>;
3310 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3311 int_x86_sse41_packusdw, 0>;
3312 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3313 int_x86_sse41_pminsb, 1>;
3314 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3315 int_x86_sse41_pminsd, 1>;
3316 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3317 int_x86_sse41_pminud, 1>;
3318 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3319 int_x86_sse41_pminuw, 1>;
3320 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3321 int_x86_sse41_pmaxsb, 1>;
3322 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3323 int_x86_sse41_pmaxsd, 1>;
3324 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3325 int_x86_sse41_pmaxud, 1>;
3326 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3327 int_x86_sse41_pmaxuw, 1>;
3329 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3331 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3332 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3333 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3334 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3336 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3337 let Constraints = "$src1 = $dst" in {
3338 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3339 SDNode OpNode, Intrinsic IntId128,
3340 bit Commutable = 0> {
3341 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3342 (ins VR128:$src1, VR128:$src2),
3343 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3344 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3345 VR128:$src2))]>, OpSize {
3346 let isCommutable = Commutable;
3348 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3349 (ins VR128:$src1, VR128:$src2),
3350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3351 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3353 let isCommutable = Commutable;
3355 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3356 (ins VR128:$src1, i128mem:$src2),
3357 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3359 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3360 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3361 (ins VR128:$src1, i128mem:$src2),
3362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3364 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3368 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3369 int_x86_sse41_pmulld, 1>;
3371 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3372 let Constraints = "$src1 = $dst" in {
3373 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3374 Intrinsic IntId128, bit Commutable = 0> {
3375 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3376 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3377 !strconcat(OpcodeStr,
3378 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3380 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3382 let isCommutable = Commutable;
3384 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3385 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3386 !strconcat(OpcodeStr,
3387 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3389 (IntId128 VR128:$src1,
3390 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3395 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3396 int_x86_sse41_blendps, 0>;
3397 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3398 int_x86_sse41_blendpd, 0>;
3399 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3400 int_x86_sse41_pblendw, 0>;
3401 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3402 int_x86_sse41_dpps, 1>;
3403 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3404 int_x86_sse41_dppd, 1>;
3405 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3406 int_x86_sse41_mpsadbw, 1>;
3409 /// SS41I_ternary_int - SSE 4.1 ternary operator
3410 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3411 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3412 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3413 (ins VR128:$src1, VR128:$src2),
3414 !strconcat(OpcodeStr,
3415 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3416 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3419 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3420 (ins VR128:$src1, i128mem:$src2),
3421 !strconcat(OpcodeStr,
3422 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3425 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3429 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3430 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3431 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3434 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3435 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3436 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3437 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3439 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3442 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3446 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3447 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3448 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3449 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3450 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3451 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3453 // Common patterns involving scalar load.
3454 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3455 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3456 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3457 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3459 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3460 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3461 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3462 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3464 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3465 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3466 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3467 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3469 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3470 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3471 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3472 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3474 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3475 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3476 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3477 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3479 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3480 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3481 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3482 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3485 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3486 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3490 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3491 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3493 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3497 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3498 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3499 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3500 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3502 // Common patterns involving scalar load
3503 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3504 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3505 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3506 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3508 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3509 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3510 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3511 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3514 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3515 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3517 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3519 // Expecting a i16 load any extended to i32 value.
3520 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3521 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3522 [(set VR128:$dst, (IntId (bitconvert
3523 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3527 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3528 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3530 // Common patterns involving scalar load
3531 def : Pat<(int_x86_sse41_pmovsxbq
3532 (bitconvert (v4i32 (X86vzmovl
3533 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3534 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3536 def : Pat<(int_x86_sse41_pmovzxbq
3537 (bitconvert (v4i32 (X86vzmovl
3538 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3539 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3542 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3543 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3544 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3545 (ins VR128:$src1, i32i8imm:$src2),
3546 !strconcat(OpcodeStr,
3547 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3548 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3550 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3551 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3552 !strconcat(OpcodeStr,
3553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3556 // There's an AssertZext in the way of writing the store pattern
3557 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3560 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3563 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3564 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3565 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3566 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3567 !strconcat(OpcodeStr,
3568 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3571 // There's an AssertZext in the way of writing the store pattern
3572 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3575 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3578 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3579 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3580 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3581 (ins VR128:$src1, i32i8imm:$src2),
3582 !strconcat(OpcodeStr,
3583 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3585 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3586 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3587 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3588 !strconcat(OpcodeStr,
3589 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3590 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3591 addr:$dst)]>, OpSize;
3594 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3597 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3599 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3600 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3601 (ins VR128:$src1, i32i8imm:$src2),
3602 !strconcat(OpcodeStr,
3603 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3605 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3607 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3608 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3609 !strconcat(OpcodeStr,
3610 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3611 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3612 addr:$dst)]>, OpSize;
3615 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3617 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3618 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3621 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3622 Requires<[HasSSE41]>;
3624 let Constraints = "$src1 = $dst" in {
3625 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3626 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3627 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3628 !strconcat(OpcodeStr,
3629 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3631 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3632 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3633 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3634 !strconcat(OpcodeStr,
3635 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3637 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3638 imm:$src3))]>, OpSize;
3642 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3644 let Constraints = "$src1 = $dst" in {
3645 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3646 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3647 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3648 !strconcat(OpcodeStr,
3649 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3651 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3653 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3654 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3655 !strconcat(OpcodeStr,
3656 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3658 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3659 imm:$src3)))]>, OpSize;
3663 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3665 let Constraints = "$src1 = $dst" in {
3666 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3667 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3668 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3669 !strconcat(OpcodeStr,
3670 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3672 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3673 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3674 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3675 !strconcat(OpcodeStr,
3676 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3678 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3679 imm:$src3))]>, OpSize;
3683 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3685 let Defs = [EFLAGS] in {
3686 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3687 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3688 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3689 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3692 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3693 "movntdqa\t{$src, $dst|$dst, $src}",
3694 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3696 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3697 let Constraints = "$src1 = $dst" in {
3698 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3699 Intrinsic IntId128, bit Commutable = 0> {
3700 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3701 (ins VR128:$src1, VR128:$src2),
3702 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3703 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3705 let isCommutable = Commutable;
3707 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3708 (ins VR128:$src1, i128mem:$src2),
3709 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3711 (IntId128 VR128:$src1,
3712 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3716 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3718 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3719 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3720 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3721 (PCMPGTQrm VR128:$src1, addr:$src2)>;