1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 //===----------------------------------------------------------------------===//
73 // SSE Complex Patterns
74 //===----------------------------------------------------------------------===//
76 // These are 'extloads' from a scalar to the low element of a vector, zeroing
77 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
79 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
80 [SDNPHasChain, SDNPMayLoad]>;
81 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
82 [SDNPHasChain, SDNPMayLoad]>;
84 def ssmem : Operand<v4f32> {
85 let PrintMethod = "printf32mem";
86 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
88 def sdmem : Operand<v2f64> {
89 let PrintMethod = "printf64mem";
90 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
93 //===----------------------------------------------------------------------===//
94 // SSE pattern fragments
95 //===----------------------------------------------------------------------===//
97 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
98 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
99 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
100 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
102 // Like 'store', but always requires vector alignment.
103 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
104 (store node:$val, node:$ptr), [{
105 return cast<StoreSDNode>(N)->getAlignment() >= 16;
108 // Like 'load', but always requires vector alignment.
109 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
110 return cast<LoadSDNode>(N)->getAlignment() >= 16;
113 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
114 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
115 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
116 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
117 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
118 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
120 // Like 'load', but uses special alignment checks suitable for use in
121 // memory operands in most SSE instructions, which are required to
122 // be naturally aligned on some targets but not on others.
123 // FIXME: Actually implement support for targets that don't require the
124 // alignment. This probably wants a subtarget predicate.
125 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
126 return cast<LoadSDNode>(N)->getAlignment() >= 16;
129 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
130 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
131 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
132 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
133 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
134 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
135 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
137 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
139 // FIXME: 8 byte alignment for mmx reads is not required
140 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAlignment() >= 8;
144 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
145 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
146 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
147 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
149 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
150 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
151 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
152 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
153 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
154 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
156 def vzmovl_v2i64 : PatFrag<(ops node:$src),
157 (bitconvert (v2i64 (X86vzmovl
158 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
159 def vzmovl_v4i32 : PatFrag<(ops node:$src),
160 (bitconvert (v4i32 (X86vzmovl
161 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
163 def vzload_v2i64 : PatFrag<(ops node:$src),
164 (bitconvert (v2i64 (X86vzload node:$src)))>;
167 def fp32imm0 : PatLeaf<(f32 fpimm), [{
168 return N->isExactlyValue(+0.0);
171 def PSxLDQ_imm : SDNodeXForm<imm, [{
172 // Transformation function: imm >> 3
173 return getI32Imm(N->getZExtValue() >> 3);
176 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
178 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
179 return getI8Imm(X86::getShuffleSHUFImmediate(N));
182 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
184 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
185 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
188 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
190 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
191 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
194 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
195 (vector_shuffle node:$lhs, node:$rhs), [{
196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
197 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
200 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
201 (vector_shuffle node:$lhs, node:$rhs), [{
202 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
205 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
206 (vector_shuffle node:$lhs, node:$rhs), [{
207 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
210 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
211 (vector_shuffle node:$lhs, node:$rhs), [{
212 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
215 def movhp : PatFrag<(ops node:$lhs, node:$rhs),
216 (vector_shuffle node:$lhs, node:$rhs), [{
217 return X86::isMOVHPMask(cast<ShuffleVectorSDNode>(N));
220 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
221 (vector_shuffle node:$lhs, node:$rhs), [{
222 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
225 def movl : PatFrag<(ops node:$lhs, node:$rhs),
226 (vector_shuffle node:$lhs, node:$rhs), [{
227 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
230 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
231 (vector_shuffle node:$lhs, node:$rhs), [{
232 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
235 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
236 (vector_shuffle node:$lhs, node:$rhs), [{
237 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
240 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
241 (vector_shuffle node:$lhs, node:$rhs), [{
242 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
245 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
246 (vector_shuffle node:$lhs, node:$rhs), [{
247 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
250 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
251 (vector_shuffle node:$lhs, node:$rhs), [{
252 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
255 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
256 (vector_shuffle node:$lhs, node:$rhs), [{
257 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
260 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
261 (vector_shuffle node:$lhs, node:$rhs), [{
262 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
263 }], SHUFFLE_get_shuf_imm>;
265 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
266 (vector_shuffle node:$lhs, node:$rhs), [{
267 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
268 }], SHUFFLE_get_shuf_imm>;
270 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
271 (vector_shuffle node:$lhs, node:$rhs), [{
272 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
273 }], SHUFFLE_get_pshufhw_imm>;
275 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
276 (vector_shuffle node:$lhs, node:$rhs), [{
277 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
278 }], SHUFFLE_get_pshuflw_imm>;
280 //===----------------------------------------------------------------------===//
281 // SSE scalar FP Instructions
282 //===----------------------------------------------------------------------===//
284 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
285 // scheduler into a branch sequence.
286 // These are expanded by the scheduler.
287 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
288 def CMOV_FR32 : I<0, Pseudo,
289 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
290 "#CMOV_FR32 PSEUDO!",
291 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
293 def CMOV_FR64 : I<0, Pseudo,
294 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
295 "#CMOV_FR64 PSEUDO!",
296 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
298 def CMOV_V4F32 : I<0, Pseudo,
299 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
300 "#CMOV_V4F32 PSEUDO!",
302 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
304 def CMOV_V2F64 : I<0, Pseudo,
305 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
306 "#CMOV_V2F64 PSEUDO!",
308 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 def CMOV_V2I64 : I<0, Pseudo,
311 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
312 "#CMOV_V2I64 PSEUDO!",
314 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
323 let neverHasSideEffects = 1 in
324 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
325 "movss\t{$src, $dst|$dst, $src}", []>;
326 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
327 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
328 "movss\t{$src, $dst|$dst, $src}",
329 [(set FR32:$dst, (loadf32 addr:$src))]>;
330 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
331 "movss\t{$src, $dst|$dst, $src}",
332 [(store FR32:$src, addr:$dst)]>;
334 // Conversion instructions
335 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
336 "cvttss2si\t{$src, $dst|$dst, $src}",
337 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
338 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
339 "cvttss2si\t{$src, $dst|$dst, $src}",
340 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
341 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
342 "cvtsi2ss\t{$src, $dst|$dst, $src}",
343 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
344 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
345 "cvtsi2ss\t{$src, $dst|$dst, $src}",
346 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
348 // Match intrinsics which expect XMM operand(s).
349 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
350 "cvtss2si\t{$src, $dst|$dst, $src}",
351 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
352 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
353 "cvtss2si\t{$src, $dst|$dst, $src}",
354 [(set GR32:$dst, (int_x86_sse_cvtss2si
355 (load addr:$src)))]>;
357 // Match intrinisics which expect MM and XMM operand(s).
358 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
359 "cvtps2pi\t{$src, $dst|$dst, $src}",
360 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
361 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
362 "cvtps2pi\t{$src, $dst|$dst, $src}",
363 [(set VR64:$dst, (int_x86_sse_cvtps2pi
364 (load addr:$src)))]>;
365 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
366 "cvttps2pi\t{$src, $dst|$dst, $src}",
367 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
368 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
369 "cvttps2pi\t{$src, $dst|$dst, $src}",
370 [(set VR64:$dst, (int_x86_sse_cvttps2pi
371 (load addr:$src)))]>;
372 let Constraints = "$src1 = $dst" in {
373 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
374 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
375 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
376 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
378 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
380 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
381 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
382 (load addr:$src2)))]>;
385 // Aliases for intrinsics
386 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
387 "cvttss2si\t{$src, $dst|$dst, $src}",
389 (int_x86_sse_cvttss2si VR128:$src))]>;
390 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
391 "cvttss2si\t{$src, $dst|$dst, $src}",
393 (int_x86_sse_cvttss2si(load addr:$src)))]>;
395 let Constraints = "$src1 = $dst" in {
396 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
397 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
398 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
399 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
401 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
402 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
403 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
404 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
405 (loadi32 addr:$src2)))]>;
408 // Comparison instructions
409 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
410 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
411 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
412 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
414 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
415 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
416 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
419 let Defs = [EFLAGS] in {
420 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
421 "ucomiss\t{$src2, $src1|$src1, $src2}",
422 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
423 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
424 "ucomiss\t{$src2, $src1|$src1, $src2}",
425 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
429 // Aliases to match intrinsics which expect XMM operand(s).
430 let Constraints = "$src1 = $dst" in {
431 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
432 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
433 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
434 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
435 VR128:$src, imm:$cc))]>;
436 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
437 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
438 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
439 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
440 (load addr:$src), imm:$cc))]>;
443 let Defs = [EFLAGS] in {
444 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
445 "ucomiss\t{$src2, $src1|$src1, $src2}",
446 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
448 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
449 "ucomiss\t{$src2, $src1|$src1, $src2}",
450 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
453 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
454 "comiss\t{$src2, $src1|$src1, $src2}",
455 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
457 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
458 "comiss\t{$src2, $src1|$src1, $src2}",
459 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
463 // Aliases of packed SSE1 instructions for scalar use. These all have names that
466 // Alias instructions that map fld0 to pxor for sse.
467 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
468 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
469 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
470 Requires<[HasSSE1]>, TB, OpSize;
472 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
474 let neverHasSideEffects = 1 in
475 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
476 "movaps\t{$src, $dst|$dst, $src}", []>;
478 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
480 let canFoldAsLoad = 1 in
481 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
482 "movaps\t{$src, $dst|$dst, $src}",
483 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
485 // Alias bitwise logical operations using SSE logical ops on packed FP values.
486 let Constraints = "$src1 = $dst" in {
487 let isCommutable = 1 in {
488 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
489 (ins FR32:$src1, FR32:$src2),
490 "andps\t{$src2, $dst|$dst, $src2}",
491 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
492 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
493 (ins FR32:$src1, FR32:$src2),
494 "orps\t{$src2, $dst|$dst, $src2}",
495 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
496 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
497 (ins FR32:$src1, FR32:$src2),
498 "xorps\t{$src2, $dst|$dst, $src2}",
499 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
502 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
503 (ins FR32:$src1, f128mem:$src2),
504 "andps\t{$src2, $dst|$dst, $src2}",
505 [(set FR32:$dst, (X86fand FR32:$src1,
506 (memopfsf32 addr:$src2)))]>;
507 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
508 (ins FR32:$src1, f128mem:$src2),
509 "orps\t{$src2, $dst|$dst, $src2}",
510 [(set FR32:$dst, (X86for FR32:$src1,
511 (memopfsf32 addr:$src2)))]>;
512 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
513 (ins FR32:$src1, f128mem:$src2),
514 "xorps\t{$src2, $dst|$dst, $src2}",
515 [(set FR32:$dst, (X86fxor FR32:$src1,
516 (memopfsf32 addr:$src2)))]>;
518 let neverHasSideEffects = 1 in {
519 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
520 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
521 "andnps\t{$src2, $dst|$dst, $src2}", []>;
523 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
524 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
525 "andnps\t{$src2, $dst|$dst, $src2}", []>;
529 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
531 /// In addition, we also have a special variant of the scalar form here to
532 /// represent the associated intrinsic operation. This form is unlike the
533 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
534 /// and leaves the top elements unmodified (therefore these cannot be commuted).
536 /// These three forms can each be reg+reg or reg+mem, so there are a total of
537 /// six "instructions".
539 let Constraints = "$src1 = $dst" in {
540 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
541 SDNode OpNode, Intrinsic F32Int,
542 bit Commutable = 0> {
543 // Scalar operation, reg+reg.
544 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
545 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
546 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
547 let isCommutable = Commutable;
550 // Scalar operation, reg+mem.
551 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
552 (ins FR32:$src1, f32mem:$src2),
553 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
554 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
556 // Vector operation, reg+reg.
557 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
558 (ins VR128:$src1, VR128:$src2),
559 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
561 let isCommutable = Commutable;
564 // Vector operation, reg+mem.
565 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
566 (ins VR128:$src1, f128mem:$src2),
567 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
568 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
570 // Intrinsic operation, reg+reg.
571 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
572 (ins VR128:$src1, VR128:$src2),
573 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
574 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
576 // Intrinsic operation, reg+mem.
577 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
578 (ins VR128:$src1, ssmem:$src2),
579 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
580 [(set VR128:$dst, (F32Int VR128:$src1,
581 sse_load_f32:$src2))]>;
585 // Arithmetic instructions
586 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
587 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
588 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
589 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
591 /// sse1_fp_binop_rm - Other SSE1 binops
593 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
594 /// instructions for a full-vector intrinsic form. Operations that map
595 /// onto C operators don't use this form since they just use the plain
596 /// vector form instead of having a separate vector intrinsic form.
598 /// This provides a total of eight "instructions".
600 let Constraints = "$src1 = $dst" in {
601 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
605 bit Commutable = 0> {
607 // Scalar operation, reg+reg.
608 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
609 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
610 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
611 let isCommutable = Commutable;
614 // Scalar operation, reg+mem.
615 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
616 (ins FR32:$src1, f32mem:$src2),
617 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
618 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
620 // Vector operation, reg+reg.
621 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
622 (ins VR128:$src1, VR128:$src2),
623 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
625 let isCommutable = Commutable;
628 // Vector operation, reg+mem.
629 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
630 (ins VR128:$src1, f128mem:$src2),
631 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
634 // Intrinsic operation, reg+reg.
635 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
636 (ins VR128:$src1, VR128:$src2),
637 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
638 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
639 let isCommutable = Commutable;
642 // Intrinsic operation, reg+mem.
643 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
644 (ins VR128:$src1, ssmem:$src2),
645 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
646 [(set VR128:$dst, (F32Int VR128:$src1,
647 sse_load_f32:$src2))]>;
649 // Vector intrinsic operation, reg+reg.
650 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
651 (ins VR128:$src1, VR128:$src2),
652 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
653 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
654 let isCommutable = Commutable;
657 // Vector intrinsic operation, reg+mem.
658 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
659 (ins VR128:$src1, f128mem:$src2),
660 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
661 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
665 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
666 int_x86_sse_max_ss, int_x86_sse_max_ps>;
667 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
668 int_x86_sse_min_ss, int_x86_sse_min_ps>;
670 //===----------------------------------------------------------------------===//
671 // SSE packed FP Instructions
674 let neverHasSideEffects = 1 in
675 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
676 "movaps\t{$src, $dst|$dst, $src}", []>;
677 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
678 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
679 "movaps\t{$src, $dst|$dst, $src}",
680 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
682 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
683 "movaps\t{$src, $dst|$dst, $src}",
684 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
686 let neverHasSideEffects = 1 in
687 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
688 "movups\t{$src, $dst|$dst, $src}", []>;
689 let canFoldAsLoad = 1 in
690 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
691 "movups\t{$src, $dst|$dst, $src}",
692 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
693 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
694 "movups\t{$src, $dst|$dst, $src}",
695 [(store (v4f32 VR128:$src), addr:$dst)]>;
697 // Intrinsic forms of MOVUPS load and store
698 let canFoldAsLoad = 1 in
699 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
700 "movups\t{$src, $dst|$dst, $src}",
701 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
702 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
703 "movups\t{$src, $dst|$dst, $src}",
704 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
706 let Constraints = "$src1 = $dst" in {
707 let AddedComplexity = 20 in {
708 def MOVLPSrm : PSI<0x12, MRMSrcMem,
709 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
710 "movlps\t{$src2, $dst|$dst, $src2}",
713 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
714 def MOVHPSrm : PSI<0x16, MRMSrcMem,
715 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
716 "movhps\t{$src2, $dst|$dst, $src2}",
719 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
721 } // Constraints = "$src1 = $dst"
724 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
725 "movlps\t{$src, $dst|$dst, $src}",
726 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
727 (iPTR 0))), addr:$dst)]>;
729 // v2f64 extract element 1 is always custom lowered to unpack high to low
730 // and extract element 0 so the non-store version isn't too horrible.
731 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movhps\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract
734 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
735 (undef)), (iPTR 0))), addr:$dst)]>;
737 let Constraints = "$src1 = $dst" in {
738 let AddedComplexity = 20 in {
739 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
740 (ins VR128:$src1, VR128:$src2),
741 "movlhps\t{$src2, $dst|$dst, $src2}",
743 (v4f32 (movhp VR128:$src1, VR128:$src2)))]>;
745 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
746 (ins VR128:$src1, VR128:$src2),
747 "movhlps\t{$src2, $dst|$dst, $src2}",
749 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
751 } // Constraints = "$src1 = $dst"
753 let AddedComplexity = 20 in {
754 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
755 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
756 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
757 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
764 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
766 /// In addition, we also have a special variant of the scalar form here to
767 /// represent the associated intrinsic operation. This form is unlike the
768 /// plain scalar form, in that it takes an entire vector (instead of a
769 /// scalar) and leaves the top elements undefined.
771 /// And, we have a special variant form for a full-vector intrinsic form.
773 /// These four forms can each have a reg or a mem operand, so there are a
774 /// total of eight "instructions".
776 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
780 bit Commutable = 0> {
781 // Scalar operation, reg.
782 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
783 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
784 [(set FR32:$dst, (OpNode FR32:$src))]> {
785 let isCommutable = Commutable;
788 // Scalar operation, mem.
789 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
791 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
793 // Vector operation, reg.
794 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
795 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
796 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
797 let isCommutable = Commutable;
800 // Vector operation, mem.
801 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
802 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
805 // Intrinsic operation, reg.
806 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
807 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
808 [(set VR128:$dst, (F32Int VR128:$src))]> {
809 let isCommutable = Commutable;
812 // Intrinsic operation, mem.
813 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
814 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
817 // Vector intrinsic operation, reg
818 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
819 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
820 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
821 let isCommutable = Commutable;
824 // Vector intrinsic operation, mem
825 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
826 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
827 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
831 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
832 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
834 // Reciprocal approximations. Note that these typically require refinement
835 // in order to obtain suitable precision.
836 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
837 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
838 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
839 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
842 let Constraints = "$src1 = $dst" in {
843 let isCommutable = 1 in {
844 def ANDPSrr : PSI<0x54, MRMSrcReg,
845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
846 "andps\t{$src2, $dst|$dst, $src2}",
847 [(set VR128:$dst, (v2i64
848 (and VR128:$src1, VR128:$src2)))]>;
849 def ORPSrr : PSI<0x56, MRMSrcReg,
850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
851 "orps\t{$src2, $dst|$dst, $src2}",
852 [(set VR128:$dst, (v2i64
853 (or VR128:$src1, VR128:$src2)))]>;
854 def XORPSrr : PSI<0x57, MRMSrcReg,
855 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
856 "xorps\t{$src2, $dst|$dst, $src2}",
857 [(set VR128:$dst, (v2i64
858 (xor VR128:$src1, VR128:$src2)))]>;
861 def ANDPSrm : PSI<0x54, MRMSrcMem,
862 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
863 "andps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
865 (memopv2i64 addr:$src2)))]>;
866 def ORPSrm : PSI<0x56, MRMSrcMem,
867 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
868 "orps\t{$src2, $dst|$dst, $src2}",
869 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
870 (memopv2i64 addr:$src2)))]>;
871 def XORPSrm : PSI<0x57, MRMSrcMem,
872 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
873 "xorps\t{$src2, $dst|$dst, $src2}",
874 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
875 (memopv2i64 addr:$src2)))]>;
876 def ANDNPSrr : PSI<0x55, MRMSrcReg,
877 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
878 "andnps\t{$src2, $dst|$dst, $src2}",
880 (v2i64 (and (xor VR128:$src1,
881 (bc_v2i64 (v4i32 immAllOnesV))),
883 def ANDNPSrm : PSI<0x55, MRMSrcMem,
884 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
885 "andnps\t{$src2, $dst|$dst, $src2}",
887 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
888 (bc_v2i64 (v4i32 immAllOnesV))),
889 (memopv2i64 addr:$src2))))]>;
892 let Constraints = "$src1 = $dst" in {
893 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
895 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
896 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
897 VR128:$src, imm:$cc))]>;
898 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
899 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
900 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
902 (memop addr:$src), imm:$cc))]>;
904 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
905 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
906 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
907 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
909 // Shuffle and unpack instructions
910 let Constraints = "$src1 = $dst" in {
911 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
912 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
913 (outs VR128:$dst), (ins VR128:$src1,
914 VR128:$src2, i8imm:$src3),
915 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
917 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
918 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
919 (outs VR128:$dst), (ins VR128:$src1,
920 f128mem:$src2, i8imm:$src3),
921 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
924 VR128:$src1, (memopv4f32 addr:$src2))))]>;
926 let AddedComplexity = 10 in {
927 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
928 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
929 "unpckhps\t{$src2, $dst|$dst, $src2}",
931 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
932 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
934 "unpckhps\t{$src2, $dst|$dst, $src2}",
936 (v4f32 (unpckh VR128:$src1,
937 (memopv4f32 addr:$src2))))]>;
939 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
940 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
941 "unpcklps\t{$src2, $dst|$dst, $src2}",
943 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
944 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
945 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
946 "unpcklps\t{$src2, $dst|$dst, $src2}",
948 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
950 } // Constraints = "$src1 = $dst"
953 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
954 "movmskps\t{$src, $dst|$dst, $src}",
955 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
956 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
957 "movmskpd\t{$src, $dst|$dst, $src}",
958 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
960 // Prefetch intrinsic.
961 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
962 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
963 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
964 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
965 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
966 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
967 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
968 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
970 // Non-temporal stores
971 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
972 "movntps\t{$src, $dst|$dst, $src}",
973 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
975 // Load, store, and memory fence
976 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
979 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
980 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
981 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
982 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
984 // Alias instructions that map zero vector to pxor / xorp* for sse.
985 // We set canFoldAsLoad because this can be converted to a constant-pool
986 // load of an all-zeros value if folding it would be beneficial.
987 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
988 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
990 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
992 let Predicates = [HasSSE1] in {
993 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
994 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
995 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
996 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
997 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1000 // FR32 to 128-bit vector conversion.
1001 let isAsCheapAsAMove = 1 in
1002 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1003 "movss\t{$src, $dst|$dst, $src}",
1005 (v4f32 (scalar_to_vector FR32:$src)))]>;
1006 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1007 "movss\t{$src, $dst|$dst, $src}",
1009 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1011 // FIXME: may not be able to eliminate this movss with coalescing the src and
1012 // dest register classes are different. We really want to write this pattern
1014 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1015 // (f32 FR32:$src)>;
1016 let isAsCheapAsAMove = 1 in
1017 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1018 "movss\t{$src, $dst|$dst, $src}",
1019 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1021 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1022 "movss\t{$src, $dst|$dst, $src}",
1023 [(store (f32 (vector_extract (v4f32 VR128:$src),
1024 (iPTR 0))), addr:$dst)]>;
1027 // Move to lower bits of a VR128, leaving upper bits alone.
1028 // Three operand (but two address) aliases.
1029 let Constraints = "$src1 = $dst" in {
1030 let neverHasSideEffects = 1 in
1031 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1032 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1033 "movss\t{$src2, $dst|$dst, $src2}", []>;
1035 let AddedComplexity = 15 in
1036 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1037 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1038 "movss\t{$src2, $dst|$dst, $src2}",
1040 (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
1043 // Move to lower bits of a VR128 and zeroing upper bits.
1044 // Loading from memory automatically zeroing upper bits.
1045 let AddedComplexity = 20 in
1046 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1047 "movss\t{$src, $dst|$dst, $src}",
1048 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1049 (loadf32 addr:$src))))))]>;
1051 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1052 (MOVZSS2PSrm addr:$src)>;
1054 //===----------------------------------------------------------------------===//
1055 // SSE2 Instructions
1056 //===----------------------------------------------------------------------===//
1058 // Move Instructions
1059 let neverHasSideEffects = 1 in
1060 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1061 "movsd\t{$src, $dst|$dst, $src}", []>;
1062 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1063 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1064 "movsd\t{$src, $dst|$dst, $src}",
1065 [(set FR64:$dst, (loadf64 addr:$src))]>;
1066 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1067 "movsd\t{$src, $dst|$dst, $src}",
1068 [(store FR64:$src, addr:$dst)]>;
1070 // Conversion instructions
1071 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1072 "cvttsd2si\t{$src, $dst|$dst, $src}",
1073 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1074 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1075 "cvttsd2si\t{$src, $dst|$dst, $src}",
1076 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1077 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1078 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1079 [(set FR32:$dst, (fround FR64:$src))]>;
1080 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1081 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1082 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1083 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1084 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1085 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1086 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1087 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1088 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1090 // SSE2 instructions with XS prefix
1091 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1092 "cvtss2sd\t{$src, $dst|$dst, $src}",
1093 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1094 Requires<[HasSSE2]>;
1095 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1096 "cvtss2sd\t{$src, $dst|$dst, $src}",
1097 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1098 Requires<[HasSSE2]>;
1100 // Match intrinsics which expect XMM operand(s).
1101 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1102 "cvtsd2si\t{$src, $dst|$dst, $src}",
1103 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1104 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1105 "cvtsd2si\t{$src, $dst|$dst, $src}",
1106 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1107 (load addr:$src)))]>;
1109 // Match intrinisics which expect MM and XMM operand(s).
1110 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1111 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1112 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1113 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1114 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1115 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1116 (memop addr:$src)))]>;
1117 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1118 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1119 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1120 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1121 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1122 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1123 (memop addr:$src)))]>;
1124 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1125 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1126 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1127 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1128 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1129 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1130 (load addr:$src)))]>;
1132 // Aliases for intrinsics
1133 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1134 "cvttsd2si\t{$src, $dst|$dst, $src}",
1136 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1137 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1138 "cvttsd2si\t{$src, $dst|$dst, $src}",
1139 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1140 (load addr:$src)))]>;
1142 // Comparison instructions
1143 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1144 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1145 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1146 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1148 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1149 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1150 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1153 let Defs = [EFLAGS] in {
1154 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1155 "ucomisd\t{$src2, $src1|$src1, $src2}",
1156 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1157 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1158 "ucomisd\t{$src2, $src1|$src1, $src2}",
1159 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1160 (implicit EFLAGS)]>;
1161 } // Defs = [EFLAGS]
1163 // Aliases to match intrinsics which expect XMM operand(s).
1164 let Constraints = "$src1 = $dst" in {
1165 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1166 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1167 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1168 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1169 VR128:$src, imm:$cc))]>;
1170 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1171 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1172 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1173 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1174 (load addr:$src), imm:$cc))]>;
1177 let Defs = [EFLAGS] in {
1178 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1179 "ucomisd\t{$src2, $src1|$src1, $src2}",
1180 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1181 (implicit EFLAGS)]>;
1182 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1183 "ucomisd\t{$src2, $src1|$src1, $src2}",
1184 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1185 (implicit EFLAGS)]>;
1187 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1188 "comisd\t{$src2, $src1|$src1, $src2}",
1189 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1190 (implicit EFLAGS)]>;
1191 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1192 "comisd\t{$src2, $src1|$src1, $src2}",
1193 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1194 (implicit EFLAGS)]>;
1195 } // Defs = [EFLAGS]
1197 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1200 // Alias instructions that map fld0 to pxor for sse.
1201 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1202 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1203 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1204 Requires<[HasSSE2]>, TB, OpSize;
1206 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1208 let neverHasSideEffects = 1 in
1209 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1210 "movapd\t{$src, $dst|$dst, $src}", []>;
1212 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1214 let canFoldAsLoad = 1 in
1215 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1216 "movapd\t{$src, $dst|$dst, $src}",
1217 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1219 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1220 let Constraints = "$src1 = $dst" in {
1221 let isCommutable = 1 in {
1222 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1223 (ins FR64:$src1, FR64:$src2),
1224 "andpd\t{$src2, $dst|$dst, $src2}",
1225 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1226 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1227 (ins FR64:$src1, FR64:$src2),
1228 "orpd\t{$src2, $dst|$dst, $src2}",
1229 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1230 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1231 (ins FR64:$src1, FR64:$src2),
1232 "xorpd\t{$src2, $dst|$dst, $src2}",
1233 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1236 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1237 (ins FR64:$src1, f128mem:$src2),
1238 "andpd\t{$src2, $dst|$dst, $src2}",
1239 [(set FR64:$dst, (X86fand FR64:$src1,
1240 (memopfsf64 addr:$src2)))]>;
1241 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1242 (ins FR64:$src1, f128mem:$src2),
1243 "orpd\t{$src2, $dst|$dst, $src2}",
1244 [(set FR64:$dst, (X86for FR64:$src1,
1245 (memopfsf64 addr:$src2)))]>;
1246 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1247 (ins FR64:$src1, f128mem:$src2),
1248 "xorpd\t{$src2, $dst|$dst, $src2}",
1249 [(set FR64:$dst, (X86fxor FR64:$src1,
1250 (memopfsf64 addr:$src2)))]>;
1252 let neverHasSideEffects = 1 in {
1253 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1254 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1255 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1257 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1258 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1259 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1263 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1265 /// In addition, we also have a special variant of the scalar form here to
1266 /// represent the associated intrinsic operation. This form is unlike the
1267 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1268 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1270 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1271 /// six "instructions".
1273 let Constraints = "$src1 = $dst" in {
1274 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1275 SDNode OpNode, Intrinsic F64Int,
1276 bit Commutable = 0> {
1277 // Scalar operation, reg+reg.
1278 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1279 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1280 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1281 let isCommutable = Commutable;
1284 // Scalar operation, reg+mem.
1285 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1286 (ins FR64:$src1, f64mem:$src2),
1287 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1288 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1290 // Vector operation, reg+reg.
1291 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1292 (ins VR128:$src1, VR128:$src2),
1293 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1294 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1295 let isCommutable = Commutable;
1298 // Vector operation, reg+mem.
1299 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1300 (ins VR128:$src1, f128mem:$src2),
1301 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1302 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1304 // Intrinsic operation, reg+reg.
1305 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1306 (ins VR128:$src1, VR128:$src2),
1307 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1308 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1310 // Intrinsic operation, reg+mem.
1311 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1312 (ins VR128:$src1, sdmem:$src2),
1313 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1314 [(set VR128:$dst, (F64Int VR128:$src1,
1315 sse_load_f64:$src2))]>;
1319 // Arithmetic instructions
1320 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1321 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1322 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1323 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1325 /// sse2_fp_binop_rm - Other SSE2 binops
1327 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1328 /// instructions for a full-vector intrinsic form. Operations that map
1329 /// onto C operators don't use this form since they just use the plain
1330 /// vector form instead of having a separate vector intrinsic form.
1332 /// This provides a total of eight "instructions".
1334 let Constraints = "$src1 = $dst" in {
1335 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1339 bit Commutable = 0> {
1341 // Scalar operation, reg+reg.
1342 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1343 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1344 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1345 let isCommutable = Commutable;
1348 // Scalar operation, reg+mem.
1349 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1350 (ins FR64:$src1, f64mem:$src2),
1351 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1352 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1354 // Vector operation, reg+reg.
1355 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1356 (ins VR128:$src1, VR128:$src2),
1357 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1358 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1359 let isCommutable = Commutable;
1362 // Vector operation, reg+mem.
1363 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1364 (ins VR128:$src1, f128mem:$src2),
1365 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1366 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1368 // Intrinsic operation, reg+reg.
1369 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1370 (ins VR128:$src1, VR128:$src2),
1371 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1372 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1373 let isCommutable = Commutable;
1376 // Intrinsic operation, reg+mem.
1377 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1378 (ins VR128:$src1, sdmem:$src2),
1379 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1380 [(set VR128:$dst, (F64Int VR128:$src1,
1381 sse_load_f64:$src2))]>;
1383 // Vector intrinsic operation, reg+reg.
1384 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1385 (ins VR128:$src1, VR128:$src2),
1386 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1387 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1388 let isCommutable = Commutable;
1391 // Vector intrinsic operation, reg+mem.
1392 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1393 (ins VR128:$src1, f128mem:$src2),
1394 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1395 [(set VR128:$dst, (V2F64Int VR128:$src1,
1396 (memopv2f64 addr:$src2)))]>;
1400 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1401 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1402 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1403 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1405 //===----------------------------------------------------------------------===//
1406 // SSE packed FP Instructions
1408 // Move Instructions
1409 let neverHasSideEffects = 1 in
1410 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1411 "movapd\t{$src, $dst|$dst, $src}", []>;
1412 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1413 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1414 "movapd\t{$src, $dst|$dst, $src}",
1415 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1417 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1418 "movapd\t{$src, $dst|$dst, $src}",
1419 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1421 let neverHasSideEffects = 1 in
1422 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1423 "movupd\t{$src, $dst|$dst, $src}", []>;
1424 let canFoldAsLoad = 1 in
1425 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1426 "movupd\t{$src, $dst|$dst, $src}",
1427 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1428 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1429 "movupd\t{$src, $dst|$dst, $src}",
1430 [(store (v2f64 VR128:$src), addr:$dst)]>;
1432 // Intrinsic forms of MOVUPD load and store
1433 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1434 "movupd\t{$src, $dst|$dst, $src}",
1435 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1436 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1437 "movupd\t{$src, $dst|$dst, $src}",
1438 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1440 let Constraints = "$src1 = $dst" in {
1441 let AddedComplexity = 20 in {
1442 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1443 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1444 "movlpd\t{$src2, $dst|$dst, $src2}",
1446 (v2f64 (movlp VR128:$src1,
1447 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1448 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1449 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1450 "movhpd\t{$src2, $dst|$dst, $src2}",
1452 (v2f64 (movhp VR128:$src1,
1453 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1454 } // AddedComplexity
1455 } // Constraints = "$src1 = $dst"
1457 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1458 "movlpd\t{$src, $dst|$dst, $src}",
1459 [(store (f64 (vector_extract (v2f64 VR128:$src),
1460 (iPTR 0))), addr:$dst)]>;
1462 // v2f64 extract element 1 is always custom lowered to unpack high to low
1463 // and extract element 0 so the non-store version isn't too horrible.
1464 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1465 "movhpd\t{$src, $dst|$dst, $src}",
1466 [(store (f64 (vector_extract
1467 (v2f64 (unpckh VR128:$src, (undef))),
1468 (iPTR 0))), addr:$dst)]>;
1470 // SSE2 instructions without OpSize prefix
1471 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1472 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1473 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1474 TB, Requires<[HasSSE2]>;
1475 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1476 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1477 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1478 (bitconvert (memopv2i64 addr:$src))))]>,
1479 TB, Requires<[HasSSE2]>;
1481 // SSE2 instructions with XS prefix
1482 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1483 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1484 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1485 XS, Requires<[HasSSE2]>;
1486 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1487 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1488 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1489 (bitconvert (memopv2i64 addr:$src))))]>,
1490 XS, Requires<[HasSSE2]>;
1492 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1493 "cvtps2dq\t{$src, $dst|$dst, $src}",
1494 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1495 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1496 "cvtps2dq\t{$src, $dst|$dst, $src}",
1497 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1498 (memop addr:$src)))]>;
1499 // SSE2 packed instructions with XS prefix
1500 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1501 "cvttps2dq\t{$src, $dst|$dst, $src}",
1502 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1503 XS, Requires<[HasSSE2]>;
1504 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1505 "cvttps2dq\t{$src, $dst|$dst, $src}",
1506 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1507 (memop addr:$src)))]>,
1508 XS, Requires<[HasSSE2]>;
1510 // SSE2 packed instructions with XD prefix
1511 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1512 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1513 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1514 XD, Requires<[HasSSE2]>;
1515 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1516 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1517 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1518 (memop addr:$src)))]>,
1519 XD, Requires<[HasSSE2]>;
1521 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1522 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1523 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1524 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1525 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1526 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1527 (memop addr:$src)))]>;
1529 // SSE2 instructions without OpSize prefix
1530 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1531 "cvtps2pd\t{$src, $dst|$dst, $src}",
1532 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1533 TB, Requires<[HasSSE2]>;
1534 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1535 "cvtps2pd\t{$src, $dst|$dst, $src}",
1536 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1537 (load addr:$src)))]>,
1538 TB, Requires<[HasSSE2]>;
1540 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1541 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1542 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1543 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1544 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1545 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1546 (memop addr:$src)))]>;
1548 // Match intrinsics which expect XMM operand(s).
1549 // Aliases for intrinsics
1550 let Constraints = "$src1 = $dst" in {
1551 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1552 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1553 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1554 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1556 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1557 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1558 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1560 (loadi32 addr:$src2)))]>;
1561 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1562 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1563 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1566 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1567 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1568 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1570 (load addr:$src2)))]>;
1571 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1572 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1573 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1575 VR128:$src2))]>, XS,
1576 Requires<[HasSSE2]>;
1577 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1578 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1579 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1580 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1581 (load addr:$src2)))]>, XS,
1582 Requires<[HasSSE2]>;
1587 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1589 /// In addition, we also have a special variant of the scalar form here to
1590 /// represent the associated intrinsic operation. This form is unlike the
1591 /// plain scalar form, in that it takes an entire vector (instead of a
1592 /// scalar) and leaves the top elements undefined.
1594 /// And, we have a special variant form for a full-vector intrinsic form.
1596 /// These four forms can each have a reg or a mem operand, so there are a
1597 /// total of eight "instructions".
1599 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1603 bit Commutable = 0> {
1604 // Scalar operation, reg.
1605 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1606 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1607 [(set FR64:$dst, (OpNode FR64:$src))]> {
1608 let isCommutable = Commutable;
1611 // Scalar operation, mem.
1612 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1613 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1614 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1616 // Vector operation, reg.
1617 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1618 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1619 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1620 let isCommutable = Commutable;
1623 // Vector operation, mem.
1624 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1625 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1626 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1628 // Intrinsic operation, reg.
1629 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1630 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1631 [(set VR128:$dst, (F64Int VR128:$src))]> {
1632 let isCommutable = Commutable;
1635 // Intrinsic operation, mem.
1636 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1637 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1638 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1640 // Vector intrinsic operation, reg
1641 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1642 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1643 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1644 let isCommutable = Commutable;
1647 // Vector intrinsic operation, mem
1648 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1649 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1650 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1654 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1655 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1657 // There is no f64 version of the reciprocal approximation instructions.
1660 let Constraints = "$src1 = $dst" in {
1661 let isCommutable = 1 in {
1662 def ANDPDrr : PDI<0x54, MRMSrcReg,
1663 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1664 "andpd\t{$src2, $dst|$dst, $src2}",
1666 (and (bc_v2i64 (v2f64 VR128:$src1)),
1667 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1668 def ORPDrr : PDI<0x56, MRMSrcReg,
1669 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1670 "orpd\t{$src2, $dst|$dst, $src2}",
1672 (or (bc_v2i64 (v2f64 VR128:$src1)),
1673 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1674 def XORPDrr : PDI<0x57, MRMSrcReg,
1675 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1676 "xorpd\t{$src2, $dst|$dst, $src2}",
1678 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1679 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1682 def ANDPDrm : PDI<0x54, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1684 "andpd\t{$src2, $dst|$dst, $src2}",
1686 (and (bc_v2i64 (v2f64 VR128:$src1)),
1687 (memopv2i64 addr:$src2)))]>;
1688 def ORPDrm : PDI<0x56, MRMSrcMem,
1689 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1690 "orpd\t{$src2, $dst|$dst, $src2}",
1692 (or (bc_v2i64 (v2f64 VR128:$src1)),
1693 (memopv2i64 addr:$src2)))]>;
1694 def XORPDrm : PDI<0x57, MRMSrcMem,
1695 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1696 "xorpd\t{$src2, $dst|$dst, $src2}",
1698 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1699 (memopv2i64 addr:$src2)))]>;
1700 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1701 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1702 "andnpd\t{$src2, $dst|$dst, $src2}",
1704 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1705 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1706 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1707 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1708 "andnpd\t{$src2, $dst|$dst, $src2}",
1710 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1711 (memopv2i64 addr:$src2)))]>;
1714 let Constraints = "$src1 = $dst" in {
1715 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1717 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1719 VR128:$src, imm:$cc))]>;
1720 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1721 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1722 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1723 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1724 (memop addr:$src), imm:$cc))]>;
1726 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1727 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1728 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1729 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1731 // Shuffle and unpack instructions
1732 let Constraints = "$src1 = $dst" in {
1733 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1734 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1735 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1737 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1738 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1739 (outs VR128:$dst), (ins VR128:$src1,
1740 f128mem:$src2, i8imm:$src3),
1741 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1744 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1746 let AddedComplexity = 10 in {
1747 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1751 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1752 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1753 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1754 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1756 (v2f64 (unpckh VR128:$src1,
1757 (memopv2f64 addr:$src2))))]>;
1759 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1760 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1761 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1763 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1764 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1765 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1766 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1768 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1769 } // AddedComplexity
1770 } // Constraints = "$src1 = $dst"
1773 //===----------------------------------------------------------------------===//
1774 // SSE integer instructions
1776 // Move Instructions
1777 let neverHasSideEffects = 1 in
1778 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1779 "movdqa\t{$src, $dst|$dst, $src}", []>;
1780 let canFoldAsLoad = 1, mayLoad = 1 in
1781 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1782 "movdqa\t{$src, $dst|$dst, $src}",
1783 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1785 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1786 "movdqa\t{$src, $dst|$dst, $src}",
1787 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1788 let canFoldAsLoad = 1, mayLoad = 1 in
1789 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1790 "movdqu\t{$src, $dst|$dst, $src}",
1791 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1792 XS, Requires<[HasSSE2]>;
1794 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1795 "movdqu\t{$src, $dst|$dst, $src}",
1796 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1797 XS, Requires<[HasSSE2]>;
1799 // Intrinsic forms of MOVDQU load and store
1800 let canFoldAsLoad = 1 in
1801 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1802 "movdqu\t{$src, $dst|$dst, $src}",
1803 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1804 XS, Requires<[HasSSE2]>;
1805 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1806 "movdqu\t{$src, $dst|$dst, $src}",
1807 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1808 XS, Requires<[HasSSE2]>;
1810 let Constraints = "$src1 = $dst" in {
1812 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1813 bit Commutable = 0> {
1814 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1815 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1816 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1817 let isCommutable = Commutable;
1819 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1821 [(set VR128:$dst, (IntId VR128:$src1,
1822 (bitconvert (memopv2i64 addr:$src2))))]>;
1825 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1827 Intrinsic IntId, Intrinsic IntId2> {
1828 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1830 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1831 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1833 [(set VR128:$dst, (IntId VR128:$src1,
1834 (bitconvert (memopv2i64 addr:$src2))))]>;
1835 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1837 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1840 /// PDI_binop_rm - Simple SSE2 binary operator.
1841 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1842 ValueType OpVT, bit Commutable = 0> {
1843 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1844 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1845 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1846 let isCommutable = Commutable;
1848 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1850 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1851 (bitconvert (memopv2i64 addr:$src2)))))]>;
1854 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1856 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1857 /// to collapse (bitconvert VT to VT) into its operand.
1859 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1860 bit Commutable = 0> {
1861 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1863 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1864 let isCommutable = Commutable;
1866 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1867 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1868 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1871 } // Constraints = "$src1 = $dst"
1873 // 128-bit Integer Arithmetic
1875 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1876 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1877 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1878 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1880 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1881 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1882 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1883 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1885 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1886 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1887 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1888 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1890 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1891 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1892 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1893 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1895 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1897 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1898 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1899 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1901 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1903 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1904 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1907 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1908 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1909 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1910 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1911 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
1914 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1915 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1916 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1917 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1918 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1919 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1921 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1922 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1923 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1924 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1925 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1926 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1928 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1929 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1930 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1931 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1933 // 128-bit logical shifts.
1934 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1935 def PSLLDQri : PDIi8<0x73, MRM7r,
1936 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1937 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1938 def PSRLDQri : PDIi8<0x73, MRM3r,
1939 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1940 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1941 // PSRADQri doesn't exist in SSE[1-3].
1944 let Predicates = [HasSSE2] in {
1945 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1946 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1947 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1948 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1949 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1950 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1951 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1952 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1953 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1954 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1956 // Shift up / down and insert zero's.
1957 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1958 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1959 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1960 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1964 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1965 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1966 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1968 let Constraints = "$src1 = $dst" in {
1969 def PANDNrr : PDI<0xDF, MRMSrcReg,
1970 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1971 "pandn\t{$src2, $dst|$dst, $src2}",
1972 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1975 def PANDNrm : PDI<0xDF, MRMSrcMem,
1976 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1977 "pandn\t{$src2, $dst|$dst, $src2}",
1978 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1979 (memopv2i64 addr:$src2))))]>;
1982 // SSE2 Integer comparison
1983 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1984 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1985 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1986 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1987 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1988 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1990 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
1991 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
1992 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
1993 (PCMPEQBrm VR128:$src1, addr:$src2)>;
1994 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
1995 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
1996 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
1997 (PCMPEQWrm VR128:$src1, addr:$src2)>;
1998 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
1999 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2000 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2001 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2003 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2004 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2005 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2006 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2007 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2008 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2009 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2010 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2011 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2012 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2013 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2014 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2017 // Pack instructions
2018 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2019 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2020 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2022 // Shuffle and unpack instructions
2023 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2024 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2025 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2026 [(set VR128:$dst, (v4i32 (pshufd:$src2
2027 VR128:$src1, (undef))))]>;
2028 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2029 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2030 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2031 [(set VR128:$dst, (v4i32 (pshufd:$src2
2032 (bc_v4i32(memopv2i64 addr:$src1)),
2035 // SSE2 with ImmT == Imm8 and XS prefix.
2036 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2037 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2038 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2039 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2041 XS, Requires<[HasSSE2]>;
2042 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2043 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2044 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2045 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2046 (bc_v8i16 (memopv2i64 addr:$src1)),
2048 XS, Requires<[HasSSE2]>;
2050 // SSE2 with ImmT == Imm8 and XD prefix.
2051 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2052 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2053 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2054 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2056 XD, Requires<[HasSSE2]>;
2057 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2058 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2059 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2060 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2061 (bc_v8i16 (memopv2i64 addr:$src1)),
2063 XD, Requires<[HasSSE2]>;
2066 let Constraints = "$src1 = $dst" in {
2067 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2068 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2069 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2071 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2072 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2073 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2074 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2076 (unpckl VR128:$src1,
2077 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2078 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2079 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2080 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2082 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2083 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2084 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2085 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2087 (unpckl VR128:$src1,
2088 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2089 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2090 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2091 "punpckldq\t{$src2, $dst|$dst, $src2}",
2093 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2094 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2095 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2096 "punpckldq\t{$src2, $dst|$dst, $src2}",
2098 (unpckl VR128:$src1,
2099 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2100 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2101 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2102 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2104 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2105 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2106 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2107 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2109 (v2i64 (unpckl VR128:$src1,
2110 (memopv2i64 addr:$src2))))]>;
2112 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2113 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2114 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2116 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2117 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2118 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2119 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2121 (unpckh VR128:$src1,
2122 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2123 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2124 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2125 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2127 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2128 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2129 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2130 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2132 (unpckh VR128:$src1,
2133 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2134 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2135 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2136 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2138 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2139 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2140 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2141 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2143 (unpckh VR128:$src1,
2144 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2145 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2146 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2147 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2149 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2150 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2151 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2152 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2154 (v2i64 (unpckh VR128:$src1,
2155 (memopv2i64 addr:$src2))))]>;
2159 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2160 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2161 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2162 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2164 let Constraints = "$src1 = $dst" in {
2165 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2166 (outs VR128:$dst), (ins VR128:$src1,
2167 GR32:$src2, i32i8imm:$src3),
2168 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2170 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2171 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2172 (outs VR128:$dst), (ins VR128:$src1,
2173 i16mem:$src2, i32i8imm:$src3),
2174 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2176 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2181 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2182 "pmovmskb\t{$src, $dst|$dst, $src}",
2183 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2185 // Conditional store
2187 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2188 "maskmovdqu\t{$mask, $src|$src, $mask}",
2189 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2192 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2193 "maskmovdqu\t{$mask, $src|$src, $mask}",
2194 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2196 // Non-temporal stores
2197 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2198 "movntpd\t{$src, $dst|$dst, $src}",
2199 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2200 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2201 "movntdq\t{$src, $dst|$dst, $src}",
2202 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2203 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2204 "movnti\t{$src, $dst|$dst, $src}",
2205 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2206 TB, Requires<[HasSSE2]>;
2209 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2210 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2211 TB, Requires<[HasSSE2]>;
2213 // Load, store, and memory fence
2214 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2215 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2216 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2217 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2219 //TODO: custom lower this so as to never even generate the noop
2220 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2222 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2223 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2224 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2227 // Alias instructions that map zero vector to pxor / xorp* for sse.
2228 // We set canFoldAsLoad because this can be converted to a constant-pool
2229 // load of an all-ones value if folding it would be beneficial.
2230 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2231 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2232 "pcmpeqd\t$dst, $dst",
2233 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2235 // FR64 to 128-bit vector conversion.
2236 let isAsCheapAsAMove = 1 in
2237 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2238 "movsd\t{$src, $dst|$dst, $src}",
2240 (v2f64 (scalar_to_vector FR64:$src)))]>;
2241 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2242 "movsd\t{$src, $dst|$dst, $src}",
2244 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2246 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2247 "movd\t{$src, $dst|$dst, $src}",
2249 (v4i32 (scalar_to_vector GR32:$src)))]>;
2250 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2251 "movd\t{$src, $dst|$dst, $src}",
2253 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2255 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2256 "movd\t{$src, $dst|$dst, $src}",
2257 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2259 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2260 "movd\t{$src, $dst|$dst, $src}",
2261 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2263 // SSE2 instructions with XS prefix
2264 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2265 "movq\t{$src, $dst|$dst, $src}",
2267 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2268 Requires<[HasSSE2]>;
2269 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2270 "movq\t{$src, $dst|$dst, $src}",
2271 [(store (i64 (vector_extract (v2i64 VR128:$src),
2272 (iPTR 0))), addr:$dst)]>;
2274 // FIXME: may not be able to eliminate this movss with coalescing the src and
2275 // dest register classes are different. We really want to write this pattern
2277 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2278 // (f32 FR32:$src)>;
2279 let isAsCheapAsAMove = 1 in
2280 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2281 "movsd\t{$src, $dst|$dst, $src}",
2282 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2284 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2285 "movsd\t{$src, $dst|$dst, $src}",
2286 [(store (f64 (vector_extract (v2f64 VR128:$src),
2287 (iPTR 0))), addr:$dst)]>;
2288 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2289 "movd\t{$src, $dst|$dst, $src}",
2290 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2292 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2293 "movd\t{$src, $dst|$dst, $src}",
2294 [(store (i32 (vector_extract (v4i32 VR128:$src),
2295 (iPTR 0))), addr:$dst)]>;
2297 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2298 "movd\t{$src, $dst|$dst, $src}",
2299 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2300 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2301 "movd\t{$src, $dst|$dst, $src}",
2302 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2305 // Move to lower bits of a VR128, leaving upper bits alone.
2306 // Three operand (but two address) aliases.
2307 let Constraints = "$src1 = $dst" in {
2308 let neverHasSideEffects = 1 in
2309 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2310 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2311 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2313 let AddedComplexity = 15 in
2314 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2315 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2316 "movsd\t{$src2, $dst|$dst, $src2}",
2318 (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
2321 // Store / copy lower 64-bits of a XMM register.
2322 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2323 "movq\t{$src, $dst|$dst, $src}",
2324 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2326 // Move to lower bits of a VR128 and zeroing upper bits.
2327 // Loading from memory automatically zeroing upper bits.
2328 let AddedComplexity = 20 in {
2329 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2330 "movsd\t{$src, $dst|$dst, $src}",
2332 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2333 (loadf64 addr:$src))))))]>;
2335 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2336 (MOVZSD2PDrm addr:$src)>;
2337 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2338 (MOVZSD2PDrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2342 // movd / movq to XMM register zero-extends
2343 let AddedComplexity = 15 in {
2344 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2345 "movd\t{$src, $dst|$dst, $src}",
2346 [(set VR128:$dst, (v4i32 (X86vzmovl
2347 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2348 // This is X86-64 only.
2349 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2350 "mov{d|q}\t{$src, $dst|$dst, $src}",
2351 [(set VR128:$dst, (v2i64 (X86vzmovl
2352 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2355 let AddedComplexity = 20 in {
2356 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2357 "movd\t{$src, $dst|$dst, $src}",
2359 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2360 (loadi32 addr:$src))))))]>;
2362 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2363 (MOVZDI2PDIrm addr:$src)>;
2364 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2365 (MOVZDI2PDIrm addr:$src)>;
2366 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2367 (MOVZDI2PDIrm addr:$src)>;
2369 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2370 "movq\t{$src, $dst|$dst, $src}",
2372 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2373 (loadi64 addr:$src))))))]>, XS,
2374 Requires<[HasSSE2]>;
2376 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2377 (MOVZQI2PQIrm addr:$src)>;
2378 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2379 (MOVZQI2PQIrm addr:$src)>;
2380 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2383 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2384 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2385 let AddedComplexity = 15 in
2386 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2387 "movq\t{$src, $dst|$dst, $src}",
2388 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2389 XS, Requires<[HasSSE2]>;
2391 let AddedComplexity = 20 in {
2392 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2393 "movq\t{$src, $dst|$dst, $src}",
2394 [(set VR128:$dst, (v2i64 (X86vzmovl
2395 (loadv2i64 addr:$src))))]>,
2396 XS, Requires<[HasSSE2]>;
2398 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2399 (MOVZPQILo2PQIrm addr:$src)>;
2402 //===----------------------------------------------------------------------===//
2403 // SSE3 Instructions
2404 //===----------------------------------------------------------------------===//
2406 // Move Instructions
2407 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2408 "movshdup\t{$src, $dst|$dst, $src}",
2409 [(set VR128:$dst, (v4f32 (movshdup
2410 VR128:$src, (undef))))]>;
2411 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2412 "movshdup\t{$src, $dst|$dst, $src}",
2413 [(set VR128:$dst, (movshdup
2414 (memopv4f32 addr:$src), (undef)))]>;
2416 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2417 "movsldup\t{$src, $dst|$dst, $src}",
2418 [(set VR128:$dst, (v4f32 (movsldup
2419 VR128:$src, (undef))))]>;
2420 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2421 "movsldup\t{$src, $dst|$dst, $src}",
2422 [(set VR128:$dst, (movsldup
2423 (memopv4f32 addr:$src), (undef)))]>;
2425 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2426 "movddup\t{$src, $dst|$dst, $src}",
2427 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2428 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2429 "movddup\t{$src, $dst|$dst, $src}",
2431 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2434 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2436 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2438 let AddedComplexity = 5 in {
2439 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2440 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2441 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2442 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2443 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2444 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2445 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2446 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2450 let Constraints = "$src1 = $dst" in {
2451 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2452 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2453 "addsubps\t{$src2, $dst|$dst, $src2}",
2454 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2456 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2457 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2458 "addsubps\t{$src2, $dst|$dst, $src2}",
2459 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2460 (memop addr:$src2)))]>;
2461 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2462 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2463 "addsubpd\t{$src2, $dst|$dst, $src2}",
2464 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2466 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2467 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2468 "addsubpd\t{$src2, $dst|$dst, $src2}",
2469 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2470 (memop addr:$src2)))]>;
2473 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2474 "lddqu\t{$src, $dst|$dst, $src}",
2475 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2478 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2479 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2480 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2481 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2482 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2483 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2484 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2485 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2486 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2487 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2488 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2489 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2490 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2491 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2492 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2493 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2495 let Constraints = "$src1 = $dst" in {
2496 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2497 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2498 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2499 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2500 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2501 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2502 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2503 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2506 // Thread synchronization
2507 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2508 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2509 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2510 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2512 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2513 let AddedComplexity = 15 in
2514 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2515 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2516 let AddedComplexity = 20 in
2517 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2518 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2520 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2521 let AddedComplexity = 15 in
2522 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2523 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2524 let AddedComplexity = 20 in
2525 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2526 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2528 //===----------------------------------------------------------------------===//
2529 // SSSE3 Instructions
2530 //===----------------------------------------------------------------------===//
2532 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2533 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2534 Intrinsic IntId64, Intrinsic IntId128> {
2535 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2536 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2537 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2539 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2542 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2544 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2547 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2550 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2555 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2558 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2559 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2560 Intrinsic IntId64, Intrinsic IntId128> {
2561 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2564 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2566 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2571 (bitconvert (memopv4i16 addr:$src))))]>;
2573 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2576 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2579 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2584 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2587 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2588 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2589 Intrinsic IntId64, Intrinsic IntId128> {
2590 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2593 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2595 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2597 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2600 (bitconvert (memopv2i32 addr:$src))))]>;
2602 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2604 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2605 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2608 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2610 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2613 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2616 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2617 int_x86_ssse3_pabs_b,
2618 int_x86_ssse3_pabs_b_128>;
2619 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2620 int_x86_ssse3_pabs_w,
2621 int_x86_ssse3_pabs_w_128>;
2622 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2623 int_x86_ssse3_pabs_d,
2624 int_x86_ssse3_pabs_d_128>;
2626 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2627 let Constraints = "$src1 = $dst" in {
2628 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2629 Intrinsic IntId64, Intrinsic IntId128,
2630 bit Commutable = 0> {
2631 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2632 (ins VR64:$src1, VR64:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2635 let isCommutable = Commutable;
2637 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2638 (ins VR64:$src1, i64mem:$src2),
2639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2641 (IntId64 VR64:$src1,
2642 (bitconvert (memopv8i8 addr:$src2))))]>;
2644 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2645 (ins VR128:$src1, VR128:$src2),
2646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2647 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2649 let isCommutable = Commutable;
2651 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2652 (ins VR128:$src1, i128mem:$src2),
2653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2655 (IntId128 VR128:$src1,
2656 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2660 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2661 let Constraints = "$src1 = $dst" in {
2662 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2663 Intrinsic IntId64, Intrinsic IntId128,
2664 bit Commutable = 0> {
2665 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2666 (ins VR64:$src1, VR64:$src2),
2667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2668 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2669 let isCommutable = Commutable;
2671 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2672 (ins VR64:$src1, i64mem:$src2),
2673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2675 (IntId64 VR64:$src1,
2676 (bitconvert (memopv4i16 addr:$src2))))]>;
2678 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2679 (ins VR128:$src1, VR128:$src2),
2680 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2681 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2683 let isCommutable = Commutable;
2685 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2686 (ins VR128:$src1, i128mem:$src2),
2687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2689 (IntId128 VR128:$src1,
2690 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2694 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2695 let Constraints = "$src1 = $dst" in {
2696 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2697 Intrinsic IntId64, Intrinsic IntId128,
2698 bit Commutable = 0> {
2699 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2700 (ins VR64:$src1, VR64:$src2),
2701 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2702 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2703 let isCommutable = Commutable;
2705 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2706 (ins VR64:$src1, i64mem:$src2),
2707 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2709 (IntId64 VR64:$src1,
2710 (bitconvert (memopv2i32 addr:$src2))))]>;
2712 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2713 (ins VR128:$src1, VR128:$src2),
2714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2717 let isCommutable = Commutable;
2719 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2720 (ins VR128:$src1, i128mem:$src2),
2721 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2723 (IntId128 VR128:$src1,
2724 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2728 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2729 int_x86_ssse3_phadd_w,
2730 int_x86_ssse3_phadd_w_128>;
2731 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2732 int_x86_ssse3_phadd_d,
2733 int_x86_ssse3_phadd_d_128>;
2734 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2735 int_x86_ssse3_phadd_sw,
2736 int_x86_ssse3_phadd_sw_128>;
2737 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2738 int_x86_ssse3_phsub_w,
2739 int_x86_ssse3_phsub_w_128>;
2740 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2741 int_x86_ssse3_phsub_d,
2742 int_x86_ssse3_phsub_d_128>;
2743 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2744 int_x86_ssse3_phsub_sw,
2745 int_x86_ssse3_phsub_sw_128>;
2746 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2747 int_x86_ssse3_pmadd_ub_sw,
2748 int_x86_ssse3_pmadd_ub_sw_128>;
2749 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2750 int_x86_ssse3_pmul_hr_sw,
2751 int_x86_ssse3_pmul_hr_sw_128, 1>;
2752 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2753 int_x86_ssse3_pshuf_b,
2754 int_x86_ssse3_pshuf_b_128>;
2755 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2756 int_x86_ssse3_psign_b,
2757 int_x86_ssse3_psign_b_128>;
2758 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2759 int_x86_ssse3_psign_w,
2760 int_x86_ssse3_psign_w_128>;
2761 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2762 int_x86_ssse3_psign_d,
2763 int_x86_ssse3_psign_d_128>;
2765 let Constraints = "$src1 = $dst" in {
2766 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2767 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2768 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2770 (int_x86_ssse3_palign_r
2771 VR64:$src1, VR64:$src2,
2773 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2774 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2775 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2777 (int_x86_ssse3_palign_r
2779 (bitconvert (memopv2i32 addr:$src2)),
2782 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2783 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2784 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2786 (int_x86_ssse3_palign_r_128
2787 VR128:$src1, VR128:$src2,
2788 imm:$src3))]>, OpSize;
2789 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2790 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2791 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2793 (int_x86_ssse3_palign_r_128
2795 (bitconvert (memopv4i32 addr:$src2)),
2796 imm:$src3))]>, OpSize;
2799 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2800 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2801 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2802 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2804 //===----------------------------------------------------------------------===//
2805 // Non-Instruction Patterns
2806 //===----------------------------------------------------------------------===//
2808 // extload f32 -> f64. This matches load+fextend because we have a hack in
2809 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2810 // Since these loads aren't folded into the fextend, we have to match it
2812 let Predicates = [HasSSE2] in
2813 def : Pat<(fextend (loadf32 addr:$src)),
2814 (CVTSS2SDrm addr:$src)>;
2817 let Predicates = [HasSSE2] in {
2818 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2819 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2820 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2821 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2822 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2823 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2824 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2825 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2826 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2827 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2828 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2829 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2830 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2831 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2832 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2833 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2834 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2835 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2836 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2837 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2838 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2839 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2840 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2841 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2842 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2843 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2844 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2845 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2846 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2847 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2850 // Move scalar to XMM zero-extended
2851 // movd to XMM register zero-extends
2852 let AddedComplexity = 15 in {
2853 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2854 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2855 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2856 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2857 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2858 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2859 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2860 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2861 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2864 // Splat v2f64 / v2i64
2865 let AddedComplexity = 10 in {
2866 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2867 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2868 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2869 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2870 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2871 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2872 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2873 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2876 // Special unary SHUFPSrri case.
2877 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2878 (SHUFPSrri VR128:$src1, VR128:$src1,
2879 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2880 Requires<[HasSSE1]>;
2881 let AddedComplexity = 5 in
2882 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2883 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2884 Requires<[HasSSE2]>;
2885 // Special unary SHUFPDrri case.
2886 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2887 (SHUFPDrri VR128:$src1, VR128:$src1,
2888 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2889 Requires<[HasSSE2]>;
2890 // Special unary SHUFPDrri case.
2891 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2892 (SHUFPDrri VR128:$src1, VR128:$src1,
2893 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2894 Requires<[HasSSE2]>;
2895 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2896 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2897 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2898 Requires<[HasSSE2]>;
2900 // Special binary v4i32 shuffle cases with SHUFPS.
2901 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2902 (SHUFPSrri VR128:$src1, VR128:$src2,
2903 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2904 Requires<[HasSSE2]>;
2905 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2906 (SHUFPSrmi VR128:$src1, addr:$src2,
2907 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2908 Requires<[HasSSE2]>;
2909 // Special binary v2i64 shuffle cases using SHUFPDrri.
2910 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2911 (SHUFPDrri VR128:$src1, VR128:$src2,
2912 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2913 Requires<[HasSSE2]>;
2915 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2916 let AddedComplexity = 15 in {
2917 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2918 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2919 Requires<[OptForSpeed, HasSSE2]>;
2920 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2921 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2922 Requires<[OptForSpeed, HasSSE2]>;
2924 let AddedComplexity = 10 in {
2925 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2926 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2927 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2928 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2929 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2930 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2931 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2932 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2935 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2936 let AddedComplexity = 15 in {
2937 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
2938 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2939 Requires<[OptForSpeed, HasSSE2]>;
2940 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
2941 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2942 Requires<[OptForSpeed, HasSSE2]>;
2944 let AddedComplexity = 10 in {
2945 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
2946 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2947 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
2948 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2949 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
2950 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2951 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
2952 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2955 let AddedComplexity = 20 in {
2956 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2957 def : Pat<(v4i32 (movhp VR128:$src1, VR128:$src2)),
2958 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2960 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2961 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
2962 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2964 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2965 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
2966 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2967 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
2968 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2971 let AddedComplexity = 20 in {
2972 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2973 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2974 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
2975 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2976 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
2977 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2978 def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
2979 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2980 def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
2981 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2983 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
2984 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2985 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
2986 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2987 def : Pat<(v4i32 (movhp VR128:$src1, (load addr:$src2))),
2988 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2989 def : Pat<(v2i64 (movhp VR128:$src1, (load addr:$src2))),
2990 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2993 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
2994 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
2995 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
2996 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
2997 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
2998 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2999 def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3000 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3001 def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3002 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3004 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3006 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3007 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3008 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3009 def : Pat<(store (v4i32 (movhp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3011 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3012 def : Pat<(store (v2i64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3013 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3016 let AddedComplexity = 15 in {
3017 // Setting the lowest element in the vector.
3018 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3019 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3020 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3021 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3023 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3024 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3025 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3026 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3027 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3030 // Set lowest element and zero upper elements.
3031 let AddedComplexity = 15 in
3032 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3033 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3034 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3035 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3037 // Some special case pandn patterns.
3038 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3040 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3041 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3043 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3044 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3046 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3048 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3049 (memop addr:$src2))),
3050 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3051 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3052 (memop addr:$src2))),
3053 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3054 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3055 (memop addr:$src2))),
3056 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3058 // vector -> vector casts
3059 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3060 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3061 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3062 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3063 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3064 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3065 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3066 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3068 // Use movaps / movups for SSE integer load / store (one byte shorter).
3069 def : Pat<(alignedloadv4i32 addr:$src),
3070 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3071 def : Pat<(loadv4i32 addr:$src),
3072 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3073 def : Pat<(alignedloadv2i64 addr:$src),
3074 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3075 def : Pat<(loadv2i64 addr:$src),
3076 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3078 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3079 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3080 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3081 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3082 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3083 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3084 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3085 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3086 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3087 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3088 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3089 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3090 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3091 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3092 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3093 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3095 //===----------------------------------------------------------------------===//
3096 // SSE4.1 Instructions
3097 //===----------------------------------------------------------------------===//
3099 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3102 Intrinsic V2F64Int> {
3103 // Intrinsic operation, reg.
3104 // Vector intrinsic operation, reg
3105 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3106 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3107 !strconcat(OpcodeStr,
3108 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3109 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3112 // Vector intrinsic operation, mem
3113 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3114 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3115 !strconcat(OpcodeStr,
3116 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3118 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3121 // Vector intrinsic operation, reg
3122 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3123 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3124 !strconcat(OpcodeStr,
3125 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3126 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3129 // Vector intrinsic operation, mem
3130 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3131 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3132 !strconcat(OpcodeStr,
3133 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3135 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3139 let Constraints = "$src1 = $dst" in {
3140 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3144 // Intrinsic operation, reg.
3145 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3147 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3148 !strconcat(OpcodeStr,
3149 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3151 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3154 // Intrinsic operation, mem.
3155 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3157 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3158 !strconcat(OpcodeStr,
3159 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3161 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3164 // Intrinsic operation, reg.
3165 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3167 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3168 !strconcat(OpcodeStr,
3169 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3171 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3174 // Intrinsic operation, mem.
3175 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3177 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3178 !strconcat(OpcodeStr,
3179 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3181 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3186 // FP round - roundss, roundps, roundsd, roundpd
3187 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3188 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3189 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3190 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3192 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3193 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3194 Intrinsic IntId128> {
3195 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3198 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3199 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3201 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3207 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3208 int_x86_sse41_phminposuw>;
3210 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3211 let Constraints = "$src1 = $dst" in {
3212 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3213 Intrinsic IntId128, bit Commutable = 0> {
3214 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3215 (ins VR128:$src1, VR128:$src2),
3216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3217 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3219 let isCommutable = Commutable;
3221 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3222 (ins VR128:$src1, i128mem:$src2),
3223 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3225 (IntId128 VR128:$src1,
3226 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3230 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3231 int_x86_sse41_pcmpeqq, 1>;
3232 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3233 int_x86_sse41_packusdw, 0>;
3234 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3235 int_x86_sse41_pminsb, 1>;
3236 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3237 int_x86_sse41_pminsd, 1>;
3238 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3239 int_x86_sse41_pminud, 1>;
3240 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3241 int_x86_sse41_pminuw, 1>;
3242 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3243 int_x86_sse41_pmaxsb, 1>;
3244 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3245 int_x86_sse41_pmaxsd, 1>;
3246 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3247 int_x86_sse41_pmaxud, 1>;
3248 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3249 int_x86_sse41_pmaxuw, 1>;
3251 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3253 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3254 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3255 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3256 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3258 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3259 let Constraints = "$src1 = $dst" in {
3260 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3261 SDNode OpNode, Intrinsic IntId128,
3262 bit Commutable = 0> {
3263 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3264 (ins VR128:$src1, VR128:$src2),
3265 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3266 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3267 VR128:$src2))]>, OpSize {
3268 let isCommutable = Commutable;
3270 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3271 (ins VR128:$src1, VR128:$src2),
3272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3273 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3275 let isCommutable = Commutable;
3277 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3278 (ins VR128:$src1, i128mem:$src2),
3279 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3281 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3282 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3283 (ins VR128:$src1, i128mem:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3290 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3291 int_x86_sse41_pmulld, 1>;
3293 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3294 let Constraints = "$src1 = $dst" in {
3295 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3296 Intrinsic IntId128, bit Commutable = 0> {
3297 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3298 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3299 !strconcat(OpcodeStr,
3300 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3302 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3304 let isCommutable = Commutable;
3306 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3307 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3308 !strconcat(OpcodeStr,
3309 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3311 (IntId128 VR128:$src1,
3312 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3317 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3318 int_x86_sse41_blendps, 0>;
3319 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3320 int_x86_sse41_blendpd, 0>;
3321 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3322 int_x86_sse41_pblendw, 0>;
3323 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3324 int_x86_sse41_dpps, 1>;
3325 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3326 int_x86_sse41_dppd, 1>;
3327 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3328 int_x86_sse41_mpsadbw, 1>;
3331 /// SS41I_ternary_int - SSE 4.1 ternary operator
3332 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3333 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3334 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3335 (ins VR128:$src1, VR128:$src2),
3336 !strconcat(OpcodeStr,
3337 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3338 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3341 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3342 (ins VR128:$src1, i128mem:$src2),
3343 !strconcat(OpcodeStr,
3344 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3347 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3351 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3352 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3353 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3356 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3357 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3359 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3361 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3362 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3364 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3368 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3369 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3370 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3371 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3372 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3373 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3375 // Common patterns involving scalar load.
3376 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3377 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3378 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3379 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3381 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3382 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3383 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3384 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3386 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3387 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3388 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3389 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3391 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3392 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3393 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3394 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3396 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3397 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3398 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3399 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3401 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3402 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3403 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3404 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3407 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3408 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3409 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3410 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3412 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3413 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3415 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3419 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3420 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3421 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3422 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3424 // Common patterns involving scalar load
3425 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3426 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3427 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3428 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3430 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3431 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3432 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3433 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3436 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3437 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3439 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3441 // Expecting a i16 load any extended to i32 value.
3442 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3443 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3444 [(set VR128:$dst, (IntId (bitconvert
3445 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3449 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3450 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3452 // Common patterns involving scalar load
3453 def : Pat<(int_x86_sse41_pmovsxbq
3454 (bitconvert (v4i32 (X86vzmovl
3455 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3456 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3458 def : Pat<(int_x86_sse41_pmovzxbq
3459 (bitconvert (v4i32 (X86vzmovl
3460 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3461 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3464 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3465 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3466 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3467 (ins VR128:$src1, i32i8imm:$src2),
3468 !strconcat(OpcodeStr,
3469 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3470 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3472 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3473 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3474 !strconcat(OpcodeStr,
3475 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3478 // There's an AssertZext in the way of writing the store pattern
3479 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3482 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3485 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3486 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3487 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3488 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3489 !strconcat(OpcodeStr,
3490 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3493 // There's an AssertZext in the way of writing the store pattern
3494 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3497 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3500 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3501 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3502 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3503 (ins VR128:$src1, i32i8imm:$src2),
3504 !strconcat(OpcodeStr,
3505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3507 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3508 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3509 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3510 !strconcat(OpcodeStr,
3511 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3512 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3513 addr:$dst)]>, OpSize;
3516 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3519 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3521 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3522 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3523 (ins VR128:$src1, i32i8imm:$src2),
3524 !strconcat(OpcodeStr,
3525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3527 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3529 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3530 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3531 !strconcat(OpcodeStr,
3532 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3533 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3534 addr:$dst)]>, OpSize;
3537 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3539 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3540 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3543 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3544 Requires<[HasSSE41]>;
3546 let Constraints = "$src1 = $dst" in {
3547 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3548 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3549 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3550 !strconcat(OpcodeStr,
3551 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3553 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3554 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3555 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3556 !strconcat(OpcodeStr,
3557 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3559 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3560 imm:$src3))]>, OpSize;
3564 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3566 let Constraints = "$src1 = $dst" in {
3567 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3568 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3569 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3570 !strconcat(OpcodeStr,
3571 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3573 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3575 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3576 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3577 !strconcat(OpcodeStr,
3578 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3580 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3581 imm:$src3)))]>, OpSize;
3585 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3587 let Constraints = "$src1 = $dst" in {
3588 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3589 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3590 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3591 !strconcat(OpcodeStr,
3592 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3594 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3595 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3596 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3597 !strconcat(OpcodeStr,
3598 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3600 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3601 imm:$src3))]>, OpSize;
3605 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3607 let Defs = [EFLAGS] in {
3608 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3609 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3610 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3611 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3614 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3615 "movntdqa\t{$src, $dst|$dst, $src}",
3616 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3618 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3619 let Constraints = "$src1 = $dst" in {
3620 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3621 Intrinsic IntId128, bit Commutable = 0> {
3622 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3623 (ins VR128:$src1, VR128:$src2),
3624 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3625 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3627 let isCommutable = Commutable;
3629 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3630 (ins VR128:$src1, i128mem:$src2),
3631 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3633 (IntId128 VR128:$src1,
3634 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3638 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3640 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3641 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3642 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3643 (PCMPGTQrm VR128:$src1, addr:$src2)>;