1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (COPY_TO_REGCLASS FR32:$src, VR128)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (COPY_TO_REGCLASS FR64:$src, VR128)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
387 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
402 isPseudo = 1, Predicates = [HasAVX] in {
403 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
404 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
407 let Predicates = [HasAVX] in
408 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
410 let Predicates = [HasAVX2] in {
411 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
412 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
413 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
417 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
418 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
419 let Predicates = [HasAVX1Only] in {
420 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
421 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
422 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
424 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
425 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
426 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
428 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
429 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
430 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
432 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
433 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
434 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
437 // We set canFoldAsLoad because this can be converted to a constant-pool
438 // load of an all-ones value if folding it would be beneficial.
439 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
441 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
442 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
443 let Predicates = [HasAVX2] in
444 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
445 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
449 //===----------------------------------------------------------------------===//
450 // SSE 1 & 2 - Move FP Scalar Instructions
452 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
453 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
454 // is used instead. Register-to-register movss/movsd is not modeled as an
455 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
456 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
457 //===----------------------------------------------------------------------===//
459 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
460 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
461 [(set VR128:$dst, (vt (OpNode VR128:$src1,
462 (scalar_to_vector RC:$src2))))],
465 // Loading from memory automatically zeroing upper bits.
466 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
467 PatFrag mem_pat, string OpcodeStr> :
468 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
469 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
470 [(set RC:$dst, (mem_pat addr:$src))],
474 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
475 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
477 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
478 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
481 // For the disassembler
482 let isCodeGenOnly = 1 in {
483 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
484 (ins VR128:$src1, FR32:$src2),
485 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
488 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
489 (ins VR128:$src1, FR64:$src2),
490 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
495 let canFoldAsLoad = 1, isReMaterializable = 1 in {
496 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
498 let AddedComplexity = 20 in
499 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
503 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
504 "movss\t{$src, $dst|$dst, $src}",
505 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
507 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
508 "movsd\t{$src, $dst|$dst, $src}",
509 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
513 let Constraints = "$src1 = $dst" in {
514 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
515 "movss\t{$src2, $dst|$dst, $src2}">, XS;
516 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
517 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
519 // For the disassembler
520 let isCodeGenOnly = 1 in {
521 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
522 (ins VR128:$src1, FR32:$src2),
523 "movss\t{$src2, $dst|$dst, $src2}", [],
524 IIC_SSE_MOV_S_RR>, XS;
525 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
526 (ins VR128:$src1, FR64:$src2),
527 "movsd\t{$src2, $dst|$dst, $src2}", [],
528 IIC_SSE_MOV_S_RR>, XD;
532 let canFoldAsLoad = 1, isReMaterializable = 1 in {
533 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
535 let AddedComplexity = 20 in
536 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
539 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
540 "movss\t{$src, $dst|$dst, $src}",
541 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
542 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
543 "movsd\t{$src, $dst|$dst, $src}",
544 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
547 let Predicates = [HasAVX] in {
548 let AddedComplexity = 15 in {
549 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
550 // MOVS{S,D} to the lower bits.
551 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
552 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
553 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
554 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
555 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
556 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
557 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
558 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
560 // Move low f32 and clear high bits.
561 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
562 (SUBREG_TO_REG (i32 0),
563 (VMOVSSrr (v4f32 (V_SET0)),
564 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
565 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
566 (SUBREG_TO_REG (i32 0),
567 (VMOVSSrr (v4i32 (V_SET0)),
568 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
571 let AddedComplexity = 20 in {
572 // MOVSSrm zeros the high parts of the register; represent this
573 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
574 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
575 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
576 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
578 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
581 // MOVSDrm zeros the high parts of the register; represent this
582 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
583 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
584 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
585 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
586 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
587 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
589 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
590 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
591 def : Pat<(v2f64 (X86vzload addr:$src)),
592 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
594 // Represent the same patterns above but in the form they appear for
596 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
597 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
598 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
599 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
600 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
601 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
602 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
603 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
604 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
606 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
607 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
608 (SUBREG_TO_REG (i32 0),
609 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
611 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
612 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
613 (SUBREG_TO_REG (i64 0),
614 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
616 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
617 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
618 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
620 // Move low f64 and clear high bits.
621 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
622 (SUBREG_TO_REG (i32 0),
623 (VMOVSDrr (v2f64 (V_SET0)),
624 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
626 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
627 (SUBREG_TO_REG (i32 0),
628 (VMOVSDrr (v2i64 (V_SET0)),
629 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
631 // Extract and store.
632 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
634 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
635 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
637 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
639 // Shuffle with VMOVSS
640 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
641 (VMOVSSrr (v4i32 VR128:$src1),
642 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
643 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
644 (VMOVSSrr (v4f32 VR128:$src1),
645 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
648 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
649 (SUBREG_TO_REG (i32 0),
650 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
651 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
653 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
654 (SUBREG_TO_REG (i32 0),
655 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
656 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
659 // Shuffle with VMOVSD
660 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
661 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
662 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
663 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
664 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
665 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
666 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
671 (SUBREG_TO_REG (i32 0),
672 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
673 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
675 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
676 (SUBREG_TO_REG (i32 0),
677 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
678 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
682 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
683 // is during lowering, where it's not possible to recognize the fold cause
684 // it has two uses through a bitcast. One use disappears at isel time and the
685 // fold opportunity reappears.
686 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
687 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
688 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
689 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
690 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
691 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
692 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
693 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
696 let Predicates = [UseSSE1] in {
697 let AddedComplexity = 15 in {
698 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
699 // MOVSS to the lower bits.
700 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
701 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
702 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
703 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
704 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
705 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
708 let AddedComplexity = 20 in {
709 // MOVSSrm already zeros the high parts of the register.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
711 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
712 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
713 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
714 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
715 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
718 // Extract and store.
719 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
721 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
723 // Shuffle with MOVSS
724 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
725 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
726 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
727 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
730 let Predicates = [UseSSE2] in {
731 let AddedComplexity = 15 in {
732 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
733 // MOVSD to the lower bits.
734 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
735 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
738 let AddedComplexity = 20 in {
739 // MOVSDrm already zeros the high parts of the register.
740 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
741 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
742 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
743 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
744 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
745 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
746 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
747 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
748 def : Pat<(v2f64 (X86vzload addr:$src)),
749 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 // Extract and store.
753 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
755 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
757 // Shuffle with MOVSD
758 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
759 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
760 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
761 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
762 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
763 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
764 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
765 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
767 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
768 // is during lowering, where it's not possible to recognize the fold cause
769 // it has two uses through a bitcast. One use disappears at isel time and the
770 // fold opportunity reappears.
771 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
772 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
773 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
778 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
781 //===----------------------------------------------------------------------===//
782 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
783 //===----------------------------------------------------------------------===//
785 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
786 X86MemOperand x86memop, PatFrag ld_frag,
787 string asm, Domain d,
789 bit IsReMaterializable = 1> {
790 let neverHasSideEffects = 1 in
791 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
792 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
793 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
794 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
795 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
796 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
799 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
800 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
802 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
803 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
805 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
806 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
808 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
809 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
812 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
813 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
815 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
816 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
818 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
819 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
821 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
822 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
838 "movaps\t{$src, $dst|$dst, $src}",
839 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
840 IIC_SSE_MOVA_P_MR>, VEX;
841 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
842 "movapd\t{$src, $dst|$dst, $src}",
843 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
844 IIC_SSE_MOVA_P_MR>, VEX;
845 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
846 "movups\t{$src, $dst|$dst, $src}",
847 [(store (v4f32 VR128:$src), addr:$dst)],
848 IIC_SSE_MOVU_P_MR>, VEX;
849 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
850 "movupd\t{$src, $dst|$dst, $src}",
851 [(store (v2f64 VR128:$src), addr:$dst)],
852 IIC_SSE_MOVU_P_MR>, VEX;
853 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
854 "movaps\t{$src, $dst|$dst, $src}",
855 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
856 IIC_SSE_MOVA_P_MR>, VEX;
857 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
858 "movapd\t{$src, $dst|$dst, $src}",
859 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
860 IIC_SSE_MOVA_P_MR>, VEX;
861 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
862 "movups\t{$src, $dst|$dst, $src}",
863 [(store (v8f32 VR256:$src), addr:$dst)],
864 IIC_SSE_MOVU_P_MR>, VEX;
865 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
866 "movupd\t{$src, $dst|$dst, $src}",
867 [(store (v4f64 VR256:$src), addr:$dst)],
868 IIC_SSE_MOVU_P_MR>, VEX;
871 let isCodeGenOnly = 1 in {
872 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
874 "movaps\t{$src, $dst|$dst, $src}", [],
875 IIC_SSE_MOVA_P_RR>, VEX;
876 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
878 "movapd\t{$src, $dst|$dst, $src}", [],
879 IIC_SSE_MOVA_P_RR>, VEX;
880 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
882 "movups\t{$src, $dst|$dst, $src}", [],
883 IIC_SSE_MOVU_P_RR>, VEX;
884 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
886 "movupd\t{$src, $dst|$dst, $src}", [],
887 IIC_SSE_MOVU_P_RR>, VEX;
888 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
890 "movaps\t{$src, $dst|$dst, $src}", [],
891 IIC_SSE_MOVA_P_RR>, VEX;
892 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
894 "movapd\t{$src, $dst|$dst, $src}", [],
895 IIC_SSE_MOVA_P_RR>, VEX;
896 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
898 "movups\t{$src, $dst|$dst, $src}", [],
899 IIC_SSE_MOVU_P_RR>, VEX;
900 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
902 "movupd\t{$src, $dst|$dst, $src}", [],
903 IIC_SSE_MOVU_P_RR>, VEX;
906 let Predicates = [HasAVX] in {
907 def : Pat<(v8i32 (X86vzmovl
908 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
909 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
910 def : Pat<(v4i64 (X86vzmovl
911 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
912 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
913 def : Pat<(v8f32 (X86vzmovl
914 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
915 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
916 def : Pat<(v4f64 (X86vzmovl
917 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
918 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
922 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
923 (VMOVUPSYmr addr:$dst, VR256:$src)>;
924 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
925 (VMOVUPDYmr addr:$dst, VR256:$src)>;
927 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
928 "movaps\t{$src, $dst|$dst, $src}",
929 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
931 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
932 "movapd\t{$src, $dst|$dst, $src}",
933 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
935 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
936 "movups\t{$src, $dst|$dst, $src}",
937 [(store (v4f32 VR128:$src), addr:$dst)],
939 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
940 "movupd\t{$src, $dst|$dst, $src}",
941 [(store (v2f64 VR128:$src), addr:$dst)],
945 let isCodeGenOnly = 1 in {
946 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
947 "movaps\t{$src, $dst|$dst, $src}", [],
949 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
950 "movapd\t{$src, $dst|$dst, $src}", [],
952 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
953 "movups\t{$src, $dst|$dst, $src}", [],
955 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
956 "movupd\t{$src, $dst|$dst, $src}", [],
960 let Predicates = [HasAVX] in {
961 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
962 (VMOVUPSmr addr:$dst, VR128:$src)>;
963 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
964 (VMOVUPDmr addr:$dst, VR128:$src)>;
967 let Predicates = [UseSSE1] in
968 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
969 (MOVUPSmr addr:$dst, VR128:$src)>;
970 let Predicates = [UseSSE2] in
971 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
972 (MOVUPDmr addr:$dst, VR128:$src)>;
974 // Use vmovaps/vmovups for AVX integer load/store.
975 let Predicates = [HasAVX] in {
976 // 128-bit load/store
977 def : Pat<(alignedloadv2i64 addr:$src),
978 (VMOVAPSrm addr:$src)>;
979 def : Pat<(loadv2i64 addr:$src),
980 (VMOVUPSrm addr:$src)>;
982 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
983 (VMOVAPSmr addr:$dst, VR128:$src)>;
984 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
985 (VMOVAPSmr addr:$dst, VR128:$src)>;
986 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
987 (VMOVAPSmr addr:$dst, VR128:$src)>;
988 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
989 (VMOVAPSmr addr:$dst, VR128:$src)>;
990 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
993 (VMOVUPSmr addr:$dst, VR128:$src)>;
994 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
995 (VMOVUPSmr addr:$dst, VR128:$src)>;
996 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
999 // 256-bit load/store
1000 def : Pat<(alignedloadv4i64 addr:$src),
1001 (VMOVAPSYrm addr:$src)>;
1002 def : Pat<(loadv4i64 addr:$src),
1003 (VMOVUPSYrm addr:$src)>;
1004 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1005 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1006 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1007 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1008 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1009 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1010 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1011 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1012 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1013 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1014 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1015 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1016 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1017 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1018 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1019 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1022 // Use movaps / movups for SSE integer load / store (one byte shorter).
1023 // The instructions selected below are then converted to MOVDQA/MOVDQU
1024 // during the SSE domain pass.
1025 let Predicates = [UseSSE1] in {
1026 def : Pat<(alignedloadv2i64 addr:$src),
1027 (MOVAPSrm addr:$src)>;
1028 def : Pat<(loadv2i64 addr:$src),
1029 (MOVUPSrm addr:$src)>;
1031 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1032 (MOVAPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1034 (MOVAPSmr addr:$dst, VR128:$src)>;
1035 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1036 (MOVAPSmr addr:$dst, VR128:$src)>;
1037 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1038 (MOVAPSmr addr:$dst, VR128:$src)>;
1039 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1040 (MOVUPSmr addr:$dst, VR128:$src)>;
1041 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1042 (MOVUPSmr addr:$dst, VR128:$src)>;
1043 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1044 (MOVUPSmr addr:$dst, VR128:$src)>;
1045 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1046 (MOVUPSmr addr:$dst, VR128:$src)>;
1049 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1050 // bits are disregarded. FIXME: Set encoding to pseudo!
1051 let neverHasSideEffects = 1 in {
1052 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1053 "movaps\t{$src, $dst|$dst, $src}", [],
1054 IIC_SSE_MOVA_P_RR>, VEX;
1055 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1056 "movapd\t{$src, $dst|$dst, $src}", [],
1057 IIC_SSE_MOVA_P_RR>, VEX;
1058 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1059 "movaps\t{$src, $dst|$dst, $src}", [],
1061 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1062 "movapd\t{$src, $dst|$dst, $src}", [],
1066 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1067 // bits are disregarded. FIXME: Set encoding to pseudo!
1068 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1069 let isCodeGenOnly = 1 in {
1070 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1071 "movaps\t{$src, $dst|$dst, $src}",
1072 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1073 IIC_SSE_MOVA_P_RM>, VEX;
1074 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1075 "movapd\t{$src, $dst|$dst, $src}",
1076 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1077 IIC_SSE_MOVA_P_RM>, VEX;
1079 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1080 "movaps\t{$src, $dst|$dst, $src}",
1081 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1083 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1084 "movapd\t{$src, $dst|$dst, $src}",
1085 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1089 //===----------------------------------------------------------------------===//
1090 // SSE 1 & 2 - Move Low packed FP Instructions
1091 //===----------------------------------------------------------------------===//
1093 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1094 SDNode psnode, SDNode pdnode, string base_opc,
1095 string asm_opr, InstrItinClass itin> {
1096 def PSrm : PI<opc, MRMSrcMem,
1097 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1098 !strconcat(base_opc, "s", asm_opr),
1101 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1102 itin, SSEPackedSingle>, TB;
1104 def PDrm : PI<opc, MRMSrcMem,
1105 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1106 !strconcat(base_opc, "d", asm_opr),
1107 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1108 (scalar_to_vector (loadf64 addr:$src2)))))],
1109 itin, SSEPackedDouble>, TB, OpSize;
1112 let AddedComplexity = 20 in {
1113 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1115 IIC_SSE_MOV_LH>, VEX_4V;
1117 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1118 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1119 "\t{$src2, $dst|$dst, $src2}",
1123 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movlps\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1126 (iPTR 0))), addr:$dst)],
1127 IIC_SSE_MOV_LH>, VEX;
1128 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1129 "movlpd\t{$src, $dst|$dst, $src}",
1130 [(store (f64 (vector_extract (v2f64 VR128:$src),
1131 (iPTR 0))), addr:$dst)],
1132 IIC_SSE_MOV_LH>, VEX;
1133 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1134 "movlps\t{$src, $dst|$dst, $src}",
1135 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1136 (iPTR 0))), addr:$dst)],
1138 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1139 "movlpd\t{$src, $dst|$dst, $src}",
1140 [(store (f64 (vector_extract (v2f64 VR128:$src),
1141 (iPTR 0))), addr:$dst)],
1144 let Predicates = [HasAVX] in {
1145 // Shuffle with VMOVLPS
1146 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1147 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1148 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1149 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1151 // Shuffle with VMOVLPD
1152 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1153 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1154 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1155 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1158 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1160 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1161 def : Pat<(store (v4i32 (X86Movlps
1162 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1163 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1164 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1166 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1167 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1169 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1172 let Predicates = [UseSSE1] in {
1173 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1174 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1175 (iPTR 0))), addr:$src1),
1176 (MOVLPSmr addr:$src1, VR128:$src2)>;
1178 // Shuffle with MOVLPS
1179 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1180 (MOVLPSrm VR128:$src1, addr:$src2)>;
1181 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1182 (MOVLPSrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(X86Movlps VR128:$src1,
1184 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1185 (MOVLPSrm VR128:$src1, addr:$src2)>;
1188 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1190 (MOVLPSmr addr:$src1, VR128:$src2)>;
1191 def : Pat<(store (v4i32 (X86Movlps
1192 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1194 (MOVLPSmr addr:$src1, VR128:$src2)>;
1197 let Predicates = [UseSSE2] in {
1198 // Shuffle with MOVLPD
1199 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1200 (MOVLPDrm VR128:$src1, addr:$src2)>;
1201 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1202 (MOVLPDrm VR128:$src1, addr:$src2)>;
1205 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1207 (MOVLPDmr addr:$src1, VR128:$src2)>;
1208 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1210 (MOVLPDmr addr:$src1, VR128:$src2)>;
1213 //===----------------------------------------------------------------------===//
1214 // SSE 1 & 2 - Move Hi packed FP Instructions
1215 //===----------------------------------------------------------------------===//
1217 let AddedComplexity = 20 in {
1218 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1220 IIC_SSE_MOV_LH>, VEX_4V;
1222 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1223 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1224 "\t{$src2, $dst|$dst, $src2}",
1228 // v2f64 extract element 1 is always custom lowered to unpack high to low
1229 // and extract element 0 so the non-store version isn't too horrible.
1230 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1231 "movhps\t{$src, $dst|$dst, $src}",
1232 [(store (f64 (vector_extract
1233 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1234 (bc_v2f64 (v4f32 VR128:$src))),
1235 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1236 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1237 "movhpd\t{$src, $dst|$dst, $src}",
1238 [(store (f64 (vector_extract
1239 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1240 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1241 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1242 "movhps\t{$src, $dst|$dst, $src}",
1243 [(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))),
1246 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1247 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1248 "movhpd\t{$src, $dst|$dst, $src}",
1249 [(store (f64 (vector_extract
1250 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1251 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1253 let Predicates = [HasAVX] in {
1255 def : Pat<(X86Movlhps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1258 def : Pat<(X86Movlhps VR128:$src1,
1259 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1260 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1262 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1263 // is during lowering, where it's not possible to recognize the load fold
1264 // cause it has two uses through a bitcast. One use disappears at isel time
1265 // and the fold opportunity reappears.
1266 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1267 (scalar_to_vector (loadf64 addr:$src2)))),
1268 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1271 let Predicates = [UseSSE1] in {
1273 def : Pat<(X86Movlhps VR128:$src1,
1274 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1275 (MOVHPSrm VR128:$src1, addr:$src2)>;
1276 def : Pat<(X86Movlhps VR128:$src1,
1277 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1278 (MOVHPSrm VR128:$src1, addr:$src2)>;
1281 let Predicates = [UseSSE2] in {
1282 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1283 // is during lowering, where it's not possible to recognize the load fold
1284 // cause it has two uses through a bitcast. One use disappears at isel time
1285 // and the fold opportunity reappears.
1286 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1287 (scalar_to_vector (loadf64 addr:$src2)))),
1288 (MOVHPDrm VR128:$src1, addr:$src2)>;
1291 //===----------------------------------------------------------------------===//
1292 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1293 //===----------------------------------------------------------------------===//
1295 let AddedComplexity = 20 in {
1296 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1297 (ins VR128:$src1, VR128:$src2),
1298 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1300 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1303 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1304 (ins VR128:$src1, VR128:$src2),
1305 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1307 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1311 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1312 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 "movlhps\t{$src2, $dst|$dst, $src2}",
1316 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1318 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1319 (ins VR128:$src1, VR128:$src2),
1320 "movhlps\t{$src2, $dst|$dst, $src2}",
1322 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1329 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1330 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1331 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1334 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1335 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1338 let Predicates = [UseSSE1] in {
1340 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1341 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1342 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1343 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1346 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1347 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1350 //===----------------------------------------------------------------------===//
1351 // SSE 1 & 2 - Conversion Instructions
1352 //===----------------------------------------------------------------------===//
1354 def SSE_CVT_PD : OpndItins<
1355 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1358 def SSE_CVT_PS : OpndItins<
1359 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1362 def SSE_CVT_Scalar : OpndItins<
1363 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1366 def SSE_CVT_SS2SI_32 : OpndItins<
1367 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1370 def SSE_CVT_SS2SI_64 : OpndItins<
1371 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1374 def SSE_CVT_SD2SI : OpndItins<
1375 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1378 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1379 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1380 string asm, OpndItins itins> {
1381 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1382 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1384 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1385 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1389 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1390 X86MemOperand x86memop, string asm, Domain d,
1392 let neverHasSideEffects = 1 in {
1393 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1396 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1401 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1402 X86MemOperand x86memop, string asm> {
1403 let neverHasSideEffects = 1 in {
1404 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1405 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1407 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1408 (ins DstRC:$src1, x86memop:$src),
1409 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1410 } // neverHasSideEffects = 1
1413 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1414 "cvttss2si\t{$src, $dst|$dst, $src}",
1417 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1418 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1420 XS, VEX, VEX_W, VEX_LIG;
1421 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1422 "cvttsd2si\t{$src, $dst|$dst, $src}",
1425 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1426 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1428 XD, VEX, VEX_W, VEX_LIG;
1430 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1431 // register, but the same isn't true when only using memory operands,
1432 // provide other assembly "l" and "q" forms to address this explicitly
1433 // where appropriate to do so.
1434 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1435 XS, VEX_4V, VEX_LIG;
1436 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1437 XS, VEX_4V, VEX_W, VEX_LIG;
1438 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1439 XD, VEX_4V, VEX_LIG;
1440 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1441 XD, VEX_4V, VEX_W, VEX_LIG;
1443 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1444 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1445 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1446 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1448 let Predicates = [HasAVX] in {
1449 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1450 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1451 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1452 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1453 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1454 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1455 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1456 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1458 def : Pat<(f32 (sint_to_fp GR32:$src)),
1459 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1460 def : Pat<(f32 (sint_to_fp GR64:$src)),
1461 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1462 def : Pat<(f64 (sint_to_fp GR32:$src)),
1463 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1464 def : Pat<(f64 (sint_to_fp GR64:$src)),
1465 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1468 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1469 "cvttss2si\t{$src, $dst|$dst, $src}",
1470 SSE_CVT_SS2SI_32>, XS;
1471 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1473 SSE_CVT_SS2SI_64>, XS, REX_W;
1474 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1475 "cvttsd2si\t{$src, $dst|$dst, $src}",
1477 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1478 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1479 SSE_CVT_SD2SI>, XD, REX_W;
1480 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1481 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1482 SSE_CVT_Scalar>, XS;
1483 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1484 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1485 SSE_CVT_Scalar>, XS, REX_W;
1486 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1487 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1488 SSE_CVT_Scalar>, XD;
1489 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1490 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1491 SSE_CVT_Scalar>, XD, REX_W;
1493 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1494 // and/or XMM operand(s).
1496 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1497 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1498 string asm, OpndItins itins> {
1499 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1500 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1501 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1502 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1503 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1504 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1507 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1508 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1509 PatFrag ld_frag, string asm, OpndItins itins,
1511 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1513 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1514 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1515 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1517 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1518 (ins DstRC:$src1, x86memop:$src2),
1520 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1521 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1522 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1526 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1527 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1528 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1529 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1530 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1531 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1533 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1534 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1535 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1536 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1539 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1540 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1541 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1542 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1543 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1544 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1546 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1547 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1548 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1549 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1550 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1551 SSE_CVT_Scalar, 0>, XD,
1554 let Constraints = "$src1 = $dst" in {
1555 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1556 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1557 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1558 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1559 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1560 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1561 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1562 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1563 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1564 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1565 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1566 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1571 // Aliases for intrinsics
1572 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1573 ssmem, sse_load_f32, "cvttss2si",
1574 SSE_CVT_SS2SI_32>, XS, VEX;
1575 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1576 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1577 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1579 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1580 sdmem, sse_load_f64, "cvttsd2si",
1581 SSE_CVT_SD2SI>, XD, VEX;
1582 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1583 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1584 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1586 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1587 ssmem, sse_load_f32, "cvttss2si",
1588 SSE_CVT_SS2SI_32>, XS;
1589 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1590 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1591 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1592 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1593 sdmem, sse_load_f64, "cvttsd2si",
1595 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1596 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1597 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1599 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1600 ssmem, sse_load_f32, "cvtss2si{l}",
1601 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1602 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1603 ssmem, sse_load_f32, "cvtss2si{q}",
1604 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1606 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1607 ssmem, sse_load_f32, "cvtss2si{l}",
1608 SSE_CVT_SS2SI_32>, XS;
1609 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1610 ssmem, sse_load_f32, "cvtss2si{q}",
1611 SSE_CVT_SS2SI_64>, XS, REX_W;
1613 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1614 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1615 SSEPackedSingle, SSE_CVT_PS>,
1616 TB, VEX, Requires<[HasAVX]>;
1617 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1618 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1619 SSEPackedSingle, SSE_CVT_PS>,
1620 TB, VEX, Requires<[HasAVX]>;
1622 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1623 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1624 SSEPackedSingle, SSE_CVT_PS>,
1625 TB, Requires<[UseSSE2]>;
1629 // Convert scalar double to scalar single
1630 let neverHasSideEffects = 1 in {
1631 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1632 (ins FR64:$src1, FR64:$src2),
1633 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1634 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1636 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1637 (ins FR64:$src1, f64mem:$src2),
1638 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1639 [], IIC_SSE_CVT_Scalar_RM>,
1640 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1643 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1646 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1647 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1648 [(set FR32:$dst, (fround FR64:$src))],
1649 IIC_SSE_CVT_Scalar_RR>;
1650 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1651 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1652 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1653 IIC_SSE_CVT_Scalar_RM>,
1655 Requires<[UseSSE2, OptForSize]>;
1657 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1658 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1659 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1661 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1662 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1663 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1664 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1665 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1667 VR128:$src1, sse_load_f64:$src2))],
1668 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1670 let Constraints = "$src1 = $dst" in {
1671 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1672 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1673 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1675 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1676 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1677 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1678 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1679 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1680 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1681 VR128:$src1, sse_load_f64:$src2))],
1682 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1685 // Convert scalar single to scalar double
1686 // SSE2 instructions with XS prefix
1687 let neverHasSideEffects = 1 in {
1688 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1689 (ins FR32:$src1, FR32:$src2),
1690 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1691 [], IIC_SSE_CVT_Scalar_RR>,
1692 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1694 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1695 (ins FR32:$src1, f32mem:$src2),
1696 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1697 [], IIC_SSE_CVT_Scalar_RM>,
1698 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1701 def : Pat<(f64 (fextend FR32:$src)),
1702 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1703 def : Pat<(fextend (loadf32 addr:$src)),
1704 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1706 def : Pat<(extloadf32 addr:$src),
1707 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1708 Requires<[HasAVX, OptForSize]>;
1709 def : Pat<(extloadf32 addr:$src),
1710 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1711 Requires<[HasAVX, OptForSpeed]>;
1713 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1714 "cvtss2sd\t{$src, $dst|$dst, $src}",
1715 [(set FR64:$dst, (fextend FR32:$src))],
1716 IIC_SSE_CVT_Scalar_RR>, XS,
1717 Requires<[UseSSE2]>;
1718 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1719 "cvtss2sd\t{$src, $dst|$dst, $src}",
1720 [(set FR64:$dst, (extloadf32 addr:$src))],
1721 IIC_SSE_CVT_Scalar_RM>, XS,
1722 Requires<[UseSSE2, OptForSize]>;
1724 // extload f32 -> f64. This matches load+fextend because we have a hack in
1725 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1727 // Since these loads aren't folded into the fextend, we have to match it
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1734 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1735 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1736 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1738 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1739 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1740 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1741 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1742 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1744 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1745 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1746 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1747 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1751 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1752 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1753 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1754 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1755 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1757 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1758 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1761 // Convert packed single/double fp to doubleword
1762 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1763 "cvtps2dq\t{$src, $dst|$dst, $src}",
1764 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1765 IIC_SSE_CVT_PS_RR>, VEX;
1766 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1767 "cvtps2dq\t{$src, $dst|$dst, $src}",
1769 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1770 IIC_SSE_CVT_PS_RM>, VEX;
1771 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1772 "cvtps2dq\t{$src, $dst|$dst, $src}",
1774 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1775 IIC_SSE_CVT_PS_RR>, VEX;
1776 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1777 "cvtps2dq\t{$src, $dst|$dst, $src}",
1779 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1780 IIC_SSE_CVT_PS_RM>, VEX;
1781 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 "cvtps2dq\t{$src, $dst|$dst, $src}",
1783 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1785 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1786 "cvtps2dq\t{$src, $dst|$dst, $src}",
1788 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1792 // Convert Packed Double FP to Packed DW Integers
1793 let Predicates = [HasAVX] in {
1794 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1795 // register, but the same isn't true when using memory operands instead.
1796 // Provide other assembly rr and rm forms to address this explicitly.
1797 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1798 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1799 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1803 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1804 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1805 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1806 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1808 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1811 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1812 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1814 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX;
1815 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1816 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1818 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1820 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1821 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1824 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1825 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1827 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1829 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1831 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1834 // Convert with truncation packed single/double fp to doubleword
1835 // SSE2 packed instructions with XS prefix
1836 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1837 "cvttps2dq\t{$src, $dst|$dst, $src}",
1839 (int_x86_sse2_cvttps2dq VR128:$src))],
1840 IIC_SSE_CVT_PS_RR>, VEX;
1841 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1842 "cvttps2dq\t{$src, $dst|$dst, $src}",
1843 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1844 (memopv4f32 addr:$src)))],
1845 IIC_SSE_CVT_PS_RM>, VEX;
1846 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1847 "cvttps2dq\t{$src, $dst|$dst, $src}",
1849 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1850 IIC_SSE_CVT_PS_RR>, VEX;
1851 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1852 "cvttps2dq\t{$src, $dst|$dst, $src}",
1853 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1854 (memopv8f32 addr:$src)))],
1855 IIC_SSE_CVT_PS_RM>, VEX;
1857 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1858 "cvttps2dq\t{$src, $dst|$dst, $src}",
1859 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1861 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1862 "cvttps2dq\t{$src, $dst|$dst, $src}",
1864 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1867 let Predicates = [HasAVX] in {
1868 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1869 (VCVTDQ2PSrr VR128:$src)>;
1870 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1871 (VCVTDQ2PSrm addr:$src)>;
1873 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1874 (VCVTDQ2PSrr VR128:$src)>;
1875 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1876 (VCVTDQ2PSrm addr:$src)>;
1878 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1879 (VCVTTPS2DQrr VR128:$src)>;
1880 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1881 (VCVTTPS2DQrm addr:$src)>;
1883 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1884 (VCVTDQ2PSYrr VR256:$src)>;
1885 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1886 (VCVTDQ2PSYrm addr:$src)>;
1888 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1889 (VCVTTPS2DQYrr VR256:$src)>;
1890 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1891 (VCVTTPS2DQYrm addr:$src)>;
1894 let Predicates = [UseSSE2] in {
1895 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1896 (CVTDQ2PSrr VR128:$src)>;
1897 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1898 (CVTDQ2PSrm addr:$src)>;
1900 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1901 (CVTDQ2PSrr VR128:$src)>;
1902 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1903 (CVTDQ2PSrm addr:$src)>;
1905 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1906 (CVTTPS2DQrr VR128:$src)>;
1907 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1908 (CVTTPS2DQrm addr:$src)>;
1911 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1912 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1914 (int_x86_sse2_cvttpd2dq VR128:$src))],
1915 IIC_SSE_CVT_PD_RR>, VEX;
1917 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1918 // register, but the same isn't true when using memory operands instead.
1919 // Provide other assembly rr and rm forms to address this explicitly.
1922 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1923 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1924 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1925 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1926 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1927 (memopv2f64 addr:$src)))],
1928 IIC_SSE_CVT_PD_RM>, VEX;
1931 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1932 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1934 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1935 IIC_SSE_CVT_PD_RR>, VEX;
1936 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1937 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1939 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1940 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1941 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1942 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1944 let Predicates = [HasAVX] in {
1945 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1946 (VCVTTPD2DQYrr VR256:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1948 (VCVTTPD2DQYrm addr:$src)>;
1949 } // Predicates = [HasAVX]
1951 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1952 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1953 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1955 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1956 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1958 (memopv2f64 addr:$src)))],
1961 // Convert packed single to packed double
1962 let Predicates = [HasAVX] in {
1963 // SSE2 instructions without OpSize prefix
1964 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1965 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1966 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
1967 IIC_SSE_CVT_PD_RR>, TB, VEX;
1968 let neverHasSideEffects = 1, mayLoad = 1 in
1969 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1970 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
1971 IIC_SSE_CVT_PD_RM>, TB, VEX;
1972 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1973 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1975 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
1976 IIC_SSE_CVT_PD_RR>, TB, VEX;
1977 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1978 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
1981 IIC_SSE_CVT_PD_RM>, TB, VEX;
1984 let Predicates = [UseSSE2] in {
1985 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1986 "cvtps2pd\t{$src, $dst|$dst, $src}",
1987 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
1988 IIC_SSE_CVT_PD_RR>, TB;
1989 let neverHasSideEffects = 1, mayLoad = 1 in
1990 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1991 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
1992 IIC_SSE_CVT_PD_RM>, TB;
1995 // Convert Packed DW Integers to Packed Double FP
1996 let Predicates = [HasAVX] in {
1997 let neverHasSideEffects = 1, mayLoad = 1 in
1998 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1999 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2001 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2002 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2004 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2005 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2006 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2008 (int_x86_avx_cvtdq2_pd_256
2009 (bitconvert (memopv2i64 addr:$src))))]>, VEX;
2010 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2011 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2013 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
2016 let neverHasSideEffects = 1, mayLoad = 1 in
2017 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2018 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2020 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2021 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2022 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2025 // AVX 256-bit register conversion intrinsics
2026 let Predicates = [HasAVX] in {
2027 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2028 (VCVTDQ2PDYrr VR128:$src)>;
2029 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2030 (VCVTDQ2PDYrm addr:$src)>;
2031 } // Predicates = [HasAVX]
2033 // Convert packed double to packed single
2034 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2035 // register, but the same isn't true when using memory operands instead.
2036 // Provide other assembly rr and rm forms to address this explicitly.
2037 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2038 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2039 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2040 IIC_SSE_CVT_PD_RR>, VEX;
2043 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2044 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2045 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2046 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2048 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2049 IIC_SSE_CVT_PD_RM>, VEX;
2052 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2053 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2055 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2056 IIC_SSE_CVT_PD_RR>, VEX;
2057 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2058 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2060 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2061 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2062 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2063 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2065 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2069 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2076 // AVX 256-bit register conversion intrinsics
2077 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2078 // whenever possible to avoid declaring two versions of each one.
2079 let Predicates = [HasAVX] in {
2080 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2081 (VCVTDQ2PSYrr VR256:$src)>;
2082 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2083 (VCVTDQ2PSYrm addr:$src)>;
2085 // Match fround and fextend for 128/256-bit conversions
2086 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2087 (VCVTPD2PSYrr VR256:$src)>;
2088 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2089 (VCVTPD2PSYrm addr:$src)>;
2091 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2092 (VCVTPS2PDrr VR128:$src)>;
2093 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2094 (VCVTPS2PDYrr VR128:$src)>;
2095 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2096 (VCVTPS2PDYrm addr:$src)>;
2099 let Predicates = [UseSSE2] in {
2100 // Match fextend for 128 conversions
2101 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2102 (CVTPS2PDrr VR128:$src)>;
2105 //===----------------------------------------------------------------------===//
2106 // SSE 1 & 2 - Compare Instructions
2107 //===----------------------------------------------------------------------===//
2109 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2110 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2111 Operand CC, SDNode OpNode, ValueType VT,
2112 PatFrag ld_frag, string asm, string asm_alt,
2114 def rr : SIi8<0xC2, MRMSrcReg,
2115 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2116 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2118 def rm : SIi8<0xC2, MRMSrcMem,
2119 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2120 [(set RC:$dst, (OpNode (VT RC:$src1),
2121 (ld_frag addr:$src2), imm:$cc))],
2124 // Accept explicit immediate argument form instead of comparison code.
2125 let neverHasSideEffects = 1 in {
2126 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2127 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2128 IIC_SSE_ALU_F32S_RR>;
2130 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2131 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2132 IIC_SSE_ALU_F32S_RM>;
2136 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2137 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2138 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2140 XS, VEX_4V, VEX_LIG;
2141 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2142 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2143 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2144 SSE_ALU_F32S>, // same latency as 32 bit compare
2145 XD, VEX_4V, VEX_LIG;
2147 let Constraints = "$src1 = $dst" in {
2148 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2149 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2150 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2152 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2153 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2154 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2155 SSE_ALU_F32S>, // same latency as 32 bit compare
2159 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2160 Intrinsic Int, string asm, OpndItins itins> {
2161 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2162 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2163 [(set VR128:$dst, (Int VR128:$src1,
2164 VR128:$src, imm:$cc))],
2166 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2167 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2168 [(set VR128:$dst, (Int VR128:$src1,
2169 (load addr:$src), imm:$cc))],
2173 // Aliases to match intrinsics which expect XMM operand(s).
2174 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2175 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2178 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2179 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2180 SSE_ALU_F32S>, // same latency as f32
2182 let Constraints = "$src1 = $dst" in {
2183 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2184 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2186 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2187 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2188 SSE_ALU_F32S>, // same latency as f32
2193 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2194 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2195 ValueType vt, X86MemOperand x86memop,
2196 PatFrag ld_frag, string OpcodeStr, Domain d> {
2197 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2198 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2199 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2200 IIC_SSE_COMIS_RR, d>;
2201 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2202 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2203 [(set EFLAGS, (OpNode (vt RC:$src1),
2204 (ld_frag addr:$src2)))],
2205 IIC_SSE_COMIS_RM, d>;
2208 let Defs = [EFLAGS] in {
2209 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2210 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2211 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2212 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2214 let Pattern = []<dag> in {
2215 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2216 "comiss", SSEPackedSingle>, TB, VEX,
2218 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2219 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2223 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2224 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2225 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2226 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2228 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2229 load, "comiss", SSEPackedSingle>, TB, VEX;
2230 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2231 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2232 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2233 "ucomiss", SSEPackedSingle>, TB;
2234 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2235 "ucomisd", SSEPackedDouble>, TB, OpSize;
2237 let Pattern = []<dag> in {
2238 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2239 "comiss", SSEPackedSingle>, TB;
2240 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2241 "comisd", SSEPackedDouble>, TB, OpSize;
2244 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2245 load, "ucomiss", SSEPackedSingle>, TB;
2246 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2247 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2249 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2250 "comiss", SSEPackedSingle>, TB;
2251 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2252 "comisd", SSEPackedDouble>, TB, OpSize;
2253 } // Defs = [EFLAGS]
2255 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2256 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2257 Operand CC, Intrinsic Int, string asm,
2258 string asm_alt, Domain d> {
2259 def rri : PIi8<0xC2, MRMSrcReg,
2260 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2261 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2262 IIC_SSE_CMPP_RR, d>;
2263 def rmi : PIi8<0xC2, MRMSrcMem,
2264 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2265 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2266 IIC_SSE_CMPP_RM, d>;
2268 // Accept explicit immediate argument form instead of comparison code.
2269 let neverHasSideEffects = 1 in {
2270 def rri_alt : PIi8<0xC2, MRMSrcReg,
2271 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2272 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2273 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2274 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2275 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2279 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2280 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2281 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2282 SSEPackedSingle>, TB, VEX_4V;
2283 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2284 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2285 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2286 SSEPackedDouble>, TB, OpSize, VEX_4V;
2287 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2288 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2289 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2290 SSEPackedSingle>, TB, VEX_4V;
2291 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2292 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2293 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2294 SSEPackedDouble>, TB, OpSize, VEX_4V;
2295 let Constraints = "$src1 = $dst" in {
2296 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2297 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2298 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2299 SSEPackedSingle>, TB;
2300 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2301 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2302 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2303 SSEPackedDouble>, TB, OpSize;
2306 let Predicates = [HasAVX] in {
2307 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2308 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2309 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2310 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2311 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2312 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2313 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2314 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2316 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2317 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2318 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2319 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2320 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2321 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2322 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2323 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2326 let Predicates = [UseSSE1] in {
2327 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2328 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2329 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2330 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2333 let Predicates = [UseSSE2] in {
2334 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2335 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2336 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2337 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2340 //===----------------------------------------------------------------------===//
2341 // SSE 1 & 2 - Shuffle Instructions
2342 //===----------------------------------------------------------------------===//
2344 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2345 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2346 ValueType vt, string asm, PatFrag mem_frag,
2347 Domain d, bit IsConvertibleToThreeAddress = 0> {
2348 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2349 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2350 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2351 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2352 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2353 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2354 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2355 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2356 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2359 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2360 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2361 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2362 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2363 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2364 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2365 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2366 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2367 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2368 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2369 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2370 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2372 let Constraints = "$src1 = $dst" in {
2373 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2374 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2375 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2377 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2378 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2379 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2383 let Predicates = [HasAVX] in {
2384 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2385 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2386 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2387 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2388 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2390 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2391 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2392 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2393 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2394 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2397 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2398 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2399 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2400 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2401 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2403 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2404 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2405 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2406 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2407 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2410 let Predicates = [UseSSE1] in {
2411 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2412 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2413 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2414 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2415 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2418 let Predicates = [UseSSE2] in {
2419 // Generic SHUFPD patterns
2420 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2421 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2422 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2423 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2424 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2427 //===----------------------------------------------------------------------===//
2428 // SSE 1 & 2 - Unpack Instructions
2429 //===----------------------------------------------------------------------===//
2431 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2432 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2433 PatFrag mem_frag, RegisterClass RC,
2434 X86MemOperand x86memop, string asm,
2436 def rr : PI<opc, MRMSrcReg,
2437 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2439 (vt (OpNode RC:$src1, RC:$src2)))],
2441 def rm : PI<opc, MRMSrcMem,
2442 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2444 (vt (OpNode RC:$src1,
2445 (mem_frag addr:$src2))))],
2449 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2450 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2451 SSEPackedSingle>, TB, VEX_4V;
2452 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2453 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2454 SSEPackedDouble>, TB, OpSize, VEX_4V;
2455 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2456 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2457 SSEPackedSingle>, TB, VEX_4V;
2458 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2459 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 SSEPackedDouble>, TB, OpSize, VEX_4V;
2462 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2463 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 SSEPackedSingle>, TB, VEX_4V;
2465 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2466 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2467 SSEPackedDouble>, TB, OpSize, VEX_4V;
2468 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2469 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2470 SSEPackedSingle>, TB, VEX_4V;
2471 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2472 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2473 SSEPackedDouble>, TB, OpSize, VEX_4V;
2475 let Constraints = "$src1 = $dst" in {
2476 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2477 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2478 SSEPackedSingle>, TB;
2479 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2480 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2481 SSEPackedDouble>, TB, OpSize;
2482 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2483 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2484 SSEPackedSingle>, TB;
2485 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2486 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2487 SSEPackedDouble>, TB, OpSize;
2488 } // Constraints = "$src1 = $dst"
2490 let Predicates = [HasAVX1Only] in {
2491 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2492 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2493 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2494 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2495 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2496 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2497 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2498 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2500 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2501 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2502 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2503 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2504 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2505 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2506 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2507 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2510 let Predicates = [HasAVX] in {
2511 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2512 // problem is during lowering, where it's not possible to recognize the load
2513 // fold cause it has two uses through a bitcast. One use disappears at isel
2514 // time and the fold opportunity reappears.
2515 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2516 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2519 let Predicates = [UseSSE2] in {
2520 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2521 // problem is during lowering, where it's not possible to recognize the load
2522 // fold cause it has two uses through a bitcast. One use disappears at isel
2523 // time and the fold opportunity reappears.
2524 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2525 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2528 //===----------------------------------------------------------------------===//
2529 // SSE 1 & 2 - Extract Floating-Point Sign mask
2530 //===----------------------------------------------------------------------===//
2532 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2533 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2535 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2536 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2537 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2538 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2540 IIC_SSE_MOVMSK, d>, REX_W;
2543 let Predicates = [HasAVX] in {
2544 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2545 "movmskps", SSEPackedSingle>, TB, VEX;
2546 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2547 "movmskpd", SSEPackedDouble>, TB,
2549 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2550 "movmskps", SSEPackedSingle>, TB, VEX;
2551 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2552 "movmskpd", SSEPackedDouble>, TB,
2555 def : Pat<(i32 (X86fgetsign FR32:$src)),
2556 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2557 def : Pat<(i64 (X86fgetsign FR32:$src)),
2558 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2559 def : Pat<(i32 (X86fgetsign FR64:$src)),
2560 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2561 def : Pat<(i64 (X86fgetsign FR64:$src)),
2562 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2565 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2566 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2567 SSEPackedSingle>, TB, VEX;
2568 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2569 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2570 SSEPackedDouble>, TB,
2572 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2573 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2574 SSEPackedSingle>, TB, VEX;
2575 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2576 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2577 SSEPackedDouble>, TB,
2581 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2582 SSEPackedSingle>, TB;
2583 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2584 SSEPackedDouble>, TB, OpSize;
2586 def : Pat<(i32 (X86fgetsign FR32:$src)),
2587 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2588 Requires<[UseSSE1]>;
2589 def : Pat<(i64 (X86fgetsign FR32:$src)),
2590 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2591 Requires<[UseSSE1]>;
2592 def : Pat<(i32 (X86fgetsign FR64:$src)),
2593 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2594 Requires<[UseSSE2]>;
2595 def : Pat<(i64 (X86fgetsign FR64:$src)),
2596 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2597 Requires<[UseSSE2]>;
2599 //===---------------------------------------------------------------------===//
2600 // SSE2 - Packed Integer Logical Instructions
2601 //===---------------------------------------------------------------------===//
2603 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2605 /// PDI_binop_rm - Simple SSE2 binary operator.
2606 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2607 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2608 X86MemOperand x86memop,
2610 bit IsCommutable = 0,
2612 let isCommutable = IsCommutable in
2613 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2614 (ins RC:$src1, RC:$src2),
2616 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2617 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2618 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2619 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2620 (ins RC:$src1, x86memop:$src2),
2622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2624 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2625 (bitconvert (memop_frag addr:$src2)))))],
2628 } // ExeDomain = SSEPackedInt
2630 // These are ordered here for pattern ordering requirements with the fp versions
2632 let Predicates = [HasAVX] in {
2633 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2634 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2635 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2636 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2637 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2638 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2639 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2640 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2643 let Constraints = "$src1 = $dst" in {
2644 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2645 i128mem, SSE_BIT_ITINS_P, 1>;
2646 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2647 i128mem, SSE_BIT_ITINS_P, 1>;
2648 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2649 i128mem, SSE_BIT_ITINS_P, 1>;
2650 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2651 i128mem, SSE_BIT_ITINS_P, 0>;
2652 } // Constraints = "$src1 = $dst"
2654 let Predicates = [HasAVX2] in {
2655 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2656 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2657 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2658 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2659 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2660 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2661 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2662 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2665 //===----------------------------------------------------------------------===//
2666 // SSE 1 & 2 - Logical Instructions
2667 //===----------------------------------------------------------------------===//
2669 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2671 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2672 SDNode OpNode, OpndItins itins> {
2673 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2674 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2677 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2678 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2681 let Constraints = "$src1 = $dst" in {
2682 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2683 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2686 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2687 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2692 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2693 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2695 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2697 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2700 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2701 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2704 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2706 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2708 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2709 // are all promoted to v2i64, and the patterns are covered by the int
2710 // version. This is needed in SSE only, because v2i64 isn't supported on
2711 // SSE1, but only on SSE2.
2712 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2713 !strconcat(OpcodeStr, "ps"), f128mem, [],
2714 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2715 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2717 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2718 !strconcat(OpcodeStr, "pd"), f128mem,
2719 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2720 (bc_v2i64 (v2f64 VR128:$src2))))],
2721 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2722 (memopv2i64 addr:$src2)))], 0>,
2724 let Constraints = "$src1 = $dst" in {
2725 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2726 !strconcat(OpcodeStr, "ps"), f128mem,
2727 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2728 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2729 (memopv2i64 addr:$src2)))]>, TB;
2731 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2732 !strconcat(OpcodeStr, "pd"), f128mem,
2733 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2734 (bc_v2i64 (v2f64 VR128:$src2))))],
2735 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2736 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2740 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2742 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2744 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2745 !strconcat(OpcodeStr, "ps"), f256mem,
2746 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2747 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2748 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2750 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2751 !strconcat(OpcodeStr, "pd"), f256mem,
2752 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2753 (bc_v4i64 (v4f64 VR256:$src2))))],
2754 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2755 (memopv4i64 addr:$src2)))], 0>,
2759 // AVX 256-bit packed logical ops forms
2760 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2761 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2762 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2763 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2765 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2766 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2767 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2768 let isCommutable = 0 in
2769 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2771 //===----------------------------------------------------------------------===//
2772 // SSE 1 & 2 - Arithmetic Instructions
2773 //===----------------------------------------------------------------------===//
2775 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2778 /// In addition, we also have a special variant of the scalar form here to
2779 /// represent the associated intrinsic operation. This form is unlike the
2780 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2781 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2783 /// These three forms can each be reg+reg or reg+mem.
2786 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2788 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2791 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2792 OpNode, FR32, f32mem,
2793 itins.s, Is2Addr>, XS;
2794 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2795 OpNode, FR64, f64mem,
2796 itins.d, Is2Addr>, XD;
2799 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2802 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2803 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2805 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2806 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2810 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2813 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2814 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2816 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2817 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2821 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2824 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2825 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2826 itins.s, Is2Addr>, XS;
2827 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2828 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2829 itins.d, Is2Addr>, XD;
2832 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2835 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2836 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2837 SSEPackedSingle, itins.s, Is2Addr>,
2840 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2841 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2842 SSEPackedDouble, itins.d, Is2Addr>,
2846 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2848 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2849 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2850 SSEPackedSingle, itins.s, 0>, TB;
2852 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2853 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2854 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2857 // Binary Arithmetic instructions
2858 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2859 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2861 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2862 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2864 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2865 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2867 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2868 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2871 let isCommutable = 0 in {
2872 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2873 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2875 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2876 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2878 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2879 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2881 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2882 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2884 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2885 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2887 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2888 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2889 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2890 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2892 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2893 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2895 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2896 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2897 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2898 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2902 let Constraints = "$src1 = $dst" in {
2903 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2904 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2905 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2906 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2907 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2908 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2910 let isCommutable = 0 in {
2911 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2912 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2913 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2914 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2915 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2916 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2917 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2918 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2919 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2920 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2921 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2922 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2923 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2924 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2928 let isCodeGenOnly = 1 in {
2929 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2931 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2932 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2933 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2935 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2936 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2937 let Constraints = "$src1 = $dst" in {
2938 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2939 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2940 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2941 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2946 /// In addition, we also have a special variant of the scalar form here to
2947 /// represent the associated intrinsic operation. This form is unlike the
2948 /// plain scalar form, in that it takes an entire vector (instead of a
2949 /// scalar) and leaves the top elements undefined.
2951 /// And, we have a special variant form for a full-vector intrinsic form.
2953 def SSE_SQRTP : OpndItins<
2954 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2957 def SSE_SQRTS : OpndItins<
2958 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2961 def SSE_RCPP : OpndItins<
2962 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2965 def SSE_RCPS : OpndItins<
2966 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2969 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2970 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2971 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2972 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2973 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2974 [(set FR32:$dst, (OpNode FR32:$src))]>;
2975 // For scalar unary operations, fold a load into the operation
2976 // only in OptForSize mode. It eliminates an instruction, but it also
2977 // eliminates a whole-register clobber (the load), so it introduces a
2978 // partial register update condition.
2979 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2980 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2981 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
2982 Requires<[UseSSE1, OptForSize]>;
2983 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2984 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2985 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
2986 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2987 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2988 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
2991 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2992 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2993 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2994 !strconcat(OpcodeStr,
2995 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2996 let mayLoad = 1 in {
2997 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2998 !strconcat(OpcodeStr,
2999 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3000 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3001 (ins VR128:$src1, ssmem:$src2),
3002 !strconcat(OpcodeStr,
3003 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3007 /// sse1_fp_unop_p - SSE1 unops in packed form.
3008 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3010 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3011 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3012 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3013 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3014 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3015 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3018 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3019 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3021 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3022 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3023 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3025 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3026 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3027 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3031 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3032 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3033 Intrinsic V4F32Int, OpndItins itins> {
3034 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3035 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3036 [(set VR128:$dst, (V4F32Int VR128:$src))],
3038 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3039 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3040 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3044 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3045 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3046 Intrinsic V4F32Int, OpndItins itins> {
3047 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3048 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3049 [(set VR256:$dst, (V4F32Int VR256:$src))],
3051 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3052 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3053 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3057 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3058 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3059 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3060 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3061 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3062 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3063 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3064 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3065 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3066 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3067 Requires<[UseSSE2, OptForSize]>;
3068 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3069 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3070 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3071 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3072 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3073 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3076 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3077 let hasSideEffects = 0 in
3078 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3079 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3080 !strconcat(OpcodeStr,
3081 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3082 let mayLoad = 1 in {
3083 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3084 !strconcat(OpcodeStr,
3085 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3086 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3087 (ins VR128:$src1, sdmem:$src2),
3088 !strconcat(OpcodeStr,
3089 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3093 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3094 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3095 SDNode OpNode, OpndItins itins> {
3096 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3097 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3098 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3099 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3100 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3101 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3104 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3105 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3107 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3108 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3109 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3111 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3112 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3113 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3117 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3118 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3119 Intrinsic V2F64Int, OpndItins itins> {
3120 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3122 [(set VR128:$dst, (V2F64Int VR128:$src))],
3124 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3125 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3126 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3130 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3131 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3132 Intrinsic V2F64Int, OpndItins itins> {
3133 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3134 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3135 [(set VR256:$dst, (V2F64Int VR256:$src))],
3137 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3138 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3139 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3143 let Predicates = [HasAVX] in {
3145 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3146 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3148 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3149 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3150 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3151 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3152 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3154 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3156 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3158 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3162 // Reciprocal approximations. Note that these typically require refinement
3163 // in order to obtain suitable precision.
3164 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3165 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3166 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3167 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3169 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3172 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3173 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3174 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3175 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3177 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3181 def : Pat<(f32 (fsqrt FR32:$src)),
3182 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3183 def : Pat<(f32 (fsqrt (load addr:$src))),
3184 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3185 Requires<[HasAVX, OptForSize]>;
3186 def : Pat<(f64 (fsqrt FR64:$src)),
3187 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3188 def : Pat<(f64 (fsqrt (load addr:$src))),
3189 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3190 Requires<[HasAVX, OptForSize]>;
3192 def : Pat<(f32 (X86frsqrt FR32:$src)),
3193 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3194 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3195 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3196 Requires<[HasAVX, OptForSize]>;
3198 def : Pat<(f32 (X86frcp FR32:$src)),
3199 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3200 def : Pat<(f32 (X86frcp (load addr:$src))),
3201 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3202 Requires<[HasAVX, OptForSize]>;
3204 let Predicates = [HasAVX] in {
3205 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3206 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3207 (COPY_TO_REGCLASS VR128:$src, FR32)),
3209 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3210 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3212 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3213 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3214 (COPY_TO_REGCLASS VR128:$src, FR64)),
3216 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3217 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3219 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3220 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3221 (COPY_TO_REGCLASS VR128:$src, FR32)),
3223 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3224 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3226 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3227 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3228 (COPY_TO_REGCLASS VR128:$src, FR32)),
3230 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3231 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3235 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3237 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3238 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3239 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3241 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3242 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3244 // Reciprocal approximations. Note that these typically require refinement
3245 // in order to obtain suitable precision.
3246 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3248 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3249 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3251 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3253 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3254 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3256 // There is no f64 version of the reciprocal approximation instructions.
3258 //===----------------------------------------------------------------------===//
3259 // SSE 1 & 2 - Non-temporal stores
3260 //===----------------------------------------------------------------------===//
3262 let AddedComplexity = 400 in { // Prefer non-temporal versions
3263 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3264 (ins f128mem:$dst, VR128:$src),
3265 "movntps\t{$src, $dst|$dst, $src}",
3266 [(alignednontemporalstore (v4f32 VR128:$src),
3268 IIC_SSE_MOVNT>, VEX;
3269 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3270 (ins f128mem:$dst, VR128:$src),
3271 "movntpd\t{$src, $dst|$dst, $src}",
3272 [(alignednontemporalstore (v2f64 VR128:$src),
3274 IIC_SSE_MOVNT>, VEX;
3276 let ExeDomain = SSEPackedInt in
3277 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3278 (ins f128mem:$dst, VR128:$src),
3279 "movntdq\t{$src, $dst|$dst, $src}",
3280 [(alignednontemporalstore (v2i64 VR128:$src),
3282 IIC_SSE_MOVNT>, VEX;
3284 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3285 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3287 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3288 (ins f256mem:$dst, VR256:$src),
3289 "movntps\t{$src, $dst|$dst, $src}",
3290 [(alignednontemporalstore (v8f32 VR256:$src),
3292 IIC_SSE_MOVNT>, VEX;
3293 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3294 (ins f256mem:$dst, VR256:$src),
3295 "movntpd\t{$src, $dst|$dst, $src}",
3296 [(alignednontemporalstore (v4f64 VR256:$src),
3298 IIC_SSE_MOVNT>, VEX;
3299 let ExeDomain = SSEPackedInt in
3300 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3301 (ins f256mem:$dst, VR256:$src),
3302 "movntdq\t{$src, $dst|$dst, $src}",
3303 [(alignednontemporalstore (v4i64 VR256:$src),
3305 IIC_SSE_MOVNT>, VEX;
3308 let AddedComplexity = 400 in { // Prefer non-temporal versions
3309 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3310 "movntps\t{$src, $dst|$dst, $src}",
3311 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3313 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3314 "movntpd\t{$src, $dst|$dst, $src}",
3315 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3318 let ExeDomain = SSEPackedInt in
3319 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3320 "movntdq\t{$src, $dst|$dst, $src}",
3321 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3324 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3325 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3327 // There is no AVX form for instructions below this point
3328 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3329 "movnti{l}\t{$src, $dst|$dst, $src}",
3330 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3332 TB, Requires<[HasSSE2]>;
3333 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3334 "movnti{q}\t{$src, $dst|$dst, $src}",
3335 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3337 TB, Requires<[HasSSE2]>;
3340 //===----------------------------------------------------------------------===//
3341 // SSE 1 & 2 - Prefetch and memory fence
3342 //===----------------------------------------------------------------------===//
3344 // Prefetch intrinsic.
3345 let Predicates = [HasSSE1] in {
3346 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3347 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3348 IIC_SSE_PREFETCH>, TB;
3349 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3350 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3351 IIC_SSE_PREFETCH>, TB;
3352 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3353 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3354 IIC_SSE_PREFETCH>, TB;
3355 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3356 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3357 IIC_SSE_PREFETCH>, TB;
3361 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3362 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3363 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3365 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3366 // was introduced with SSE2, it's backward compatible.
3367 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3369 // Load, store, and memory fence
3370 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3371 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3372 TB, Requires<[HasSSE1]>;
3373 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3374 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3375 TB, Requires<[HasSSE2]>;
3376 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3377 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3378 TB, Requires<[HasSSE2]>;
3380 def : Pat<(X86SFence), (SFENCE)>;
3381 def : Pat<(X86LFence), (LFENCE)>;
3382 def : Pat<(X86MFence), (MFENCE)>;
3384 //===----------------------------------------------------------------------===//
3385 // SSE 1 & 2 - Load/Store XCSR register
3386 //===----------------------------------------------------------------------===//
3388 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3389 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3390 IIC_SSE_LDMXCSR>, VEX;
3391 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3392 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3393 IIC_SSE_STMXCSR>, VEX;
3395 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3396 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3398 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3399 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3402 //===---------------------------------------------------------------------===//
3403 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3404 //===---------------------------------------------------------------------===//
3406 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3408 let neverHasSideEffects = 1 in {
3409 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3410 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3412 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3413 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3416 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3417 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3419 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3420 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3424 let isCodeGenOnly = 1 in {
3425 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3426 "movdqa\t{$src, $dst|$dst, $src}", [],
3429 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3430 "movdqa\t{$src, $dst|$dst, $src}", [],
3433 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3434 "movdqu\t{$src, $dst|$dst, $src}", [],
3437 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3438 "movdqu\t{$src, $dst|$dst, $src}", [],
3443 let canFoldAsLoad = 1, mayLoad = 1 in {
3444 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3445 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3447 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3448 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3450 let Predicates = [HasAVX] in {
3451 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3452 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3454 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3455 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3460 let mayStore = 1 in {
3461 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3462 (ins i128mem:$dst, VR128:$src),
3463 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3465 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3466 (ins i256mem:$dst, VR256:$src),
3467 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3469 let Predicates = [HasAVX] in {
3470 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3471 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3473 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3474 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3479 let neverHasSideEffects = 1 in
3480 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3481 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3483 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3484 "movdqu\t{$src, $dst|$dst, $src}",
3485 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3488 let isCodeGenOnly = 1 in {
3489 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3490 "movdqa\t{$src, $dst|$dst, $src}", [],
3493 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3494 "movdqu\t{$src, $dst|$dst, $src}",
3495 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3498 let canFoldAsLoad = 1, mayLoad = 1 in {
3499 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3500 "movdqa\t{$src, $dst|$dst, $src}",
3501 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3503 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3504 "movdqu\t{$src, $dst|$dst, $src}",
3505 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3507 XS, Requires<[UseSSE2]>;
3510 let mayStore = 1 in {
3511 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3512 "movdqa\t{$src, $dst|$dst, $src}",
3513 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3515 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3516 "movdqu\t{$src, $dst|$dst, $src}",
3517 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3519 XS, Requires<[UseSSE2]>;
3522 // Intrinsic forms of MOVDQU load and store
3523 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3524 "vmovdqu\t{$src, $dst|$dst, $src}",
3525 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3527 XS, VEX, Requires<[HasAVX]>;
3529 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3530 "movdqu\t{$src, $dst|$dst, $src}",
3531 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3533 XS, Requires<[UseSSE2]>;
3535 } // ExeDomain = SSEPackedInt
3537 let Predicates = [HasAVX] in {
3538 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3539 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3542 //===---------------------------------------------------------------------===//
3543 // SSE2 - Packed Integer Arithmetic Instructions
3544 //===---------------------------------------------------------------------===//
3546 def SSE_PMADD : OpndItins<
3547 IIC_SSE_PMADD, IIC_SSE_PMADD
3550 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3552 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3553 RegisterClass RC, PatFrag memop_frag,
3554 X86MemOperand x86memop,
3556 bit IsCommutable = 0,
3558 let isCommutable = IsCommutable in
3559 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3560 (ins RC:$src1, RC:$src2),
3562 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3564 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3565 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3566 (ins RC:$src1, x86memop:$src2),
3568 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3569 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3570 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3574 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3575 string OpcodeStr, SDNode OpNode,
3576 SDNode OpNode2, RegisterClass RC,
3577 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3578 ShiftOpndItins itins,
3580 // src2 is always 128-bit
3581 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3582 (ins RC:$src1, VR128:$src2),
3584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3585 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3586 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3588 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3589 (ins RC:$src1, i128mem:$src2),
3591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3593 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3594 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3595 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3596 (ins RC:$src1, i32i8imm:$src2),
3598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3600 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3603 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3604 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3605 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3606 PatFrag memop_frag, X86MemOperand x86memop,
3608 bit IsCommutable = 0, bit Is2Addr = 1> {
3609 let isCommutable = IsCommutable in
3610 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3611 (ins RC:$src1, RC:$src2),
3613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3615 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3616 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3617 (ins RC:$src1, x86memop:$src2),
3619 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3620 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3621 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3622 (bitconvert (memop_frag addr:$src2)))))]>;
3624 } // ExeDomain = SSEPackedInt
3626 // 128-bit Integer Arithmetic
3628 let Predicates = [HasAVX] in {
3629 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3630 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3632 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3633 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3634 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3635 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3636 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3637 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3638 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3639 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3640 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3641 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3642 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3643 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3644 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3645 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3646 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3647 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3648 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3649 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3653 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3654 VR128, memopv2i64, i128mem,
3655 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3656 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3657 VR128, memopv2i64, i128mem,
3658 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3659 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3660 VR128, memopv2i64, i128mem,
3661 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3662 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3663 VR128, memopv2i64, i128mem,
3664 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3665 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3666 VR128, memopv2i64, i128mem,
3667 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3668 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3669 VR128, memopv2i64, i128mem,
3670 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3671 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3672 VR128, memopv2i64, i128mem,
3673 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3674 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3675 VR128, memopv2i64, i128mem,
3676 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3677 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3678 VR128, memopv2i64, i128mem,
3679 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3680 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3681 VR128, memopv2i64, i128mem,
3682 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3683 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3684 VR128, memopv2i64, i128mem,
3685 SSE_PMADD, 1, 0>, VEX_4V;
3686 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3687 VR128, memopv2i64, i128mem,
3688 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3689 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3690 VR128, memopv2i64, i128mem,
3691 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3692 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3693 VR128, memopv2i64, i128mem,
3694 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3695 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3696 VR128, memopv2i64, i128mem,
3697 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3698 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3699 VR128, memopv2i64, i128mem,
3700 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3701 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3702 VR128, memopv2i64, i128mem,
3703 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3704 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3705 VR128, memopv2i64, i128mem,
3706 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3709 let Predicates = [HasAVX2] in {
3710 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3711 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3712 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3713 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3714 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3715 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3716 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3717 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3718 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3719 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3720 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3721 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3722 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3723 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3724 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3725 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3726 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3727 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3728 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3729 VR256, memopv4i64, i256mem,
3730 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3733 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3734 VR256, memopv4i64, i256mem,
3735 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3736 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3737 VR256, memopv4i64, i256mem,
3738 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3739 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3740 VR256, memopv4i64, i256mem,
3741 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3742 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3743 VR256, memopv4i64, i256mem,
3744 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3745 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3746 VR256, memopv4i64, i256mem,
3747 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3748 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3749 VR256, memopv4i64, i256mem,
3750 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3751 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3752 VR256, memopv4i64, i256mem,
3753 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3754 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3755 VR256, memopv4i64, i256mem,
3756 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3757 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3758 VR256, memopv4i64, i256mem,
3759 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3760 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3761 VR256, memopv4i64, i256mem,
3762 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3763 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3764 VR256, memopv4i64, i256mem,
3765 SSE_PMADD, 1, 0>, VEX_4V;
3766 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3767 VR256, memopv4i64, i256mem,
3768 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3769 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3770 VR256, memopv4i64, i256mem,
3771 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3772 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3773 VR256, memopv4i64, i256mem,
3774 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3775 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3776 VR256, memopv4i64, i256mem,
3777 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3778 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3779 VR256, memopv4i64, i256mem,
3780 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3781 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3782 VR256, memopv4i64, i256mem,
3783 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3784 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3785 VR256, memopv4i64, i256mem,
3786 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3789 let Constraints = "$src1 = $dst" in {
3790 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3791 i128mem, SSE_INTALU_ITINS_P, 1>;
3792 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3793 i128mem, SSE_INTALU_ITINS_P, 1>;
3794 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3795 i128mem, SSE_INTALU_ITINS_P, 1>;
3796 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3797 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3798 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3799 i128mem, SSE_INTMUL_ITINS_P, 1>;
3800 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3801 i128mem, SSE_INTALU_ITINS_P>;
3802 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3803 i128mem, SSE_INTALU_ITINS_P>;
3804 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3805 i128mem, SSE_INTALU_ITINS_P>;
3806 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3807 i128mem, SSE_INTALUQ_ITINS_P>;
3808 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3809 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3812 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3813 VR128, memopv2i64, i128mem,
3814 SSE_INTALU_ITINS_P>;
3815 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3816 VR128, memopv2i64, i128mem,
3817 SSE_INTALU_ITINS_P>;
3818 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3819 VR128, memopv2i64, i128mem,
3820 SSE_INTALU_ITINS_P>;
3821 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3822 VR128, memopv2i64, i128mem,
3823 SSE_INTALU_ITINS_P>;
3824 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3825 VR128, memopv2i64, i128mem,
3826 SSE_INTALU_ITINS_P, 1>;
3827 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3828 VR128, memopv2i64, i128mem,
3829 SSE_INTALU_ITINS_P, 1>;
3830 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3831 VR128, memopv2i64, i128mem,
3832 SSE_INTALU_ITINS_P, 1>;
3833 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3834 VR128, memopv2i64, i128mem,
3835 SSE_INTALU_ITINS_P, 1>;
3836 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3837 VR128, memopv2i64, i128mem,
3838 SSE_INTMUL_ITINS_P, 1>;
3839 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3840 VR128, memopv2i64, i128mem,
3841 SSE_INTMUL_ITINS_P, 1>;
3842 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3843 VR128, memopv2i64, i128mem,
3845 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3846 VR128, memopv2i64, i128mem,
3847 SSE_INTALU_ITINS_P, 1>;
3848 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3849 VR128, memopv2i64, i128mem,
3850 SSE_INTALU_ITINS_P, 1>;
3851 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3852 VR128, memopv2i64, i128mem,
3853 SSE_INTALU_ITINS_P, 1>;
3854 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3855 VR128, memopv2i64, i128mem,
3856 SSE_INTALU_ITINS_P, 1>;
3857 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3858 VR128, memopv2i64, i128mem,
3859 SSE_INTALU_ITINS_P, 1>;
3860 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3861 VR128, memopv2i64, i128mem,
3862 SSE_INTALU_ITINS_P, 1>;
3863 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3864 VR128, memopv2i64, i128mem,
3865 SSE_INTALU_ITINS_P, 1>;
3867 } // Constraints = "$src1 = $dst"
3869 //===---------------------------------------------------------------------===//
3870 // SSE2 - Packed Integer Logical Instructions
3871 //===---------------------------------------------------------------------===//
3873 let Predicates = [HasAVX] in {
3874 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3875 VR128, v8i16, v8i16, bc_v8i16,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3877 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3878 VR128, v4i32, v4i32, bc_v4i32,
3879 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3880 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3881 VR128, v2i64, v2i64, bc_v2i64,
3882 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3885 VR128, v8i16, v8i16, bc_v8i16,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3888 VR128, v4i32, v4i32, bc_v4i32,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3890 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3891 VR128, v2i64, v2i64, bc_v2i64,
3892 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3894 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3895 VR128, v8i16, v8i16, bc_v8i16,
3896 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3897 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3898 VR128, v4i32, v4i32, bc_v4i32,
3899 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3901 let ExeDomain = SSEPackedInt in {
3902 // 128-bit logical shifts.
3903 def VPSLLDQri : PDIi8<0x73, MRM7r,
3904 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3905 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3907 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3909 def VPSRLDQri : PDIi8<0x73, MRM3r,
3910 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3911 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3913 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3915 // PSRADQri doesn't exist in SSE[1-3].
3917 } // Predicates = [HasAVX]
3919 let Predicates = [HasAVX2] in {
3920 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3921 VR256, v16i16, v8i16, bc_v8i16,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3923 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3924 VR256, v8i32, v4i32, bc_v4i32,
3925 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3926 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3927 VR256, v4i64, v2i64, bc_v2i64,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3930 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3931 VR256, v16i16, v8i16, bc_v8i16,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3933 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3934 VR256, v8i32, v4i32, bc_v4i32,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3936 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3937 VR256, v4i64, v2i64, bc_v2i64,
3938 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3940 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3941 VR256, v16i16, v8i16, bc_v8i16,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3943 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3944 VR256, v8i32, v4i32, bc_v4i32,
3945 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3947 let ExeDomain = SSEPackedInt in {
3948 // 256-bit logical shifts.
3949 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3950 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3951 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3955 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3956 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3957 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3959 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3961 // PSRADQYri doesn't exist in SSE[1-3].
3963 } // Predicates = [HasAVX2]
3965 let Constraints = "$src1 = $dst" in {
3966 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3967 VR128, v8i16, v8i16, bc_v8i16,
3968 SSE_INTSHIFT_ITINS_P>;
3969 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3970 VR128, v4i32, v4i32, bc_v4i32,
3971 SSE_INTSHIFT_ITINS_P>;
3972 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3973 VR128, v2i64, v2i64, bc_v2i64,
3974 SSE_INTSHIFT_ITINS_P>;
3976 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3977 VR128, v8i16, v8i16, bc_v8i16,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3980 VR128, v4i32, v4i32, bc_v4i32,
3981 SSE_INTSHIFT_ITINS_P>;
3982 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3983 VR128, v2i64, v2i64, bc_v2i64,
3984 SSE_INTSHIFT_ITINS_P>;
3986 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3987 VR128, v8i16, v8i16, bc_v8i16,
3988 SSE_INTSHIFT_ITINS_P>;
3989 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3990 VR128, v4i32, v4i32, bc_v4i32,
3991 SSE_INTSHIFT_ITINS_P>;
3993 let ExeDomain = SSEPackedInt in {
3994 // 128-bit logical shifts.
3995 def PSLLDQri : PDIi8<0x73, MRM7r,
3996 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3997 "pslldq\t{$src2, $dst|$dst, $src2}",
3999 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4000 def PSRLDQri : PDIi8<0x73, MRM3r,
4001 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4002 "psrldq\t{$src2, $dst|$dst, $src2}",
4004 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4005 // PSRADQri doesn't exist in SSE[1-3].
4007 } // Constraints = "$src1 = $dst"
4009 let Predicates = [HasAVX] in {
4010 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4011 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4012 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4013 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4014 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4015 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4017 // Shift up / down and insert zero's.
4018 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4019 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4020 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4021 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4024 let Predicates = [HasAVX2] in {
4025 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4026 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4027 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4028 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4031 let Predicates = [UseSSE2] in {
4032 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4033 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4034 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4035 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4036 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4037 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4039 // Shift up / down and insert zero's.
4040 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4041 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4042 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4043 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4046 //===---------------------------------------------------------------------===//
4047 // SSE2 - Packed Integer Comparison Instructions
4048 //===---------------------------------------------------------------------===//
4050 let Predicates = [HasAVX] in {
4051 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4052 VR128, memopv2i64, i128mem,
4053 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4054 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4055 VR128, memopv2i64, i128mem,
4056 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4057 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4058 VR128, memopv2i64, i128mem,
4059 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4060 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4061 VR128, memopv2i64, i128mem,
4062 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4063 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4064 VR128, memopv2i64, i128mem,
4065 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4066 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4067 VR128, memopv2i64, i128mem,
4068 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4071 let Predicates = [HasAVX2] in {
4072 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4073 VR256, memopv4i64, i256mem,
4074 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4075 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4076 VR256, memopv4i64, i256mem,
4077 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4078 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4079 VR256, memopv4i64, i256mem,
4080 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4081 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4082 VR256, memopv4i64, i256mem,
4083 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4084 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4085 VR256, memopv4i64, i256mem,
4086 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4087 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4088 VR256, memopv4i64, i256mem,
4089 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4092 let Constraints = "$src1 = $dst" in {
4093 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4094 VR128, memopv2i64, i128mem,
4095 SSE_INTALU_ITINS_P, 1>;
4096 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4097 VR128, memopv2i64, i128mem,
4098 SSE_INTALU_ITINS_P, 1>;
4099 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4100 VR128, memopv2i64, i128mem,
4101 SSE_INTALU_ITINS_P, 1>;
4102 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4103 VR128, memopv2i64, i128mem,
4104 SSE_INTALU_ITINS_P>;
4105 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4106 VR128, memopv2i64, i128mem,
4107 SSE_INTALU_ITINS_P>;
4108 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4109 VR128, memopv2i64, i128mem,
4110 SSE_INTALU_ITINS_P>;
4111 } // Constraints = "$src1 = $dst"
4113 //===---------------------------------------------------------------------===//
4114 // SSE2 - Packed Integer Pack Instructions
4115 //===---------------------------------------------------------------------===//
4117 let Predicates = [HasAVX] in {
4118 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4119 VR128, memopv2i64, i128mem,
4120 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4121 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4122 VR128, memopv2i64, i128mem,
4123 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4124 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4125 VR128, memopv2i64, i128mem,
4126 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4129 let Predicates = [HasAVX2] in {
4130 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4131 VR256, memopv4i64, i256mem,
4132 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4133 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4134 VR256, memopv4i64, i256mem,
4135 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4136 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4137 VR256, memopv4i64, i256mem,
4138 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4141 let Constraints = "$src1 = $dst" in {
4142 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4143 VR128, memopv2i64, i128mem,
4144 SSE_INTALU_ITINS_P>;
4145 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4146 VR128, memopv2i64, i128mem,
4147 SSE_INTALU_ITINS_P>;
4148 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4149 VR128, memopv2i64, i128mem,
4150 SSE_INTALU_ITINS_P>;
4151 } // Constraints = "$src1 = $dst"
4153 //===---------------------------------------------------------------------===//
4154 // SSE2 - Packed Integer Shuffle Instructions
4155 //===---------------------------------------------------------------------===//
4157 let ExeDomain = SSEPackedInt in {
4158 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4159 def ri : Ii8<0x70, MRMSrcReg,
4160 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4161 !strconcat(OpcodeStr,
4162 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4163 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4165 def mi : Ii8<0x70, MRMSrcMem,
4166 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4167 !strconcat(OpcodeStr,
4168 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4170 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4175 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4176 def Yri : Ii8<0x70, MRMSrcReg,
4177 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4178 !strconcat(OpcodeStr,
4179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4180 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4181 def Ymi : Ii8<0x70, MRMSrcMem,
4182 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4183 !strconcat(OpcodeStr,
4184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4186 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4187 (i8 imm:$src2))))]>;
4189 } // ExeDomain = SSEPackedInt
4191 let Predicates = [HasAVX] in {
4192 let AddedComplexity = 5 in
4193 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4195 // SSE2 with ImmT == Imm8 and XS prefix.
4196 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4198 // SSE2 with ImmT == Imm8 and XD prefix.
4199 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4201 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4202 (VPSHUFDmi addr:$src1, imm:$imm)>;
4203 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4204 (VPSHUFDri VR128:$src1, imm:$imm)>;
4207 let Predicates = [HasAVX2] in {
4208 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4209 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4210 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4213 let Predicates = [UseSSE2] in {
4214 let AddedComplexity = 5 in
4215 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4217 // SSE2 with ImmT == Imm8 and XS prefix.
4218 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4220 // SSE2 with ImmT == Imm8 and XD prefix.
4221 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4223 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4224 (PSHUFDmi addr:$src1, imm:$imm)>;
4225 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4226 (PSHUFDri VR128:$src1, imm:$imm)>;
4229 //===---------------------------------------------------------------------===//
4230 // SSE2 - Packed Integer Unpack Instructions
4231 //===---------------------------------------------------------------------===//
4233 let ExeDomain = SSEPackedInt in {
4234 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4235 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4236 def rr : PDI<opc, MRMSrcReg,
4237 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4239 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4240 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4241 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4243 def rm : PDI<opc, MRMSrcMem,
4244 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4246 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4247 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4248 [(set VR128:$dst, (OpNode VR128:$src1,
4249 (bc_frag (memopv2i64
4254 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4255 SDNode OpNode, PatFrag bc_frag> {
4256 def Yrr : PDI<opc, MRMSrcReg,
4257 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4258 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4259 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4260 def Yrm : PDI<opc, MRMSrcMem,
4261 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4262 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4263 [(set VR256:$dst, (OpNode VR256:$src1,
4264 (bc_frag (memopv4i64 addr:$src2))))]>;
4267 let Predicates = [HasAVX] in {
4268 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4269 bc_v16i8, 0>, VEX_4V;
4270 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4271 bc_v8i16, 0>, VEX_4V;
4272 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4273 bc_v4i32, 0>, VEX_4V;
4274 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4275 bc_v2i64, 0>, VEX_4V;
4277 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4278 bc_v16i8, 0>, VEX_4V;
4279 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4280 bc_v8i16, 0>, VEX_4V;
4281 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4282 bc_v4i32, 0>, VEX_4V;
4283 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4284 bc_v2i64, 0>, VEX_4V;
4287 let Predicates = [HasAVX2] in {
4288 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4290 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4292 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4294 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4297 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4299 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4301 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4303 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4307 let Constraints = "$src1 = $dst" in {
4308 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4310 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4312 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4314 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4317 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4319 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4321 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4323 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4326 } // ExeDomain = SSEPackedInt
4328 //===---------------------------------------------------------------------===//
4329 // SSE2 - Packed Integer Extract and Insert
4330 //===---------------------------------------------------------------------===//
4332 let ExeDomain = SSEPackedInt in {
4333 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4334 def rri : Ii8<0xC4, MRMSrcReg,
4335 (outs VR128:$dst), (ins VR128:$src1,
4336 GR32:$src2, i32i8imm:$src3),
4338 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4339 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4341 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4342 def rmi : Ii8<0xC4, MRMSrcMem,
4343 (outs VR128:$dst), (ins VR128:$src1,
4344 i16mem:$src2, i32i8imm:$src3),
4346 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4347 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4349 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4350 imm:$src3))], IIC_SSE_PINSRW>;
4354 let Predicates = [HasAVX] in
4355 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4356 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4357 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4358 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4359 imm:$src2))]>, TB, OpSize, VEX;
4360 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4361 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4362 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4363 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4364 imm:$src2))], IIC_SSE_PEXTRW>;
4367 let Predicates = [HasAVX] in {
4368 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4369 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4370 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4371 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4372 []>, TB, OpSize, VEX_4V;
4375 let Constraints = "$src1 = $dst" in
4376 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4378 } // ExeDomain = SSEPackedInt
4380 //===---------------------------------------------------------------------===//
4381 // SSE2 - Packed Mask Creation
4382 //===---------------------------------------------------------------------===//
4384 let ExeDomain = SSEPackedInt in {
4386 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4387 "pmovmskb\t{$src, $dst|$dst, $src}",
4388 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4389 IIC_SSE_MOVMSK>, VEX;
4390 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4391 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4393 let Predicates = [HasAVX2] in {
4394 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4395 "pmovmskb\t{$src, $dst|$dst, $src}",
4396 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4397 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4398 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4401 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4402 "pmovmskb\t{$src, $dst|$dst, $src}",
4403 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4406 } // ExeDomain = SSEPackedInt
4408 //===---------------------------------------------------------------------===//
4409 // SSE2 - Conditional Store
4410 //===---------------------------------------------------------------------===//
4412 let ExeDomain = SSEPackedInt in {
4415 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4416 (ins VR128:$src, VR128:$mask),
4417 "maskmovdqu\t{$mask, $src|$src, $mask}",
4418 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4419 IIC_SSE_MASKMOV>, VEX;
4421 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4422 (ins VR128:$src, VR128:$mask),
4423 "maskmovdqu\t{$mask, $src|$src, $mask}",
4424 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4425 IIC_SSE_MASKMOV>, VEX;
4428 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4429 "maskmovdqu\t{$mask, $src|$src, $mask}",
4430 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4433 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4434 "maskmovdqu\t{$mask, $src|$src, $mask}",
4435 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4438 } // ExeDomain = SSEPackedInt
4440 //===---------------------------------------------------------------------===//
4441 // SSE2 - Move Doubleword
4442 //===---------------------------------------------------------------------===//
4444 //===---------------------------------------------------------------------===//
4445 // Move Int Doubleword to Packed Double Int
4447 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4448 "movd\t{$src, $dst|$dst, $src}",
4450 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4452 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4453 "movd\t{$src, $dst|$dst, $src}",
4455 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4458 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4459 "mov{d|q}\t{$src, $dst|$dst, $src}",
4461 (v2i64 (scalar_to_vector GR64:$src)))],
4462 IIC_SSE_MOVDQ>, VEX;
4463 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4464 "mov{d|q}\t{$src, $dst|$dst, $src}",
4465 [(set FR64:$dst, (bitconvert GR64:$src))],
4466 IIC_SSE_MOVDQ>, VEX;
4468 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4469 "movd\t{$src, $dst|$dst, $src}",
4471 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4472 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4473 "movd\t{$src, $dst|$dst, $src}",
4475 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4477 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4478 "mov{d|q}\t{$src, $dst|$dst, $src}",
4480 (v2i64 (scalar_to_vector GR64:$src)))],
4482 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4483 "mov{d|q}\t{$src, $dst|$dst, $src}",
4484 [(set FR64:$dst, (bitconvert GR64:$src))],
4487 //===---------------------------------------------------------------------===//
4488 // Move Int Doubleword to Single Scalar
4490 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4491 "movd\t{$src, $dst|$dst, $src}",
4492 [(set FR32:$dst, (bitconvert GR32:$src))],
4493 IIC_SSE_MOVDQ>, VEX;
4495 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4496 "movd\t{$src, $dst|$dst, $src}",
4497 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4500 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4501 "movd\t{$src, $dst|$dst, $src}",
4502 [(set FR32:$dst, (bitconvert GR32:$src))],
4505 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4506 "movd\t{$src, $dst|$dst, $src}",
4507 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4510 //===---------------------------------------------------------------------===//
4511 // Move Packed Doubleword Int to Packed Double Int
4513 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4514 "movd\t{$src, $dst|$dst, $src}",
4515 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4516 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4517 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4518 (ins i32mem:$dst, VR128:$src),
4519 "movd\t{$src, $dst|$dst, $src}",
4520 [(store (i32 (vector_extract (v4i32 VR128:$src),
4521 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4523 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4524 "movd\t{$src, $dst|$dst, $src}",
4525 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4526 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4527 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4528 "movd\t{$src, $dst|$dst, $src}",
4529 [(store (i32 (vector_extract (v4i32 VR128:$src),
4530 (iPTR 0))), addr:$dst)],
4533 //===---------------------------------------------------------------------===//
4534 // Move Packed Doubleword Int first element to Doubleword Int
4536 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4537 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4538 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4541 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4543 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4544 "mov{d|q}\t{$src, $dst|$dst, $src}",
4545 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4549 //===---------------------------------------------------------------------===//
4550 // Bitcast FR64 <-> GR64
4552 let Predicates = [HasAVX] in
4553 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4554 "vmovq\t{$src, $dst|$dst, $src}",
4555 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4557 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4558 "mov{d|q}\t{$src, $dst|$dst, $src}",
4559 [(set GR64:$dst, (bitconvert FR64:$src))],
4560 IIC_SSE_MOVDQ>, VEX;
4561 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4562 "movq\t{$src, $dst|$dst, $src}",
4563 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4564 IIC_SSE_MOVDQ>, VEX;
4566 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4567 "movq\t{$src, $dst|$dst, $src}",
4568 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4570 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4571 "mov{d|q}\t{$src, $dst|$dst, $src}",
4572 [(set GR64:$dst, (bitconvert FR64:$src))],
4574 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4575 "movq\t{$src, $dst|$dst, $src}",
4576 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4579 //===---------------------------------------------------------------------===//
4580 // Move Scalar Single to Double Int
4582 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4583 "movd\t{$src, $dst|$dst, $src}",
4584 [(set GR32:$dst, (bitconvert FR32:$src))],
4585 IIC_SSE_MOVD_ToGP>, VEX;
4586 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4587 "movd\t{$src, $dst|$dst, $src}",
4588 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4589 IIC_SSE_MOVDQ>, VEX;
4590 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4591 "movd\t{$src, $dst|$dst, $src}",
4592 [(set GR32:$dst, (bitconvert FR32:$src))],
4594 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4595 "movd\t{$src, $dst|$dst, $src}",
4596 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4599 //===---------------------------------------------------------------------===//
4600 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4602 let AddedComplexity = 15 in {
4603 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4604 "movd\t{$src, $dst|$dst, $src}",
4605 [(set VR128:$dst, (v4i32 (X86vzmovl
4606 (v4i32 (scalar_to_vector GR32:$src)))))],
4607 IIC_SSE_MOVDQ>, VEX;
4608 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4609 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4610 [(set VR128:$dst, (v2i64 (X86vzmovl
4611 (v2i64 (scalar_to_vector GR64:$src)))))],
4615 let AddedComplexity = 15 in {
4616 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4617 "movd\t{$src, $dst|$dst, $src}",
4618 [(set VR128:$dst, (v4i32 (X86vzmovl
4619 (v4i32 (scalar_to_vector GR32:$src)))))],
4621 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4622 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4623 [(set VR128:$dst, (v2i64 (X86vzmovl
4624 (v2i64 (scalar_to_vector GR64:$src)))))],
4628 let AddedComplexity = 20 in {
4629 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4630 "movd\t{$src, $dst|$dst, $src}",
4632 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4633 (loadi32 addr:$src))))))],
4634 IIC_SSE_MOVDQ>, VEX;
4635 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4636 "movd\t{$src, $dst|$dst, $src}",
4638 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4639 (loadi32 addr:$src))))))],
4643 let Predicates = [HasAVX] in {
4644 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4645 let AddedComplexity = 20 in {
4646 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4647 (VMOVZDI2PDIrm addr:$src)>;
4648 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4649 (VMOVZDI2PDIrm addr:$src)>;
4651 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4652 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4653 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4654 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4655 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4656 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4657 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4660 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4661 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4662 (MOVZDI2PDIrm addr:$src)>;
4663 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4664 (MOVZDI2PDIrm addr:$src)>;
4667 // These are the correct encodings of the instructions so that we know how to
4668 // read correct assembly, even though we continue to emit the wrong ones for
4669 // compatibility with Darwin's buggy assembler.
4670 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4671 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4672 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4673 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4674 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4675 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4676 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4677 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4678 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4679 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4680 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4681 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4683 //===---------------------------------------------------------------------===//
4684 // SSE2 - Move Quadword
4685 //===---------------------------------------------------------------------===//
4687 //===---------------------------------------------------------------------===//
4688 // Move Quadword Int to Packed Quadword Int
4690 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4691 "vmovq\t{$src, $dst|$dst, $src}",
4693 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4694 VEX, Requires<[HasAVX]>;
4695 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4696 "movq\t{$src, $dst|$dst, $src}",
4698 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4700 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4702 //===---------------------------------------------------------------------===//
4703 // Move Packed Quadword Int to Quadword Int
4705 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4706 "movq\t{$src, $dst|$dst, $src}",
4707 [(store (i64 (vector_extract (v2i64 VR128:$src),
4708 (iPTR 0))), addr:$dst)],
4709 IIC_SSE_MOVDQ>, VEX;
4710 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4711 "movq\t{$src, $dst|$dst, $src}",
4712 [(store (i64 (vector_extract (v2i64 VR128:$src),
4713 (iPTR 0))), addr:$dst)],
4716 //===---------------------------------------------------------------------===//
4717 // Store / copy lower 64-bits of a XMM register.
4719 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4720 "movq\t{$src, $dst|$dst, $src}",
4721 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4722 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4723 "movq\t{$src, $dst|$dst, $src}",
4724 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4727 let AddedComplexity = 20 in
4728 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4729 "vmovq\t{$src, $dst|$dst, $src}",
4731 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4732 (loadi64 addr:$src))))))],
4734 XS, VEX, Requires<[HasAVX]>;
4736 let AddedComplexity = 20 in
4737 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4738 "movq\t{$src, $dst|$dst, $src}",
4740 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4741 (loadi64 addr:$src))))))],
4743 XS, Requires<[UseSSE2]>;
4745 let Predicates = [HasAVX], AddedComplexity = 20 in {
4746 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4747 (VMOVZQI2PQIrm addr:$src)>;
4748 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4749 (VMOVZQI2PQIrm addr:$src)>;
4750 def : Pat<(v2i64 (X86vzload addr:$src)),
4751 (VMOVZQI2PQIrm addr:$src)>;
4754 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4755 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4756 (MOVZQI2PQIrm addr:$src)>;
4757 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4758 (MOVZQI2PQIrm addr:$src)>;
4759 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4762 let Predicates = [HasAVX] in {
4763 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4764 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4765 def : Pat<(v4i64 (X86vzload addr:$src)),
4766 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4769 //===---------------------------------------------------------------------===//
4770 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4771 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4773 let AddedComplexity = 15 in
4774 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4775 "vmovq\t{$src, $dst|$dst, $src}",
4776 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4778 XS, VEX, Requires<[HasAVX]>;
4779 let AddedComplexity = 15 in
4780 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4781 "movq\t{$src, $dst|$dst, $src}",
4782 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4784 XS, Requires<[UseSSE2]>;
4786 let AddedComplexity = 20 in
4787 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4788 "vmovq\t{$src, $dst|$dst, $src}",
4789 [(set VR128:$dst, (v2i64 (X86vzmovl
4790 (loadv2i64 addr:$src))))],
4792 XS, VEX, Requires<[HasAVX]>;
4793 let AddedComplexity = 20 in {
4794 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4795 "movq\t{$src, $dst|$dst, $src}",
4796 [(set VR128:$dst, (v2i64 (X86vzmovl
4797 (loadv2i64 addr:$src))))],
4799 XS, Requires<[UseSSE2]>;
4802 let AddedComplexity = 20 in {
4803 let Predicates = [HasAVX] in {
4804 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4805 (VMOVZPQILo2PQIrm addr:$src)>;
4806 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4807 (VMOVZPQILo2PQIrr VR128:$src)>;
4809 let Predicates = [UseSSE2] in {
4810 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4811 (MOVZPQILo2PQIrm addr:$src)>;
4812 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4813 (MOVZPQILo2PQIrr VR128:$src)>;
4817 // Instructions to match in the assembler
4818 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4819 "movq\t{$src, $dst|$dst, $src}", [],
4820 IIC_SSE_MOVDQ>, VEX, VEX_W;
4821 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4822 "movq\t{$src, $dst|$dst, $src}", [],
4823 IIC_SSE_MOVDQ>, VEX, VEX_W;
4824 // Recognize "movd" with GR64 destination, but encode as a "movq"
4825 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4826 "movd\t{$src, $dst|$dst, $src}", [],
4827 IIC_SSE_MOVDQ>, VEX, VEX_W;
4829 // Instructions for the disassembler
4830 // xr = XMM register
4833 let Predicates = [HasAVX] in
4834 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4835 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4836 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4837 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4839 //===---------------------------------------------------------------------===//
4840 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4841 //===---------------------------------------------------------------------===//
4842 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4843 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4844 X86MemOperand x86memop> {
4845 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4846 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4847 [(set RC:$dst, (vt (OpNode RC:$src)))],
4849 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4850 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4851 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4855 let Predicates = [HasAVX] in {
4856 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4857 v4f32, VR128, memopv4f32, f128mem>, VEX;
4858 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4859 v4f32, VR128, memopv4f32, f128mem>, VEX;
4860 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4861 v8f32, VR256, memopv8f32, f256mem>, VEX;
4862 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4863 v8f32, VR256, memopv8f32, f256mem>, VEX;
4865 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4866 memopv4f32, f128mem>;
4867 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4868 memopv4f32, f128mem>;
4870 let Predicates = [HasAVX] in {
4871 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4872 (VMOVSHDUPrr VR128:$src)>;
4873 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4874 (VMOVSHDUPrm addr:$src)>;
4875 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4876 (VMOVSLDUPrr VR128:$src)>;
4877 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4878 (VMOVSLDUPrm addr:$src)>;
4879 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4880 (VMOVSHDUPYrr VR256:$src)>;
4881 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4882 (VMOVSHDUPYrm addr:$src)>;
4883 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4884 (VMOVSLDUPYrr VR256:$src)>;
4885 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4886 (VMOVSLDUPYrm addr:$src)>;
4889 let Predicates = [UseSSE3] in {
4890 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4891 (MOVSHDUPrr VR128:$src)>;
4892 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4893 (MOVSHDUPrm addr:$src)>;
4894 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4895 (MOVSLDUPrr VR128:$src)>;
4896 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4897 (MOVSLDUPrm addr:$src)>;
4900 //===---------------------------------------------------------------------===//
4901 // SSE3 - Replicate Double FP - MOVDDUP
4902 //===---------------------------------------------------------------------===//
4904 multiclass sse3_replicate_dfp<string OpcodeStr> {
4905 let neverHasSideEffects = 1 in
4906 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4907 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4908 [], IIC_SSE_MOV_LH>;
4909 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4910 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4913 (scalar_to_vector (loadf64 addr:$src)))))],
4917 // FIXME: Merge with above classe when there're patterns for the ymm version
4918 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4919 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4920 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4921 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4922 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4923 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4926 (scalar_to_vector (loadf64 addr:$src)))))]>;
4929 let Predicates = [HasAVX] in {
4930 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4931 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4934 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4936 let Predicates = [HasAVX] in {
4937 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4938 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4939 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4940 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4941 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4942 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4943 def : Pat<(X86Movddup (bc_v2f64
4944 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4945 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4948 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4949 (VMOVDDUPYrm addr:$src)>;
4950 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4951 (VMOVDDUPYrm addr:$src)>;
4952 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4953 (VMOVDDUPYrm addr:$src)>;
4954 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4955 (VMOVDDUPYrr VR256:$src)>;
4958 let Predicates = [UseSSE3] in {
4959 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4960 (MOVDDUPrm addr:$src)>;
4961 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4962 (MOVDDUPrm addr:$src)>;
4963 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4964 (MOVDDUPrm addr:$src)>;
4965 def : Pat<(X86Movddup (bc_v2f64
4966 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4967 (MOVDDUPrm addr:$src)>;
4970 //===---------------------------------------------------------------------===//
4971 // SSE3 - Move Unaligned Integer
4972 //===---------------------------------------------------------------------===//
4974 let Predicates = [HasAVX] in {
4975 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4976 "vlddqu\t{$src, $dst|$dst, $src}",
4977 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4978 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4979 "vlddqu\t{$src, $dst|$dst, $src}",
4980 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4982 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4983 "lddqu\t{$src, $dst|$dst, $src}",
4984 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4987 //===---------------------------------------------------------------------===//
4988 // SSE3 - Arithmetic
4989 //===---------------------------------------------------------------------===//
4991 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4992 X86MemOperand x86memop, OpndItins itins,
4994 def rr : I<0xD0, MRMSrcReg,
4995 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4997 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4998 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4999 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5000 def rm : I<0xD0, MRMSrcMem,
5001 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5003 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5005 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5008 let Predicates = [HasAVX] in {
5009 let ExeDomain = SSEPackedSingle in {
5010 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5011 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5012 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5013 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5015 let ExeDomain = SSEPackedDouble in {
5016 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5017 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5018 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5019 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5022 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5023 let ExeDomain = SSEPackedSingle in
5024 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5025 f128mem, SSE_ALU_F32P>, TB, XD;
5026 let ExeDomain = SSEPackedDouble in
5027 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5028 f128mem, SSE_ALU_F64P>, TB, OpSize;
5031 //===---------------------------------------------------------------------===//
5032 // SSE3 Instructions
5033 //===---------------------------------------------------------------------===//
5036 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5037 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5038 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5040 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5041 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5042 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5044 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5048 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5049 IIC_SSE_HADDSUB_RM>;
5051 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5052 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5053 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5055 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5056 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5057 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5059 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5061 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5062 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5063 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5064 IIC_SSE_HADDSUB_RM>;
5067 let Predicates = [HasAVX] in {
5068 let ExeDomain = SSEPackedSingle in {
5069 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5070 X86fhadd, 0>, VEX_4V;
5071 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5072 X86fhsub, 0>, VEX_4V;
5073 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5074 X86fhadd, 0>, VEX_4V;
5075 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5076 X86fhsub, 0>, VEX_4V;
5078 let ExeDomain = SSEPackedDouble in {
5079 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5080 X86fhadd, 0>, VEX_4V;
5081 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5082 X86fhsub, 0>, VEX_4V;
5083 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5084 X86fhadd, 0>, VEX_4V;
5085 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5086 X86fhsub, 0>, VEX_4V;
5090 let Constraints = "$src1 = $dst" in {
5091 let ExeDomain = SSEPackedSingle in {
5092 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5093 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5095 let ExeDomain = SSEPackedDouble in {
5096 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5097 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5101 //===---------------------------------------------------------------------===//
5102 // SSSE3 - Packed Absolute Instructions
5103 //===---------------------------------------------------------------------===//
5106 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5107 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5108 Intrinsic IntId128> {
5109 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5112 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5115 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5117 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5120 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5124 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5125 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5126 Intrinsic IntId256> {
5127 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5130 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5133 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5135 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5138 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5141 let Predicates = [HasAVX] in {
5142 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5143 int_x86_ssse3_pabs_b_128>, VEX;
5144 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5145 int_x86_ssse3_pabs_w_128>, VEX;
5146 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5147 int_x86_ssse3_pabs_d_128>, VEX;
5150 let Predicates = [HasAVX2] in {
5151 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5152 int_x86_avx2_pabs_b>, VEX;
5153 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5154 int_x86_avx2_pabs_w>, VEX;
5155 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5156 int_x86_avx2_pabs_d>, VEX;
5159 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5160 int_x86_ssse3_pabs_b_128>;
5161 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5162 int_x86_ssse3_pabs_w_128>;
5163 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5164 int_x86_ssse3_pabs_d_128>;
5166 //===---------------------------------------------------------------------===//
5167 // SSSE3 - Packed Binary Operator Instructions
5168 //===---------------------------------------------------------------------===//
5170 def SSE_PHADDSUBD : OpndItins<
5171 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5173 def SSE_PHADDSUBSW : OpndItins<
5174 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5176 def SSE_PHADDSUBW : OpndItins<
5177 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5179 def SSE_PSHUFB : OpndItins<
5180 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5182 def SSE_PSIGN : OpndItins<
5183 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5185 def SSE_PMULHRSW : OpndItins<
5186 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5189 /// SS3I_binop_rm - Simple SSSE3 bin op
5190 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5191 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5192 X86MemOperand x86memop, OpndItins itins,
5194 let isCommutable = 1 in
5195 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5196 (ins RC:$src1, RC:$src2),
5198 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5199 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5200 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5202 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5203 (ins RC:$src1, x86memop:$src2),
5205 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5208 (OpVT (OpNode RC:$src1,
5209 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5212 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5213 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5214 Intrinsic IntId128, OpndItins itins,
5216 let isCommutable = 1 in
5217 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5218 (ins VR128:$src1, VR128:$src2),
5220 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5222 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5224 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5225 (ins VR128:$src1, i128mem:$src2),
5227 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5230 (IntId128 VR128:$src1,
5231 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5234 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5235 Intrinsic IntId256> {
5236 let isCommutable = 1 in
5237 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5238 (ins VR256:$src1, VR256:$src2),
5239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5240 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5242 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5243 (ins VR256:$src1, i256mem:$src2),
5244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5246 (IntId256 VR256:$src1,
5247 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5250 let ImmT = NoImm, Predicates = [HasAVX] in {
5251 let isCommutable = 0 in {
5252 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5253 memopv2i64, i128mem,
5254 SSE_PHADDSUBW, 0>, VEX_4V;
5255 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5256 memopv2i64, i128mem,
5257 SSE_PHADDSUBD, 0>, VEX_4V;
5258 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5259 memopv2i64, i128mem,
5260 SSE_PHADDSUBW, 0>, VEX_4V;
5261 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5262 memopv2i64, i128mem,
5263 SSE_PHADDSUBD, 0>, VEX_4V;
5264 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5265 memopv2i64, i128mem,
5266 SSE_PSIGN, 0>, VEX_4V;
5267 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5268 memopv2i64, i128mem,
5269 SSE_PSIGN, 0>, VEX_4V;
5270 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5271 memopv2i64, i128mem,
5272 SSE_PSIGN, 0>, VEX_4V;
5273 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5274 memopv2i64, i128mem,
5275 SSE_PSHUFB, 0>, VEX_4V;
5276 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5277 int_x86_ssse3_phadd_sw_128,
5278 SSE_PHADDSUBSW, 0>, VEX_4V;
5279 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5280 int_x86_ssse3_phsub_sw_128,
5281 SSE_PHADDSUBSW, 0>, VEX_4V;
5282 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5283 int_x86_ssse3_pmadd_ub_sw_128,
5284 SSE_PMADD, 0>, VEX_4V;
5286 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5287 int_x86_ssse3_pmul_hr_sw_128,
5288 SSE_PMULHRSW, 0>, VEX_4V;
5291 let ImmT = NoImm, Predicates = [HasAVX2] in {
5292 let isCommutable = 0 in {
5293 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5294 memopv4i64, i256mem,
5295 SSE_PHADDSUBW, 0>, VEX_4V;
5296 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5297 memopv4i64, i256mem,
5298 SSE_PHADDSUBW, 0>, VEX_4V;
5299 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5300 memopv4i64, i256mem,
5301 SSE_PHADDSUBW, 0>, VEX_4V;
5302 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5303 memopv4i64, i256mem,
5304 SSE_PHADDSUBW, 0>, VEX_4V;
5305 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5306 memopv4i64, i256mem,
5307 SSE_PHADDSUBW, 0>, VEX_4V;
5308 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5309 memopv4i64, i256mem,
5310 SSE_PHADDSUBW, 0>, VEX_4V;
5311 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5312 memopv4i64, i256mem,
5313 SSE_PHADDSUBW, 0>, VEX_4V;
5314 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5315 memopv4i64, i256mem,
5316 SSE_PHADDSUBW, 0>, VEX_4V;
5317 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5318 int_x86_avx2_phadd_sw>, VEX_4V;
5319 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5320 int_x86_avx2_phsub_sw>, VEX_4V;
5321 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5322 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5324 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5325 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5328 // None of these have i8 immediate fields.
5329 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5330 let isCommutable = 0 in {
5331 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5332 memopv2i64, i128mem, SSE_PHADDSUBW>;
5333 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5334 memopv2i64, i128mem, SSE_PHADDSUBD>;
5335 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5336 memopv2i64, i128mem, SSE_PHADDSUBW>;
5337 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5338 memopv2i64, i128mem, SSE_PHADDSUBD>;
5339 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5340 memopv2i64, i128mem, SSE_PSIGN>;
5341 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5342 memopv2i64, i128mem, SSE_PSIGN>;
5343 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5344 memopv2i64, i128mem, SSE_PSIGN>;
5345 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5346 memopv2i64, i128mem, SSE_PSHUFB>;
5347 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5348 int_x86_ssse3_phadd_sw_128,
5350 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5351 int_x86_ssse3_phsub_sw_128,
5353 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5354 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5356 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5357 int_x86_ssse3_pmul_hr_sw_128,
5361 //===---------------------------------------------------------------------===//
5362 // SSSE3 - Packed Align Instruction Patterns
5363 //===---------------------------------------------------------------------===//
5365 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5366 let neverHasSideEffects = 1 in {
5367 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5368 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5370 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5372 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5373 [], IIC_SSE_PALIGNR>, OpSize;
5375 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5376 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5378 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5380 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5381 [], IIC_SSE_PALIGNR>, OpSize;
5385 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5386 let neverHasSideEffects = 1 in {
5387 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5388 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5390 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5393 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5394 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5396 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5401 let Predicates = [HasAVX] in
5402 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5403 let Predicates = [HasAVX2] in
5404 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5405 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5406 defm PALIGN : ssse3_palign<"palignr">;
5408 let Predicates = [HasAVX2] in {
5409 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5410 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5411 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5412 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5413 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5414 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5415 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5416 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5419 let Predicates = [HasAVX] in {
5420 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5421 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5422 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5423 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5424 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5425 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5426 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5427 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5430 let Predicates = [UseSSSE3] in {
5431 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5432 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5433 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5434 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5435 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5436 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5437 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5438 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5441 //===---------------------------------------------------------------------===//
5442 // SSSE3 - Thread synchronization
5443 //===---------------------------------------------------------------------===//
5445 let usesCustomInserter = 1 in {
5446 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5447 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5448 Requires<[HasSSE3]>;
5451 let Uses = [EAX, ECX, EDX] in
5452 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5453 TB, Requires<[HasSSE3]>;
5454 let Uses = [ECX, EAX] in
5455 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5456 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5457 TB, Requires<[HasSSE3]>;
5459 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5460 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5462 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5463 Requires<[In32BitMode]>;
5464 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5465 Requires<[In64BitMode]>;
5467 //===----------------------------------------------------------------------===//
5468 // SSE4.1 - Packed Move with Sign/Zero Extend
5469 //===----------------------------------------------------------------------===//
5471 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5472 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5473 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5474 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5476 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5479 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5483 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5485 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5487 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5489 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5490 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5491 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5494 let Predicates = [HasAVX] in {
5495 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5497 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5499 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5501 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5503 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5505 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5509 let Predicates = [HasAVX2] in {
5510 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5511 int_x86_avx2_pmovsxbw>, VEX;
5512 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5513 int_x86_avx2_pmovsxwd>, VEX;
5514 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5515 int_x86_avx2_pmovsxdq>, VEX;
5516 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5517 int_x86_avx2_pmovzxbw>, VEX;
5518 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5519 int_x86_avx2_pmovzxwd>, VEX;
5520 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5521 int_x86_avx2_pmovzxdq>, VEX;
5524 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5525 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5526 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5527 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5528 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5529 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5531 let Predicates = [HasAVX] in {
5532 // Common patterns involving scalar load.
5533 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5534 (VPMOVSXBWrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5536 (VPMOVSXBWrm addr:$src)>;
5538 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5539 (VPMOVSXWDrm addr:$src)>;
5540 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5541 (VPMOVSXWDrm addr:$src)>;
5543 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5544 (VPMOVSXDQrm addr:$src)>;
5545 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5546 (VPMOVSXDQrm addr:$src)>;
5548 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5549 (VPMOVZXBWrm addr:$src)>;
5550 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5551 (VPMOVZXBWrm addr:$src)>;
5553 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5554 (VPMOVZXWDrm addr:$src)>;
5555 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5556 (VPMOVZXWDrm addr:$src)>;
5558 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5559 (VPMOVZXDQrm addr:$src)>;
5560 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5561 (VPMOVZXDQrm addr:$src)>;
5564 let Predicates = [UseSSE41] in {
5565 // Common patterns involving scalar load.
5566 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5567 (PMOVSXBWrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5569 (PMOVSXBWrm addr:$src)>;
5571 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5572 (PMOVSXWDrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5574 (PMOVSXWDrm addr:$src)>;
5576 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5577 (PMOVSXDQrm addr:$src)>;
5578 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5579 (PMOVSXDQrm addr:$src)>;
5581 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5582 (PMOVZXBWrm addr:$src)>;
5583 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5584 (PMOVZXBWrm addr:$src)>;
5586 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5587 (PMOVZXWDrm addr:$src)>;
5588 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5589 (PMOVZXWDrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5592 (PMOVZXDQrm addr:$src)>;
5593 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5594 (PMOVZXDQrm addr:$src)>;
5597 let Predicates = [HasAVX2] in {
5598 let AddedComplexity = 15 in {
5599 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5600 (VPMOVZXDQYrr VR128:$src)>;
5601 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5602 (VPMOVZXWDYrr VR128:$src)>;
5605 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5606 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5609 let Predicates = [HasAVX] in {
5610 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5611 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5614 let Predicates = [UseSSE41] in {
5615 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5616 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5620 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5621 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5622 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5623 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5625 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5628 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5632 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5634 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5636 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5638 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5641 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5645 let Predicates = [HasAVX] in {
5646 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5648 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5650 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5652 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5656 let Predicates = [HasAVX2] in {
5657 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5658 int_x86_avx2_pmovsxbd>, VEX;
5659 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5660 int_x86_avx2_pmovsxwq>, VEX;
5661 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5662 int_x86_avx2_pmovzxbd>, VEX;
5663 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5664 int_x86_avx2_pmovzxwq>, VEX;
5667 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5668 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5669 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5670 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5672 let Predicates = [HasAVX] in {
5673 // Common patterns involving scalar load
5674 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5675 (VPMOVSXBDrm addr:$src)>;
5676 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5677 (VPMOVSXWQrm addr:$src)>;
5679 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5680 (VPMOVZXBDrm addr:$src)>;
5681 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5682 (VPMOVZXWQrm addr:$src)>;
5685 let Predicates = [UseSSE41] in {
5686 // Common patterns involving scalar load
5687 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5688 (PMOVSXBDrm addr:$src)>;
5689 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5690 (PMOVSXWQrm addr:$src)>;
5692 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5693 (PMOVZXBDrm addr:$src)>;
5694 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5695 (PMOVZXWQrm addr:$src)>;
5698 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5699 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5700 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5701 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5703 // Expecting a i16 load any extended to i32 value.
5704 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5705 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5706 [(set VR128:$dst, (IntId (bitconvert
5707 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5711 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5713 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5715 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5717 // Expecting a i16 load any extended to i32 value.
5718 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5720 [(set VR256:$dst, (IntId (bitconvert
5721 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5725 let Predicates = [HasAVX] in {
5726 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5728 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5731 let Predicates = [HasAVX2] in {
5732 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5733 int_x86_avx2_pmovsxbq>, VEX;
5734 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5735 int_x86_avx2_pmovzxbq>, VEX;
5737 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5738 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5740 let Predicates = [HasAVX] in {
5741 // Common patterns involving scalar load
5742 def : Pat<(int_x86_sse41_pmovsxbq
5743 (bitconvert (v4i32 (X86vzmovl
5744 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5745 (VPMOVSXBQrm addr:$src)>;
5747 def : Pat<(int_x86_sse41_pmovzxbq
5748 (bitconvert (v4i32 (X86vzmovl
5749 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5750 (VPMOVZXBQrm addr:$src)>;
5753 let Predicates = [UseSSE41] in {
5754 // Common patterns involving scalar load
5755 def : Pat<(int_x86_sse41_pmovsxbq
5756 (bitconvert (v4i32 (X86vzmovl
5757 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5758 (PMOVSXBQrm addr:$src)>;
5760 def : Pat<(int_x86_sse41_pmovzxbq
5761 (bitconvert (v4i32 (X86vzmovl
5762 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5763 (PMOVZXBQrm addr:$src)>;
5766 //===----------------------------------------------------------------------===//
5767 // SSE4.1 - Extract Instructions
5768 //===----------------------------------------------------------------------===//
5770 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5771 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5772 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5773 (ins VR128:$src1, i32i8imm:$src2),
5774 !strconcat(OpcodeStr,
5775 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5776 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5778 let neverHasSideEffects = 1, mayStore = 1 in
5779 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5780 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5781 !strconcat(OpcodeStr,
5782 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5785 // There's an AssertZext in the way of writing the store pattern
5786 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5789 let Predicates = [HasAVX] in {
5790 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5791 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5792 (ins VR128:$src1, i32i8imm:$src2),
5793 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5796 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5799 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5800 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5801 let neverHasSideEffects = 1, mayStore = 1 in
5802 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5803 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5804 !strconcat(OpcodeStr,
5805 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5808 // There's an AssertZext in the way of writing the store pattern
5809 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5812 let Predicates = [HasAVX] in
5813 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5815 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5818 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5819 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5820 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5821 (ins VR128:$src1, i32i8imm:$src2),
5822 !strconcat(OpcodeStr,
5823 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5825 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5826 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5827 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5828 !strconcat(OpcodeStr,
5829 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5830 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5831 addr:$dst)]>, OpSize;
5834 let Predicates = [HasAVX] in
5835 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5837 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5839 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5840 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5841 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5842 (ins VR128:$src1, i32i8imm:$src2),
5843 !strconcat(OpcodeStr,
5844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5846 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5847 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5848 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5849 !strconcat(OpcodeStr,
5850 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5851 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5852 addr:$dst)]>, OpSize, REX_W;
5855 let Predicates = [HasAVX] in
5856 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5858 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5860 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5862 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5863 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5864 (ins VR128:$src1, i32i8imm:$src2),
5865 !strconcat(OpcodeStr,
5866 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5868 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5870 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5871 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5872 !strconcat(OpcodeStr,
5873 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5874 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5875 addr:$dst)]>, OpSize;
5878 let ExeDomain = SSEPackedSingle in {
5879 let Predicates = [HasAVX] in {
5880 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5881 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5882 (ins VR128:$src1, i32i8imm:$src2),
5883 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5886 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5889 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5890 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5893 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5895 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5898 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5899 Requires<[UseSSE41]>;
5901 //===----------------------------------------------------------------------===//
5902 // SSE4.1 - Insert Instructions
5903 //===----------------------------------------------------------------------===//
5905 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5906 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5907 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5909 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5911 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5913 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5914 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5915 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5917 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5919 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5921 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5922 imm:$src3))]>, OpSize;
5925 let Predicates = [HasAVX] in
5926 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5927 let Constraints = "$src1 = $dst" in
5928 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5930 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5931 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5932 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5934 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5936 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5938 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5940 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5941 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5943 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5945 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5947 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5948 imm:$src3)))]>, OpSize;
5951 let Predicates = [HasAVX] in
5952 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5953 let Constraints = "$src1 = $dst" in
5954 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5956 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5957 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5958 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5960 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5962 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5964 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5966 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5967 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5969 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5971 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5973 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5974 imm:$src3)))]>, OpSize;
5977 let Predicates = [HasAVX] in
5978 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5979 let Constraints = "$src1 = $dst" in
5980 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5982 // insertps has a few different modes, there's the first two here below which
5983 // are optimized inserts that won't zero arbitrary elements in the destination
5984 // vector. The next one matches the intrinsic and could zero arbitrary elements
5985 // in the target vector.
5986 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5987 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5988 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5990 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5992 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5994 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5996 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5997 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5999 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6001 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6003 (X86insrtps VR128:$src1,
6004 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6005 imm:$src3))]>, OpSize;
6008 let ExeDomain = SSEPackedSingle in {
6009 let Predicates = [HasAVX] in
6010 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6011 let Constraints = "$src1 = $dst" in
6012 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6015 //===----------------------------------------------------------------------===//
6016 // SSE4.1 - Round Instructions
6017 //===----------------------------------------------------------------------===//
6019 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6020 X86MemOperand x86memop, RegisterClass RC,
6021 PatFrag mem_frag32, PatFrag mem_frag64,
6022 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6023 let ExeDomain = SSEPackedSingle in {
6024 // Intrinsic operation, reg.
6025 // Vector intrinsic operation, reg
6026 def PSr : SS4AIi8<opcps, MRMSrcReg,
6027 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6028 !strconcat(OpcodeStr,
6029 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6030 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6033 // Vector intrinsic operation, mem
6034 def PSm : SS4AIi8<opcps, MRMSrcMem,
6035 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6036 !strconcat(OpcodeStr,
6037 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6039 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6041 } // ExeDomain = SSEPackedSingle
6043 let ExeDomain = SSEPackedDouble in {
6044 // Vector intrinsic operation, reg
6045 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6046 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6047 !strconcat(OpcodeStr,
6048 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6049 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6052 // Vector intrinsic operation, mem
6053 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6054 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6055 !strconcat(OpcodeStr,
6056 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6058 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6060 } // ExeDomain = SSEPackedDouble
6063 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6066 Intrinsic F64Int, bit Is2Addr = 1> {
6067 let ExeDomain = GenericDomain in {
6069 def SSr : SS4AIi8<opcss, MRMSrcReg,
6070 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6072 !strconcat(OpcodeStr,
6073 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6074 !strconcat(OpcodeStr,
6075 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6078 // Intrinsic operation, reg.
6079 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6080 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6082 !strconcat(OpcodeStr,
6083 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6084 !strconcat(OpcodeStr,
6085 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6086 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6089 // Intrinsic operation, mem.
6090 def SSm : SS4AIi8<opcss, MRMSrcMem,
6091 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6093 !strconcat(OpcodeStr,
6094 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6095 !strconcat(OpcodeStr,
6096 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6098 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6102 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6103 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6105 !strconcat(OpcodeStr,
6106 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6107 !strconcat(OpcodeStr,
6108 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6111 // Intrinsic operation, reg.
6112 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6113 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6115 !strconcat(OpcodeStr,
6116 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6117 !strconcat(OpcodeStr,
6118 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6119 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6122 // Intrinsic operation, mem.
6123 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6124 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6126 !strconcat(OpcodeStr,
6127 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6128 !strconcat(OpcodeStr,
6129 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6131 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6133 } // ExeDomain = GenericDomain
6136 // FP round - roundss, roundps, roundsd, roundpd
6137 let Predicates = [HasAVX] in {
6139 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6140 memopv4f32, memopv2f64,
6141 int_x86_sse41_round_ps,
6142 int_x86_sse41_round_pd>, VEX;
6143 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6144 memopv8f32, memopv4f64,
6145 int_x86_avx_round_ps_256,
6146 int_x86_avx_round_pd_256>, VEX;
6147 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6148 int_x86_sse41_round_ss,
6149 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6151 def : Pat<(ffloor FR32:$src),
6152 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6153 def : Pat<(f64 (ffloor FR64:$src)),
6154 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6155 def : Pat<(f32 (fnearbyint FR32:$src)),
6156 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6157 def : Pat<(f64 (fnearbyint FR64:$src)),
6158 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6159 def : Pat<(f32 (fceil FR32:$src)),
6160 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6161 def : Pat<(f64 (fceil FR64:$src)),
6162 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6163 def : Pat<(f32 (frint FR32:$src)),
6164 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6165 def : Pat<(f64 (frint FR64:$src)),
6166 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6167 def : Pat<(f32 (ftrunc FR32:$src)),
6168 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6169 def : Pat<(f64 (ftrunc FR64:$src)),
6170 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6173 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6174 memopv4f32, memopv2f64,
6175 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6176 let Constraints = "$src1 = $dst" in
6177 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6178 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6180 def : Pat<(ffloor FR32:$src),
6181 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6182 def : Pat<(f64 (ffloor FR64:$src)),
6183 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6184 def : Pat<(f32 (fnearbyint FR32:$src)),
6185 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6186 def : Pat<(f64 (fnearbyint FR64:$src)),
6187 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6188 def : Pat<(f32 (fceil FR32:$src)),
6189 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6190 def : Pat<(f64 (fceil FR64:$src)),
6191 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6192 def : Pat<(f32 (frint FR32:$src)),
6193 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6194 def : Pat<(f64 (frint FR64:$src)),
6195 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6196 def : Pat<(f32 (ftrunc FR32:$src)),
6197 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6198 def : Pat<(f64 (ftrunc FR64:$src)),
6199 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6201 //===----------------------------------------------------------------------===//
6202 // SSE4.1 - Packed Bit Test
6203 //===----------------------------------------------------------------------===//
6205 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6206 // the intel intrinsic that corresponds to this.
6207 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6208 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6209 "vptest\t{$src2, $src1|$src1, $src2}",
6210 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6212 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6213 "vptest\t{$src2, $src1|$src1, $src2}",
6214 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6217 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6218 "vptest\t{$src2, $src1|$src1, $src2}",
6219 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6221 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6222 "vptest\t{$src2, $src1|$src1, $src2}",
6223 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6227 let Defs = [EFLAGS] in {
6228 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6229 "ptest\t{$src2, $src1|$src1, $src2}",
6230 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6232 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6233 "ptest\t{$src2, $src1|$src1, $src2}",
6234 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6238 // The bit test instructions below are AVX only
6239 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6240 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6241 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6242 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6243 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6244 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6245 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6246 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6250 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6251 let ExeDomain = SSEPackedSingle in {
6252 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6253 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6255 let ExeDomain = SSEPackedDouble in {
6256 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6257 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6261 //===----------------------------------------------------------------------===//
6262 // SSE4.1 - Misc Instructions
6263 //===----------------------------------------------------------------------===//
6265 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6266 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6267 "popcnt{w}\t{$src, $dst|$dst, $src}",
6268 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6270 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6271 "popcnt{w}\t{$src, $dst|$dst, $src}",
6272 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6273 (implicit EFLAGS)]>, OpSize, XS;
6275 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6276 "popcnt{l}\t{$src, $dst|$dst, $src}",
6277 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6279 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6280 "popcnt{l}\t{$src, $dst|$dst, $src}",
6281 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6282 (implicit EFLAGS)]>, XS;
6284 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6285 "popcnt{q}\t{$src, $dst|$dst, $src}",
6286 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6288 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6289 "popcnt{q}\t{$src, $dst|$dst, $src}",
6290 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6291 (implicit EFLAGS)]>, XS;
6296 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6297 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6298 Intrinsic IntId128> {
6299 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6301 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6302 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6303 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6305 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6308 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6311 let Predicates = [HasAVX] in
6312 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6313 int_x86_sse41_phminposuw>, VEX;
6314 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6315 int_x86_sse41_phminposuw>;
6317 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6318 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6319 Intrinsic IntId128, bit Is2Addr = 1> {
6320 let isCommutable = 1 in
6321 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6322 (ins VR128:$src1, VR128:$src2),
6324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6326 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6327 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6328 (ins VR128:$src1, i128mem:$src2),
6330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6333 (IntId128 VR128:$src1,
6334 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6337 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6338 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6339 Intrinsic IntId256> {
6340 let isCommutable = 1 in
6341 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6342 (ins VR256:$src1, VR256:$src2),
6343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6344 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6345 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6346 (ins VR256:$src1, i256mem:$src2),
6347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6349 (IntId256 VR256:$src1,
6350 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6353 let Predicates = [HasAVX] in {
6354 let isCommutable = 0 in
6355 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6357 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6359 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6361 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6363 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6365 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6367 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6369 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6371 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6373 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6377 let Predicates = [HasAVX2] in {
6378 let isCommutable = 0 in
6379 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6380 int_x86_avx2_packusdw>, VEX_4V;
6381 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6382 int_x86_avx2_pmins_b>, VEX_4V;
6383 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6384 int_x86_avx2_pmins_d>, VEX_4V;
6385 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6386 int_x86_avx2_pminu_d>, VEX_4V;
6387 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6388 int_x86_avx2_pminu_w>, VEX_4V;
6389 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6390 int_x86_avx2_pmaxs_b>, VEX_4V;
6391 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6392 int_x86_avx2_pmaxs_d>, VEX_4V;
6393 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6394 int_x86_avx2_pmaxu_d>, VEX_4V;
6395 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6396 int_x86_avx2_pmaxu_w>, VEX_4V;
6397 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6398 int_x86_avx2_pmul_dq>, VEX_4V;
6401 let Constraints = "$src1 = $dst" in {
6402 let isCommutable = 0 in
6403 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6404 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6405 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6406 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6407 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6408 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6409 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6410 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6411 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6412 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6415 /// SS48I_binop_rm - Simple SSE41 binary operator.
6416 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6417 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6418 X86MemOperand x86memop, bit Is2Addr = 1> {
6419 let isCommutable = 1 in
6420 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6421 (ins RC:$src1, RC:$src2),
6423 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6424 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6425 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6426 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6427 (ins RC:$src1, x86memop:$src2),
6429 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6432 (OpVT (OpNode RC:$src1,
6433 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6436 let Predicates = [HasAVX] in {
6437 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6438 memopv2i64, i128mem, 0>, VEX_4V;
6439 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6440 memopv2i64, i128mem, 0>, VEX_4V;
6442 let Predicates = [HasAVX2] in {
6443 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6444 memopv4i64, i256mem, 0>, VEX_4V;
6445 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6446 memopv4i64, i256mem, 0>, VEX_4V;
6449 let Constraints = "$src1 = $dst" in {
6450 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6451 memopv2i64, i128mem>;
6452 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6453 memopv2i64, i128mem>;
6456 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6457 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6458 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6459 X86MemOperand x86memop, bit Is2Addr = 1> {
6460 let isCommutable = 1 in
6461 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6462 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6464 !strconcat(OpcodeStr,
6465 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6466 !strconcat(OpcodeStr,
6467 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6468 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6470 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6471 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6473 !strconcat(OpcodeStr,
6474 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6475 !strconcat(OpcodeStr,
6476 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6479 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6483 let Predicates = [HasAVX] in {
6484 let isCommutable = 0 in {
6485 let ExeDomain = SSEPackedSingle in {
6486 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6487 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6488 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6489 int_x86_avx_blend_ps_256, VR256, memopv8f32, f256mem, 0>, VEX_4V;
6491 let ExeDomain = SSEPackedDouble in {
6492 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6493 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6494 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6495 int_x86_avx_blend_pd_256, VR256, memopv4f64, f256mem, 0>, VEX_4V;
6497 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6498 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6499 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6500 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6502 let ExeDomain = SSEPackedSingle in
6503 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6504 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6505 let ExeDomain = SSEPackedDouble in
6506 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6507 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6508 let ExeDomain = SSEPackedSingle in
6509 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6510 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6513 let Predicates = [HasAVX2] in {
6514 let isCommutable = 0 in {
6515 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6516 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6517 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6518 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6522 let Constraints = "$src1 = $dst" in {
6523 let isCommutable = 0 in {
6524 let ExeDomain = SSEPackedSingle in
6525 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6526 VR128, memopv4f32, f128mem>;
6527 let ExeDomain = SSEPackedDouble in
6528 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6529 VR128, memopv2f64, f128mem>;
6530 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6531 VR128, memopv2i64, i128mem>;
6532 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6533 VR128, memopv2i64, i128mem>;
6535 let ExeDomain = SSEPackedSingle in
6536 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6537 VR128, memopv4f32, f128mem>;
6538 let ExeDomain = SSEPackedDouble in
6539 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6540 VR128, memopv2f64, f128mem>;
6543 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6544 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6545 RegisterClass RC, X86MemOperand x86memop,
6546 PatFrag mem_frag, Intrinsic IntId> {
6547 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6548 (ins RC:$src1, RC:$src2, RC:$src3),
6549 !strconcat(OpcodeStr,
6550 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6551 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6552 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6554 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6555 (ins RC:$src1, x86memop:$src2, RC:$src3),
6556 !strconcat(OpcodeStr,
6557 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6559 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6561 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6564 let Predicates = [HasAVX] in {
6565 let ExeDomain = SSEPackedDouble in {
6566 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6567 memopv2f64, int_x86_sse41_blendvpd>;
6568 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6569 memopv4f64, int_x86_avx_blendv_pd_256>;
6570 } // ExeDomain = SSEPackedDouble
6571 let ExeDomain = SSEPackedSingle in {
6572 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6573 memopv4f32, int_x86_sse41_blendvps>;
6574 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6575 memopv8f32, int_x86_avx_blendv_ps_256>;
6576 } // ExeDomain = SSEPackedSingle
6577 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6578 memopv2i64, int_x86_sse41_pblendvb>;
6581 let Predicates = [HasAVX2] in {
6582 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6583 memopv4i64, int_x86_avx2_pblendvb>;
6586 let Predicates = [HasAVX] in {
6587 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6588 (v16i8 VR128:$src2))),
6589 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6590 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6591 (v4i32 VR128:$src2))),
6592 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6593 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6594 (v4f32 VR128:$src2))),
6595 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6596 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6597 (v2i64 VR128:$src2))),
6598 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6599 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6600 (v2f64 VR128:$src2))),
6601 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6602 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6603 (v8i32 VR256:$src2))),
6604 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6605 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6606 (v8f32 VR256:$src2))),
6607 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6608 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6609 (v4i64 VR256:$src2))),
6610 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6611 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6612 (v4f64 VR256:$src2))),
6613 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6615 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6617 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6618 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6620 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6622 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6624 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6625 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6627 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6628 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6630 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6633 let Predicates = [HasAVX2] in {
6634 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6635 (v32i8 VR256:$src2))),
6636 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6637 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6639 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6642 /// SS41I_ternary_int - SSE 4.1 ternary operator
6643 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6644 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6645 X86MemOperand x86memop, Intrinsic IntId> {
6646 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6647 (ins VR128:$src1, VR128:$src2),
6648 !strconcat(OpcodeStr,
6649 "\t{$src2, $dst|$dst, $src2}"),
6650 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6653 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6654 (ins VR128:$src1, x86memop:$src2),
6655 !strconcat(OpcodeStr,
6656 "\t{$src2, $dst|$dst, $src2}"),
6659 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6663 let ExeDomain = SSEPackedDouble in
6664 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6665 int_x86_sse41_blendvpd>;
6666 let ExeDomain = SSEPackedSingle in
6667 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6668 int_x86_sse41_blendvps>;
6669 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6670 int_x86_sse41_pblendvb>;
6672 // Aliases with the implicit xmm0 argument
6673 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6674 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6675 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6676 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6677 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6678 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6679 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6680 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6681 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6682 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6683 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6684 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6686 let Predicates = [UseSSE41] in {
6687 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6688 (v16i8 VR128:$src2))),
6689 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6690 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6691 (v4i32 VR128:$src2))),
6692 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6693 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6694 (v4f32 VR128:$src2))),
6695 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6696 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6697 (v2i64 VR128:$src2))),
6698 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6699 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6700 (v2f64 VR128:$src2))),
6701 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6703 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6705 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6706 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6708 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6709 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6711 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6715 let Predicates = [HasAVX] in
6716 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6717 "vmovntdqa\t{$src, $dst|$dst, $src}",
6718 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6720 let Predicates = [HasAVX2] in
6721 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6722 "vmovntdqa\t{$src, $dst|$dst, $src}",
6723 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6725 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6726 "movntdqa\t{$src, $dst|$dst, $src}",
6727 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6730 //===----------------------------------------------------------------------===//
6731 // SSE4.2 - Compare Instructions
6732 //===----------------------------------------------------------------------===//
6734 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6735 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6736 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6737 X86MemOperand x86memop, bit Is2Addr = 1> {
6738 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6739 (ins RC:$src1, RC:$src2),
6741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6742 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6743 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6745 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6746 (ins RC:$src1, x86memop:$src2),
6748 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6749 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6751 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6754 let Predicates = [HasAVX] in
6755 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6756 memopv2i64, i128mem, 0>, VEX_4V;
6758 let Predicates = [HasAVX2] in
6759 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6760 memopv4i64, i256mem, 0>, VEX_4V;
6762 let Constraints = "$src1 = $dst" in
6763 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6764 memopv2i64, i128mem>;
6766 //===----------------------------------------------------------------------===//
6767 // SSE4.2 - String/text Processing Instructions
6768 //===----------------------------------------------------------------------===//
6770 // Packed Compare Implicit Length Strings, Return Mask
6771 multiclass pseudo_pcmpistrm<string asm> {
6772 def REG : PseudoI<(outs VR128:$dst),
6773 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6774 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6776 def MEM : PseudoI<(outs VR128:$dst),
6777 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6778 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6779 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6782 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6783 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6784 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6787 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6788 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6789 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6790 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6792 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6793 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6794 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6797 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6798 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6799 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6800 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6802 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6803 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6804 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6807 // Packed Compare Explicit Length Strings, Return Mask
6808 multiclass pseudo_pcmpestrm<string asm> {
6809 def REG : PseudoI<(outs VR128:$dst),
6810 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6811 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6812 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6813 def MEM : PseudoI<(outs VR128:$dst),
6814 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6815 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6816 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6819 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6820 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6821 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6824 let Predicates = [HasAVX],
6825 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6826 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6827 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6828 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6830 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6831 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6832 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6835 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6836 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6837 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6838 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6840 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6841 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6842 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6845 // Packed Compare Implicit Length Strings, Return Index
6846 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6847 multiclass SS42AI_pcmpistri<string asm> {
6848 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6849 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6850 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6853 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6854 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6855 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6860 let Predicates = [HasAVX] in
6861 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6862 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6864 // Packed Compare Explicit Length Strings, Return Index
6865 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6866 multiclass SS42AI_pcmpestri<string asm> {
6867 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6868 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6869 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6872 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6873 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6874 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6879 let Predicates = [HasAVX] in
6880 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
6881 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
6883 //===----------------------------------------------------------------------===//
6884 // SSE4.2 - CRC Instructions
6885 //===----------------------------------------------------------------------===//
6887 // No CRC instructions have AVX equivalents
6889 // crc intrinsic instruction
6890 // This set of instructions are only rm, the only difference is the size
6892 let Constraints = "$src1 = $dst" in {
6893 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6894 (ins GR32:$src1, i8mem:$src2),
6895 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6897 (int_x86_sse42_crc32_32_8 GR32:$src1,
6898 (load addr:$src2)))]>;
6899 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6900 (ins GR32:$src1, GR8:$src2),
6901 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6903 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6904 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6905 (ins GR32:$src1, i16mem:$src2),
6906 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6908 (int_x86_sse42_crc32_32_16 GR32:$src1,
6909 (load addr:$src2)))]>,
6911 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6912 (ins GR32:$src1, GR16:$src2),
6913 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6915 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6917 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6918 (ins GR32:$src1, i32mem:$src2),
6919 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6921 (int_x86_sse42_crc32_32_32 GR32:$src1,
6922 (load addr:$src2)))]>;
6923 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6924 (ins GR32:$src1, GR32:$src2),
6925 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6927 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6928 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6929 (ins GR64:$src1, i8mem:$src2),
6930 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6932 (int_x86_sse42_crc32_64_8 GR64:$src1,
6933 (load addr:$src2)))]>,
6935 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6936 (ins GR64:$src1, GR8:$src2),
6937 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6939 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6941 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6942 (ins GR64:$src1, i64mem:$src2),
6943 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6945 (int_x86_sse42_crc32_64_64 GR64:$src1,
6946 (load addr:$src2)))]>,
6948 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6949 (ins GR64:$src1, GR64:$src2),
6950 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6952 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6956 //===----------------------------------------------------------------------===//
6957 // AES-NI Instructions
6958 //===----------------------------------------------------------------------===//
6960 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6961 Intrinsic IntId128, bit Is2Addr = 1> {
6962 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6963 (ins VR128:$src1, VR128:$src2),
6965 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6967 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6969 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6970 (ins VR128:$src1, i128mem:$src2),
6972 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6975 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6978 // Perform One Round of an AES Encryption/Decryption Flow
6979 let Predicates = [HasAVX, HasAES] in {
6980 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6981 int_x86_aesni_aesenc, 0>, VEX_4V;
6982 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6983 int_x86_aesni_aesenclast, 0>, VEX_4V;
6984 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6985 int_x86_aesni_aesdec, 0>, VEX_4V;
6986 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6987 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6990 let Constraints = "$src1 = $dst" in {
6991 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6992 int_x86_aesni_aesenc>;
6993 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6994 int_x86_aesni_aesenclast>;
6995 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6996 int_x86_aesni_aesdec>;
6997 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6998 int_x86_aesni_aesdeclast>;
7001 // Perform the AES InvMixColumn Transformation
7002 let Predicates = [HasAVX, HasAES] in {
7003 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7005 "vaesimc\t{$src1, $dst|$dst, $src1}",
7007 (int_x86_aesni_aesimc VR128:$src1))]>,
7009 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7010 (ins i128mem:$src1),
7011 "vaesimc\t{$src1, $dst|$dst, $src1}",
7012 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7015 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7017 "aesimc\t{$src1, $dst|$dst, $src1}",
7019 (int_x86_aesni_aesimc VR128:$src1))]>,
7021 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7022 (ins i128mem:$src1),
7023 "aesimc\t{$src1, $dst|$dst, $src1}",
7024 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7027 // AES Round Key Generation Assist
7028 let Predicates = [HasAVX, HasAES] in {
7029 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7030 (ins VR128:$src1, i8imm:$src2),
7031 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7033 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7035 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7036 (ins i128mem:$src1, i8imm:$src2),
7037 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7039 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7042 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7043 (ins VR128:$src1, i8imm:$src2),
7044 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7046 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7048 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7049 (ins i128mem:$src1, i8imm:$src2),
7050 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7052 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7055 //===----------------------------------------------------------------------===//
7056 // PCLMUL Instructions
7057 //===----------------------------------------------------------------------===//
7059 // AVX carry-less Multiplication instructions
7060 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7061 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7062 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7064 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7066 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7067 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7068 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7069 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7070 (memopv2i64 addr:$src2), imm:$src3))]>;
7072 // Carry-less Multiplication instructions
7073 let Constraints = "$src1 = $dst" in {
7074 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7075 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7076 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7078 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7080 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7081 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7082 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7083 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7084 (memopv2i64 addr:$src2), imm:$src3))]>;
7085 } // Constraints = "$src1 = $dst"
7088 multiclass pclmul_alias<string asm, int immop> {
7089 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7090 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7092 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7093 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7095 def : InstAlias<!strconcat("vpclmul", asm,
7096 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7097 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7099 def : InstAlias<!strconcat("vpclmul", asm,
7100 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7101 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7103 defm : pclmul_alias<"hqhq", 0x11>;
7104 defm : pclmul_alias<"hqlq", 0x01>;
7105 defm : pclmul_alias<"lqhq", 0x10>;
7106 defm : pclmul_alias<"lqlq", 0x00>;
7108 //===----------------------------------------------------------------------===//
7109 // SSE4A Instructions
7110 //===----------------------------------------------------------------------===//
7112 let Predicates = [HasSSE4A] in {
7114 let Constraints = "$src = $dst" in {
7115 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7116 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7117 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7118 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7119 imm:$idx))]>, TB, OpSize;
7120 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7121 (ins VR128:$src, VR128:$mask),
7122 "extrq\t{$mask, $src|$src, $mask}",
7123 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7124 VR128:$mask))]>, TB, OpSize;
7126 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7127 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7128 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7129 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7130 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7131 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7132 (ins VR128:$src, VR128:$mask),
7133 "insertq\t{$mask, $src|$src, $mask}",
7134 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7135 VR128:$mask))]>, XD;
7138 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7139 "movntss\t{$src, $dst|$dst, $src}",
7140 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7142 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7143 "movntsd\t{$src, $dst|$dst, $src}",
7144 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7147 //===----------------------------------------------------------------------===//
7149 //===----------------------------------------------------------------------===//
7151 //===----------------------------------------------------------------------===//
7152 // VBROADCAST - Load from memory and broadcast to all elements of the
7153 // destination operand
7155 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7156 X86MemOperand x86memop, Intrinsic Int> :
7157 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7159 [(set RC:$dst, (Int addr:$src))]>, VEX;
7161 // AVX2 adds register forms
7162 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7164 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7166 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7168 let ExeDomain = SSEPackedSingle in {
7169 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7170 int_x86_avx_vbroadcast_ss>;
7171 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7172 int_x86_avx_vbroadcast_ss_256>;
7174 let ExeDomain = SSEPackedDouble in
7175 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7176 int_x86_avx_vbroadcast_sd_256>;
7177 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7178 int_x86_avx_vbroadcastf128_pd_256>;
7180 let ExeDomain = SSEPackedSingle in {
7181 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7182 int_x86_avx2_vbroadcast_ss_ps>;
7183 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7184 int_x86_avx2_vbroadcast_ss_ps_256>;
7186 let ExeDomain = SSEPackedDouble in
7187 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7188 int_x86_avx2_vbroadcast_sd_pd_256>;
7190 let Predicates = [HasAVX2] in
7191 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7192 int_x86_avx2_vbroadcasti128>;
7194 let Predicates = [HasAVX] in
7195 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7196 (VBROADCASTF128 addr:$src)>;
7199 //===----------------------------------------------------------------------===//
7200 // VINSERTF128 - Insert packed floating-point values
7202 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7203 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7204 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7205 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7208 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7209 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7210 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7214 let Predicates = [HasAVX] in {
7215 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7217 (VINSERTF128rr VR256:$src1, VR128:$src2,
7218 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7219 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7221 (VINSERTF128rr VR256:$src1, VR128:$src2,
7222 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7224 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7226 (VINSERTF128rm VR256:$src1, addr:$src2,
7227 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7228 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7230 (VINSERTF128rm VR256:$src1, addr:$src2,
7231 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7234 let Predicates = [HasAVX1Only] in {
7235 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7237 (VINSERTF128rr VR256:$src1, VR128:$src2,
7238 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7239 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7241 (VINSERTF128rr VR256:$src1, VR128:$src2,
7242 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7243 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7245 (VINSERTF128rr VR256:$src1, VR128:$src2,
7246 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7247 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7249 (VINSERTF128rr VR256:$src1, VR128:$src2,
7250 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7252 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7254 (VINSERTF128rm VR256:$src1, addr:$src2,
7255 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7258 //===----------------------------------------------------------------------===//
7259 // VEXTRACTF128 - Extract packed floating-point values
7261 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7262 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7263 (ins VR256:$src1, i8imm:$src2),
7264 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7267 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7268 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7269 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7273 // Extract and store.
7274 let Predicates = [HasAVX] in {
7275 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1,
7276 imm:$src2), addr:$dst),
7277 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7278 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1,
7279 imm:$src2), addr:$dst),
7280 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7281 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1,
7282 imm:$src2), addr:$dst),
7283 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7287 let Predicates = [HasAVX] in {
7288 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7289 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7290 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7291 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7292 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7293 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7295 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7296 (v4f32 (VEXTRACTF128rr
7297 (v8f32 VR256:$src1),
7298 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7299 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7300 (v2f64 (VEXTRACTF128rr
7301 (v4f64 VR256:$src1),
7302 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7305 let Predicates = [HasAVX1Only] in {
7306 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7307 (v2i64 (VEXTRACTF128rr
7308 (v4i64 VR256:$src1),
7309 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7310 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7311 (v4i32 (VEXTRACTF128rr
7312 (v8i32 VR256:$src1),
7313 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7314 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7315 (v8i16 (VEXTRACTF128rr
7316 (v16i16 VR256:$src1),
7317 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7318 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7319 (v16i8 (VEXTRACTF128rr
7320 (v32i8 VR256:$src1),
7321 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7324 //===----------------------------------------------------------------------===//
7325 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7327 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7328 Intrinsic IntLd, Intrinsic IntLd256,
7329 Intrinsic IntSt, Intrinsic IntSt256> {
7330 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7331 (ins VR128:$src1, f128mem:$src2),
7332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7333 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7335 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7336 (ins VR256:$src1, f256mem:$src2),
7337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7338 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7340 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7341 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7343 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7344 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7345 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7347 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7350 let ExeDomain = SSEPackedSingle in
7351 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7352 int_x86_avx_maskload_ps,
7353 int_x86_avx_maskload_ps_256,
7354 int_x86_avx_maskstore_ps,
7355 int_x86_avx_maskstore_ps_256>;
7356 let ExeDomain = SSEPackedDouble in
7357 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7358 int_x86_avx_maskload_pd,
7359 int_x86_avx_maskload_pd_256,
7360 int_x86_avx_maskstore_pd,
7361 int_x86_avx_maskstore_pd_256>;
7363 //===----------------------------------------------------------------------===//
7364 // VPERMIL - Permute Single and Double Floating-Point Values
7366 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7367 RegisterClass RC, X86MemOperand x86memop_f,
7368 X86MemOperand x86memop_i, PatFrag i_frag,
7369 Intrinsic IntVar, ValueType vt> {
7370 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7371 (ins RC:$src1, RC:$src2),
7372 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7373 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7374 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7375 (ins RC:$src1, x86memop_i:$src2),
7376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7377 [(set RC:$dst, (IntVar RC:$src1,
7378 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7380 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7381 (ins RC:$src1, i8imm:$src2),
7382 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7383 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7384 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7385 (ins x86memop_f:$src1, i8imm:$src2),
7386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7388 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7391 let ExeDomain = SSEPackedSingle in {
7392 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7393 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7394 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7395 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7397 let ExeDomain = SSEPackedDouble in {
7398 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7399 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7400 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7401 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7404 let Predicates = [HasAVX] in {
7405 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7406 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7407 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7408 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7409 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7411 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7412 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7413 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7415 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7416 (VPERMILPDri VR128:$src1, imm:$imm)>;
7417 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7418 (VPERMILPDmi addr:$src1, imm:$imm)>;
7421 //===----------------------------------------------------------------------===//
7422 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7424 let ExeDomain = SSEPackedSingle in {
7425 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7426 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7427 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7428 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7429 (i8 imm:$src3))))]>, VEX_4V;
7430 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7431 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7432 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7433 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7434 (i8 imm:$src3)))]>, VEX_4V;
7437 let Predicates = [HasAVX] in {
7438 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7439 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7440 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7441 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7442 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7445 let Predicates = [HasAVX1Only] in {
7446 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7447 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7448 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7449 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7450 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7451 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7452 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7453 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7455 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7456 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7457 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7458 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7459 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7460 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7461 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7462 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7463 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7464 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7465 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7466 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7469 //===----------------------------------------------------------------------===//
7470 // VZERO - Zero YMM registers
7472 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7473 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7474 // Zero All YMM registers
7475 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7476 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7478 // Zero Upper bits of YMM registers
7479 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7480 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7483 //===----------------------------------------------------------------------===//
7484 // Half precision conversion instructions
7485 //===----------------------------------------------------------------------===//
7486 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7487 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7488 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7489 [(set RC:$dst, (Int VR128:$src))]>,
7491 let neverHasSideEffects = 1, mayLoad = 1 in
7492 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7493 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7496 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7497 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7498 (ins RC:$src1, i32i8imm:$src2),
7499 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7500 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7502 let neverHasSideEffects = 1, mayStore = 1 in
7503 def mr : Ii8<0x1D, MRMDestMem, (outs),
7504 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7505 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7509 let Predicates = [HasAVX, HasF16C] in {
7510 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7511 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7512 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7513 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7516 //===----------------------------------------------------------------------===//
7517 // AVX2 Instructions
7518 //===----------------------------------------------------------------------===//
7520 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7521 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7522 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7523 X86MemOperand x86memop> {
7524 let isCommutable = 1 in
7525 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7526 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7527 !strconcat(OpcodeStr,
7528 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7529 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7531 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7532 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7533 !strconcat(OpcodeStr,
7534 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7537 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7541 let isCommutable = 0 in {
7542 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7543 VR128, memopv2i64, i128mem>;
7544 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7545 VR256, memopv4i64, i256mem>;
7548 //===----------------------------------------------------------------------===//
7549 // VPBROADCAST - Load from memory and broadcast to all elements of the
7550 // destination operand
7552 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7553 X86MemOperand x86memop, PatFrag ld_frag,
7554 Intrinsic Int128, Intrinsic Int256> {
7555 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7557 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7558 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7561 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7562 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7564 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7565 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7568 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7571 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7572 int_x86_avx2_pbroadcastb_128,
7573 int_x86_avx2_pbroadcastb_256>;
7574 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7575 int_x86_avx2_pbroadcastw_128,
7576 int_x86_avx2_pbroadcastw_256>;
7577 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7578 int_x86_avx2_pbroadcastd_128,
7579 int_x86_avx2_pbroadcastd_256>;
7580 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7581 int_x86_avx2_pbroadcastq_128,
7582 int_x86_avx2_pbroadcastq_256>;
7584 let Predicates = [HasAVX2] in {
7585 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7586 (VPBROADCASTBrm addr:$src)>;
7587 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7588 (VPBROADCASTBYrm addr:$src)>;
7589 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7590 (VPBROADCASTWrm addr:$src)>;
7591 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7592 (VPBROADCASTWYrm addr:$src)>;
7593 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7594 (VPBROADCASTDrm addr:$src)>;
7595 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7596 (VPBROADCASTDYrm addr:$src)>;
7597 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7598 (VPBROADCASTQrm addr:$src)>;
7599 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7600 (VPBROADCASTQYrm addr:$src)>;
7602 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7603 (VPBROADCASTBrr VR128:$src)>;
7604 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7605 (VPBROADCASTBYrr VR128:$src)>;
7606 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7607 (VPBROADCASTWrr VR128:$src)>;
7608 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7609 (VPBROADCASTWYrr VR128:$src)>;
7610 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7611 (VPBROADCASTDrr VR128:$src)>;
7612 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7613 (VPBROADCASTDYrr VR128:$src)>;
7614 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7615 (VPBROADCASTQrr VR128:$src)>;
7616 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7617 (VPBROADCASTQYrr VR128:$src)>;
7618 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7619 (VBROADCASTSSrr VR128:$src)>;
7620 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7621 (VBROADCASTSSYrr VR128:$src)>;
7622 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7623 (VPBROADCASTQrr VR128:$src)>;
7624 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7625 (VBROADCASTSDYrr VR128:$src)>;
7627 // Provide fallback in case the load node that is used in the patterns above
7628 // is used by additional users, which prevents the pattern selection.
7629 let AddedComplexity = 20 in {
7630 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7631 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7632 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7633 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7634 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7635 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7637 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7638 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7639 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7640 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7641 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7642 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7646 // AVX1 broadcast patterns
7647 let Predicates = [HasAVX1Only] in {
7648 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7649 (VBROADCASTSSYrm addr:$src)>;
7650 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7651 (VBROADCASTSDYrm addr:$src)>;
7652 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7653 (VBROADCASTSSrm addr:$src)>;
7656 let Predicates = [HasAVX] in {
7657 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7658 (VBROADCASTSSYrm addr:$src)>;
7659 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7660 (VBROADCASTSDYrm addr:$src)>;
7661 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7662 (VBROADCASTSSrm addr:$src)>;
7664 // Provide fallback in case the load node that is used in the patterns above
7665 // is used by additional users, which prevents the pattern selection.
7666 let AddedComplexity = 20 in {
7667 // 128bit broadcasts:
7668 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7669 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7670 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7671 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7672 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7673 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7674 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7675 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7676 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7677 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7679 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7680 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7681 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7682 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7683 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7684 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7685 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7686 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7687 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7688 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7692 //===----------------------------------------------------------------------===//
7693 // VPERM - Permute instructions
7696 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7698 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7699 (ins VR256:$src1, VR256:$src2),
7700 !strconcat(OpcodeStr,
7701 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7703 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7704 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7705 (ins VR256:$src1, i256mem:$src2),
7706 !strconcat(OpcodeStr,
7707 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7709 (OpVT (X86VPermv VR256:$src1,
7710 (bitconvert (mem_frag addr:$src2)))))]>,
7714 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7715 let ExeDomain = SSEPackedSingle in
7716 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7718 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7720 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7721 (ins VR256:$src1, i8imm:$src2),
7722 !strconcat(OpcodeStr,
7723 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7725 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7726 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7727 (ins i256mem:$src1, i8imm:$src2),
7728 !strconcat(OpcodeStr,
7729 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7731 (OpVT (X86VPermi (mem_frag addr:$src1),
7732 (i8 imm:$src2))))]>, VEX;
7735 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7736 let ExeDomain = SSEPackedDouble in
7737 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7739 //===----------------------------------------------------------------------===//
7740 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7742 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7743 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7744 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7745 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7746 (i8 imm:$src3))))]>, VEX_4V;
7747 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7748 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7749 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7750 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7751 (i8 imm:$src3)))]>, VEX_4V;
7753 let Predicates = [HasAVX2] in {
7754 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7755 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7756 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7757 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7758 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7759 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7761 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7763 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7764 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7765 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7766 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7767 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7769 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7773 //===----------------------------------------------------------------------===//
7774 // VINSERTI128 - Insert packed integer values
7776 let neverHasSideEffects = 1 in {
7777 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7778 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7779 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7782 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7783 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7784 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7788 let Predicates = [HasAVX2] in {
7789 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7791 (VINSERTI128rr VR256:$src1, VR128:$src2,
7792 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7793 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7795 (VINSERTI128rr VR256:$src1, VR128:$src2,
7796 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7797 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7799 (VINSERTI128rr VR256:$src1, VR128:$src2,
7800 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7801 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7803 (VINSERTI128rr VR256:$src1, VR128:$src2,
7804 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7806 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7808 (VINSERTI128rm VR256:$src1, addr:$src2,
7809 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7812 //===----------------------------------------------------------------------===//
7813 // VEXTRACTI128 - Extract packed integer values
7815 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7816 (ins VR256:$src1, i8imm:$src2),
7817 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7819 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7821 let neverHasSideEffects = 1, mayStore = 1 in
7822 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7823 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7824 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7826 let Predicates = [HasAVX2] in {
7827 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7828 (v2i64 (VEXTRACTI128rr
7829 (v4i64 VR256:$src1),
7830 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7831 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7832 (v4i32 (VEXTRACTI128rr
7833 (v8i32 VR256:$src1),
7834 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7835 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7836 (v8i16 (VEXTRACTI128rr
7837 (v16i16 VR256:$src1),
7838 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7839 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7840 (v16i8 (VEXTRACTI128rr
7841 (v32i8 VR256:$src1),
7842 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7845 //===----------------------------------------------------------------------===//
7846 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7848 multiclass avx2_pmovmask<string OpcodeStr,
7849 Intrinsic IntLd128, Intrinsic IntLd256,
7850 Intrinsic IntSt128, Intrinsic IntSt256> {
7851 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7852 (ins VR128:$src1, i128mem:$src2),
7853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7854 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7855 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7856 (ins VR256:$src1, i256mem:$src2),
7857 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7858 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7859 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7860 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7861 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7862 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7863 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7864 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7865 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7866 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7869 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7870 int_x86_avx2_maskload_d,
7871 int_x86_avx2_maskload_d_256,
7872 int_x86_avx2_maskstore_d,
7873 int_x86_avx2_maskstore_d_256>;
7874 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7875 int_x86_avx2_maskload_q,
7876 int_x86_avx2_maskload_q_256,
7877 int_x86_avx2_maskstore_q,
7878 int_x86_avx2_maskstore_q_256>, VEX_W;
7881 //===----------------------------------------------------------------------===//
7882 // Variable Bit Shifts
7884 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7885 ValueType vt128, ValueType vt256> {
7886 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7887 (ins VR128:$src1, VR128:$src2),
7888 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7890 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7892 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7893 (ins VR128:$src1, i128mem:$src2),
7894 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7896 (vt128 (OpNode VR128:$src1,
7897 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7899 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7900 (ins VR256:$src1, VR256:$src2),
7901 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7903 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7905 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7906 (ins VR256:$src1, i256mem:$src2),
7907 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7909 (vt256 (OpNode VR256:$src1,
7910 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7914 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7915 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7916 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7917 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7918 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
7920 //===----------------------------------------------------------------------===//
7921 // VGATHER - GATHER Operations
7922 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
7923 X86MemOperand memop128, X86MemOperand memop256> {
7924 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
7925 (ins VR128:$src1, memop128:$src2, VR128:$mask),
7926 !strconcat(OpcodeStr,
7927 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7929 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
7930 (ins RC256:$src1, memop256:$src2, RC256:$mask),
7931 !strconcat(OpcodeStr,
7932 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7933 []>, VEX_4VOp3, VEX_L;
7936 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
7937 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
7938 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
7939 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
7940 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
7941 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
7942 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
7943 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
7944 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;