1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 // A 128-bit subvector extract from the first 256-bit vector position
127 // is a subregister copy that needs no instruction.
128 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
129 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
130 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
131 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
133 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
134 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
135 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
136 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
138 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
139 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
140 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
141 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
143 // A 128-bit subvector insert to the first 256-bit vector position
144 // is a subregister copy that needs no instruction.
145 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
146 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
147 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 // Implicitly promote a 32-bit scalar to a vector.
159 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
160 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
161 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 // Implicitly promote a 64-bit scalar to a vector.
164 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
165 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
166 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 // Bitcasts between 128-bit vector types. Return the original type since
170 // no instruction is needed for the conversion
171 let Predicates = [HasXMMInt] in {
172 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
173 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
174 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
178 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
183 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
188 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
193 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
198 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
204 // Bitcasts between 256-bit vector types. Return the original type since
205 // no instruction is needed for the conversion
206 let Predicates = [HasAVX] in {
207 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
208 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
209 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
213 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
218 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
223 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
228 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
233 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
239 //===----------------------------------------------------------------------===//
240 // AVX & SSE - Zero/One Vectors
241 //===----------------------------------------------------------------------===//
243 // Alias instructions that map zero vector to pxor / xorp* for sse.
244 // We set canFoldAsLoad because this can be converted to a constant-pool
245 // load of an all-zeros value if folding it would be beneficial.
246 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
247 // JIT implementation, it does not expand the instructions below like
248 // X86MCInstLower does.
249 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
250 isCodeGenOnly = 1 in {
251 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
252 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
253 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
254 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
255 let ExeDomain = SSEPackedInt in
256 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
257 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
260 // The same as done above but for AVX. The 128-bit versions are the
261 // same, but re-encoded. The 256-bit does not support PI version, and
262 // doesn't need it because on sandy bridge the register is set to zero
263 // at the rename stage without using any execution unit, so SET0PSY
264 // and SET0PDY can be used for vector int instructions without penalty
265 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
266 // JIT implementatioan, it does not expand the instructions below like
267 // X86MCInstLower does.
268 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
269 isCodeGenOnly = 1, Predicates = [HasAVX] in {
270 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
271 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
272 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
273 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
274 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
275 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
276 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
277 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
278 let ExeDomain = SSEPackedInt in
279 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
280 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
283 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
284 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
285 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
287 // AVX has no support for 256-bit integer instructions, but since the 128-bit
288 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
289 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
290 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
291 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
293 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
294 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
295 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
297 //===----------------------------------------------------------------------===//
298 // SSE 1 & 2 - Move FP Scalar Instructions
300 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
301 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
302 // is used instead. Register-to-register movss/movsd is not modeled as an
303 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
304 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
305 //===----------------------------------------------------------------------===//
307 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
308 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
309 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
311 // Loading from memory automatically zeroing upper bits.
312 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
313 PatFrag mem_pat, string OpcodeStr> :
314 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
316 [(set RC:$dst, (mem_pat addr:$src))]>;
319 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
320 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
321 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
322 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
324 let canFoldAsLoad = 1, isReMaterializable = 1 in {
325 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
326 let AddedComplexity = 20 in
327 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
330 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
331 "movss\t{$src, $dst|$dst, $src}",
332 [(store FR32:$src, addr:$dst)]>, XS, VEX;
333 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
334 "movsd\t{$src, $dst|$dst, $src}",
335 [(store FR64:$src, addr:$dst)]>, XD, VEX;
338 let Constraints = "$src1 = $dst" in {
339 def MOVSSrr : sse12_move_rr<FR32, v4f32,
340 "movss\t{$src2, $dst|$dst, $src2}">, XS;
341 def MOVSDrr : sse12_move_rr<FR64, v2f64,
342 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
345 let canFoldAsLoad = 1, isReMaterializable = 1 in {
346 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
348 let AddedComplexity = 20 in
349 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
352 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
353 "movss\t{$src, $dst|$dst, $src}",
354 [(store FR32:$src, addr:$dst)]>;
355 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
356 "movsd\t{$src, $dst|$dst, $src}",
357 [(store FR64:$src, addr:$dst)]>;
360 let Predicates = [HasSSE1] in {
361 let AddedComplexity = 15 in {
362 // Extract the low 32-bit value from one vector and insert it into another.
363 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
364 (MOVSSrr (v4f32 VR128:$src1),
365 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
366 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
367 (MOVSSrr (v4i32 VR128:$src1),
368 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
370 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
371 // MOVSS to the lower bits.
372 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
373 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
374 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
375 (MOVSSrr (v4f32 (V_SET0PS)),
376 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
377 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
378 (MOVSSrr (v4i32 (V_SET0PI)),
379 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
382 let AddedComplexity = 20 in {
383 // MOVSSrm zeros the high parts of the register; represent this
384 // with SUBREG_TO_REG.
385 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
386 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
387 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
388 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
389 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
390 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
393 // Extract and store.
394 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
397 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
399 // Shuffle with MOVSS
400 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
401 (MOVSSrr VR128:$src1, FR32:$src2)>;
402 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
403 (MOVSSrr (v4i32 VR128:$src1),
404 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
405 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
406 (MOVSSrr (v4f32 VR128:$src1),
407 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
410 let Predicates = [HasSSE2] in {
411 let AddedComplexity = 15 in {
412 // Extract the low 64-bit value from one vector and insert it into another.
413 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
414 (MOVSDrr (v2f64 VR128:$src1),
415 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
416 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
417 (MOVSDrr (v2i64 VR128:$src1),
418 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
420 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
421 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
422 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
423 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
424 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
426 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
427 // MOVSD to the lower bits.
428 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
429 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
432 let AddedComplexity = 20 in {
433 // MOVSDrm zeros the high parts of the register; represent this
434 // with SUBREG_TO_REG.
435 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
436 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
437 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
438 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
439 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
440 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
441 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
442 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
443 def : Pat<(v2f64 (X86vzload addr:$src)),
444 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
447 // Extract and store.
448 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
451 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
453 // Shuffle with MOVSD
454 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
455 (MOVSDrr VR128:$src1, FR64:$src2)>;
456 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
457 (MOVSDrr (v2i64 VR128:$src1),
458 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
459 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
460 (MOVSDrr (v2f64 VR128:$src1),
461 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
462 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
463 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
464 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
465 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
467 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
468 // is during lowering, where it's not possible to recognize the fold cause
469 // it has two uses through a bitcast. One use disappears at isel time and the
470 // fold opportunity reappears.
471 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
472 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
473 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
474 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
477 let Predicates = [HasAVX] in {
478 let AddedComplexity = 15 in {
479 // Extract the low 32-bit value from one vector and insert it into another.
480 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
481 (VMOVSSrr (v4f32 VR128:$src1),
482 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
483 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
484 (VMOVSSrr (v4i32 VR128:$src1),
485 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
487 // Extract the low 64-bit value from one vector and insert it into another.
488 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
489 (VMOVSDrr (v2f64 VR128:$src1),
490 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
491 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
492 (VMOVSDrr (v2i64 VR128:$src1),
493 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
495 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
496 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
497 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
498 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
499 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
501 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
502 // MOVS{S,D} to the lower bits.
503 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
504 (VMOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
505 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
506 (VMOVSSrr (v4f32 (V_SET0PS)),
507 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
508 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
509 (VMOVSSrr (v4i32 (V_SET0PI)),
510 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
511 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
512 (VMOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
515 let AddedComplexity = 20 in {
516 // MOVSSrm zeros the high parts of the register; represent this
517 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
518 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
519 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
520 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
521 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
522 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
523 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
525 // MOVSDrm zeros the high parts of the register; represent this
526 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
527 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
528 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
529 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
530 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
531 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
532 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
533 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
534 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
535 def : Pat<(v2f64 (X86vzload addr:$src)),
536 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
538 // Represent the same patterns above but in the form they appear for
540 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
541 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
542 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
543 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
544 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
545 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
548 // Extract and store.
549 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
552 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
553 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
556 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
558 // Shuffle with VMOVSS
559 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
560 (VMOVSSrr VR128:$src1, FR32:$src2)>;
561 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
562 (VMOVSSrr (v4i32 VR128:$src1),
563 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
564 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
565 (VMOVSSrr (v4f32 VR128:$src1),
566 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
568 // Shuffle with VMOVSD
569 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
570 (VMOVSDrr VR128:$src1, FR64:$src2)>;
571 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
572 (VMOVSDrr (v2i64 VR128:$src1),
573 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
574 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
575 (VMOVSDrr (v2f64 VR128:$src1),
576 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
577 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
578 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
580 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
581 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
584 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
585 // is during lowering, where it's not possible to recognize the fold cause
586 // it has two uses through a bitcast. One use disappears at isel time and the
587 // fold opportunity reappears.
588 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
589 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
591 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
592 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
596 //===----------------------------------------------------------------------===//
597 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
598 //===----------------------------------------------------------------------===//
600 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
601 X86MemOperand x86memop, PatFrag ld_frag,
602 string asm, Domain d,
603 bit IsReMaterializable = 1> {
604 let neverHasSideEffects = 1 in
605 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
606 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
607 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
608 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
609 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
610 [(set RC:$dst, (ld_frag addr:$src))], d>;
613 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
614 "movaps", SSEPackedSingle>, TB, VEX;
615 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
616 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
617 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
618 "movups", SSEPackedSingle>, TB, VEX;
619 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
620 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
622 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
623 "movaps", SSEPackedSingle>, TB, VEX;
624 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
625 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
626 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
627 "movups", SSEPackedSingle>, TB, VEX;
628 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
629 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
630 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
631 "movaps", SSEPackedSingle>, TB;
632 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
633 "movapd", SSEPackedDouble>, TB, OpSize;
634 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
635 "movups", SSEPackedSingle>, TB;
636 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
637 "movupd", SSEPackedDouble, 0>, TB, OpSize;
639 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
640 "movaps\t{$src, $dst|$dst, $src}",
641 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
642 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
643 "movapd\t{$src, $dst|$dst, $src}",
644 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
645 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
646 "movups\t{$src, $dst|$dst, $src}",
647 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
648 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
649 "movupd\t{$src, $dst|$dst, $src}",
650 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
651 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
652 "movaps\t{$src, $dst|$dst, $src}",
653 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
654 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
655 "movapd\t{$src, $dst|$dst, $src}",
656 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
657 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
658 "movups\t{$src, $dst|$dst, $src}",
659 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
660 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
661 "movupd\t{$src, $dst|$dst, $src}",
662 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
664 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
665 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
666 (VMOVUPSYmr addr:$dst, VR256:$src)>;
668 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
669 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
670 (VMOVUPDYmr addr:$dst, VR256:$src)>;
672 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
673 "movaps\t{$src, $dst|$dst, $src}",
674 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
675 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
676 "movapd\t{$src, $dst|$dst, $src}",
677 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
678 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
679 "movups\t{$src, $dst|$dst, $src}",
680 [(store (v4f32 VR128:$src), addr:$dst)]>;
681 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
682 "movupd\t{$src, $dst|$dst, $src}",
683 [(store (v2f64 VR128:$src), addr:$dst)]>;
685 let Predicates = [HasAVX] in {
686 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
687 (VMOVUPSmr addr:$dst, VR128:$src)>;
688 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
689 (VMOVUPDmr addr:$dst, VR128:$src)>;
692 let Predicates = [HasSSE1] in
693 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
694 (MOVUPSmr addr:$dst, VR128:$src)>;
695 let Predicates = [HasSSE2] in
696 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
697 (MOVUPDmr addr:$dst, VR128:$src)>;
699 // Move Low/High packed floating point values
700 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
701 PatFrag mov_frag, string base_opc,
703 def PSrm : PI<opc, MRMSrcMem,
704 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
705 !strconcat(base_opc, "s", asm_opr),
708 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
709 SSEPackedSingle>, TB;
711 def PDrm : PI<opc, MRMSrcMem,
712 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
713 !strconcat(base_opc, "d", asm_opr),
714 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
715 (scalar_to_vector (loadf64 addr:$src2)))))],
716 SSEPackedDouble>, TB, OpSize;
719 let AddedComplexity = 20 in {
720 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
721 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
722 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
723 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
725 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
726 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
727 "\t{$src2, $dst|$dst, $src2}">;
728 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
729 "\t{$src2, $dst|$dst, $src2}">;
732 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
733 "movlps\t{$src, $dst|$dst, $src}",
734 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
735 (iPTR 0))), addr:$dst)]>, VEX;
736 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
737 "movlpd\t{$src, $dst|$dst, $src}",
738 [(store (f64 (vector_extract (v2f64 VR128:$src),
739 (iPTR 0))), addr:$dst)]>, VEX;
740 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
741 "movlps\t{$src, $dst|$dst, $src}",
742 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
743 (iPTR 0))), addr:$dst)]>;
744 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
745 "movlpd\t{$src, $dst|$dst, $src}",
746 [(store (f64 (vector_extract (v2f64 VR128:$src),
747 (iPTR 0))), addr:$dst)]>;
749 // v2f64 extract element 1 is always custom lowered to unpack high to low
750 // and extract element 0 so the non-store version isn't too horrible.
751 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
752 "movhps\t{$src, $dst|$dst, $src}",
753 [(store (f64 (vector_extract
754 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
755 (undef)), (iPTR 0))), addr:$dst)]>,
757 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
758 "movhpd\t{$src, $dst|$dst, $src}",
759 [(store (f64 (vector_extract
760 (v2f64 (unpckh VR128:$src, (undef))),
761 (iPTR 0))), addr:$dst)]>,
763 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
764 "movhps\t{$src, $dst|$dst, $src}",
765 [(store (f64 (vector_extract
766 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
767 (undef)), (iPTR 0))), addr:$dst)]>;
768 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
769 "movhpd\t{$src, $dst|$dst, $src}",
770 [(store (f64 (vector_extract
771 (v2f64 (unpckh VR128:$src, (undef))),
772 (iPTR 0))), addr:$dst)]>;
774 let AddedComplexity = 20 in {
775 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
776 (ins VR128:$src1, VR128:$src2),
777 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
779 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
781 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
782 (ins VR128:$src1, VR128:$src2),
783 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
785 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
788 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
789 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
790 (ins VR128:$src1, VR128:$src2),
791 "movlhps\t{$src2, $dst|$dst, $src2}",
793 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
794 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
795 (ins VR128:$src1, VR128:$src2),
796 "movhlps\t{$src2, $dst|$dst, $src2}",
798 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
801 let Predicates = [HasAVX] in {
803 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
804 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
805 def : Pat<(X86Movlhps VR128:$src1,
806 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
807 (VMOVHPSrm VR128:$src1, addr:$src2)>;
808 def : Pat<(X86Movlhps VR128:$src1,
809 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
810 (VMOVHPSrm VR128:$src1, addr:$src2)>;
813 let AddedComplexity = 20 in {
814 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
815 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
816 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
817 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
819 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
820 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
821 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
823 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
824 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
825 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
826 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
827 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
828 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
831 let AddedComplexity = 20 in {
832 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
833 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
834 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
836 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
837 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
838 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
839 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
840 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
843 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
844 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
845 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
846 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
849 let Predicates = [HasSSE1] in {
851 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
852 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
854 def : Pat<(X86Movlhps VR128:$src1,
855 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
856 (MOVHPSrm VR128:$src1, addr:$src2)>;
857 def : Pat<(X86Movlhps VR128:$src1,
858 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
859 (MOVHPSrm VR128:$src1, addr:$src2)>;
862 let AddedComplexity = 20 in {
863 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
864 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
865 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
866 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
868 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
869 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
870 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
872 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
873 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
874 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
875 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
876 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
877 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
880 let AddedComplexity = 20 in {
881 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
882 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
883 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
885 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
886 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
887 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
888 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
889 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
892 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
893 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
894 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
895 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
898 //===----------------------------------------------------------------------===//
899 // SSE 1 & 2 - Conversion Instructions
900 //===----------------------------------------------------------------------===//
902 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
903 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
905 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
906 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
907 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
908 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
911 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
912 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
913 string asm, Domain d> {
914 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
915 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
916 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
917 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
920 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
921 X86MemOperand x86memop, string asm> {
922 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
923 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
924 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
925 (ins DstRC:$src1, x86memop:$src),
926 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
929 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
930 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
931 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
932 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
934 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
935 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
936 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
937 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
940 // The assembler can recognize rr 64-bit instructions by seeing a rxx
941 // register, but the same isn't true when only using memory operands,
942 // provide other assembly "l" and "q" forms to address this explicitly
943 // where appropriate to do so.
944 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
946 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
948 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
950 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
952 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
955 let Predicates = [HasAVX] in {
956 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
957 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
958 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
959 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
960 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
961 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
962 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
963 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
965 def : Pat<(f32 (sint_to_fp GR32:$src)),
966 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
967 def : Pat<(f32 (sint_to_fp GR64:$src)),
968 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
969 def : Pat<(f64 (sint_to_fp GR32:$src)),
970 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
971 def : Pat<(f64 (sint_to_fp GR64:$src)),
972 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
975 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
976 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
977 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
978 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
979 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
980 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
981 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
982 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
983 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
984 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
985 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
986 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
987 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
988 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
989 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
990 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
992 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
993 // and/or XMM operand(s).
995 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
996 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
998 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
999 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1000 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1001 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1002 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1003 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1006 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1007 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1008 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1009 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1011 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1012 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1013 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1014 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1015 (ins DstRC:$src1, x86memop:$src2),
1017 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1018 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1019 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1022 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1023 f128mem, load, "cvtsd2si">, XD, VEX;
1024 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1025 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1028 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1029 // Get rid of this hack or rename the intrinsics, there are several
1030 // intructions that only match with the intrinsic form, why create duplicates
1031 // to let them be recognized by the assembler?
1032 let Pattern = []<dag> in {
1033 defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load,
1034 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1035 defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load,
1036 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1038 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1039 f128mem, load, "cvtsd2si{l}">, XD;
1040 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1041 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1044 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1045 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1046 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1047 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1049 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1050 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1051 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1052 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1055 let Constraints = "$src1 = $dst" in {
1056 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1057 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1059 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1060 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1061 "cvtsi2ss{q}">, XS, REX_W;
1062 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1063 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1065 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1066 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1067 "cvtsi2sd">, XD, REX_W;
1072 // Aliases for intrinsics
1073 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1074 f32mem, load, "cvttss2si">, XS, VEX;
1075 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1076 int_x86_sse_cvttss2si64, f32mem, load,
1077 "cvttss2si">, XS, VEX, VEX_W;
1078 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1079 f128mem, load, "cvttsd2si">, XD, VEX;
1080 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1081 int_x86_sse2_cvttsd2si64, f128mem, load,
1082 "cvttsd2si">, XD, VEX, VEX_W;
1083 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1084 f32mem, load, "cvttss2si">, XS;
1085 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1086 int_x86_sse_cvttss2si64, f32mem, load,
1087 "cvttss2si{q}">, XS, REX_W;
1088 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1089 f128mem, load, "cvttsd2si">, XD;
1090 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1091 int_x86_sse2_cvttsd2si64, f128mem, load,
1092 "cvttsd2si{q}">, XD, REX_W;
1094 let Pattern = []<dag> in {
1095 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1096 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1097 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1098 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1100 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1101 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1102 SSEPackedSingle>, TB, VEX;
1103 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1104 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1105 SSEPackedSingle>, TB, VEX;
1108 let Pattern = []<dag> in {
1109 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1110 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1111 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1112 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1113 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1114 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1115 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1118 let Predicates = [HasSSE1] in {
1119 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1120 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1121 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1122 (CVTSS2SIrm addr:$src)>;
1123 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1124 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1125 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1126 (CVTSS2SI64rm addr:$src)>;
1129 let Predicates = [HasAVX] in {
1130 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1131 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1132 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1133 (VCVTSS2SIrm addr:$src)>;
1134 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1135 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1136 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1137 (VCVTSS2SI64rm addr:$src)>;
1142 // Convert scalar double to scalar single
1143 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1144 (ins FR64:$src1, FR64:$src2),
1145 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1147 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1148 (ins FR64:$src1, f64mem:$src2),
1149 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1150 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1151 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1154 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1155 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1156 [(set FR32:$dst, (fround FR64:$src))]>;
1157 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1158 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1159 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1160 Requires<[HasSSE2, OptForSize]>;
1162 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1163 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1165 let Constraints = "$src1 = $dst" in
1166 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1167 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1169 // Convert scalar single to scalar double
1170 // SSE2 instructions with XS prefix
1171 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1172 (ins FR32:$src1, FR32:$src2),
1173 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1174 []>, XS, Requires<[HasAVX]>, VEX_4V;
1175 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1176 (ins FR32:$src1, f32mem:$src2),
1177 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1178 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1180 let Predicates = [HasAVX] in {
1181 def : Pat<(f64 (fextend FR32:$src)),
1182 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1183 def : Pat<(fextend (loadf32 addr:$src)),
1184 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1185 def : Pat<(extloadf32 addr:$src),
1186 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1189 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1190 "cvtss2sd\t{$src, $dst|$dst, $src}",
1191 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1192 Requires<[HasSSE2]>;
1193 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1194 "cvtss2sd\t{$src, $dst|$dst, $src}",
1195 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1196 Requires<[HasSSE2, OptForSize]>;
1198 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1199 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1200 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1201 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1202 VR128:$src2))]>, XS, VEX_4V,
1204 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1205 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1206 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1207 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1208 (load addr:$src2)))]>, XS, VEX_4V,
1210 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1211 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1212 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1213 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1214 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1215 VR128:$src2))]>, XS,
1216 Requires<[HasSSE2]>;
1217 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1218 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1219 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1220 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1221 (load addr:$src2)))]>, XS,
1222 Requires<[HasSSE2]>;
1225 def : Pat<(extloadf32 addr:$src),
1226 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1227 Requires<[HasSSE2, OptForSpeed]>;
1229 // Convert doubleword to packed single/double fp
1230 // SSE2 instructions without OpSize prefix
1231 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1232 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1233 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1234 TB, VEX, Requires<[HasAVX]>;
1235 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1236 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1238 (bitconvert (memopv2i64 addr:$src))))]>,
1239 TB, VEX, Requires<[HasAVX]>;
1240 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1241 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1242 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1243 TB, Requires<[HasSSE2]>;
1244 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1245 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1246 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1247 (bitconvert (memopv2i64 addr:$src))))]>,
1248 TB, Requires<[HasSSE2]>;
1250 // FIXME: why the non-intrinsic version is described as SSE3?
1251 // SSE2 instructions with XS prefix
1252 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1253 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1254 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1255 XS, VEX, Requires<[HasAVX]>;
1256 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1257 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1258 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1259 (bitconvert (memopv2i64 addr:$src))))]>,
1260 XS, VEX, Requires<[HasAVX]>;
1261 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1262 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1263 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1264 XS, Requires<[HasSSE2]>;
1265 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1266 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1267 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1268 (bitconvert (memopv2i64 addr:$src))))]>,
1269 XS, Requires<[HasSSE2]>;
1272 // Convert packed single/double fp to doubleword
1273 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1274 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1275 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1276 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1277 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1278 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1279 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1280 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1281 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1282 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1283 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1284 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1286 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1287 "cvtps2dq\t{$src, $dst|$dst, $src}",
1288 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1290 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1292 "cvtps2dq\t{$src, $dst|$dst, $src}",
1293 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1294 (memop addr:$src)))]>, VEX;
1295 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1296 "cvtps2dq\t{$src, $dst|$dst, $src}",
1297 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1298 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1299 "cvtps2dq\t{$src, $dst|$dst, $src}",
1300 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1301 (memop addr:$src)))]>;
1303 // SSE2 packed instructions with XD prefix
1304 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1305 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1306 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1307 XD, VEX, Requires<[HasAVX]>;
1308 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1309 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1310 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1311 (memop addr:$src)))]>,
1312 XD, VEX, Requires<[HasAVX]>;
1313 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1314 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1315 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1316 XD, Requires<[HasSSE2]>;
1317 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1318 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1319 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1320 (memop addr:$src)))]>,
1321 XD, Requires<[HasSSE2]>;
1324 // Convert with truncation packed single/double fp to doubleword
1325 // SSE2 packed instructions with XS prefix
1326 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1327 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1328 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1329 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1330 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1331 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1332 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1333 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1334 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1335 "cvttps2dq\t{$src, $dst|$dst, $src}",
1337 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1338 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1339 "cvttps2dq\t{$src, $dst|$dst, $src}",
1341 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1343 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1344 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1346 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1347 XS, VEX, Requires<[HasAVX]>;
1348 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1349 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1350 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1351 (memop addr:$src)))]>,
1352 XS, VEX, Requires<[HasAVX]>;
1354 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1355 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
1356 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1357 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
1359 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1360 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
1361 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1362 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
1363 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1364 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
1365 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1366 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
1368 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1370 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1371 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1373 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1375 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1376 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1377 (memop addr:$src)))]>, VEX;
1378 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1379 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1380 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1381 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1382 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1383 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1384 (memop addr:$src)))]>;
1386 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1387 // register, but the same isn't true when using memory operands instead.
1388 // Provide other assembly rr and rm forms to address this explicitly.
1389 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1390 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1391 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1392 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1395 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1396 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1397 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1398 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1401 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1402 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1403 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1404 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1406 // Convert packed single to packed double
1407 let Predicates = [HasAVX] in {
1408 // SSE2 instructions without OpSize prefix
1409 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1410 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1411 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1412 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1413 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1414 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1415 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1416 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1418 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1419 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1420 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1421 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1423 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1424 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1425 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1426 TB, VEX, Requires<[HasAVX]>;
1427 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1428 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1429 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1430 (load addr:$src)))]>,
1431 TB, VEX, Requires<[HasAVX]>;
1432 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1433 "cvtps2pd\t{$src, $dst|$dst, $src}",
1434 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1435 TB, Requires<[HasSSE2]>;
1436 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1437 "cvtps2pd\t{$src, $dst|$dst, $src}",
1438 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1439 (load addr:$src)))]>,
1440 TB, Requires<[HasSSE2]>;
1442 // Convert packed double to packed single
1443 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1444 // register, but the same isn't true when using memory operands instead.
1445 // Provide other assembly rr and rm forms to address this explicitly.
1446 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1447 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1448 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1449 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1452 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1453 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1454 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1455 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1458 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1459 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1460 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1461 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1462 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1463 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1464 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1465 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1468 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1469 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1470 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1471 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1473 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1474 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1475 (memop addr:$src)))]>;
1476 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1477 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1478 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1479 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1480 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1481 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1482 (memop addr:$src)))]>;
1484 // AVX 256-bit register conversion intrinsics
1485 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1486 // whenever possible to avoid declaring two versions of each one.
1487 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1488 (VCVTDQ2PSYrr VR256:$src)>;
1489 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1490 (VCVTDQ2PSYrm addr:$src)>;
1492 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1493 (VCVTPD2PSYrr VR256:$src)>;
1494 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1495 (VCVTPD2PSYrm addr:$src)>;
1497 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1498 (VCVTPS2DQYrr VR256:$src)>;
1499 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1500 (VCVTPS2DQYrm addr:$src)>;
1502 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1503 (VCVTPS2PDYrr VR128:$src)>;
1504 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1505 (VCVTPS2PDYrm addr:$src)>;
1507 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1508 (VCVTTPD2DQYrr VR256:$src)>;
1509 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1510 (VCVTTPD2DQYrm addr:$src)>;
1512 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1513 (VCVTTPS2DQYrr VR256:$src)>;
1514 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1515 (VCVTTPS2DQYrm addr:$src)>;
1517 // Match fround and fextend for 128/256-bit conversions
1518 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1519 (VCVTPD2PSYrr VR256:$src)>;
1520 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1521 (VCVTPD2PSYrm addr:$src)>;
1523 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1524 (VCVTPS2PDYrr VR128:$src)>;
1525 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1526 (VCVTPS2PDYrm addr:$src)>;
1528 //===----------------------------------------------------------------------===//
1529 // SSE 1 & 2 - Compare Instructions
1530 //===----------------------------------------------------------------------===//
1532 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1533 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1534 string asm, string asm_alt> {
1535 let isAsmParserOnly = 1 in {
1536 def rr : SIi8<0xC2, MRMSrcReg,
1537 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1540 def rm : SIi8<0xC2, MRMSrcMem,
1541 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1545 // Accept explicit immediate argument form instead of comparison code.
1546 def rr_alt : SIi8<0xC2, MRMSrcReg,
1547 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1550 def rm_alt : SIi8<0xC2, MRMSrcMem,
1551 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1555 let neverHasSideEffects = 1 in {
1556 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1557 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1558 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1560 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1561 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1562 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1566 let Constraints = "$src1 = $dst" in {
1567 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1568 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1569 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1570 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1571 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1572 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1573 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1574 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1575 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1576 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1577 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1578 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1579 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1580 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1581 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1582 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1584 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1585 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1586 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1587 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1588 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1589 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1590 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1591 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1592 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1593 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1594 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1595 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1596 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1599 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1600 Intrinsic Int, string asm> {
1601 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1602 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1603 [(set VR128:$dst, (Int VR128:$src1,
1604 VR128:$src, imm:$cc))]>;
1605 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1606 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1607 [(set VR128:$dst, (Int VR128:$src1,
1608 (load addr:$src), imm:$cc))]>;
1611 // Aliases to match intrinsics which expect XMM operand(s).
1612 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1613 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1615 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1616 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1618 let Constraints = "$src1 = $dst" in {
1619 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1620 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1621 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1622 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1626 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1627 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1628 ValueType vt, X86MemOperand x86memop,
1629 PatFrag ld_frag, string OpcodeStr, Domain d> {
1630 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1631 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1632 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1633 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1634 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1635 [(set EFLAGS, (OpNode (vt RC:$src1),
1636 (ld_frag addr:$src2)))], d>;
1639 let Defs = [EFLAGS] in {
1640 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1641 "ucomiss", SSEPackedSingle>, TB, VEX;
1642 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1643 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
1644 let Pattern = []<dag> in {
1645 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1646 "comiss", SSEPackedSingle>, TB, VEX;
1647 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1648 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
1651 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1652 load, "ucomiss", SSEPackedSingle>, TB, VEX;
1653 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1654 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
1656 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1657 load, "comiss", SSEPackedSingle>, TB, VEX;
1658 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1659 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
1660 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1661 "ucomiss", SSEPackedSingle>, TB;
1662 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1663 "ucomisd", SSEPackedDouble>, TB, OpSize;
1665 let Pattern = []<dag> in {
1666 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1667 "comiss", SSEPackedSingle>, TB;
1668 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1669 "comisd", SSEPackedDouble>, TB, OpSize;
1672 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1673 load, "ucomiss", SSEPackedSingle>, TB;
1674 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1675 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1677 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1678 "comiss", SSEPackedSingle>, TB;
1679 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1680 "comisd", SSEPackedDouble>, TB, OpSize;
1681 } // Defs = [EFLAGS]
1683 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1684 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1685 Intrinsic Int, string asm, string asm_alt,
1687 let isAsmParserOnly = 1 in {
1688 def rri : PIi8<0xC2, MRMSrcReg,
1689 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1690 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1691 def rmi : PIi8<0xC2, MRMSrcMem,
1692 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1693 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1696 // Accept explicit immediate argument form instead of comparison code.
1697 def rri_alt : PIi8<0xC2, MRMSrcReg,
1698 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1700 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1701 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1705 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1706 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1707 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1708 SSEPackedSingle>, TB, VEX_4V;
1709 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1710 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1711 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1712 SSEPackedDouble>, TB, OpSize, VEX_4V;
1713 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1714 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1715 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1716 SSEPackedSingle>, TB, VEX_4V;
1717 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1718 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1719 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1720 SSEPackedDouble>, TB, OpSize, VEX_4V;
1721 let Constraints = "$src1 = $dst" in {
1722 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1723 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1724 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1725 SSEPackedSingle>, TB;
1726 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1727 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1728 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1729 SSEPackedDouble>, TB, OpSize;
1732 let Predicates = [HasSSE1] in {
1733 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1734 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1735 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1736 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1739 let Predicates = [HasSSE2] in {
1740 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1741 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1742 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1743 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1746 let Predicates = [HasAVX] in {
1747 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1748 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1749 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1750 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1751 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1752 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1753 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1754 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1756 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1757 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1758 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1759 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1760 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1761 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1762 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1763 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1766 //===----------------------------------------------------------------------===//
1767 // SSE 1 & 2 - Shuffle Instructions
1768 //===----------------------------------------------------------------------===//
1770 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1771 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1772 ValueType vt, string asm, PatFrag mem_frag,
1773 Domain d, bit IsConvertibleToThreeAddress = 0> {
1774 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1775 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1776 [(set RC:$dst, (vt (shufp:$src3
1777 RC:$src1, (mem_frag addr:$src2))))], d>;
1778 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1779 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1780 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1782 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1785 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1786 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1787 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1788 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1789 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1790 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1791 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1792 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1793 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1794 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1795 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1796 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1798 let Constraints = "$src1 = $dst" in {
1799 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1800 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1801 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1803 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1804 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1805 memopv2f64, SSEPackedDouble>, TB, OpSize;
1808 let Predicates = [HasSSE1] in {
1809 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1810 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1811 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1812 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1813 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1814 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1815 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1816 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1817 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1818 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1819 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1820 // fall back to this for SSE1)
1821 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1822 (SHUFPSrri VR128:$src2, VR128:$src1,
1823 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1824 // Special unary SHUFPSrri case.
1825 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1826 (SHUFPSrri VR128:$src1, VR128:$src1,
1827 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1830 let Predicates = [HasSSE2] in {
1831 // Special binary v4i32 shuffle cases with SHUFPS.
1832 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1833 (SHUFPSrri VR128:$src1, VR128:$src2,
1834 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1835 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1836 (bc_v4i32 (memopv2i64 addr:$src2)))),
1837 (SHUFPSrmi VR128:$src1, addr:$src2,
1838 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1839 // Special unary SHUFPDrri cases.
1840 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1841 (SHUFPDrri VR128:$src1, VR128:$src1,
1842 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1843 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1844 (SHUFPDrri VR128:$src1, VR128:$src1,
1845 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1846 // Special binary v2i64 shuffle cases using SHUFPDrri.
1847 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1848 (SHUFPDrri VR128:$src1, VR128:$src2,
1849 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1850 // Generic SHUFPD patterns
1851 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1852 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1853 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1854 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1855 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1856 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1857 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1860 let Predicates = [HasAVX] in {
1861 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1862 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1863 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1864 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1865 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1866 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1867 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1868 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1869 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1870 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1871 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1872 // fall back to this for SSE1)
1873 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1874 (VSHUFPSrri VR128:$src2, VR128:$src1,
1875 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1876 // Special unary SHUFPSrri case.
1877 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1878 (VSHUFPSrri VR128:$src1, VR128:$src1,
1879 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1880 // Special binary v4i32 shuffle cases with SHUFPS.
1881 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1882 (VSHUFPSrri VR128:$src1, VR128:$src2,
1883 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1884 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1885 (bc_v4i32 (memopv2i64 addr:$src2)))),
1886 (VSHUFPSrmi VR128:$src1, addr:$src2,
1887 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1888 // Special unary SHUFPDrri cases.
1889 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1890 (VSHUFPDrri VR128:$src1, VR128:$src1,
1891 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1892 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1893 (VSHUFPDrri VR128:$src1, VR128:$src1,
1894 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1895 // Special binary v2i64 shuffle cases using SHUFPDrri.
1896 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1897 (VSHUFPDrri VR128:$src1, VR128:$src2,
1898 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1900 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1901 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1902 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1903 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1904 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1905 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1906 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1909 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1910 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1911 def : Pat<(v8i32 (X86Shufps VR256:$src1,
1912 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
1913 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1915 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1916 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1917 def : Pat<(v8f32 (X86Shufps VR256:$src1,
1918 (memopv8f32 addr:$src2), (i8 imm:$imm))),
1919 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1921 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1922 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1923 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
1924 (memopv4i64 addr:$src2), (i8 imm:$imm))),
1925 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1927 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1928 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1929 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
1930 (memopv4f64 addr:$src2), (i8 imm:$imm))),
1931 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1934 //===----------------------------------------------------------------------===//
1935 // SSE 1 & 2 - Unpack Instructions
1936 //===----------------------------------------------------------------------===//
1938 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1939 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1940 PatFrag mem_frag, RegisterClass RC,
1941 X86MemOperand x86memop, string asm,
1943 def rr : PI<opc, MRMSrcReg,
1944 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1946 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1947 def rm : PI<opc, MRMSrcMem,
1948 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1950 (vt (OpNode RC:$src1,
1951 (mem_frag addr:$src2))))], d>;
1954 let AddedComplexity = 10 in {
1955 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1956 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1957 SSEPackedSingle>, TB, VEX_4V;
1958 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1959 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1960 SSEPackedDouble>, TB, OpSize, VEX_4V;
1961 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1962 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1963 SSEPackedSingle>, TB, VEX_4V;
1964 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1965 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1966 SSEPackedDouble>, TB, OpSize, VEX_4V;
1968 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1969 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1970 SSEPackedSingle>, TB, VEX_4V;
1971 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1972 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1973 SSEPackedDouble>, TB, OpSize, VEX_4V;
1974 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1975 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1976 SSEPackedSingle>, TB, VEX_4V;
1977 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1978 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1979 SSEPackedDouble>, TB, OpSize, VEX_4V;
1981 let Constraints = "$src1 = $dst" in {
1982 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1983 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1984 SSEPackedSingle>, TB;
1985 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1986 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1987 SSEPackedDouble>, TB, OpSize;
1988 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1989 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1990 SSEPackedSingle>, TB;
1991 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1992 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1993 SSEPackedDouble>, TB, OpSize;
1994 } // Constraints = "$src1 = $dst"
1995 } // AddedComplexity
1997 let Predicates = [HasSSE1] in {
1998 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
1999 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2000 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2001 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2002 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2003 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2004 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2005 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2008 let Predicates = [HasSSE2] in {
2009 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2010 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2011 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2012 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2013 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2014 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2015 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2016 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2018 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2019 // problem is during lowering, where it's not possible to recognize the load
2020 // fold cause it has two uses through a bitcast. One use disappears at isel
2021 // time and the fold opportunity reappears.
2022 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2023 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2025 let AddedComplexity = 10 in
2026 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2027 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2030 let Predicates = [HasAVX] in {
2031 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2032 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2033 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2034 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2035 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2036 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2037 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2038 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2040 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2041 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2042 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2043 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2044 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2045 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2046 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2047 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2048 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2049 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2050 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2051 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2052 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2053 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2054 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2055 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2057 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2058 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2059 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2060 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2061 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2062 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2063 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2064 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2066 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2067 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2068 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2069 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2070 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2071 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2072 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2073 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2074 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2075 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2076 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2077 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2078 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2079 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2080 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2081 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2083 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2084 // problem is during lowering, where it's not possible to recognize the load
2085 // fold cause it has two uses through a bitcast. One use disappears at isel
2086 // time and the fold opportunity reappears.
2087 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2088 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2089 let AddedComplexity = 10 in
2090 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2091 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2094 //===----------------------------------------------------------------------===//
2095 // SSE 1 & 2 - Extract Floating-Point Sign mask
2096 //===----------------------------------------------------------------------===//
2098 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2099 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2101 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2102 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2103 [(set GR32:$dst, (Int RC:$src))], d>;
2104 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2105 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2108 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2109 SSEPackedSingle>, TB;
2110 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2111 SSEPackedDouble>, TB, OpSize;
2113 def : Pat<(i32 (X86fgetsign FR32:$src)),
2114 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2115 sub_ss))>, Requires<[HasSSE1]>;
2116 def : Pat<(i64 (X86fgetsign FR32:$src)),
2117 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2118 sub_ss))>, Requires<[HasSSE1]>;
2119 def : Pat<(i32 (X86fgetsign FR64:$src)),
2120 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2121 sub_sd))>, Requires<[HasSSE2]>;
2122 def : Pat<(i64 (X86fgetsign FR64:$src)),
2123 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2124 sub_sd))>, Requires<[HasSSE2]>;
2126 let Predicates = [HasAVX] in {
2127 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2128 "movmskps", SSEPackedSingle>, TB, VEX;
2129 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2130 "movmskpd", SSEPackedDouble>, TB, OpSize,
2132 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2133 "movmskps", SSEPackedSingle>, TB, VEX;
2134 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2135 "movmskpd", SSEPackedDouble>, TB, OpSize,
2138 def : Pat<(i32 (X86fgetsign FR32:$src)),
2139 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2141 def : Pat<(i64 (X86fgetsign FR32:$src)),
2142 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2144 def : Pat<(i32 (X86fgetsign FR64:$src)),
2145 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2147 def : Pat<(i64 (X86fgetsign FR64:$src)),
2148 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2152 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2153 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2154 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2155 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
2157 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2158 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2159 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2160 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
2164 //===----------------------------------------------------------------------===//
2165 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
2166 //===----------------------------------------------------------------------===//
2168 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
2169 // names that start with 'Fs'.
2171 // Alias instructions that map fld0 to pxor for sse.
2172 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
2173 canFoldAsLoad = 1 in {
2174 // FIXME: Set encoding to pseudo!
2175 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
2176 [(set FR32:$dst, fp32imm0)]>,
2177 Requires<[HasSSE1]>, TB, OpSize;
2178 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
2179 [(set FR64:$dst, fpimm0)]>,
2180 Requires<[HasSSE2]>, TB, OpSize;
2181 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
2182 [(set FR32:$dst, fp32imm0)]>,
2183 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
2184 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
2185 [(set FR64:$dst, fpimm0)]>,
2186 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
2189 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
2190 // bits are disregarded.
2191 let neverHasSideEffects = 1 in {
2192 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2193 "movaps\t{$src, $dst|$dst, $src}", []>;
2194 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2195 "movapd\t{$src, $dst|$dst, $src}", []>;
2198 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
2199 // bits are disregarded.
2200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
2201 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
2202 "movaps\t{$src, $dst|$dst, $src}",
2203 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
2204 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
2205 "movapd\t{$src, $dst|$dst, $src}",
2206 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
2209 //===----------------------------------------------------------------------===//
2210 // SSE 1 & 2 - Logical Instructions
2211 //===----------------------------------------------------------------------===//
2213 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2215 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2217 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2218 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2220 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2221 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2223 let Constraints = "$src1 = $dst" in {
2224 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2225 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2227 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2228 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2232 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2233 let mayLoad = 0 in {
2234 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2235 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2236 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2239 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2240 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2242 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2244 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2246 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2247 // are all promoted to v2i64, and the patterns are covered by the int
2248 // version. This is needed in SSE only, because v2i64 isn't supported on
2249 // SSE1, but only on SSE2.
2250 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2251 !strconcat(OpcodeStr, "ps"), f128mem, [],
2252 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2253 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2255 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2256 !strconcat(OpcodeStr, "pd"), f128mem,
2257 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2258 (bc_v2i64 (v2f64 VR128:$src2))))],
2259 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2260 (memopv2i64 addr:$src2)))], 0>,
2262 let Constraints = "$src1 = $dst" in {
2263 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2264 !strconcat(OpcodeStr, "ps"), f128mem,
2265 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2266 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2267 (memopv2i64 addr:$src2)))]>, TB;
2269 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2270 !strconcat(OpcodeStr, "pd"), f128mem,
2271 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2272 (bc_v2i64 (v2f64 VR128:$src2))))],
2273 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2274 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2278 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2280 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2282 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2283 !strconcat(OpcodeStr, "ps"), f256mem,
2284 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2285 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2286 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2288 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2289 !strconcat(OpcodeStr, "pd"), f256mem,
2290 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2291 (bc_v4i64 (v4f64 VR256:$src2))))],
2292 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2293 (memopv4i64 addr:$src2)))], 0>,
2297 // AVX 256-bit packed logical ops forms
2298 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2299 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2300 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2301 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2303 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2304 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2305 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2306 let isCommutable = 0 in
2307 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2309 //===----------------------------------------------------------------------===//
2310 // SSE 1 & 2 - Arithmetic Instructions
2311 //===----------------------------------------------------------------------===//
2313 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2316 /// In addition, we also have a special variant of the scalar form here to
2317 /// represent the associated intrinsic operation. This form is unlike the
2318 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2319 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2321 /// These three forms can each be reg+reg or reg+mem.
2324 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2326 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2328 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2329 OpNode, FR32, f32mem, Is2Addr>, XS;
2330 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2331 OpNode, FR64, f64mem, Is2Addr>, XD;
2334 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2336 let mayLoad = 0 in {
2337 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2338 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2339 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2340 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2344 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2346 let mayLoad = 0 in {
2347 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2348 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2349 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2350 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2354 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2356 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2357 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2358 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2359 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2362 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2364 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2365 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2366 SSEPackedSingle, Is2Addr>, TB;
2368 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2369 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2370 SSEPackedDouble, Is2Addr>, TB, OpSize;
2373 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2374 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2375 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2376 SSEPackedSingle, 0>, TB;
2378 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2379 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2380 SSEPackedDouble, 0>, TB, OpSize;
2383 // Binary Arithmetic instructions
2384 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2385 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2386 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2387 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2388 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2389 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2390 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2391 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2393 let isCommutable = 0 in {
2394 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2395 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2396 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2397 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2398 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2399 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2400 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2401 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2402 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2403 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2404 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2405 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2406 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2407 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2408 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2409 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2410 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2411 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2412 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2413 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2416 let Constraints = "$src1 = $dst" in {
2417 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2418 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2419 basic_sse12_fp_binop_s_int<0x58, "add">;
2420 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2421 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2422 basic_sse12_fp_binop_s_int<0x59, "mul">;
2424 let isCommutable = 0 in {
2425 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2426 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2427 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2428 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2429 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2430 basic_sse12_fp_binop_s_int<0x5E, "div">;
2431 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2432 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2433 basic_sse12_fp_binop_s_int<0x5F, "max">,
2434 basic_sse12_fp_binop_p_int<0x5F, "max">;
2435 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2436 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2437 basic_sse12_fp_binop_s_int<0x5D, "min">,
2438 basic_sse12_fp_binop_p_int<0x5D, "min">;
2443 /// In addition, we also have a special variant of the scalar form here to
2444 /// represent the associated intrinsic operation. This form is unlike the
2445 /// plain scalar form, in that it takes an entire vector (instead of a
2446 /// scalar) and leaves the top elements undefined.
2448 /// And, we have a special variant form for a full-vector intrinsic form.
2450 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2451 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2452 SDNode OpNode, Intrinsic F32Int> {
2453 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2454 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2455 [(set FR32:$dst, (OpNode FR32:$src))]>;
2456 // For scalar unary operations, fold a load into the operation
2457 // only in OptForSize mode. It eliminates an instruction, but it also
2458 // eliminates a whole-register clobber (the load), so it introduces a
2459 // partial register update condition.
2460 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2461 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2462 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2463 Requires<[HasSSE1, OptForSize]>;
2464 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2465 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2466 [(set VR128:$dst, (F32Int VR128:$src))]>;
2467 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2468 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2469 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2472 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2473 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2474 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2475 !strconcat(OpcodeStr,
2476 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2477 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2478 !strconcat(OpcodeStr,
2479 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2480 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2481 (ins ssmem:$src1, VR128:$src2),
2482 !strconcat(OpcodeStr,
2483 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2486 /// sse1_fp_unop_p - SSE1 unops in packed form.
2487 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2488 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2489 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2490 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2491 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2492 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2493 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2496 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2497 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2498 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2499 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2500 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2501 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2502 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2503 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2506 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2507 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2508 Intrinsic V4F32Int> {
2509 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2510 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2511 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2512 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2513 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2514 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2517 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2518 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2519 Intrinsic V4F32Int> {
2520 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2521 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2522 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2523 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2524 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2525 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2528 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2529 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2530 SDNode OpNode, Intrinsic F64Int> {
2531 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2532 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2533 [(set FR64:$dst, (OpNode FR64:$src))]>;
2534 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2535 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2536 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2537 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2538 Requires<[HasSSE2, OptForSize]>;
2539 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2540 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2541 [(set VR128:$dst, (F64Int VR128:$src))]>;
2542 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2543 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2544 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2547 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2548 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2549 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2550 !strconcat(OpcodeStr,
2551 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2552 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2553 !strconcat(OpcodeStr,
2554 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2555 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2556 (ins VR128:$src1, sdmem:$src2),
2557 !strconcat(OpcodeStr,
2558 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2561 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2562 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2564 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2565 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2566 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2567 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2568 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2569 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2572 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2573 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2574 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2575 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2576 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2577 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2578 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2579 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2582 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2583 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2584 Intrinsic V2F64Int> {
2585 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2586 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2587 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2588 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2589 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2590 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2593 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2594 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2595 Intrinsic V2F64Int> {
2596 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2597 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2598 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2599 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2600 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2601 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2604 let Predicates = [HasAVX] in {
2606 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2607 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2609 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2610 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2611 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2612 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2613 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2614 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2615 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2616 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2619 // Reciprocal approximations. Note that these typically require refinement
2620 // in order to obtain suitable precision.
2621 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2622 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2623 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2624 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2625 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2627 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2628 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2629 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2630 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2631 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2634 def : Pat<(f32 (fsqrt FR32:$src)),
2635 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2636 def : Pat<(f32 (fsqrt (load addr:$src))),
2637 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2638 Requires<[HasAVX, OptForSize]>;
2639 def : Pat<(f64 (fsqrt FR64:$src)),
2640 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2641 def : Pat<(f64 (fsqrt (load addr:$src))),
2642 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2643 Requires<[HasAVX, OptForSize]>;
2645 def : Pat<(f32 (X86frsqrt FR32:$src)),
2646 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2647 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2648 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2649 Requires<[HasAVX, OptForSize]>;
2651 def : Pat<(f32 (X86frcp FR32:$src)),
2652 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2653 def : Pat<(f32 (X86frcp (load addr:$src))),
2654 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2655 Requires<[HasAVX, OptForSize]>;
2657 let Predicates = [HasAVX] in {
2658 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2659 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2660 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2661 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2663 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2664 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2666 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2667 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2668 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2669 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2671 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2672 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2674 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
2675 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2676 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
2677 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2679 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
2680 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2682 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
2683 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2684 (VRCPSSr (f32 (IMPLICIT_DEF)),
2685 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2687 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
2688 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2692 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2693 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2694 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2695 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2696 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2697 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2699 // Reciprocal approximations. Note that these typically require refinement
2700 // in order to obtain suitable precision.
2701 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2702 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2703 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2704 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2705 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2706 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2708 // There is no f64 version of the reciprocal approximation instructions.
2710 //===----------------------------------------------------------------------===//
2711 // SSE 1 & 2 - Non-temporal stores
2712 //===----------------------------------------------------------------------===//
2714 let AddedComplexity = 400 in { // Prefer non-temporal versions
2715 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2716 (ins f128mem:$dst, VR128:$src),
2717 "movntps\t{$src, $dst|$dst, $src}",
2718 [(alignednontemporalstore (v4f32 VR128:$src),
2720 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2721 (ins f128mem:$dst, VR128:$src),
2722 "movntpd\t{$src, $dst|$dst, $src}",
2723 [(alignednontemporalstore (v2f64 VR128:$src),
2725 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2726 (ins f128mem:$dst, VR128:$src),
2727 "movntdq\t{$src, $dst|$dst, $src}",
2728 [(alignednontemporalstore (v2f64 VR128:$src),
2731 let ExeDomain = SSEPackedInt in
2732 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2733 (ins f128mem:$dst, VR128:$src),
2734 "movntdq\t{$src, $dst|$dst, $src}",
2735 [(alignednontemporalstore (v4f32 VR128:$src),
2738 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2739 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2741 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2742 (ins f256mem:$dst, VR256:$src),
2743 "movntps\t{$src, $dst|$dst, $src}",
2744 [(alignednontemporalstore (v8f32 VR256:$src),
2746 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2747 (ins f256mem:$dst, VR256:$src),
2748 "movntpd\t{$src, $dst|$dst, $src}",
2749 [(alignednontemporalstore (v4f64 VR256:$src),
2751 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2752 (ins f256mem:$dst, VR256:$src),
2753 "movntdq\t{$src, $dst|$dst, $src}",
2754 [(alignednontemporalstore (v4f64 VR256:$src),
2756 let ExeDomain = SSEPackedInt in
2757 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2758 (ins f256mem:$dst, VR256:$src),
2759 "movntdq\t{$src, $dst|$dst, $src}",
2760 [(alignednontemporalstore (v8f32 VR256:$src),
2764 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2765 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2766 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2767 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2768 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2769 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2771 let AddedComplexity = 400 in { // Prefer non-temporal versions
2772 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2773 "movntps\t{$src, $dst|$dst, $src}",
2774 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2775 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2776 "movntpd\t{$src, $dst|$dst, $src}",
2777 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2779 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2780 "movntdq\t{$src, $dst|$dst, $src}",
2781 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2783 let ExeDomain = SSEPackedInt in
2784 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2785 "movntdq\t{$src, $dst|$dst, $src}",
2786 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2788 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2789 (MOVNTDQmr addr:$dst, VR128:$src)>;
2791 // There is no AVX form for instructions below this point
2792 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2793 "movnti{l}\t{$src, $dst|$dst, $src}",
2794 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2795 TB, Requires<[HasSSE2]>;
2796 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2797 "movnti{q}\t{$src, $dst|$dst, $src}",
2798 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2799 TB, Requires<[HasSSE2]>;
2802 //===----------------------------------------------------------------------===//
2803 // SSE 1 & 2 - Prefetch and memory fence
2804 //===----------------------------------------------------------------------===//
2806 // Prefetch intrinsic.
2807 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2808 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2809 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2810 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2811 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2812 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2813 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2814 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2816 // Load, store, and memory fence
2817 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2818 TB, Requires<[HasSSE1]>;
2819 def : Pat<(X86SFence), (SFENCE)>;
2821 //===----------------------------------------------------------------------===//
2822 // SSE 1 & 2 - Load/Store XCSR register
2823 //===----------------------------------------------------------------------===//
2825 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2826 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2827 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2828 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2830 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2831 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2832 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2833 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2835 //===---------------------------------------------------------------------===//
2836 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2837 //===---------------------------------------------------------------------===//
2839 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2841 let neverHasSideEffects = 1 in {
2842 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2843 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2844 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2845 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2847 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2848 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2849 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2850 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2852 let canFoldAsLoad = 1, mayLoad = 1 in {
2853 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2854 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2855 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2856 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2857 let Predicates = [HasAVX] in {
2858 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2859 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2860 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2861 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2865 let mayStore = 1 in {
2866 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2867 (ins i128mem:$dst, VR128:$src),
2868 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2869 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2870 (ins i256mem:$dst, VR256:$src),
2871 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2872 let Predicates = [HasAVX] in {
2873 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2874 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2875 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2876 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2880 let neverHasSideEffects = 1 in
2881 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2882 "movdqa\t{$src, $dst|$dst, $src}", []>;
2884 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2885 "movdqu\t{$src, $dst|$dst, $src}",
2886 []>, XS, Requires<[HasSSE2]>;
2888 let canFoldAsLoad = 1, mayLoad = 1 in {
2889 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2890 "movdqa\t{$src, $dst|$dst, $src}",
2891 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2892 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2893 "movdqu\t{$src, $dst|$dst, $src}",
2894 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2895 XS, Requires<[HasSSE2]>;
2898 let mayStore = 1 in {
2899 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2900 "movdqa\t{$src, $dst|$dst, $src}",
2901 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2902 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2903 "movdqu\t{$src, $dst|$dst, $src}",
2904 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2905 XS, Requires<[HasSSE2]>;
2908 // Intrinsic forms of MOVDQU load and store
2909 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2910 "vmovdqu\t{$src, $dst|$dst, $src}",
2911 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2912 XS, VEX, Requires<[HasAVX]>;
2914 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2915 "movdqu\t{$src, $dst|$dst, $src}",
2916 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2917 XS, Requires<[HasSSE2]>;
2919 } // ExeDomain = SSEPackedInt
2921 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2922 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2923 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2925 //===---------------------------------------------------------------------===//
2926 // SSE2 - Packed Integer Arithmetic Instructions
2927 //===---------------------------------------------------------------------===//
2929 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2931 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2932 bit IsCommutable = 0, bit Is2Addr = 1> {
2933 let isCommutable = IsCommutable in
2934 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2935 (ins VR128:$src1, VR128:$src2),
2937 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2939 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2940 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2941 (ins VR128:$src1, i128mem:$src2),
2943 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2945 [(set VR128:$dst, (IntId VR128:$src1,
2946 (bitconvert (memopv2i64 addr:$src2))))]>;
2949 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2950 string OpcodeStr, Intrinsic IntId,
2951 Intrinsic IntId2, bit Is2Addr = 1> {
2952 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2953 (ins VR128:$src1, VR128:$src2),
2955 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2957 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2958 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2959 (ins VR128:$src1, i128mem:$src2),
2961 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2963 [(set VR128:$dst, (IntId VR128:$src1,
2964 (bitconvert (memopv2i64 addr:$src2))))]>;
2965 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2966 (ins VR128:$src1, i32i8imm:$src2),
2968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2970 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2973 /// PDI_binop_rm - Simple SSE2 binary operator.
2974 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2975 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2976 let isCommutable = IsCommutable in
2977 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2978 (ins VR128:$src1, VR128:$src2),
2980 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2981 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2982 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2983 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2984 (ins VR128:$src1, i128mem:$src2),
2986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2988 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2989 (bitconvert (memopv2i64 addr:$src2)))))]>;
2992 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2994 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2995 /// to collapse (bitconvert VT to VT) into its operand.
2997 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2998 bit IsCommutable = 0, bit Is2Addr = 1> {
2999 let isCommutable = IsCommutable in
3000 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3001 (ins VR128:$src1, VR128:$src2),
3003 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3005 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3006 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3007 (ins VR128:$src1, i128mem:$src2),
3009 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3011 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3014 } // ExeDomain = SSEPackedInt
3016 // 128-bit Integer Arithmetic
3018 let Predicates = [HasAVX] in {
3019 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3020 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3021 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3022 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3023 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3024 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3025 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3026 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3027 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3030 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3032 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3034 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3036 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3038 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3040 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3042 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3044 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3046 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3048 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3050 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3052 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3054 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3056 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3058 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3060 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3062 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3064 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3066 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3070 let Constraints = "$src1 = $dst" in {
3071 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3072 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3073 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3074 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3075 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3076 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3077 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3078 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3079 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3082 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3083 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3084 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3085 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3086 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3087 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3088 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3089 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3090 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3091 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3092 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3093 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3094 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3095 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3096 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3097 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3098 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3099 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3100 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3102 } // Constraints = "$src1 = $dst"
3104 //===---------------------------------------------------------------------===//
3105 // SSE2 - Packed Integer Logical Instructions
3106 //===---------------------------------------------------------------------===//
3108 let Predicates = [HasAVX] in {
3109 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3110 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3112 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3113 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3115 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3116 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3119 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3120 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3122 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3123 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3125 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3126 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3129 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3130 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3132 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3133 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3136 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3137 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3138 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3140 let ExeDomain = SSEPackedInt in {
3141 let neverHasSideEffects = 1 in {
3142 // 128-bit logical shifts.
3143 def VPSLLDQri : PDIi8<0x73, MRM7r,
3144 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3145 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3147 def VPSRLDQri : PDIi8<0x73, MRM3r,
3148 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3149 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3151 // PSRADQri doesn't exist in SSE[1-3].
3153 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3154 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3155 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3157 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3159 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3160 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3161 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3162 [(set VR128:$dst, (X86andnp VR128:$src1,
3163 (memopv2i64 addr:$src2)))]>, VEX_4V;
3167 let Constraints = "$src1 = $dst" in {
3168 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3169 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3170 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3171 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3172 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3173 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3175 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3176 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3177 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3178 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3179 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3180 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3182 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3183 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3184 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3185 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3187 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3188 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3189 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3191 let ExeDomain = SSEPackedInt in {
3192 let neverHasSideEffects = 1 in {
3193 // 128-bit logical shifts.
3194 def PSLLDQri : PDIi8<0x73, MRM7r,
3195 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3196 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3197 def PSRLDQri : PDIi8<0x73, MRM3r,
3198 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3199 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3200 // PSRADQri doesn't exist in SSE[1-3].
3202 def PANDNrr : PDI<0xDF, MRMSrcReg,
3203 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3204 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3206 def PANDNrm : PDI<0xDF, MRMSrcMem,
3207 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3208 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3210 } // Constraints = "$src1 = $dst"
3212 let Predicates = [HasAVX] in {
3213 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3214 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3215 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3216 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3217 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3218 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3219 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3220 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3221 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3222 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3224 // Shift up / down and insert zero's.
3225 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3226 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3227 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3228 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3231 let Predicates = [HasSSE2] in {
3232 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3233 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3234 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3235 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3236 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3237 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3238 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3239 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3240 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3241 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3243 // Shift up / down and insert zero's.
3244 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3245 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3246 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3247 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3250 //===---------------------------------------------------------------------===//
3251 // SSE2 - Packed Integer Comparison Instructions
3252 //===---------------------------------------------------------------------===//
3254 let Predicates = [HasAVX] in {
3255 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3257 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3259 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3261 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3263 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3265 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3268 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3269 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3270 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3271 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3272 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3273 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3274 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3275 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3276 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3277 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3278 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3279 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3281 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3282 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3283 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3284 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3285 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3286 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3287 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3288 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3289 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3290 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3291 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3292 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3295 let Constraints = "$src1 = $dst" in {
3296 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3297 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3298 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3299 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3300 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3301 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3302 } // Constraints = "$src1 = $dst"
3304 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3305 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3306 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3307 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3308 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3309 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3310 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3311 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3312 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3313 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3314 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3315 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3317 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3318 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3319 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3320 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3321 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3322 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3323 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3324 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3325 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3326 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3327 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3328 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3330 //===---------------------------------------------------------------------===//
3331 // SSE2 - Packed Integer Pack Instructions
3332 //===---------------------------------------------------------------------===//
3334 let Predicates = [HasAVX] in {
3335 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3337 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3339 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3343 let Constraints = "$src1 = $dst" in {
3344 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3345 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3346 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3347 } // Constraints = "$src1 = $dst"
3349 //===---------------------------------------------------------------------===//
3350 // SSE2 - Packed Integer Shuffle Instructions
3351 //===---------------------------------------------------------------------===//
3353 let ExeDomain = SSEPackedInt in {
3354 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3356 def ri : Ii8<0x70, MRMSrcReg,
3357 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3358 !strconcat(OpcodeStr,
3359 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3360 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3362 def mi : Ii8<0x70, MRMSrcMem,
3363 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3364 !strconcat(OpcodeStr,
3365 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3366 [(set VR128:$dst, (vt (pshuf_frag:$src2
3367 (bc_frag (memopv2i64 addr:$src1)),
3370 } // ExeDomain = SSEPackedInt
3372 let Predicates = [HasAVX] in {
3373 let AddedComplexity = 5 in
3374 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3377 // SSE2 with ImmT == Imm8 and XS prefix.
3378 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3381 // SSE2 with ImmT == Imm8 and XD prefix.
3382 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3385 let AddedComplexity = 5 in
3386 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3387 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3388 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3389 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3390 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3392 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3394 (VPSHUFDmi addr:$src1, imm:$imm)>;
3395 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3397 (VPSHUFDmi addr:$src1, imm:$imm)>;
3398 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3399 (VPSHUFDri VR128:$src1, imm:$imm)>;
3400 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3401 (VPSHUFDri VR128:$src1, imm:$imm)>;
3402 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3403 (VPSHUFHWri VR128:$src, imm:$imm)>;
3404 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3406 (VPSHUFHWmi addr:$src, imm:$imm)>;
3407 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3408 (VPSHUFLWri VR128:$src, imm:$imm)>;
3409 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3411 (VPSHUFLWmi addr:$src, imm:$imm)>;
3414 let Predicates = [HasSSE2] in {
3415 let AddedComplexity = 5 in
3416 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3418 // SSE2 with ImmT == Imm8 and XS prefix.
3419 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3421 // SSE2 with ImmT == Imm8 and XD prefix.
3422 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3424 let AddedComplexity = 5 in
3425 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3426 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3427 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3428 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3429 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3431 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3433 (PSHUFDmi addr:$src1, imm:$imm)>;
3434 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3436 (PSHUFDmi addr:$src1, imm:$imm)>;
3437 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3438 (PSHUFDri VR128:$src1, imm:$imm)>;
3439 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3440 (PSHUFDri VR128:$src1, imm:$imm)>;
3441 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3442 (PSHUFHWri VR128:$src, imm:$imm)>;
3443 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3445 (PSHUFHWmi addr:$src, imm:$imm)>;
3446 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3447 (PSHUFLWri VR128:$src, imm:$imm)>;
3448 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3450 (PSHUFLWmi addr:$src, imm:$imm)>;
3453 //===---------------------------------------------------------------------===//
3454 // SSE2 - Packed Integer Unpack Instructions
3455 //===---------------------------------------------------------------------===//
3457 let ExeDomain = SSEPackedInt in {
3458 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3459 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3460 def rr : PDI<opc, MRMSrcReg,
3461 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3463 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3464 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3465 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3466 def rm : PDI<opc, MRMSrcMem,
3467 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3469 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3470 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3471 [(set VR128:$dst, (OpNode VR128:$src1,
3472 (bc_frag (memopv2i64
3476 let Predicates = [HasAVX] in {
3477 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3478 bc_v16i8, 0>, VEX_4V;
3479 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3480 bc_v8i16, 0>, VEX_4V;
3481 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3482 bc_v4i32, 0>, VEX_4V;
3484 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3485 /// knew to collapse (bitconvert VT to VT) into its operand.
3486 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3487 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3488 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3489 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3490 VR128:$src2)))]>, VEX_4V;
3491 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3492 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3493 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3494 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3495 (memopv2i64 addr:$src2))))]>, VEX_4V;
3497 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3498 bc_v16i8, 0>, VEX_4V;
3499 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3500 bc_v8i16, 0>, VEX_4V;
3501 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3502 bc_v4i32, 0>, VEX_4V;
3504 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3505 /// knew to collapse (bitconvert VT to VT) into its operand.
3506 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3507 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3508 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3509 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3510 VR128:$src2)))]>, VEX_4V;
3511 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3512 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3513 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3514 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3515 (memopv2i64 addr:$src2))))]>, VEX_4V;
3518 let Constraints = "$src1 = $dst" in {
3519 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3520 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3521 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3523 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3524 /// knew to collapse (bitconvert VT to VT) into its operand.
3525 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3526 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3527 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3529 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3530 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3531 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3532 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3534 (v2i64 (X86Punpcklqdq VR128:$src1,
3535 (memopv2i64 addr:$src2))))]>;
3537 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3538 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3539 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3541 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3542 /// knew to collapse (bitconvert VT to VT) into its operand.
3543 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3544 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3545 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3547 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3548 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3549 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3550 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3552 (v2i64 (X86Punpckhqdq VR128:$src1,
3553 (memopv2i64 addr:$src2))))]>;
3556 } // ExeDomain = SSEPackedInt
3558 //===---------------------------------------------------------------------===//
3559 // SSE2 - Packed Integer Extract and Insert
3560 //===---------------------------------------------------------------------===//
3562 let ExeDomain = SSEPackedInt in {
3563 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3564 def rri : Ii8<0xC4, MRMSrcReg,
3565 (outs VR128:$dst), (ins VR128:$src1,
3566 GR32:$src2, i32i8imm:$src3),
3568 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3569 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3571 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3572 def rmi : Ii8<0xC4, MRMSrcMem,
3573 (outs VR128:$dst), (ins VR128:$src1,
3574 i16mem:$src2, i32i8imm:$src3),
3576 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3577 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3579 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3584 let Predicates = [HasAVX] in
3585 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3586 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3587 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3588 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3589 imm:$src2))]>, TB, OpSize, VEX;
3590 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3591 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3592 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3593 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3597 let Predicates = [HasAVX] in {
3598 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
3599 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
3600 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3601 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
3602 []>, TB, OpSize, VEX_4V;
3605 let Constraints = "$src1 = $dst" in
3606 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
3608 } // ExeDomain = SSEPackedInt
3610 //===---------------------------------------------------------------------===//
3611 // SSE2 - Packed Mask Creation
3612 //===---------------------------------------------------------------------===//
3614 let ExeDomain = SSEPackedInt in {
3616 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3617 "pmovmskb\t{$src, $dst|$dst, $src}",
3618 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
3619 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
3620 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
3621 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3622 "pmovmskb\t{$src, $dst|$dst, $src}",
3623 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
3625 } // ExeDomain = SSEPackedInt
3627 //===---------------------------------------------------------------------===//
3628 // SSE2 - Conditional Store
3629 //===---------------------------------------------------------------------===//
3631 let ExeDomain = SSEPackedInt in {
3634 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
3635 (ins VR128:$src, VR128:$mask),
3636 "maskmovdqu\t{$mask, $src|$src, $mask}",
3637 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
3639 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
3640 (ins VR128:$src, VR128:$mask),
3641 "maskmovdqu\t{$mask, $src|$src, $mask}",
3642 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
3645 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3646 "maskmovdqu\t{$mask, $src|$src, $mask}",
3647 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
3649 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3650 "maskmovdqu\t{$mask, $src|$src, $mask}",
3651 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
3653 } // ExeDomain = SSEPackedInt
3655 //===---------------------------------------------------------------------===//
3656 // SSE2 - Move Doubleword
3657 //===---------------------------------------------------------------------===//
3659 //===---------------------------------------------------------------------===//
3660 // Move Int Doubleword to Packed Double Int
3662 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3663 "movd\t{$src, $dst|$dst, $src}",
3665 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
3666 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3667 "movd\t{$src, $dst|$dst, $src}",
3669 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3671 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3672 "mov{d|q}\t{$src, $dst|$dst, $src}",
3674 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
3675 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3676 "mov{d|q}\t{$src, $dst|$dst, $src}",
3677 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
3679 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3680 "movd\t{$src, $dst|$dst, $src}",
3682 (v4i32 (scalar_to_vector GR32:$src)))]>;
3683 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3684 "movd\t{$src, $dst|$dst, $src}",
3686 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
3687 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3688 "mov{d|q}\t{$src, $dst|$dst, $src}",
3690 (v2i64 (scalar_to_vector GR64:$src)))]>;
3691 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3692 "mov{d|q}\t{$src, $dst|$dst, $src}",
3693 [(set FR64:$dst, (bitconvert GR64:$src))]>;
3695 //===---------------------------------------------------------------------===//
3696 // Move Int Doubleword to Single Scalar
3698 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3699 "movd\t{$src, $dst|$dst, $src}",
3700 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3702 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3703 "movd\t{$src, $dst|$dst, $src}",
3704 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3706 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3707 "movd\t{$src, $dst|$dst, $src}",
3708 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3710 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3711 "movd\t{$src, $dst|$dst, $src}",
3712 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3714 //===---------------------------------------------------------------------===//
3715 // Move Packed Doubleword Int to Packed Double Int
3717 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3718 "movd\t{$src, $dst|$dst, $src}",
3719 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3721 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3722 (ins i32mem:$dst, VR128:$src),
3723 "movd\t{$src, $dst|$dst, $src}",
3724 [(store (i32 (vector_extract (v4i32 VR128:$src),
3725 (iPTR 0))), addr:$dst)]>, VEX;
3726 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3727 "movd\t{$src, $dst|$dst, $src}",
3728 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3730 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3731 "movd\t{$src, $dst|$dst, $src}",
3732 [(store (i32 (vector_extract (v4i32 VR128:$src),
3733 (iPTR 0))), addr:$dst)]>;
3735 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3736 "mov{d|q}\t{$src, $dst|$dst, $src}",
3737 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3739 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3740 "movq\t{$src, $dst|$dst, $src}",
3741 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3743 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3744 "mov{d|q}\t{$src, $dst|$dst, $src}",
3745 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3746 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3747 "movq\t{$src, $dst|$dst, $src}",
3748 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3750 //===---------------------------------------------------------------------===//
3751 // Move Scalar Single to Double Int
3753 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3754 "movd\t{$src, $dst|$dst, $src}",
3755 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3756 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3757 "movd\t{$src, $dst|$dst, $src}",
3758 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3759 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3760 "movd\t{$src, $dst|$dst, $src}",
3761 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3762 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3763 "movd\t{$src, $dst|$dst, $src}",
3764 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3766 //===---------------------------------------------------------------------===//
3767 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3769 let AddedComplexity = 15 in {
3770 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3771 "movd\t{$src, $dst|$dst, $src}",
3772 [(set VR128:$dst, (v4i32 (X86vzmovl
3773 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3775 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3776 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3777 [(set VR128:$dst, (v2i64 (X86vzmovl
3778 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3781 let AddedComplexity = 15 in {
3782 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3783 "movd\t{$src, $dst|$dst, $src}",
3784 [(set VR128:$dst, (v4i32 (X86vzmovl
3785 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3786 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3787 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3788 [(set VR128:$dst, (v2i64 (X86vzmovl
3789 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3792 let AddedComplexity = 20 in {
3793 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3794 "movd\t{$src, $dst|$dst, $src}",
3796 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3797 (loadi32 addr:$src))))))]>,
3799 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3800 "movd\t{$src, $dst|$dst, $src}",
3802 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3803 (loadi32 addr:$src))))))]>;
3805 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3806 (MOVZDI2PDIrm addr:$src)>;
3807 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3808 (MOVZDI2PDIrm addr:$src)>;
3809 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3810 (MOVZDI2PDIrm addr:$src)>;
3813 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3814 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3815 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3816 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3817 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3818 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3819 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3820 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3822 // These are the correct encodings of the instructions so that we know how to
3823 // read correct assembly, even though we continue to emit the wrong ones for
3824 // compatibility with Darwin's buggy assembler.
3825 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3826 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3827 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3828 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3829 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3830 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3831 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3832 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3833 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3834 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3835 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3836 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3838 //===---------------------------------------------------------------------===//
3839 // SSE2 - Move Quadword
3840 //===---------------------------------------------------------------------===//
3842 //===---------------------------------------------------------------------===//
3843 // Move Quadword Int to Packed Quadword Int
3845 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3846 "vmovq\t{$src, $dst|$dst, $src}",
3848 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3849 VEX, Requires<[HasAVX]>;
3850 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3851 "movq\t{$src, $dst|$dst, $src}",
3853 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3854 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3856 //===---------------------------------------------------------------------===//
3857 // Move Packed Quadword Int to Quadword Int
3859 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3860 "movq\t{$src, $dst|$dst, $src}",
3861 [(store (i64 (vector_extract (v2i64 VR128:$src),
3862 (iPTR 0))), addr:$dst)]>, VEX;
3863 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3864 "movq\t{$src, $dst|$dst, $src}",
3865 [(store (i64 (vector_extract (v2i64 VR128:$src),
3866 (iPTR 0))), addr:$dst)]>;
3868 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3869 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3871 //===---------------------------------------------------------------------===//
3872 // Store / copy lower 64-bits of a XMM register.
3874 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3875 "movq\t{$src, $dst|$dst, $src}",
3876 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3877 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3878 "movq\t{$src, $dst|$dst, $src}",
3879 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3881 let AddedComplexity = 20 in
3882 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3883 "vmovq\t{$src, $dst|$dst, $src}",
3885 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3886 (loadi64 addr:$src))))))]>,
3887 XS, VEX, Requires<[HasAVX]>;
3889 let AddedComplexity = 20 in {
3890 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3891 "movq\t{$src, $dst|$dst, $src}",
3893 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3894 (loadi64 addr:$src))))))]>,
3895 XS, Requires<[HasSSE2]>;
3897 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3898 (MOVZQI2PQIrm addr:$src)>;
3899 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3900 (MOVZQI2PQIrm addr:$src)>;
3901 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3904 //===---------------------------------------------------------------------===//
3905 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3906 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3908 let AddedComplexity = 15 in
3909 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3910 "vmovq\t{$src, $dst|$dst, $src}",
3911 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3912 XS, VEX, Requires<[HasAVX]>;
3913 let AddedComplexity = 15 in
3914 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3915 "movq\t{$src, $dst|$dst, $src}",
3916 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3917 XS, Requires<[HasSSE2]>;
3919 let AddedComplexity = 20 in
3920 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3921 "vmovq\t{$src, $dst|$dst, $src}",
3922 [(set VR128:$dst, (v2i64 (X86vzmovl
3923 (loadv2i64 addr:$src))))]>,
3924 XS, VEX, Requires<[HasAVX]>;
3925 let AddedComplexity = 20 in {
3926 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3927 "movq\t{$src, $dst|$dst, $src}",
3928 [(set VR128:$dst, (v2i64 (X86vzmovl
3929 (loadv2i64 addr:$src))))]>,
3930 XS, Requires<[HasSSE2]>;
3932 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3933 (MOVZPQILo2PQIrm addr:$src)>;
3936 // Instructions to match in the assembler
3937 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3938 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3939 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3940 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3941 // Recognize "movd" with GR64 destination, but encode as a "movq"
3942 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3943 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3945 // Instructions for the disassembler
3946 // xr = XMM register
3949 let Predicates = [HasAVX] in
3950 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3951 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3952 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3953 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3955 //===---------------------------------------------------------------------===//
3956 // SSE2 - Misc Instructions
3957 //===---------------------------------------------------------------------===//
3960 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3961 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3962 TB, Requires<[HasSSE2]>;
3964 // Load, store, and memory fence
3965 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3966 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3967 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3968 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3969 def : Pat<(X86LFence), (LFENCE)>;
3970 def : Pat<(X86MFence), (MFENCE)>;
3973 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3974 // was introduced with SSE2, it's backward compatible.
3975 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3977 // Alias instructions that map zero vector to pxor / xorp* for sse.
3978 // We set canFoldAsLoad because this can be converted to a constant-pool
3979 // load of an all-ones value if folding it would be beneficial.
3980 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3981 // JIT implementation, it does not expand the instructions below like
3982 // X86MCInstLower does.
3983 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3984 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3985 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3986 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3987 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3988 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3989 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3990 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3992 //===---------------------------------------------------------------------===//
3993 // SSE3 - Conversion Instructions
3994 //===---------------------------------------------------------------------===//
3996 // Convert Packed Double FP to Packed DW Integers
3997 let Predicates = [HasAVX] in {
3998 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3999 // register, but the same isn't true when using memory operands instead.
4000 // Provide other assembly rr and rm forms to address this explicitly.
4001 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4002 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4003 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4004 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4007 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4008 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4009 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4010 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4013 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4014 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4015 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4016 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4019 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4020 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4021 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4022 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4024 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4025 (VCVTPD2DQYrr VR256:$src)>;
4026 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4027 (VCVTPD2DQYrm addr:$src)>;
4029 // Convert Packed DW Integers to Packed Double FP
4030 let Predicates = [HasAVX] in {
4031 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4032 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4033 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4034 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4035 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4036 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4037 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4038 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4041 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4042 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4043 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4044 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4046 // AVX 256-bit register conversion intrinsics
4047 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4048 (VCVTDQ2PDYrr VR128:$src)>;
4049 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4050 (VCVTDQ2PDYrm addr:$src)>;
4052 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4053 (VCVTPD2DQYrr VR256:$src)>;
4054 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4055 (VCVTPD2DQYrm addr:$src)>;
4057 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4058 (VCVTDQ2PDYrr VR128:$src)>;
4059 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4060 (VCVTDQ2PDYrm addr:$src)>;
4062 //===---------------------------------------------------------------------===//
4063 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4064 //===---------------------------------------------------------------------===//
4065 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4066 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4067 X86MemOperand x86memop> {
4068 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4070 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4071 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4072 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4073 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4076 let Predicates = [HasAVX] in {
4077 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4078 v4f32, VR128, memopv4f32, f128mem>, VEX;
4079 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4080 v4f32, VR128, memopv4f32, f128mem>, VEX;
4081 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4082 v8f32, VR256, memopv8f32, f256mem>, VEX;
4083 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4084 v8f32, VR256, memopv8f32, f256mem>, VEX;
4086 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4087 memopv4f32, f128mem>;
4088 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4089 memopv4f32, f128mem>;
4091 let Predicates = [HasSSE3] in {
4092 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4093 (MOVSHDUPrr VR128:$src)>;
4094 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4095 (MOVSHDUPrm addr:$src)>;
4096 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4097 (MOVSLDUPrr VR128:$src)>;
4098 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4099 (MOVSLDUPrm addr:$src)>;
4102 let Predicates = [HasAVX] in {
4103 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4104 (VMOVSHDUPrr VR128:$src)>;
4105 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4106 (VMOVSHDUPrm addr:$src)>;
4107 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4108 (VMOVSLDUPrr VR128:$src)>;
4109 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4110 (VMOVSLDUPrm addr:$src)>;
4111 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4112 (VMOVSHDUPYrr VR256:$src)>;
4113 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4114 (VMOVSHDUPYrm addr:$src)>;
4115 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4116 (VMOVSLDUPYrr VR256:$src)>;
4117 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4118 (VMOVSLDUPYrm addr:$src)>;
4121 //===---------------------------------------------------------------------===//
4122 // SSE3 - Replicate Double FP - MOVDDUP
4123 //===---------------------------------------------------------------------===//
4125 multiclass sse3_replicate_dfp<string OpcodeStr> {
4126 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4127 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4128 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4129 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4132 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4136 // FIXME: Merge with above classe when there're patterns for the ymm version
4137 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4138 let Predicates = [HasAVX] in {
4139 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4140 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4142 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4143 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4148 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4149 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4150 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4152 let Predicates = [HasSSE3] in {
4153 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4155 (MOVDDUPrm addr:$src)>;
4156 let AddedComplexity = 5 in {
4157 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4158 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4159 (MOVDDUPrm addr:$src)>;
4160 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4161 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4162 (MOVDDUPrm addr:$src)>;
4164 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4165 (MOVDDUPrm addr:$src)>;
4166 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4167 (MOVDDUPrm addr:$src)>;
4168 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4169 (MOVDDUPrm addr:$src)>;
4170 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4171 (MOVDDUPrm addr:$src)>;
4172 def : Pat<(X86Movddup (bc_v2f64
4173 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4174 (MOVDDUPrm addr:$src)>;
4177 let Predicates = [HasAVX] in {
4178 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4180 (VMOVDDUPrm addr:$src)>;
4181 let AddedComplexity = 5 in {
4182 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4183 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4184 (VMOVDDUPrm addr:$src)>;
4185 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4186 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4187 (VMOVDDUPrm addr:$src)>;
4189 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4190 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4191 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4192 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4193 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4194 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4195 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4196 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4197 def : Pat<(X86Movddup (bc_v2f64
4198 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4199 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4202 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4203 (VMOVDDUPYrm addr:$src)>;
4204 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4205 (VMOVDDUPYrm addr:$src)>;
4206 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4207 (VMOVDDUPYrm addr:$src)>;
4208 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4209 (VMOVDDUPYrm addr:$src)>;
4210 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4211 (VMOVDDUPYrr VR256:$src)>;
4212 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4213 (VMOVDDUPYrr VR256:$src)>;
4216 //===---------------------------------------------------------------------===//
4217 // SSE3 - Move Unaligned Integer
4218 //===---------------------------------------------------------------------===//
4220 let Predicates = [HasAVX] in {
4221 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4222 "vlddqu\t{$src, $dst|$dst, $src}",
4223 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4224 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4225 "vlddqu\t{$src, $dst|$dst, $src}",
4226 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4228 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4229 "lddqu\t{$src, $dst|$dst, $src}",
4230 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4232 //===---------------------------------------------------------------------===//
4233 // SSE3 - Arithmetic
4234 //===---------------------------------------------------------------------===//
4236 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4237 X86MemOperand x86memop, bit Is2Addr = 1> {
4238 def rr : I<0xD0, MRMSrcReg,
4239 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4243 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4244 def rm : I<0xD0, MRMSrcMem,
4245 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4247 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4249 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4252 let Predicates = [HasAVX],
4253 ExeDomain = SSEPackedDouble in {
4254 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4255 f128mem, 0>, TB, XD, VEX_4V;
4256 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4257 f128mem, 0>, TB, OpSize, VEX_4V;
4258 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4259 f256mem, 0>, TB, XD, VEX_4V;
4260 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4261 f256mem, 0>, TB, OpSize, VEX_4V;
4263 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4264 ExeDomain = SSEPackedDouble in {
4265 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4267 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4268 f128mem>, TB, OpSize;
4271 //===---------------------------------------------------------------------===//
4272 // SSE3 Instructions
4273 //===---------------------------------------------------------------------===//
4276 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4277 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4278 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4282 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4284 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4286 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4287 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4288 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4290 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4291 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4292 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4296 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4298 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4302 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4305 let Predicates = [HasAVX] in {
4306 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4307 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4308 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4309 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4310 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4311 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4312 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4313 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4314 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4315 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4316 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4317 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4318 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4319 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4320 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4321 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4324 let Constraints = "$src1 = $dst" in {
4325 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4326 int_x86_sse3_hadd_ps>;
4327 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4328 int_x86_sse3_hadd_pd>;
4329 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4330 int_x86_sse3_hsub_ps>;
4331 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4332 int_x86_sse3_hsub_pd>;
4335 //===---------------------------------------------------------------------===//
4336 // SSSE3 - Packed Absolute Instructions
4337 //===---------------------------------------------------------------------===//
4340 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4341 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4342 PatFrag mem_frag128, Intrinsic IntId128> {
4343 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4346 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4349 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4351 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4354 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4357 let Predicates = [HasAVX] in {
4358 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4359 int_x86_ssse3_pabs_b_128>, VEX;
4360 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4361 int_x86_ssse3_pabs_w_128>, VEX;
4362 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4363 int_x86_ssse3_pabs_d_128>, VEX;
4366 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4367 int_x86_ssse3_pabs_b_128>;
4368 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4369 int_x86_ssse3_pabs_w_128>;
4370 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4371 int_x86_ssse3_pabs_d_128>;
4373 //===---------------------------------------------------------------------===//
4374 // SSSE3 - Packed Binary Operator Instructions
4375 //===---------------------------------------------------------------------===//
4377 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4378 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4379 PatFrag mem_frag128, Intrinsic IntId128,
4381 let isCommutable = 1 in
4382 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4383 (ins VR128:$src1, VR128:$src2),
4385 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4387 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4389 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4390 (ins VR128:$src1, i128mem:$src2),
4392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4395 (IntId128 VR128:$src1,
4396 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4399 let Predicates = [HasAVX] in {
4400 let isCommutable = 0 in {
4401 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4402 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4403 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4404 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4405 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4406 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4407 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4408 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4409 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4410 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4411 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4412 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4413 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4414 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4415 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4416 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4417 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4418 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4419 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4420 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4421 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4422 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4424 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4425 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4428 // None of these have i8 immediate fields.
4429 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4430 let isCommutable = 0 in {
4431 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4432 int_x86_ssse3_phadd_w_128>;
4433 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4434 int_x86_ssse3_phadd_d_128>;
4435 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4436 int_x86_ssse3_phadd_sw_128>;
4437 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4438 int_x86_ssse3_phsub_w_128>;
4439 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4440 int_x86_ssse3_phsub_d_128>;
4441 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4442 int_x86_ssse3_phsub_sw_128>;
4443 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4444 int_x86_ssse3_pmadd_ub_sw_128>;
4445 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4446 int_x86_ssse3_pshuf_b_128>;
4447 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4448 int_x86_ssse3_psign_b_128>;
4449 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4450 int_x86_ssse3_psign_w_128>;
4451 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4452 int_x86_ssse3_psign_d_128>;
4454 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4455 int_x86_ssse3_pmul_hr_sw_128>;
4458 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4459 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
4460 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4461 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
4463 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4464 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4465 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4466 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4467 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4468 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4470 //===---------------------------------------------------------------------===//
4471 // SSSE3 - Packed Align Instruction Patterns
4472 //===---------------------------------------------------------------------===//
4474 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4475 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4476 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4478 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4480 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4482 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4483 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4485 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4487 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4491 let Predicates = [HasAVX] in
4492 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4493 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4494 defm PALIGN : ssse3_palign<"palignr">;
4496 let Predicates = [HasSSSE3] in {
4497 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4498 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4499 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4500 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4501 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4502 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4503 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4504 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4507 let Predicates = [HasAVX] in {
4508 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4509 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4510 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4511 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4512 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4513 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4514 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4515 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4518 //===---------------------------------------------------------------------===//
4519 // SSSE3 Misc Instructions
4520 //===---------------------------------------------------------------------===//
4522 // Thread synchronization
4523 let usesCustomInserter = 1 in {
4524 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4525 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4526 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4527 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4530 let Uses = [EAX, ECX, EDX] in
4531 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4532 Requires<[HasSSE3]>;
4533 let Uses = [ECX, EAX] in
4534 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4535 Requires<[HasSSE3]>;
4537 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4538 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4540 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4541 Requires<[In32BitMode]>;
4542 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4543 Requires<[In64BitMode]>;
4545 // extload f32 -> f64. This matches load+fextend because we have a hack in
4546 // the isel (PreprocessForFPConvert) that can introduce loads after dag
4548 // Since these loads aren't folded into the fextend, we have to match it
4550 let Predicates = [HasSSE2] in
4551 def : Pat<(fextend (loadf32 addr:$src)),
4552 (CVTSS2SDrm addr:$src)>;
4554 // Splat v2f64 / v2i64
4555 let AddedComplexity = 10 in {
4556 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4557 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4560 let AddedComplexity = 20 in {
4561 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
4562 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
4563 (MOVLPSrm VR128:$src1, addr:$src2)>;
4564 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
4565 (MOVLPDrm VR128:$src1, addr:$src2)>;
4566 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
4567 (MOVLPSrm VR128:$src1, addr:$src2)>;
4568 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
4569 (MOVLPDrm VR128:$src1, addr:$src2)>;
4572 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
4573 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4574 (MOVLPSmr addr:$src1, VR128:$src2)>;
4575 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4576 (MOVLPDmr addr:$src1, VR128:$src2)>;
4577 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
4579 (MOVLPSmr addr:$src1, VR128:$src2)>;
4580 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4581 (MOVLPDmr addr:$src1, VR128:$src2)>;
4583 // Set lowest element and zero upper elements.
4584 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4585 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4587 // Use movaps / movups for SSE integer load / store (one byte shorter).
4588 // The instructions selected below are then converted to MOVDQA/MOVDQU
4589 // during the SSE domain pass.
4590 let Predicates = [HasSSE1] in {
4591 def : Pat<(alignedloadv4i32 addr:$src),
4592 (MOVAPSrm addr:$src)>;
4593 def : Pat<(loadv4i32 addr:$src),
4594 (MOVUPSrm addr:$src)>;
4595 def : Pat<(alignedloadv2i64 addr:$src),
4596 (MOVAPSrm addr:$src)>;
4597 def : Pat<(loadv2i64 addr:$src),
4598 (MOVUPSrm addr:$src)>;
4600 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4601 (MOVAPSmr addr:$dst, VR128:$src)>;
4602 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4603 (MOVAPSmr addr:$dst, VR128:$src)>;
4604 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4605 (MOVAPSmr addr:$dst, VR128:$src)>;
4606 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4607 (MOVAPSmr addr:$dst, VR128:$src)>;
4608 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4609 (MOVUPSmr addr:$dst, VR128:$src)>;
4610 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4611 (MOVUPSmr addr:$dst, VR128:$src)>;
4612 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4613 (MOVUPSmr addr:$dst, VR128:$src)>;
4614 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4615 (MOVUPSmr addr:$dst, VR128:$src)>;
4618 // Use vmovaps/vmovups for AVX integer load/store.
4619 let Predicates = [HasAVX] in {
4620 // 128-bit load/store
4621 def : Pat<(alignedloadv4i32 addr:$src),
4622 (VMOVAPSrm addr:$src)>;
4623 def : Pat<(loadv4i32 addr:$src),
4624 (VMOVUPSrm addr:$src)>;
4625 def : Pat<(alignedloadv2i64 addr:$src),
4626 (VMOVAPSrm addr:$src)>;
4627 def : Pat<(loadv2i64 addr:$src),
4628 (VMOVUPSrm addr:$src)>;
4630 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4631 (VMOVAPSmr addr:$dst, VR128:$src)>;
4632 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4633 (VMOVAPSmr addr:$dst, VR128:$src)>;
4634 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4635 (VMOVAPSmr addr:$dst, VR128:$src)>;
4636 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4637 (VMOVAPSmr addr:$dst, VR128:$src)>;
4638 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4639 (VMOVUPSmr addr:$dst, VR128:$src)>;
4640 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4641 (VMOVUPSmr addr:$dst, VR128:$src)>;
4642 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4643 (VMOVUPSmr addr:$dst, VR128:$src)>;
4644 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4645 (VMOVUPSmr addr:$dst, VR128:$src)>;
4647 // 256-bit load/store
4648 def : Pat<(alignedloadv4i64 addr:$src),
4649 (VMOVAPSYrm addr:$src)>;
4650 def : Pat<(loadv4i64 addr:$src),
4651 (VMOVUPSYrm addr:$src)>;
4652 def : Pat<(alignedloadv8i32 addr:$src),
4653 (VMOVAPSYrm addr:$src)>;
4654 def : Pat<(loadv8i32 addr:$src),
4655 (VMOVUPSYrm addr:$src)>;
4656 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4657 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4658 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4659 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4660 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4661 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4662 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4663 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4664 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4665 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4666 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4667 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4668 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4669 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4670 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4671 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4674 //===----------------------------------------------------------------------===//
4675 // SSE4.1 - Packed Move with Sign/Zero Extend
4676 //===----------------------------------------------------------------------===//
4678 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4679 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4680 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4681 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4683 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4684 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4686 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4690 let Predicates = [HasAVX] in {
4691 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4693 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4695 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4697 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4699 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4701 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4705 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4706 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4707 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4708 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4709 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4710 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4712 // Common patterns involving scalar load.
4713 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4714 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4715 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4716 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4718 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4719 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4720 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4721 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4723 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4724 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4725 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4726 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4728 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4729 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4730 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4731 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4733 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4734 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4735 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4736 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4738 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4739 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4740 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4741 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4744 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4745 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4747 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4749 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4752 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4756 let Predicates = [HasAVX] in {
4757 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4759 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4761 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4763 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4767 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4768 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4769 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4770 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4772 // Common patterns involving scalar load
4773 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4774 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4775 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4776 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4778 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4779 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4780 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4781 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4784 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4785 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4786 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4787 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4789 // Expecting a i16 load any extended to i32 value.
4790 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4792 [(set VR128:$dst, (IntId (bitconvert
4793 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4797 let Predicates = [HasAVX] in {
4798 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4800 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4803 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4804 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4806 // Common patterns involving scalar load
4807 def : Pat<(int_x86_sse41_pmovsxbq
4808 (bitconvert (v4i32 (X86vzmovl
4809 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4810 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4812 def : Pat<(int_x86_sse41_pmovzxbq
4813 (bitconvert (v4i32 (X86vzmovl
4814 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4815 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4817 //===----------------------------------------------------------------------===//
4818 // SSE4.1 - Extract Instructions
4819 //===----------------------------------------------------------------------===//
4821 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4822 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4823 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4824 (ins VR128:$src1, i32i8imm:$src2),
4825 !strconcat(OpcodeStr,
4826 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4827 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4829 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4830 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4831 !strconcat(OpcodeStr,
4832 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4835 // There's an AssertZext in the way of writing the store pattern
4836 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4839 let Predicates = [HasAVX] in {
4840 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4841 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4842 (ins VR128:$src1, i32i8imm:$src2),
4843 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4846 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4849 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4850 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4851 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4852 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4853 !strconcat(OpcodeStr,
4854 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4857 // There's an AssertZext in the way of writing the store pattern
4858 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4861 let Predicates = [HasAVX] in
4862 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4864 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4867 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4868 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4869 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4870 (ins VR128:$src1, i32i8imm:$src2),
4871 !strconcat(OpcodeStr,
4872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4874 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4875 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4876 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4877 !strconcat(OpcodeStr,
4878 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4879 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4880 addr:$dst)]>, OpSize;
4883 let Predicates = [HasAVX] in
4884 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4886 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4888 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4889 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4890 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4891 (ins VR128:$src1, i32i8imm:$src2),
4892 !strconcat(OpcodeStr,
4893 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4895 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4896 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4897 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4898 !strconcat(OpcodeStr,
4899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4900 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4901 addr:$dst)]>, OpSize, REX_W;
4904 let Predicates = [HasAVX] in
4905 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4907 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4909 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4911 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4912 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4913 (ins VR128:$src1, i32i8imm:$src2),
4914 !strconcat(OpcodeStr,
4915 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4917 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4919 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4920 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4921 !strconcat(OpcodeStr,
4922 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4923 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4924 addr:$dst)]>, OpSize;
4927 let Predicates = [HasAVX] in {
4928 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4929 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4930 (ins VR128:$src1, i32i8imm:$src2),
4931 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4934 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4936 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4937 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4940 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4941 Requires<[HasSSE41]>;
4943 //===----------------------------------------------------------------------===//
4944 // SSE4.1 - Insert Instructions
4945 //===----------------------------------------------------------------------===//
4947 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4948 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4949 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4951 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4953 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4955 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4956 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4957 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4959 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4961 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4963 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4964 imm:$src3))]>, OpSize;
4967 let Predicates = [HasAVX] in
4968 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4969 let Constraints = "$src1 = $dst" in
4970 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4972 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4973 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4974 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4976 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4978 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4980 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4982 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4983 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4985 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4987 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4989 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4990 imm:$src3)))]>, OpSize;
4993 let Predicates = [HasAVX] in
4994 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4995 let Constraints = "$src1 = $dst" in
4996 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4998 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4999 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5000 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5002 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5004 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5006 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5008 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5009 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5011 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5013 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5015 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5016 imm:$src3)))]>, OpSize;
5019 let Predicates = [HasAVX] in
5020 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5021 let Constraints = "$src1 = $dst" in
5022 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5024 // insertps has a few different modes, there's the first two here below which
5025 // are optimized inserts that won't zero arbitrary elements in the destination
5026 // vector. The next one matches the intrinsic and could zero arbitrary elements
5027 // in the target vector.
5028 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5029 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5030 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5032 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5034 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5036 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5038 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5039 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5041 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5043 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5045 (X86insrtps VR128:$src1,
5046 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5047 imm:$src3))]>, OpSize;
5050 let Constraints = "$src1 = $dst" in
5051 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5052 let Predicates = [HasAVX] in
5053 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5055 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5056 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5058 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5059 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5060 Requires<[HasSSE41]>;
5062 //===----------------------------------------------------------------------===//
5063 // SSE4.1 - Round Instructions
5064 //===----------------------------------------------------------------------===//
5066 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5067 X86MemOperand x86memop, RegisterClass RC,
5068 PatFrag mem_frag32, PatFrag mem_frag64,
5069 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5070 // Intrinsic operation, reg.
5071 // Vector intrinsic operation, reg
5072 def PSr : SS4AIi8<opcps, MRMSrcReg,
5073 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5074 !strconcat(OpcodeStr,
5075 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5076 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5079 // Vector intrinsic operation, mem
5080 def PSm : Ii8<opcps, MRMSrcMem,
5081 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5082 !strconcat(OpcodeStr,
5083 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5085 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5087 Requires<[HasSSE41]>;
5089 // Vector intrinsic operation, reg
5090 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5091 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5092 !strconcat(OpcodeStr,
5093 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5094 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5097 // Vector intrinsic operation, mem
5098 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5099 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5100 !strconcat(OpcodeStr,
5101 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5103 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5107 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5108 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5109 // Intrinsic operation, reg.
5110 // Vector intrinsic operation, reg
5111 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5112 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5113 !strconcat(OpcodeStr,
5114 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5117 // Vector intrinsic operation, mem
5118 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5119 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5120 !strconcat(OpcodeStr,
5121 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5122 []>, TA, OpSize, Requires<[HasSSE41]>;
5124 // Vector intrinsic operation, reg
5125 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5126 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5127 !strconcat(OpcodeStr,
5128 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5131 // Vector intrinsic operation, mem
5132 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5133 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5134 !strconcat(OpcodeStr,
5135 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5139 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5142 Intrinsic F64Int, bit Is2Addr = 1> {
5143 // Intrinsic operation, reg.
5144 def SSr : SS4AIi8<opcss, MRMSrcReg,
5145 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5147 !strconcat(OpcodeStr,
5148 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5149 !strconcat(OpcodeStr,
5150 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5151 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5154 // Intrinsic operation, mem.
5155 def SSm : SS4AIi8<opcss, MRMSrcMem,
5156 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5158 !strconcat(OpcodeStr,
5159 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5160 !strconcat(OpcodeStr,
5161 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5163 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5166 // Intrinsic operation, reg.
5167 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5168 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5170 !strconcat(OpcodeStr,
5171 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5172 !strconcat(OpcodeStr,
5173 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5174 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5177 // Intrinsic operation, mem.
5178 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5179 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5181 !strconcat(OpcodeStr,
5182 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5183 !strconcat(OpcodeStr,
5184 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5186 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5190 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5192 // Intrinsic operation, reg.
5193 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5194 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5195 !strconcat(OpcodeStr,
5196 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5199 // Intrinsic operation, mem.
5200 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5201 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5202 !strconcat(OpcodeStr,
5203 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5206 // Intrinsic operation, reg.
5207 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5208 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5209 !strconcat(OpcodeStr,
5210 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5213 // Intrinsic operation, mem.
5214 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5215 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5216 !strconcat(OpcodeStr,
5217 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5221 // FP round - roundss, roundps, roundsd, roundpd
5222 let Predicates = [HasAVX] in {
5224 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5225 memopv4f32, memopv2f64,
5226 int_x86_sse41_round_ps,
5227 int_x86_sse41_round_pd>, VEX;
5228 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5229 memopv8f32, memopv4f64,
5230 int_x86_avx_round_ps_256,
5231 int_x86_avx_round_pd_256>, VEX;
5232 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5233 int_x86_sse41_round_ss,
5234 int_x86_sse41_round_sd, 0>, VEX_4V;
5236 // Instructions for the assembler
5237 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5239 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5241 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5244 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5245 memopv4f32, memopv2f64,
5246 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5247 let Constraints = "$src1 = $dst" in
5248 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5249 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5251 //===----------------------------------------------------------------------===//
5252 // SSE4.1 - Packed Bit Test
5253 //===----------------------------------------------------------------------===//
5255 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5256 // the intel intrinsic that corresponds to this.
5257 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5258 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5259 "vptest\t{$src2, $src1|$src1, $src2}",
5260 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5262 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5263 "vptest\t{$src2, $src1|$src1, $src2}",
5264 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5267 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5268 "vptest\t{$src2, $src1|$src1, $src2}",
5269 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5271 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5272 "vptest\t{$src2, $src1|$src1, $src2}",
5273 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5277 let Defs = [EFLAGS] in {
5278 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5279 "ptest \t{$src2, $src1|$src1, $src2}",
5280 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5282 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5283 "ptest \t{$src2, $src1|$src1, $src2}",
5284 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5288 // The bit test instructions below are AVX only
5289 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5290 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5291 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5292 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5293 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5294 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5295 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5296 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5300 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5301 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5302 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5303 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5304 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5307 //===----------------------------------------------------------------------===//
5308 // SSE4.1 - Misc Instructions
5309 //===----------------------------------------------------------------------===//
5311 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5312 "popcnt{w}\t{$src, $dst|$dst, $src}",
5313 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5314 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5315 "popcnt{w}\t{$src, $dst|$dst, $src}",
5316 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5318 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5319 "popcnt{l}\t{$src, $dst|$dst, $src}",
5320 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5321 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5322 "popcnt{l}\t{$src, $dst|$dst, $src}",
5323 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5325 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5326 "popcnt{q}\t{$src, $dst|$dst, $src}",
5327 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5328 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5329 "popcnt{q}\t{$src, $dst|$dst, $src}",
5330 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5334 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5335 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5336 Intrinsic IntId128> {
5337 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5339 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5340 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5341 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5343 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5346 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5349 let Predicates = [HasAVX] in
5350 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5351 int_x86_sse41_phminposuw>, VEX;
5352 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5353 int_x86_sse41_phminposuw>;
5355 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5356 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5357 Intrinsic IntId128, bit Is2Addr = 1> {
5358 let isCommutable = 1 in
5359 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5360 (ins VR128:$src1, VR128:$src2),
5362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5364 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5365 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5366 (ins VR128:$src1, i128mem:$src2),
5368 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5371 (IntId128 VR128:$src1,
5372 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5375 let Predicates = [HasAVX] in {
5376 let isCommutable = 0 in
5377 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5379 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5381 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5383 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5385 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5387 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5389 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5391 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5393 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5395 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5397 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5400 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5401 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5402 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5403 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5406 let Constraints = "$src1 = $dst" in {
5407 let isCommutable = 0 in
5408 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5409 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5410 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5411 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5412 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5413 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5414 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5415 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5416 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5417 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5418 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5421 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5422 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5423 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5424 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5426 /// SS48I_binop_rm - Simple SSE41 binary operator.
5427 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5428 ValueType OpVT, bit Is2Addr = 1> {
5429 let isCommutable = 1 in
5430 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5431 (ins VR128:$src1, VR128:$src2),
5433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5435 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5437 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5438 (ins VR128:$src1, i128mem:$src2),
5440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5441 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5442 [(set VR128:$dst, (OpNode VR128:$src1,
5443 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5447 let Predicates = [HasAVX] in
5448 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5449 let Constraints = "$src1 = $dst" in
5450 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5452 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5453 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5454 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5455 X86MemOperand x86memop, bit Is2Addr = 1> {
5456 let isCommutable = 1 in
5457 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5458 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5460 !strconcat(OpcodeStr,
5461 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5462 !strconcat(OpcodeStr,
5463 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5464 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5466 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5467 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5469 !strconcat(OpcodeStr,
5470 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5471 !strconcat(OpcodeStr,
5472 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5475 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5479 let Predicates = [HasAVX] in {
5480 let isCommutable = 0 in {
5481 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5482 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5483 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5484 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5485 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5486 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5487 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5488 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5489 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5490 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5491 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5492 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5494 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5495 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5496 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5497 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5498 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5499 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5502 let Constraints = "$src1 = $dst" in {
5503 let isCommutable = 0 in {
5504 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5505 VR128, memopv16i8, i128mem>;
5506 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5507 VR128, memopv16i8, i128mem>;
5508 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5509 VR128, memopv16i8, i128mem>;
5510 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5511 VR128, memopv16i8, i128mem>;
5513 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5514 VR128, memopv16i8, i128mem>;
5515 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5516 VR128, memopv16i8, i128mem>;
5519 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5520 let Predicates = [HasAVX] in {
5521 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5522 RegisterClass RC, X86MemOperand x86memop,
5523 PatFrag mem_frag, Intrinsic IntId> {
5524 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5525 (ins RC:$src1, RC:$src2, RC:$src3),
5526 !strconcat(OpcodeStr,
5527 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5528 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5529 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5531 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5532 (ins RC:$src1, x86memop:$src2, RC:$src3),
5533 !strconcat(OpcodeStr,
5534 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5536 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5538 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5542 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5543 memopv16i8, int_x86_sse41_blendvpd>;
5544 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5545 memopv16i8, int_x86_sse41_blendvps>;
5546 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5547 memopv16i8, int_x86_sse41_pblendvb>;
5548 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5549 memopv32i8, int_x86_avx_blendv_pd_256>;
5550 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5551 memopv32i8, int_x86_avx_blendv_ps_256>;
5553 /// SS41I_ternary_int - SSE 4.1 ternary operator
5554 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5555 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5556 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5557 (ins VR128:$src1, VR128:$src2),
5558 !strconcat(OpcodeStr,
5559 "\t{$src2, $dst|$dst, $src2}"),
5560 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5563 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5564 (ins VR128:$src1, i128mem:$src2),
5565 !strconcat(OpcodeStr,
5566 "\t{$src2, $dst|$dst, $src2}"),
5569 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5573 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5574 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5575 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5577 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
5578 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5580 let Predicates = [HasAVX] in
5581 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5582 "vmovntdqa\t{$src, $dst|$dst, $src}",
5583 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5585 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5586 "movntdqa\t{$src, $dst|$dst, $src}",
5587 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5590 //===----------------------------------------------------------------------===//
5591 // SSE4.2 - Compare Instructions
5592 //===----------------------------------------------------------------------===//
5594 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5595 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5596 Intrinsic IntId128, bit Is2Addr = 1> {
5597 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5598 (ins VR128:$src1, VR128:$src2),
5600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5602 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5604 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5605 (ins VR128:$src1, i128mem:$src2),
5607 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5608 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5610 (IntId128 VR128:$src1,
5611 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5614 let Predicates = [HasAVX] in {
5615 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5618 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5619 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
5620 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5621 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
5624 let Constraints = "$src1 = $dst" in
5625 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5627 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5628 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5629 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5630 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5632 //===----------------------------------------------------------------------===//
5633 // SSE4.2 - String/text Processing Instructions
5634 //===----------------------------------------------------------------------===//
5636 // Packed Compare Implicit Length Strings, Return Mask
5637 multiclass pseudo_pcmpistrm<string asm> {
5638 def REG : PseudoI<(outs VR128:$dst),
5639 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5640 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5642 def MEM : PseudoI<(outs VR128:$dst),
5643 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5644 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5645 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5648 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5649 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5650 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5653 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5654 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5655 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5656 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5657 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5658 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5659 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5662 let Defs = [XMM0, EFLAGS] in {
5663 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5664 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5665 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5666 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5667 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5668 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5671 // Packed Compare Explicit Length Strings, Return Mask
5672 multiclass pseudo_pcmpestrm<string asm> {
5673 def REG : PseudoI<(outs VR128:$dst),
5674 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5675 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5676 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5677 def MEM : PseudoI<(outs VR128:$dst),
5678 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5679 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5680 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5683 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5684 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5685 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5688 let Predicates = [HasAVX],
5689 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5690 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5691 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5692 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5693 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5694 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5695 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5698 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5699 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5700 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5701 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5702 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5703 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5704 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5707 // Packed Compare Implicit Length Strings, Return Index
5708 let Defs = [ECX, EFLAGS] in {
5709 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5710 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5711 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5712 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5713 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5714 (implicit EFLAGS)]>, OpSize;
5715 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5716 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5717 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5718 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5719 (implicit EFLAGS)]>, OpSize;
5723 let Predicates = [HasAVX] in {
5724 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5726 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5728 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5730 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5732 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5734 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5738 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5739 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5740 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5741 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5742 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5743 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5745 // Packed Compare Explicit Length Strings, Return Index
5746 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5747 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5748 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5749 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5750 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5751 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5752 (implicit EFLAGS)]>, OpSize;
5753 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5754 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5755 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5757 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5758 (implicit EFLAGS)]>, OpSize;
5762 let Predicates = [HasAVX] in {
5763 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5765 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5767 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5769 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5771 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5773 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5777 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5778 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5779 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5780 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5781 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5782 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5784 //===----------------------------------------------------------------------===//
5785 // SSE4.2 - CRC Instructions
5786 //===----------------------------------------------------------------------===//
5788 // No CRC instructions have AVX equivalents
5790 // crc intrinsic instruction
5791 // This set of instructions are only rm, the only difference is the size
5793 let Constraints = "$src1 = $dst" in {
5794 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5795 (ins GR32:$src1, i8mem:$src2),
5796 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5798 (int_x86_sse42_crc32_32_8 GR32:$src1,
5799 (load addr:$src2)))]>;
5800 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5801 (ins GR32:$src1, GR8:$src2),
5802 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5804 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5805 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5806 (ins GR32:$src1, i16mem:$src2),
5807 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5809 (int_x86_sse42_crc32_32_16 GR32:$src1,
5810 (load addr:$src2)))]>,
5812 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5813 (ins GR32:$src1, GR16:$src2),
5814 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5816 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5818 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5819 (ins GR32:$src1, i32mem:$src2),
5820 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5822 (int_x86_sse42_crc32_32_32 GR32:$src1,
5823 (load addr:$src2)))]>;
5824 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5825 (ins GR32:$src1, GR32:$src2),
5826 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5828 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5829 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5830 (ins GR64:$src1, i8mem:$src2),
5831 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5833 (int_x86_sse42_crc32_64_8 GR64:$src1,
5834 (load addr:$src2)))]>,
5836 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5837 (ins GR64:$src1, GR8:$src2),
5838 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5840 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5842 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5843 (ins GR64:$src1, i64mem:$src2),
5844 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5846 (int_x86_sse42_crc32_64_64 GR64:$src1,
5847 (load addr:$src2)))]>,
5849 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5850 (ins GR64:$src1, GR64:$src2),
5851 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5853 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5857 //===----------------------------------------------------------------------===//
5858 // AES-NI Instructions
5859 //===----------------------------------------------------------------------===//
5861 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5862 Intrinsic IntId128, bit Is2Addr = 1> {
5863 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5864 (ins VR128:$src1, VR128:$src2),
5866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5868 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5870 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5871 (ins VR128:$src1, i128mem:$src2),
5873 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5876 (IntId128 VR128:$src1,
5877 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5880 // Perform One Round of an AES Encryption/Decryption Flow
5881 let Predicates = [HasAVX, HasAES] in {
5882 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5883 int_x86_aesni_aesenc, 0>, VEX_4V;
5884 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5885 int_x86_aesni_aesenclast, 0>, VEX_4V;
5886 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5887 int_x86_aesni_aesdec, 0>, VEX_4V;
5888 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5889 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5892 let Constraints = "$src1 = $dst" in {
5893 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5894 int_x86_aesni_aesenc>;
5895 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5896 int_x86_aesni_aesenclast>;
5897 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5898 int_x86_aesni_aesdec>;
5899 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5900 int_x86_aesni_aesdeclast>;
5903 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5904 (AESENCrr VR128:$src1, VR128:$src2)>;
5905 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5906 (AESENCrm VR128:$src1, addr:$src2)>;
5907 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5908 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5909 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5910 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5911 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5912 (AESDECrr VR128:$src1, VR128:$src2)>;
5913 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5914 (AESDECrm VR128:$src1, addr:$src2)>;
5915 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5916 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5917 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5918 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5920 // Perform the AES InvMixColumn Transformation
5921 let Predicates = [HasAVX, HasAES] in {
5922 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5924 "vaesimc\t{$src1, $dst|$dst, $src1}",
5926 (int_x86_aesni_aesimc VR128:$src1))]>,
5928 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5929 (ins i128mem:$src1),
5930 "vaesimc\t{$src1, $dst|$dst, $src1}",
5932 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5935 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5937 "aesimc\t{$src1, $dst|$dst, $src1}",
5939 (int_x86_aesni_aesimc VR128:$src1))]>,
5941 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5942 (ins i128mem:$src1),
5943 "aesimc\t{$src1, $dst|$dst, $src1}",
5945 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5948 // AES Round Key Generation Assist
5949 let Predicates = [HasAVX, HasAES] in {
5950 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5951 (ins VR128:$src1, i8imm:$src2),
5952 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5954 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5956 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5957 (ins i128mem:$src1, i8imm:$src2),
5958 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5960 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5964 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5965 (ins VR128:$src1, i8imm:$src2),
5966 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5968 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5970 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5971 (ins i128mem:$src1, i8imm:$src2),
5972 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5974 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5978 //===----------------------------------------------------------------------===//
5979 // CLMUL Instructions
5980 //===----------------------------------------------------------------------===//
5982 // Carry-less Multiplication instructions
5983 let Constraints = "$src1 = $dst" in {
5984 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5985 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5986 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5989 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5990 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5991 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5995 // AVX carry-less Multiplication instructions
5996 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5997 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5998 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6001 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6002 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6003 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6007 multiclass pclmul_alias<string asm, int immop> {
6008 def : InstAlias<!strconcat("pclmul", asm,
6009 "dq {$src, $dst|$dst, $src}"),
6010 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6012 def : InstAlias<!strconcat("pclmul", asm,
6013 "dq {$src, $dst|$dst, $src}"),
6014 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6016 def : InstAlias<!strconcat("vpclmul", asm,
6017 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6018 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6020 def : InstAlias<!strconcat("vpclmul", asm,
6021 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6022 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6024 defm : pclmul_alias<"hqhq", 0x11>;
6025 defm : pclmul_alias<"hqlq", 0x01>;
6026 defm : pclmul_alias<"lqhq", 0x10>;
6027 defm : pclmul_alias<"lqlq", 0x00>;
6029 //===----------------------------------------------------------------------===//
6031 //===----------------------------------------------------------------------===//
6033 //===----------------------------------------------------------------------===//
6034 // VBROADCAST - Load from memory and broadcast to all elements of the
6035 // destination operand
6037 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6038 X86MemOperand x86memop, Intrinsic Int> :
6039 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6041 [(set RC:$dst, (Int addr:$src))]>, VEX;
6043 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6044 int_x86_avx_vbroadcastss>;
6045 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6046 int_x86_avx_vbroadcastss_256>;
6047 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6048 int_x86_avx_vbroadcast_sd_256>;
6049 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6050 int_x86_avx_vbroadcastf128_pd_256>;
6052 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6053 (VBROADCASTF128 addr:$src)>;
6055 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6056 (VBROADCASTSSY addr:$src)>;
6057 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6058 (VBROADCASTSD addr:$src)>;
6059 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6060 (VBROADCASTSSY addr:$src)>;
6061 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6062 (VBROADCASTSD addr:$src)>;
6064 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6065 (VBROADCASTSS addr:$src)>;
6066 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6067 (VBROADCASTSS addr:$src)>;
6069 //===----------------------------------------------------------------------===//
6070 // VINSERTF128 - Insert packed floating-point values
6072 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6073 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6074 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6076 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6077 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6078 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6081 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6082 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6083 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6084 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6085 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6086 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6088 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6090 (VINSERTF128rr VR256:$src1, VR128:$src2,
6091 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6092 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6094 (VINSERTF128rr VR256:$src1, VR128:$src2,
6095 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6096 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6098 (VINSERTF128rr VR256:$src1, VR128:$src2,
6099 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6100 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6102 (VINSERTF128rr VR256:$src1, VR128:$src2,
6103 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6104 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6106 (VINSERTF128rr VR256:$src1, VR128:$src2,
6107 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6108 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6110 (VINSERTF128rr VR256:$src1, VR128:$src2,
6111 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6113 //===----------------------------------------------------------------------===//
6114 // VEXTRACTF128 - Extract packed floating-point values
6116 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6117 (ins VR256:$src1, i8imm:$src2),
6118 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6120 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6121 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6122 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6125 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6126 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6127 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6128 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6129 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6130 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6132 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6133 (v4f32 (VEXTRACTF128rr
6134 (v8f32 VR256:$src1),
6135 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6136 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6137 (v2f64 (VEXTRACTF128rr
6138 (v4f64 VR256:$src1),
6139 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6140 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6141 (v4i32 (VEXTRACTF128rr
6142 (v8i32 VR256:$src1),
6143 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6144 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6145 (v2i64 (VEXTRACTF128rr
6146 (v4i64 VR256:$src1),
6147 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6148 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6149 (v8i16 (VEXTRACTF128rr
6150 (v16i16 VR256:$src1),
6151 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6152 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6153 (v16i8 (VEXTRACTF128rr
6154 (v32i8 VR256:$src1),
6155 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6157 //===----------------------------------------------------------------------===//
6158 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6160 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6161 Intrinsic IntLd, Intrinsic IntLd256,
6162 Intrinsic IntSt, Intrinsic IntSt256,
6163 PatFrag pf128, PatFrag pf256> {
6164 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6165 (ins VR128:$src1, f128mem:$src2),
6166 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6167 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6169 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6170 (ins VR256:$src1, f256mem:$src2),
6171 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6172 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6174 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6175 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6176 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6177 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6178 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6179 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6180 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6181 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6184 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6185 int_x86_avx_maskload_ps,
6186 int_x86_avx_maskload_ps_256,
6187 int_x86_avx_maskstore_ps,
6188 int_x86_avx_maskstore_ps_256,
6189 memopv4f32, memopv8f32>;
6190 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6191 int_x86_avx_maskload_pd,
6192 int_x86_avx_maskload_pd_256,
6193 int_x86_avx_maskstore_pd,
6194 int_x86_avx_maskstore_pd_256,
6195 memopv2f64, memopv4f64>;
6197 //===----------------------------------------------------------------------===//
6198 // VPERMIL - Permute Single and Double Floating-Point Values
6200 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6201 RegisterClass RC, X86MemOperand x86memop_f,
6202 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6203 Intrinsic IntVar, Intrinsic IntImm> {
6204 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6205 (ins RC:$src1, RC:$src2),
6206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6207 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6208 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6209 (ins RC:$src1, x86memop_i:$src2),
6210 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6211 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6213 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6214 (ins RC:$src1, i8imm:$src2),
6215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6216 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6217 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6218 (ins x86memop_f:$src1, i8imm:$src2),
6219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6220 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6223 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6224 memopv4f32, memopv4i32,
6225 int_x86_avx_vpermilvar_ps,
6226 int_x86_avx_vpermil_ps>;
6227 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6228 memopv8f32, memopv8i32,
6229 int_x86_avx_vpermilvar_ps_256,
6230 int_x86_avx_vpermil_ps_256>;
6231 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6232 memopv2f64, memopv2i64,
6233 int_x86_avx_vpermilvar_pd,
6234 int_x86_avx_vpermil_pd>;
6235 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6236 memopv4f64, memopv4i64,
6237 int_x86_avx_vpermilvar_pd_256,
6238 int_x86_avx_vpermil_pd_256>;
6240 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6241 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6242 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6243 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6244 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6245 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6246 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6247 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6249 //===----------------------------------------------------------------------===//
6250 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6252 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6253 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6254 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6256 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6257 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6258 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6261 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6262 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6263 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6264 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6265 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6266 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6268 def : Pat<(int_x86_avx_vperm2f128_ps_256
6269 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6270 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6271 def : Pat<(int_x86_avx_vperm2f128_pd_256
6272 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6273 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6274 def : Pat<(int_x86_avx_vperm2f128_si_256
6275 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6276 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6278 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6279 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6280 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6281 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6282 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6283 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6284 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6285 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6286 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6287 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6288 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6289 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6291 //===----------------------------------------------------------------------===//
6292 // VZERO - Zero YMM registers
6294 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6295 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6296 // Zero All YMM registers
6297 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6298 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6300 // Zero Upper bits of YMM registers
6301 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6302 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
6305 //===----------------------------------------------------------------------===//
6306 // SSE Shuffle pattern fragments
6307 //===----------------------------------------------------------------------===//
6309 // This is part of a "work in progress" refactoring. The idea is that all
6310 // vector shuffles are going to be translated into target specific nodes and
6311 // directly matched by the patterns below (which can be changed along the way)
6312 // The AVX version of some but not all of them are described here, and more
6313 // should come in a near future.
6315 // Shuffle with MOVLHPD
6316 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
6317 (scalar_to_vector (loadf64 addr:$src2)))),
6318 (MOVHPDrm VR128:$src1, addr:$src2)>;
6320 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
6321 // is during lowering, where it's not possible to recognize the load fold cause
6322 // it has two uses through a bitcast. One use disappears at isel time and the
6323 // fold opportunity reappears.
6324 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
6325 (scalar_to_vector (loadf64 addr:$src2)))),
6326 (MOVHPDrm VR128:$src1, addr:$src2)>;
6328 // Shuffle with MOVLPS
6329 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
6330 (MOVLPSrm VR128:$src1, addr:$src2)>;
6331 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
6332 (MOVLPSrm VR128:$src1, addr:$src2)>;
6333 def : Pat<(X86Movlps VR128:$src1,
6334 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
6335 (MOVLPSrm VR128:$src1, addr:$src2)>;
6337 // Shuffle with MOVLPD
6338 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6339 (MOVLPDrm VR128:$src1, addr:$src2)>;
6340 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6341 (MOVLPDrm VR128:$src1, addr:$src2)>;
6342 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6343 (scalar_to_vector (loadf64 addr:$src2)))),
6344 (MOVLPDrm VR128:$src1, addr:$src2)>;
6346 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6347 def : Pat<(store (f64 (vector_extract
6348 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6349 (MOVHPSmr addr:$dst, VR128:$src)>;
6350 def : Pat<(store (f64 (vector_extract
6351 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6352 (MOVHPDmr addr:$dst, VR128:$src)>;
6354 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6355 (MOVLPSmr addr:$src1, VR128:$src2)>;
6356 def : Pat<(store (v4i32 (X86Movlps
6357 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6358 (MOVLPSmr addr:$src1, VR128:$src2)>;
6360 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6361 (MOVLPDmr addr:$src1, VR128:$src2)>;
6362 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6363 (MOVLPDmr addr:$src1, VR128:$src2)>;