1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2079 (VCVTDQ2PSrm addr:$src)>;
2081 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2082 (VCVTDQ2PSrr VR128:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2084 (VCVTDQ2PSrm addr:$src)>;
2086 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2087 (VCVTTPS2DQrr VR128:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2089 (VCVTTPS2DQrm addr:$src)>;
2091 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2092 (VCVTDQ2PSYrr VR256:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2094 (VCVTDQ2PSYrm addr:$src)>;
2096 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2097 (VCVTTPS2DQYrr VR256:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2099 (VCVTTPS2DQYrm addr:$src)>;
2102 let Predicates = [UseSSE2] in {
2103 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2104 (CVTDQ2PSrr VR128:$src)>;
2105 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2106 (CVTDQ2PSrm addr:$src)>;
2108 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2109 (CVTDQ2PSrr VR128:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2111 (CVTDQ2PSrm addr:$src)>;
2113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2114 (CVTTPS2DQrr VR128:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2116 (CVTTPS2DQrm addr:$src)>;
2119 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2120 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2122 (int_x86_sse2_cvttpd2dq VR128:$src))],
2123 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2125 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2126 // register, but the same isn't true when using memory operands instead.
2127 // Provide other assembly rr and rm forms to address this explicitly.
2130 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2131 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2132 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2133 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2135 (loadv2f64 addr:$src)))],
2136 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2139 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2140 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2143 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2144 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2145 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2147 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2148 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2149 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2150 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2152 let Predicates = [HasAVX] in {
2153 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2154 (VCVTTPD2DQYrr VR256:$src)>;
2155 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2156 (VCVTTPD2DQYrm addr:$src)>;
2157 } // Predicates = [HasAVX]
2159 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2160 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2161 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2162 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2163 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2164 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2165 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2166 (memopv2f64 addr:$src)))],
2168 Sched<[WriteCvtF2ILd]>;
2170 // Convert packed single to packed double
2171 let Predicates = [HasAVX] in {
2172 // SSE2 instructions without OpSize prefix
2173 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2177 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2178 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2179 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2180 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2181 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2184 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2185 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2186 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2187 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2189 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2190 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2193 let Predicates = [UseSSE2] in {
2194 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2195 "cvtps2pd\t{$src, $dst|$dst, $src}",
2196 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2197 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2198 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2199 "cvtps2pd\t{$src, $dst|$dst, $src}",
2200 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2201 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2204 // Convert Packed DW Integers to Packed Double FP
2205 let Predicates = [HasAVX] in {
2206 let hasSideEffects = 0, mayLoad = 1 in
2207 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2208 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2209 []>, VEX, Sched<[WriteCvtI2FLd]>;
2210 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2211 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2213 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2214 Sched<[WriteCvtI2F]>;
2215 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2218 (int_x86_avx_cvtdq2_pd_256
2219 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2220 Sched<[WriteCvtI2FLd]>;
2221 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2222 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2224 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2225 Sched<[WriteCvtI2F]>;
2228 let hasSideEffects = 0, mayLoad = 1 in
2229 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2230 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2231 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2232 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2235 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2237 // AVX 256-bit register conversion intrinsics
2238 let Predicates = [HasAVX] in {
2239 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2240 (VCVTDQ2PDYrr VR128:$src)>;
2241 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2242 (VCVTDQ2PDYrm addr:$src)>;
2243 } // Predicates = [HasAVX]
2245 // Convert packed double to packed single
2246 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2247 // register, but the same isn't true when using memory operands instead.
2248 // Provide other assembly rr and rm forms to address this explicitly.
2249 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2250 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2252 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2255 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2256 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2257 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2258 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2260 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2261 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2264 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2265 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2267 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2268 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2269 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2270 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2272 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2273 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2274 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2275 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2277 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2278 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2279 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2280 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2281 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2282 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2284 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2285 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2288 // AVX 256-bit register conversion intrinsics
2289 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2290 // whenever possible to avoid declaring two versions of each one.
2291 let Predicates = [HasAVX] in {
2292 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2293 (VCVTDQ2PSYrr VR256:$src)>;
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2295 (VCVTDQ2PSYrm addr:$src)>;
2297 // Match fround and fextend for 128/256-bit conversions
2298 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2299 (VCVTPD2PSrr VR128:$src)>;
2300 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2301 (VCVTPD2PSXrm addr:$src)>;
2302 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2303 (VCVTPD2PSYrr VR256:$src)>;
2304 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2305 (VCVTPD2PSYrm addr:$src)>;
2307 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2308 (VCVTPS2PDrr VR128:$src)>;
2309 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2310 (VCVTPS2PDYrr VR128:$src)>;
2311 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2312 (VCVTPS2PDYrm addr:$src)>;
2315 let Predicates = [UseSSE2] in {
2316 // Match fround and fextend for 128 conversions
2317 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2318 (CVTPD2PSrr VR128:$src)>;
2319 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2320 (CVTPD2PSrm addr:$src)>;
2322 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2323 (CVTPS2PDrr VR128:$src)>;
2326 //===----------------------------------------------------------------------===//
2327 // SSE 1 & 2 - Compare Instructions
2328 //===----------------------------------------------------------------------===//
2330 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2331 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2332 Operand CC, SDNode OpNode, ValueType VT,
2333 PatFrag ld_frag, string asm, string asm_alt,
2334 OpndItins itins, ImmLeaf immLeaf> {
2335 def rr : SIi8<0xC2, MRMSrcReg,
2336 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2337 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2338 itins.rr>, Sched<[itins.Sched]>;
2339 def rm : SIi8<0xC2, MRMSrcMem,
2340 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2341 [(set RC:$dst, (OpNode (VT RC:$src1),
2342 (ld_frag addr:$src2), immLeaf:$cc))],
2344 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2346 // Accept explicit immediate argument form instead of comparison code.
2347 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2348 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2349 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2350 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2352 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2353 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2354 IIC_SSE_ALU_F32S_RM>,
2355 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2359 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2360 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2361 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2362 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2363 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2364 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2366 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2367 XD, VEX_4V, VEX_LIG;
2369 let Constraints = "$src1 = $dst" in {
2370 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2371 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2372 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2374 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2375 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2376 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2377 SSE_ALU_F64S, i8immZExt3>, XD;
2380 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2381 Intrinsic Int, string asm, OpndItins itins,
2383 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2384 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2385 [(set VR128:$dst, (Int VR128:$src1,
2386 VR128:$src, immLeaf:$cc))],
2388 Sched<[itins.Sched]>;
2389 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2390 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2391 [(set VR128:$dst, (Int VR128:$src1,
2392 (load addr:$src), immLeaf:$cc))],
2394 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2397 let isCodeGenOnly = 1 in {
2398 // Aliases to match intrinsics which expect XMM operand(s).
2399 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2400 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2401 SSE_ALU_F32S, i8immZExt5>,
2403 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2404 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2405 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2407 let Constraints = "$src1 = $dst" in {
2408 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2409 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2410 SSE_ALU_F32S, i8immZExt3>, XS;
2411 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2413 SSE_ALU_F64S, i8immZExt3>,
2419 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2420 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2421 ValueType vt, X86MemOperand x86memop,
2422 PatFrag ld_frag, string OpcodeStr> {
2423 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2424 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2425 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2428 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2430 [(set EFLAGS, (OpNode (vt RC:$src1),
2431 (ld_frag addr:$src2)))],
2433 Sched<[WriteFAddLd, ReadAfterLd]>;
2436 let Defs = [EFLAGS] in {
2437 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2438 "ucomiss">, PS, VEX, VEX_LIG;
2439 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2440 "ucomisd">, PD, VEX, VEX_LIG;
2441 let Pattern = []<dag> in {
2442 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2443 "comiss">, PS, VEX, VEX_LIG;
2444 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2445 "comisd">, PD, VEX, VEX_LIG;
2448 let isCodeGenOnly = 1 in {
2449 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2450 load, "ucomiss">, PS, VEX;
2451 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2452 load, "ucomisd">, PD, VEX;
2454 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2455 load, "comiss">, PS, VEX;
2456 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2457 load, "comisd">, PD, VEX;
2459 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2461 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2464 let Pattern = []<dag> in {
2465 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2467 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2471 let isCodeGenOnly = 1 in {
2472 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2473 load, "ucomiss">, PS;
2474 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2475 load, "ucomisd">, PD;
2477 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2479 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2482 } // Defs = [EFLAGS]
2484 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2485 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2486 Operand CC, Intrinsic Int, string asm,
2487 string asm_alt, Domain d, ImmLeaf immLeaf,
2488 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2489 let isCommutable = 1 in
2490 def rri : PIi8<0xC2, MRMSrcReg,
2491 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2492 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2495 def rmi : PIi8<0xC2, MRMSrcMem,
2496 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2497 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2499 Sched<[WriteFAddLd, ReadAfterLd]>;
2501 // Accept explicit immediate argument form instead of comparison code.
2502 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2503 def rri_alt : PIi8<0xC2, MRMSrcReg,
2504 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2505 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2507 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2508 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2509 asm_alt, [], itins.rm, d>,
2510 Sched<[WriteFAddLd, ReadAfterLd]>;
2514 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2515 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2516 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2517 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2518 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2519 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2521 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2522 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2526 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2530 let Constraints = "$src1 = $dst" in {
2531 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2533 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2535 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2537 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2541 let Predicates = [HasAVX] in {
2542 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2543 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2544 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2545 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2546 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2547 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2548 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2549 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2551 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2552 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2553 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2554 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2555 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2556 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2557 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2558 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2561 let Predicates = [UseSSE1] in {
2562 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2563 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2564 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2565 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2568 let Predicates = [UseSSE2] in {
2569 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2570 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2571 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2572 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2575 //===----------------------------------------------------------------------===//
2576 // SSE 1 & 2 - Shuffle Instructions
2577 //===----------------------------------------------------------------------===//
2579 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2580 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2581 ValueType vt, string asm, PatFrag mem_frag,
2583 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2584 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2585 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2586 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2587 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2588 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2589 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2590 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2591 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2592 Sched<[WriteFShuffle]>;
2595 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2596 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2597 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2598 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2599 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2600 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2601 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2602 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2603 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2604 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2605 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2606 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2608 let Constraints = "$src1 = $dst" in {
2609 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2610 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2611 memopv4f32, SSEPackedSingle>, PS;
2612 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2613 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 memopv2f64, SSEPackedDouble>, PD;
2617 let Predicates = [HasAVX] in {
2618 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2619 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2620 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2621 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2622 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2624 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2625 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2626 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2627 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2628 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2631 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2632 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2633 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2634 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2635 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2637 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2638 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2639 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2640 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2641 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2644 let Predicates = [UseSSE1] in {
2645 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2646 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2647 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2648 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2649 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2652 let Predicates = [UseSSE2] in {
2653 // Generic SHUFPD patterns
2654 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2655 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2656 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2657 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2658 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2661 //===----------------------------------------------------------------------===//
2662 // SSE 1 & 2 - Unpack FP Instructions
2663 //===----------------------------------------------------------------------===//
2665 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2666 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2667 PatFrag mem_frag, RegisterClass RC,
2668 X86MemOperand x86memop, string asm,
2670 def rr : PI<opc, MRMSrcReg,
2671 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2673 (vt (OpNode RC:$src1, RC:$src2)))],
2674 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2675 def rm : PI<opc, MRMSrcMem,
2676 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2678 (vt (OpNode RC:$src1,
2679 (mem_frag addr:$src2))))],
2681 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2684 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2685 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2686 SSEPackedSingle>, PS, VEX_4V;
2687 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2688 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2689 SSEPackedDouble>, PD, VEX_4V;
2690 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2691 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2692 SSEPackedSingle>, PS, VEX_4V;
2693 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2694 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2695 SSEPackedDouble>, PD, VEX_4V;
2697 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2698 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2700 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2701 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2703 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2704 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2706 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2707 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2710 let Constraints = "$src1 = $dst" in {
2711 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2712 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2713 SSEPackedSingle>, PS;
2714 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2715 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2716 SSEPackedDouble>, PD;
2717 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2718 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2719 SSEPackedSingle>, PS;
2720 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2721 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2722 SSEPackedDouble>, PD;
2723 } // Constraints = "$src1 = $dst"
2725 let Predicates = [HasAVX1Only] in {
2726 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2727 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2728 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2729 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2730 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2731 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2732 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2733 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2735 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2736 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2737 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2738 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2739 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2740 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2741 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2742 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2745 //===----------------------------------------------------------------------===//
2746 // SSE 1 & 2 - Extract Floating-Point Sign mask
2747 //===----------------------------------------------------------------------===//
2749 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2750 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2752 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2753 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2754 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2755 Sched<[WriteVecLogic]>;
2758 let Predicates = [HasAVX] in {
2759 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2760 "movmskps", SSEPackedSingle>, PS, VEX;
2761 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2762 "movmskpd", SSEPackedDouble>, PD, VEX;
2763 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2764 "movmskps", SSEPackedSingle>, PS,
2766 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2767 "movmskpd", SSEPackedDouble>, PD,
2770 def : Pat<(i32 (X86fgetsign FR32:$src)),
2771 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2772 def : Pat<(i64 (X86fgetsign FR32:$src)),
2773 (SUBREG_TO_REG (i64 0),
2774 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2775 def : Pat<(i32 (X86fgetsign FR64:$src)),
2776 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2777 def : Pat<(i64 (X86fgetsign FR64:$src)),
2778 (SUBREG_TO_REG (i64 0),
2779 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2782 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2783 SSEPackedSingle>, PS;
2784 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2785 SSEPackedDouble>, PD;
2787 def : Pat<(i32 (X86fgetsign FR32:$src)),
2788 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2789 Requires<[UseSSE1]>;
2790 def : Pat<(i64 (X86fgetsign FR32:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2793 Requires<[UseSSE1]>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2796 Requires<[UseSSE2]>;
2797 def : Pat<(i64 (X86fgetsign FR64:$src)),
2798 (SUBREG_TO_REG (i64 0),
2799 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2800 Requires<[UseSSE2]>;
2802 //===---------------------------------------------------------------------===//
2803 // SSE2 - Packed Integer Logical Instructions
2804 //===---------------------------------------------------------------------===//
2806 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2808 /// PDI_binop_rm - Simple SSE2 binary operator.
2809 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2810 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2811 X86MemOperand x86memop, OpndItins itins,
2812 bit IsCommutable, bit Is2Addr> {
2813 let isCommutable = IsCommutable in
2814 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2815 (ins RC:$src1, RC:$src2),
2817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2819 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2820 Sched<[itins.Sched]>;
2821 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2822 (ins RC:$src1, x86memop:$src2),
2824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2826 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2827 (bitconvert (memop_frag addr:$src2)))))],
2829 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2831 } // ExeDomain = SSEPackedInt
2833 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2834 ValueType OpVT128, ValueType OpVT256,
2835 OpndItins itins, bit IsCommutable = 0> {
2836 let Predicates = [HasAVX, NoVLX] in
2837 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2838 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2840 let Constraints = "$src1 = $dst" in
2841 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2842 memopv2i64, i128mem, itins, IsCommutable, 1>;
2844 let Predicates = [HasAVX2, NoVLX] in
2845 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2846 OpVT256, VR256, loadv4i64, i256mem, itins,
2847 IsCommutable, 0>, VEX_4V, VEX_L;
2850 // These are ordered here for pattern ordering requirements with the fp versions
2852 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2853 SSE_VEC_BIT_ITINS_P, 1>;
2854 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2855 SSE_VEC_BIT_ITINS_P, 1>;
2856 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2857 SSE_VEC_BIT_ITINS_P, 1>;
2858 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2859 SSE_VEC_BIT_ITINS_P, 0>;
2861 //===----------------------------------------------------------------------===//
2862 // SSE 1 & 2 - Logical Instructions
2863 //===----------------------------------------------------------------------===//
2865 // Multiclass for scalars using the X86 logical operation aliases for FP.
2866 multiclass sse12_fp_packed_scalar_logical_alias<
2867 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2868 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2869 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2872 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2873 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2876 let Constraints = "$src1 = $dst" in {
2877 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2878 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2880 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2881 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2885 let isCodeGenOnly = 1 in {
2886 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2888 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2890 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2893 let isCommutable = 0 in
2894 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2898 // Multiclass for vectors using the X86 logical operation aliases for FP.
2899 multiclass sse12_fp_packed_vector_logical_alias<
2900 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2901 let Predicates = [HasAVX, NoVLX] in {
2902 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2903 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2906 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2907 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2911 let Constraints = "$src1 = $dst" in {
2912 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2913 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2916 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2917 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2922 let isCodeGenOnly = 1 in {
2923 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2925 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2927 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2930 let isCommutable = 0 in
2931 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2935 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2937 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2939 let Predicates = [HasAVX, NoVLX] in {
2940 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2941 !strconcat(OpcodeStr, "ps"), f256mem,
2942 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2943 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2944 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2946 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2947 !strconcat(OpcodeStr, "pd"), f256mem,
2948 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2949 (bc_v4i64 (v4f64 VR256:$src2))))],
2950 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2951 (loadv4i64 addr:$src2)))], 0>,
2954 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2955 // are all promoted to v2i64, and the patterns are covered by the int
2956 // version. This is needed in SSE only, because v2i64 isn't supported on
2957 // SSE1, but only on SSE2.
2958 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2959 !strconcat(OpcodeStr, "ps"), f128mem, [],
2960 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2961 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2963 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2964 !strconcat(OpcodeStr, "pd"), f128mem,
2965 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2966 (bc_v2i64 (v2f64 VR128:$src2))))],
2967 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2968 (loadv2i64 addr:$src2)))], 0>,
2972 let Constraints = "$src1 = $dst" in {
2973 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2974 !strconcat(OpcodeStr, "ps"), f128mem,
2975 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2977 (memopv2i64 addr:$src2)))]>, PS;
2979 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2980 !strconcat(OpcodeStr, "pd"), f128mem,
2981 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2982 (bc_v2i64 (v2f64 VR128:$src2))))],
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (memopv2i64 addr:$src2)))]>, PD;
2988 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2989 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2990 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2991 let isCommutable = 0 in
2992 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2994 // AVX1 requires type coercions in order to fold loads directly into logical
2996 let Predicates = [HasAVX1Only] in {
2997 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2998 (VANDPSYrm VR256:$src1, addr:$src2)>;
2999 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3000 (VORPSYrm VR256:$src1, addr:$src2)>;
3001 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3002 (VXORPSYrm VR256:$src1, addr:$src2)>;
3003 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3004 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3007 //===----------------------------------------------------------------------===//
3008 // SSE 1 & 2 - Arithmetic Instructions
3009 //===----------------------------------------------------------------------===//
3011 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3014 /// In addition, we also have a special variant of the scalar form here to
3015 /// represent the associated intrinsic operation. This form is unlike the
3016 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3017 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3019 /// These three forms can each be reg+reg or reg+mem.
3022 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3024 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3025 SDNode OpNode, SizeItins itins> {
3026 let Predicates = [HasAVX, NoVLX] in {
3027 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3028 VR128, v4f32, f128mem, loadv4f32,
3029 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3030 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3031 VR128, v2f64, f128mem, loadv2f64,
3032 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3034 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3035 OpNode, VR256, v8f32, f256mem, loadv8f32,
3036 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3037 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3038 OpNode, VR256, v4f64, f256mem, loadv4f64,
3039 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3042 let Constraints = "$src1 = $dst" in {
3043 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3044 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3046 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3047 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3052 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3054 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3055 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3056 XS, VEX_4V, VEX_LIG;
3057 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3058 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3059 XD, VEX_4V, VEX_LIG;
3061 let Constraints = "$src1 = $dst" in {
3062 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3063 OpNode, FR32, f32mem, SSEPackedSingle,
3065 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3066 OpNode, FR64, f64mem, SSEPackedDouble,
3071 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3073 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3074 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3075 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3076 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3077 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3078 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3080 let Constraints = "$src1 = $dst" in {
3081 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3082 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3083 SSEPackedSingle, itins.s>, XS;
3084 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3085 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3086 SSEPackedDouble, itins.d>, XD;
3090 // Binary Arithmetic instructions
3091 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3093 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3094 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3095 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3096 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3097 let isCommutable = 0 in {
3098 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3101 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3102 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3103 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3104 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3107 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3112 let isCodeGenOnly = 1 in {
3113 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3114 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3115 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3116 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3119 // Patterns used to select SSE scalar fp arithmetic instructions from
3122 // (1) a scalar fp operation followed by a blend
3124 // The effect is that the backend no longer emits unnecessary vector
3125 // insert instructions immediately after SSE scalar fp instructions
3126 // like addss or mulss.
3128 // For example, given the following code:
3129 // __m128 foo(__m128 A, __m128 B) {
3134 // Previously we generated:
3135 // addss %xmm0, %xmm1
3136 // movss %xmm1, %xmm0
3139 // addss %xmm1, %xmm0
3141 // (2) a vector packed single/double fp operation followed by a vector insert
3143 // The effect is that the backend converts the packed fp instruction
3144 // followed by a vector insert into a single SSE scalar fp instruction.
3146 // For example, given the following code:
3147 // __m128 foo(__m128 A, __m128 B) {
3148 // __m128 C = A + B;
3149 // return (__m128) {c[0], a[1], a[2], a[3]};
3152 // Previously we generated:
3153 // addps %xmm0, %xmm1
3154 // movss %xmm1, %xmm0
3157 // addss %xmm1, %xmm0
3159 // TODO: Some canonicalization in lowering would simplify the number of
3160 // patterns we have to try to match.
3161 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3162 let Predicates = [UseSSE1] in {
3163 // extracted scalar math op with insert via movss
3164 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3165 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3167 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3168 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3170 // vector math op with insert via movss
3171 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3172 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3173 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3176 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3177 let Predicates = [UseSSE41] in {
3178 // extracted scalar math op with insert via blend
3179 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3180 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3181 FR32:$src))), (i8 1))),
3182 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3183 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3185 // vector math op with insert via blend
3186 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3187 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3188 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3192 // Repeat everything for AVX, except for the movss + scalar combo...
3193 // because that one shouldn't occur with AVX codegen?
3194 let Predicates = [HasAVX] in {
3195 // extracted scalar math op with insert via blend
3196 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3197 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (i8 1))),
3199 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3200 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3202 // vector math op with insert via movss
3203 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3204 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3205 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3207 // vector math op with insert via blend
3208 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3209 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3210 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3214 defm : scalar_math_f32_patterns<fadd, "ADD">;
3215 defm : scalar_math_f32_patterns<fsub, "SUB">;
3216 defm : scalar_math_f32_patterns<fmul, "MUL">;
3217 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3219 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3220 let Predicates = [UseSSE2] in {
3221 // extracted scalar math op with insert via movsd
3222 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3223 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3225 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3226 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 // vector math op with insert via movsd
3229 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3230 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3231 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3234 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3235 let Predicates = [UseSSE41] in {
3236 // extracted scalar math op with insert via blend
3237 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3238 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3239 FR64:$src))), (i8 1))),
3240 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3241 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3243 // vector math op with insert via blend
3244 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3245 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3246 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3249 // Repeat everything for AVX.
3250 let Predicates = [HasAVX] in {
3251 // extracted scalar math op with insert via movsd
3252 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3253 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3255 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3256 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3258 // extracted scalar math op with insert via blend
3259 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3260 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3261 FR64:$src))), (i8 1))),
3262 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3263 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3265 // vector math op with insert via movsd
3266 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3267 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3268 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3270 // vector math op with insert via blend
3271 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3272 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3277 defm : scalar_math_f64_patterns<fadd, "ADD">;
3278 defm : scalar_math_f64_patterns<fsub, "SUB">;
3279 defm : scalar_math_f64_patterns<fmul, "MUL">;
3280 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3284 /// In addition, we also have a special variant of the scalar form here to
3285 /// represent the associated intrinsic operation. This form is unlike the
3286 /// plain scalar form, in that it takes an entire vector (instead of a
3287 /// scalar) and leaves the top elements undefined.
3289 /// And, we have a special variant form for a full-vector intrinsic form.
3291 let Sched = WriteFSqrt in {
3292 def SSE_SQRTPS : OpndItins<
3293 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3296 def SSE_SQRTSS : OpndItins<
3297 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3300 def SSE_SQRTPD : OpndItins<
3301 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3304 def SSE_SQRTSD : OpndItins<
3305 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3309 let Sched = WriteFRsqrt in {
3310 def SSE_RSQRTPS : OpndItins<
3311 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3314 def SSE_RSQRTSS : OpndItins<
3315 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3319 let Sched = WriteFRcp in {
3320 def SSE_RCPP : OpndItins<
3321 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3324 def SSE_RCPS : OpndItins<
3325 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3329 /// sse_fp_unop_s - SSE1 unops in scalar form
3330 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3331 /// the HW instructions are 2 operand / destructive.
3332 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3333 ValueType vt, ValueType ScalarVT,
3334 X86MemOperand x86memop, Operand vec_memop,
3335 ComplexPattern mem_cpat, Intrinsic Intr,
3336 SDNode OpNode, Domain d, OpndItins itins,
3337 Predicate target, string Suffix> {
3338 let hasSideEffects = 0 in {
3339 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3340 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3341 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3344 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3345 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3346 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3347 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3348 Requires<[target, OptForSize]>;
3350 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3351 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3352 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3353 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3355 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3357 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3361 let Predicates = [target] in {
3362 def : Pat<(vt (OpNode mem_cpat:$src)),
3363 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3364 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3365 // These are unary operations, but they are modeled as having 2 source operands
3366 // because the high elements of the destination are unchanged in SSE.
3367 def : Pat<(Intr VR128:$src),
3368 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3369 def : Pat<(Intr (load addr:$src)),
3370 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3371 addr:$src), VR128))>;
3372 def : Pat<(Intr mem_cpat:$src),
3373 (!cast<Instruction>(NAME#Suffix##m_Int)
3374 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3378 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3379 ValueType vt, ValueType ScalarVT,
3380 X86MemOperand x86memop, Operand vec_memop,
3381 ComplexPattern mem_cpat,
3382 Intrinsic Intr, SDNode OpNode, Domain d,
3383 OpndItins itins, Predicate target, string Suffix> {
3384 let hasSideEffects = 0 in {
3385 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3387 [], itins.rr, d>, Sched<[itins.Sched]>;
3389 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3391 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3392 let isCodeGenOnly = 1 in {
3393 // todo: uncomment when all r_Int forms will be added to X86InstrInfo.cpp
3394 //def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3395 // (ins VR128:$src1, VR128:$src2),
3396 // !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3397 // []>, Sched<[itins.Sched.Folded]>;
3399 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3400 (ins VR128:$src1, vec_memop:$src2),
3401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3402 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3406 let Predicates = [target] in {
3407 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3408 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3410 def : Pat<(vt (OpNode mem_cpat:$src)),
3411 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3414 // todo: use r_Int form when it will be ready
3415 //def : Pat<(Intr VR128:$src), (!cast<Instruction>("V"#NAME#Suffix##r_Int)
3416 // (VT (IMPLICIT_DEF)), VR128:$src)>;
3417 def : Pat<(Intr VR128:$src),
3418 (vt (COPY_TO_REGCLASS(
3419 !cast<Instruction>("V"#NAME#Suffix##r) (ScalarVT (IMPLICIT_DEF)),
3420 (ScalarVT (COPY_TO_REGCLASS VR128:$src, RC))), VR128))>;
3421 def : Pat<(Intr mem_cpat:$src),
3422 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3423 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3425 let Predicates = [target, OptForSize] in
3426 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3427 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3431 /// sse1_fp_unop_p - SSE1 unops in packed form.
3432 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3434 let Predicates = [HasAVX] in {
3435 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3436 !strconcat("v", OpcodeStr,
3437 "ps\t{$src, $dst|$dst, $src}"),
3438 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3439 itins.rr>, VEX, Sched<[itins.Sched]>;
3440 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3441 !strconcat("v", OpcodeStr,
3442 "ps\t{$src, $dst|$dst, $src}"),
3443 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3444 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3445 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3446 !strconcat("v", OpcodeStr,
3447 "ps\t{$src, $dst|$dst, $src}"),
3448 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3449 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3450 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3451 !strconcat("v", OpcodeStr,
3452 "ps\t{$src, $dst|$dst, $src}"),
3453 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3454 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3457 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3458 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3460 Sched<[itins.Sched]>;
3461 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3462 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3463 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3464 Sched<[itins.Sched.Folded]>;
3467 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3468 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3469 SDNode OpNode, OpndItins itins> {
3470 let Predicates = [HasAVX] in {
3471 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3472 !strconcat("v", OpcodeStr,
3473 "pd\t{$src, $dst|$dst, $src}"),
3474 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3475 itins.rr>, VEX, Sched<[itins.Sched]>;
3476 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3477 !strconcat("v", OpcodeStr,
3478 "pd\t{$src, $dst|$dst, $src}"),
3479 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3480 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3481 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3482 !strconcat("v", OpcodeStr,
3483 "pd\t{$src, $dst|$dst, $src}"),
3484 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3485 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3486 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3487 !strconcat("v", OpcodeStr,
3488 "pd\t{$src, $dst|$dst, $src}"),
3489 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3490 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3493 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3494 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3495 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3496 Sched<[itins.Sched]>;
3497 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3498 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3499 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3500 Sched<[itins.Sched.Folded]>;
3503 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3505 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3506 ssmem, sse_load_f32,
3507 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3508 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3509 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3510 f32mem, ssmem, sse_load_f32,
3511 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3512 SSEPackedSingle, itins, UseAVX, "SS">, XS, VEX_4V, VEX_LIG;
3515 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3517 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3518 sdmem, sse_load_f64,
3519 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3520 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3521 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3522 f64mem, sdmem, sse_load_f64,
3523 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3524 OpNode, SSEPackedDouble, itins, UseAVX, "SD">,
3525 XD, VEX_4V, VEX_LIG;
3529 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3530 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3531 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3532 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3534 // Reciprocal approximations. Note that these typically require refinement
3535 // in order to obtain suitable precision.
3536 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3537 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3538 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3539 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3541 // There is no f64 version of the reciprocal approximation instructions.
3543 //===----------------------------------------------------------------------===//
3544 // SSE 1 & 2 - Non-temporal stores
3545 //===----------------------------------------------------------------------===//
3547 let AddedComplexity = 400 in { // Prefer non-temporal versions
3548 let SchedRW = [WriteStore] in {
3549 let Predicates = [HasAVX, NoVLX] in {
3550 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3551 (ins f128mem:$dst, VR128:$src),
3552 "movntps\t{$src, $dst|$dst, $src}",
3553 [(alignednontemporalstore (v4f32 VR128:$src),
3555 IIC_SSE_MOVNT>, VEX;
3556 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3557 (ins f128mem:$dst, VR128:$src),
3558 "movntpd\t{$src, $dst|$dst, $src}",
3559 [(alignednontemporalstore (v2f64 VR128:$src),
3561 IIC_SSE_MOVNT>, VEX;
3563 let ExeDomain = SSEPackedInt in
3564 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3565 (ins f128mem:$dst, VR128:$src),
3566 "movntdq\t{$src, $dst|$dst, $src}",
3567 [(alignednontemporalstore (v2i64 VR128:$src),
3569 IIC_SSE_MOVNT>, VEX;
3571 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3572 (ins f256mem:$dst, VR256:$src),
3573 "movntps\t{$src, $dst|$dst, $src}",
3574 [(alignednontemporalstore (v8f32 VR256:$src),
3576 IIC_SSE_MOVNT>, VEX, VEX_L;
3577 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3578 (ins f256mem:$dst, VR256:$src),
3579 "movntpd\t{$src, $dst|$dst, $src}",
3580 [(alignednontemporalstore (v4f64 VR256:$src),
3582 IIC_SSE_MOVNT>, VEX, VEX_L;
3583 let ExeDomain = SSEPackedInt in
3584 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3585 (ins f256mem:$dst, VR256:$src),
3586 "movntdq\t{$src, $dst|$dst, $src}",
3587 [(alignednontemporalstore (v4i64 VR256:$src),
3589 IIC_SSE_MOVNT>, VEX, VEX_L;
3592 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3593 "movntps\t{$src, $dst|$dst, $src}",
3594 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3596 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3597 "movntpd\t{$src, $dst|$dst, $src}",
3598 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3601 let ExeDomain = SSEPackedInt in
3602 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3603 "movntdq\t{$src, $dst|$dst, $src}",
3604 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3607 // There is no AVX form for instructions below this point
3608 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3609 "movnti{l}\t{$src, $dst|$dst, $src}",
3610 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3612 PS, Requires<[HasSSE2]>;
3613 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3614 "movnti{q}\t{$src, $dst|$dst, $src}",
3615 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3617 PS, Requires<[HasSSE2]>;
3618 } // SchedRW = [WriteStore]
3620 let Predicates = [HasAVX2, NoVLX] in {
3621 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3622 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3623 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3624 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3625 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3626 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3629 let Predicates = [HasAVX, NoVLX] in {
3630 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3631 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3632 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3633 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3634 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3635 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3638 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3639 (MOVNTDQmr addr:$dst, VR128:$src)>;
3640 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3641 (MOVNTDQmr addr:$dst, VR128:$src)>;
3642 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3643 (MOVNTDQmr addr:$dst, VR128:$src)>;
3645 } // AddedComplexity
3647 //===----------------------------------------------------------------------===//
3648 // SSE 1 & 2 - Prefetch and memory fence
3649 //===----------------------------------------------------------------------===//
3651 // Prefetch intrinsic.
3652 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3653 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3654 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3655 IIC_SSE_PREFETCH>, TB;
3656 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3657 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3658 IIC_SSE_PREFETCH>, TB;
3659 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3660 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3661 IIC_SSE_PREFETCH>, TB;
3662 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3663 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3664 IIC_SSE_PREFETCH>, TB;
3667 // FIXME: How should flush instruction be modeled?
3668 let SchedRW = [WriteLoad] in {
3670 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3671 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3672 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3675 let SchedRW = [WriteNop] in {
3676 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3677 // was introduced with SSE2, it's backward compatible.
3678 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3679 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3680 OBXS, Requires<[HasSSE2]>;
3683 let SchedRW = [WriteFence] in {
3684 // Load, store, and memory fence
3685 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3686 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3687 PS, Requires<[HasSSE1]>;
3688 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3689 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3690 TB, Requires<[HasSSE2]>;
3691 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3692 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3693 TB, Requires<[HasSSE2]>;
3696 def : Pat<(X86SFence), (SFENCE)>;
3697 def : Pat<(X86LFence), (LFENCE)>;
3698 def : Pat<(X86MFence), (MFENCE)>;
3700 //===----------------------------------------------------------------------===//
3701 // SSE 1 & 2 - Load/Store XCSR register
3702 //===----------------------------------------------------------------------===//
3704 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3705 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3706 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3707 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3708 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3709 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3711 let Predicates = [UseSSE1] in {
3712 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3713 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3714 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3715 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3716 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3717 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3720 //===---------------------------------------------------------------------===//
3721 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3722 //===---------------------------------------------------------------------===//
3724 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3726 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3727 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3728 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3730 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3731 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3733 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3734 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3736 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3737 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3742 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3743 SchedRW = [WriteMove] in {
3744 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3745 "movdqa\t{$src, $dst|$dst, $src}", [],
3748 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3749 "movdqa\t{$src, $dst|$dst, $src}", [],
3750 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3751 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3752 "movdqu\t{$src, $dst|$dst, $src}", [],
3755 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3756 "movdqu\t{$src, $dst|$dst, $src}", [],
3757 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3760 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3761 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3762 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3763 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3765 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3766 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3768 let Predicates = [HasAVX] in {
3769 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3770 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3772 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3773 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3778 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3779 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3780 (ins i128mem:$dst, VR128:$src),
3781 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3783 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3784 (ins i256mem:$dst, VR256:$src),
3785 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3787 let Predicates = [HasAVX] in {
3788 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3789 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3791 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3792 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3797 let SchedRW = [WriteMove] in {
3798 let hasSideEffects = 0 in
3799 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3800 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3802 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3803 "movdqu\t{$src, $dst|$dst, $src}",
3804 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3807 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3808 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3809 "movdqa\t{$src, $dst|$dst, $src}", [],
3812 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3813 "movdqu\t{$src, $dst|$dst, $src}",
3814 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3818 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3819 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3820 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3821 "movdqa\t{$src, $dst|$dst, $src}",
3822 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3824 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3825 "movdqu\t{$src, $dst|$dst, $src}",
3826 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3828 XS, Requires<[UseSSE2]>;
3831 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3832 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3833 "movdqa\t{$src, $dst|$dst, $src}",
3834 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3836 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3837 "movdqu\t{$src, $dst|$dst, $src}",
3838 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3840 XS, Requires<[UseSSE2]>;
3843 } // ExeDomain = SSEPackedInt
3845 let Predicates = [HasAVX] in {
3846 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3847 (VMOVDQUmr addr:$dst, VR128:$src)>;
3848 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3849 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3851 let Predicates = [UseSSE2] in
3852 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3853 (MOVDQUmr addr:$dst, VR128:$src)>;
3855 //===---------------------------------------------------------------------===//
3856 // SSE2 - Packed Integer Arithmetic Instructions
3857 //===---------------------------------------------------------------------===//
3859 let Sched = WriteVecIMul in
3860 def SSE_PMADD : OpndItins<
3861 IIC_SSE_PMADD, IIC_SSE_PMADD
3864 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3866 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3867 RegisterClass RC, PatFrag memop_frag,
3868 X86MemOperand x86memop,
3870 bit IsCommutable = 0,
3872 let isCommutable = IsCommutable in
3873 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3874 (ins RC:$src1, RC:$src2),
3876 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3878 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3879 Sched<[itins.Sched]>;
3880 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3881 (ins RC:$src1, x86memop:$src2),
3883 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3885 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3886 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3889 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3890 Intrinsic IntId256, OpndItins itins,
3891 bit IsCommutable = 0> {
3892 let Predicates = [HasAVX] in
3893 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3894 VR128, loadv2i64, i128mem, itins,
3895 IsCommutable, 0>, VEX_4V;
3897 let Constraints = "$src1 = $dst" in
3898 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3899 i128mem, itins, IsCommutable, 1>;
3901 let Predicates = [HasAVX2] in
3902 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3903 VR256, loadv4i64, i256mem, itins,
3904 IsCommutable, 0>, VEX_4V, VEX_L;
3907 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3908 string OpcodeStr, SDNode OpNode,
3909 SDNode OpNode2, RegisterClass RC,
3910 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3911 PatFrag ld_frag, ShiftOpndItins itins,
3913 // src2 is always 128-bit
3914 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3915 (ins RC:$src1, VR128:$src2),
3917 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3918 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3919 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3920 itins.rr>, Sched<[WriteVecShift]>;
3921 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3922 (ins RC:$src1, i128mem:$src2),
3924 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3925 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3926 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3927 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3928 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3929 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3930 (ins RC:$src1, u8imm:$src2),
3932 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3933 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3934 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3935 Sched<[WriteVecShift]>;
3938 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3939 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3940 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3941 PatFrag memop_frag, X86MemOperand x86memop,
3943 bit IsCommutable = 0, bit Is2Addr = 1> {
3944 let isCommutable = IsCommutable in
3945 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3946 (ins RC:$src1, RC:$src2),
3948 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3950 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3951 Sched<[itins.Sched]>;
3952 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3953 (ins RC:$src1, x86memop:$src2),
3955 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3957 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3958 (bitconvert (memop_frag addr:$src2)))))]>,
3959 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3961 } // ExeDomain = SSEPackedInt
3963 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3964 SSE_INTALU_ITINS_P, 1>;
3965 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3966 SSE_INTALU_ITINS_P, 1>;
3967 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3968 SSE_INTALU_ITINS_P, 1>;
3969 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3970 SSE_INTALUQ_ITINS_P, 1>;
3971 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3972 SSE_INTMUL_ITINS_P, 1>;
3973 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
3974 SSE_INTMUL_ITINS_P, 1>;
3975 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
3976 SSE_INTMUL_ITINS_P, 1>;
3977 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3978 SSE_INTALU_ITINS_P, 0>;
3979 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3980 SSE_INTALU_ITINS_P, 0>;
3981 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3982 SSE_INTALU_ITINS_P, 0>;
3983 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3984 SSE_INTALUQ_ITINS_P, 0>;
3985 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3986 SSE_INTALU_ITINS_P, 0>;
3987 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3988 SSE_INTALU_ITINS_P, 0>;
3989 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3990 SSE_INTALU_ITINS_P, 1>;
3991 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3992 SSE_INTALU_ITINS_P, 1>;
3993 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3994 SSE_INTALU_ITINS_P, 1>;
3995 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3996 SSE_INTALU_ITINS_P, 1>;
3999 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4000 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4001 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4002 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4003 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4004 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4005 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4006 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4007 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4008 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4009 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4010 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4011 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4012 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4013 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4014 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4015 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4016 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4017 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4018 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4020 let Predicates = [HasAVX] in
4021 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4022 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4024 let Predicates = [HasAVX2] in
4025 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4026 VR256, loadv4i64, i256mem,
4027 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4028 let Constraints = "$src1 = $dst" in
4029 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4030 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4032 //===---------------------------------------------------------------------===//
4033 // SSE2 - Packed Integer Logical Instructions
4034 //===---------------------------------------------------------------------===//
4036 let Predicates = [HasAVX, NoVLX] in {
4037 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4038 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4039 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4040 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4041 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4042 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4043 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4044 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4045 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4047 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4048 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4049 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4050 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4051 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4052 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4053 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4054 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4055 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4057 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4058 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4059 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4060 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4061 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4062 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4064 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4065 // 128-bit logical shifts.
4066 def VPSLLDQri : PDIi8<0x73, MRM7r,
4067 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4068 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4070 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4072 def VPSRLDQri : PDIi8<0x73, MRM3r,
4073 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4074 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4076 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4078 // PSRADQri doesn't exist in SSE[1-3].
4080 } // Predicates = [HasAVX]
4082 let Predicates = [HasAVX2, NoVLX] in {
4083 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4084 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4085 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4086 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4087 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4088 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4089 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4090 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4091 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4093 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4094 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4095 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4096 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4097 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4098 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4099 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4100 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4101 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4103 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4104 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4105 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4106 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4107 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4108 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4110 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4111 // 256-bit logical shifts.
4112 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4113 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4114 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4116 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4118 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4119 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4120 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4122 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4124 // PSRADQYri doesn't exist in SSE[1-3].
4126 } // Predicates = [HasAVX2]
4128 let Constraints = "$src1 = $dst" in {
4129 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4130 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4131 SSE_INTSHIFT_ITINS_P>;
4132 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4133 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4134 SSE_INTSHIFT_ITINS_P>;
4135 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4136 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4137 SSE_INTSHIFT_ITINS_P>;
4139 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4140 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4141 SSE_INTSHIFT_ITINS_P>;
4142 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4143 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4144 SSE_INTSHIFT_ITINS_P>;
4145 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4146 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4147 SSE_INTSHIFT_ITINS_P>;
4149 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4150 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4151 SSE_INTSHIFT_ITINS_P>;
4152 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4153 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4154 SSE_INTSHIFT_ITINS_P>;
4156 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4157 // 128-bit logical shifts.
4158 def PSLLDQri : PDIi8<0x73, MRM7r,
4159 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4160 "pslldq\t{$src2, $dst|$dst, $src2}",
4162 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4163 IIC_SSE_INTSHDQ_P_RI>;
4164 def PSRLDQri : PDIi8<0x73, MRM3r,
4165 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4166 "psrldq\t{$src2, $dst|$dst, $src2}",
4168 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4169 IIC_SSE_INTSHDQ_P_RI>;
4170 // PSRADQri doesn't exist in SSE[1-3].
4172 } // Constraints = "$src1 = $dst"
4174 let Predicates = [HasAVX] in {
4175 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4176 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4179 let Predicates = [UseSSE2] in {
4180 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4181 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4184 //===---------------------------------------------------------------------===//
4185 // SSE2 - Packed Integer Comparison Instructions
4186 //===---------------------------------------------------------------------===//
4188 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4189 SSE_INTALU_ITINS_P, 1>;
4190 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4191 SSE_INTALU_ITINS_P, 1>;
4192 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4193 SSE_INTALU_ITINS_P, 1>;
4194 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4195 SSE_INTALU_ITINS_P, 0>;
4196 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4197 SSE_INTALU_ITINS_P, 0>;
4198 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4199 SSE_INTALU_ITINS_P, 0>;
4201 //===---------------------------------------------------------------------===//
4202 // SSE2 - Packed Integer Shuffle Instructions
4203 //===---------------------------------------------------------------------===//
4205 let ExeDomain = SSEPackedInt in {
4206 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4208 let Predicates = [HasAVX] in {
4209 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4210 (ins VR128:$src1, u8imm:$src2),
4211 !strconcat("v", OpcodeStr,
4212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4214 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4215 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4216 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4217 (ins i128mem:$src1, u8imm:$src2),
4218 !strconcat("v", OpcodeStr,
4219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4221 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4222 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4223 Sched<[WriteShuffleLd]>;
4226 let Predicates = [HasAVX2] in {
4227 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4228 (ins VR256:$src1, u8imm:$src2),
4229 !strconcat("v", OpcodeStr,
4230 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4232 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4233 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4234 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4235 (ins i256mem:$src1, u8imm:$src2),
4236 !strconcat("v", OpcodeStr,
4237 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4239 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4240 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4241 Sched<[WriteShuffleLd]>;
4244 let Predicates = [UseSSE2] in {
4245 def ri : Ii8<0x70, MRMSrcReg,
4246 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4247 !strconcat(OpcodeStr,
4248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4250 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4251 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4252 def mi : Ii8<0x70, MRMSrcMem,
4253 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4254 !strconcat(OpcodeStr,
4255 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4257 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4258 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4259 Sched<[WriteShuffleLd, ReadAfterLd]>;
4262 } // ExeDomain = SSEPackedInt
4264 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4265 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4266 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4268 let Predicates = [HasAVX] in {
4269 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4270 (VPSHUFDmi addr:$src1, imm:$imm)>;
4271 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4272 (VPSHUFDri VR128:$src1, imm:$imm)>;
4275 let Predicates = [UseSSE2] in {
4276 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4277 (PSHUFDmi addr:$src1, imm:$imm)>;
4278 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4279 (PSHUFDri VR128:$src1, imm:$imm)>;
4282 //===---------------------------------------------------------------------===//
4283 // Packed Integer Pack Instructions (SSE & AVX)
4284 //===---------------------------------------------------------------------===//
4286 let ExeDomain = SSEPackedInt in {
4287 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4288 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4289 PatFrag ld_frag, bit Is2Addr = 1> {
4290 def rr : PDI<opc, MRMSrcReg,
4291 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4294 !strconcat(OpcodeStr,
4295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4297 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4298 Sched<[WriteShuffle]>;
4299 def rm : PDI<opc, MRMSrcMem,
4300 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4302 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4303 !strconcat(OpcodeStr,
4304 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4306 (OutVT (OpNode VR128:$src1,
4307 (bc_frag (ld_frag addr:$src2)))))]>,
4308 Sched<[WriteShuffleLd, ReadAfterLd]>;
4311 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4312 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4313 def Yrr : PDI<opc, MRMSrcReg,
4314 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4315 !strconcat(OpcodeStr,
4316 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4318 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4319 Sched<[WriteShuffle]>;
4320 def Yrm : PDI<opc, MRMSrcMem,
4321 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4322 !strconcat(OpcodeStr,
4323 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4325 (OutVT (OpNode VR256:$src1,
4326 (bc_frag (loadv4i64 addr:$src2)))))]>,
4327 Sched<[WriteShuffleLd, ReadAfterLd]>;
4330 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4331 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4332 PatFrag ld_frag, bit Is2Addr = 1> {
4333 def rr : SS48I<opc, MRMSrcReg,
4334 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4337 !strconcat(OpcodeStr,
4338 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4340 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4341 Sched<[WriteShuffle]>;
4342 def rm : SS48I<opc, MRMSrcMem,
4343 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4345 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4346 !strconcat(OpcodeStr,
4347 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4349 (OutVT (OpNode VR128:$src1,
4350 (bc_frag (ld_frag addr:$src2)))))]>,
4351 Sched<[WriteShuffleLd, ReadAfterLd]>;
4354 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4355 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4356 def Yrr : SS48I<opc, MRMSrcReg,
4357 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4358 !strconcat(OpcodeStr,
4359 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4361 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4362 Sched<[WriteShuffle]>;
4363 def Yrm : SS48I<opc, MRMSrcMem,
4364 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4365 !strconcat(OpcodeStr,
4366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4368 (OutVT (OpNode VR256:$src1,
4369 (bc_frag (loadv4i64 addr:$src2)))))]>,
4370 Sched<[WriteShuffleLd, ReadAfterLd]>;
4373 let Predicates = [HasAVX] in {
4374 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4375 bc_v8i16, loadv2i64, 0>, VEX_4V;
4376 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4377 bc_v4i32, loadv2i64, 0>, VEX_4V;
4379 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4380 bc_v8i16, loadv2i64, 0>, VEX_4V;
4381 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4382 bc_v4i32, loadv2i64, 0>, VEX_4V;
4385 let Predicates = [HasAVX2] in {
4386 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4387 bc_v16i16>, VEX_4V, VEX_L;
4388 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4389 bc_v8i32>, VEX_4V, VEX_L;
4391 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4392 bc_v16i16>, VEX_4V, VEX_L;
4393 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4394 bc_v8i32>, VEX_4V, VEX_L;
4397 let Constraints = "$src1 = $dst" in {
4398 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4399 bc_v8i16, memopv2i64>;
4400 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4401 bc_v4i32, memopv2i64>;
4403 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4404 bc_v8i16, memopv2i64>;
4406 let Predicates = [HasSSE41] in
4407 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4408 bc_v4i32, memopv2i64>;
4410 } // ExeDomain = SSEPackedInt
4412 //===---------------------------------------------------------------------===//
4413 // SSE2 - Packed Integer Unpack Instructions
4414 //===---------------------------------------------------------------------===//
4416 let ExeDomain = SSEPackedInt in {
4417 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4418 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4420 def rr : PDI<opc, MRMSrcReg,
4421 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4423 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4424 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4425 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4426 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4427 def rm : PDI<opc, MRMSrcMem,
4428 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4430 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4431 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4432 [(set VR128:$dst, (OpNode VR128:$src1,
4433 (bc_frag (ld_frag addr:$src2))))],
4435 Sched<[WriteShuffleLd, ReadAfterLd]>;
4438 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4439 SDNode OpNode, PatFrag bc_frag> {
4440 def Yrr : PDI<opc, MRMSrcReg,
4441 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4442 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4443 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4444 Sched<[WriteShuffle]>;
4445 def Yrm : PDI<opc, MRMSrcMem,
4446 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4447 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4448 [(set VR256:$dst, (OpNode VR256:$src1,
4449 (bc_frag (loadv4i64 addr:$src2))))]>,
4450 Sched<[WriteShuffleLd, ReadAfterLd]>;
4453 let Predicates = [HasAVX] in {
4454 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4455 bc_v16i8, loadv2i64, 0>, VEX_4V;
4456 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4457 bc_v8i16, loadv2i64, 0>, VEX_4V;
4458 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4459 bc_v4i32, loadv2i64, 0>, VEX_4V;
4460 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4461 bc_v2i64, loadv2i64, 0>, VEX_4V;
4463 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4464 bc_v16i8, loadv2i64, 0>, VEX_4V;
4465 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4466 bc_v8i16, loadv2i64, 0>, VEX_4V;
4467 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4468 bc_v4i32, loadv2i64, 0>, VEX_4V;
4469 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4470 bc_v2i64, loadv2i64, 0>, VEX_4V;
4473 let Predicates = [HasAVX2] in {
4474 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4475 bc_v32i8>, VEX_4V, VEX_L;
4476 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4477 bc_v16i16>, VEX_4V, VEX_L;
4478 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4479 bc_v8i32>, VEX_4V, VEX_L;
4480 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4481 bc_v4i64>, VEX_4V, VEX_L;
4483 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4484 bc_v32i8>, VEX_4V, VEX_L;
4485 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4486 bc_v16i16>, VEX_4V, VEX_L;
4487 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4488 bc_v8i32>, VEX_4V, VEX_L;
4489 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4490 bc_v4i64>, VEX_4V, VEX_L;
4493 let Constraints = "$src1 = $dst" in {
4494 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4495 bc_v16i8, memopv2i64>;
4496 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4497 bc_v8i16, memopv2i64>;
4498 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4499 bc_v4i32, memopv2i64>;
4500 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4501 bc_v2i64, memopv2i64>;
4503 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4504 bc_v16i8, memopv2i64>;
4505 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4506 bc_v8i16, memopv2i64>;
4507 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4508 bc_v4i32, memopv2i64>;
4509 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4510 bc_v2i64, memopv2i64>;
4512 } // ExeDomain = SSEPackedInt
4514 //===---------------------------------------------------------------------===//
4515 // SSE2 - Packed Integer Extract and Insert
4516 //===---------------------------------------------------------------------===//
4518 let ExeDomain = SSEPackedInt in {
4519 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4520 def rri : Ii8<0xC4, MRMSrcReg,
4521 (outs VR128:$dst), (ins VR128:$src1,
4522 GR32orGR64:$src2, u8imm:$src3),
4524 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4525 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4527 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4528 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4529 def rmi : Ii8<0xC4, MRMSrcMem,
4530 (outs VR128:$dst), (ins VR128:$src1,
4531 i16mem:$src2, u8imm:$src3),
4533 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4534 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4536 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4537 imm:$src3))], IIC_SSE_PINSRW>,
4538 Sched<[WriteShuffleLd, ReadAfterLd]>;
4542 let Predicates = [HasAVX] in
4543 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4544 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4545 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4546 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4547 imm:$src2))]>, PD, VEX,
4548 Sched<[WriteShuffle]>;
4549 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4550 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4551 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4552 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4553 imm:$src2))], IIC_SSE_PEXTRW>,
4554 Sched<[WriteShuffleLd, ReadAfterLd]>;
4557 let Predicates = [HasAVX] in
4558 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4560 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4561 defm PINSRW : sse2_pinsrw, PD;
4563 } // ExeDomain = SSEPackedInt
4565 //===---------------------------------------------------------------------===//
4566 // SSE2 - Packed Mask Creation
4567 //===---------------------------------------------------------------------===//
4569 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4571 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4573 "pmovmskb\t{$src, $dst|$dst, $src}",
4574 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4575 IIC_SSE_MOVMSK>, VEX;
4577 let Predicates = [HasAVX2] in {
4578 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4580 "pmovmskb\t{$src, $dst|$dst, $src}",
4581 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4585 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4586 "pmovmskb\t{$src, $dst|$dst, $src}",
4587 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4590 } // ExeDomain = SSEPackedInt
4592 //===---------------------------------------------------------------------===//
4593 // SSE2 - Conditional Store
4594 //===---------------------------------------------------------------------===//
4596 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4598 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4599 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4600 (ins VR128:$src, VR128:$mask),
4601 "maskmovdqu\t{$mask, $src|$src, $mask}",
4602 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4603 IIC_SSE_MASKMOV>, VEX;
4604 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4605 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4606 (ins VR128:$src, VR128:$mask),
4607 "maskmovdqu\t{$mask, $src|$src, $mask}",
4608 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4609 IIC_SSE_MASKMOV>, VEX;
4611 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4612 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4613 "maskmovdqu\t{$mask, $src|$src, $mask}",
4614 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4616 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4617 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4618 "maskmovdqu\t{$mask, $src|$src, $mask}",
4619 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4622 } // ExeDomain = SSEPackedInt
4624 //===---------------------------------------------------------------------===//
4625 // SSE2 - Move Doubleword
4626 //===---------------------------------------------------------------------===//
4628 //===---------------------------------------------------------------------===//
4629 // Move Int Doubleword to Packed Double Int
4631 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4632 "movd\t{$src, $dst|$dst, $src}",
4634 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4635 VEX, Sched<[WriteMove]>;
4636 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4637 "movd\t{$src, $dst|$dst, $src}",
4639 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4641 VEX, Sched<[WriteLoad]>;
4642 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4643 "movq\t{$src, $dst|$dst, $src}",
4645 (v2i64 (scalar_to_vector GR64:$src)))],
4646 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4647 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4648 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4649 "movq\t{$src, $dst|$dst, $src}",
4650 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4651 let isCodeGenOnly = 1 in
4652 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4653 "movq\t{$src, $dst|$dst, $src}",
4654 [(set FR64:$dst, (bitconvert GR64:$src))],
4655 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4657 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4658 "movd\t{$src, $dst|$dst, $src}",
4660 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4662 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4663 "movd\t{$src, $dst|$dst, $src}",
4665 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4666 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4667 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4668 "mov{d|q}\t{$src, $dst|$dst, $src}",
4670 (v2i64 (scalar_to_vector GR64:$src)))],
4671 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4672 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4673 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4674 "mov{d|q}\t{$src, $dst|$dst, $src}",
4675 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4676 let isCodeGenOnly = 1 in
4677 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4678 "mov{d|q}\t{$src, $dst|$dst, $src}",
4679 [(set FR64:$dst, (bitconvert GR64:$src))],
4680 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4682 //===---------------------------------------------------------------------===//
4683 // Move Int Doubleword to Single Scalar
4685 let isCodeGenOnly = 1 in {
4686 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4687 "movd\t{$src, $dst|$dst, $src}",
4688 [(set FR32:$dst, (bitconvert GR32:$src))],
4689 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4691 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4692 "movd\t{$src, $dst|$dst, $src}",
4693 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4695 VEX, Sched<[WriteLoad]>;
4696 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4697 "movd\t{$src, $dst|$dst, $src}",
4698 [(set FR32:$dst, (bitconvert GR32:$src))],
4699 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4701 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4702 "movd\t{$src, $dst|$dst, $src}",
4703 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4704 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4707 //===---------------------------------------------------------------------===//
4708 // Move Packed Doubleword Int to Packed Double Int
4710 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4711 "movd\t{$src, $dst|$dst, $src}",
4712 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4713 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4715 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4716 (ins i32mem:$dst, VR128:$src),
4717 "movd\t{$src, $dst|$dst, $src}",
4718 [(store (i32 (vector_extract (v4i32 VR128:$src),
4719 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4720 VEX, Sched<[WriteStore]>;
4721 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4722 "movd\t{$src, $dst|$dst, $src}",
4723 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4724 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4726 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4727 "movd\t{$src, $dst|$dst, $src}",
4728 [(store (i32 (vector_extract (v4i32 VR128:$src),
4729 (iPTR 0))), addr:$dst)],
4730 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4732 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4733 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4735 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4736 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4738 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4739 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4741 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4742 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4744 //===---------------------------------------------------------------------===//
4745 // Move Packed Doubleword Int first element to Doubleword Int
4747 let SchedRW = [WriteMove] in {
4748 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4749 "movq\t{$src, $dst|$dst, $src}",
4750 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4755 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4756 "mov{d|q}\t{$src, $dst|$dst, $src}",
4757 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4762 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4763 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4764 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4765 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4766 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4767 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4768 "mov{d|q}\t{$src, $dst|$dst, $src}",
4769 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4771 //===---------------------------------------------------------------------===//
4772 // Bitcast FR64 <-> GR64
4774 let isCodeGenOnly = 1 in {
4775 let Predicates = [UseAVX] in
4776 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4777 "movq\t{$src, $dst|$dst, $src}",
4778 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4779 VEX, Sched<[WriteLoad]>;
4780 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4781 "movq\t{$src, $dst|$dst, $src}",
4782 [(set GR64:$dst, (bitconvert FR64:$src))],
4783 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4784 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4785 "movq\t{$src, $dst|$dst, $src}",
4786 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4787 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4789 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4790 "movq\t{$src, $dst|$dst, $src}",
4791 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4792 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4793 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4794 "mov{d|q}\t{$src, $dst|$dst, $src}",
4795 [(set GR64:$dst, (bitconvert FR64:$src))],
4796 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4797 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4798 "movq\t{$src, $dst|$dst, $src}",
4799 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4800 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4803 //===---------------------------------------------------------------------===//
4804 // Move Scalar Single to Double Int
4806 let isCodeGenOnly = 1 in {
4807 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4808 "movd\t{$src, $dst|$dst, $src}",
4809 [(set GR32:$dst, (bitconvert FR32:$src))],
4810 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4811 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4812 "movd\t{$src, $dst|$dst, $src}",
4813 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4814 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4815 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4816 "movd\t{$src, $dst|$dst, $src}",
4817 [(set GR32:$dst, (bitconvert FR32:$src))],
4818 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4819 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4820 "movd\t{$src, $dst|$dst, $src}",
4821 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4822 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4825 //===---------------------------------------------------------------------===//
4826 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4828 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4829 let AddedComplexity = 15 in {
4830 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4831 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4832 [(set VR128:$dst, (v2i64 (X86vzmovl
4833 (v2i64 (scalar_to_vector GR64:$src)))))],
4836 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4837 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4838 [(set VR128:$dst, (v2i64 (X86vzmovl
4839 (v2i64 (scalar_to_vector GR64:$src)))))],
4842 } // isCodeGenOnly, SchedRW
4844 let Predicates = [UseAVX] in {
4845 let AddedComplexity = 15 in
4846 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4847 (VMOVDI2PDIrr GR32:$src)>;
4849 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4850 // These instructions also write zeros in the high part of a 256-bit register.
4851 let AddedComplexity = 20 in {
4852 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4853 (VMOVDI2PDIrm addr:$src)>;
4854 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4855 (VMOVDI2PDIrm addr:$src)>;
4856 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4857 (VMOVDI2PDIrm addr:$src)>;
4858 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4859 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4860 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4862 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4863 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4864 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4865 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4866 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4867 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4868 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4871 let Predicates = [UseSSE2] in {
4872 let AddedComplexity = 15 in
4873 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4874 (MOVDI2PDIrr GR32:$src)>;
4876 let AddedComplexity = 20 in {
4877 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4878 (MOVDI2PDIrm addr:$src)>;
4879 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4880 (MOVDI2PDIrm addr:$src)>;
4881 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4882 (MOVDI2PDIrm addr:$src)>;
4886 // These are the correct encodings of the instructions so that we know how to
4887 // read correct assembly, even though we continue to emit the wrong ones for
4888 // compatibility with Darwin's buggy assembler.
4889 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4890 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4891 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4892 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4893 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4894 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4895 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4896 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4897 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4899 //===---------------------------------------------------------------------===//
4900 // SSE2 - Move Quadword
4901 //===---------------------------------------------------------------------===//
4903 //===---------------------------------------------------------------------===//
4904 // Move Quadword Int to Packed Quadword Int
4907 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4908 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4909 "vmovq\t{$src, $dst|$dst, $src}",
4911 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4912 VEX, Requires<[UseAVX]>;
4913 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4914 "movq\t{$src, $dst|$dst, $src}",
4916 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4918 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4919 } // ExeDomain, SchedRW
4921 //===---------------------------------------------------------------------===//
4922 // Move Packed Quadword Int to Quadword Int
4924 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4925 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4926 "movq\t{$src, $dst|$dst, $src}",
4927 [(store (i64 (vector_extract (v2i64 VR128:$src),
4928 (iPTR 0))), addr:$dst)],
4929 IIC_SSE_MOVDQ>, VEX;
4930 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4931 "movq\t{$src, $dst|$dst, $src}",
4932 [(store (i64 (vector_extract (v2i64 VR128:$src),
4933 (iPTR 0))), addr:$dst)],
4935 } // ExeDomain, SchedRW
4937 // For disassembler only
4938 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4939 SchedRW = [WriteVecLogic] in {
4940 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4941 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4942 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4943 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4946 //===---------------------------------------------------------------------===//
4947 // Store / copy lower 64-bits of a XMM register.
4949 let Predicates = [UseAVX] in
4950 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4951 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4952 let Predicates = [UseSSE2] in
4953 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4954 (MOVPQI2QImr addr:$dst, VR128:$src)>;
4956 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
4957 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4958 "vmovq\t{$src, $dst|$dst, $src}",
4960 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4961 (loadi64 addr:$src))))))],
4963 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4965 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4966 "movq\t{$src, $dst|$dst, $src}",
4968 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4969 (loadi64 addr:$src))))))],
4971 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4972 } // ExeDomain, isCodeGenOnly, AddedComplexity
4974 let Predicates = [UseAVX], AddedComplexity = 20 in {
4975 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4976 (VMOVZQI2PQIrm addr:$src)>;
4977 def : Pat<(v2i64 (X86vzload addr:$src)),
4978 (VMOVZQI2PQIrm addr:$src)>;
4979 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4980 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
4981 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4984 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4985 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4986 (MOVZQI2PQIrm addr:$src)>;
4987 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4990 let Predicates = [HasAVX] in {
4991 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4992 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4993 def : Pat<(v4i64 (X86vzload addr:$src)),
4994 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4997 //===---------------------------------------------------------------------===//
4998 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4999 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5001 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5002 let AddedComplexity = 15 in
5003 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5004 "vmovq\t{$src, $dst|$dst, $src}",
5005 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5007 XS, VEX, Requires<[UseAVX]>;
5008 let AddedComplexity = 15 in
5009 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5010 "movq\t{$src, $dst|$dst, $src}",
5011 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5013 XS, Requires<[UseSSE2]>;
5014 } // ExeDomain, SchedRW
5016 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5017 let AddedComplexity = 20 in
5018 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5019 "vmovq\t{$src, $dst|$dst, $src}",
5020 [(set VR128:$dst, (v2i64 (X86vzmovl
5021 (loadv2i64 addr:$src))))],
5023 XS, VEX, Requires<[UseAVX]>;
5024 let AddedComplexity = 20 in {
5025 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5026 "movq\t{$src, $dst|$dst, $src}",
5027 [(set VR128:$dst, (v2i64 (X86vzmovl
5028 (loadv2i64 addr:$src))))],
5030 XS, Requires<[UseSSE2]>;
5032 } // ExeDomain, isCodeGenOnly, SchedRW
5034 let AddedComplexity = 20 in {
5035 let Predicates = [UseAVX] in {
5036 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5037 (VMOVZPQILo2PQIrr VR128:$src)>;
5039 let Predicates = [UseSSE2] in {
5040 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5041 (MOVZPQILo2PQIrr VR128:$src)>;
5045 //===---------------------------------------------------------------------===//
5046 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5047 //===---------------------------------------------------------------------===//
5048 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5049 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5050 X86MemOperand x86memop> {
5051 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5052 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5053 [(set RC:$dst, (vt (OpNode RC:$src)))],
5054 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5055 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5056 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5057 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5058 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5061 let Predicates = [HasAVX] in {
5062 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5063 v4f32, VR128, loadv4f32, f128mem>, VEX;
5064 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5065 v4f32, VR128, loadv4f32, f128mem>, VEX;
5066 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5067 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5068 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5069 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5071 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5072 memopv4f32, f128mem>;
5073 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5074 memopv4f32, f128mem>;
5076 let Predicates = [HasAVX] in {
5077 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5078 (VMOVSHDUPrr VR128:$src)>;
5079 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5080 (VMOVSHDUPrm addr:$src)>;
5081 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5082 (VMOVSLDUPrr VR128:$src)>;
5083 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5084 (VMOVSLDUPrm addr:$src)>;
5085 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5086 (VMOVSHDUPYrr VR256:$src)>;
5087 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5088 (VMOVSHDUPYrm addr:$src)>;
5089 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5090 (VMOVSLDUPYrr VR256:$src)>;
5091 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5092 (VMOVSLDUPYrm addr:$src)>;
5095 let Predicates = [UseSSE3] in {
5096 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5097 (MOVSHDUPrr VR128:$src)>;
5098 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5099 (MOVSHDUPrm addr:$src)>;
5100 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5101 (MOVSLDUPrr VR128:$src)>;
5102 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5103 (MOVSLDUPrm addr:$src)>;
5106 //===---------------------------------------------------------------------===//
5107 // SSE3 - Replicate Double FP - MOVDDUP
5108 //===---------------------------------------------------------------------===//
5110 multiclass sse3_replicate_dfp<string OpcodeStr> {
5111 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5112 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5113 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5114 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5115 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5116 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5119 (scalar_to_vector (loadf64 addr:$src)))))],
5120 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5123 // FIXME: Merge with above classe when there're patterns for the ymm version
5124 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5125 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5127 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5128 Sched<[WriteFShuffle]>;
5129 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5133 (scalar_to_vector (loadf64 addr:$src)))))]>,
5137 let Predicates = [HasAVX] in {
5138 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5139 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5142 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5144 let Predicates = [HasAVX] in {
5145 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5146 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5147 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5148 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5149 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5150 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5151 def : Pat<(X86Movddup (bc_v2f64
5152 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5153 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5156 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5157 (VMOVDDUPYrm addr:$src)>;
5158 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5159 (VMOVDDUPYrm addr:$src)>;
5160 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5161 (VMOVDDUPYrm addr:$src)>;
5162 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5163 (VMOVDDUPYrr VR256:$src)>;
5166 let Predicates = [UseAVX, OptForSize] in {
5167 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5168 (VMOVDDUPrm addr:$src)>;
5169 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5170 (VMOVDDUPrm addr:$src)>;
5173 let Predicates = [UseSSE3] in {
5174 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5175 (MOVDDUPrm addr:$src)>;
5176 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5177 (MOVDDUPrm addr:$src)>;
5178 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5179 (MOVDDUPrm addr:$src)>;
5180 def : Pat<(X86Movddup (bc_v2f64
5181 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5182 (MOVDDUPrm addr:$src)>;
5185 //===---------------------------------------------------------------------===//
5186 // SSE3 - Move Unaligned Integer
5187 //===---------------------------------------------------------------------===//
5189 let SchedRW = [WriteLoad] in {
5190 let Predicates = [HasAVX] in {
5191 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5192 "vlddqu\t{$src, $dst|$dst, $src}",
5193 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5194 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5195 "vlddqu\t{$src, $dst|$dst, $src}",
5196 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5199 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5200 "lddqu\t{$src, $dst|$dst, $src}",
5201 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5205 //===---------------------------------------------------------------------===//
5206 // SSE3 - Arithmetic
5207 //===---------------------------------------------------------------------===//
5209 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5210 X86MemOperand x86memop, OpndItins itins,
5211 PatFrag ld_frag, bit Is2Addr = 1> {
5212 def rr : I<0xD0, MRMSrcReg,
5213 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5217 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5218 Sched<[itins.Sched]>;
5219 def rm : I<0xD0, MRMSrcMem,
5220 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5223 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5224 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5225 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5228 let Predicates = [HasAVX] in {
5229 let ExeDomain = SSEPackedSingle in {
5230 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5231 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5232 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5233 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5235 let ExeDomain = SSEPackedDouble in {
5236 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5237 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5238 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5239 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5242 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5243 let ExeDomain = SSEPackedSingle in
5244 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5245 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5246 let ExeDomain = SSEPackedDouble in
5247 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5248 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5251 // Patterns used to select 'addsub' instructions.
5252 let Predicates = [HasAVX] in {
5253 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5254 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5255 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5256 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5257 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5258 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5259 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5260 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5262 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5263 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5264 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5265 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5266 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5267 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5268 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5269 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5272 let Predicates = [UseSSE3] in {
5273 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5274 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5275 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5276 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5277 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5278 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5279 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5280 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5283 //===---------------------------------------------------------------------===//
5284 // SSE3 Instructions
5285 //===---------------------------------------------------------------------===//
5288 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5289 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5291 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5295 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5298 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5302 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5303 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5305 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5306 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5308 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5310 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5311 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5312 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5315 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5317 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5318 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5319 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5320 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5323 let Predicates = [HasAVX] in {
5324 let ExeDomain = SSEPackedSingle in {
5325 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5326 X86fhadd, loadv4f32, 0>, VEX_4V;
5327 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5328 X86fhsub, loadv4f32, 0>, VEX_4V;
5329 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5330 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5331 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5332 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5334 let ExeDomain = SSEPackedDouble in {
5335 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5336 X86fhadd, loadv2f64, 0>, VEX_4V;
5337 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5338 X86fhsub, loadv2f64, 0>, VEX_4V;
5339 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5340 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5341 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5342 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5346 let Constraints = "$src1 = $dst" in {
5347 let ExeDomain = SSEPackedSingle in {
5348 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5350 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5353 let ExeDomain = SSEPackedDouble in {
5354 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5356 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5361 //===---------------------------------------------------------------------===//
5362 // SSSE3 - Packed Absolute Instructions
5363 //===---------------------------------------------------------------------===//
5366 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5367 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5369 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5371 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5372 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5373 Sched<[WriteVecALU]>;
5375 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5377 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5380 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5381 Sched<[WriteVecALULd]>;
5384 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5385 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5386 Intrinsic IntId256> {
5387 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5389 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5390 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5391 Sched<[WriteVecALU]>;
5393 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5395 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5398 (bitconvert (loadv4i64 addr:$src))))]>,
5399 Sched<[WriteVecALULd]>;
5402 // Helper fragments to match sext vXi1 to vXiY.
5403 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5405 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5406 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5407 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5409 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5410 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5412 let Predicates = [HasAVX] in {
5413 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5415 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5417 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5421 (bc_v2i64 (v16i1sextv16i8)),
5422 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5423 (VPABSBrr128 VR128:$src)>;
5425 (bc_v2i64 (v8i1sextv8i16)),
5426 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5427 (VPABSWrr128 VR128:$src)>;
5429 (bc_v2i64 (v4i1sextv4i32)),
5430 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5431 (VPABSDrr128 VR128:$src)>;
5434 let Predicates = [HasAVX2] in {
5435 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5436 int_x86_avx2_pabs_b>, VEX, VEX_L;
5437 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5438 int_x86_avx2_pabs_w>, VEX, VEX_L;
5439 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5440 int_x86_avx2_pabs_d>, VEX, VEX_L;
5443 (bc_v4i64 (v32i1sextv32i8)),
5444 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5445 (VPABSBrr256 VR256:$src)>;
5447 (bc_v4i64 (v16i1sextv16i16)),
5448 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5449 (VPABSWrr256 VR256:$src)>;
5451 (bc_v4i64 (v8i1sextv8i32)),
5452 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5453 (VPABSDrr256 VR256:$src)>;
5456 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5458 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5460 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5463 let Predicates = [HasSSSE3] in {
5465 (bc_v2i64 (v16i1sextv16i8)),
5466 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5467 (PABSBrr128 VR128:$src)>;
5469 (bc_v2i64 (v8i1sextv8i16)),
5470 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5471 (PABSWrr128 VR128:$src)>;
5473 (bc_v2i64 (v4i1sextv4i32)),
5474 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5475 (PABSDrr128 VR128:$src)>;
5478 //===---------------------------------------------------------------------===//
5479 // SSSE3 - Packed Binary Operator Instructions
5480 //===---------------------------------------------------------------------===//
5482 let Sched = WriteVecALU in {
5483 def SSE_PHADDSUBD : OpndItins<
5484 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5486 def SSE_PHADDSUBSW : OpndItins<
5487 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5489 def SSE_PHADDSUBW : OpndItins<
5490 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5493 let Sched = WriteShuffle in
5494 def SSE_PSHUFB : OpndItins<
5495 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5497 let Sched = WriteVecALU in
5498 def SSE_PSIGN : OpndItins<
5499 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5501 let Sched = WriteVecIMul in
5502 def SSE_PMULHRSW : OpndItins<
5503 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5506 /// SS3I_binop_rm - Simple SSSE3 bin op
5507 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5508 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5509 X86MemOperand x86memop, OpndItins itins,
5511 let isCommutable = 1 in
5512 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5513 (ins RC:$src1, RC:$src2),
5515 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5516 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5517 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5518 Sched<[itins.Sched]>;
5519 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5520 (ins RC:$src1, x86memop:$src2),
5522 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5523 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5525 (OpVT (OpNode RC:$src1,
5526 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5527 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5530 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5531 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5532 Intrinsic IntId128, OpndItins itins,
5533 PatFrag ld_frag, bit Is2Addr = 1> {
5534 let isCommutable = 1 in
5535 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5536 (ins VR128:$src1, VR128:$src2),
5538 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5540 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5541 Sched<[itins.Sched]>;
5542 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5543 (ins VR128:$src1, i128mem:$src2),
5545 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5546 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5548 (IntId128 VR128:$src1,
5549 (bitconvert (ld_frag addr:$src2))))]>,
5550 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5553 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5555 X86FoldableSchedWrite Sched> {
5556 let isCommutable = 1 in
5557 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5558 (ins VR256:$src1, VR256:$src2),
5559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5560 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5562 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5563 (ins VR256:$src1, i256mem:$src2),
5564 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5566 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5567 Sched<[Sched.Folded, ReadAfterLd]>;
5570 let ImmT = NoImm, Predicates = [HasAVX] in {
5571 let isCommutable = 0 in {
5572 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5574 SSE_PHADDSUBW, 0>, VEX_4V;
5575 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5577 SSE_PHADDSUBD, 0>, VEX_4V;
5578 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5580 SSE_PHADDSUBW, 0>, VEX_4V;
5581 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5583 SSE_PHADDSUBD, 0>, VEX_4V;
5584 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5586 SSE_PSIGN, 0>, VEX_4V;
5587 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5589 SSE_PSIGN, 0>, VEX_4V;
5590 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5592 SSE_PSIGN, 0>, VEX_4V;
5593 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5595 SSE_PSHUFB, 0>, VEX_4V;
5596 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5597 int_x86_ssse3_phadd_sw_128,
5598 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5599 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5600 int_x86_ssse3_phsub_sw_128,
5601 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5602 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5603 int_x86_ssse3_pmadd_ub_sw_128,
5604 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5606 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5607 int_x86_ssse3_pmul_hr_sw_128,
5608 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5611 let ImmT = NoImm, Predicates = [HasAVX2] in {
5612 let isCommutable = 0 in {
5613 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5615 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5616 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5618 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5619 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5621 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5622 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5624 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5625 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5627 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5628 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5630 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5631 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5633 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5634 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5636 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5637 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5638 int_x86_avx2_phadd_sw,
5639 WriteVecALU>, VEX_4V, VEX_L;
5640 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5641 int_x86_avx2_phsub_sw,
5642 WriteVecALU>, VEX_4V, VEX_L;
5643 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5644 int_x86_avx2_pmadd_ub_sw,
5645 WriteVecIMul>, VEX_4V, VEX_L;
5647 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5648 int_x86_avx2_pmul_hr_sw,
5649 WriteVecIMul>, VEX_4V, VEX_L;
5652 // None of these have i8 immediate fields.
5653 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5654 let isCommutable = 0 in {
5655 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5656 memopv2i64, i128mem, SSE_PHADDSUBW>;
5657 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5658 memopv2i64, i128mem, SSE_PHADDSUBD>;
5659 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5660 memopv2i64, i128mem, SSE_PHADDSUBW>;
5661 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5662 memopv2i64, i128mem, SSE_PHADDSUBD>;
5663 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5664 memopv2i64, i128mem, SSE_PSIGN>;
5665 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5666 memopv2i64, i128mem, SSE_PSIGN>;
5667 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5668 memopv2i64, i128mem, SSE_PSIGN>;
5669 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5670 memopv2i64, i128mem, SSE_PSHUFB>;
5671 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5672 int_x86_ssse3_phadd_sw_128,
5673 SSE_PHADDSUBSW, memopv2i64>;
5674 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5675 int_x86_ssse3_phsub_sw_128,
5676 SSE_PHADDSUBSW, memopv2i64>;
5677 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5678 int_x86_ssse3_pmadd_ub_sw_128,
5679 SSE_PMADD, memopv2i64>;
5681 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5682 int_x86_ssse3_pmul_hr_sw_128,
5683 SSE_PMULHRSW, memopv2i64>;
5686 //===---------------------------------------------------------------------===//
5687 // SSSE3 - Packed Align Instruction Patterns
5688 //===---------------------------------------------------------------------===//
5690 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5691 let hasSideEffects = 0 in {
5692 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5693 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5695 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5697 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5698 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5700 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5701 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5703 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5705 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5706 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5710 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5711 let hasSideEffects = 0 in {
5712 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5713 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5715 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5716 []>, Sched<[WriteShuffle]>;
5718 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5719 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5721 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5722 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5726 let Predicates = [HasAVX] in
5727 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5728 let Predicates = [HasAVX2] in
5729 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5730 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5731 defm PALIGN : ssse3_palignr<"palignr">;
5733 let Predicates = [HasAVX2] in {
5734 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5735 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5736 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5737 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5738 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5739 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5740 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5741 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5744 let Predicates = [HasAVX] in {
5745 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5746 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5747 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5748 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5749 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5750 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5751 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5752 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5755 let Predicates = [UseSSSE3] in {
5756 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5757 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5758 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5759 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5760 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5761 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5762 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5763 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5766 //===---------------------------------------------------------------------===//
5767 // SSSE3 - Thread synchronization
5768 //===---------------------------------------------------------------------===//
5770 let SchedRW = [WriteSystem] in {
5771 let usesCustomInserter = 1 in {
5772 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5773 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5774 Requires<[HasSSE3]>;
5777 let Uses = [EAX, ECX, EDX] in
5778 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5779 TB, Requires<[HasSSE3]>;
5780 let Uses = [ECX, EAX] in
5781 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5782 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5783 TB, Requires<[HasSSE3]>;
5786 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5787 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5789 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5790 Requires<[Not64BitMode]>;
5791 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5792 Requires<[In64BitMode]>;
5794 //===----------------------------------------------------------------------===//
5795 // SSE4.1 - Packed Move with Sign/Zero Extend
5796 //===----------------------------------------------------------------------===//
5798 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5799 RegisterClass OutRC, RegisterClass InRC,
5801 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5804 Sched<[itins.Sched]>;
5806 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5809 itins.rm>, Sched<[itins.Sched.Folded]>;
5812 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5813 X86MemOperand MemOp, X86MemOperand MemYOp,
5814 OpndItins SSEItins, OpndItins AVXItins,
5815 OpndItins AVX2Itins> {
5816 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5817 let Predicates = [HasAVX] in
5818 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5819 VR128, VR128, AVXItins>, VEX;
5820 let Predicates = [HasAVX2] in
5821 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5822 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5825 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5826 X86MemOperand MemOp, X86MemOperand MemYOp> {
5827 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5829 SSE_INTALU_ITINS_SHUFF_P,
5830 DEFAULT_ITINS_SHUFFLESCHED,
5831 DEFAULT_ITINS_SHUFFLESCHED>;
5832 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5833 !strconcat("pmovzx", OpcodeStr),
5835 SSE_INTALU_ITINS_SHUFF_P,
5836 DEFAULT_ITINS_SHUFFLESCHED,
5837 DEFAULT_ITINS_SHUFFLESCHED>;
5840 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5841 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5842 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5844 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5845 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5847 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5850 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5851 // Register-Register patterns
5852 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5853 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5854 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5855 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5856 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5857 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5859 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5860 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5861 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5862 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5864 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5865 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5867 // On AVX2, we also support 256bit inputs.
5868 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5869 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5870 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5871 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5872 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5873 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5875 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5876 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5877 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5878 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5880 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5881 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5883 // Simple Register-Memory patterns
5884 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5885 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5886 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5887 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5888 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5889 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5891 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5892 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5893 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5894 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5896 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5897 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5899 // AVX2 Register-Memory patterns
5900 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5901 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5902 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5903 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5904 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5905 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5906 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5907 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5909 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5910 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5911 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5912 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5913 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5914 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5915 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5916 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5918 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5919 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5920 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5921 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5922 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5923 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5924 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5925 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5927 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5928 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5929 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5930 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5931 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5932 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5933 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5934 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5936 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5937 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5938 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5939 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5940 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5941 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5942 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5943 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5945 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5946 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5947 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5948 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5949 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5950 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5951 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5952 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5955 let Predicates = [HasAVX2] in {
5956 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
5957 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
5960 // SSE4.1/AVX patterns.
5961 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5962 SDNode ExtOp, PatFrag ExtLoad16> {
5963 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5964 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
5965 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
5966 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
5967 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
5968 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
5970 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
5971 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
5972 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
5973 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
5975 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
5976 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
5978 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5979 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
5980 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5981 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
5982 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5983 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
5985 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5986 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
5987 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5988 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
5990 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5991 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
5993 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5994 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
5995 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
5996 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
5997 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5998 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
5999 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6000 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6001 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6002 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6004 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6005 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6006 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6007 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6008 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6009 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6010 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6011 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6013 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6014 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6015 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6016 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6017 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6018 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6019 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6020 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6022 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6023 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6024 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6025 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6026 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6027 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6028 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6029 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6030 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6031 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6033 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6034 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6035 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6036 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6037 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6038 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6039 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6040 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6042 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6043 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6044 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6045 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6046 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6047 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6048 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6049 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6050 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6051 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6054 let Predicates = [HasAVX] in {
6055 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6056 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6059 let Predicates = [UseSSE41] in {
6060 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6061 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6064 //===----------------------------------------------------------------------===//
6065 // SSE4.1 - Extract Instructions
6066 //===----------------------------------------------------------------------===//
6068 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6069 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6070 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6071 (ins VR128:$src1, u8imm:$src2),
6072 !strconcat(OpcodeStr,
6073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6074 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6076 Sched<[WriteShuffle]>;
6077 let hasSideEffects = 0, mayStore = 1,
6078 SchedRW = [WriteShuffleLd, WriteRMW] in
6079 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6080 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6081 !strconcat(OpcodeStr,
6082 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6083 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6084 imm:$src2)))), addr:$dst)]>;
6087 let Predicates = [HasAVX] in
6088 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6090 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6093 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6094 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6095 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6096 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6097 (ins VR128:$src1, u8imm:$src2),
6098 !strconcat(OpcodeStr,
6099 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6100 []>, Sched<[WriteShuffle]>;
6102 let hasSideEffects = 0, mayStore = 1,
6103 SchedRW = [WriteShuffleLd, WriteRMW] in
6104 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6105 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6106 !strconcat(OpcodeStr,
6107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6108 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6109 imm:$src2)))), addr:$dst)]>;
6112 let Predicates = [HasAVX] in
6113 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6115 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6118 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6119 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6120 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6121 (ins VR128:$src1, u8imm:$src2),
6122 !strconcat(OpcodeStr,
6123 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6125 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6126 Sched<[WriteShuffle]>;
6127 let SchedRW = [WriteShuffleLd, WriteRMW] in
6128 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6129 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6130 !strconcat(OpcodeStr,
6131 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6132 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6136 let Predicates = [HasAVX] in
6137 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6139 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6141 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6142 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6143 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6144 (ins VR128:$src1, u8imm:$src2),
6145 !strconcat(OpcodeStr,
6146 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6148 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6149 Sched<[WriteShuffle]>, REX_W;
6150 let SchedRW = [WriteShuffleLd, WriteRMW] in
6151 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6152 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6153 !strconcat(OpcodeStr,
6154 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6155 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6156 addr:$dst)]>, REX_W;
6159 let Predicates = [HasAVX] in
6160 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6162 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6164 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6166 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6167 OpndItins itins = DEFAULT_ITINS> {
6168 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6169 (ins VR128:$src1, u8imm:$src2),
6170 !strconcat(OpcodeStr,
6171 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6172 [(set GR32orGR64:$dst,
6173 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6174 itins.rr>, Sched<[WriteFBlend]>;
6175 let SchedRW = [WriteFBlendLd, WriteRMW] in
6176 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6177 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6178 !strconcat(OpcodeStr,
6179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6180 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6181 addr:$dst)], itins.rm>;
6184 let ExeDomain = SSEPackedSingle in {
6185 let Predicates = [UseAVX] in
6186 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6187 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6190 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6191 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6194 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6196 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6199 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6200 Requires<[UseSSE41]>;
6202 //===----------------------------------------------------------------------===//
6203 // SSE4.1 - Insert Instructions
6204 //===----------------------------------------------------------------------===//
6206 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6207 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6208 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6210 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6212 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6214 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6215 Sched<[WriteShuffle]>;
6216 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6217 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6219 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6221 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6223 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6224 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6227 let Predicates = [HasAVX] in
6228 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6229 let Constraints = "$src1 = $dst" in
6230 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6232 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6233 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6234 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6236 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6238 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6240 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6241 Sched<[WriteShuffle]>;
6242 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6243 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6245 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6247 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6249 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6250 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6253 let Predicates = [HasAVX] in
6254 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6255 let Constraints = "$src1 = $dst" in
6256 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6258 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6259 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6260 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6262 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6264 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6266 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6267 Sched<[WriteShuffle]>;
6268 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6269 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6271 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6273 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6275 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6276 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6279 let Predicates = [HasAVX] in
6280 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6281 let Constraints = "$src1 = $dst" in
6282 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6284 // insertps has a few different modes, there's the first two here below which
6285 // are optimized inserts that won't zero arbitrary elements in the destination
6286 // vector. The next one matches the intrinsic and could zero arbitrary elements
6287 // in the target vector.
6288 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6289 OpndItins itins = DEFAULT_ITINS> {
6290 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6291 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6293 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6297 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6298 Sched<[WriteFShuffle]>;
6299 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6300 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6302 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6304 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6306 (X86insertps VR128:$src1,
6307 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6308 imm:$src3))], itins.rm>,
6309 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6312 let ExeDomain = SSEPackedSingle in {
6313 let Predicates = [UseAVX] in
6314 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6315 let Constraints = "$src1 = $dst" in
6316 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6319 let Predicates = [UseSSE41] in {
6320 // If we're inserting an element from a load or a null pshuf of a load,
6321 // fold the load into the insertps instruction.
6322 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6323 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6325 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6326 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6327 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6328 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6331 let Predicates = [UseAVX] in {
6332 // If we're inserting an element from a vbroadcast of a load, fold the
6333 // load into the X86insertps instruction.
6334 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6335 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6336 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6337 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6338 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6339 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6342 //===----------------------------------------------------------------------===//
6343 // SSE4.1 - Round Instructions
6344 //===----------------------------------------------------------------------===//
6346 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6347 X86MemOperand x86memop, RegisterClass RC,
6348 PatFrag mem_frag32, PatFrag mem_frag64,
6349 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6350 let ExeDomain = SSEPackedSingle in {
6351 // Intrinsic operation, reg.
6352 // Vector intrinsic operation, reg
6353 def PSr : SS4AIi8<opcps, MRMSrcReg,
6354 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6355 !strconcat(OpcodeStr,
6356 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6357 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6358 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6360 // Vector intrinsic operation, mem
6361 def PSm : SS4AIi8<opcps, MRMSrcMem,
6362 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6363 !strconcat(OpcodeStr,
6364 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6366 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6367 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6368 } // ExeDomain = SSEPackedSingle
6370 let ExeDomain = SSEPackedDouble in {
6371 // Vector intrinsic operation, reg
6372 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6373 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6374 !strconcat(OpcodeStr,
6375 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6376 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6377 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6379 // Vector intrinsic operation, mem
6380 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6381 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6382 !strconcat(OpcodeStr,
6383 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6385 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6386 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6387 } // ExeDomain = SSEPackedDouble
6390 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6393 Intrinsic F64Int, bit Is2Addr = 1> {
6394 let ExeDomain = GenericDomain in {
6396 let hasSideEffects = 0 in
6397 def SSr : SS4AIi8<opcss, MRMSrcReg,
6398 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6400 !strconcat(OpcodeStr,
6401 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6402 !strconcat(OpcodeStr,
6403 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6404 []>, Sched<[WriteFAdd]>;
6406 // Intrinsic operation, reg.
6407 let isCodeGenOnly = 1 in
6408 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6409 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6411 !strconcat(OpcodeStr,
6412 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6413 !strconcat(OpcodeStr,
6414 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6415 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6418 // Intrinsic operation, mem.
6419 def SSm : SS4AIi8<opcss, MRMSrcMem,
6420 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6422 !strconcat(OpcodeStr,
6423 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6424 !strconcat(OpcodeStr,
6425 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6427 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6428 Sched<[WriteFAddLd, ReadAfterLd]>;
6431 let hasSideEffects = 0 in
6432 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6433 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6435 !strconcat(OpcodeStr,
6436 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6437 !strconcat(OpcodeStr,
6438 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6439 []>, Sched<[WriteFAdd]>;
6441 // Intrinsic operation, reg.
6442 let isCodeGenOnly = 1 in
6443 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6444 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6446 !strconcat(OpcodeStr,
6447 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6448 !strconcat(OpcodeStr,
6449 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6450 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6453 // Intrinsic operation, mem.
6454 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6455 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6457 !strconcat(OpcodeStr,
6458 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6459 !strconcat(OpcodeStr,
6460 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6462 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6463 Sched<[WriteFAddLd, ReadAfterLd]>;
6464 } // ExeDomain = GenericDomain
6467 // FP round - roundss, roundps, roundsd, roundpd
6468 let Predicates = [HasAVX] in {
6470 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6471 loadv4f32, loadv2f64,
6472 int_x86_sse41_round_ps,
6473 int_x86_sse41_round_pd>, VEX;
6474 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6475 loadv8f32, loadv4f64,
6476 int_x86_avx_round_ps_256,
6477 int_x86_avx_round_pd_256>, VEX, VEX_L;
6478 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6479 int_x86_sse41_round_ss,
6480 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6483 let Predicates = [UseAVX] in {
6484 def : Pat<(ffloor FR32:$src),
6485 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6486 def : Pat<(f64 (ffloor FR64:$src)),
6487 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6488 def : Pat<(f32 (fnearbyint FR32:$src)),
6489 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6490 def : Pat<(f64 (fnearbyint FR64:$src)),
6491 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6492 def : Pat<(f32 (fceil FR32:$src)),
6493 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6494 def : Pat<(f64 (fceil FR64:$src)),
6495 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6496 def : Pat<(f32 (frint FR32:$src)),
6497 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6498 def : Pat<(f64 (frint FR64:$src)),
6499 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6500 def : Pat<(f32 (ftrunc FR32:$src)),
6501 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6502 def : Pat<(f64 (ftrunc FR64:$src)),
6503 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6506 let Predicates = [HasAVX] in {
6507 def : Pat<(v4f32 (ffloor VR128:$src)),
6508 (VROUNDPSr VR128:$src, (i32 0x1))>;
6509 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6510 (VROUNDPSr VR128:$src, (i32 0xC))>;
6511 def : Pat<(v4f32 (fceil VR128:$src)),
6512 (VROUNDPSr VR128:$src, (i32 0x2))>;
6513 def : Pat<(v4f32 (frint VR128:$src)),
6514 (VROUNDPSr VR128:$src, (i32 0x4))>;
6515 def : Pat<(v4f32 (ftrunc VR128:$src)),
6516 (VROUNDPSr VR128:$src, (i32 0x3))>;
6518 def : Pat<(v2f64 (ffloor VR128:$src)),
6519 (VROUNDPDr VR128:$src, (i32 0x1))>;
6520 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6521 (VROUNDPDr VR128:$src, (i32 0xC))>;
6522 def : Pat<(v2f64 (fceil VR128:$src)),
6523 (VROUNDPDr VR128:$src, (i32 0x2))>;
6524 def : Pat<(v2f64 (frint VR128:$src)),
6525 (VROUNDPDr VR128:$src, (i32 0x4))>;
6526 def : Pat<(v2f64 (ftrunc VR128:$src)),
6527 (VROUNDPDr VR128:$src, (i32 0x3))>;
6529 def : Pat<(v8f32 (ffloor VR256:$src)),
6530 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6531 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6532 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6533 def : Pat<(v8f32 (fceil VR256:$src)),
6534 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6535 def : Pat<(v8f32 (frint VR256:$src)),
6536 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6537 def : Pat<(v8f32 (ftrunc VR256:$src)),
6538 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6540 def : Pat<(v4f64 (ffloor VR256:$src)),
6541 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6542 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6543 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6544 def : Pat<(v4f64 (fceil VR256:$src)),
6545 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6546 def : Pat<(v4f64 (frint VR256:$src)),
6547 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6548 def : Pat<(v4f64 (ftrunc VR256:$src)),
6549 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6552 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6553 memopv4f32, memopv2f64,
6554 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6555 let Constraints = "$src1 = $dst" in
6556 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6557 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6559 let Predicates = [UseSSE41] in {
6560 def : Pat<(ffloor FR32:$src),
6561 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6562 def : Pat<(f64 (ffloor FR64:$src)),
6563 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6564 def : Pat<(f32 (fnearbyint FR32:$src)),
6565 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6566 def : Pat<(f64 (fnearbyint FR64:$src)),
6567 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6568 def : Pat<(f32 (fceil FR32:$src)),
6569 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6570 def : Pat<(f64 (fceil FR64:$src)),
6571 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6572 def : Pat<(f32 (frint FR32:$src)),
6573 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6574 def : Pat<(f64 (frint FR64:$src)),
6575 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6576 def : Pat<(f32 (ftrunc FR32:$src)),
6577 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6578 def : Pat<(f64 (ftrunc FR64:$src)),
6579 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6581 def : Pat<(v4f32 (ffloor VR128:$src)),
6582 (ROUNDPSr VR128:$src, (i32 0x1))>;
6583 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6584 (ROUNDPSr VR128:$src, (i32 0xC))>;
6585 def : Pat<(v4f32 (fceil VR128:$src)),
6586 (ROUNDPSr VR128:$src, (i32 0x2))>;
6587 def : Pat<(v4f32 (frint VR128:$src)),
6588 (ROUNDPSr VR128:$src, (i32 0x4))>;
6589 def : Pat<(v4f32 (ftrunc VR128:$src)),
6590 (ROUNDPSr VR128:$src, (i32 0x3))>;
6592 def : Pat<(v2f64 (ffloor VR128:$src)),
6593 (ROUNDPDr VR128:$src, (i32 0x1))>;
6594 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6595 (ROUNDPDr VR128:$src, (i32 0xC))>;
6596 def : Pat<(v2f64 (fceil VR128:$src)),
6597 (ROUNDPDr VR128:$src, (i32 0x2))>;
6598 def : Pat<(v2f64 (frint VR128:$src)),
6599 (ROUNDPDr VR128:$src, (i32 0x4))>;
6600 def : Pat<(v2f64 (ftrunc VR128:$src)),
6601 (ROUNDPDr VR128:$src, (i32 0x3))>;
6604 //===----------------------------------------------------------------------===//
6605 // SSE4.1 - Packed Bit Test
6606 //===----------------------------------------------------------------------===//
6608 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6609 // the intel intrinsic that corresponds to this.
6610 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6611 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6612 "vptest\t{$src2, $src1|$src1, $src2}",
6613 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6614 Sched<[WriteVecLogic]>, VEX;
6615 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6616 "vptest\t{$src2, $src1|$src1, $src2}",
6617 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6618 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6620 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6621 "vptest\t{$src2, $src1|$src1, $src2}",
6622 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6623 Sched<[WriteVecLogic]>, VEX, VEX_L;
6624 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6625 "vptest\t{$src2, $src1|$src1, $src2}",
6626 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6627 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6630 let Defs = [EFLAGS] in {
6631 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6632 "ptest\t{$src2, $src1|$src1, $src2}",
6633 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6634 Sched<[WriteVecLogic]>;
6635 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6636 "ptest\t{$src2, $src1|$src1, $src2}",
6637 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6638 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6641 // The bit test instructions below are AVX only
6642 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6643 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6644 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6645 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6646 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6647 Sched<[WriteVecLogic]>, VEX;
6648 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6649 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6650 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6651 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6654 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6655 let ExeDomain = SSEPackedSingle in {
6656 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6657 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6660 let ExeDomain = SSEPackedDouble in {
6661 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6662 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6667 //===----------------------------------------------------------------------===//
6668 // SSE4.1 - Misc Instructions
6669 //===----------------------------------------------------------------------===//
6671 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6672 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6673 "popcnt{w}\t{$src, $dst|$dst, $src}",
6674 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6675 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6677 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6678 "popcnt{w}\t{$src, $dst|$dst, $src}",
6679 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6680 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6681 Sched<[WriteFAddLd]>, OpSize16, XS;
6683 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6684 "popcnt{l}\t{$src, $dst|$dst, $src}",
6685 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6686 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6689 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6690 "popcnt{l}\t{$src, $dst|$dst, $src}",
6691 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6692 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6693 Sched<[WriteFAddLd]>, OpSize32, XS;
6695 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6696 "popcnt{q}\t{$src, $dst|$dst, $src}",
6697 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6698 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6699 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6700 "popcnt{q}\t{$src, $dst|$dst, $src}",
6701 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6702 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6703 Sched<[WriteFAddLd]>, XS;
6708 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6709 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6710 Intrinsic IntId128, PatFrag ld_frag,
6711 X86FoldableSchedWrite Sched> {
6712 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6715 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6717 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6721 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6722 Sched<[Sched.Folded]>;
6725 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6726 // model, although the naming is misleading.
6727 let Predicates = [HasAVX] in
6728 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6729 int_x86_sse41_phminposuw, loadv2i64,
6731 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6732 int_x86_sse41_phminposuw, memopv2i64,
6735 /// SS48I_binop_rm - Simple SSE41 binary operator.
6736 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6737 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6738 X86MemOperand x86memop, bit Is2Addr = 1,
6739 OpndItins itins = SSE_INTALU_ITINS_P> {
6740 let isCommutable = 1 in
6741 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6742 (ins RC:$src1, RC:$src2),
6744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6746 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6747 Sched<[itins.Sched]>;
6748 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6749 (ins RC:$src1, x86memop:$src2),
6751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6754 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6755 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6758 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6760 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6761 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6762 PatFrag memop_frag, X86MemOperand x86memop,
6764 bit IsCommutable = 0, bit Is2Addr = 1> {
6765 let isCommutable = IsCommutable in
6766 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6767 (ins RC:$src1, RC:$src2),
6769 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6771 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6772 Sched<[itins.Sched]>;
6773 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6774 (ins RC:$src1, x86memop:$src2),
6776 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6777 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6778 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6779 (bitconvert (memop_frag addr:$src2)))))]>,
6780 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6783 let Predicates = [HasAVX, NoVLX] in {
6784 let isCommutable = 0 in
6785 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6786 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6788 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6789 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6791 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6792 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6794 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6795 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6797 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6798 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6800 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6801 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6803 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6804 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6806 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6807 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6809 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6810 VR128, loadv2i64, i128mem,
6811 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6814 let Predicates = [HasAVX2, NoVLX] in {
6815 let isCommutable = 0 in
6816 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6817 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6819 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6820 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6822 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6823 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6825 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6826 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6828 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6829 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6831 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6832 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6834 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6835 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6837 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6838 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6840 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6841 VR256, loadv4i64, i256mem,
6842 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6845 let Constraints = "$src1 = $dst" in {
6846 let isCommutable = 0 in
6847 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6848 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6849 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6850 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6851 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6852 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6853 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6854 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6855 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6856 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6857 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6858 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6859 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6860 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6861 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6862 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6863 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6864 VR128, memopv2i64, i128mem,
6865 SSE_INTMUL_ITINS_P, 1>;
6868 let Predicates = [HasAVX, NoVLX] in {
6869 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6870 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6872 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6873 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6876 let Predicates = [HasAVX2] in {
6877 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6878 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6880 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6881 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6885 let Constraints = "$src1 = $dst" in {
6886 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6887 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6888 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6889 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6892 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6893 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6894 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6895 X86MemOperand x86memop, bit Is2Addr = 1,
6896 OpndItins itins = DEFAULT_ITINS> {
6897 let isCommutable = 1 in
6898 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6899 (ins RC:$src1, RC:$src2, u8imm:$src3),
6901 !strconcat(OpcodeStr,
6902 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6903 !strconcat(OpcodeStr,
6904 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6905 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6906 Sched<[itins.Sched]>;
6907 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6908 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6910 !strconcat(OpcodeStr,
6911 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6912 !strconcat(OpcodeStr,
6913 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6916 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6917 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6920 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6921 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6922 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6923 X86MemOperand x86memop, bit Is2Addr = 1,
6924 OpndItins itins = DEFAULT_ITINS> {
6925 let isCommutable = 1 in
6926 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6927 (ins RC:$src1, RC:$src2, u8imm:$src3),
6929 !strconcat(OpcodeStr,
6930 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6931 !strconcat(OpcodeStr,
6932 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6933 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6934 itins.rr>, Sched<[itins.Sched]>;
6935 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6936 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6938 !strconcat(OpcodeStr,
6939 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6940 !strconcat(OpcodeStr,
6941 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6943 (OpVT (OpNode RC:$src1,
6944 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6945 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6948 let Predicates = [HasAVX] in {
6949 let isCommutable = 0 in {
6950 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6951 VR128, loadv2i64, i128mem, 0,
6952 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
6955 let ExeDomain = SSEPackedSingle in {
6956 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
6957 VR128, loadv4f32, f128mem, 0,
6958 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
6959 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
6960 VR256, loadv8f32, f256mem, 0,
6961 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
6963 let ExeDomain = SSEPackedDouble in {
6964 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
6965 VR128, loadv2f64, f128mem, 0,
6966 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
6967 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
6968 VR256, loadv4f64, f256mem, 0,
6969 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
6971 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
6972 VR128, loadv2i64, i128mem, 0,
6973 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
6975 let ExeDomain = SSEPackedSingle in
6976 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6977 VR128, loadv4f32, f128mem, 0,
6978 SSE_DPPS_ITINS>, VEX_4V;
6979 let ExeDomain = SSEPackedDouble in
6980 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6981 VR128, loadv2f64, f128mem, 0,
6982 SSE_DPPS_ITINS>, VEX_4V;
6983 let ExeDomain = SSEPackedSingle in
6984 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6985 VR256, loadv8f32, i256mem, 0,
6986 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
6989 let Predicates = [HasAVX2] in {
6990 let isCommutable = 0 in {
6991 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6992 VR256, loadv4i64, i256mem, 0,
6993 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
6995 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
6996 VR256, loadv4i64, i256mem, 0,
6997 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7000 let Constraints = "$src1 = $dst" in {
7001 let isCommutable = 0 in {
7002 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7003 VR128, memopv2i64, i128mem,
7004 1, SSE_MPSADBW_ITINS>;
7006 let ExeDomain = SSEPackedSingle in
7007 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7008 VR128, memopv4f32, f128mem,
7009 1, SSE_INTALU_ITINS_FBLEND_P>;
7010 let ExeDomain = SSEPackedDouble in
7011 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7012 VR128, memopv2f64, f128mem,
7013 1, SSE_INTALU_ITINS_FBLEND_P>;
7014 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7015 VR128, memopv2i64, i128mem,
7016 1, SSE_INTALU_ITINS_BLEND_P>;
7017 let ExeDomain = SSEPackedSingle in
7018 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7019 VR128, memopv4f32, f128mem, 1,
7021 let ExeDomain = SSEPackedDouble in
7022 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7023 VR128, memopv2f64, f128mem, 1,
7027 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7028 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7029 RegisterClass RC, X86MemOperand x86memop,
7030 PatFrag mem_frag, Intrinsic IntId,
7031 X86FoldableSchedWrite Sched> {
7032 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7033 (ins RC:$src1, RC:$src2, RC:$src3),
7034 !strconcat(OpcodeStr,
7035 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7036 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7037 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7040 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7041 (ins RC:$src1, x86memop:$src2, RC:$src3),
7042 !strconcat(OpcodeStr,
7043 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7045 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7047 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7048 Sched<[Sched.Folded, ReadAfterLd]>;
7051 let Predicates = [HasAVX] in {
7052 let ExeDomain = SSEPackedDouble in {
7053 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7054 loadv2f64, int_x86_sse41_blendvpd,
7056 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7057 loadv4f64, int_x86_avx_blendv_pd_256,
7058 WriteFVarBlend>, VEX_L;
7059 } // ExeDomain = SSEPackedDouble
7060 let ExeDomain = SSEPackedSingle in {
7061 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7062 loadv4f32, int_x86_sse41_blendvps,
7064 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7065 loadv8f32, int_x86_avx_blendv_ps_256,
7066 WriteFVarBlend>, VEX_L;
7067 } // ExeDomain = SSEPackedSingle
7068 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7069 loadv2i64, int_x86_sse41_pblendvb,
7073 let Predicates = [HasAVX2] in {
7074 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7075 loadv4i64, int_x86_avx2_pblendvb,
7076 WriteVarBlend>, VEX_L;
7079 let Predicates = [HasAVX] in {
7080 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7081 (v16i8 VR128:$src2))),
7082 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7083 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7084 (v4i32 VR128:$src2))),
7085 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7086 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7087 (v4f32 VR128:$src2))),
7088 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7089 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7090 (v2i64 VR128:$src2))),
7091 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7092 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7093 (v2f64 VR128:$src2))),
7094 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7095 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7096 (v8i32 VR256:$src2))),
7097 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7098 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7099 (v8f32 VR256:$src2))),
7100 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7101 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7102 (v4i64 VR256:$src2))),
7103 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7104 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7105 (v4f64 VR256:$src2))),
7106 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7109 let Predicates = [HasAVX2] in {
7110 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7111 (v32i8 VR256:$src2))),
7112 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7116 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7117 // on targets where they have equal performance. These were changed to use
7118 // blends because blends have better throughput on SandyBridge and Haswell, but
7119 // movs[s/d] are 1-2 byte shorter instructions.
7120 let Predicates = [UseAVX] in {
7121 let AddedComplexity = 15 in {
7122 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7123 // MOVS{S,D} to the lower bits.
7124 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7125 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7126 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7127 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7128 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7129 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7130 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7131 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7133 // Move low f32 and clear high bits.
7134 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7135 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7137 // Move low f64 and clear high bits.
7138 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7139 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7142 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7143 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7144 (SUBREG_TO_REG (i32 0),
7145 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7147 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7148 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7149 (SUBREG_TO_REG (i64 0),
7150 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7153 // These will incur an FP/int domain crossing penalty, but it may be the only
7154 // way without AVX2. Do not add any complexity because we may be able to match
7155 // more optimal patterns defined earlier in this file.
7156 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7157 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7158 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7159 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7162 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7163 // on targets where they have equal performance. These were changed to use
7164 // blends because blends have better throughput on SandyBridge and Haswell, but
7165 // movs[s/d] are 1-2 byte shorter instructions.
7166 let Predicates = [UseSSE41] in {
7167 // With SSE41 we can use blends for these patterns.
7168 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7169 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7170 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7171 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7172 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7173 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7177 /// SS41I_ternary_int - SSE 4.1 ternary operator
7178 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7179 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7180 X86MemOperand x86memop, Intrinsic IntId,
7181 OpndItins itins = DEFAULT_ITINS> {
7182 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7183 (ins VR128:$src1, VR128:$src2),
7184 !strconcat(OpcodeStr,
7185 "\t{$src2, $dst|$dst, $src2}"),
7186 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7187 itins.rr>, Sched<[itins.Sched]>;
7189 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7190 (ins VR128:$src1, x86memop:$src2),
7191 !strconcat(OpcodeStr,
7192 "\t{$src2, $dst|$dst, $src2}"),
7195 (bitconvert (mem_frag addr:$src2)), XMM0))],
7196 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7200 let ExeDomain = SSEPackedDouble in
7201 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7202 int_x86_sse41_blendvpd,
7203 DEFAULT_ITINS_FBLENDSCHED>;
7204 let ExeDomain = SSEPackedSingle in
7205 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7206 int_x86_sse41_blendvps,
7207 DEFAULT_ITINS_FBLENDSCHED>;
7208 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7209 int_x86_sse41_pblendvb,
7210 DEFAULT_ITINS_VARBLENDSCHED>;
7212 // Aliases with the implicit xmm0 argument
7213 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7214 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7215 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7216 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7217 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7218 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7219 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7220 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7221 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7222 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7223 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7224 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7226 let Predicates = [UseSSE41] in {
7227 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7228 (v16i8 VR128:$src2))),
7229 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7230 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7231 (v4i32 VR128:$src2))),
7232 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7233 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7234 (v4f32 VR128:$src2))),
7235 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7236 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7237 (v2i64 VR128:$src2))),
7238 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7239 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7240 (v2f64 VR128:$src2))),
7241 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7244 let SchedRW = [WriteLoad] in {
7245 let Predicates = [HasAVX] in
7246 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7247 "vmovntdqa\t{$src, $dst|$dst, $src}",
7248 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7250 let Predicates = [HasAVX2] in
7251 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7252 "vmovntdqa\t{$src, $dst|$dst, $src}",
7253 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7255 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7256 "movntdqa\t{$src, $dst|$dst, $src}",
7257 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7260 //===----------------------------------------------------------------------===//
7261 // SSE4.2 - Compare Instructions
7262 //===----------------------------------------------------------------------===//
7264 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7265 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7266 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7267 X86MemOperand x86memop, bit Is2Addr = 1> {
7268 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7269 (ins RC:$src1, RC:$src2),
7271 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7272 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7273 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7274 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7275 (ins RC:$src1, x86memop:$src2),
7277 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7278 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7280 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7283 let Predicates = [HasAVX] in
7284 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7285 loadv2i64, i128mem, 0>, VEX_4V;
7287 let Predicates = [HasAVX2] in
7288 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7289 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7291 let Constraints = "$src1 = $dst" in
7292 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7293 memopv2i64, i128mem>;
7295 //===----------------------------------------------------------------------===//
7296 // SSE4.2 - String/text Processing Instructions
7297 //===----------------------------------------------------------------------===//
7299 // Packed Compare Implicit Length Strings, Return Mask
7300 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7301 def REG : PseudoI<(outs VR128:$dst),
7302 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7303 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7305 def MEM : PseudoI<(outs VR128:$dst),
7306 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7307 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7308 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7311 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7312 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7314 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7315 Requires<[UseSSE42]>;
7318 multiclass pcmpistrm_SS42AI<string asm> {
7319 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7320 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7321 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7322 []>, Sched<[WritePCmpIStrM]>;
7324 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7325 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7326 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7327 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7330 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7331 let Predicates = [HasAVX] in
7332 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7333 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7336 // Packed Compare Explicit Length Strings, Return Mask
7337 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7338 def REG : PseudoI<(outs VR128:$dst),
7339 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7340 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7341 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7342 def MEM : PseudoI<(outs VR128:$dst),
7343 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7344 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7345 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7348 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7349 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7351 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7352 Requires<[UseSSE42]>;
7355 multiclass SS42AI_pcmpestrm<string asm> {
7356 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7357 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7358 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7359 []>, Sched<[WritePCmpEStrM]>;
7361 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7362 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7363 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7364 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7367 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7368 let Predicates = [HasAVX] in
7369 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7370 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7373 // Packed Compare Implicit Length Strings, Return Index
7374 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7375 def REG : PseudoI<(outs GR32:$dst),
7376 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7377 [(set GR32:$dst, EFLAGS,
7378 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7379 def MEM : PseudoI<(outs GR32:$dst),
7380 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7381 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7382 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7385 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7386 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7388 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7389 Requires<[UseSSE42]>;
7392 multiclass SS42AI_pcmpistri<string asm> {
7393 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7394 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7395 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7396 []>, Sched<[WritePCmpIStrI]>;
7398 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7399 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7400 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7401 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7404 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7405 let Predicates = [HasAVX] in
7406 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7407 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7410 // Packed Compare Explicit Length Strings, Return Index
7411 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7412 def REG : PseudoI<(outs GR32:$dst),
7413 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7414 [(set GR32:$dst, EFLAGS,
7415 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7416 def MEM : PseudoI<(outs GR32:$dst),
7417 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7418 [(set GR32:$dst, EFLAGS,
7419 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7423 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7424 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7426 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7427 Requires<[UseSSE42]>;
7430 multiclass SS42AI_pcmpestri<string asm> {
7431 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7432 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7433 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7434 []>, Sched<[WritePCmpEStrI]>;
7436 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7437 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7438 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7439 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7442 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7443 let Predicates = [HasAVX] in
7444 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7445 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7448 //===----------------------------------------------------------------------===//
7449 // SSE4.2 - CRC Instructions
7450 //===----------------------------------------------------------------------===//
7452 // No CRC instructions have AVX equivalents
7454 // crc intrinsic instruction
7455 // This set of instructions are only rm, the only difference is the size
7457 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7458 RegisterClass RCIn, SDPatternOperator Int> :
7459 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7460 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7461 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7464 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7465 X86MemOperand x86memop, SDPatternOperator Int> :
7466 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7467 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7468 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7469 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7471 let Constraints = "$src1 = $dst" in {
7472 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7473 int_x86_sse42_crc32_32_8>;
7474 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7475 int_x86_sse42_crc32_32_8>;
7476 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7477 int_x86_sse42_crc32_32_16>, OpSize16;
7478 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7479 int_x86_sse42_crc32_32_16>, OpSize16;
7480 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7481 int_x86_sse42_crc32_32_32>, OpSize32;
7482 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7483 int_x86_sse42_crc32_32_32>, OpSize32;
7484 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7485 int_x86_sse42_crc32_64_64>, REX_W;
7486 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7487 int_x86_sse42_crc32_64_64>, REX_W;
7488 let hasSideEffects = 0 in {
7490 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7492 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7497 //===----------------------------------------------------------------------===//
7498 // SHA-NI Instructions
7499 //===----------------------------------------------------------------------===//
7501 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7503 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7504 (ins VR128:$src1, VR128:$src2),
7505 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7507 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7508 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7510 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7511 (ins VR128:$src1, i128mem:$src2),
7512 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7514 (set VR128:$dst, (IntId VR128:$src1,
7515 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7516 (set VR128:$dst, (IntId VR128:$src1,
7517 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7520 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7521 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7522 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7523 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7525 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7526 (i8 imm:$src3)))]>, TA;
7527 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7528 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7529 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7531 (int_x86_sha1rnds4 VR128:$src1,
7532 (bc_v4i32 (memopv2i64 addr:$src2)),
7533 (i8 imm:$src3)))]>, TA;
7535 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7536 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7537 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7540 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7542 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7543 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7546 // Aliases with explicit %xmm0
7547 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7548 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7549 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7550 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7552 //===----------------------------------------------------------------------===//
7553 // AES-NI Instructions
7554 //===----------------------------------------------------------------------===//
7556 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7557 PatFrag ld_frag, bit Is2Addr = 1> {
7558 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7559 (ins VR128:$src1, VR128:$src2),
7561 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7562 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7563 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7564 Sched<[WriteAESDecEnc]>;
7565 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7566 (ins VR128:$src1, i128mem:$src2),
7568 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7569 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7571 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7572 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7575 // Perform One Round of an AES Encryption/Decryption Flow
7576 let Predicates = [HasAVX, HasAES] in {
7577 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7578 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7579 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7580 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7581 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7582 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7583 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7584 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7587 let Constraints = "$src1 = $dst" in {
7588 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7589 int_x86_aesni_aesenc, memopv2i64>;
7590 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7591 int_x86_aesni_aesenclast, memopv2i64>;
7592 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7593 int_x86_aesni_aesdec, memopv2i64>;
7594 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7595 int_x86_aesni_aesdeclast, memopv2i64>;
7598 // Perform the AES InvMixColumn Transformation
7599 let Predicates = [HasAVX, HasAES] in {
7600 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7602 "vaesimc\t{$src1, $dst|$dst, $src1}",
7604 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7606 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7607 (ins i128mem:$src1),
7608 "vaesimc\t{$src1, $dst|$dst, $src1}",
7609 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7610 Sched<[WriteAESIMCLd]>, VEX;
7612 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7614 "aesimc\t{$src1, $dst|$dst, $src1}",
7616 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7617 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7618 (ins i128mem:$src1),
7619 "aesimc\t{$src1, $dst|$dst, $src1}",
7620 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7621 Sched<[WriteAESIMCLd]>;
7623 // AES Round Key Generation Assist
7624 let Predicates = [HasAVX, HasAES] in {
7625 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7626 (ins VR128:$src1, u8imm:$src2),
7627 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7629 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7630 Sched<[WriteAESKeyGen]>, VEX;
7631 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7632 (ins i128mem:$src1, u8imm:$src2),
7633 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7635 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7636 Sched<[WriteAESKeyGenLd]>, VEX;
7638 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7639 (ins VR128:$src1, u8imm:$src2),
7640 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7642 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7643 Sched<[WriteAESKeyGen]>;
7644 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7645 (ins i128mem:$src1, u8imm:$src2),
7646 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7648 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7649 Sched<[WriteAESKeyGenLd]>;
7651 //===----------------------------------------------------------------------===//
7652 // PCLMUL Instructions
7653 //===----------------------------------------------------------------------===//
7655 // AVX carry-less Multiplication instructions
7656 let isCommutable = 1 in
7657 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7658 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7659 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7661 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7662 Sched<[WriteCLMul]>;
7664 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7665 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7666 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7667 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7668 (loadv2i64 addr:$src2), imm:$src3))]>,
7669 Sched<[WriteCLMulLd, ReadAfterLd]>;
7671 // Carry-less Multiplication instructions
7672 let Constraints = "$src1 = $dst" in {
7673 let isCommutable = 1 in
7674 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7675 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7676 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7678 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7679 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7681 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7682 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7683 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7684 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7685 (memopv2i64 addr:$src2), imm:$src3))],
7686 IIC_SSE_PCLMULQDQ_RM>,
7687 Sched<[WriteCLMulLd, ReadAfterLd]>;
7688 } // Constraints = "$src1 = $dst"
7691 multiclass pclmul_alias<string asm, int immop> {
7692 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7693 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7695 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7696 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7698 def : InstAlias<!strconcat("vpclmul", asm,
7699 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7700 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7703 def : InstAlias<!strconcat("vpclmul", asm,
7704 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7705 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7708 defm : pclmul_alias<"hqhq", 0x11>;
7709 defm : pclmul_alias<"hqlq", 0x01>;
7710 defm : pclmul_alias<"lqhq", 0x10>;
7711 defm : pclmul_alias<"lqlq", 0x00>;
7713 //===----------------------------------------------------------------------===//
7714 // SSE4A Instructions
7715 //===----------------------------------------------------------------------===//
7717 let Predicates = [HasSSE4A] in {
7719 let Constraints = "$src = $dst" in {
7720 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7721 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7722 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7723 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7725 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7726 (ins VR128:$src, VR128:$mask),
7727 "extrq\t{$mask, $src|$src, $mask}",
7728 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7729 VR128:$mask))]>, PD;
7731 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7732 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7733 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7734 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7735 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7736 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7737 (ins VR128:$src, VR128:$mask),
7738 "insertq\t{$mask, $src|$src, $mask}",
7739 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7740 VR128:$mask))]>, XD;
7743 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7744 "movntss\t{$src, $dst|$dst, $src}",
7745 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7747 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7748 "movntsd\t{$src, $dst|$dst, $src}",
7749 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7752 //===----------------------------------------------------------------------===//
7754 //===----------------------------------------------------------------------===//
7756 //===----------------------------------------------------------------------===//
7757 // VBROADCAST - Load from memory and broadcast to all elements of the
7758 // destination operand
7760 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7761 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7762 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7764 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7766 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7767 X86MemOperand x86memop, ValueType VT,
7768 PatFrag ld_frag, SchedWrite Sched> :
7769 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7770 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7771 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7772 Sched<[Sched]>, VEX {
7776 // AVX2 adds register forms
7777 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7778 Intrinsic Int, SchedWrite Sched> :
7779 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7780 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7781 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7783 let ExeDomain = SSEPackedSingle in {
7784 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7785 f32mem, v4f32, loadf32, WriteLoad>;
7786 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7787 f32mem, v8f32, loadf32,
7788 WriteFShuffleLd>, VEX_L;
7790 let ExeDomain = SSEPackedDouble in
7791 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7792 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7793 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7794 int_x86_avx_vbroadcastf128_pd_256,
7795 WriteFShuffleLd>, VEX_L;
7797 let ExeDomain = SSEPackedSingle in {
7798 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7799 int_x86_avx2_vbroadcast_ss_ps,
7801 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7802 int_x86_avx2_vbroadcast_ss_ps_256,
7803 WriteFShuffle256>, VEX_L;
7805 let ExeDomain = SSEPackedDouble in
7806 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7807 int_x86_avx2_vbroadcast_sd_pd_256,
7808 WriteFShuffle256>, VEX_L;
7810 let Predicates = [HasAVX2] in
7811 def VBROADCASTI128 : avx_broadcast_no_int<0x5A, "vbroadcasti128", VR256,
7812 i128mem, v4i64, loadv2i64,
7815 let Predicates = [HasAVX] in
7816 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7817 (VBROADCASTF128 addr:$src)>;
7820 //===----------------------------------------------------------------------===//
7821 // VINSERTF128 - Insert packed floating-point values
7823 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7824 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7825 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7826 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7827 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7829 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7830 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7831 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7832 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7835 let Predicates = [HasAVX] in {
7836 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7838 (VINSERTF128rr VR256:$src1, VR128:$src2,
7839 (INSERT_get_vinsert128_imm VR256:$ins))>;
7840 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7842 (VINSERTF128rr VR256:$src1, VR128:$src2,
7843 (INSERT_get_vinsert128_imm VR256:$ins))>;
7845 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7847 (VINSERTF128rm VR256:$src1, addr:$src2,
7848 (INSERT_get_vinsert128_imm VR256:$ins))>;
7849 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7851 (VINSERTF128rm VR256:$src1, addr:$src2,
7852 (INSERT_get_vinsert128_imm VR256:$ins))>;
7855 let Predicates = [HasAVX1Only] in {
7856 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7858 (VINSERTF128rr VR256:$src1, VR128:$src2,
7859 (INSERT_get_vinsert128_imm VR256:$ins))>;
7860 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7862 (VINSERTF128rr VR256:$src1, VR128:$src2,
7863 (INSERT_get_vinsert128_imm VR256:$ins))>;
7864 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7866 (VINSERTF128rr VR256:$src1, VR128:$src2,
7867 (INSERT_get_vinsert128_imm VR256:$ins))>;
7868 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7870 (VINSERTF128rr VR256:$src1, VR128:$src2,
7871 (INSERT_get_vinsert128_imm VR256:$ins))>;
7873 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7875 (VINSERTF128rm VR256:$src1, addr:$src2,
7876 (INSERT_get_vinsert128_imm VR256:$ins))>;
7877 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7878 (bc_v4i32 (loadv2i64 addr:$src2)),
7880 (VINSERTF128rm VR256:$src1, addr:$src2,
7881 (INSERT_get_vinsert128_imm VR256:$ins))>;
7882 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7883 (bc_v16i8 (loadv2i64 addr:$src2)),
7885 (VINSERTF128rm VR256:$src1, addr:$src2,
7886 (INSERT_get_vinsert128_imm VR256:$ins))>;
7887 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7888 (bc_v8i16 (loadv2i64 addr:$src2)),
7890 (VINSERTF128rm VR256:$src1, addr:$src2,
7891 (INSERT_get_vinsert128_imm VR256:$ins))>;
7894 //===----------------------------------------------------------------------===//
7895 // VEXTRACTF128 - Extract packed floating-point values
7897 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7898 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7899 (ins VR256:$src1, u8imm:$src2),
7900 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7901 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7903 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7904 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7905 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7906 []>, Sched<[WriteStore]>, VEX, VEX_L;
7910 let Predicates = [HasAVX] in {
7911 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7912 (v4f32 (VEXTRACTF128rr
7913 (v8f32 VR256:$src1),
7914 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7915 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7916 (v2f64 (VEXTRACTF128rr
7917 (v4f64 VR256:$src1),
7918 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7920 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7921 (iPTR imm))), addr:$dst),
7922 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7923 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7924 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7925 (iPTR imm))), addr:$dst),
7926 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7927 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7930 let Predicates = [HasAVX1Only] in {
7931 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7932 (v2i64 (VEXTRACTF128rr
7933 (v4i64 VR256:$src1),
7934 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7935 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7936 (v4i32 (VEXTRACTF128rr
7937 (v8i32 VR256:$src1),
7938 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7939 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7940 (v8i16 (VEXTRACTF128rr
7941 (v16i16 VR256:$src1),
7942 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7943 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7944 (v16i8 (VEXTRACTF128rr
7945 (v32i8 VR256:$src1),
7946 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7948 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7949 (iPTR imm))), addr:$dst),
7950 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7951 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7952 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7953 (iPTR imm))), addr:$dst),
7954 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7955 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7956 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7957 (iPTR imm))), addr:$dst),
7958 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7959 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7960 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7961 (iPTR imm))), addr:$dst),
7962 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7963 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7966 //===----------------------------------------------------------------------===//
7967 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7969 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7970 Intrinsic IntLd, Intrinsic IntLd256,
7971 Intrinsic IntSt, Intrinsic IntSt256> {
7972 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7973 (ins VR128:$src1, f128mem:$src2),
7974 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7975 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7977 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7978 (ins VR256:$src1, f256mem:$src2),
7979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7980 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7982 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7983 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7984 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7985 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7986 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7987 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7989 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7992 let ExeDomain = SSEPackedSingle in
7993 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7994 int_x86_avx_maskload_ps,
7995 int_x86_avx_maskload_ps_256,
7996 int_x86_avx_maskstore_ps,
7997 int_x86_avx_maskstore_ps_256>;
7998 let ExeDomain = SSEPackedDouble in
7999 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8000 int_x86_avx_maskload_pd,
8001 int_x86_avx_maskload_pd_256,
8002 int_x86_avx_maskstore_pd,
8003 int_x86_avx_maskstore_pd_256>;
8005 //===----------------------------------------------------------------------===//
8006 // VPERMIL - Permute Single and Double Floating-Point Values
8008 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8009 RegisterClass RC, X86MemOperand x86memop_f,
8010 X86MemOperand x86memop_i, PatFrag i_frag,
8011 Intrinsic IntVar, ValueType vt> {
8012 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8013 (ins RC:$src1, RC:$src2),
8014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8015 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8016 Sched<[WriteFShuffle]>;
8017 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8018 (ins RC:$src1, x86memop_i:$src2),
8019 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8020 [(set RC:$dst, (IntVar RC:$src1,
8021 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8022 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8024 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8025 (ins RC:$src1, u8imm:$src2),
8026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8027 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8028 Sched<[WriteFShuffle]>;
8029 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8030 (ins x86memop_f:$src1, u8imm:$src2),
8031 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8033 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8034 Sched<[WriteFShuffleLd]>;
8037 let ExeDomain = SSEPackedSingle in {
8038 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8039 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8040 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8041 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8043 let ExeDomain = SSEPackedDouble in {
8044 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8045 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8046 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8047 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8050 let Predicates = [HasAVX] in {
8051 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8052 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8053 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8054 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8055 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8056 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8057 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8058 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8060 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8061 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8062 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8063 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8064 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8066 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8067 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8068 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8070 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8071 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8072 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8073 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8074 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8075 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8076 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8077 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8079 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8080 (VPERMILPDri VR128:$src1, imm:$imm)>;
8081 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8082 (VPERMILPDmi addr:$src1, imm:$imm)>;
8085 //===----------------------------------------------------------------------===//
8086 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8088 let ExeDomain = SSEPackedSingle in {
8089 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8090 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8091 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8092 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8093 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8094 Sched<[WriteFShuffle]>;
8095 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8096 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8097 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8098 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8099 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8100 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8103 let Predicates = [HasAVX] in {
8104 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8105 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8106 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8107 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8108 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8111 let Predicates = [HasAVX1Only] in {
8112 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8113 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8114 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8115 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8116 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8117 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8118 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8119 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8121 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8122 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8123 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8124 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8125 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8126 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8127 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8128 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8129 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8130 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8131 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8132 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8135 //===----------------------------------------------------------------------===//
8136 // VZERO - Zero YMM registers
8138 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8139 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8140 // Zero All YMM registers
8141 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8142 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8144 // Zero Upper bits of YMM registers
8145 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8146 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8149 //===----------------------------------------------------------------------===//
8150 // Half precision conversion instructions
8151 //===----------------------------------------------------------------------===//
8152 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8153 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8154 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8155 [(set RC:$dst, (Int VR128:$src))]>,
8156 T8PD, VEX, Sched<[WriteCvtF2F]>;
8157 let hasSideEffects = 0, mayLoad = 1 in
8158 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8159 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8160 Sched<[WriteCvtF2FLd]>;
8163 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8164 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8165 (ins RC:$src1, i32u8imm:$src2),
8166 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8167 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8168 TAPD, VEX, Sched<[WriteCvtF2F]>;
8169 let hasSideEffects = 0, mayStore = 1,
8170 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8171 def mr : Ii8<0x1D, MRMDestMem, (outs),
8172 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8173 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8177 let Predicates = [HasF16C] in {
8178 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8179 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8180 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8181 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8183 // Pattern match vcvtph2ps of a scalar i64 load.
8184 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8185 (VCVTPH2PSrm addr:$src)>;
8186 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8187 (VCVTPH2PSrm addr:$src)>;
8189 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8190 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8192 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8193 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8194 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8196 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8197 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8199 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8202 // Patterns for matching conversions from float to half-float and vice versa.
8203 let Predicates = [HasF16C] in {
8204 def : Pat<(fp_to_f16 FR32:$src),
8205 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8206 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8208 def : Pat<(f16_to_fp GR16:$src),
8209 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8210 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8212 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8213 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8214 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8217 //===----------------------------------------------------------------------===//
8218 // AVX2 Instructions
8219 //===----------------------------------------------------------------------===//
8221 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8222 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8223 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8224 X86MemOperand x86memop> {
8225 let isCommutable = 1 in
8226 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8227 (ins RC:$src1, RC:$src2, u8imm:$src3),
8228 !strconcat(OpcodeStr,
8229 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8230 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8231 Sched<[WriteBlend]>, VEX_4V;
8232 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8233 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8234 !strconcat(OpcodeStr,
8235 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8237 (OpVT (OpNode RC:$src1,
8238 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8239 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8242 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8243 VR128, loadv2i64, i128mem>;
8244 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8245 VR256, loadv4i64, i256mem>, VEX_L;
8247 //===----------------------------------------------------------------------===//
8248 // VPBROADCAST - Load from memory and broadcast to all elements of the
8249 // destination operand
8251 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8252 X86MemOperand x86memop, PatFrag ld_frag,
8253 Intrinsic Int128, Intrinsic Int256> {
8254 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8255 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8256 [(set VR128:$dst, (Int128 VR128:$src))]>,
8257 Sched<[WriteShuffle]>, VEX;
8258 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8259 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8261 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8262 Sched<[WriteLoad]>, VEX;
8263 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8264 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8265 [(set VR256:$dst, (Int256 VR128:$src))]>,
8266 Sched<[WriteShuffle256]>, VEX, VEX_L;
8267 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8268 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8270 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8271 Sched<[WriteLoad]>, VEX, VEX_L;
8274 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8275 int_x86_avx2_pbroadcastb_128,
8276 int_x86_avx2_pbroadcastb_256>;
8277 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8278 int_x86_avx2_pbroadcastw_128,
8279 int_x86_avx2_pbroadcastw_256>;
8280 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8281 int_x86_avx2_pbroadcastd_128,
8282 int_x86_avx2_pbroadcastd_256>;
8283 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8284 int_x86_avx2_pbroadcastq_128,
8285 int_x86_avx2_pbroadcastq_256>;
8287 let Predicates = [HasAVX2] in {
8288 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8289 (VPBROADCASTBrm addr:$src)>;
8290 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8291 (VPBROADCASTBYrm addr:$src)>;
8292 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8293 (VPBROADCASTWrm addr:$src)>;
8294 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8295 (VPBROADCASTWYrm addr:$src)>;
8296 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8297 (VPBROADCASTDrm addr:$src)>;
8298 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8299 (VPBROADCASTDYrm addr:$src)>;
8300 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8301 (VPBROADCASTQrm addr:$src)>;
8302 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8303 (VPBROADCASTQYrm addr:$src)>;
8305 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8306 (VPBROADCASTBrr VR128:$src)>;
8307 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8308 (VPBROADCASTBYrr VR128:$src)>;
8309 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8310 (VPBROADCASTWrr VR128:$src)>;
8311 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8312 (VPBROADCASTWYrr VR128:$src)>;
8313 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8314 (VPBROADCASTDrr VR128:$src)>;
8315 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8316 (VPBROADCASTDYrr VR128:$src)>;
8317 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8318 (VPBROADCASTQrr VR128:$src)>;
8319 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8320 (VPBROADCASTQYrr VR128:$src)>;
8321 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8322 (VBROADCASTSSrr VR128:$src)>;
8323 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8324 (VBROADCASTSSYrr VR128:$src)>;
8325 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8326 (VPBROADCASTQrr VR128:$src)>;
8327 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8328 (VBROADCASTSDYrr VR128:$src)>;
8330 // Provide aliases for broadcast from the same register class that
8331 // automatically does the extract.
8332 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8333 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8335 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8336 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8338 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8339 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8341 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8342 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8344 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8345 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8347 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8348 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8351 // Provide fallback in case the load node that is used in the patterns above
8352 // is used by additional users, which prevents the pattern selection.
8353 let AddedComplexity = 20 in {
8354 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8355 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8356 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8357 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8358 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8359 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8361 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8362 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8363 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8364 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8365 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8366 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8368 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8369 (VPBROADCASTBrr (COPY_TO_REGCLASS
8370 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8372 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8373 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8374 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8377 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8378 (VPBROADCASTWrr (COPY_TO_REGCLASS
8379 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8381 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8382 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8383 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8386 // The patterns for VPBROADCASTD are not needed because they would match
8387 // the exact same thing as VBROADCASTSS patterns.
8389 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8390 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8391 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8395 // AVX1 broadcast patterns
8396 let Predicates = [HasAVX1Only] in {
8397 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8398 (VBROADCASTSSYrm addr:$src)>;
8399 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8400 (VBROADCASTSDYrm addr:$src)>;
8401 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8402 (VBROADCASTSSrm addr:$src)>;
8405 let Predicates = [HasAVX] in {
8406 // Provide fallback in case the load node that is used in the patterns above
8407 // is used by additional users, which prevents the pattern selection.
8408 let AddedComplexity = 20 in {
8409 // 128bit broadcasts:
8410 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8411 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8412 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8413 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8414 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8415 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8416 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8417 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8418 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8419 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8421 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8422 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8423 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8424 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8425 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8426 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8427 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8428 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8429 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8430 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8433 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8434 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8435 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8436 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8439 //===----------------------------------------------------------------------===//
8440 // VPERM - Permute instructions
8443 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8444 ValueType OpVT, X86FoldableSchedWrite Sched> {
8445 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8446 (ins VR256:$src1, VR256:$src2),
8447 !strconcat(OpcodeStr,
8448 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8450 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8451 Sched<[Sched]>, VEX_4V, VEX_L;
8452 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8453 (ins VR256:$src1, i256mem:$src2),
8454 !strconcat(OpcodeStr,
8455 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8457 (OpVT (X86VPermv VR256:$src1,
8458 (bitconvert (mem_frag addr:$src2)))))]>,
8459 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8462 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8463 let ExeDomain = SSEPackedSingle in
8464 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8466 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8467 ValueType OpVT, X86FoldableSchedWrite Sched> {
8468 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8469 (ins VR256:$src1, u8imm:$src2),
8470 !strconcat(OpcodeStr,
8471 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8473 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8474 Sched<[Sched]>, VEX, VEX_L;
8475 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8476 (ins i256mem:$src1, u8imm:$src2),
8477 !strconcat(OpcodeStr,
8478 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8480 (OpVT (X86VPermi (mem_frag addr:$src1),
8481 (i8 imm:$src2))))]>,
8482 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8485 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8486 WriteShuffle256>, VEX_W;
8487 let ExeDomain = SSEPackedDouble in
8488 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8489 WriteFShuffle256>, VEX_W;
8491 //===----------------------------------------------------------------------===//
8492 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8494 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8495 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8496 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8497 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8498 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8500 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8501 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8502 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8503 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8505 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8507 let Predicates = [HasAVX2] in {
8508 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8509 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8510 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8511 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8512 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8513 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8515 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8517 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8518 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8519 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8520 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8521 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8523 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8527 //===----------------------------------------------------------------------===//
8528 // VINSERTI128 - Insert packed integer values
8530 let hasSideEffects = 0 in {
8531 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8532 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8533 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8534 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8536 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8537 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8538 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8539 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8542 let Predicates = [HasAVX2] in {
8543 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8545 (VINSERTI128rr VR256:$src1, VR128:$src2,
8546 (INSERT_get_vinsert128_imm VR256:$ins))>;
8547 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8549 (VINSERTI128rr VR256:$src1, VR128:$src2,
8550 (INSERT_get_vinsert128_imm VR256:$ins))>;
8551 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8553 (VINSERTI128rr VR256:$src1, VR128:$src2,
8554 (INSERT_get_vinsert128_imm VR256:$ins))>;
8555 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8557 (VINSERTI128rr VR256:$src1, VR128:$src2,
8558 (INSERT_get_vinsert128_imm VR256:$ins))>;
8560 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8562 (VINSERTI128rm VR256:$src1, addr:$src2,
8563 (INSERT_get_vinsert128_imm VR256:$ins))>;
8564 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8565 (bc_v4i32 (loadv2i64 addr:$src2)),
8567 (VINSERTI128rm VR256:$src1, addr:$src2,
8568 (INSERT_get_vinsert128_imm VR256:$ins))>;
8569 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8570 (bc_v16i8 (loadv2i64 addr:$src2)),
8572 (VINSERTI128rm VR256:$src1, addr:$src2,
8573 (INSERT_get_vinsert128_imm VR256:$ins))>;
8574 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8575 (bc_v8i16 (loadv2i64 addr:$src2)),
8577 (VINSERTI128rm VR256:$src1, addr:$src2,
8578 (INSERT_get_vinsert128_imm VR256:$ins))>;
8581 //===----------------------------------------------------------------------===//
8582 // VEXTRACTI128 - Extract packed integer values
8584 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8585 (ins VR256:$src1, u8imm:$src2),
8586 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8587 Sched<[WriteShuffle256]>, VEX, VEX_L;
8588 let hasSideEffects = 0, mayStore = 1 in
8589 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8590 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8591 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8592 Sched<[WriteStore]>, VEX, VEX_L;
8594 let Predicates = [HasAVX2] in {
8595 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8596 (v2i64 (VEXTRACTI128rr
8597 (v4i64 VR256:$src1),
8598 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8599 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8600 (v4i32 (VEXTRACTI128rr
8601 (v8i32 VR256:$src1),
8602 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8603 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8604 (v8i16 (VEXTRACTI128rr
8605 (v16i16 VR256:$src1),
8606 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8607 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8608 (v16i8 (VEXTRACTI128rr
8609 (v32i8 VR256:$src1),
8610 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8612 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8613 (iPTR imm))), addr:$dst),
8614 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8615 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8616 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8617 (iPTR imm))), addr:$dst),
8618 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8619 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8620 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8621 (iPTR imm))), addr:$dst),
8622 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8623 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8624 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8625 (iPTR imm))), addr:$dst),
8626 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8627 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8630 //===----------------------------------------------------------------------===//
8631 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8633 multiclass avx2_pmovmask<string OpcodeStr,
8634 Intrinsic IntLd128, Intrinsic IntLd256,
8635 Intrinsic IntSt128, Intrinsic IntSt256> {
8636 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8637 (ins VR128:$src1, i128mem:$src2),
8638 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8639 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8640 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8641 (ins VR256:$src1, i256mem:$src2),
8642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8643 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8645 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8646 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8648 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8649 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8650 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8652 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8655 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8656 int_x86_avx2_maskload_d,
8657 int_x86_avx2_maskload_d_256,
8658 int_x86_avx2_maskstore_d,
8659 int_x86_avx2_maskstore_d_256>;
8660 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8661 int_x86_avx2_maskload_q,
8662 int_x86_avx2_maskload_q_256,
8663 int_x86_avx2_maskstore_q,
8664 int_x86_avx2_maskstore_q_256>, VEX_W;
8666 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8667 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8669 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8670 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8672 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8673 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8675 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8676 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8678 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8679 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8681 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8682 (bc_v8f32 (v8i32 immAllZerosV)))),
8683 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8685 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8686 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8689 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8690 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8692 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8693 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8695 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8696 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8699 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8700 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8702 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8703 (bc_v4f32 (v4i32 immAllZerosV)))),
8704 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8706 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8707 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8710 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8711 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8713 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8714 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8716 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8717 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8720 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8721 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8723 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8724 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8726 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8727 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8729 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8730 (v4f64 immAllZerosV))),
8731 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8733 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8734 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8737 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8738 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8740 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8741 (bc_v4i64 (v8i32 immAllZerosV)))),
8742 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8744 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8745 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8748 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8749 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8751 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8752 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8754 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8755 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8757 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8758 (v2f64 immAllZerosV))),
8759 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8761 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8762 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8765 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8766 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8768 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8769 (bc_v2i64 (v4i32 immAllZerosV)))),
8770 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8772 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8773 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8776 //===----------------------------------------------------------------------===//
8777 // Variable Bit Shifts
8779 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8780 ValueType vt128, ValueType vt256> {
8781 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8782 (ins VR128:$src1, VR128:$src2),
8783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8785 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8786 VEX_4V, Sched<[WriteVarVecShift]>;
8787 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8788 (ins VR128:$src1, i128mem:$src2),
8789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8791 (vt128 (OpNode VR128:$src1,
8792 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8793 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8794 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8795 (ins VR256:$src1, VR256:$src2),
8796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8798 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8799 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8800 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8801 (ins VR256:$src1, i256mem:$src2),
8802 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8804 (vt256 (OpNode VR256:$src1,
8805 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8806 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8809 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8810 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8811 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8812 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8813 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8815 //===----------------------------------------------------------------------===//
8816 // VGATHER - GATHER Operations
8817 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8818 X86MemOperand memop128, X86MemOperand memop256> {
8819 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8820 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8821 !strconcat(OpcodeStr,
8822 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8824 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8825 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8826 !strconcat(OpcodeStr,
8827 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8828 []>, VEX_4VOp3, VEX_L;
8831 let mayLoad = 1, Constraints
8832 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8834 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8835 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8836 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8837 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8839 let ExeDomain = SSEPackedDouble in {
8840 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8841 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8844 let ExeDomain = SSEPackedSingle in {
8845 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8846 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;