1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 //===----------------------------------------------------------------------===//
155 // SSE 1 & 2 Instructions Classes
156 //===----------------------------------------------------------------------===//
158 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
159 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
160 RegisterClass RC, X86MemOperand x86memop,
163 let isCommutable = 1 in {
164 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
168 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
169 Sched<[itins.Sched]>;
171 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
175 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
176 Sched<[itins.Sched.Folded, ReadAfterLd]>;
179 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
180 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
181 string asm, string SSEVer, string FPSizeStr,
182 Operand memopr, ComplexPattern mem_cpat,
185 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
187 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
188 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
189 [(set RC:$dst, (!cast<Intrinsic>(
190 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
191 RC:$src1, RC:$src2))], itins.rr>,
192 Sched<[itins.Sched]>;
193 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
195 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
196 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
197 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
198 SSEVer, "_", OpcodeStr, FPSizeStr))
199 RC:$src1, mem_cpat:$src2))], itins.rm>,
200 Sched<[itins.Sched.Folded, ReadAfterLd]>;
203 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
204 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
205 RegisterClass RC, ValueType vt,
206 X86MemOperand x86memop, PatFrag mem_frag,
207 Domain d, OpndItins itins, bit Is2Addr = 1> {
208 let isCommutable = 1 in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
214 Sched<[itins.Sched]>;
216 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
220 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
222 Sched<[itins.Sched.Folded, ReadAfterLd]>;
225 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
226 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
227 string OpcodeStr, X86MemOperand x86memop,
228 list<dag> pat_rr, list<dag> pat_rm,
230 let isCommutable = 1, hasSideEffects = 0 in
231 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
233 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
235 pat_rr, NoItinerary, d>,
236 Sched<[WriteVecLogic]>;
237 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 pat_rm, NoItinerary, d>,
242 Sched<[WriteVecLogicLd, ReadAfterLd]>;
245 //===----------------------------------------------------------------------===//
246 // Non-instruction patterns
247 //===----------------------------------------------------------------------===//
249 // A vector extract of the first f32/f64 position is a subregister copy
250 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
251 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
252 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
253 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
255 // A 128-bit subvector extract from the first 256-bit vector position
256 // is a subregister copy that needs no instruction.
257 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
258 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
259 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
260 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
262 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
263 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
264 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
265 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
267 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
268 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
269 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
270 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
272 // A 128-bit subvector insert to the first 256-bit vector position
273 // is a subregister copy that needs no instruction.
274 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
275 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
276 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
278 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
280 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
282 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
283 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
284 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
285 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
286 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
289 // Implicitly promote a 32-bit scalar to a vector.
290 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
291 (COPY_TO_REGCLASS FR32:$src, VR128)>;
292 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
293 (COPY_TO_REGCLASS FR32:$src, VR128)>;
294 // Implicitly promote a 64-bit scalar to a vector.
295 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
296 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
298 (COPY_TO_REGCLASS FR64:$src, VR128)>;
300 // Bitcasts between 128-bit vector types. Return the original type since
301 // no instruction is needed for the conversion
302 let Predicates = [HasSSE2] in {
303 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
306 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
307 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
312 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
326 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
327 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
330 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
331 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
335 // Bitcasts between 256-bit vector types. Return the original type since
336 // no instruction is needed for the conversion
337 let Predicates = [HasAVX] in {
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
370 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
371 // This is expanded by ExpandPostRAPseudos.
372 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
373 isPseudo = 1, SchedRW = [WriteZero] in {
374 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
375 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
376 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
377 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
380 //===----------------------------------------------------------------------===//
381 // AVX & SSE - Zero/One Vectors
382 //===----------------------------------------------------------------------===//
384 // Alias instruction that maps zero vector to pxor / xorp* for sse.
385 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
386 // swizzled by ExecutionDepsFix to pxor.
387 // We set canFoldAsLoad because this can be converted to a constant-pool
388 // load of an all-zeros value if folding it would be beneficial.
389 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
390 isPseudo = 1, SchedRW = [WriteZero] in {
391 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
392 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
395 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
396 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
397 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
398 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
399 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
402 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
403 // and doesn't need it because on sandy bridge the register is set to zero
404 // at the rename stage without using any execution unit, so SET0PSY
405 // and SET0PDY can be used for vector int instructions without penalty
406 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
407 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
408 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
409 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
412 let Predicates = [HasAVX] in
413 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
415 let Predicates = [HasAVX2] in {
416 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
417 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
418 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
419 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
422 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
423 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
424 let Predicates = [HasAVX1Only] in {
425 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
427 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
429 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
431 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
433 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
435 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
437 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
438 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
439 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
445 isPseudo = 1, SchedRW = [WriteZero] in {
446 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
447 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
448 let Predicates = [HasAVX2] in
449 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
450 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
454 //===----------------------------------------------------------------------===//
455 // SSE 1 & 2 - Move FP Scalar Instructions
457 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
458 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
459 // is used instead. Register-to-register movss/movsd is not modeled as an
460 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
461 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
462 //===----------------------------------------------------------------------===//
464 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
465 X86MemOperand x86memop, string base_opc,
467 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
468 (ins VR128:$src1, RC:$src2),
469 !strconcat(base_opc, asm_opr),
470 [(set VR128:$dst, (vt (OpNode VR128:$src1,
471 (scalar_to_vector RC:$src2))))],
472 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
474 // For the disassembler
475 let isCodeGenOnly = 1, hasSideEffects = 0 in
476 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
477 (ins VR128:$src1, RC:$src2),
478 !strconcat(base_opc, asm_opr),
479 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
482 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
483 X86MemOperand x86memop, string OpcodeStr> {
485 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
489 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
490 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
491 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
492 VEX, VEX_LIG, Sched<[WriteStore]>;
494 let Constraints = "$src1 = $dst" in {
495 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
496 "\t{$src2, $dst|$dst, $src2}">;
499 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
501 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
505 // Loading from memory automatically zeroing upper bits.
506 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
507 PatFrag mem_pat, string OpcodeStr> {
508 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
510 [(set RC:$dst, (mem_pat addr:$src))],
511 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
512 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
514 [(set RC:$dst, (mem_pat addr:$src))],
515 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
518 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
519 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
521 let canFoldAsLoad = 1, isReMaterializable = 1 in {
522 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
524 let AddedComplexity = 20 in
525 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
529 let Predicates = [HasAVX] in {
530 let AddedComplexity = 15 in {
531 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
532 // MOVS{S,D} to the lower bits.
533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
534 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
535 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
536 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
537 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
538 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
539 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
540 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
542 // Move low f32 and clear high bits.
543 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
544 (SUBREG_TO_REG (i32 0),
545 (VMOVSSrr (v4f32 (V_SET0)),
546 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
547 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
548 (SUBREG_TO_REG (i32 0),
549 (VMOVSSrr (v4i32 (V_SET0)),
550 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
553 let AddedComplexity = 20 in {
554 // MOVSSrm zeros the high parts of the register; represent this
555 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
557 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
558 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
559 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
560 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
561 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
563 // MOVSDrm zeros the high parts of the register; represent this
564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
565 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
566 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
567 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
568 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
569 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
570 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
571 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
572 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
573 def : Pat<(v2f64 (X86vzload addr:$src)),
574 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
576 // Represent the same patterns above but in the form they appear for
578 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
579 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
581 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
582 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
583 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
584 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
585 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
586 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
588 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
589 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
590 (SUBREG_TO_REG (i32 0),
591 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
593 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
594 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
595 (SUBREG_TO_REG (i64 0),
596 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
598 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
599 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
602 // Move low f64 and clear high bits.
603 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
604 (SUBREG_TO_REG (i32 0),
605 (VMOVSDrr (v2f64 (V_SET0)),
606 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
608 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
609 (SUBREG_TO_REG (i32 0),
610 (VMOVSDrr (v2i64 (V_SET0)),
611 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
613 // Extract and store.
614 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
616 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
617 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
619 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
621 // Shuffle with VMOVSS
622 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
623 (VMOVSSrr (v4i32 VR128:$src1),
624 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
625 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
626 (VMOVSSrr (v4f32 VR128:$src1),
627 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
630 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
631 (SUBREG_TO_REG (i32 0),
632 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
633 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
635 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
636 (SUBREG_TO_REG (i32 0),
637 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
638 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
641 // Shuffle with VMOVSD
642 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
643 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
644 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
646 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
648 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
649 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
652 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
653 (SUBREG_TO_REG (i32 0),
654 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
655 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
657 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
658 (SUBREG_TO_REG (i32 0),
659 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
660 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
664 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
665 // is during lowering, where it's not possible to recognize the fold cause
666 // it has two uses through a bitcast. One use disappears at isel time and the
667 // fold opportunity reappears.
668 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
678 let Predicates = [UseSSE1] in {
679 let AddedComplexity = 15 in {
680 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
681 // MOVSS to the lower bits.
682 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
683 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
684 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
685 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
686 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
687 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
690 let AddedComplexity = 20 in {
691 // MOVSSrm already zeros the high parts of the register.
692 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
693 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
694 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
695 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
696 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
697 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
700 // Extract and store.
701 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
703 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
705 // Shuffle with MOVSS
706 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
707 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
708 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
709 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
712 let Predicates = [UseSSE2] in {
713 let AddedComplexity = 15 in {
714 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
715 // MOVSD to the lower bits.
716 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
717 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
720 let AddedComplexity = 20 in {
721 // MOVSDrm already zeros the high parts of the register.
722 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
723 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
724 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
726 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
727 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
728 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
729 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
730 def : Pat<(v2f64 (X86vzload addr:$src)),
731 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
734 // Extract and store.
735 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
737 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
739 // Shuffle with MOVSD
740 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
741 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
742 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
743 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
744 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
745 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
746 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
747 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 //===----------------------------------------------------------------------===//
764 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
765 //===----------------------------------------------------------------------===//
767 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
768 X86MemOperand x86memop, PatFrag ld_frag,
769 string asm, Domain d,
771 bit IsReMaterializable = 1> {
772 let neverHasSideEffects = 1 in
773 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
774 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
776 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
777 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
778 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
779 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
783 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
784 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
786 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
787 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
789 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
790 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
792 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
793 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
796 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
797 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
799 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
800 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
801 TB, OpSize, VEX, VEX_L;
802 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
803 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
805 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
806 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
807 TB, OpSize, VEX, VEX_L;
808 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
809 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
811 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
812 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
814 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
815 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
817 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
818 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
821 let SchedRW = [WriteStore] in {
822 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
823 "movaps\t{$src, $dst|$dst, $src}",
824 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
825 IIC_SSE_MOVA_P_MR>, VEX;
826 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
827 "movapd\t{$src, $dst|$dst, $src}",
828 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
829 IIC_SSE_MOVA_P_MR>, VEX;
830 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
831 "movups\t{$src, $dst|$dst, $src}",
832 [(store (v4f32 VR128:$src), addr:$dst)],
833 IIC_SSE_MOVU_P_MR>, VEX;
834 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
835 "movupd\t{$src, $dst|$dst, $src}",
836 [(store (v2f64 VR128:$src), addr:$dst)],
837 IIC_SSE_MOVU_P_MR>, VEX;
838 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
839 "movaps\t{$src, $dst|$dst, $src}",
840 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
841 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
842 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
843 "movapd\t{$src, $dst|$dst, $src}",
844 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
845 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
846 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
847 "movups\t{$src, $dst|$dst, $src}",
848 [(store (v8f32 VR256:$src), addr:$dst)],
849 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
850 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
851 "movupd\t{$src, $dst|$dst, $src}",
852 [(store (v4f64 VR256:$src), addr:$dst)],
853 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
857 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
858 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
860 "movaps\t{$src, $dst|$dst, $src}", [],
861 IIC_SSE_MOVA_P_RR>, VEX;
862 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
864 "movapd\t{$src, $dst|$dst, $src}", [],
865 IIC_SSE_MOVA_P_RR>, VEX;
866 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
868 "movups\t{$src, $dst|$dst, $src}", [],
869 IIC_SSE_MOVU_P_RR>, VEX;
870 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
872 "movupd\t{$src, $dst|$dst, $src}", [],
873 IIC_SSE_MOVU_P_RR>, VEX;
874 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
878 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
882 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
886 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
892 let Predicates = [HasAVX] in {
893 def : Pat<(v8i32 (X86vzmovl
894 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
895 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
896 def : Pat<(v4i64 (X86vzmovl
897 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
898 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
899 def : Pat<(v8f32 (X86vzmovl
900 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
901 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
902 def : Pat<(v4f64 (X86vzmovl
903 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
904 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
908 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
909 (VMOVUPSYmr addr:$dst, VR256:$src)>;
910 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
911 (VMOVUPDYmr addr:$dst, VR256:$src)>;
913 let SchedRW = [WriteStore] in {
914 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
918 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
919 "movapd\t{$src, $dst|$dst, $src}",
920 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
922 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
923 "movups\t{$src, $dst|$dst, $src}",
924 [(store (v4f32 VR128:$src), addr:$dst)],
926 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
927 "movupd\t{$src, $dst|$dst, $src}",
928 [(store (v2f64 VR128:$src), addr:$dst)],
933 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
934 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
935 "movaps\t{$src, $dst|$dst, $src}", [],
937 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
938 "movapd\t{$src, $dst|$dst, $src}", [],
940 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
941 "movups\t{$src, $dst|$dst, $src}", [],
943 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
944 "movupd\t{$src, $dst|$dst, $src}", [],
948 let Predicates = [HasAVX] in {
949 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
950 (VMOVUPSmr addr:$dst, VR128:$src)>;
951 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
952 (VMOVUPDmr addr:$dst, VR128:$src)>;
955 let Predicates = [UseSSE1] in
956 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 let Predicates = [UseSSE2] in
959 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
960 (MOVUPDmr addr:$dst, VR128:$src)>;
962 // Use vmovaps/vmovups for AVX integer load/store.
963 let Predicates = [HasAVX] in {
964 // 128-bit load/store
965 def : Pat<(alignedloadv2i64 addr:$src),
966 (VMOVAPSrm addr:$src)>;
967 def : Pat<(loadv2i64 addr:$src),
968 (VMOVUPSrm addr:$src)>;
970 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
971 (VMOVAPSmr addr:$dst, VR128:$src)>;
972 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
973 (VMOVAPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
975 (VMOVAPSmr addr:$dst, VR128:$src)>;
976 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
977 (VMOVAPSmr addr:$dst, VR128:$src)>;
978 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
979 (VMOVUPSmr addr:$dst, VR128:$src)>;
980 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
981 (VMOVUPSmr addr:$dst, VR128:$src)>;
982 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
983 (VMOVUPSmr addr:$dst, VR128:$src)>;
984 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
985 (VMOVUPSmr addr:$dst, VR128:$src)>;
987 // 256-bit load/store
988 def : Pat<(alignedloadv4i64 addr:$src),
989 (VMOVAPSYrm addr:$src)>;
990 def : Pat<(loadv4i64 addr:$src),
991 (VMOVUPSYrm addr:$src)>;
992 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
993 (VMOVAPSYmr addr:$dst, VR256:$src)>;
994 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
995 (VMOVAPSYmr addr:$dst, VR256:$src)>;
996 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
997 (VMOVAPSYmr addr:$dst, VR256:$src)>;
998 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
999 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1000 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1001 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1002 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1003 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1004 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1005 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1006 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1007 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1009 // Special patterns for storing subvector extracts of lower 128-bits
1010 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1011 def : Pat<(alignedstore (v2f64 (extract_subvector
1012 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1013 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1014 def : Pat<(alignedstore (v4f32 (extract_subvector
1015 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1016 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1017 def : Pat<(alignedstore (v2i64 (extract_subvector
1018 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1019 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1020 def : Pat<(alignedstore (v4i32 (extract_subvector
1021 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1022 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1023 def : Pat<(alignedstore (v8i16 (extract_subvector
1024 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1025 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1026 def : Pat<(alignedstore (v16i8 (extract_subvector
1027 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1028 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1030 def : Pat<(store (v2f64 (extract_subvector
1031 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1032 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1033 def : Pat<(store (v4f32 (extract_subvector
1034 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1035 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1036 def : Pat<(store (v2i64 (extract_subvector
1037 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1038 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1039 def : Pat<(store (v4i32 (extract_subvector
1040 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(store (v8i16 (extract_subvector
1043 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(store (v16i8 (extract_subvector
1046 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 // Use movaps / movups for SSE integer load / store (one byte shorter).
1051 // The instructions selected below are then converted to MOVDQA/MOVDQU
1052 // during the SSE domain pass.
1053 let Predicates = [UseSSE1] in {
1054 def : Pat<(alignedloadv2i64 addr:$src),
1055 (MOVAPSrm addr:$src)>;
1056 def : Pat<(loadv2i64 addr:$src),
1057 (MOVUPSrm addr:$src)>;
1059 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1060 (MOVAPSmr addr:$dst, VR128:$src)>;
1061 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1062 (MOVAPSmr addr:$dst, VR128:$src)>;
1063 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1064 (MOVAPSmr addr:$dst, VR128:$src)>;
1065 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1066 (MOVAPSmr addr:$dst, VR128:$src)>;
1067 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1068 (MOVUPSmr addr:$dst, VR128:$src)>;
1069 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1070 (MOVUPSmr addr:$dst, VR128:$src)>;
1071 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1072 (MOVUPSmr addr:$dst, VR128:$src)>;
1073 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1074 (MOVUPSmr addr:$dst, VR128:$src)>;
1077 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1078 // bits are disregarded. FIXME: Set encoding to pseudo!
1079 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
1080 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1081 "movaps\t{$src, $dst|$dst, $src}", [],
1082 IIC_SSE_MOVA_P_RR>, VEX;
1083 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1084 "movapd\t{$src, $dst|$dst, $src}", [],
1085 IIC_SSE_MOVA_P_RR>, VEX;
1086 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1087 "movaps\t{$src, $dst|$dst, $src}", [],
1089 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1090 "movapd\t{$src, $dst|$dst, $src}", [],
1094 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1095 // bits are disregarded. FIXME: Set encoding to pseudo!
1096 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1097 let isCodeGenOnly = 1 in {
1098 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1099 "movaps\t{$src, $dst|$dst, $src}",
1100 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1101 IIC_SSE_MOVA_P_RM>, VEX;
1102 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1103 "movapd\t{$src, $dst|$dst, $src}",
1104 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1105 IIC_SSE_MOVA_P_RM>, VEX;
1107 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1108 "movaps\t{$src, $dst|$dst, $src}",
1109 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1111 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1112 "movapd\t{$src, $dst|$dst, $src}",
1113 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1117 //===----------------------------------------------------------------------===//
1118 // SSE 1 & 2 - Move Low packed FP Instructions
1119 //===----------------------------------------------------------------------===//
1121 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1122 string base_opc, string asm_opr,
1123 InstrItinClass itin> {
1124 def PSrm : PI<opc, MRMSrcMem,
1125 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1126 !strconcat(base_opc, "s", asm_opr),
1128 (psnode VR128:$src1,
1129 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1130 itin, SSEPackedSingle>, TB,
1131 Sched<[WriteShuffleLd, ReadAfterLd]>;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize,
1139 Sched<[WriteShuffleLd, ReadAfterLd]>;
1143 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1144 string base_opc, InstrItinClass itin> {
1145 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1146 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1149 let Constraints = "$src1 = $dst" in
1150 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1151 "\t{$src2, $dst|$dst, $src2}",
1155 let AddedComplexity = 20 in {
1156 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1160 let SchedRW = [WriteStore] in {
1161 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1162 "movlps\t{$src, $dst|$dst, $src}",
1163 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1164 (iPTR 0))), addr:$dst)],
1165 IIC_SSE_MOV_LH>, VEX;
1166 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1167 "movlpd\t{$src, $dst|$dst, $src}",
1168 [(store (f64 (vector_extract (v2f64 VR128:$src),
1169 (iPTR 0))), addr:$dst)],
1170 IIC_SSE_MOV_LH>, VEX;
1171 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1172 "movlps\t{$src, $dst|$dst, $src}",
1173 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1174 (iPTR 0))), addr:$dst)],
1176 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1177 "movlpd\t{$src, $dst|$dst, $src}",
1178 [(store (f64 (vector_extract (v2f64 VR128:$src),
1179 (iPTR 0))), addr:$dst)],
1183 let Predicates = [HasAVX] in {
1184 // Shuffle with VMOVLPS
1185 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1186 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1188 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 // Shuffle with VMOVLPD
1191 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1192 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1193 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1194 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1197 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1199 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1200 def : Pat<(store (v4i32 (X86Movlps
1201 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1205 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1211 let Predicates = [UseSSE1] in {
1212 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1213 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1214 (iPTR 0))), addr:$src1),
1215 (MOVLPSmr addr:$src1, VR128:$src2)>;
1217 // Shuffle with MOVLPS
1218 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1219 (MOVLPSrm VR128:$src1, addr:$src2)>;
1220 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1221 (MOVLPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1229 (MOVLPSmr addr:$src1, VR128:$src2)>;
1230 def : Pat<(store (v4i32 (X86Movlps
1231 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1233 (MOVLPSmr addr:$src1, VR128:$src2)>;
1236 let Predicates = [UseSSE2] in {
1237 // Shuffle with MOVLPD
1238 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1239 (MOVLPDrm VR128:$src1, addr:$src2)>;
1240 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1241 (MOVLPDrm VR128:$src1, addr:$src2)>;
1244 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1246 (MOVLPDmr addr:$src1, VR128:$src2)>;
1247 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1252 //===----------------------------------------------------------------------===//
1253 // SSE 1 & 2 - Move Hi packed FP Instructions
1254 //===----------------------------------------------------------------------===//
1256 let AddedComplexity = 20 in {
1257 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1261 let SchedRW = [WriteStore] in {
1262 // v2f64 extract element 1 is always custom lowered to unpack high to low
1263 // and extract element 0 so the non-store version isn't too horrible.
1264 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1265 "movhps\t{$src, $dst|$dst, $src}",
1266 [(store (f64 (vector_extract
1267 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1268 (bc_v2f64 (v4f32 VR128:$src))),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhpd\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1274 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1275 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1281 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1288 let Predicates = [HasAVX] in {
1290 def : Pat<(X86Movlhps VR128:$src1,
1291 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1292 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1293 def : Pat<(X86Movlhps VR128:$src1,
1294 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1295 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1297 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1298 // is during lowering, where it's not possible to recognize the load fold
1299 // cause it has two uses through a bitcast. One use disappears at isel time
1300 // and the fold opportunity reappears.
1301 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1302 (scalar_to_vector (loadf64 addr:$src2)))),
1303 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1306 let Predicates = [UseSSE1] in {
1308 def : Pat<(X86Movlhps VR128:$src1,
1309 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1310 (MOVHPSrm VR128:$src1, addr:$src2)>;
1311 def : Pat<(X86Movlhps VR128:$src1,
1312 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1313 (MOVHPSrm VR128:$src1, addr:$src2)>;
1316 let Predicates = [UseSSE2] in {
1317 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1318 // is during lowering, where it's not possible to recognize the load fold
1319 // cause it has two uses through a bitcast. One use disappears at isel time
1320 // and the fold opportunity reappears.
1321 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1322 (scalar_to_vector (loadf64 addr:$src2)))),
1323 (MOVHPDrm VR128:$src1, addr:$src2)>;
1326 //===----------------------------------------------------------------------===//
1327 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1328 //===----------------------------------------------------------------------===//
1330 let AddedComplexity = 20 in {
1331 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1332 (ins VR128:$src1, VR128:$src2),
1333 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1335 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1337 VEX_4V, Sched<[WriteShuffle]>;
1338 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1344 VEX_4V, Sched<[WriteShuffle]>;
1346 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1347 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movlhps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1352 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1353 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movhlps\t{$src2, $dst|$dst, $src2}",
1357 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1358 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1361 let Predicates = [HasAVX] in {
1363 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1364 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1365 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1366 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1369 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1370 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1373 let Predicates = [UseSSE1] in {
1375 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1376 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1377 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1378 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1381 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1382 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1385 //===----------------------------------------------------------------------===//
1386 // SSE 1 & 2 - Conversion Instructions
1387 //===----------------------------------------------------------------------===//
1389 def SSE_CVT_PD : OpndItins<
1390 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1393 let Sched = WriteCvtI2F in
1394 def SSE_CVT_PS : OpndItins<
1395 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1398 let Sched = WriteCvtI2F in
1399 def SSE_CVT_Scalar : OpndItins<
1400 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1403 let Sched = WriteCvtF2I in
1404 def SSE_CVT_SS2SI_32 : OpndItins<
1405 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1408 let Sched = WriteCvtF2I in
1409 def SSE_CVT_SS2SI_64 : OpndItins<
1410 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1413 let Sched = WriteCvtF2I in
1414 def SSE_CVT_SD2SI : OpndItins<
1415 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1418 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, OpndItins itins> {
1421 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1423 itins.rr>, Sched<[itins.Sched]>;
1424 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1426 itins.rm>, Sched<[itins.Sched.Folded]>;
1429 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm, Domain d,
1432 let neverHasSideEffects = 1 in {
1433 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1434 [], itins.rr, d>, Sched<[itins.Sched]>;
1436 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1437 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1441 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1442 X86MemOperand x86memop, string asm> {
1443 let neverHasSideEffects = 1 in {
1444 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1445 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1446 Sched<[WriteCvtI2F]>;
1448 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1449 (ins DstRC:$src1, x86memop:$src),
1450 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1451 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1473 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1474 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1475 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1476 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1477 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1478 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1479 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1480 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1481 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1482 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1483 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1484 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1486 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1489 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1490 // register, but the same isn't true when only using memory operands,
1491 // provide other assembly "l" and "q" forms to address this explicitly
1492 // where appropriate to do so.
1493 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1494 XS, VEX_4V, VEX_LIG;
1495 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1496 XS, VEX_4V, VEX_W, VEX_LIG;
1497 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1498 XD, VEX_4V, VEX_LIG;
1499 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1500 XD, VEX_4V, VEX_W, VEX_LIG;
1502 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1503 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1504 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1505 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1507 let Predicates = [HasAVX] in {
1508 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1509 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1510 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1511 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1512 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1513 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1514 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1515 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1517 def : Pat<(f32 (sint_to_fp GR32:$src)),
1518 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1519 def : Pat<(f32 (sint_to_fp GR64:$src)),
1520 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1521 def : Pat<(f64 (sint_to_fp GR32:$src)),
1522 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1523 def : Pat<(f64 (sint_to_fp GR64:$src)),
1524 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1527 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1528 "cvttss2si\t{$src, $dst|$dst, $src}",
1529 SSE_CVT_SS2SI_32>, XS;
1530 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1531 "cvttss2si\t{$src, $dst|$dst, $src}",
1532 SSE_CVT_SS2SI_64>, XS, REX_W;
1533 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1534 "cvttsd2si\t{$src, $dst|$dst, $src}",
1536 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1537 "cvttsd2si\t{$src, $dst|$dst, $src}",
1538 SSE_CVT_SD2SI>, XD, REX_W;
1539 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1540 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_Scalar>, XS;
1542 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1543 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_Scalar>, XS, REX_W;
1545 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1546 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1547 SSE_CVT_Scalar>, XD;
1548 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1549 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_Scalar>, XD, REX_W;
1552 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1553 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1554 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1555 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1556 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1557 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1558 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1559 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1560 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1561 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1562 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1563 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1564 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1565 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1566 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1567 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1569 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1570 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1571 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1572 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1574 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1575 // and/or XMM operand(s).
1577 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1578 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1579 string asm, OpndItins itins> {
1580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1581 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1582 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1583 Sched<[itins.Sched]>;
1584 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1585 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1586 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1587 Sched<[itins.Sched.Folded]>;
1590 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1591 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1592 PatFrag ld_frag, string asm, OpndItins itins,
1594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1596 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1597 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1598 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1599 itins.rr>, Sched<[itins.Sched]>;
1600 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1601 (ins DstRC:$src1, x86memop:$src2),
1603 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1604 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1605 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1606 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1609 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1610 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1611 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1612 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1613 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1614 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1616 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1617 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1618 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1619 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1622 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1623 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1624 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1625 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1626 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1627 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1629 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1630 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1631 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1632 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1633 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1634 SSE_CVT_Scalar, 0>, XD,
1637 let Constraints = "$src1 = $dst" in {
1638 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1639 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1640 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1641 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1642 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1643 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1644 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1645 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1646 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1647 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1648 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1649 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1654 // Aliases for intrinsics
1655 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1656 ssmem, sse_load_f32, "cvttss2si",
1657 SSE_CVT_SS2SI_32>, XS, VEX;
1658 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1659 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1660 "cvttss2si", SSE_CVT_SS2SI_64>,
1662 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1663 sdmem, sse_load_f64, "cvttsd2si",
1664 SSE_CVT_SD2SI>, XD, VEX;
1665 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1666 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1667 "cvttsd2si", SSE_CVT_SD2SI>,
1669 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1670 ssmem, sse_load_f32, "cvttss2si",
1671 SSE_CVT_SS2SI_32>, XS;
1672 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1673 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1674 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1675 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1676 sdmem, sse_load_f64, "cvttsd2si",
1678 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1679 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1680 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1682 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1683 ssmem, sse_load_f32, "cvtss2si",
1684 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1685 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1686 ssmem, sse_load_f32, "cvtss2si",
1687 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1689 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1690 ssmem, sse_load_f32, "cvtss2si",
1691 SSE_CVT_SS2SI_32>, XS;
1692 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1693 ssmem, sse_load_f32, "cvtss2si",
1694 SSE_CVT_SS2SI_64>, XS, REX_W;
1696 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 SSEPackedSingle, SSE_CVT_PS>,
1699 TB, VEX, Requires<[HasAVX]>;
1700 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1701 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1702 SSEPackedSingle, SSE_CVT_PS>,
1703 TB, VEX, VEX_L, Requires<[HasAVX]>;
1705 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 SSEPackedSingle, SSE_CVT_PS>,
1708 TB, Requires<[UseSSE2]>;
1710 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1711 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1712 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1713 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1714 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1715 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1716 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1717 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1718 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1719 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1720 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1721 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1722 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1723 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1724 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1725 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1727 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1728 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1729 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1730 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1731 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1732 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1733 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1734 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1735 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1736 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1737 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1738 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1739 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1740 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1741 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1742 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1746 // Convert scalar double to scalar single
1747 let neverHasSideEffects = 1 in {
1748 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1749 (ins FR64:$src1, FR64:$src2),
1750 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1751 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1752 Sched<[WriteCvtF2F]>;
1754 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1755 (ins FR64:$src1, f64mem:$src2),
1756 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1757 [], IIC_SSE_CVT_Scalar_RM>,
1758 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1759 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1762 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1765 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1766 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1767 [(set FR32:$dst, (fround FR64:$src))],
1768 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1769 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1770 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1771 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1772 IIC_SSE_CVT_Scalar_RM>,
1774 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1776 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1782 Sched<[WriteCvtF2F]>;
1783 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1784 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1785 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1787 VR128:$src1, sse_load_f64:$src2))],
1788 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1789 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1791 let Constraints = "$src1 = $dst" in {
1792 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1793 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1794 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1796 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1797 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1798 Sched<[WriteCvtF2F]>;
1799 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1800 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1801 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1802 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1803 VR128:$src1, sse_load_f64:$src2))],
1804 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1805 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1808 // Convert scalar single to scalar double
1809 // SSE2 instructions with XS prefix
1810 let neverHasSideEffects = 1 in {
1811 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1812 (ins FR32:$src1, FR32:$src2),
1813 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 [], IIC_SSE_CVT_Scalar_RR>,
1815 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1816 Sched<[WriteCvtF2F]>;
1818 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1819 (ins FR32:$src1, f32mem:$src2),
1820 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1821 [], IIC_SSE_CVT_Scalar_RM>,
1822 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1823 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1826 def : Pat<(f64 (fextend FR32:$src)),
1827 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1828 def : Pat<(fextend (loadf32 addr:$src)),
1829 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1831 def : Pat<(extloadf32 addr:$src),
1832 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1833 Requires<[HasAVX, OptForSize]>;
1834 def : Pat<(extloadf32 addr:$src),
1835 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1836 Requires<[HasAVX, OptForSpeed]>;
1838 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1839 "cvtss2sd\t{$src, $dst|$dst, $src}",
1840 [(set FR64:$dst, (fextend FR32:$src))],
1841 IIC_SSE_CVT_Scalar_RR>, XS,
1842 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1843 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1844 "cvtss2sd\t{$src, $dst|$dst, $src}",
1845 [(set FR64:$dst, (extloadf32 addr:$src))],
1846 IIC_SSE_CVT_Scalar_RM>, XS,
1847 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1849 // extload f32 -> f64. This matches load+fextend because we have a hack in
1850 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1852 // Since these loads aren't folded into the fextend, we have to match it
1854 def : Pat<(fextend (loadf32 addr:$src)),
1855 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1856 def : Pat<(extloadf32 addr:$src),
1857 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1859 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1860 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1861 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1863 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1864 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1865 Sched<[WriteCvtF2F]>;
1866 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1867 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1868 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1870 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1871 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1872 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1873 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1874 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1876 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1878 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1879 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2F]>;
1881 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1882 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1883 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1885 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1886 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1887 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1890 // Convert packed single/double fp to doubleword
1891 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1892 "cvtps2dq\t{$src, $dst|$dst, $src}",
1893 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1894 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1895 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1896 "cvtps2dq\t{$src, $dst|$dst, $src}",
1898 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1899 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1900 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1901 "cvtps2dq\t{$src, $dst|$dst, $src}",
1903 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1904 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1905 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1906 "cvtps2dq\t{$src, $dst|$dst, $src}",
1908 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1909 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1910 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1914 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1921 // Convert Packed Double FP to Packed DW Integers
1922 let Predicates = [HasAVX] in {
1923 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1924 // register, but the same isn't true when using memory operands instead.
1925 // Provide other assembly rr and rm forms to address this explicitly.
1926 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1927 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1928 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1929 VEX, Sched<[WriteCvtF2I]>;
1932 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1933 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1934 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1935 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1937 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1938 Sched<[WriteCvtF2ILd]>;
1941 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1942 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1944 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1945 Sched<[WriteCvtF2I]>;
1946 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1947 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1949 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1950 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1951 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1955 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1958 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1959 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1960 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1961 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1962 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1963 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1965 // Convert with truncation packed single/double fp to doubleword
1966 // SSE2 packed instructions with XS prefix
1967 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvttps2dq\t{$src, $dst|$dst, $src}",
1970 (int_x86_sse2_cvttps2dq VR128:$src))],
1971 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1972 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1973 "cvttps2dq\t{$src, $dst|$dst, $src}",
1974 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1975 (memopv4f32 addr:$src)))],
1976 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1977 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1978 "cvttps2dq\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1981 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1982 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1983 "cvttps2dq\t{$src, $dst|$dst, $src}",
1984 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1985 (memopv8f32 addr:$src)))],
1986 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
1987 Sched<[WriteCvtF2ILd]>;
1989 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1990 "cvttps2dq\t{$src, $dst|$dst, $src}",
1991 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1992 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1993 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1994 "cvttps2dq\t{$src, $dst|$dst, $src}",
1996 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1997 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 let Predicates = [HasAVX] in {
2000 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2001 (VCVTDQ2PSrr VR128:$src)>;
2002 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2003 (VCVTDQ2PSrm addr:$src)>;
2005 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2006 (VCVTDQ2PSrr VR128:$src)>;
2007 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2008 (VCVTDQ2PSrm addr:$src)>;
2010 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2011 (VCVTTPS2DQrr VR128:$src)>;
2012 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2013 (VCVTTPS2DQrm addr:$src)>;
2015 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2016 (VCVTDQ2PSYrr VR256:$src)>;
2017 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2018 (VCVTDQ2PSYrm addr:$src)>;
2020 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2021 (VCVTTPS2DQYrr VR256:$src)>;
2022 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2023 (VCVTTPS2DQYrm addr:$src)>;
2026 let Predicates = [UseSSE2] in {
2027 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2028 (CVTDQ2PSrr VR128:$src)>;
2029 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2030 (CVTDQ2PSrm addr:$src)>;
2032 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2033 (CVTDQ2PSrr VR128:$src)>;
2034 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2035 (CVTDQ2PSrm addr:$src)>;
2037 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2038 (CVTTPS2DQrr VR128:$src)>;
2039 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2040 (CVTTPS2DQrm addr:$src)>;
2043 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttpd2dq VR128:$src))],
2047 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2049 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2050 // register, but the same isn't true when using memory operands instead.
2051 // Provide other assembly rr and rm forms to address this explicitly.
2054 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2055 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2056 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2059 (memopv2f64 addr:$src)))],
2060 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2063 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2064 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2066 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2067 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2068 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2069 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2071 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2072 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2073 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2076 let Predicates = [HasAVX] in {
2077 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2078 (VCVTTPD2DQYrr VR256:$src)>;
2079 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2080 (VCVTTPD2DQYrm addr:$src)>;
2081 } // Predicates = [HasAVX]
2083 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2084 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2085 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2086 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2087 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2088 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2090 (memopv2f64 addr:$src)))],
2092 Sched<[WriteCvtF2ILd]>;
2094 // Convert packed single to packed double
2095 let Predicates = [HasAVX] in {
2096 // SSE2 instructions without OpSize prefix
2097 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2098 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2099 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2100 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2101 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2102 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2103 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2104 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2105 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2106 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2108 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2109 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2110 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2111 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2113 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2114 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2117 let Predicates = [UseSSE2] in {
2118 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "cvtps2pd\t{$src, $dst|$dst, $src}",
2120 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2121 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2122 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2123 "cvtps2pd\t{$src, $dst|$dst, $src}",
2124 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2125 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2128 // Convert Packed DW Integers to Packed Double FP
2129 let Predicates = [HasAVX] in {
2130 let neverHasSideEffects = 1, mayLoad = 1 in
2131 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2132 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2133 []>, VEX, Sched<[WriteCvtI2FLd]>;
2134 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2135 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2137 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2138 Sched<[WriteCvtI2F]>;
2139 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2140 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtdq2_pd_256
2143 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2144 Sched<[WriteCvtI2FLd]>;
2145 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2146 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2148 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2149 Sched<[WriteCvtI2F]>;
2152 let neverHasSideEffects = 1, mayLoad = 1 in
2153 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2154 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2155 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2156 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2157 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2158 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2159 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2161 // AVX 256-bit register conversion intrinsics
2162 let Predicates = [HasAVX] in {
2163 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2164 (VCVTDQ2PDYrr VR128:$src)>;
2165 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2166 (VCVTDQ2PDYrm addr:$src)>;
2167 } // Predicates = [HasAVX]
2169 // Convert packed double to packed single
2170 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2171 // register, but the same isn't true when using memory operands instead.
2172 // Provide other assembly rr and rm forms to address this explicitly.
2173 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2179 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2180 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2181 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2182 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2184 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2185 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2188 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2189 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2192 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2193 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2194 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2196 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2197 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2198 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2201 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2203 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2204 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2205 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2206 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2208 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2209 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2212 // AVX 256-bit register conversion intrinsics
2213 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2214 // whenever possible to avoid declaring two versions of each one.
2215 let Predicates = [HasAVX] in {
2216 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2217 (VCVTDQ2PSYrr VR256:$src)>;
2218 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2219 (VCVTDQ2PSYrm addr:$src)>;
2221 // Match fround and fextend for 128/256-bit conversions
2222 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2223 (VCVTPD2PSrr VR128:$src)>;
2224 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2225 (VCVTPD2PSXrm addr:$src)>;
2226 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2227 (VCVTPD2PSYrr VR256:$src)>;
2228 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2229 (VCVTPD2PSYrm addr:$src)>;
2231 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2232 (VCVTPS2PDrr VR128:$src)>;
2233 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2234 (VCVTPS2PDYrr VR128:$src)>;
2235 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2236 (VCVTPS2PDYrm addr:$src)>;
2239 let Predicates = [UseSSE2] in {
2240 // Match fround and fextend for 128 conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (CVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2244 (CVTPD2PSrm addr:$src)>;
2246 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2247 (CVTPS2PDrr VR128:$src)>;
2250 //===----------------------------------------------------------------------===//
2251 // SSE 1 & 2 - Compare Instructions
2252 //===----------------------------------------------------------------------===//
2254 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2255 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2256 Operand CC, SDNode OpNode, ValueType VT,
2257 PatFrag ld_frag, string asm, string asm_alt,
2259 def rr : SIi8<0xC2, MRMSrcReg,
2260 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2261 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2262 itins.rr>, Sched<[itins.Sched]>;
2263 def rm : SIi8<0xC2, MRMSrcMem,
2264 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2265 [(set RC:$dst, (OpNode (VT RC:$src1),
2266 (ld_frag addr:$src2), imm:$cc))],
2268 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2270 // Accept explicit immediate argument form instead of comparison code.
2271 let neverHasSideEffects = 1 in {
2272 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2273 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2274 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2276 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2277 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2278 IIC_SSE_ALU_F32S_RM>,
2279 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2283 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2284 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2285 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2287 XS, VEX_4V, VEX_LIG;
2288 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2289 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2290 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2291 SSE_ALU_F32S>, // same latency as 32 bit compare
2292 XD, VEX_4V, VEX_LIG;
2294 let Constraints = "$src1 = $dst" in {
2295 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2296 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2297 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2299 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2300 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2301 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2302 SSE_ALU_F32S>, // same latency as 32 bit compare
2306 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2307 Intrinsic Int, string asm, OpndItins itins> {
2308 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2309 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2310 [(set VR128:$dst, (Int VR128:$src1,
2311 VR128:$src, imm:$cc))],
2313 Sched<[itins.Sched]>;
2314 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2315 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2316 [(set VR128:$dst, (Int VR128:$src1,
2317 (load addr:$src), imm:$cc))],
2319 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2322 // Aliases to match intrinsics which expect XMM operand(s).
2323 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2324 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2327 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2328 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2329 SSE_ALU_F32S>, // same latency as f32
2331 let Constraints = "$src1 = $dst" in {
2332 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2333 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2335 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2336 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2337 SSE_ALU_F32S>, // same latency as f32
2342 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2343 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2344 ValueType vt, X86MemOperand x86memop,
2345 PatFrag ld_frag, string OpcodeStr, Domain d> {
2346 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2347 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2348 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2349 IIC_SSE_COMIS_RR, d>,
2351 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2352 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2353 [(set EFLAGS, (OpNode (vt RC:$src1),
2354 (ld_frag addr:$src2)))],
2355 IIC_SSE_COMIS_RM, d>,
2356 Sched<[WriteFAddLd, ReadAfterLd]>;
2359 let Defs = [EFLAGS] in {
2360 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2361 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2362 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2363 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2365 let Pattern = []<dag> in {
2366 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2367 "comiss", SSEPackedSingle>, TB, VEX,
2369 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2370 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2374 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2375 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2376 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2377 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2379 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2380 load, "comiss", SSEPackedSingle>, TB, VEX;
2381 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2382 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2383 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2384 "ucomiss", SSEPackedSingle>, TB;
2385 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2386 "ucomisd", SSEPackedDouble>, TB, OpSize;
2388 let Pattern = []<dag> in {
2389 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2390 "comiss", SSEPackedSingle>, TB;
2391 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2392 "comisd", SSEPackedDouble>, TB, OpSize;
2395 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2396 load, "ucomiss", SSEPackedSingle>, TB;
2397 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2398 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2400 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2401 "comiss", SSEPackedSingle>, TB;
2402 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2403 "comisd", SSEPackedDouble>, TB, OpSize;
2404 } // Defs = [EFLAGS]
2406 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2407 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2408 Operand CC, Intrinsic Int, string asm,
2409 string asm_alt, Domain d> {
2410 def rri : PIi8<0xC2, MRMSrcReg,
2411 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2412 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2413 IIC_SSE_CMPP_RR, d>,
2415 def rmi : PIi8<0xC2, MRMSrcMem,
2416 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2417 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2418 IIC_SSE_CMPP_RM, d>,
2419 Sched<[WriteFAddLd, ReadAfterLd]>;
2421 // Accept explicit immediate argument form instead of comparison code.
2422 let neverHasSideEffects = 1 in {
2423 def rri_alt : PIi8<0xC2, MRMSrcReg,
2424 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2425 asm_alt, [], IIC_SSE_CMPP_RR, d>, Sched<[WriteFAdd]>;
2426 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2427 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2428 asm_alt, [], IIC_SSE_CMPP_RM, d>,
2429 Sched<[WriteFAddLd, ReadAfterLd]>;
2433 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2434 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2435 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2436 SSEPackedSingle>, TB, VEX_4V;
2437 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2438 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2439 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2440 SSEPackedDouble>, TB, OpSize, VEX_4V;
2441 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2442 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2443 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2444 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2445 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2446 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2447 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2448 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2449 let Constraints = "$src1 = $dst" in {
2450 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2452 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2453 SSEPackedSingle>, TB;
2454 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2456 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize;
2460 let Predicates = [HasAVX] in {
2461 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2462 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2463 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2464 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2465 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2466 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2467 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2468 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2470 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2471 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2472 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2473 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2474 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2475 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2476 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2477 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2480 let Predicates = [UseSSE1] in {
2481 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2482 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2483 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2484 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2487 let Predicates = [UseSSE2] in {
2488 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2489 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2490 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2491 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2494 //===----------------------------------------------------------------------===//
2495 // SSE 1 & 2 - Shuffle Instructions
2496 //===----------------------------------------------------------------------===//
2498 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2499 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2500 ValueType vt, string asm, PatFrag mem_frag,
2501 Domain d, bit IsConvertibleToThreeAddress = 0> {
2502 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2503 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2504 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2505 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2506 Sched<[WriteShuffleLd, ReadAfterLd]>;
2507 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2508 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2509 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2510 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2511 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2512 Sched<[WriteShuffle]>;
2515 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2516 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2517 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2518 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2519 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2520 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2521 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2522 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2523 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2524 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2525 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2526 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2528 let Constraints = "$src1 = $dst" in {
2529 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2530 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2531 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2533 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2534 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2535 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2539 let Predicates = [HasAVX] in {
2540 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2541 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2542 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2543 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2544 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2546 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2547 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2548 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2549 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2550 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2553 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2554 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2555 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2556 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2557 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2559 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2560 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2561 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2562 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2563 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2566 let Predicates = [UseSSE1] in {
2567 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2568 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2569 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2570 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2571 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2574 let Predicates = [UseSSE2] in {
2575 // Generic SHUFPD patterns
2576 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2577 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2578 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2579 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2580 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2583 //===----------------------------------------------------------------------===//
2584 // SSE 1 & 2 - Unpack Instructions
2585 //===----------------------------------------------------------------------===//
2587 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2588 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2589 PatFrag mem_frag, RegisterClass RC,
2590 X86MemOperand x86memop, string asm,
2592 def rr : PI<opc, MRMSrcReg,
2593 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2595 (vt (OpNode RC:$src1, RC:$src2)))],
2596 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2597 def rm : PI<opc, MRMSrcMem,
2598 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2600 (vt (OpNode RC:$src1,
2601 (mem_frag addr:$src2))))],
2603 Sched<[WriteShuffleLd, ReadAfterLd]>;
2606 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2607 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2608 SSEPackedSingle>, TB, VEX_4V;
2609 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2610 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2611 SSEPackedDouble>, TB, OpSize, VEX_4V;
2612 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2613 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2614 SSEPackedSingle>, TB, VEX_4V;
2615 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2616 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2617 SSEPackedDouble>, TB, OpSize, VEX_4V;
2619 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2620 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2621 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2622 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2623 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2624 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2625 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2626 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2627 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2628 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2629 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2630 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2632 let Constraints = "$src1 = $dst" in {
2633 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2634 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2635 SSEPackedSingle>, TB;
2636 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2637 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2638 SSEPackedDouble>, TB, OpSize;
2639 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2640 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2641 SSEPackedSingle>, TB;
2642 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2643 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2644 SSEPackedDouble>, TB, OpSize;
2645 } // Constraints = "$src1 = $dst"
2647 let Predicates = [HasAVX1Only] in {
2648 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2649 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2650 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2651 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2652 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2653 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2654 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2655 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2657 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2658 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2659 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2660 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2661 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2662 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2663 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2664 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2667 let Predicates = [HasAVX] in {
2668 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2669 // problem is during lowering, where it's not possible to recognize the load
2670 // fold cause it has two uses through a bitcast. One use disappears at isel
2671 // time and the fold opportunity reappears.
2672 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2673 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2676 let Predicates = [UseSSE2] in {
2677 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2678 // problem is during lowering, where it's not possible to recognize the load
2679 // fold cause it has two uses through a bitcast. One use disappears at isel
2680 // time and the fold opportunity reappears.
2681 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2682 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2685 //===----------------------------------------------------------------------===//
2686 // SSE 1 & 2 - Extract Floating-Point Sign mask
2687 //===----------------------------------------------------------------------===//
2689 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2690 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2692 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2693 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2694 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2695 Sched<[WriteVecLogic]>;
2696 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2697 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2698 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2701 let Predicates = [HasAVX] in {
2702 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2703 "movmskps", SSEPackedSingle>, TB, VEX;
2704 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2705 "movmskpd", SSEPackedDouble>, TB,
2707 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2708 "movmskps", SSEPackedSingle>, TB,
2710 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2711 "movmskpd", SSEPackedDouble>, TB,
2714 def : Pat<(i32 (X86fgetsign FR32:$src)),
2715 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2716 def : Pat<(i64 (X86fgetsign FR32:$src)),
2717 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2718 def : Pat<(i32 (X86fgetsign FR64:$src)),
2719 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2720 def : Pat<(i64 (X86fgetsign FR64:$src)),
2721 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2724 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2725 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2726 SSEPackedSingle>, TB, VEX, Sched<[WriteVecLogic]>;
2727 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2728 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2729 SSEPackedDouble>, TB,
2730 OpSize, VEX, Sched<[WriteVecLogic]>;
2731 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2732 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2733 SSEPackedSingle>, TB, VEX, VEX_L, Sched<[WriteVecLogic]>;
2734 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2735 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2736 SSEPackedDouble>, TB,
2737 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2740 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2741 SSEPackedSingle>, TB;
2742 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2743 SSEPackedDouble>, TB, OpSize;
2745 def : Pat<(i32 (X86fgetsign FR32:$src)),
2746 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2747 Requires<[UseSSE1]>;
2748 def : Pat<(i64 (X86fgetsign FR32:$src)),
2749 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2750 Requires<[UseSSE1]>;
2751 def : Pat<(i32 (X86fgetsign FR64:$src)),
2752 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2753 Requires<[UseSSE2]>;
2754 def : Pat<(i64 (X86fgetsign FR64:$src)),
2755 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2756 Requires<[UseSSE2]>;
2758 //===---------------------------------------------------------------------===//
2759 // SSE2 - Packed Integer Logical Instructions
2760 //===---------------------------------------------------------------------===//
2762 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2764 /// PDI_binop_rm - Simple SSE2 binary operator.
2765 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2766 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2767 X86MemOperand x86memop, OpndItins itins,
2768 bit IsCommutable, bit Is2Addr> {
2769 let isCommutable = IsCommutable in
2770 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2771 (ins RC:$src1, RC:$src2),
2773 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2774 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2775 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2776 Sched<[itins.Sched]>;
2777 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2778 (ins RC:$src1, x86memop:$src2),
2780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2782 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2783 (bitconvert (memop_frag addr:$src2)))))],
2785 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2787 } // ExeDomain = SSEPackedInt
2789 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2790 ValueType OpVT128, ValueType OpVT256,
2791 OpndItins itins, bit IsCommutable = 0> {
2792 let Predicates = [HasAVX] in
2793 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2794 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2796 let Constraints = "$src1 = $dst" in
2797 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2798 memopv2i64, i128mem, itins, IsCommutable, 1>;
2800 let Predicates = [HasAVX2] in
2801 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2802 OpVT256, VR256, memopv4i64, i256mem, itins,
2803 IsCommutable, 0>, VEX_4V, VEX_L;
2806 // These are ordered here for pattern ordering requirements with the fp versions
2808 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2809 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2810 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2811 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2812 SSE_BIT_ITINS_P, 0>;
2814 //===----------------------------------------------------------------------===//
2815 // SSE 1 & 2 - Logical Instructions
2816 //===----------------------------------------------------------------------===//
2818 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2820 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2821 SDNode OpNode, OpndItins itins> {
2822 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2823 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2826 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2827 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2830 let Constraints = "$src1 = $dst" in {
2831 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2832 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2835 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2836 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2841 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2842 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2844 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2846 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2849 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2850 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2853 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2855 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2857 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2858 !strconcat(OpcodeStr, "ps"), f256mem,
2859 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2860 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2861 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2863 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2864 !strconcat(OpcodeStr, "pd"), f256mem,
2865 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2866 (bc_v4i64 (v4f64 VR256:$src2))))],
2867 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2868 (memopv4i64 addr:$src2)))], 0>,
2869 TB, OpSize, VEX_4V, VEX_L;
2871 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2872 // are all promoted to v2i64, and the patterns are covered by the int
2873 // version. This is needed in SSE only, because v2i64 isn't supported on
2874 // SSE1, but only on SSE2.
2875 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2876 !strconcat(OpcodeStr, "ps"), f128mem, [],
2877 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2878 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2880 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2881 !strconcat(OpcodeStr, "pd"), f128mem,
2882 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2883 (bc_v2i64 (v2f64 VR128:$src2))))],
2884 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2885 (memopv2i64 addr:$src2)))], 0>,
2888 let Constraints = "$src1 = $dst" in {
2889 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2890 !strconcat(OpcodeStr, "ps"), f128mem,
2891 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2892 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2893 (memopv2i64 addr:$src2)))]>, TB;
2895 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2896 !strconcat(OpcodeStr, "pd"), f128mem,
2897 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2898 (bc_v2i64 (v2f64 VR128:$src2))))],
2899 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2900 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2904 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2905 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2906 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2907 let isCommutable = 0 in
2908 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2910 //===----------------------------------------------------------------------===//
2911 // SSE 1 & 2 - Arithmetic Instructions
2912 //===----------------------------------------------------------------------===//
2914 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2917 /// In addition, we also have a special variant of the scalar form here to
2918 /// represent the associated intrinsic operation. This form is unlike the
2919 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2920 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2922 /// These three forms can each be reg+reg or reg+mem.
2925 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2927 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2930 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2931 OpNode, FR32, f32mem,
2932 itins.s, Is2Addr>, XS;
2933 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2934 OpNode, FR64, f64mem,
2935 itins.d, Is2Addr>, XD;
2938 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2939 SDNode OpNode, SizeItins itins> {
2940 let Predicates = [HasAVX] in {
2941 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2942 VR128, v4f32, f128mem, memopv4f32,
2943 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2944 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2945 VR128, v2f64, f128mem, memopv2f64,
2946 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2948 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2949 OpNode, VR256, v8f32, f256mem, memopv8f32,
2950 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2951 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2952 OpNode, VR256, v4f64, f256mem, memopv4f64,
2953 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2956 let Constraints = "$src1 = $dst" in {
2957 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2958 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2960 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2961 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2962 itins.d, 1>, TB, OpSize;
2966 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2969 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2970 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2971 itins.s, Is2Addr>, XS;
2972 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2973 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2974 itins.d, Is2Addr>, XD;
2977 // Binary Arithmetic instructions
2978 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
2979 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
2980 let isCommutable = 0 in {
2981 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
2982 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
2983 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
2984 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
2987 let isCodeGenOnly = 1 in {
2988 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2989 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2992 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2993 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2995 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2996 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2999 let isCommutable = 0 in {
3000 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
3001 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
3003 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
3004 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
3006 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
3007 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
3009 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
3010 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
3014 let Constraints = "$src1 = $dst" in {
3015 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3016 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3017 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3018 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3020 let isCommutable = 0 in {
3021 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3022 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3023 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3024 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3025 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3026 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3027 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3028 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3032 let isCodeGenOnly = 1 in {
3033 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
3035 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
3037 let Constraints = "$src1 = $dst" in {
3038 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3039 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3044 /// In addition, we also have a special variant of the scalar form here to
3045 /// represent the associated intrinsic operation. This form is unlike the
3046 /// plain scalar form, in that it takes an entire vector (instead of a
3047 /// scalar) and leaves the top elements undefined.
3049 /// And, we have a special variant form for a full-vector intrinsic form.
3051 let Sched = WriteFSqrt in {
3052 def SSE_SQRTP : OpndItins<
3053 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
3056 def SSE_SQRTS : OpndItins<
3057 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3061 let Sched = WriteFRcp in {
3062 def SSE_RCPP : OpndItins<
3063 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3066 def SSE_RCPS : OpndItins<
3067 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3071 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3072 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3073 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3074 let Predicates = [HasAVX], hasSideEffects = 0 in {
3075 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3076 (ins FR32:$src1, FR32:$src2),
3077 !strconcat("v", OpcodeStr,
3078 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3079 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3080 let mayLoad = 1 in {
3081 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3082 (ins FR32:$src1,f32mem:$src2),
3083 !strconcat("v", OpcodeStr,
3084 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3085 []>, VEX_4V, VEX_LIG,
3086 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3087 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3088 (ins VR128:$src1, ssmem:$src2),
3089 !strconcat("v", OpcodeStr,
3090 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3091 []>, VEX_4V, VEX_LIG,
3092 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3096 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3097 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3098 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3099 // For scalar unary operations, fold a load into the operation
3100 // only in OptForSize mode. It eliminates an instruction, but it also
3101 // eliminates a whole-register clobber (the load), so it introduces a
3102 // partial register update condition.
3103 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3104 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3105 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3106 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3107 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3108 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3109 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3110 Sched<[itins.Sched]>;
3111 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3112 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3113 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3114 Sched<[itins.Sched.Folded]>;
3117 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3118 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3120 let Predicates = [HasAVX], hasSideEffects = 0 in {
3121 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3122 (ins FR32:$src1, FR32:$src2),
3123 !strconcat("v", OpcodeStr,
3124 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3125 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3126 let mayLoad = 1 in {
3127 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3128 (ins FR32:$src1,f32mem:$src2),
3129 !strconcat("v", OpcodeStr,
3130 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3131 []>, VEX_4V, VEX_LIG,
3132 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3133 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3134 (ins VR128:$src1, ssmem:$src2),
3135 !strconcat("v", OpcodeStr,
3136 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3137 []>, VEX_4V, VEX_LIG,
3138 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3142 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3143 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3144 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3145 // For scalar unary operations, fold a load into the operation
3146 // only in OptForSize mode. It eliminates an instruction, but it also
3147 // eliminates a whole-register clobber (the load), so it introduces a
3148 // partial register update condition.
3149 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3150 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3151 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3152 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3153 let Constraints = "$src1 = $dst" in {
3154 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3155 (ins VR128:$src1, VR128:$src2),
3156 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3157 [], itins.rr>, Sched<[itins.Sched]>;
3158 let mayLoad = 1, hasSideEffects = 0 in
3159 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3160 (ins VR128:$src1, ssmem:$src2),
3161 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3162 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3166 /// sse1_fp_unop_p - SSE1 unops in packed form.
3167 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3169 let Predicates = [HasAVX] in {
3170 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3171 !strconcat("v", OpcodeStr,
3172 "ps\t{$src, $dst|$dst, $src}"),
3173 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3174 itins.rr>, VEX, Sched<[itins.Sched]>;
3175 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3176 !strconcat("v", OpcodeStr,
3177 "ps\t{$src, $dst|$dst, $src}"),
3178 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3179 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3180 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3181 !strconcat("v", OpcodeStr,
3182 "ps\t{$src, $dst|$dst, $src}"),
3183 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3184 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3185 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3186 !strconcat("v", OpcodeStr,
3187 "ps\t{$src, $dst|$dst, $src}"),
3188 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3189 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3192 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3193 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3194 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3195 Sched<[itins.Sched]>;
3196 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3197 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3198 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3199 Sched<[itins.Sched.Folded]>;
3202 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3203 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3204 Intrinsic V4F32Int, Intrinsic V8F32Int,
3206 let Predicates = [HasAVX] in {
3207 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3208 !strconcat("v", OpcodeStr,
3209 "ps\t{$src, $dst|$dst, $src}"),
3210 [(set VR128:$dst, (V4F32Int VR128:$src))],
3211 itins.rr>, VEX, Sched<[itins.Sched]>;
3212 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3213 !strconcat("v", OpcodeStr,
3214 "ps\t{$src, $dst|$dst, $src}"),
3215 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3216 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3217 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3218 !strconcat("v", OpcodeStr,
3219 "ps\t{$src, $dst|$dst, $src}"),
3220 [(set VR256:$dst, (V8F32Int VR256:$src))],
3221 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3222 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3224 !strconcat("v", OpcodeStr,
3225 "ps\t{$src, $dst|$dst, $src}"),
3226 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3227 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3230 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3231 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3232 [(set VR128:$dst, (V4F32Int VR128:$src))],
3233 itins.rr>, Sched<[itins.Sched]>;
3234 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3235 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3236 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3237 itins.rm>, Sched<[itins.Sched.Folded]>;
3240 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3241 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3242 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3243 let Predicates = [HasAVX], hasSideEffects = 0 in {
3244 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3245 (ins FR64:$src1, FR64:$src2),
3246 !strconcat("v", OpcodeStr,
3247 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3248 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3249 let mayLoad = 1 in {
3250 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3251 (ins FR64:$src1,f64mem:$src2),
3252 !strconcat("v", OpcodeStr,
3253 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3254 []>, VEX_4V, VEX_LIG,
3255 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3256 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3257 (ins VR128:$src1, sdmem:$src2),
3258 !strconcat("v", OpcodeStr,
3259 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3260 []>, VEX_4V, VEX_LIG,
3261 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3265 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3266 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3267 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3268 Sched<[itins.Sched]>;
3269 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3270 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3271 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3272 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3273 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3274 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3275 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3276 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3277 Sched<[itins.Sched]>;
3278 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3279 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3280 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3281 Sched<[itins.Sched.Folded]>;
3284 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3285 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3286 SDNode OpNode, OpndItins itins> {
3287 let Predicates = [HasAVX] in {
3288 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3289 !strconcat("v", OpcodeStr,
3290 "pd\t{$src, $dst|$dst, $src}"),
3291 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3292 itins.rr>, VEX, Sched<[itins.Sched]>;
3293 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3294 !strconcat("v", OpcodeStr,
3295 "pd\t{$src, $dst|$dst, $src}"),
3296 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3297 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3298 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3299 !strconcat("v", OpcodeStr,
3300 "pd\t{$src, $dst|$dst, $src}"),
3301 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3302 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3303 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3304 !strconcat("v", OpcodeStr,
3305 "pd\t{$src, $dst|$dst, $src}"),
3306 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3307 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3310 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3311 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3312 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3313 Sched<[itins.Sched]>;
3314 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3315 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3316 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3317 Sched<[itins.Sched.Folded]>;
3321 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3323 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
3324 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3326 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
3328 // Reciprocal approximations. Note that these typically require refinement
3329 // in order to obtain suitable precision.
3330 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3331 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
3332 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3333 int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;
3334 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3335 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3336 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3337 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3339 def : Pat<(f32 (fsqrt FR32:$src)),
3340 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3341 def : Pat<(f32 (fsqrt (load addr:$src))),
3342 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3343 Requires<[HasAVX, OptForSize]>;
3344 def : Pat<(f64 (fsqrt FR64:$src)),
3345 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3346 def : Pat<(f64 (fsqrt (load addr:$src))),
3347 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3348 Requires<[HasAVX, OptForSize]>;
3350 def : Pat<(f32 (X86frsqrt FR32:$src)),
3351 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3352 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3353 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3354 Requires<[HasAVX, OptForSize]>;
3356 def : Pat<(f32 (X86frcp FR32:$src)),
3357 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3358 def : Pat<(f32 (X86frcp (load addr:$src))),
3359 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3360 Requires<[HasAVX, OptForSize]>;
3362 let Predicates = [HasAVX] in {
3363 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3364 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3365 (COPY_TO_REGCLASS VR128:$src, FR32)),
3367 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3368 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3370 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3371 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3372 (COPY_TO_REGCLASS VR128:$src, FR64)),
3374 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3375 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3377 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3378 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3379 (COPY_TO_REGCLASS VR128:$src, FR32)),
3381 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3382 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3384 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3385 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3386 (COPY_TO_REGCLASS VR128:$src, FR32)),
3388 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3389 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3392 // Reciprocal approximations. Note that these typically require refinement
3393 // in order to obtain suitable precision.
3394 let Predicates = [UseSSE1] in {
3395 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3396 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3397 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3398 (RCPSSr_Int VR128:$src, VR128:$src)>;
3401 // There is no f64 version of the reciprocal approximation instructions.
3403 //===----------------------------------------------------------------------===//
3404 // SSE 1 & 2 - Non-temporal stores
3405 //===----------------------------------------------------------------------===//
3407 let AddedComplexity = 400 in { // Prefer non-temporal versions
3408 let SchedRW = [WriteStore] in {
3409 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3410 (ins f128mem:$dst, VR128:$src),
3411 "movntps\t{$src, $dst|$dst, $src}",
3412 [(alignednontemporalstore (v4f32 VR128:$src),
3414 IIC_SSE_MOVNT>, VEX;
3415 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3416 (ins f128mem:$dst, VR128:$src),
3417 "movntpd\t{$src, $dst|$dst, $src}",
3418 [(alignednontemporalstore (v2f64 VR128:$src),
3420 IIC_SSE_MOVNT>, VEX;
3422 let ExeDomain = SSEPackedInt in
3423 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3424 (ins f128mem:$dst, VR128:$src),
3425 "movntdq\t{$src, $dst|$dst, $src}",
3426 [(alignednontemporalstore (v2i64 VR128:$src),
3428 IIC_SSE_MOVNT>, VEX;
3430 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3431 (ins f256mem:$dst, VR256:$src),
3432 "movntps\t{$src, $dst|$dst, $src}",
3433 [(alignednontemporalstore (v8f32 VR256:$src),
3435 IIC_SSE_MOVNT>, VEX, VEX_L;
3436 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3437 (ins f256mem:$dst, VR256:$src),
3438 "movntpd\t{$src, $dst|$dst, $src}",
3439 [(alignednontemporalstore (v4f64 VR256:$src),
3441 IIC_SSE_MOVNT>, VEX, VEX_L;
3442 let ExeDomain = SSEPackedInt in
3443 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3444 (ins f256mem:$dst, VR256:$src),
3445 "movntdq\t{$src, $dst|$dst, $src}",
3446 [(alignednontemporalstore (v4i64 VR256:$src),
3448 IIC_SSE_MOVNT>, VEX, VEX_L;
3450 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3451 "movntps\t{$src, $dst|$dst, $src}",
3452 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3454 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3455 "movntpd\t{$src, $dst|$dst, $src}",
3456 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3459 let ExeDomain = SSEPackedInt in
3460 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3461 "movntdq\t{$src, $dst|$dst, $src}",
3462 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3465 // There is no AVX form for instructions below this point
3466 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3467 "movnti{l}\t{$src, $dst|$dst, $src}",
3468 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3470 TB, Requires<[HasSSE2]>;
3471 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3472 "movnti{q}\t{$src, $dst|$dst, $src}",
3473 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3475 TB, Requires<[HasSSE2]>;
3476 } // SchedRW = [WriteStore]
3478 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3479 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3481 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3482 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3483 } // AddedComplexity
3485 //===----------------------------------------------------------------------===//
3486 // SSE 1 & 2 - Prefetch and memory fence
3487 //===----------------------------------------------------------------------===//
3489 // Prefetch intrinsic.
3490 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3491 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3492 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3493 IIC_SSE_PREFETCH>, TB;
3494 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3495 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3496 IIC_SSE_PREFETCH>, TB;
3497 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3498 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3499 IIC_SSE_PREFETCH>, TB;
3500 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3501 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3502 IIC_SSE_PREFETCH>, TB;
3505 // FIXME: How should these memory instructions be modeled?
3506 let SchedRW = [WriteLoad] in {
3508 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3509 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3510 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3512 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3513 // was introduced with SSE2, it's backward compatible.
3514 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3516 // Load, store, and memory fence
3517 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3518 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3519 TB, Requires<[HasSSE1]>;
3520 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3521 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3522 TB, Requires<[HasSSE2]>;
3523 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3524 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3525 TB, Requires<[HasSSE2]>;
3528 def : Pat<(X86SFence), (SFENCE)>;
3529 def : Pat<(X86LFence), (LFENCE)>;
3530 def : Pat<(X86MFence), (MFENCE)>;
3532 //===----------------------------------------------------------------------===//
3533 // SSE 1 & 2 - Load/Store XCSR register
3534 //===----------------------------------------------------------------------===//
3536 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3537 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3538 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3539 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3540 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3541 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3543 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3544 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3545 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3546 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3547 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3548 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3550 //===---------------------------------------------------------------------===//
3551 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3552 //===---------------------------------------------------------------------===//
3554 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3556 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3557 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3558 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3560 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3561 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3563 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3564 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3566 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3567 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3572 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3573 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3574 "movdqa\t{$src, $dst|$dst, $src}", [],
3577 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3578 "movdqa\t{$src, $dst|$dst, $src}", [],
3579 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3580 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3581 "movdqu\t{$src, $dst|$dst, $src}", [],
3584 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3585 "movdqu\t{$src, $dst|$dst, $src}", [],
3586 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3589 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3590 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3591 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3592 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3594 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3595 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3597 let Predicates = [HasAVX] in {
3598 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3599 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3601 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3602 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3607 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3608 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3609 (ins i128mem:$dst, VR128:$src),
3610 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3612 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3613 (ins i256mem:$dst, VR256:$src),
3614 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3616 let Predicates = [HasAVX] in {
3617 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3618 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3620 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3621 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3626 let SchedRW = [WriteMove] in {
3627 let neverHasSideEffects = 1 in
3628 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3629 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3631 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3632 "movdqu\t{$src, $dst|$dst, $src}",
3633 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3636 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3637 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3638 "movdqa\t{$src, $dst|$dst, $src}", [],
3641 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3642 "movdqu\t{$src, $dst|$dst, $src}",
3643 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3647 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3648 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3649 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3650 "movdqa\t{$src, $dst|$dst, $src}",
3651 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3653 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3654 "movdqu\t{$src, $dst|$dst, $src}",
3655 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3657 XS, Requires<[UseSSE2]>;
3660 let mayStore = 1, SchedRW = [WriteStore] in {
3661 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3662 "movdqa\t{$src, $dst|$dst, $src}",
3663 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3665 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3666 "movdqu\t{$src, $dst|$dst, $src}",
3667 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3669 XS, Requires<[UseSSE2]>;
3672 } // ExeDomain = SSEPackedInt
3674 let Predicates = [HasAVX] in {
3675 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3676 (VMOVDQUmr addr:$dst, VR128:$src)>;
3677 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3678 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3680 let Predicates = [UseSSE2] in
3681 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3682 (MOVDQUmr addr:$dst, VR128:$src)>;
3684 //===---------------------------------------------------------------------===//
3685 // SSE2 - Packed Integer Arithmetic Instructions
3686 //===---------------------------------------------------------------------===//
3688 let Sched = WriteVecIMul in
3689 def SSE_PMADD : OpndItins<
3690 IIC_SSE_PMADD, IIC_SSE_PMADD
3693 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3695 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3696 RegisterClass RC, PatFrag memop_frag,
3697 X86MemOperand x86memop,
3699 bit IsCommutable = 0,
3701 let isCommutable = IsCommutable in
3702 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3703 (ins RC:$src1, RC:$src2),
3705 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3707 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3708 Sched<[itins.Sched]>;
3709 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3710 (ins RC:$src1, x86memop:$src2),
3712 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3713 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3714 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3715 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3718 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3719 Intrinsic IntId256, OpndItins itins,
3720 bit IsCommutable = 0> {
3721 let Predicates = [HasAVX] in
3722 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3723 VR128, memopv2i64, i128mem, itins,
3724 IsCommutable, 0>, VEX_4V;
3726 let Constraints = "$src1 = $dst" in
3727 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3728 i128mem, itins, IsCommutable, 1>;
3730 let Predicates = [HasAVX2] in
3731 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3732 VR256, memopv4i64, i256mem, itins,
3733 IsCommutable, 0>, VEX_4V, VEX_L;
3736 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3737 string OpcodeStr, SDNode OpNode,
3738 SDNode OpNode2, RegisterClass RC,
3739 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3740 ShiftOpndItins itins,
3742 // src2 is always 128-bit
3743 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3744 (ins RC:$src1, VR128:$src2),
3746 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3747 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3748 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3749 itins.rr>, Sched<[WriteVecShift]>;
3750 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3751 (ins RC:$src1, i128mem:$src2),
3753 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3754 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3755 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3756 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3757 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3758 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3759 (ins RC:$src1, i32i8imm:$src2),
3761 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3762 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3763 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3764 Sched<[WriteVecShift]>;
3767 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3768 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3769 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3770 PatFrag memop_frag, X86MemOperand x86memop,
3772 bit IsCommutable = 0, bit Is2Addr = 1> {
3773 let isCommutable = IsCommutable in
3774 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3775 (ins RC:$src1, RC:$src2),
3777 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3778 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3779 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3780 Sched<[itins.Sched]>;
3781 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3782 (ins RC:$src1, x86memop:$src2),
3784 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3785 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3786 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3787 (bitconvert (memop_frag addr:$src2)))))]>,
3788 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3790 } // ExeDomain = SSEPackedInt
3792 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3793 SSE_INTALU_ITINS_P, 1>;
3794 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3795 SSE_INTALU_ITINS_P, 1>;
3796 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3797 SSE_INTALU_ITINS_P, 1>;
3798 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3799 SSE_INTALUQ_ITINS_P, 1>;
3800 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3801 SSE_INTMUL_ITINS_P, 1>;
3802 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3803 SSE_INTALU_ITINS_P, 0>;
3804 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3805 SSE_INTALU_ITINS_P, 0>;
3806 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3807 SSE_INTALU_ITINS_P, 0>;
3808 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3809 SSE_INTALUQ_ITINS_P, 0>;
3810 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3811 SSE_INTALU_ITINS_P, 0>;
3812 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3813 SSE_INTALU_ITINS_P, 0>;
3814 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3815 SSE_INTALU_ITINS_P, 1>;
3816 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3817 SSE_INTALU_ITINS_P, 1>;
3818 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3819 SSE_INTALU_ITINS_P, 1>;
3820 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3821 SSE_INTALU_ITINS_P, 1>;
3824 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3825 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3826 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3827 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3828 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3829 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3830 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3831 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3832 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3833 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3834 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3835 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3836 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3837 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3838 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3839 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3840 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3841 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3842 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3843 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3844 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3845 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3846 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3847 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3849 let Predicates = [HasAVX] in
3850 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3851 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3853 let Predicates = [HasAVX2] in
3854 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3855 VR256, memopv4i64, i256mem,
3856 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3857 let Constraints = "$src1 = $dst" in
3858 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3859 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3861 //===---------------------------------------------------------------------===//
3862 // SSE2 - Packed Integer Logical Instructions
3863 //===---------------------------------------------------------------------===//
3865 let Predicates = [HasAVX] in {
3866 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3867 VR128, v8i16, v8i16, bc_v8i16,
3868 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3869 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3870 VR128, v4i32, v4i32, bc_v4i32,
3871 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3872 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3873 VR128, v2i64, v2i64, bc_v2i64,
3874 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3876 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3877 VR128, v8i16, v8i16, bc_v8i16,
3878 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3879 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3880 VR128, v4i32, v4i32, bc_v4i32,
3881 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3882 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3883 VR128, v2i64, v2i64, bc_v2i64,
3884 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3886 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3887 VR128, v8i16, v8i16, bc_v8i16,
3888 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3889 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3890 VR128, v4i32, v4i32, bc_v4i32,
3891 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3893 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3894 // 128-bit logical shifts.
3895 def VPSLLDQri : PDIi8<0x73, MRM7r,
3896 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3897 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3899 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3901 def VPSRLDQri : PDIi8<0x73, MRM3r,
3902 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3903 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3905 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3907 // PSRADQri doesn't exist in SSE[1-3].
3909 } // Predicates = [HasAVX]
3911 let Predicates = [HasAVX2] in {
3912 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3913 VR256, v16i16, v8i16, bc_v8i16,
3914 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3915 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3916 VR256, v8i32, v4i32, bc_v4i32,
3917 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3918 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3919 VR256, v4i64, v2i64, bc_v2i64,
3920 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3922 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3923 VR256, v16i16, v8i16, bc_v8i16,
3924 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3925 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3926 VR256, v8i32, v4i32, bc_v4i32,
3927 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3928 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3929 VR256, v4i64, v2i64, bc_v2i64,
3930 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3932 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3933 VR256, v16i16, v8i16, bc_v8i16,
3934 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3935 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3936 VR256, v8i32, v4i32, bc_v4i32,
3937 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3939 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3940 // 256-bit logical shifts.
3941 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3942 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3943 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3945 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3947 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3948 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3949 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3951 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3953 // PSRADQYri doesn't exist in SSE[1-3].
3955 } // Predicates = [HasAVX2]
3957 let Constraints = "$src1 = $dst" in {
3958 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3959 VR128, v8i16, v8i16, bc_v8i16,
3960 SSE_INTSHIFT_ITINS_P>;
3961 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3962 VR128, v4i32, v4i32, bc_v4i32,
3963 SSE_INTSHIFT_ITINS_P>;
3964 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3965 VR128, v2i64, v2i64, bc_v2i64,
3966 SSE_INTSHIFT_ITINS_P>;
3968 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3969 VR128, v8i16, v8i16, bc_v8i16,
3970 SSE_INTSHIFT_ITINS_P>;
3971 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3972 VR128, v4i32, v4i32, bc_v4i32,
3973 SSE_INTSHIFT_ITINS_P>;
3974 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3975 VR128, v2i64, v2i64, bc_v2i64,
3976 SSE_INTSHIFT_ITINS_P>;
3978 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3979 VR128, v8i16, v8i16, bc_v8i16,
3980 SSE_INTSHIFT_ITINS_P>;
3981 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3982 VR128, v4i32, v4i32, bc_v4i32,
3983 SSE_INTSHIFT_ITINS_P>;
3985 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3986 // 128-bit logical shifts.
3987 def PSLLDQri : PDIi8<0x73, MRM7r,
3988 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3989 "pslldq\t{$src2, $dst|$dst, $src2}",
3991 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3992 def PSRLDQri : PDIi8<0x73, MRM3r,
3993 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3994 "psrldq\t{$src2, $dst|$dst, $src2}",
3996 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3997 // PSRADQri doesn't exist in SSE[1-3].
3999 } // Constraints = "$src1 = $dst"
4001 let Predicates = [HasAVX] in {
4002 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4003 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4004 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4005 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4006 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4007 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4009 // Shift up / down and insert zero's.
4010 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4011 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4012 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4013 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4016 let Predicates = [HasAVX2] in {
4017 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4018 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4019 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4020 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4023 let Predicates = [UseSSE2] in {
4024 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4025 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4026 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4027 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4028 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4029 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4031 // Shift up / down and insert zero's.
4032 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4033 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4034 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4035 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4038 //===---------------------------------------------------------------------===//
4039 // SSE2 - Packed Integer Comparison Instructions
4040 //===---------------------------------------------------------------------===//
4042 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4043 SSE_INTALU_ITINS_P, 1>;
4044 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4045 SSE_INTALU_ITINS_P, 1>;
4046 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4047 SSE_INTALU_ITINS_P, 1>;
4048 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4049 SSE_INTALU_ITINS_P, 0>;
4050 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4051 SSE_INTALU_ITINS_P, 0>;
4052 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4053 SSE_INTALU_ITINS_P, 0>;
4055 //===---------------------------------------------------------------------===//
4056 // SSE2 - Packed Integer Pack Instructions
4057 //===---------------------------------------------------------------------===//
4059 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4060 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4061 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4062 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4063 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4064 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4066 //===---------------------------------------------------------------------===//
4067 // SSE2 - Packed Integer Shuffle Instructions
4068 //===---------------------------------------------------------------------===//
4070 let ExeDomain = SSEPackedInt in {
4071 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4073 let Predicates = [HasAVX] in {
4074 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4075 (ins VR128:$src1, i8imm:$src2),
4076 !strconcat("v", OpcodeStr,
4077 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4079 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4080 IIC_SSE_PSHUF>, VEX, Sched<[WriteShuffle]>;
4081 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4082 (ins i128mem:$src1, i8imm:$src2),
4083 !strconcat("v", OpcodeStr,
4084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4087 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX,
4088 Sched<[WriteShuffleLd]>;
4091 let Predicates = [HasAVX2] in {
4092 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4093 (ins VR256:$src1, i8imm:$src2),
4094 !strconcat("v", OpcodeStr,
4095 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4097 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4098 IIC_SSE_PSHUF>, VEX, VEX_L, Sched<[WriteShuffle]>;
4099 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4100 (ins i256mem:$src1, i8imm:$src2),
4101 !strconcat("v", OpcodeStr,
4102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4104 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4105 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX, VEX_L,
4106 Sched<[WriteShuffleLd]>;
4109 let Predicates = [UseSSE2] in {
4110 def ri : Ii8<0x70, MRMSrcReg,
4111 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4112 !strconcat(OpcodeStr,
4113 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4115 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4116 IIC_SSE_PSHUF>, Sched<[WriteShuffle]>;
4117 def mi : Ii8<0x70, MRMSrcMem,
4118 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4119 !strconcat(OpcodeStr,
4120 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4122 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4123 (i8 imm:$src2))))], IIC_SSE_PSHUF>,
4124 Sched<[WriteShuffleLd]>;
4127 } // ExeDomain = SSEPackedInt
4129 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4130 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4131 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4133 let Predicates = [HasAVX] in {
4134 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4135 (VPSHUFDmi addr:$src1, imm:$imm)>;
4136 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4137 (VPSHUFDri VR128:$src1, imm:$imm)>;
4140 let Predicates = [UseSSE2] in {
4141 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4142 (PSHUFDmi addr:$src1, imm:$imm)>;
4143 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4144 (PSHUFDri VR128:$src1, imm:$imm)>;
4147 //===---------------------------------------------------------------------===//
4148 // SSE2 - Packed Integer Unpack Instructions
4149 //===---------------------------------------------------------------------===//
4151 let ExeDomain = SSEPackedInt in {
4152 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4153 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4154 def rr : PDI<opc, MRMSrcReg,
4155 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4157 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4158 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4159 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4160 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4161 def rm : PDI<opc, MRMSrcMem,
4162 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4164 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4165 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4166 [(set VR128:$dst, (OpNode VR128:$src1,
4167 (bc_frag (memopv2i64
4170 Sched<[WriteShuffleLd, ReadAfterLd]>;
4173 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4174 SDNode OpNode, PatFrag bc_frag> {
4175 def Yrr : PDI<opc, MRMSrcReg,
4176 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4177 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4178 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4179 Sched<[WriteShuffle]>;
4180 def Yrm : PDI<opc, MRMSrcMem,
4181 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4182 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4183 [(set VR256:$dst, (OpNode VR256:$src1,
4184 (bc_frag (memopv4i64 addr:$src2))))]>,
4185 Sched<[WriteShuffleLd, ReadAfterLd]>;
4188 let Predicates = [HasAVX] in {
4189 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4190 bc_v16i8, 0>, VEX_4V;
4191 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4192 bc_v8i16, 0>, VEX_4V;
4193 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4194 bc_v4i32, 0>, VEX_4V;
4195 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4196 bc_v2i64, 0>, VEX_4V;
4198 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4199 bc_v16i8, 0>, VEX_4V;
4200 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4201 bc_v8i16, 0>, VEX_4V;
4202 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4203 bc_v4i32, 0>, VEX_4V;
4204 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4205 bc_v2i64, 0>, VEX_4V;
4208 let Predicates = [HasAVX2] in {
4209 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4210 bc_v32i8>, VEX_4V, VEX_L;
4211 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4212 bc_v16i16>, VEX_4V, VEX_L;
4213 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4214 bc_v8i32>, VEX_4V, VEX_L;
4215 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4216 bc_v4i64>, VEX_4V, VEX_L;
4218 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4219 bc_v32i8>, VEX_4V, VEX_L;
4220 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4221 bc_v16i16>, VEX_4V, VEX_L;
4222 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4223 bc_v8i32>, VEX_4V, VEX_L;
4224 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4225 bc_v4i64>, VEX_4V, VEX_L;
4228 let Constraints = "$src1 = $dst" in {
4229 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4231 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4233 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4235 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4238 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4240 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4242 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4244 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4247 } // ExeDomain = SSEPackedInt
4249 //===---------------------------------------------------------------------===//
4250 // SSE2 - Packed Integer Extract and Insert
4251 //===---------------------------------------------------------------------===//
4253 let ExeDomain = SSEPackedInt in {
4254 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4255 def rri : Ii8<0xC4, MRMSrcReg,
4256 (outs VR128:$dst), (ins VR128:$src1,
4257 GR32:$src2, i32i8imm:$src3),
4259 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4260 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4262 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4263 Sched<[WriteShuffle]>;
4264 def rmi : Ii8<0xC4, MRMSrcMem,
4265 (outs VR128:$dst), (ins VR128:$src1,
4266 i16mem:$src2, i32i8imm:$src3),
4268 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4269 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4271 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4272 imm:$src3))], IIC_SSE_PINSRW>,
4273 Sched<[WriteShuffleLd, ReadAfterLd]>;
4277 let Predicates = [HasAVX] in
4278 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4279 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4280 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4281 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4282 imm:$src2))]>, TB, OpSize, VEX,
4283 Sched<[WriteShuffle]>;
4284 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4285 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4286 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4287 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4288 imm:$src2))], IIC_SSE_PEXTRW>,
4289 Sched<[WriteShuffleLd, ReadAfterLd]>;
4292 let Predicates = [HasAVX] in {
4293 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4294 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4295 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4296 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4297 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4300 let Constraints = "$src1 = $dst" in
4301 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4303 } // ExeDomain = SSEPackedInt
4305 //===---------------------------------------------------------------------===//
4306 // SSE2 - Packed Mask Creation
4307 //===---------------------------------------------------------------------===//
4309 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4311 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4312 "pmovmskb\t{$src, $dst|$dst, $src}",
4313 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4314 IIC_SSE_MOVMSK>, VEX;
4315 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4316 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4318 let Predicates = [HasAVX2] in {
4319 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4320 "pmovmskb\t{$src, $dst|$dst, $src}",
4321 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4322 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4323 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4326 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4327 "pmovmskb\t{$src, $dst|$dst, $src}",
4328 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4331 } // ExeDomain = SSEPackedInt
4333 //===---------------------------------------------------------------------===//
4334 // SSE2 - Conditional Store
4335 //===---------------------------------------------------------------------===//
4337 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4340 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4341 (ins VR128:$src, VR128:$mask),
4342 "maskmovdqu\t{$mask, $src|$src, $mask}",
4343 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4344 IIC_SSE_MASKMOV>, VEX;
4346 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4347 (ins VR128:$src, VR128:$mask),
4348 "maskmovdqu\t{$mask, $src|$src, $mask}",
4349 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4350 IIC_SSE_MASKMOV>, VEX;
4353 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4354 "maskmovdqu\t{$mask, $src|$src, $mask}",
4355 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4358 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4359 "maskmovdqu\t{$mask, $src|$src, $mask}",
4360 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4363 } // ExeDomain = SSEPackedInt
4365 //===---------------------------------------------------------------------===//
4366 // SSE2 - Move Doubleword
4367 //===---------------------------------------------------------------------===//
4369 //===---------------------------------------------------------------------===//
4370 // Move Int Doubleword to Packed Double Int
4372 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4373 "movd\t{$src, $dst|$dst, $src}",
4375 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4376 VEX, Sched<[WriteMove]>;
4377 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4378 "movd\t{$src, $dst|$dst, $src}",
4380 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4382 VEX, Sched<[WriteLoad]>;
4383 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4384 "mov{d|q}\t{$src, $dst|$dst, $src}",
4386 (v2i64 (scalar_to_vector GR64:$src)))],
4387 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4388 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4389 "mov{d|q}\t{$src, $dst|$dst, $src}",
4390 [(set FR64:$dst, (bitconvert GR64:$src))],
4391 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4393 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4394 "movd\t{$src, $dst|$dst, $src}",
4396 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4398 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4399 "movd\t{$src, $dst|$dst, $src}",
4401 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4402 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4403 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4404 "mov{d|q}\t{$src, $dst|$dst, $src}",
4406 (v2i64 (scalar_to_vector GR64:$src)))],
4407 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4408 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4409 "mov{d|q}\t{$src, $dst|$dst, $src}",
4410 [(set FR64:$dst, (bitconvert GR64:$src))],
4411 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4413 //===---------------------------------------------------------------------===//
4414 // Move Int Doubleword to Single Scalar
4416 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4417 "movd\t{$src, $dst|$dst, $src}",
4418 [(set FR32:$dst, (bitconvert GR32:$src))],
4419 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4421 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4422 "movd\t{$src, $dst|$dst, $src}",
4423 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4425 VEX, Sched<[WriteLoad]>;
4426 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4427 "movd\t{$src, $dst|$dst, $src}",
4428 [(set FR32:$dst, (bitconvert GR32:$src))],
4429 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4431 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4432 "movd\t{$src, $dst|$dst, $src}",
4433 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4434 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4436 //===---------------------------------------------------------------------===//
4437 // Move Packed Doubleword Int to Packed Double Int
4439 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4440 "movd\t{$src, $dst|$dst, $src}",
4441 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4442 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4444 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4445 (ins i32mem:$dst, VR128:$src),
4446 "movd\t{$src, $dst|$dst, $src}",
4447 [(store (i32 (vector_extract (v4i32 VR128:$src),
4448 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4449 VEX, Sched<[WriteLoad]>;
4450 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4451 "movd\t{$src, $dst|$dst, $src}",
4452 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4453 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4455 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4456 "movd\t{$src, $dst|$dst, $src}",
4457 [(store (i32 (vector_extract (v4i32 VR128:$src),
4458 (iPTR 0))), addr:$dst)],
4459 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4461 //===---------------------------------------------------------------------===//
4462 // Move Packed Doubleword Int first element to Doubleword Int
4464 let SchedRW = [WriteMove] in {
4465 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4466 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4467 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4470 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4472 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4473 "mov{d|q}\t{$src, $dst|$dst, $src}",
4474 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4479 //===---------------------------------------------------------------------===//
4480 // Bitcast FR64 <-> GR64
4482 let Predicates = [HasAVX] in
4483 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4484 "vmovq\t{$src, $dst|$dst, $src}",
4485 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4486 VEX, Sched<[WriteLoad]>;
4487 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4488 "mov{d|q}\t{$src, $dst|$dst, $src}",
4489 [(set GR64:$dst, (bitconvert FR64:$src))],
4490 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4491 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4492 "movq\t{$src, $dst|$dst, $src}",
4493 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4494 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4496 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4497 "movq\t{$src, $dst|$dst, $src}",
4498 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4499 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4500 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4501 "mov{d|q}\t{$src, $dst|$dst, $src}",
4502 [(set GR64:$dst, (bitconvert FR64:$src))],
4503 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4504 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4505 "movq\t{$src, $dst|$dst, $src}",
4506 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4507 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4509 //===---------------------------------------------------------------------===//
4510 // Move Scalar Single to Double Int
4512 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4513 "movd\t{$src, $dst|$dst, $src}",
4514 [(set GR32:$dst, (bitconvert FR32:$src))],
4515 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4516 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4517 "movd\t{$src, $dst|$dst, $src}",
4518 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4519 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4520 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4522 [(set GR32:$dst, (bitconvert FR32:$src))],
4523 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4524 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4525 "movd\t{$src, $dst|$dst, $src}",
4526 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4527 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4529 //===---------------------------------------------------------------------===//
4530 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4532 let SchedRW = [WriteMove] in {
4533 let AddedComplexity = 15 in {
4534 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4535 "movd\t{$src, $dst|$dst, $src}",
4536 [(set VR128:$dst, (v4i32 (X86vzmovl
4537 (v4i32 (scalar_to_vector GR32:$src)))))],
4538 IIC_SSE_MOVDQ>, VEX;
4539 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4540 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4541 [(set VR128:$dst, (v2i64 (X86vzmovl
4542 (v2i64 (scalar_to_vector GR64:$src)))))],
4546 let AddedComplexity = 15 in {
4547 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4548 "movd\t{$src, $dst|$dst, $src}",
4549 [(set VR128:$dst, (v4i32 (X86vzmovl
4550 (v4i32 (scalar_to_vector GR32:$src)))))],
4552 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4553 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4554 [(set VR128:$dst, (v2i64 (X86vzmovl
4555 (v2i64 (scalar_to_vector GR64:$src)))))],
4560 let AddedComplexity = 20, SchedRW = [WriteLoad] in {
4561 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4562 "movd\t{$src, $dst|$dst, $src}",
4564 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4565 (loadi32 addr:$src))))))],
4566 IIC_SSE_MOVDQ>, VEX;
4567 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4570 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4571 (loadi32 addr:$src))))))],
4573 } // AddedComplexity, SchedRW
4575 let Predicates = [HasAVX] in {
4576 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4577 let AddedComplexity = 20 in {
4578 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4579 (VMOVZDI2PDIrm addr:$src)>;
4580 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4581 (VMOVZDI2PDIrm addr:$src)>;
4583 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4584 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4585 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4586 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4587 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4588 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4589 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4592 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4593 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4594 (MOVZDI2PDIrm addr:$src)>;
4595 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4596 (MOVZDI2PDIrm addr:$src)>;
4599 // These are the correct encodings of the instructions so that we know how to
4600 // read correct assembly, even though we continue to emit the wrong ones for
4601 // compatibility with Darwin's buggy assembler.
4602 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4603 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4604 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4605 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4606 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4607 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4608 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4609 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4610 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4611 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4612 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4613 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4615 //===---------------------------------------------------------------------===//
4616 // SSE2 - Move Quadword
4617 //===---------------------------------------------------------------------===//
4619 //===---------------------------------------------------------------------===//
4620 // Move Quadword Int to Packed Quadword Int
4623 let SchedRW = [WriteLoad] in {
4624 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4625 "vmovq\t{$src, $dst|$dst, $src}",
4627 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4628 VEX, Requires<[HasAVX]>;
4629 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4630 "movq\t{$src, $dst|$dst, $src}",
4632 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4634 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4637 //===---------------------------------------------------------------------===//
4638 // Move Packed Quadword Int to Quadword Int
4640 let SchedRW = [WriteStore] in {
4641 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4642 "movq\t{$src, $dst|$dst, $src}",
4643 [(store (i64 (vector_extract (v2i64 VR128:$src),
4644 (iPTR 0))), addr:$dst)],
4645 IIC_SSE_MOVDQ>, VEX;
4646 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4647 "movq\t{$src, $dst|$dst, $src}",
4648 [(store (i64 (vector_extract (v2i64 VR128:$src),
4649 (iPTR 0))), addr:$dst)],
4653 //===---------------------------------------------------------------------===//
4654 // Store / copy lower 64-bits of a XMM register.
4656 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4657 "movq\t{$src, $dst|$dst, $src}",
4658 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4659 Sched<[WriteStore]>;
4660 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4661 "movq\t{$src, $dst|$dst, $src}",
4662 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4663 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4665 let AddedComplexity = 20 in
4666 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4667 "vmovq\t{$src, $dst|$dst, $src}",
4669 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4670 (loadi64 addr:$src))))))],
4672 XS, VEX, Requires<[HasAVX]>, Sched<[WriteLoad]>;
4674 let AddedComplexity = 20 in
4675 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4676 "movq\t{$src, $dst|$dst, $src}",
4678 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4679 (loadi64 addr:$src))))))],
4681 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4683 let Predicates = [HasAVX], AddedComplexity = 20 in {
4684 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4685 (VMOVZQI2PQIrm addr:$src)>;
4686 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4687 (VMOVZQI2PQIrm addr:$src)>;
4688 def : Pat<(v2i64 (X86vzload addr:$src)),
4689 (VMOVZQI2PQIrm addr:$src)>;
4692 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4693 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4694 (MOVZQI2PQIrm addr:$src)>;
4695 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4696 (MOVZQI2PQIrm addr:$src)>;
4697 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4700 let Predicates = [HasAVX] in {
4701 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4702 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4703 def : Pat<(v4i64 (X86vzload addr:$src)),
4704 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4707 //===---------------------------------------------------------------------===//
4708 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4709 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4711 let SchedRW = [WriteVecLogic] in {
4712 let AddedComplexity = 15 in
4713 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4714 "vmovq\t{$src, $dst|$dst, $src}",
4715 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4717 XS, VEX, Requires<[HasAVX]>;
4718 let AddedComplexity = 15 in
4719 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4720 "movq\t{$src, $dst|$dst, $src}",
4721 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4723 XS, Requires<[UseSSE2]>;
4726 let SchedRW = [WriteVecLogicLd] in {
4727 let AddedComplexity = 20 in
4728 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4729 "vmovq\t{$src, $dst|$dst, $src}",
4730 [(set VR128:$dst, (v2i64 (X86vzmovl
4731 (loadv2i64 addr:$src))))],
4733 XS, VEX, Requires<[HasAVX]>;
4734 let AddedComplexity = 20 in {
4735 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4736 "movq\t{$src, $dst|$dst, $src}",
4737 [(set VR128:$dst, (v2i64 (X86vzmovl
4738 (loadv2i64 addr:$src))))],
4740 XS, Requires<[UseSSE2]>;
4744 let AddedComplexity = 20 in {
4745 let Predicates = [HasAVX] in {
4746 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4747 (VMOVZPQILo2PQIrm addr:$src)>;
4748 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4749 (VMOVZPQILo2PQIrr VR128:$src)>;
4751 let Predicates = [UseSSE2] in {
4752 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4753 (MOVZPQILo2PQIrm addr:$src)>;
4754 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4755 (MOVZPQILo2PQIrr VR128:$src)>;
4759 // Instructions to match in the assembler
4760 let SchedRW = [WriteMove] in {
4761 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4762 "movq\t{$src, $dst|$dst, $src}", [],
4763 IIC_SSE_MOVDQ>, VEX, VEX_W;
4764 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4765 "movq\t{$src, $dst|$dst, $src}", [],
4766 IIC_SSE_MOVDQ>, VEX, VEX_W;
4767 // Recognize "movd" with GR64 destination, but encode as a "movq"
4768 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4769 "movd\t{$src, $dst|$dst, $src}", [],
4770 IIC_SSE_MOVDQ>, VEX, VEX_W;
4773 // Instructions for the disassembler
4774 // xr = XMM register
4777 let SchedRW = [WriteMove] in {
4778 let Predicates = [HasAVX] in
4779 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4780 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4781 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4782 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4785 //===---------------------------------------------------------------------===//
4786 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4787 //===---------------------------------------------------------------------===//
4788 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4789 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4790 X86MemOperand x86memop> {
4791 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4792 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4793 [(set RC:$dst, (vt (OpNode RC:$src)))],
4794 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4795 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4797 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4798 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4801 let Predicates = [HasAVX] in {
4802 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4803 v4f32, VR128, memopv4f32, f128mem>, VEX;
4804 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4805 v4f32, VR128, memopv4f32, f128mem>, VEX;
4806 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4807 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4808 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4809 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4811 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4812 memopv4f32, f128mem>;
4813 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4814 memopv4f32, f128mem>;
4816 let Predicates = [HasAVX] in {
4817 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4818 (VMOVSHDUPrr VR128:$src)>;
4819 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4820 (VMOVSHDUPrm addr:$src)>;
4821 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4822 (VMOVSLDUPrr VR128:$src)>;
4823 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4824 (VMOVSLDUPrm addr:$src)>;
4825 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4826 (VMOVSHDUPYrr VR256:$src)>;
4827 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4828 (VMOVSHDUPYrm addr:$src)>;
4829 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4830 (VMOVSLDUPYrr VR256:$src)>;
4831 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4832 (VMOVSLDUPYrm addr:$src)>;
4835 let Predicates = [UseSSE3] in {
4836 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4837 (MOVSHDUPrr VR128:$src)>;
4838 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4839 (MOVSHDUPrm addr:$src)>;
4840 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4841 (MOVSLDUPrr VR128:$src)>;
4842 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4843 (MOVSLDUPrm addr:$src)>;
4846 //===---------------------------------------------------------------------===//
4847 // SSE3 - Replicate Double FP - MOVDDUP
4848 //===---------------------------------------------------------------------===//
4850 multiclass sse3_replicate_dfp<string OpcodeStr> {
4851 let neverHasSideEffects = 1 in
4852 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4854 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4855 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4856 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4859 (scalar_to_vector (loadf64 addr:$src)))))],
4860 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4863 // FIXME: Merge with above classe when there're patterns for the ymm version
4864 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4865 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4867 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4868 Sched<[WriteShuffle]>;
4869 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4873 (scalar_to_vector (loadf64 addr:$src)))))]>,
4874 Sched<[WriteShuffleLd]>;
4877 let Predicates = [HasAVX] in {
4878 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4879 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4882 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4884 let Predicates = [HasAVX] in {
4885 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4886 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4887 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4888 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4889 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4890 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4891 def : Pat<(X86Movddup (bc_v2f64
4892 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4893 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4896 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4897 (VMOVDDUPYrm addr:$src)>;
4898 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4899 (VMOVDDUPYrm addr:$src)>;
4900 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4901 (VMOVDDUPYrm addr:$src)>;
4902 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4903 (VMOVDDUPYrr VR256:$src)>;
4906 let Predicates = [UseSSE3] in {
4907 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4908 (MOVDDUPrm addr:$src)>;
4909 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4910 (MOVDDUPrm addr:$src)>;
4911 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4912 (MOVDDUPrm addr:$src)>;
4913 def : Pat<(X86Movddup (bc_v2f64
4914 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4915 (MOVDDUPrm addr:$src)>;
4918 //===---------------------------------------------------------------------===//
4919 // SSE3 - Move Unaligned Integer
4920 //===---------------------------------------------------------------------===//
4922 let SchedRW = [WriteLoad] in {
4923 let Predicates = [HasAVX] in {
4924 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4925 "vlddqu\t{$src, $dst|$dst, $src}",
4926 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4927 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4928 "vlddqu\t{$src, $dst|$dst, $src}",
4929 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4932 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4933 "lddqu\t{$src, $dst|$dst, $src}",
4934 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4938 //===---------------------------------------------------------------------===//
4939 // SSE3 - Arithmetic
4940 //===---------------------------------------------------------------------===//
4942 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4943 X86MemOperand x86memop, OpndItins itins,
4945 def rr : I<0xD0, MRMSrcReg,
4946 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4948 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4950 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4951 Sched<[itins.Sched]>;
4952 def rm : I<0xD0, MRMSrcMem,
4953 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4955 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4957 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4958 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4961 let Predicates = [HasAVX] in {
4962 let ExeDomain = SSEPackedSingle in {
4963 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4964 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4965 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4966 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4968 let ExeDomain = SSEPackedDouble in {
4969 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4970 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4971 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4972 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4975 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4976 let ExeDomain = SSEPackedSingle in
4977 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4978 f128mem, SSE_ALU_F32P>, TB, XD;
4979 let ExeDomain = SSEPackedDouble in
4980 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4981 f128mem, SSE_ALU_F64P>, TB, OpSize;
4984 //===---------------------------------------------------------------------===//
4985 // SSE3 Instructions
4986 //===---------------------------------------------------------------------===//
4989 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4990 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4991 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4993 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4994 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4995 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4998 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5000 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5002 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5003 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5005 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5006 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5007 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5009 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5011 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5014 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5016 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5017 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5018 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5019 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5022 let Predicates = [HasAVX] in {
5023 let ExeDomain = SSEPackedSingle in {
5024 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5025 X86fhadd, 0>, VEX_4V;
5026 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5027 X86fhsub, 0>, VEX_4V;
5028 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5029 X86fhadd, 0>, VEX_4V, VEX_L;
5030 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5031 X86fhsub, 0>, VEX_4V, VEX_L;
5033 let ExeDomain = SSEPackedDouble in {
5034 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5035 X86fhadd, 0>, VEX_4V;
5036 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5037 X86fhsub, 0>, VEX_4V;
5038 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5039 X86fhadd, 0>, VEX_4V, VEX_L;
5040 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5041 X86fhsub, 0>, VEX_4V, VEX_L;
5045 let Constraints = "$src1 = $dst" in {
5046 let ExeDomain = SSEPackedSingle in {
5047 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5048 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5050 let ExeDomain = SSEPackedDouble in {
5051 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5052 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5056 //===---------------------------------------------------------------------===//
5057 // SSSE3 - Packed Absolute Instructions
5058 //===---------------------------------------------------------------------===//
5061 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5062 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5063 Intrinsic IntId128> {
5064 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5066 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5067 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5068 OpSize, Sched<[WriteVecALU]>;
5070 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5072 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5075 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5076 OpSize, Sched<[WriteVecALULd]>;
5079 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5080 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5081 Intrinsic IntId256> {
5082 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5084 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5085 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5086 OpSize, Sched<[WriteVecALU]>;
5088 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5090 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5093 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5094 Sched<[WriteVecALULd]>;
5097 let Predicates = [HasAVX] in {
5098 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5099 int_x86_ssse3_pabs_b_128>, VEX;
5100 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5101 int_x86_ssse3_pabs_w_128>, VEX;
5102 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5103 int_x86_ssse3_pabs_d_128>, VEX;
5106 let Predicates = [HasAVX2] in {
5107 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5108 int_x86_avx2_pabs_b>, VEX, VEX_L;
5109 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5110 int_x86_avx2_pabs_w>, VEX, VEX_L;
5111 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5112 int_x86_avx2_pabs_d>, VEX, VEX_L;
5115 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5116 int_x86_ssse3_pabs_b_128>;
5117 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5118 int_x86_ssse3_pabs_w_128>;
5119 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5120 int_x86_ssse3_pabs_d_128>;
5122 //===---------------------------------------------------------------------===//
5123 // SSSE3 - Packed Binary Operator Instructions
5124 //===---------------------------------------------------------------------===//
5126 let Sched = WriteVecALU in {
5127 def SSE_PHADDSUBD : OpndItins<
5128 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5130 def SSE_PHADDSUBSW : OpndItins<
5131 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5133 def SSE_PHADDSUBW : OpndItins<
5134 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5137 let Sched = WriteShuffle in
5138 def SSE_PSHUFB : OpndItins<
5139 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5141 let Sched = WriteVecALU in
5142 def SSE_PSIGN : OpndItins<
5143 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5145 let Sched = WriteVecIMul in
5146 def SSE_PMULHRSW : OpndItins<
5147 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5150 /// SS3I_binop_rm - Simple SSSE3 bin op
5151 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5152 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5153 X86MemOperand x86memop, OpndItins itins,
5155 let isCommutable = 1 in
5156 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5157 (ins RC:$src1, RC:$src2),
5159 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5160 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5161 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5162 OpSize, Sched<[itins.Sched]>;
5163 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5164 (ins RC:$src1, x86memop:$src2),
5166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5169 (OpVT (OpNode RC:$src1,
5170 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5171 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5174 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5175 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5176 Intrinsic IntId128, OpndItins itins,
5178 let isCommutable = 1 in
5179 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5180 (ins VR128:$src1, VR128:$src2),
5182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5184 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5185 OpSize, Sched<[itins.Sched]>;
5186 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5187 (ins VR128:$src1, i128mem:$src2),
5189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5192 (IntId128 VR128:$src1,
5193 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5194 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5197 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5198 Intrinsic IntId256> {
5199 let isCommutable = 1 in
5200 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5201 (ins VR256:$src1, VR256:$src2),
5202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5203 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5205 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5206 (ins VR256:$src1, i256mem:$src2),
5207 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5209 (IntId256 VR256:$src1,
5210 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5213 let ImmT = NoImm, Predicates = [HasAVX] in {
5214 let isCommutable = 0 in {
5215 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5216 memopv2i64, i128mem,
5217 SSE_PHADDSUBW, 0>, VEX_4V;
5218 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5219 memopv2i64, i128mem,
5220 SSE_PHADDSUBD, 0>, VEX_4V;
5221 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5222 memopv2i64, i128mem,
5223 SSE_PHADDSUBW, 0>, VEX_4V;
5224 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5225 memopv2i64, i128mem,
5226 SSE_PHADDSUBD, 0>, VEX_4V;
5227 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5228 memopv2i64, i128mem,
5229 SSE_PSIGN, 0>, VEX_4V;
5230 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5231 memopv2i64, i128mem,
5232 SSE_PSIGN, 0>, VEX_4V;
5233 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5234 memopv2i64, i128mem,
5235 SSE_PSIGN, 0>, VEX_4V;
5236 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5237 memopv2i64, i128mem,
5238 SSE_PSHUFB, 0>, VEX_4V;
5239 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5240 int_x86_ssse3_phadd_sw_128,
5241 SSE_PHADDSUBSW, 0>, VEX_4V;
5242 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5243 int_x86_ssse3_phsub_sw_128,
5244 SSE_PHADDSUBSW, 0>, VEX_4V;
5245 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5246 int_x86_ssse3_pmadd_ub_sw_128,
5247 SSE_PMADD, 0>, VEX_4V;
5249 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5250 int_x86_ssse3_pmul_hr_sw_128,
5251 SSE_PMULHRSW, 0>, VEX_4V;
5254 let ImmT = NoImm, Predicates = [HasAVX2] in {
5255 let isCommutable = 0 in {
5256 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5257 memopv4i64, i256mem,
5258 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5259 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5260 memopv4i64, i256mem,
5261 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5262 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5263 memopv4i64, i256mem,
5264 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5265 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5266 memopv4i64, i256mem,
5267 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5268 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5269 memopv4i64, i256mem,
5270 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5271 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5272 memopv4i64, i256mem,
5273 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5274 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5275 memopv4i64, i256mem,
5276 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5277 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5278 memopv4i64, i256mem,
5279 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5280 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5281 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5282 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5283 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5284 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5285 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5287 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5288 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5291 // None of these have i8 immediate fields.
5292 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5293 let isCommutable = 0 in {
5294 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5295 memopv2i64, i128mem, SSE_PHADDSUBW>;
5296 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5297 memopv2i64, i128mem, SSE_PHADDSUBD>;
5298 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5299 memopv2i64, i128mem, SSE_PHADDSUBW>;
5300 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5301 memopv2i64, i128mem, SSE_PHADDSUBD>;
5302 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5303 memopv2i64, i128mem, SSE_PSIGN>;
5304 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5305 memopv2i64, i128mem, SSE_PSIGN>;
5306 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5307 memopv2i64, i128mem, SSE_PSIGN>;
5308 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5309 memopv2i64, i128mem, SSE_PSHUFB>;
5310 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5311 int_x86_ssse3_phadd_sw_128,
5313 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5314 int_x86_ssse3_phsub_sw_128,
5316 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5317 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5319 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5320 int_x86_ssse3_pmul_hr_sw_128,
5324 //===---------------------------------------------------------------------===//
5325 // SSSE3 - Packed Align Instruction Patterns
5326 //===---------------------------------------------------------------------===//
5328 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5329 let neverHasSideEffects = 1 in {
5330 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5331 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5333 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5335 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5336 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffle]>;
5338 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5339 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5341 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5344 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5348 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5349 let neverHasSideEffects = 1 in {
5350 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5351 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5353 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5354 []>, OpSize, Sched<[WriteShuffle]>;
5356 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5357 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5359 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5360 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5364 let Predicates = [HasAVX] in
5365 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5366 let Predicates = [HasAVX2] in
5367 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5368 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5369 defm PALIGN : ssse3_palignr<"palignr">;
5371 let Predicates = [HasAVX2] in {
5372 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5373 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5374 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5375 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5376 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5377 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5378 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5379 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5382 let Predicates = [HasAVX] in {
5383 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5384 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5385 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5386 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5387 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5388 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5389 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5390 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5393 let Predicates = [UseSSSE3] in {
5394 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5395 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5396 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5397 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5398 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5399 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5400 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5401 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5404 //===---------------------------------------------------------------------===//
5405 // SSSE3 - Thread synchronization
5406 //===---------------------------------------------------------------------===//
5408 let SchedRW = [WriteSystem] in {
5409 let usesCustomInserter = 1 in {
5410 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5411 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5412 Requires<[HasSSE3]>;
5415 let Uses = [EAX, ECX, EDX] in
5416 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5417 TB, Requires<[HasSSE3]>;
5418 let Uses = [ECX, EAX] in
5419 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5420 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5421 TB, Requires<[HasSSE3]>;
5424 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5425 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5427 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5428 Requires<[In32BitMode]>;
5429 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5430 Requires<[In64BitMode]>;
5432 //===----------------------------------------------------------------------===//
5433 // SSE4.1 - Packed Move with Sign/Zero Extend
5434 //===----------------------------------------------------------------------===//
5436 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5437 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5439 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5441 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5442 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5444 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5448 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5450 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5451 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5452 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5454 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5455 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5456 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5459 let Predicates = [HasAVX] in {
5460 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5462 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5464 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5466 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5468 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5470 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5474 let Predicates = [HasAVX2] in {
5475 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5476 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5477 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5478 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5479 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5480 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5481 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5482 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5483 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5484 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5485 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5486 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5489 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5490 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5491 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5492 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5493 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5494 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5496 let Predicates = [HasAVX] in {
5497 // Common patterns involving scalar load.
5498 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5499 (VPMOVSXBWrm addr:$src)>;
5500 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5501 (VPMOVSXBWrm addr:$src)>;
5502 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5503 (VPMOVSXBWrm addr:$src)>;
5505 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5506 (VPMOVSXWDrm addr:$src)>;
5507 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5508 (VPMOVSXWDrm addr:$src)>;
5509 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5510 (VPMOVSXWDrm addr:$src)>;
5512 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5513 (VPMOVSXDQrm addr:$src)>;
5514 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5515 (VPMOVSXDQrm addr:$src)>;
5516 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5517 (VPMOVSXDQrm addr:$src)>;
5519 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5520 (VPMOVZXBWrm addr:$src)>;
5521 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5522 (VPMOVZXBWrm addr:$src)>;
5523 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5524 (VPMOVZXBWrm addr:$src)>;
5526 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5527 (VPMOVZXWDrm addr:$src)>;
5528 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5529 (VPMOVZXWDrm addr:$src)>;
5530 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5531 (VPMOVZXWDrm addr:$src)>;
5533 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5534 (VPMOVZXDQrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5536 (VPMOVZXDQrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5538 (VPMOVZXDQrm addr:$src)>;
5541 let Predicates = [UseSSE41] in {
5542 // Common patterns involving scalar load.
5543 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5544 (PMOVSXBWrm addr:$src)>;
5545 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5546 (PMOVSXBWrm addr:$src)>;
5547 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5548 (PMOVSXBWrm addr:$src)>;
5550 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5551 (PMOVSXWDrm addr:$src)>;
5552 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5553 (PMOVSXWDrm addr:$src)>;
5554 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5555 (PMOVSXWDrm addr:$src)>;
5557 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5558 (PMOVSXDQrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5560 (PMOVSXDQrm addr:$src)>;
5561 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5562 (PMOVSXDQrm addr:$src)>;
5564 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5565 (PMOVZXBWrm addr:$src)>;
5566 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5567 (PMOVZXBWrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5569 (PMOVZXBWrm addr:$src)>;
5571 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5572 (PMOVZXWDrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5574 (PMOVZXWDrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5576 (PMOVZXWDrm addr:$src)>;
5578 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5579 (PMOVZXDQrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5581 (PMOVZXDQrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5583 (PMOVZXDQrm addr:$src)>;
5586 let Predicates = [HasAVX2] in {
5587 let AddedComplexity = 15 in {
5588 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5589 (VPMOVZXDQYrr VR128:$src)>;
5590 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5591 (VPMOVZXWDYrr VR128:$src)>;
5594 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5595 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5598 let Predicates = [HasAVX] in {
5599 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5600 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5603 let Predicates = [UseSSE41] in {
5604 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5605 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5609 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5610 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5612 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5614 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5617 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5621 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5623 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5625 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5627 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5630 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5634 let Predicates = [HasAVX] in {
5635 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5637 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5639 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5641 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5645 let Predicates = [HasAVX2] in {
5646 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5647 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5648 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5649 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5650 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5651 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5652 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5653 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5656 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5657 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5658 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5659 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5661 let Predicates = [HasAVX] in {
5662 // Common patterns involving scalar load
5663 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5664 (VPMOVSXBDrm addr:$src)>;
5665 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5666 (VPMOVSXWQrm addr:$src)>;
5668 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5669 (VPMOVZXBDrm addr:$src)>;
5670 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5671 (VPMOVZXWQrm addr:$src)>;
5674 let Predicates = [UseSSE41] in {
5675 // Common patterns involving scalar load
5676 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5677 (PMOVSXBDrm addr:$src)>;
5678 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5679 (PMOVSXWQrm addr:$src)>;
5681 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5682 (PMOVZXBDrm addr:$src)>;
5683 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5684 (PMOVZXWQrm addr:$src)>;
5687 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5688 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5689 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5690 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5692 // Expecting a i16 load any extended to i32 value.
5693 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5695 [(set VR128:$dst, (IntId (bitconvert
5696 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5700 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5702 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5703 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5704 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5706 // Expecting a i16 load any extended to i32 value.
5707 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5709 [(set VR256:$dst, (IntId (bitconvert
5710 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5714 let Predicates = [HasAVX] in {
5715 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5717 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5720 let Predicates = [HasAVX2] in {
5721 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5722 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5723 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5724 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5726 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5727 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5729 let Predicates = [HasAVX2] in {
5730 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5731 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5732 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5734 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5735 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5737 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5739 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5740 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5741 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5742 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5743 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5744 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5746 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5747 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5748 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5749 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5751 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5752 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5754 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5755 (VPMOVSXWDYrm addr:$src)>;
5756 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5757 (VPMOVSXDQYrm addr:$src)>;
5759 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5760 (scalar_to_vector (loadi64 addr:$src))))))),
5761 (VPMOVSXBDYrm addr:$src)>;
5762 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5763 (scalar_to_vector (loadf64 addr:$src))))))),
5764 (VPMOVSXBDYrm addr:$src)>;
5766 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5767 (scalar_to_vector (loadi64 addr:$src))))))),
5768 (VPMOVSXWQYrm addr:$src)>;
5769 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5770 (scalar_to_vector (loadf64 addr:$src))))))),
5771 (VPMOVSXWQYrm addr:$src)>;
5773 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5774 (scalar_to_vector (loadi32 addr:$src))))))),
5775 (VPMOVSXBQYrm addr:$src)>;
5778 let Predicates = [HasAVX] in {
5779 // Common patterns involving scalar load
5780 def : Pat<(int_x86_sse41_pmovsxbq
5781 (bitconvert (v4i32 (X86vzmovl
5782 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5783 (VPMOVSXBQrm addr:$src)>;
5785 def : Pat<(int_x86_sse41_pmovzxbq
5786 (bitconvert (v4i32 (X86vzmovl
5787 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5788 (VPMOVZXBQrm addr:$src)>;
5791 let Predicates = [UseSSE41] in {
5792 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5793 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5794 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5796 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5797 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5799 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5801 // Common patterns involving scalar load
5802 def : Pat<(int_x86_sse41_pmovsxbq
5803 (bitconvert (v4i32 (X86vzmovl
5804 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5805 (PMOVSXBQrm addr:$src)>;
5807 def : Pat<(int_x86_sse41_pmovzxbq
5808 (bitconvert (v4i32 (X86vzmovl
5809 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5810 (PMOVZXBQrm addr:$src)>;
5812 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5813 (scalar_to_vector (loadi64 addr:$src))))))),
5814 (PMOVSXWDrm addr:$src)>;
5815 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5816 (scalar_to_vector (loadf64 addr:$src))))))),
5817 (PMOVSXWDrm addr:$src)>;
5818 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5819 (scalar_to_vector (loadi32 addr:$src))))))),
5820 (PMOVSXBDrm addr:$src)>;
5821 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5822 (scalar_to_vector (loadi32 addr:$src))))))),
5823 (PMOVSXWQrm addr:$src)>;
5824 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5825 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5826 (PMOVSXBQrm addr:$src)>;
5827 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5828 (scalar_to_vector (loadi64 addr:$src))))))),
5829 (PMOVSXDQrm addr:$src)>;
5830 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5831 (scalar_to_vector (loadf64 addr:$src))))))),
5832 (PMOVSXDQrm addr:$src)>;
5833 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5834 (scalar_to_vector (loadi64 addr:$src))))))),
5835 (PMOVSXBWrm addr:$src)>;
5836 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5837 (scalar_to_vector (loadf64 addr:$src))))))),
5838 (PMOVSXBWrm addr:$src)>;
5841 let Predicates = [HasAVX2] in {
5842 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5843 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5844 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5846 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5847 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5849 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5851 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5852 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5853 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5854 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5855 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5856 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5858 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5859 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5860 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5861 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5863 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5864 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5867 let Predicates = [HasAVX] in {
5868 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5869 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5870 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5872 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5873 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5875 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5877 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5878 (VPMOVZXBWrm addr:$src)>;
5879 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5880 (VPMOVZXBWrm addr:$src)>;
5881 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5882 (VPMOVZXBDrm addr:$src)>;
5883 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5884 (VPMOVZXBQrm addr:$src)>;
5886 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5887 (VPMOVZXWDrm addr:$src)>;
5888 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5889 (VPMOVZXWDrm addr:$src)>;
5890 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5891 (VPMOVZXWQrm addr:$src)>;
5893 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5894 (VPMOVZXDQrm addr:$src)>;
5895 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5896 (VPMOVZXDQrm addr:$src)>;
5897 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5898 (VPMOVZXDQrm addr:$src)>;
5900 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5901 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5902 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5904 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5905 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5907 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5909 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5910 (scalar_to_vector (loadi64 addr:$src))))))),
5911 (VPMOVSXWDrm addr:$src)>;
5912 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5913 (scalar_to_vector (loadi64 addr:$src))))))),
5914 (VPMOVSXDQrm addr:$src)>;
5915 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5916 (scalar_to_vector (loadf64 addr:$src))))))),
5917 (VPMOVSXWDrm addr:$src)>;
5918 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5919 (scalar_to_vector (loadf64 addr:$src))))))),
5920 (VPMOVSXDQrm addr:$src)>;
5921 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5922 (scalar_to_vector (loadi64 addr:$src))))))),
5923 (VPMOVSXBWrm addr:$src)>;
5924 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5925 (scalar_to_vector (loadf64 addr:$src))))))),
5926 (VPMOVSXBWrm addr:$src)>;
5928 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5929 (scalar_to_vector (loadi32 addr:$src))))))),
5930 (VPMOVSXBDrm addr:$src)>;
5931 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5932 (scalar_to_vector (loadi32 addr:$src))))))),
5933 (VPMOVSXWQrm addr:$src)>;
5934 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5935 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5936 (VPMOVSXBQrm addr:$src)>;
5939 let Predicates = [UseSSE41] in {
5940 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5941 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5942 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5944 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5945 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5947 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5949 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5950 (PMOVZXBWrm addr:$src)>;
5951 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5952 (PMOVZXBWrm addr:$src)>;
5953 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5954 (PMOVZXBDrm addr:$src)>;
5955 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5956 (PMOVZXBQrm addr:$src)>;
5958 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5959 (PMOVZXWDrm addr:$src)>;
5960 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5961 (PMOVZXWDrm addr:$src)>;
5962 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5963 (PMOVZXWQrm addr:$src)>;
5965 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5966 (PMOVZXDQrm addr:$src)>;
5967 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5968 (PMOVZXDQrm addr:$src)>;
5969 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5970 (PMOVZXDQrm addr:$src)>;
5973 //===----------------------------------------------------------------------===//
5974 // SSE4.1 - Extract Instructions
5975 //===----------------------------------------------------------------------===//
5977 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5978 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5979 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5980 (ins VR128:$src1, i32i8imm:$src2),
5981 !strconcat(OpcodeStr,
5982 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5983 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5985 let neverHasSideEffects = 1, mayStore = 1 in
5986 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5987 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5988 !strconcat(OpcodeStr,
5989 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5992 // There's an AssertZext in the way of writing the store pattern
5993 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5996 let Predicates = [HasAVX] in {
5997 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5998 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5999 (ins VR128:$src1, i32i8imm:$src2),
6000 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6003 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6006 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6007 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6008 let neverHasSideEffects = 1, mayStore = 1 in
6009 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6010 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6011 !strconcat(OpcodeStr,
6012 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6015 // There's an AssertZext in the way of writing the store pattern
6016 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6019 let Predicates = [HasAVX] in
6020 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6022 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6025 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6026 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6027 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6028 (ins VR128:$src1, i32i8imm:$src2),
6029 !strconcat(OpcodeStr,
6030 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6032 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6033 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6034 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6035 !strconcat(OpcodeStr,
6036 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6037 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6038 addr:$dst)]>, OpSize;
6041 let Predicates = [HasAVX] in
6042 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6044 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6046 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6047 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6048 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6049 (ins VR128:$src1, i32i8imm:$src2),
6050 !strconcat(OpcodeStr,
6051 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6053 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6054 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6055 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6056 !strconcat(OpcodeStr,
6057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6058 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6059 addr:$dst)]>, OpSize, REX_W;
6062 let Predicates = [HasAVX] in
6063 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6065 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6067 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6069 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
6070 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6071 (ins VR128:$src1, i32i8imm:$src2),
6072 !strconcat(OpcodeStr,
6073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6075 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6077 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6078 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6079 !strconcat(OpcodeStr,
6080 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6081 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6082 addr:$dst)]>, OpSize;
6085 let ExeDomain = SSEPackedSingle in {
6086 let Predicates = [HasAVX] in {
6087 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6088 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6089 (ins VR128:$src1, i32i8imm:$src2),
6090 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6093 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6096 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6097 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6100 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6102 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6105 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6106 Requires<[UseSSE41]>;
6108 //===----------------------------------------------------------------------===//
6109 // SSE4.1 - Insert Instructions
6110 //===----------------------------------------------------------------------===//
6112 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6113 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6114 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6116 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6118 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6120 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6121 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6122 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6124 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6126 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6128 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6129 imm:$src3))]>, OpSize;
6132 let Predicates = [HasAVX] in
6133 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6134 let Constraints = "$src1 = $dst" in
6135 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6137 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6138 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6139 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6141 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6143 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6145 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6147 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6148 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6150 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6152 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6154 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6155 imm:$src3)))]>, OpSize;
6158 let Predicates = [HasAVX] in
6159 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6160 let Constraints = "$src1 = $dst" in
6161 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6163 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6164 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6165 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6167 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6169 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6171 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6173 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6174 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6176 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6178 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6180 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6181 imm:$src3)))]>, OpSize;
6184 let Predicates = [HasAVX] in
6185 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6186 let Constraints = "$src1 = $dst" in
6187 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6189 // insertps has a few different modes, there's the first two here below which
6190 // are optimized inserts that won't zero arbitrary elements in the destination
6191 // vector. The next one matches the intrinsic and could zero arbitrary elements
6192 // in the target vector.
6193 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6194 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6195 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6197 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6199 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6201 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6203 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6204 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6206 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6208 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6210 (X86insrtps VR128:$src1,
6211 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6212 imm:$src3))]>, OpSize;
6215 let ExeDomain = SSEPackedSingle in {
6216 let Predicates = [HasAVX] in
6217 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6218 let Constraints = "$src1 = $dst" in
6219 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6222 //===----------------------------------------------------------------------===//
6223 // SSE4.1 - Round Instructions
6224 //===----------------------------------------------------------------------===//
6226 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6227 X86MemOperand x86memop, RegisterClass RC,
6228 PatFrag mem_frag32, PatFrag mem_frag64,
6229 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6230 let ExeDomain = SSEPackedSingle in {
6231 // Intrinsic operation, reg.
6232 // Vector intrinsic operation, reg
6233 def PSr : SS4AIi8<opcps, MRMSrcReg,
6234 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6235 !strconcat(OpcodeStr,
6236 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6237 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6240 // Vector intrinsic operation, mem
6241 def PSm : SS4AIi8<opcps, MRMSrcMem,
6242 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6243 !strconcat(OpcodeStr,
6244 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6246 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6248 } // ExeDomain = SSEPackedSingle
6250 let ExeDomain = SSEPackedDouble in {
6251 // Vector intrinsic operation, reg
6252 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6253 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6254 !strconcat(OpcodeStr,
6255 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6256 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6259 // Vector intrinsic operation, mem
6260 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6261 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6262 !strconcat(OpcodeStr,
6263 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6265 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6267 } // ExeDomain = SSEPackedDouble
6270 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6273 Intrinsic F64Int, bit Is2Addr = 1> {
6274 let ExeDomain = GenericDomain in {
6276 let hasSideEffects = 0 in
6277 def SSr : SS4AIi8<opcss, MRMSrcReg,
6278 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6280 !strconcat(OpcodeStr,
6281 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6282 !strconcat(OpcodeStr,
6283 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6286 // Intrinsic operation, reg.
6287 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6288 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6290 !strconcat(OpcodeStr,
6291 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6292 !strconcat(OpcodeStr,
6293 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6294 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6297 // Intrinsic operation, mem.
6298 def SSm : SS4AIi8<opcss, MRMSrcMem,
6299 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6301 !strconcat(OpcodeStr,
6302 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6303 !strconcat(OpcodeStr,
6304 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6306 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6310 let hasSideEffects = 0 in
6311 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6312 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6314 !strconcat(OpcodeStr,
6315 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6316 !strconcat(OpcodeStr,
6317 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6320 // Intrinsic operation, reg.
6321 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6322 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6324 !strconcat(OpcodeStr,
6325 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6326 !strconcat(OpcodeStr,
6327 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6328 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6331 // Intrinsic operation, mem.
6332 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6333 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6335 !strconcat(OpcodeStr,
6336 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6337 !strconcat(OpcodeStr,
6338 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6340 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6342 } // ExeDomain = GenericDomain
6345 // FP round - roundss, roundps, roundsd, roundpd
6346 let Predicates = [HasAVX] in {
6348 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6349 memopv4f32, memopv2f64,
6350 int_x86_sse41_round_ps,
6351 int_x86_sse41_round_pd>, VEX;
6352 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6353 memopv8f32, memopv4f64,
6354 int_x86_avx_round_ps_256,
6355 int_x86_avx_round_pd_256>, VEX, VEX_L;
6356 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6357 int_x86_sse41_round_ss,
6358 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6360 def : Pat<(ffloor FR32:$src),
6361 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6362 def : Pat<(f64 (ffloor FR64:$src)),
6363 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6364 def : Pat<(f32 (fnearbyint FR32:$src)),
6365 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6366 def : Pat<(f64 (fnearbyint FR64:$src)),
6367 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6368 def : Pat<(f32 (fceil FR32:$src)),
6369 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6370 def : Pat<(f64 (fceil FR64:$src)),
6371 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6372 def : Pat<(f32 (frint FR32:$src)),
6373 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6374 def : Pat<(f64 (frint FR64:$src)),
6375 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6376 def : Pat<(f32 (ftrunc FR32:$src)),
6377 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6378 def : Pat<(f64 (ftrunc FR64:$src)),
6379 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6381 def : Pat<(v4f32 (ffloor VR128:$src)),
6382 (VROUNDPSr VR128:$src, (i32 0x1))>;
6383 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6384 (VROUNDPSr VR128:$src, (i32 0xC))>;
6385 def : Pat<(v4f32 (fceil VR128:$src)),
6386 (VROUNDPSr VR128:$src, (i32 0x2))>;
6387 def : Pat<(v4f32 (frint VR128:$src)),
6388 (VROUNDPSr VR128:$src, (i32 0x4))>;
6389 def : Pat<(v4f32 (ftrunc VR128:$src)),
6390 (VROUNDPSr VR128:$src, (i32 0x3))>;
6392 def : Pat<(v2f64 (ffloor VR128:$src)),
6393 (VROUNDPDr VR128:$src, (i32 0x1))>;
6394 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6395 (VROUNDPDr VR128:$src, (i32 0xC))>;
6396 def : Pat<(v2f64 (fceil VR128:$src)),
6397 (VROUNDPDr VR128:$src, (i32 0x2))>;
6398 def : Pat<(v2f64 (frint VR128:$src)),
6399 (VROUNDPDr VR128:$src, (i32 0x4))>;
6400 def : Pat<(v2f64 (ftrunc VR128:$src)),
6401 (VROUNDPDr VR128:$src, (i32 0x3))>;
6403 def : Pat<(v8f32 (ffloor VR256:$src)),
6404 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6405 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6406 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6407 def : Pat<(v8f32 (fceil VR256:$src)),
6408 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6409 def : Pat<(v8f32 (frint VR256:$src)),
6410 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6411 def : Pat<(v8f32 (ftrunc VR256:$src)),
6412 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6414 def : Pat<(v4f64 (ffloor VR256:$src)),
6415 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6416 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6417 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6418 def : Pat<(v4f64 (fceil VR256:$src)),
6419 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6420 def : Pat<(v4f64 (frint VR256:$src)),
6421 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6422 def : Pat<(v4f64 (ftrunc VR256:$src)),
6423 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6426 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6427 memopv4f32, memopv2f64,
6428 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6429 let Constraints = "$src1 = $dst" in
6430 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6431 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6433 let Predicates = [UseSSE41] in {
6434 def : Pat<(ffloor FR32:$src),
6435 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6436 def : Pat<(f64 (ffloor FR64:$src)),
6437 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6438 def : Pat<(f32 (fnearbyint FR32:$src)),
6439 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6440 def : Pat<(f64 (fnearbyint FR64:$src)),
6441 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6442 def : Pat<(f32 (fceil FR32:$src)),
6443 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6444 def : Pat<(f64 (fceil FR64:$src)),
6445 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6446 def : Pat<(f32 (frint FR32:$src)),
6447 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6448 def : Pat<(f64 (frint FR64:$src)),
6449 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6450 def : Pat<(f32 (ftrunc FR32:$src)),
6451 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6452 def : Pat<(f64 (ftrunc FR64:$src)),
6453 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6455 def : Pat<(v4f32 (ffloor VR128:$src)),
6456 (ROUNDPSr VR128:$src, (i32 0x1))>;
6457 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6458 (ROUNDPSr VR128:$src, (i32 0xC))>;
6459 def : Pat<(v4f32 (fceil VR128:$src)),
6460 (ROUNDPSr VR128:$src, (i32 0x2))>;
6461 def : Pat<(v4f32 (frint VR128:$src)),
6462 (ROUNDPSr VR128:$src, (i32 0x4))>;
6463 def : Pat<(v4f32 (ftrunc VR128:$src)),
6464 (ROUNDPSr VR128:$src, (i32 0x3))>;
6466 def : Pat<(v2f64 (ffloor VR128:$src)),
6467 (ROUNDPDr VR128:$src, (i32 0x1))>;
6468 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6469 (ROUNDPDr VR128:$src, (i32 0xC))>;
6470 def : Pat<(v2f64 (fceil VR128:$src)),
6471 (ROUNDPDr VR128:$src, (i32 0x2))>;
6472 def : Pat<(v2f64 (frint VR128:$src)),
6473 (ROUNDPDr VR128:$src, (i32 0x4))>;
6474 def : Pat<(v2f64 (ftrunc VR128:$src)),
6475 (ROUNDPDr VR128:$src, (i32 0x3))>;
6478 //===----------------------------------------------------------------------===//
6479 // SSE4.1 - Packed Bit Test
6480 //===----------------------------------------------------------------------===//
6482 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6483 // the intel intrinsic that corresponds to this.
6484 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6485 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6486 "vptest\t{$src2, $src1|$src1, $src2}",
6487 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6489 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6490 "vptest\t{$src2, $src1|$src1, $src2}",
6491 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6494 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6495 "vptest\t{$src2, $src1|$src1, $src2}",
6496 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6498 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6499 "vptest\t{$src2, $src1|$src1, $src2}",
6500 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6504 let Defs = [EFLAGS] in {
6505 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6506 "ptest\t{$src2, $src1|$src1, $src2}",
6507 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6509 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6510 "ptest\t{$src2, $src1|$src1, $src2}",
6511 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6515 // The bit test instructions below are AVX only
6516 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6517 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6518 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6519 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6520 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6521 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6522 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6523 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6527 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6528 let ExeDomain = SSEPackedSingle in {
6529 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6530 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6533 let ExeDomain = SSEPackedDouble in {
6534 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6535 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6540 //===----------------------------------------------------------------------===//
6541 // SSE4.1 - Misc Instructions
6542 //===----------------------------------------------------------------------===//
6544 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6545 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6546 "popcnt{w}\t{$src, $dst|$dst, $src}",
6547 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6549 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6550 "popcnt{w}\t{$src, $dst|$dst, $src}",
6551 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6552 (implicit EFLAGS)]>, OpSize, XS;
6554 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6555 "popcnt{l}\t{$src, $dst|$dst, $src}",
6556 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6558 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6559 "popcnt{l}\t{$src, $dst|$dst, $src}",
6560 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6561 (implicit EFLAGS)]>, XS;
6563 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6564 "popcnt{q}\t{$src, $dst|$dst, $src}",
6565 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6567 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6568 "popcnt{q}\t{$src, $dst|$dst, $src}",
6569 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6570 (implicit EFLAGS)]>, XS;
6575 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6576 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6577 Intrinsic IntId128> {
6578 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6581 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6582 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6587 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6590 let Predicates = [HasAVX] in
6591 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6592 int_x86_sse41_phminposuw>, VEX;
6593 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6594 int_x86_sse41_phminposuw>;
6596 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6597 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6598 Intrinsic IntId128, bit Is2Addr = 1> {
6599 let isCommutable = 1 in
6600 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6601 (ins VR128:$src1, VR128:$src2),
6603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6605 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6606 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6607 (ins VR128:$src1, i128mem:$src2),
6609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6612 (IntId128 VR128:$src1,
6613 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6616 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6617 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6618 Intrinsic IntId256> {
6619 let isCommutable = 1 in
6620 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6621 (ins VR256:$src1, VR256:$src2),
6622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6623 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6624 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6625 (ins VR256:$src1, i256mem:$src2),
6626 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6628 (IntId256 VR256:$src1,
6629 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6633 /// SS48I_binop_rm - Simple SSE41 binary operator.
6634 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6635 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6636 X86MemOperand x86memop, bit Is2Addr = 1> {
6637 let isCommutable = 1 in
6638 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6639 (ins RC:$src1, RC:$src2),
6641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6643 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6644 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6645 (ins RC:$src1, x86memop:$src2),
6647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6650 (OpVT (OpNode RC:$src1,
6651 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6654 let Predicates = [HasAVX] in {
6655 let isCommutable = 0 in
6656 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6658 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6659 memopv2i64, i128mem, 0>, VEX_4V;
6660 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6661 memopv2i64, i128mem, 0>, VEX_4V;
6662 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6663 memopv2i64, i128mem, 0>, VEX_4V;
6664 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6665 memopv2i64, i128mem, 0>, VEX_4V;
6666 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6667 memopv2i64, i128mem, 0>, VEX_4V;
6668 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6669 memopv2i64, i128mem, 0>, VEX_4V;
6670 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6671 memopv2i64, i128mem, 0>, VEX_4V;
6672 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6673 memopv2i64, i128mem, 0>, VEX_4V;
6674 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6678 let Predicates = [HasAVX2] in {
6679 let isCommutable = 0 in
6680 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6681 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6682 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6683 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6684 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6685 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6686 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6687 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6688 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6689 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6690 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6691 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6692 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6693 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6694 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6695 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6696 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6697 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6698 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6699 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6702 let Constraints = "$src1 = $dst" in {
6703 let isCommutable = 0 in
6704 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6705 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6706 memopv2i64, i128mem>;
6707 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6708 memopv2i64, i128mem>;
6709 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6710 memopv2i64, i128mem>;
6711 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6712 memopv2i64, i128mem>;
6713 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6714 memopv2i64, i128mem>;
6715 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6716 memopv2i64, i128mem>;
6717 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6718 memopv2i64, i128mem>;
6719 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6720 memopv2i64, i128mem>;
6721 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6724 let Predicates = [HasAVX] in {
6725 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6726 memopv2i64, i128mem, 0>, VEX_4V;
6727 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6728 memopv2i64, i128mem, 0>, VEX_4V;
6730 let Predicates = [HasAVX2] in {
6731 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6732 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6733 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6734 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6737 let Constraints = "$src1 = $dst" in {
6738 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6739 memopv2i64, i128mem>;
6740 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6741 memopv2i64, i128mem>;
6744 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6745 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6746 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6747 X86MemOperand x86memop, bit Is2Addr = 1> {
6748 let isCommutable = 1 in
6749 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6750 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6752 !strconcat(OpcodeStr,
6753 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6754 !strconcat(OpcodeStr,
6755 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6756 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6758 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6759 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6761 !strconcat(OpcodeStr,
6762 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6763 !strconcat(OpcodeStr,
6764 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6767 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6771 let Predicates = [HasAVX] in {
6772 let isCommutable = 0 in {
6773 let ExeDomain = SSEPackedSingle in {
6774 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6775 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6776 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6777 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6778 f256mem, 0>, VEX_4V, VEX_L;
6780 let ExeDomain = SSEPackedDouble in {
6781 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6782 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6783 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6784 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6785 f256mem, 0>, VEX_4V, VEX_L;
6787 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6788 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6789 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6790 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6792 let ExeDomain = SSEPackedSingle in
6793 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6794 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6795 let ExeDomain = SSEPackedDouble in
6796 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6797 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6798 let ExeDomain = SSEPackedSingle in
6799 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6800 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6803 let Predicates = [HasAVX2] in {
6804 let isCommutable = 0 in {
6805 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6806 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6807 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6808 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6812 let Constraints = "$src1 = $dst" in {
6813 let isCommutable = 0 in {
6814 let ExeDomain = SSEPackedSingle in
6815 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6816 VR128, memopv4f32, f128mem>;
6817 let ExeDomain = SSEPackedDouble in
6818 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6819 VR128, memopv2f64, f128mem>;
6820 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6821 VR128, memopv2i64, i128mem>;
6822 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6823 VR128, memopv2i64, i128mem>;
6825 let ExeDomain = SSEPackedSingle in
6826 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6827 VR128, memopv4f32, f128mem>;
6828 let ExeDomain = SSEPackedDouble in
6829 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6830 VR128, memopv2f64, f128mem>;
6833 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6834 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6835 RegisterClass RC, X86MemOperand x86memop,
6836 PatFrag mem_frag, Intrinsic IntId> {
6837 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6838 (ins RC:$src1, RC:$src2, RC:$src3),
6839 !strconcat(OpcodeStr,
6840 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6841 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6842 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6844 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6845 (ins RC:$src1, x86memop:$src2, RC:$src3),
6846 !strconcat(OpcodeStr,
6847 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6849 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6851 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6854 let Predicates = [HasAVX] in {
6855 let ExeDomain = SSEPackedDouble in {
6856 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6857 memopv2f64, int_x86_sse41_blendvpd>;
6858 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6859 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6860 } // ExeDomain = SSEPackedDouble
6861 let ExeDomain = SSEPackedSingle in {
6862 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6863 memopv4f32, int_x86_sse41_blendvps>;
6864 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6865 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6866 } // ExeDomain = SSEPackedSingle
6867 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6868 memopv2i64, int_x86_sse41_pblendvb>;
6871 let Predicates = [HasAVX2] in {
6872 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6873 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6876 let Predicates = [HasAVX] in {
6877 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6878 (v16i8 VR128:$src2))),
6879 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6880 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6881 (v4i32 VR128:$src2))),
6882 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6883 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6884 (v4f32 VR128:$src2))),
6885 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6886 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6887 (v2i64 VR128:$src2))),
6888 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6889 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6890 (v2f64 VR128:$src2))),
6891 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6892 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6893 (v8i32 VR256:$src2))),
6894 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6895 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6896 (v8f32 VR256:$src2))),
6897 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6898 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6899 (v4i64 VR256:$src2))),
6900 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6901 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6902 (v4f64 VR256:$src2))),
6903 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6905 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6907 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6908 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6910 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6912 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6914 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6915 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6917 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6918 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6920 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6923 let Predicates = [HasAVX2] in {
6924 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6925 (v32i8 VR256:$src2))),
6926 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6927 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6929 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6932 /// SS41I_ternary_int - SSE 4.1 ternary operator
6933 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6934 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6935 X86MemOperand x86memop, Intrinsic IntId> {
6936 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6937 (ins VR128:$src1, VR128:$src2),
6938 !strconcat(OpcodeStr,
6939 "\t{$src2, $dst|$dst, $src2}"),
6940 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6943 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6944 (ins VR128:$src1, x86memop:$src2),
6945 !strconcat(OpcodeStr,
6946 "\t{$src2, $dst|$dst, $src2}"),
6949 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6953 let ExeDomain = SSEPackedDouble in
6954 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6955 int_x86_sse41_blendvpd>;
6956 let ExeDomain = SSEPackedSingle in
6957 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6958 int_x86_sse41_blendvps>;
6959 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6960 int_x86_sse41_pblendvb>;
6962 // Aliases with the implicit xmm0 argument
6963 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6964 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6965 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6966 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6967 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6968 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6969 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6970 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6971 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6972 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6973 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6974 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6976 let Predicates = [UseSSE41] in {
6977 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6978 (v16i8 VR128:$src2))),
6979 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6980 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6981 (v4i32 VR128:$src2))),
6982 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6983 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6984 (v4f32 VR128:$src2))),
6985 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6986 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6987 (v2i64 VR128:$src2))),
6988 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6989 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6990 (v2f64 VR128:$src2))),
6991 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6993 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6995 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6996 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6998 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6999 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7001 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7005 let Predicates = [HasAVX] in
7006 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7007 "vmovntdqa\t{$src, $dst|$dst, $src}",
7008 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7010 let Predicates = [HasAVX2] in
7011 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7012 "vmovntdqa\t{$src, $dst|$dst, $src}",
7013 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7015 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7016 "movntdqa\t{$src, $dst|$dst, $src}",
7017 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7020 //===----------------------------------------------------------------------===//
7021 // SSE4.2 - Compare Instructions
7022 //===----------------------------------------------------------------------===//
7024 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7025 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7026 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7027 X86MemOperand x86memop, bit Is2Addr = 1> {
7028 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7029 (ins RC:$src1, RC:$src2),
7031 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7033 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7035 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7036 (ins RC:$src1, x86memop:$src2),
7038 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7041 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7044 let Predicates = [HasAVX] in
7045 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7046 memopv2i64, i128mem, 0>, VEX_4V;
7048 let Predicates = [HasAVX2] in
7049 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7050 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7052 let Constraints = "$src1 = $dst" in
7053 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7054 memopv2i64, i128mem>;
7056 //===----------------------------------------------------------------------===//
7057 // SSE4.2 - String/text Processing Instructions
7058 //===----------------------------------------------------------------------===//
7060 // Packed Compare Implicit Length Strings, Return Mask
7061 multiclass pseudo_pcmpistrm<string asm> {
7062 def REG : PseudoI<(outs VR128:$dst),
7063 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7064 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7066 def MEM : PseudoI<(outs VR128:$dst),
7067 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7068 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7069 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7072 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7073 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7074 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7077 multiclass pcmpistrm_SS42AI<string asm> {
7078 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7079 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7080 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7083 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7084 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7085 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7089 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7090 let Predicates = [HasAVX] in
7091 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7092 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7095 // Packed Compare Explicit Length Strings, Return Mask
7096 multiclass pseudo_pcmpestrm<string asm> {
7097 def REG : PseudoI<(outs VR128:$dst),
7098 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7099 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7100 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7101 def MEM : PseudoI<(outs VR128:$dst),
7102 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7103 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7104 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7107 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7108 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7109 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7112 multiclass SS42AI_pcmpestrm<string asm> {
7113 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7114 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7115 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7118 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7119 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7120 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7124 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7125 let Predicates = [HasAVX] in
7126 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7127 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7130 // Packed Compare Implicit Length Strings, Return Index
7131 multiclass pseudo_pcmpistri<string asm> {
7132 def REG : PseudoI<(outs GR32:$dst),
7133 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7134 [(set GR32:$dst, EFLAGS,
7135 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7136 def MEM : PseudoI<(outs GR32:$dst),
7137 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7138 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7139 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7142 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7143 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7144 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7147 multiclass SS42AI_pcmpistri<string asm> {
7148 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7149 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7150 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7153 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7154 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7155 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7159 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7160 let Predicates = [HasAVX] in
7161 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7162 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7165 // Packed Compare Explicit Length Strings, Return Index
7166 multiclass pseudo_pcmpestri<string asm> {
7167 def REG : PseudoI<(outs GR32:$dst),
7168 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7169 [(set GR32:$dst, EFLAGS,
7170 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7171 def MEM : PseudoI<(outs GR32:$dst),
7172 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7173 [(set GR32:$dst, EFLAGS,
7174 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7178 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7179 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7180 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7183 multiclass SS42AI_pcmpestri<string asm> {
7184 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7185 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7186 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7189 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7190 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7191 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7195 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7196 let Predicates = [HasAVX] in
7197 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7198 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7201 //===----------------------------------------------------------------------===//
7202 // SSE4.2 - CRC Instructions
7203 //===----------------------------------------------------------------------===//
7205 // No CRC instructions have AVX equivalents
7207 // crc intrinsic instruction
7208 // This set of instructions are only rm, the only difference is the size
7210 let Constraints = "$src1 = $dst" in {
7211 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7212 (ins GR32:$src1, i8mem:$src2),
7213 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7215 (int_x86_sse42_crc32_32_8 GR32:$src1,
7216 (load addr:$src2)))]>;
7217 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7218 (ins GR32:$src1, GR8:$src2),
7219 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7221 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7222 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7223 (ins GR32:$src1, i16mem:$src2),
7224 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7226 (int_x86_sse42_crc32_32_16 GR32:$src1,
7227 (load addr:$src2)))]>,
7229 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7230 (ins GR32:$src1, GR16:$src2),
7231 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7233 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7235 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7236 (ins GR32:$src1, i32mem:$src2),
7237 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7239 (int_x86_sse42_crc32_32_32 GR32:$src1,
7240 (load addr:$src2)))]>;
7241 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7242 (ins GR32:$src1, GR32:$src2),
7243 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7245 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7246 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7247 (ins GR64:$src1, i8mem:$src2),
7248 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7250 (int_x86_sse42_crc32_64_8 GR64:$src1,
7251 (load addr:$src2)))]>,
7253 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7254 (ins GR64:$src1, GR8:$src2),
7255 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7257 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7259 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7260 (ins GR64:$src1, i64mem:$src2),
7261 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7263 (int_x86_sse42_crc32_64_64 GR64:$src1,
7264 (load addr:$src2)))]>,
7266 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7267 (ins GR64:$src1, GR64:$src2),
7268 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7270 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7274 //===----------------------------------------------------------------------===//
7275 // AES-NI Instructions
7276 //===----------------------------------------------------------------------===//
7278 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7279 Intrinsic IntId128, bit Is2Addr = 1> {
7280 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7281 (ins VR128:$src1, VR128:$src2),
7283 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7285 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7287 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7288 (ins VR128:$src1, i128mem:$src2),
7290 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7293 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7296 // Perform One Round of an AES Encryption/Decryption Flow
7297 let Predicates = [HasAVX, HasAES] in {
7298 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7299 int_x86_aesni_aesenc, 0>, VEX_4V;
7300 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7301 int_x86_aesni_aesenclast, 0>, VEX_4V;
7302 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7303 int_x86_aesni_aesdec, 0>, VEX_4V;
7304 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7305 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7308 let Constraints = "$src1 = $dst" in {
7309 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7310 int_x86_aesni_aesenc>;
7311 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7312 int_x86_aesni_aesenclast>;
7313 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7314 int_x86_aesni_aesdec>;
7315 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7316 int_x86_aesni_aesdeclast>;
7319 // Perform the AES InvMixColumn Transformation
7320 let Predicates = [HasAVX, HasAES] in {
7321 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7323 "vaesimc\t{$src1, $dst|$dst, $src1}",
7325 (int_x86_aesni_aesimc VR128:$src1))]>,
7327 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7328 (ins i128mem:$src1),
7329 "vaesimc\t{$src1, $dst|$dst, $src1}",
7330 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7333 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7335 "aesimc\t{$src1, $dst|$dst, $src1}",
7337 (int_x86_aesni_aesimc VR128:$src1))]>,
7339 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7340 (ins i128mem:$src1),
7341 "aesimc\t{$src1, $dst|$dst, $src1}",
7342 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7345 // AES Round Key Generation Assist
7346 let Predicates = [HasAVX, HasAES] in {
7347 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7348 (ins VR128:$src1, i8imm:$src2),
7349 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7351 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7353 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7354 (ins i128mem:$src1, i8imm:$src2),
7355 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7357 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7360 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7361 (ins VR128:$src1, i8imm:$src2),
7362 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7364 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7366 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7367 (ins i128mem:$src1, i8imm:$src2),
7368 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7370 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7373 //===----------------------------------------------------------------------===//
7374 // PCLMUL Instructions
7375 //===----------------------------------------------------------------------===//
7377 // AVX carry-less Multiplication instructions
7378 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7379 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7380 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7382 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7384 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7385 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7386 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7387 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7388 (memopv2i64 addr:$src2), imm:$src3))]>;
7390 // Carry-less Multiplication instructions
7391 let Constraints = "$src1 = $dst" in {
7392 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7393 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7394 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7396 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7398 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7399 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7400 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7401 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7402 (memopv2i64 addr:$src2), imm:$src3))]>;
7403 } // Constraints = "$src1 = $dst"
7406 multiclass pclmul_alias<string asm, int immop> {
7407 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7408 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7410 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7411 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7413 def : InstAlias<!strconcat("vpclmul", asm,
7414 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7415 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7417 def : InstAlias<!strconcat("vpclmul", asm,
7418 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7419 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7421 defm : pclmul_alias<"hqhq", 0x11>;
7422 defm : pclmul_alias<"hqlq", 0x01>;
7423 defm : pclmul_alias<"lqhq", 0x10>;
7424 defm : pclmul_alias<"lqlq", 0x00>;
7426 //===----------------------------------------------------------------------===//
7427 // SSE4A Instructions
7428 //===----------------------------------------------------------------------===//
7430 let Predicates = [HasSSE4A] in {
7432 let Constraints = "$src = $dst" in {
7433 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7434 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7435 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7436 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7437 imm:$idx))]>, TB, OpSize;
7438 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7439 (ins VR128:$src, VR128:$mask),
7440 "extrq\t{$mask, $src|$src, $mask}",
7441 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7442 VR128:$mask))]>, TB, OpSize;
7444 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7445 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7446 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7447 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7448 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7449 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7450 (ins VR128:$src, VR128:$mask),
7451 "insertq\t{$mask, $src|$src, $mask}",
7452 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7453 VR128:$mask))]>, XD;
7456 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7457 "movntss\t{$src, $dst|$dst, $src}",
7458 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7460 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7461 "movntsd\t{$src, $dst|$dst, $src}",
7462 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7465 //===----------------------------------------------------------------------===//
7467 //===----------------------------------------------------------------------===//
7469 //===----------------------------------------------------------------------===//
7470 // VBROADCAST - Load from memory and broadcast to all elements of the
7471 // destination operand
7473 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7474 X86MemOperand x86memop, Intrinsic Int> :
7475 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7477 [(set RC:$dst, (Int addr:$src))]>, VEX;
7479 // AVX2 adds register forms
7480 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7482 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7483 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7484 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7486 let ExeDomain = SSEPackedSingle in {
7487 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7488 int_x86_avx_vbroadcast_ss>;
7489 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7490 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7492 let ExeDomain = SSEPackedDouble in
7493 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7494 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7495 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7496 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7498 let ExeDomain = SSEPackedSingle in {
7499 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7500 int_x86_avx2_vbroadcast_ss_ps>;
7501 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7502 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7504 let ExeDomain = SSEPackedDouble in
7505 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7506 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7508 let Predicates = [HasAVX2] in
7509 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7510 int_x86_avx2_vbroadcasti128>, VEX_L;
7512 let Predicates = [HasAVX] in
7513 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7514 (VBROADCASTF128 addr:$src)>;
7517 //===----------------------------------------------------------------------===//
7518 // VINSERTF128 - Insert packed floating-point values
7520 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7521 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7522 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7523 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7526 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7527 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7528 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7532 let Predicates = [HasAVX] in {
7533 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7535 (VINSERTF128rr VR256:$src1, VR128:$src2,
7536 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7537 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7539 (VINSERTF128rr VR256:$src1, VR128:$src2,
7540 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7542 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7544 (VINSERTF128rm VR256:$src1, addr:$src2,
7545 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7546 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7548 (VINSERTF128rm VR256:$src1, addr:$src2,
7549 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7552 let Predicates = [HasAVX1Only] in {
7553 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7555 (VINSERTF128rr VR256:$src1, VR128:$src2,
7556 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7557 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7559 (VINSERTF128rr VR256:$src1, VR128:$src2,
7560 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7561 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7563 (VINSERTF128rr VR256:$src1, VR128:$src2,
7564 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7565 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7567 (VINSERTF128rr VR256:$src1, VR128:$src2,
7568 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7570 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7572 (VINSERTF128rm VR256:$src1, addr:$src2,
7573 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7574 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7575 (bc_v4i32 (memopv2i64 addr:$src2)),
7577 (VINSERTF128rm VR256:$src1, addr:$src2,
7578 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7579 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7580 (bc_v16i8 (memopv2i64 addr:$src2)),
7582 (VINSERTF128rm VR256:$src1, addr:$src2,
7583 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7584 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7585 (bc_v8i16 (memopv2i64 addr:$src2)),
7587 (VINSERTF128rm VR256:$src1, addr:$src2,
7588 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7591 //===----------------------------------------------------------------------===//
7592 // VEXTRACTF128 - Extract packed floating-point values
7594 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7595 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7596 (ins VR256:$src1, i8imm:$src2),
7597 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7600 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7601 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7602 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7607 let Predicates = [HasAVX] in {
7608 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7609 (v4f32 (VEXTRACTF128rr
7610 (v8f32 VR256:$src1),
7611 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7612 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7613 (v2f64 (VEXTRACTF128rr
7614 (v4f64 VR256:$src1),
7615 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7617 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7618 (iPTR imm))), addr:$dst),
7619 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7620 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7621 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7622 (iPTR imm))), addr:$dst),
7623 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7624 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7627 let Predicates = [HasAVX1Only] in {
7628 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7629 (v2i64 (VEXTRACTF128rr
7630 (v4i64 VR256:$src1),
7631 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7632 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7633 (v4i32 (VEXTRACTF128rr
7634 (v8i32 VR256:$src1),
7635 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7636 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7637 (v8i16 (VEXTRACTF128rr
7638 (v16i16 VR256:$src1),
7639 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7640 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7641 (v16i8 (VEXTRACTF128rr
7642 (v32i8 VR256:$src1),
7643 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7645 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7646 (iPTR imm))), addr:$dst),
7647 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7648 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7649 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7650 (iPTR imm))), addr:$dst),
7651 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7652 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7653 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7654 (iPTR imm))), addr:$dst),
7655 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7656 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7657 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7658 (iPTR imm))), addr:$dst),
7659 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7660 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7663 //===----------------------------------------------------------------------===//
7664 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7666 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7667 Intrinsic IntLd, Intrinsic IntLd256,
7668 Intrinsic IntSt, Intrinsic IntSt256> {
7669 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7670 (ins VR128:$src1, f128mem:$src2),
7671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7672 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7674 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7675 (ins VR256:$src1, f256mem:$src2),
7676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7677 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7679 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7680 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7681 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7682 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7683 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7684 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7685 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7686 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7689 let ExeDomain = SSEPackedSingle in
7690 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7691 int_x86_avx_maskload_ps,
7692 int_x86_avx_maskload_ps_256,
7693 int_x86_avx_maskstore_ps,
7694 int_x86_avx_maskstore_ps_256>;
7695 let ExeDomain = SSEPackedDouble in
7696 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7697 int_x86_avx_maskload_pd,
7698 int_x86_avx_maskload_pd_256,
7699 int_x86_avx_maskstore_pd,
7700 int_x86_avx_maskstore_pd_256>;
7702 //===----------------------------------------------------------------------===//
7703 // VPERMIL - Permute Single and Double Floating-Point Values
7705 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7706 RegisterClass RC, X86MemOperand x86memop_f,
7707 X86MemOperand x86memop_i, PatFrag i_frag,
7708 Intrinsic IntVar, ValueType vt> {
7709 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7710 (ins RC:$src1, RC:$src2),
7711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7712 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7713 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7714 (ins RC:$src1, x86memop_i:$src2),
7715 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7716 [(set RC:$dst, (IntVar RC:$src1,
7717 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7719 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7720 (ins RC:$src1, i8imm:$src2),
7721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7722 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7723 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7724 (ins x86memop_f:$src1, i8imm:$src2),
7725 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7727 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7730 let ExeDomain = SSEPackedSingle in {
7731 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7732 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7733 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7734 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7736 let ExeDomain = SSEPackedDouble in {
7737 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7738 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7739 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7740 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7743 let Predicates = [HasAVX] in {
7744 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7745 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7746 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7747 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7748 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7750 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7751 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7752 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7754 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7755 (VPERMILPDri VR128:$src1, imm:$imm)>;
7756 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7757 (VPERMILPDmi addr:$src1, imm:$imm)>;
7760 //===----------------------------------------------------------------------===//
7761 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7763 let ExeDomain = SSEPackedSingle in {
7764 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7765 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7766 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7767 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7768 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7769 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7770 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7771 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7772 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7773 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7776 let Predicates = [HasAVX] in {
7777 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7778 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7779 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7780 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7781 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7784 let Predicates = [HasAVX1Only] in {
7785 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7786 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7787 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7788 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7789 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7790 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7791 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7792 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7794 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7795 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7796 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7797 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7798 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7799 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7800 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7801 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7802 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7803 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7804 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7805 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7808 //===----------------------------------------------------------------------===//
7809 // VZERO - Zero YMM registers
7811 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7812 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7813 // Zero All YMM registers
7814 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7815 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7817 // Zero Upper bits of YMM registers
7818 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7819 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7822 //===----------------------------------------------------------------------===//
7823 // Half precision conversion instructions
7824 //===----------------------------------------------------------------------===//
7825 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7826 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7827 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7828 [(set RC:$dst, (Int VR128:$src))]>,
7830 let neverHasSideEffects = 1, mayLoad = 1 in
7831 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7832 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7835 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7836 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7837 (ins RC:$src1, i32i8imm:$src2),
7838 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7839 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7841 let neverHasSideEffects = 1, mayStore = 1 in
7842 def mr : Ii8<0x1D, MRMDestMem, (outs),
7843 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7844 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7848 let Predicates = [HasAVX, HasF16C] in {
7849 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7850 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7851 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7852 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7855 //===----------------------------------------------------------------------===//
7856 // AVX2 Instructions
7857 //===----------------------------------------------------------------------===//
7859 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7860 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7861 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7862 X86MemOperand x86memop> {
7863 let isCommutable = 1 in
7864 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7865 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7866 !strconcat(OpcodeStr,
7867 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7868 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7870 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7871 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7872 !strconcat(OpcodeStr,
7873 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7876 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7880 let isCommutable = 0 in {
7881 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7882 VR128, memopv2i64, i128mem>;
7883 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7884 VR256, memopv4i64, i256mem>, VEX_L;
7887 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7889 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7890 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7892 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7894 //===----------------------------------------------------------------------===//
7895 // VPBROADCAST - Load from memory and broadcast to all elements of the
7896 // destination operand
7898 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7899 X86MemOperand x86memop, PatFrag ld_frag,
7900 Intrinsic Int128, Intrinsic Int256> {
7901 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7903 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7904 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7905 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7907 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7908 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7909 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7910 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7911 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7914 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7918 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7919 int_x86_avx2_pbroadcastb_128,
7920 int_x86_avx2_pbroadcastb_256>;
7921 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7922 int_x86_avx2_pbroadcastw_128,
7923 int_x86_avx2_pbroadcastw_256>;
7924 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7925 int_x86_avx2_pbroadcastd_128,
7926 int_x86_avx2_pbroadcastd_256>;
7927 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7928 int_x86_avx2_pbroadcastq_128,
7929 int_x86_avx2_pbroadcastq_256>;
7931 let Predicates = [HasAVX2] in {
7932 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7933 (VPBROADCASTBrm addr:$src)>;
7934 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7935 (VPBROADCASTBYrm addr:$src)>;
7936 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7937 (VPBROADCASTWrm addr:$src)>;
7938 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7939 (VPBROADCASTWYrm addr:$src)>;
7940 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7941 (VPBROADCASTDrm addr:$src)>;
7942 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7943 (VPBROADCASTDYrm addr:$src)>;
7944 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7945 (VPBROADCASTQrm addr:$src)>;
7946 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7947 (VPBROADCASTQYrm addr:$src)>;
7949 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7950 (VPBROADCASTBrr VR128:$src)>;
7951 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7952 (VPBROADCASTBYrr VR128:$src)>;
7953 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7954 (VPBROADCASTWrr VR128:$src)>;
7955 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7956 (VPBROADCASTWYrr VR128:$src)>;
7957 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7958 (VPBROADCASTDrr VR128:$src)>;
7959 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7960 (VPBROADCASTDYrr VR128:$src)>;
7961 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7962 (VPBROADCASTQrr VR128:$src)>;
7963 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7964 (VPBROADCASTQYrr VR128:$src)>;
7965 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7966 (VBROADCASTSSrr VR128:$src)>;
7967 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7968 (VBROADCASTSSYrr VR128:$src)>;
7969 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7970 (VPBROADCASTQrr VR128:$src)>;
7971 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7972 (VBROADCASTSDYrr VR128:$src)>;
7974 // Provide fallback in case the load node that is used in the patterns above
7975 // is used by additional users, which prevents the pattern selection.
7976 let AddedComplexity = 20 in {
7977 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7978 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7979 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7980 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7981 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7982 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7984 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7985 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7986 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7987 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7988 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7989 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7993 // AVX1 broadcast patterns
7994 let Predicates = [HasAVX1Only] in {
7995 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7996 (VBROADCASTSSYrm addr:$src)>;
7997 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7998 (VBROADCASTSDYrm addr:$src)>;
7999 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8000 (VBROADCASTSSrm addr:$src)>;
8003 let Predicates = [HasAVX] in {
8004 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8005 (VBROADCASTSSYrm addr:$src)>;
8006 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8007 (VBROADCASTSDYrm addr:$src)>;
8008 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8009 (VBROADCASTSSrm addr:$src)>;
8011 // Provide fallback in case the load node that is used in the patterns above
8012 // is used by additional users, which prevents the pattern selection.
8013 let AddedComplexity = 20 in {
8014 // 128bit broadcasts:
8015 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8016 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8017 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8018 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8019 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8020 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8021 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8022 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8023 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8024 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8026 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8027 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8028 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8029 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8030 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8031 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8032 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8033 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8034 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8035 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8039 //===----------------------------------------------------------------------===//
8040 // VPERM - Permute instructions
8043 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8045 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8046 (ins VR256:$src1, VR256:$src2),
8047 !strconcat(OpcodeStr,
8048 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8050 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8052 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8053 (ins VR256:$src1, i256mem:$src2),
8054 !strconcat(OpcodeStr,
8055 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8057 (OpVT (X86VPermv VR256:$src1,
8058 (bitconvert (mem_frag addr:$src2)))))]>,
8062 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8063 let ExeDomain = SSEPackedSingle in
8064 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8066 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8068 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8069 (ins VR256:$src1, i8imm:$src2),
8070 !strconcat(OpcodeStr,
8071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8073 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8075 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8076 (ins i256mem:$src1, i8imm:$src2),
8077 !strconcat(OpcodeStr,
8078 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8080 (OpVT (X86VPermi (mem_frag addr:$src1),
8081 (i8 imm:$src2))))]>, VEX, VEX_L;
8084 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8085 let ExeDomain = SSEPackedDouble in
8086 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8088 //===----------------------------------------------------------------------===//
8089 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8091 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8092 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8093 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8094 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8095 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8096 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8097 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8098 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8099 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8100 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8102 let Predicates = [HasAVX2] in {
8103 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8104 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8105 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8106 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8107 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8108 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8110 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8112 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8113 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8114 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8115 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8116 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8118 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8122 //===----------------------------------------------------------------------===//
8123 // VINSERTI128 - Insert packed integer values
8125 let neverHasSideEffects = 1 in {
8126 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8127 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8128 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8131 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8132 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8133 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8137 let Predicates = [HasAVX2] in {
8138 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8140 (VINSERTI128rr VR256:$src1, VR128:$src2,
8141 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8142 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8144 (VINSERTI128rr VR256:$src1, VR128:$src2,
8145 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8146 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8148 (VINSERTI128rr VR256:$src1, VR128:$src2,
8149 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8150 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8152 (VINSERTI128rr VR256:$src1, VR128:$src2,
8153 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8155 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8157 (VINSERTI128rm VR256:$src1, addr:$src2,
8158 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8159 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
8160 (bc_v4i32 (memopv2i64 addr:$src2)),
8162 (VINSERTI128rm VR256:$src1, addr:$src2,
8163 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8164 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
8165 (bc_v16i8 (memopv2i64 addr:$src2)),
8167 (VINSERTI128rm VR256:$src1, addr:$src2,
8168 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8169 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
8170 (bc_v8i16 (memopv2i64 addr:$src2)),
8172 (VINSERTI128rm VR256:$src1, addr:$src2,
8173 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8176 //===----------------------------------------------------------------------===//
8177 // VEXTRACTI128 - Extract packed integer values
8179 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8180 (ins VR256:$src1, i8imm:$src2),
8181 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8183 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8185 let neverHasSideEffects = 1, mayStore = 1 in
8186 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8187 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8188 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8191 let Predicates = [HasAVX2] in {
8192 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8193 (v2i64 (VEXTRACTI128rr
8194 (v4i64 VR256:$src1),
8195 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8196 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8197 (v4i32 (VEXTRACTI128rr
8198 (v8i32 VR256:$src1),
8199 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8200 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8201 (v8i16 (VEXTRACTI128rr
8202 (v16i16 VR256:$src1),
8203 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8204 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8205 (v16i8 (VEXTRACTI128rr
8206 (v32i8 VR256:$src1),
8207 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8209 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8210 (iPTR imm))), addr:$dst),
8211 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8212 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8213 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8214 (iPTR imm))), addr:$dst),
8215 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8216 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8217 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8218 (iPTR imm))), addr:$dst),
8219 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8220 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8221 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8222 (iPTR imm))), addr:$dst),
8223 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8224 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8227 //===----------------------------------------------------------------------===//
8228 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8230 multiclass avx2_pmovmask<string OpcodeStr,
8231 Intrinsic IntLd128, Intrinsic IntLd256,
8232 Intrinsic IntSt128, Intrinsic IntSt256> {
8233 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8234 (ins VR128:$src1, i128mem:$src2),
8235 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8236 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8237 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8238 (ins VR256:$src1, i256mem:$src2),
8239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8240 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8242 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8243 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8245 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8246 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8247 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8249 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8252 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8253 int_x86_avx2_maskload_d,
8254 int_x86_avx2_maskload_d_256,
8255 int_x86_avx2_maskstore_d,
8256 int_x86_avx2_maskstore_d_256>;
8257 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8258 int_x86_avx2_maskload_q,
8259 int_x86_avx2_maskload_q_256,
8260 int_x86_avx2_maskstore_q,
8261 int_x86_avx2_maskstore_q_256>, VEX_W;
8264 //===----------------------------------------------------------------------===//
8265 // Variable Bit Shifts
8267 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8268 ValueType vt128, ValueType vt256> {
8269 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8270 (ins VR128:$src1, VR128:$src2),
8271 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8273 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8275 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8276 (ins VR128:$src1, i128mem:$src2),
8277 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8279 (vt128 (OpNode VR128:$src1,
8280 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8282 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8283 (ins VR256:$src1, VR256:$src2),
8284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8286 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8288 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8289 (ins VR256:$src1, i256mem:$src2),
8290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8292 (vt256 (OpNode VR256:$src1,
8293 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8297 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8298 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8299 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8300 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8301 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8303 //===----------------------------------------------------------------------===//
8304 // VGATHER - GATHER Operations
8305 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8306 X86MemOperand memop128, X86MemOperand memop256> {
8307 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8308 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8309 !strconcat(OpcodeStr,
8310 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8312 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8313 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8314 !strconcat(OpcodeStr,
8315 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8316 []>, VEX_4VOp3, VEX_L;
8319 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8320 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8321 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8322 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8323 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8324 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8325 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8326 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8327 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;