1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 let Predicates = [HasSSE1] in {
190 // MOVSSrm zeros the high parts of the register; represent this
191 // with SUBREG_TO_REG.
192 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
194 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
196 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
197 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 let Predicates = [HasSSE2] in {
200 // MOVSDrm zeros the high parts of the register; represent this
201 // with SUBREG_TO_REG.
202 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
203 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
204 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
205 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
206 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
207 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
208 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
209 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
210 def : Pat<(v2f64 (X86vzload addr:$src)),
211 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
215 let AddedComplexity = 20, Predicates = [HasAVX] in {
216 // MOVSSrm zeros the high parts of the register; represent this
217 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
218 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
219 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
220 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
221 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
222 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
223 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
224 // MOVSDrm zeros the high parts of the register; represent this
225 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
226 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
227 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
228 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
229 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
230 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
231 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
232 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
233 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
234 def : Pat<(v2f64 (X86vzload addr:$src)),
235 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
236 // Represent the same patterns above but in the form they appear for
238 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
239 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
240 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
241 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
242 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
243 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
246 // Store scalar value to memory.
247 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
248 "movss\t{$src, $dst|$dst, $src}",
249 [(store FR32:$src, addr:$dst)]>;
250 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
251 "movsd\t{$src, $dst|$dst, $src}",
252 [(store FR64:$src, addr:$dst)]>;
254 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
255 "movss\t{$src, $dst|$dst, $src}",
256 [(store FR32:$src, addr:$dst)]>, XS, VEX;
257 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
258 "movsd\t{$src, $dst|$dst, $src}",
259 [(store FR64:$src, addr:$dst)]>, XD, VEX;
261 // Extract and store.
262 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
265 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
266 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
271 // Move Aligned/Unaligned floating point values
272 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
273 X86MemOperand x86memop, PatFrag ld_frag,
274 string asm, Domain d,
275 bit IsReMaterializable = 1> {
276 let neverHasSideEffects = 1 in
277 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
279 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
280 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
281 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
282 [(set RC:$dst, (ld_frag addr:$src))], d>;
285 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
286 "movaps", SSEPackedSingle>, VEX;
287 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
288 "movapd", SSEPackedDouble>, OpSize, VEX;
289 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
290 "movups", SSEPackedSingle>, VEX;
291 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
292 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
294 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
295 "movaps", SSEPackedSingle>, VEX;
296 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
297 "movapd", SSEPackedDouble>, OpSize, VEX;
298 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
299 "movups", SSEPackedSingle>, VEX;
300 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
301 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
302 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
303 "movaps", SSEPackedSingle>, TB;
304 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
305 "movapd", SSEPackedDouble>, TB, OpSize;
306 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
307 "movups", SSEPackedSingle>, TB;
308 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
309 "movupd", SSEPackedDouble, 0>, TB, OpSize;
311 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
312 "movaps\t{$src, $dst|$dst, $src}",
313 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
314 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
315 "movapd\t{$src, $dst|$dst, $src}",
316 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
317 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movups\t{$src, $dst|$dst, $src}",
319 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
320 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movupd\t{$src, $dst|$dst, $src}",
322 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
323 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
324 "movaps\t{$src, $dst|$dst, $src}",
325 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
326 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
327 "movapd\t{$src, $dst|$dst, $src}",
328 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
329 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
330 "movups\t{$src, $dst|$dst, $src}",
331 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
332 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
333 "movupd\t{$src, $dst|$dst, $src}",
334 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
337 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
338 (VMOVUPSYmr addr:$dst, VR256:$src)>;
340 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
341 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
342 (VMOVUPDYmr addr:$dst, VR256:$src)>;
344 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
345 "movaps\t{$src, $dst|$dst, $src}",
346 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
347 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
348 "movapd\t{$src, $dst|$dst, $src}",
349 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
350 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
351 "movups\t{$src, $dst|$dst, $src}",
352 [(store (v4f32 VR128:$src), addr:$dst)]>;
353 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
354 "movupd\t{$src, $dst|$dst, $src}",
355 [(store (v2f64 VR128:$src), addr:$dst)]>;
357 // Intrinsic forms of MOVUPS/D load and store
358 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
359 (ins f128mem:$dst, VR128:$src),
360 "movups\t{$src, $dst|$dst, $src}",
361 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
362 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
363 (ins f128mem:$dst, VR128:$src),
364 "movupd\t{$src, $dst|$dst, $src}",
365 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
367 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
368 "movups\t{$src, $dst|$dst, $src}",
369 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
370 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
371 "movupd\t{$src, $dst|$dst, $src}",
372 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
374 // Move Low/High packed floating point values
375 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
376 PatFrag mov_frag, string base_opc,
378 def PSrm : PI<opc, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
380 !strconcat(base_opc, "s", asm_opr),
383 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
384 SSEPackedSingle>, TB;
386 def PDrm : PI<opc, MRMSrcMem,
387 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
388 !strconcat(base_opc, "d", asm_opr),
389 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
390 (scalar_to_vector (loadf64 addr:$src2)))))],
391 SSEPackedDouble>, TB, OpSize;
394 let AddedComplexity = 20 in {
395 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
397 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
400 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
401 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
402 "\t{$src2, $dst|$dst, $src2}">;
403 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
404 "\t{$src2, $dst|$dst, $src2}">;
407 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
408 "movlps\t{$src, $dst|$dst, $src}",
409 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
410 (iPTR 0))), addr:$dst)]>, VEX;
411 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
412 "movlpd\t{$src, $dst|$dst, $src}",
413 [(store (f64 (vector_extract (v2f64 VR128:$src),
414 (iPTR 0))), addr:$dst)]>, VEX;
415 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
416 "movlps\t{$src, $dst|$dst, $src}",
417 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
418 (iPTR 0))), addr:$dst)]>;
419 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
420 "movlpd\t{$src, $dst|$dst, $src}",
421 [(store (f64 (vector_extract (v2f64 VR128:$src),
422 (iPTR 0))), addr:$dst)]>;
424 // v2f64 extract element 1 is always custom lowered to unpack high to low
425 // and extract element 0 so the non-store version isn't too horrible.
426 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhps\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
430 (undef)), (iPTR 0))), addr:$dst)]>,
432 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
433 "movhpd\t{$src, $dst|$dst, $src}",
434 [(store (f64 (vector_extract
435 (v2f64 (unpckh VR128:$src, (undef))),
436 (iPTR 0))), addr:$dst)]>,
438 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhps\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
442 (undef)), (iPTR 0))), addr:$dst)]>;
443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movhpd\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract
446 (v2f64 (unpckh VR128:$src, (undef))),
447 (iPTR 0))), addr:$dst)]>;
449 let AddedComplexity = 20 in {
450 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
451 (ins VR128:$src1, VR128:$src2),
452 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
454 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
456 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
457 (ins VR128:$src1, VR128:$src2),
458 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
463 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
464 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movlhps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
469 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
470 (ins VR128:$src1, VR128:$src2),
471 "movhlps\t{$src2, $dst|$dst, $src2}",
473 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
476 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
477 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
478 let AddedComplexity = 20 in {
479 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
480 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
481 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
482 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
485 //===----------------------------------------------------------------------===//
486 // SSE 1 & 2 - Conversion Instructions
487 //===----------------------------------------------------------------------===//
489 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
490 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
493 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
495 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
498 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
499 X86MemOperand x86memop, string asm> {
500 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
502 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
506 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
507 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
508 string asm, Domain d> {
509 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
510 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
511 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
512 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
515 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
516 X86MemOperand x86memop, string asm> {
517 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
520 (ins DstRC:$src1, x86memop:$src),
521 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
525 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
526 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
527 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
529 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
530 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
531 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
532 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
535 // The assembler can recognize rr 64-bit instructions by seeing a rxx
536 // register, but the same isn't true when only using memory operands,
537 // provide other assembly "l" and "q" forms to address this explicitly
538 // where appropriate to do so.
539 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
541 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
543 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
545 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
547 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
550 let Predicates = [HasAVX] in {
551 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
552 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
553 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
554 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
555 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
556 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
557 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
558 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
560 def : Pat<(f32 (sint_to_fp GR32:$src)),
561 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
562 def : Pat<(f32 (sint_to_fp GR64:$src)),
563 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
564 def : Pat<(f64 (sint_to_fp GR32:$src)),
565 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
566 def : Pat<(f64 (sint_to_fp GR64:$src)),
567 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
570 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
571 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
572 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
573 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
574 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
575 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
576 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
577 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
578 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
579 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
580 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
581 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
582 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
583 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
584 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
585 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
587 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
588 // and/or XMM operand(s).
590 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
591 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
594 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
595 [(set DstRC:$dst, (Int SrcRC:$src))]>;
596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
601 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
602 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
603 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
606 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
607 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
608 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
609 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
610 (ins DstRC:$src1, x86memop:$src2),
612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
614 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
617 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
618 f128mem, load, "cvtsd2si">, XD, VEX;
619 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
620 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
623 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
624 // Get rid of this hack or rename the intrinsics, there are several
625 // intructions that only match with the intrinsic form, why create duplicates
626 // to let them be recognized by the assembler?
627 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
628 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
629 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
630 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
631 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
632 f128mem, load, "cvtsd2si{l}">, XD;
633 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
634 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
637 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
638 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
642 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
643 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
644 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
645 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
648 let Constraints = "$src1 = $dst" in {
649 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
650 int_x86_sse_cvtsi2ss, i32mem, loadi32,
652 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
653 int_x86_sse_cvtsi642ss, i64mem, loadi64,
654 "cvtsi2ss{q}">, XS, REX_W;
655 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
656 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
658 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
659 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
660 "cvtsi2sd">, XD, REX_W;
665 // Aliases for intrinsics
666 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
667 f32mem, load, "cvttss2si">, XS, VEX;
668 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
669 int_x86_sse_cvttss2si64, f32mem, load,
670 "cvttss2si">, XS, VEX, VEX_W;
671 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
672 f128mem, load, "cvttsd2si">, XD, VEX;
673 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
674 int_x86_sse2_cvttsd2si64, f128mem, load,
675 "cvttsd2si">, XD, VEX, VEX_W;
676 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
677 f32mem, load, "cvttss2si">, XS;
678 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
679 int_x86_sse_cvttss2si64, f32mem, load,
680 "cvttss2si{q}">, XS, REX_W;
681 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
682 f128mem, load, "cvttsd2si">, XD;
683 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
684 int_x86_sse2_cvttsd2si64, f128mem, load,
685 "cvttsd2si{q}">, XD, REX_W;
687 let Pattern = []<dag> in {
688 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
689 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
690 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
691 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
693 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
694 "cvtdq2ps\t{$src, $dst|$dst, $src}",
695 SSEPackedSingle>, TB, VEX;
696 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
697 "cvtdq2ps\t{$src, $dst|$dst, $src}",
698 SSEPackedSingle>, TB, VEX;
701 let Pattern = []<dag> in {
702 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
703 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
704 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
705 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
706 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
707 "cvtdq2ps\t{$src, $dst|$dst, $src}",
708 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
711 let Predicates = [HasSSE1] in {
712 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
713 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
714 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
715 (CVTSS2SIrm addr:$src)>;
716 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
717 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
718 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
719 (CVTSS2SI64rm addr:$src)>;
722 let Predicates = [HasAVX] in {
723 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
724 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
725 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
726 (VCVTSS2SIrm addr:$src)>;
727 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
728 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
729 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
730 (VCVTSS2SI64rm addr:$src)>;
735 // Convert scalar double to scalar single
736 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
737 (ins FR64:$src1, FR64:$src2),
738 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
740 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
741 (ins FR64:$src1, f64mem:$src2),
742 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
744 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
747 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
748 "cvtsd2ss\t{$src, $dst|$dst, $src}",
749 [(set FR32:$dst, (fround FR64:$src))]>;
750 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
751 "cvtsd2ss\t{$src, $dst|$dst, $src}",
752 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
753 Requires<[HasSSE2, OptForSize]>;
755 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
756 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
758 let Constraints = "$src1 = $dst" in
759 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
760 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
762 // Convert scalar single to scalar double
763 // SSE2 instructions with XS prefix
764 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
765 (ins FR32:$src1, FR32:$src2),
766 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
767 []>, XS, Requires<[HasAVX]>, VEX_4V;
768 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
769 (ins FR32:$src1, f32mem:$src2),
770 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
771 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
773 let Predicates = [HasAVX] in {
774 def : Pat<(f64 (fextend FR32:$src)),
775 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
776 def : Pat<(fextend (loadf32 addr:$src)),
777 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
778 def : Pat<(extloadf32 addr:$src),
779 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
782 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
783 "cvtss2sd\t{$src, $dst|$dst, $src}",
784 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
786 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
787 "cvtss2sd\t{$src, $dst|$dst, $src}",
788 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
789 Requires<[HasSSE2, OptForSize]>;
791 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
792 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
793 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
794 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
795 VR128:$src2))]>, XS, VEX_4V,
797 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
798 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
799 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
801 (load addr:$src2)))]>, XS, VEX_4V,
803 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
804 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
806 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
807 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
810 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
811 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
812 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
813 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
814 (load addr:$src2)))]>, XS,
818 def : Pat<(extloadf32 addr:$src),
819 (CVTSS2SDrr (MOVSSrm addr:$src))>,
820 Requires<[HasSSE2, OptForSpeed]>;
822 // Convert doubleword to packed single/double fp
823 // SSE2 instructions without OpSize prefix
824 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
825 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
826 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
827 TB, VEX, Requires<[HasAVX]>;
828 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
829 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
830 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
831 (bitconvert (memopv2i64 addr:$src))))]>,
832 TB, VEX, Requires<[HasAVX]>;
833 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
834 "cvtdq2ps\t{$src, $dst|$dst, $src}",
835 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
836 TB, Requires<[HasSSE2]>;
837 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
838 "cvtdq2ps\t{$src, $dst|$dst, $src}",
839 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
840 (bitconvert (memopv2i64 addr:$src))))]>,
841 TB, Requires<[HasSSE2]>;
843 // FIXME: why the non-intrinsic version is described as SSE3?
844 // SSE2 instructions with XS prefix
845 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
846 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
847 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
848 XS, VEX, Requires<[HasAVX]>;
849 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
850 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
851 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
852 (bitconvert (memopv2i64 addr:$src))))]>,
853 XS, VEX, Requires<[HasAVX]>;
854 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
855 "cvtdq2pd\t{$src, $dst|$dst, $src}",
856 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
857 XS, Requires<[HasSSE2]>;
858 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
859 "cvtdq2pd\t{$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
861 (bitconvert (memopv2i64 addr:$src))))]>,
862 XS, Requires<[HasSSE2]>;
865 // Convert packed single/double fp to doubleword
866 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
867 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
868 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
869 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
870 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
871 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
873 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
875 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
876 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
877 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
879 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
880 "cvtps2dq\t{$src, $dst|$dst, $src}",
881 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
883 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
885 "cvtps2dq\t{$src, $dst|$dst, $src}",
886 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
887 (memop addr:$src)))]>, VEX;
888 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
889 "cvtps2dq\t{$src, $dst|$dst, $src}",
890 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
891 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
892 "cvtps2dq\t{$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
894 (memop addr:$src)))]>;
896 // SSE2 packed instructions with XD prefix
897 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
898 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
900 XD, VEX, Requires<[HasAVX]>;
901 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
904 (memop addr:$src)))]>,
905 XD, VEX, Requires<[HasAVX]>;
906 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
907 "cvtpd2dq\t{$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
909 XD, Requires<[HasSSE2]>;
910 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 "cvtpd2dq\t{$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
913 (memop addr:$src)))]>,
914 XD, Requires<[HasSSE2]>;
917 // Convert with truncation packed single/double fp to doubleword
918 // SSE2 packed instructions with XS prefix
919 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
920 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
921 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
922 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
923 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
924 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
925 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
926 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
927 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "cvttps2dq\t{$src, $dst|$dst, $src}",
930 (int_x86_sse2_cvttps2dq VR128:$src))]>;
931 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
932 "cvttps2dq\t{$src, $dst|$dst, $src}",
934 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
936 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "vcvttps2dq\t{$src, $dst|$dst, $src}",
939 (int_x86_sse2_cvttps2dq VR128:$src))]>,
940 XS, VEX, Requires<[HasAVX]>;
941 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
942 "vcvttps2dq\t{$src, $dst|$dst, $src}",
943 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
944 (memop addr:$src)))]>,
945 XS, VEX, Requires<[HasAVX]>;
947 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
948 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
949 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
950 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
952 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
953 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
954 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
955 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
956 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
957 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
958 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
959 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
961 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
963 "cvttpd2dq\t{$src, $dst|$dst, $src}",
964 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
966 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
968 "cvttpd2dq\t{$src, $dst|$dst, $src}",
969 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
970 (memop addr:$src)))]>, VEX;
971 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
972 "cvttpd2dq\t{$src, $dst|$dst, $src}",
973 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
974 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
975 "cvttpd2dq\t{$src, $dst|$dst, $src}",
976 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
977 (memop addr:$src)))]>;
979 // The assembler can recognize rr 256-bit instructions by seeing a ymm
980 // register, but the same isn't true when using memory operands instead.
981 // Provide other assembly rr and rm forms to address this explicitly.
982 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
983 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
984 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
985 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
988 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
989 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
990 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
991 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
994 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
995 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
996 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
997 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
999 // Convert packed single to packed double
1000 let Predicates = [HasAVX] in {
1001 // SSE2 instructions without OpSize prefix
1002 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1003 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1004 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1005 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1006 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1007 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1008 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1009 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1011 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1012 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1013 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1014 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1016 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1017 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1018 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1019 VEX, Requires<[HasAVX]>;
1020 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1021 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1022 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1023 (load addr:$src)))]>,
1024 VEX, Requires<[HasAVX]>;
1025 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1026 "cvtps2pd\t{$src, $dst|$dst, $src}",
1027 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1028 TB, Requires<[HasSSE2]>;
1029 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1030 "cvtps2pd\t{$src, $dst|$dst, $src}",
1031 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1032 (load addr:$src)))]>,
1033 TB, Requires<[HasSSE2]>;
1035 // Convert packed double to packed single
1036 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1037 // register, but the same isn't true when using memory operands instead.
1038 // Provide other assembly rr and rm forms to address this explicitly.
1039 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1040 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1041 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1042 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1045 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1046 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1047 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1048 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1051 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1052 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1053 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1054 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1055 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1056 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1057 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1058 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1061 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1062 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1063 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1064 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1066 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1067 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1068 (memop addr:$src)))]>;
1069 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1070 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1071 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1072 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1073 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1074 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1075 (memop addr:$src)))]>;
1077 // AVX 256-bit register conversion intrinsics
1078 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1079 // whenever possible to avoid declaring two versions of each one.
1080 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1081 (VCVTDQ2PSYrr VR256:$src)>;
1082 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1083 (VCVTDQ2PSYrm addr:$src)>;
1085 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1086 (VCVTPD2PSYrr VR256:$src)>;
1087 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1088 (VCVTPD2PSYrm addr:$src)>;
1090 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1091 (VCVTPS2DQYrr VR256:$src)>;
1092 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1093 (VCVTPS2DQYrm addr:$src)>;
1095 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1096 (VCVTPS2PDYrr VR128:$src)>;
1097 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1098 (VCVTPS2PDYrm addr:$src)>;
1100 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1101 (VCVTTPD2DQYrr VR256:$src)>;
1102 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1103 (VCVTTPD2DQYrm addr:$src)>;
1105 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1106 (VCVTTPS2DQYrr VR256:$src)>;
1107 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1108 (VCVTTPS2DQYrm addr:$src)>;
1110 // Match fround and fextend for 128/256-bit conversions
1111 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1112 (VCVTPD2PSYrr VR256:$src)>;
1113 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1114 (VCVTPD2PSYrm addr:$src)>;
1116 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1117 (VCVTPS2PDYrr VR128:$src)>;
1118 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1119 (VCVTPS2PDYrm addr:$src)>;
1121 //===----------------------------------------------------------------------===//
1122 // SSE 1 & 2 - Compare Instructions
1123 //===----------------------------------------------------------------------===//
1125 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1126 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1127 string asm, string asm_alt> {
1128 let isAsmParserOnly = 1 in {
1129 def rr : SIi8<0xC2, MRMSrcReg,
1130 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1133 def rm : SIi8<0xC2, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1138 // Accept explicit immediate argument form instead of comparison code.
1139 def rr_alt : SIi8<0xC2, MRMSrcReg,
1140 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1143 def rm_alt : SIi8<0xC2, MRMSrcMem,
1144 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1148 let neverHasSideEffects = 1 in {
1149 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1150 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1151 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1153 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1154 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1155 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1159 let Constraints = "$src1 = $dst" in {
1160 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1161 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1162 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1163 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1164 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1165 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1166 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1167 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1168 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1169 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1170 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1171 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1172 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1173 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1174 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1175 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1177 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1178 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1179 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1180 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1181 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1182 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1183 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1184 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1185 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1186 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1187 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1188 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1189 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1192 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1193 Intrinsic Int, string asm> {
1194 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1195 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1196 [(set VR128:$dst, (Int VR128:$src1,
1197 VR128:$src, imm:$cc))]>;
1198 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1199 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1200 [(set VR128:$dst, (Int VR128:$src1,
1201 (load addr:$src), imm:$cc))]>;
1204 // Aliases to match intrinsics which expect XMM operand(s).
1205 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1206 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1208 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1209 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1211 let Constraints = "$src1 = $dst" in {
1212 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1213 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1214 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1215 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1219 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1220 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1221 ValueType vt, X86MemOperand x86memop,
1222 PatFrag ld_frag, string OpcodeStr, Domain d> {
1223 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1224 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1225 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1226 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1227 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1228 [(set EFLAGS, (OpNode (vt RC:$src1),
1229 (ld_frag addr:$src2)))], d>;
1232 let Defs = [EFLAGS] in {
1233 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1234 "ucomiss", SSEPackedSingle>, VEX;
1235 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1236 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1237 let Pattern = []<dag> in {
1238 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1239 "comiss", SSEPackedSingle>, VEX;
1240 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1241 "comisd", SSEPackedDouble>, OpSize, VEX;
1244 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1245 load, "ucomiss", SSEPackedSingle>, VEX;
1246 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1247 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1249 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1250 load, "comiss", SSEPackedSingle>, VEX;
1251 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1252 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1253 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1254 "ucomiss", SSEPackedSingle>, TB;
1255 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1256 "ucomisd", SSEPackedDouble>, TB, OpSize;
1258 let Pattern = []<dag> in {
1259 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1260 "comiss", SSEPackedSingle>, TB;
1261 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1262 "comisd", SSEPackedDouble>, TB, OpSize;
1265 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1266 load, "ucomiss", SSEPackedSingle>, TB;
1267 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1268 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1270 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1271 "comiss", SSEPackedSingle>, TB;
1272 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1273 "comisd", SSEPackedDouble>, TB, OpSize;
1274 } // Defs = [EFLAGS]
1276 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1277 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1278 Intrinsic Int, string asm, string asm_alt,
1280 let isAsmParserOnly = 1 in {
1281 def rri : PIi8<0xC2, MRMSrcReg,
1282 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1283 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1284 def rmi : PIi8<0xC2, MRMSrcMem,
1285 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1286 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1289 // Accept explicit immediate argument form instead of comparison code.
1290 def rri_alt : PIi8<0xC2, MRMSrcReg,
1291 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1293 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1294 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1298 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1299 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1300 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1301 SSEPackedSingle>, VEX_4V;
1302 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1303 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1304 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1305 SSEPackedDouble>, OpSize, VEX_4V;
1306 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1307 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1308 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1309 SSEPackedSingle>, VEX_4V;
1310 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1311 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1312 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1313 SSEPackedDouble>, OpSize, VEX_4V;
1314 let Constraints = "$src1 = $dst" in {
1315 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1316 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1317 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1318 SSEPackedSingle>, TB;
1319 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1320 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1321 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1322 SSEPackedDouble>, TB, OpSize;
1325 let Predicates = [HasSSE1] in {
1326 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1327 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1328 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1329 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1332 let Predicates = [HasSSE2] in {
1333 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1334 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1335 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1336 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1339 let Predicates = [HasAVX] in {
1340 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1341 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1342 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1343 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1344 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1345 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1346 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1347 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1349 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1350 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1351 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1352 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1353 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1354 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1355 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1356 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1359 //===----------------------------------------------------------------------===//
1360 // SSE 1 & 2 - Shuffle Instructions
1361 //===----------------------------------------------------------------------===//
1363 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1364 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1365 ValueType vt, string asm, PatFrag mem_frag,
1366 Domain d, bit IsConvertibleToThreeAddress = 0> {
1367 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1368 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1369 [(set RC:$dst, (vt (shufp:$src3
1370 RC:$src1, (mem_frag addr:$src2))))], d>;
1371 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1372 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1373 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1375 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1378 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1379 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1380 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1381 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1382 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1383 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1384 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1385 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1386 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1387 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1388 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1389 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1391 let Constraints = "$src1 = $dst" in {
1392 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1393 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1394 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1396 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1397 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1398 memopv2f64, SSEPackedDouble>, TB, OpSize;
1401 //===----------------------------------------------------------------------===//
1402 // SSE 1 & 2 - Unpack Instructions
1403 //===----------------------------------------------------------------------===//
1405 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1406 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1407 PatFrag mem_frag, RegisterClass RC,
1408 X86MemOperand x86memop, string asm,
1410 def rr : PI<opc, MRMSrcReg,
1411 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1413 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1414 def rm : PI<opc, MRMSrcMem,
1415 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1417 (vt (OpNode RC:$src1,
1418 (mem_frag addr:$src2))))], d>;
1421 let AddedComplexity = 10 in {
1422 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1423 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1424 SSEPackedSingle>, VEX_4V;
1425 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1426 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1427 SSEPackedDouble>, OpSize, VEX_4V;
1428 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1429 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1430 SSEPackedSingle>, VEX_4V;
1431 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1432 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1433 SSEPackedDouble>, OpSize, VEX_4V;
1435 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1436 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1437 SSEPackedSingle>, VEX_4V;
1438 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1439 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1440 SSEPackedDouble>, OpSize, VEX_4V;
1441 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1442 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1443 SSEPackedSingle>, VEX_4V;
1444 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1445 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1446 SSEPackedDouble>, OpSize, VEX_4V;
1448 let Constraints = "$src1 = $dst" in {
1449 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1450 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1451 SSEPackedSingle>, TB;
1452 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1453 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1454 SSEPackedDouble>, TB, OpSize;
1455 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1456 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1457 SSEPackedSingle>, TB;
1458 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1459 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1460 SSEPackedDouble>, TB, OpSize;
1461 } // Constraints = "$src1 = $dst"
1462 } // AddedComplexity
1464 //===----------------------------------------------------------------------===//
1465 // SSE 1 & 2 - Extract Floating-Point Sign mask
1466 //===----------------------------------------------------------------------===//
1468 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1469 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1471 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1472 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1473 [(set GR32:$dst, (Int RC:$src))], d>;
1474 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1475 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1478 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1479 SSEPackedSingle>, TB;
1480 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1481 SSEPackedDouble>, TB, OpSize;
1483 def : Pat<(i32 (X86fgetsign FR32:$src)),
1484 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1485 sub_ss))>, Requires<[HasSSE1]>;
1486 def : Pat<(i64 (X86fgetsign FR32:$src)),
1487 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1488 sub_ss))>, Requires<[HasSSE1]>;
1489 def : Pat<(i32 (X86fgetsign FR64:$src)),
1490 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1491 sub_sd))>, Requires<[HasSSE2]>;
1492 def : Pat<(i64 (X86fgetsign FR64:$src)),
1493 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1494 sub_sd))>, Requires<[HasSSE2]>;
1496 let Predicates = [HasAVX] in {
1497 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1498 "movmskps", SSEPackedSingle>, TB, VEX;
1499 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1500 "movmskpd", SSEPackedDouble>, TB, OpSize,
1502 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1503 "movmskps", SSEPackedSingle>, TB, VEX;
1504 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1505 "movmskpd", SSEPackedDouble>, TB, OpSize,
1508 def : Pat<(i32 (X86fgetsign FR32:$src)),
1509 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1511 def : Pat<(i64 (X86fgetsign FR32:$src)),
1512 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1514 def : Pat<(i32 (X86fgetsign FR64:$src)),
1515 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1517 def : Pat<(i64 (X86fgetsign FR64:$src)),
1518 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1522 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1523 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1524 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1525 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1527 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1528 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1529 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1530 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1534 //===----------------------------------------------------------------------===//
1535 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1536 //===----------------------------------------------------------------------===//
1538 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1539 // names that start with 'Fs'.
1541 // Alias instructions that map fld0 to pxor for sse.
1542 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1543 canFoldAsLoad = 1 in {
1544 // FIXME: Set encoding to pseudo!
1545 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1546 [(set FR32:$dst, fp32imm0)]>,
1547 Requires<[HasSSE1]>, TB, OpSize;
1548 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1549 [(set FR64:$dst, fpimm0)]>,
1550 Requires<[HasSSE2]>, TB, OpSize;
1551 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1552 [(set FR32:$dst, fp32imm0)]>,
1553 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1554 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1555 [(set FR64:$dst, fpimm0)]>,
1556 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1559 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1560 // bits are disregarded.
1561 let neverHasSideEffects = 1 in {
1562 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1563 "movaps\t{$src, $dst|$dst, $src}", []>;
1564 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1565 "movapd\t{$src, $dst|$dst, $src}", []>;
1568 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1569 // bits are disregarded.
1570 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1571 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1572 "movaps\t{$src, $dst|$dst, $src}",
1573 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1574 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1575 "movapd\t{$src, $dst|$dst, $src}",
1576 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1579 //===----------------------------------------------------------------------===//
1580 // SSE 1 & 2 - Logical Instructions
1581 //===----------------------------------------------------------------------===//
1583 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1585 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1587 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1588 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1590 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1591 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1593 let Constraints = "$src1 = $dst" in {
1594 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1595 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1597 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1598 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1602 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1603 let mayLoad = 0 in {
1604 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1605 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1606 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1609 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1610 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1612 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1614 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1616 let Pattern = []<dag> in {
1617 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1618 !strconcat(OpcodeStr, "ps"), f128mem,
1619 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1620 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1621 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1623 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1624 !strconcat(OpcodeStr, "pd"), f128mem,
1625 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1626 (bc_v2i64 (v2f64 VR128:$src2))))],
1627 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1628 (memopv2i64 addr:$src2)))], 0>,
1631 let Constraints = "$src1 = $dst" in {
1632 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1633 !strconcat(OpcodeStr, "ps"), f128mem,
1634 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1635 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1636 (memopv2i64 addr:$src2)))]>, TB;
1638 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1639 !strconcat(OpcodeStr, "pd"), f128mem,
1640 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1641 (bc_v2i64 (v2f64 VR128:$src2))))],
1642 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1643 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1647 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1649 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1651 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1652 !strconcat(OpcodeStr, "ps"), f256mem,
1653 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1654 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1655 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1657 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1658 !strconcat(OpcodeStr, "pd"), f256mem,
1659 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1660 (bc_v4i64 (v4f64 VR256:$src2))))],
1661 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1662 (memopv4i64 addr:$src2)))], 0>,
1666 // AVX 256-bit packed logical ops forms
1667 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1668 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1669 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1670 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1672 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1673 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1674 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1675 let isCommutable = 0 in
1676 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1678 //===----------------------------------------------------------------------===//
1679 // SSE 1 & 2 - Arithmetic Instructions
1680 //===----------------------------------------------------------------------===//
1682 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1685 /// In addition, we also have a special variant of the scalar form here to
1686 /// represent the associated intrinsic operation. This form is unlike the
1687 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1688 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1690 /// These three forms can each be reg+reg or reg+mem.
1693 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1695 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1697 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1698 OpNode, FR32, f32mem, Is2Addr>, XS;
1699 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1700 OpNode, FR64, f64mem, Is2Addr>, XD;
1703 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1705 let mayLoad = 0 in {
1706 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1707 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1708 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1709 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1713 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1715 let mayLoad = 0 in {
1716 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1717 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1718 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1719 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1723 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1725 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1726 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1727 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1728 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1731 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1733 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1734 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1735 SSEPackedSingle, Is2Addr>, TB;
1737 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1738 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1739 SSEPackedDouble, Is2Addr>, TB, OpSize;
1742 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1743 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1744 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1745 SSEPackedSingle, 0>, TB;
1747 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1748 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1749 SSEPackedDouble, 0>, TB, OpSize;
1752 // Binary Arithmetic instructions
1753 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1754 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1755 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1756 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1757 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1758 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1759 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1760 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1762 let isCommutable = 0 in {
1763 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1764 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1765 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1766 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1767 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1768 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1769 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1770 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1771 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1772 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1773 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1774 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1775 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1776 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1777 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1778 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1779 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1780 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1781 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1782 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1785 let Constraints = "$src1 = $dst" in {
1786 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1787 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1788 basic_sse12_fp_binop_s_int<0x58, "add">;
1789 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1790 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1791 basic_sse12_fp_binop_s_int<0x59, "mul">;
1793 let isCommutable = 0 in {
1794 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1795 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1796 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1797 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1798 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1799 basic_sse12_fp_binop_s_int<0x5E, "div">;
1800 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1801 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1802 basic_sse12_fp_binop_s_int<0x5F, "max">,
1803 basic_sse12_fp_binop_p_int<0x5F, "max">;
1804 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1805 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1806 basic_sse12_fp_binop_s_int<0x5D, "min">,
1807 basic_sse12_fp_binop_p_int<0x5D, "min">;
1812 /// In addition, we also have a special variant of the scalar form here to
1813 /// represent the associated intrinsic operation. This form is unlike the
1814 /// plain scalar form, in that it takes an entire vector (instead of a
1815 /// scalar) and leaves the top elements undefined.
1817 /// And, we have a special variant form for a full-vector intrinsic form.
1819 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1820 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1821 SDNode OpNode, Intrinsic F32Int> {
1822 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1823 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1824 [(set FR32:$dst, (OpNode FR32:$src))]>;
1825 // For scalar unary operations, fold a load into the operation
1826 // only in OptForSize mode. It eliminates an instruction, but it also
1827 // eliminates a whole-register clobber (the load), so it introduces a
1828 // partial register update condition.
1829 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1830 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1831 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1832 Requires<[HasSSE1, OptForSize]>;
1833 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1834 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1835 [(set VR128:$dst, (F32Int VR128:$src))]>;
1836 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1837 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1838 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1841 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1842 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1843 SDNode OpNode, Intrinsic F32Int> {
1844 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1845 !strconcat(OpcodeStr,
1846 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1847 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1848 !strconcat(OpcodeStr,
1849 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1850 []>, XS, Requires<[HasAVX, OptForSize]>;
1851 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 !strconcat(OpcodeStr,
1853 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1854 [(set VR128:$dst, (F32Int VR128:$src))]>;
1855 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1856 !strconcat(OpcodeStr,
1857 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1858 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1861 /// sse1_fp_unop_p - SSE1 unops in packed form.
1862 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1863 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1865 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1866 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1868 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1871 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1872 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1873 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1874 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1875 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1876 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1877 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1878 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1881 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1882 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1883 Intrinsic V4F32Int> {
1884 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1887 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1888 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1889 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1892 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1893 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1894 Intrinsic V4F32Int> {
1895 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1896 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1897 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1898 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1900 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1903 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1904 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1905 SDNode OpNode, Intrinsic F64Int> {
1906 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1907 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1908 [(set FR64:$dst, (OpNode FR64:$src))]>;
1909 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1910 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1911 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1912 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1913 Requires<[HasSSE2, OptForSize]>;
1914 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1915 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1916 [(set VR128:$dst, (F64Int VR128:$src))]>;
1917 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1918 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1919 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1922 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1923 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1924 SDNode OpNode, Intrinsic F64Int> {
1925 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1926 !strconcat(OpcodeStr,
1927 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1928 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1929 (ins FR64:$src1, f64mem:$src2),
1930 !strconcat(OpcodeStr,
1931 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1932 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1933 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1934 [(set VR128:$dst, (F64Int VR128:$src))]>;
1935 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1936 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1937 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1940 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1941 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1943 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1944 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1945 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1946 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1947 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1948 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1951 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1952 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1953 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1954 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1955 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1956 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1957 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1958 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1961 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1962 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1963 Intrinsic V2F64Int> {
1964 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1965 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1966 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1967 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1968 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1969 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1972 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1973 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1974 Intrinsic V2F64Int> {
1975 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1976 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1977 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1978 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1979 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1980 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1983 let Predicates = [HasAVX] in {
1985 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1986 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1989 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1990 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1991 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1992 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1993 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1994 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1995 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1996 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1999 // Reciprocal approximations. Note that these typically require refinement
2000 // in order to obtain suitable precision.
2001 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
2002 int_x86_sse_rsqrt_ss>, VEX_4V;
2003 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2004 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2005 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2006 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2008 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
2010 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2011 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2012 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2013 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2016 def : Pat<(f32 (fsqrt FR32:$src)),
2017 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2018 def : Pat<(f64 (fsqrt FR64:$src)),
2019 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2020 def : Pat<(f64 (fsqrt (load addr:$src))),
2021 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2022 Requires<[HasAVX, OptForSize]>;
2023 def : Pat<(f32 (fsqrt (load addr:$src))),
2024 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2025 Requires<[HasAVX, OptForSize]>;
2028 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2029 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2030 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2031 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2032 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2033 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2035 // Reciprocal approximations. Note that these typically require refinement
2036 // in order to obtain suitable precision.
2037 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2038 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2039 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2040 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2041 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2042 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2044 // There is no f64 version of the reciprocal approximation instructions.
2046 //===----------------------------------------------------------------------===//
2047 // SSE 1 & 2 - Non-temporal stores
2048 //===----------------------------------------------------------------------===//
2050 let AddedComplexity = 400 in { // Prefer non-temporal versions
2051 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2052 (ins f128mem:$dst, VR128:$src),
2053 "movntps\t{$src, $dst|$dst, $src}",
2054 [(alignednontemporalstore (v4f32 VR128:$src),
2056 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2057 (ins f128mem:$dst, VR128:$src),
2058 "movntpd\t{$src, $dst|$dst, $src}",
2059 [(alignednontemporalstore (v2f64 VR128:$src),
2061 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2062 (ins f128mem:$dst, VR128:$src),
2063 "movntdq\t{$src, $dst|$dst, $src}",
2064 [(alignednontemporalstore (v2f64 VR128:$src),
2067 let ExeDomain = SSEPackedInt in
2068 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2069 (ins f128mem:$dst, VR128:$src),
2070 "movntdq\t{$src, $dst|$dst, $src}",
2071 [(alignednontemporalstore (v4f32 VR128:$src),
2074 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2075 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2077 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2078 (ins f256mem:$dst, VR256:$src),
2079 "movntps\t{$src, $dst|$dst, $src}",
2080 [(alignednontemporalstore (v8f32 VR256:$src),
2082 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2083 (ins f256mem:$dst, VR256:$src),
2084 "movntpd\t{$src, $dst|$dst, $src}",
2085 [(alignednontemporalstore (v4f64 VR256:$src),
2087 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2088 (ins f256mem:$dst, VR256:$src),
2089 "movntdq\t{$src, $dst|$dst, $src}",
2090 [(alignednontemporalstore (v4f64 VR256:$src),
2092 let ExeDomain = SSEPackedInt in
2093 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2094 (ins f256mem:$dst, VR256:$src),
2095 "movntdq\t{$src, $dst|$dst, $src}",
2096 [(alignednontemporalstore (v8f32 VR256:$src),
2100 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2101 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2102 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2103 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2104 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2105 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2107 let AddedComplexity = 400 in { // Prefer non-temporal versions
2108 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2109 "movntps\t{$src, $dst|$dst, $src}",
2110 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2111 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2112 "movntpd\t{$src, $dst|$dst, $src}",
2113 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2115 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2116 "movntdq\t{$src, $dst|$dst, $src}",
2117 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2119 let ExeDomain = SSEPackedInt in
2120 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2121 "movntdq\t{$src, $dst|$dst, $src}",
2122 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2124 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2125 (MOVNTDQmr addr:$dst, VR128:$src)>;
2127 // There is no AVX form for instructions below this point
2128 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2129 "movnti{l}\t{$src, $dst|$dst, $src}",
2130 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2131 TB, Requires<[HasSSE2]>;
2132 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2133 "movnti{q}\t{$src, $dst|$dst, $src}",
2134 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2135 TB, Requires<[HasSSE2]>;
2138 //===----------------------------------------------------------------------===//
2139 // SSE 1 & 2 - Misc Instructions (No AVX form)
2140 //===----------------------------------------------------------------------===//
2142 // Prefetch intrinsic.
2143 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2144 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2145 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2146 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2147 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2148 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2149 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2150 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2152 // Load, store, and memory fence
2153 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2154 TB, Requires<[HasSSE1]>;
2155 def : Pat<(X86SFence), (SFENCE)>;
2157 // Alias instructions that map zero vector to pxor / xorp* for sse.
2158 // We set canFoldAsLoad because this can be converted to a constant-pool
2159 // load of an all-zeros value if folding it would be beneficial.
2160 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2161 // JIT implementation, it does not expand the instructions below like
2162 // X86MCInstLower does.
2163 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2164 isCodeGenOnly = 1 in {
2165 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2166 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2167 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2168 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2169 let ExeDomain = SSEPackedInt in
2170 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2171 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2174 // The same as done above but for AVX. The 128-bit versions are the
2175 // same, but re-encoded. The 256-bit does not support PI version, and
2176 // doesn't need it because on sandy bridge the register is set to zero
2177 // at the rename stage without using any execution unit, so SET0PSY
2178 // and SET0PDY can be used for vector int instructions without penalty
2179 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2180 // JIT implementatioan, it does not expand the instructions below like
2181 // X86MCInstLower does.
2182 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2183 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2184 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2185 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2186 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2187 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2188 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2189 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2190 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2191 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2192 let ExeDomain = SSEPackedInt in
2193 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2194 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2197 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2198 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2199 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2201 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2202 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2204 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2205 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2206 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2207 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2208 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2210 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2211 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2212 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2214 //===----------------------------------------------------------------------===//
2215 // SSE 1 & 2 - Load/Store XCSR register
2216 //===----------------------------------------------------------------------===//
2218 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2219 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2220 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2221 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2223 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2224 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2225 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2226 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2228 //===---------------------------------------------------------------------===//
2229 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2230 //===---------------------------------------------------------------------===//
2232 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2234 let neverHasSideEffects = 1 in {
2235 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2236 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2237 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2238 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2240 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2241 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2242 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2243 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2245 let canFoldAsLoad = 1, mayLoad = 1 in {
2246 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2247 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2248 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2249 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2250 let Predicates = [HasAVX] in {
2251 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2252 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2253 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2254 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2258 let mayStore = 1 in {
2259 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2260 (ins i128mem:$dst, VR128:$src),
2261 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2262 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2263 (ins i256mem:$dst, VR256:$src),
2264 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2265 let Predicates = [HasAVX] in {
2266 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2267 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2268 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2269 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2273 let neverHasSideEffects = 1 in
2274 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2275 "movdqa\t{$src, $dst|$dst, $src}", []>;
2277 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2278 "movdqu\t{$src, $dst|$dst, $src}",
2279 []>, XS, Requires<[HasSSE2]>;
2281 let canFoldAsLoad = 1, mayLoad = 1 in {
2282 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2283 "movdqa\t{$src, $dst|$dst, $src}",
2284 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2285 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2286 "movdqu\t{$src, $dst|$dst, $src}",
2287 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2288 XS, Requires<[HasSSE2]>;
2291 let mayStore = 1 in {
2292 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2293 "movdqa\t{$src, $dst|$dst, $src}",
2294 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2295 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2296 "movdqu\t{$src, $dst|$dst, $src}",
2297 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2298 XS, Requires<[HasSSE2]>;
2301 // Intrinsic forms of MOVDQU load and store
2302 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2303 "vmovdqu\t{$src, $dst|$dst, $src}",
2304 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2305 XS, VEX, Requires<[HasAVX]>;
2307 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2308 "movdqu\t{$src, $dst|$dst, $src}",
2309 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2310 XS, Requires<[HasSSE2]>;
2312 } // ExeDomain = SSEPackedInt
2314 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2315 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2316 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2318 //===---------------------------------------------------------------------===//
2319 // SSE2 - Packed Integer Arithmetic Instructions
2320 //===---------------------------------------------------------------------===//
2322 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2324 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2325 bit IsCommutable = 0, bit Is2Addr = 1> {
2326 let isCommutable = IsCommutable in
2327 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src2),
2330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2332 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2333 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, i128mem:$src2),
2336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2338 [(set VR128:$dst, (IntId VR128:$src1,
2339 (bitconvert (memopv2i64 addr:$src2))))]>;
2342 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2343 string OpcodeStr, Intrinsic IntId,
2344 Intrinsic IntId2, bit Is2Addr = 1> {
2345 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2346 (ins VR128:$src1, VR128:$src2),
2348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2350 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2351 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2352 (ins VR128:$src1, i128mem:$src2),
2354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2356 [(set VR128:$dst, (IntId VR128:$src1,
2357 (bitconvert (memopv2i64 addr:$src2))))]>;
2358 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2359 (ins VR128:$src1, i32i8imm:$src2),
2361 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2362 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2363 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2366 /// PDI_binop_rm - Simple SSE2 binary operator.
2367 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2368 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2369 let isCommutable = IsCommutable in
2370 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2371 (ins VR128:$src1, VR128:$src2),
2373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2375 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2376 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2377 (ins VR128:$src1, i128mem:$src2),
2379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2381 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2382 (bitconvert (memopv2i64 addr:$src2)))))]>;
2385 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2387 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2388 /// to collapse (bitconvert VT to VT) into its operand.
2390 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2391 bit IsCommutable = 0, bit Is2Addr = 1> {
2392 let isCommutable = IsCommutable in
2393 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2394 (ins VR128:$src1, VR128:$src2),
2396 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2397 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2398 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2399 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2400 (ins VR128:$src1, i128mem:$src2),
2402 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2403 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2404 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2407 } // ExeDomain = SSEPackedInt
2409 // 128-bit Integer Arithmetic
2411 let Predicates = [HasAVX] in {
2412 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2413 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2414 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2415 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2416 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2417 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2418 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2419 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2420 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2423 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2425 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2427 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2429 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2431 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2433 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2435 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2437 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2439 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2441 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2443 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2445 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2447 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2449 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2451 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2453 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2455 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2457 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2459 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2463 let Constraints = "$src1 = $dst" in {
2464 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2465 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2466 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2467 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2468 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2469 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2470 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2471 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2472 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2475 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2476 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2477 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2478 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2479 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2480 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2481 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2482 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2483 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2484 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2485 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2486 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2487 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2488 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2489 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2490 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2491 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2492 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2493 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2495 } // Constraints = "$src1 = $dst"
2497 //===---------------------------------------------------------------------===//
2498 // SSE2 - Packed Integer Logical Instructions
2499 //===---------------------------------------------------------------------===//
2501 let Predicates = [HasAVX] in {
2502 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2503 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2505 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2506 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2508 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2509 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2512 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2513 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2515 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2516 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2518 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2519 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2522 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2523 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2525 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2526 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2529 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2530 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2531 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2533 let ExeDomain = SSEPackedInt in {
2534 let neverHasSideEffects = 1 in {
2535 // 128-bit logical shifts.
2536 def VPSLLDQri : PDIi8<0x73, MRM7r,
2537 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2538 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2540 def VPSRLDQri : PDIi8<0x73, MRM3r,
2541 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2542 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2544 // PSRADQri doesn't exist in SSE[1-3].
2546 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2547 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2548 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2549 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2550 VR128:$src2)))]>, VEX_4V;
2552 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2553 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2554 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2555 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2556 (memopv2i64 addr:$src2))))]>,
2561 let Constraints = "$src1 = $dst" in {
2562 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2563 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2564 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2565 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2566 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2567 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2569 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2570 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2571 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2572 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2573 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2574 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2576 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2577 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2578 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2579 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2581 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2582 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2583 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2585 let ExeDomain = SSEPackedInt in {
2586 let neverHasSideEffects = 1 in {
2587 // 128-bit logical shifts.
2588 def PSLLDQri : PDIi8<0x73, MRM7r,
2589 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2590 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2591 def PSRLDQri : PDIi8<0x73, MRM3r,
2592 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2593 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2594 // PSRADQri doesn't exist in SSE[1-3].
2596 def PANDNrr : PDI<0xDF, MRMSrcReg,
2597 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2598 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2600 def PANDNrm : PDI<0xDF, MRMSrcMem,
2601 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2602 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2604 } // Constraints = "$src1 = $dst"
2606 let Predicates = [HasAVX] in {
2607 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2608 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2609 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2610 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2611 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2612 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2613 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2614 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2615 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2616 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2618 // Shift up / down and insert zero's.
2619 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2620 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2621 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2622 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2625 let Predicates = [HasSSE2] in {
2626 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2627 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2628 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2629 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2630 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2631 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2632 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2633 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2634 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2635 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2637 // Shift up / down and insert zero's.
2638 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2639 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2640 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2641 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2644 //===---------------------------------------------------------------------===//
2645 // SSE2 - Packed Integer Comparison Instructions
2646 //===---------------------------------------------------------------------===//
2648 let Predicates = [HasAVX] in {
2649 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2651 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2653 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2655 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2657 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2659 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2663 let Constraints = "$src1 = $dst" in {
2664 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2665 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2666 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2667 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2668 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2669 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2670 } // Constraints = "$src1 = $dst"
2672 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2673 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2674 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2675 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2676 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2677 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2678 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2679 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2680 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2681 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2682 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2683 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2685 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2686 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2687 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2688 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2689 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2690 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2691 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2692 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2693 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2694 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2695 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2696 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2698 //===---------------------------------------------------------------------===//
2699 // SSE2 - Packed Integer Pack Instructions
2700 //===---------------------------------------------------------------------===//
2702 let Predicates = [HasAVX] in {
2703 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2705 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2707 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2711 let Constraints = "$src1 = $dst" in {
2712 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2713 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2714 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2715 } // Constraints = "$src1 = $dst"
2717 //===---------------------------------------------------------------------===//
2718 // SSE2 - Packed Integer Shuffle Instructions
2719 //===---------------------------------------------------------------------===//
2721 let ExeDomain = SSEPackedInt in {
2722 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2724 def ri : Ii8<0x70, MRMSrcReg,
2725 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2726 !strconcat(OpcodeStr,
2727 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2728 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2730 def mi : Ii8<0x70, MRMSrcMem,
2731 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2732 !strconcat(OpcodeStr,
2733 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2734 [(set VR128:$dst, (vt (pshuf_frag:$src2
2735 (bc_frag (memopv2i64 addr:$src1)),
2738 } // ExeDomain = SSEPackedInt
2740 let Predicates = [HasAVX] in {
2741 let AddedComplexity = 5 in
2742 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2745 // SSE2 with ImmT == Imm8 and XS prefix.
2746 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2749 // SSE2 with ImmT == Imm8 and XD prefix.
2750 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2754 let Predicates = [HasSSE2] in {
2755 let AddedComplexity = 5 in
2756 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2758 // SSE2 with ImmT == Imm8 and XS prefix.
2759 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2761 // SSE2 with ImmT == Imm8 and XD prefix.
2762 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2765 //===---------------------------------------------------------------------===//
2766 // SSE2 - Packed Integer Unpack Instructions
2767 //===---------------------------------------------------------------------===//
2769 let ExeDomain = SSEPackedInt in {
2770 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2771 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2772 def rr : PDI<opc, MRMSrcReg,
2773 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2775 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2776 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2777 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2778 def rm : PDI<opc, MRMSrcMem,
2779 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2781 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2782 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2783 [(set VR128:$dst, (OpNode VR128:$src1,
2784 (bc_frag (memopv2i64
2788 let Predicates = [HasAVX] in {
2789 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2790 bc_v16i8, 0>, VEX_4V;
2791 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2792 bc_v8i16, 0>, VEX_4V;
2793 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2794 bc_v4i32, 0>, VEX_4V;
2796 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2797 /// knew to collapse (bitconvert VT to VT) into its operand.
2798 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2799 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2800 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2801 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2802 VR128:$src2)))]>, VEX_4V;
2803 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2804 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2805 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2806 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2807 (memopv2i64 addr:$src2))))]>, VEX_4V;
2809 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2810 bc_v16i8, 0>, VEX_4V;
2811 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2812 bc_v8i16, 0>, VEX_4V;
2813 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2814 bc_v4i32, 0>, VEX_4V;
2816 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2817 /// knew to collapse (bitconvert VT to VT) into its operand.
2818 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2819 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2820 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2821 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2822 VR128:$src2)))]>, VEX_4V;
2823 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2824 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2825 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2826 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2827 (memopv2i64 addr:$src2))))]>, VEX_4V;
2830 let Constraints = "$src1 = $dst" in {
2831 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2832 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2833 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2835 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2836 /// knew to collapse (bitconvert VT to VT) into its operand.
2837 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2839 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2841 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2842 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2843 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2844 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2846 (v2i64 (X86Punpcklqdq VR128:$src1,
2847 (memopv2i64 addr:$src2))))]>;
2849 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2850 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2851 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2853 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2854 /// knew to collapse (bitconvert VT to VT) into its operand.
2855 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2856 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2857 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2859 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2860 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2861 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2862 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2864 (v2i64 (X86Punpckhqdq VR128:$src1,
2865 (memopv2i64 addr:$src2))))]>;
2868 } // ExeDomain = SSEPackedInt
2870 //===---------------------------------------------------------------------===//
2871 // SSE2 - Packed Integer Extract and Insert
2872 //===---------------------------------------------------------------------===//
2874 let ExeDomain = SSEPackedInt in {
2875 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2876 def rri : Ii8<0xC4, MRMSrcReg,
2877 (outs VR128:$dst), (ins VR128:$src1,
2878 GR32:$src2, i32i8imm:$src3),
2880 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2881 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2883 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2884 def rmi : Ii8<0xC4, MRMSrcMem,
2885 (outs VR128:$dst), (ins VR128:$src1,
2886 i16mem:$src2, i32i8imm:$src3),
2888 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2889 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2891 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2896 let Predicates = [HasAVX] in
2897 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2898 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2899 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2900 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2901 imm:$src2))]>, OpSize, VEX;
2902 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2903 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2904 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2905 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2909 let Predicates = [HasAVX] in {
2910 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2911 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2912 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2913 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2914 []>, OpSize, VEX_4V;
2917 let Constraints = "$src1 = $dst" in
2918 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2920 } // ExeDomain = SSEPackedInt
2922 //===---------------------------------------------------------------------===//
2923 // SSE2 - Packed Mask Creation
2924 //===---------------------------------------------------------------------===//
2926 let ExeDomain = SSEPackedInt in {
2928 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2929 "pmovmskb\t{$src, $dst|$dst, $src}",
2930 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2931 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2932 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2933 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2934 "pmovmskb\t{$src, $dst|$dst, $src}",
2935 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2937 } // ExeDomain = SSEPackedInt
2939 //===---------------------------------------------------------------------===//
2940 // SSE2 - Conditional Store
2941 //===---------------------------------------------------------------------===//
2943 let ExeDomain = SSEPackedInt in {
2946 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2947 (ins VR128:$src, VR128:$mask),
2948 "maskmovdqu\t{$mask, $src|$src, $mask}",
2949 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2951 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2952 (ins VR128:$src, VR128:$mask),
2953 "maskmovdqu\t{$mask, $src|$src, $mask}",
2954 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2957 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2958 "maskmovdqu\t{$mask, $src|$src, $mask}",
2959 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2961 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2962 "maskmovdqu\t{$mask, $src|$src, $mask}",
2963 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2965 } // ExeDomain = SSEPackedInt
2967 //===---------------------------------------------------------------------===//
2968 // SSE2 - Move Doubleword
2969 //===---------------------------------------------------------------------===//
2971 //===---------------------------------------------------------------------===//
2972 // Move Int Doubleword to Packed Double Int
2974 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2975 "movd\t{$src, $dst|$dst, $src}",
2977 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2978 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2979 "movd\t{$src, $dst|$dst, $src}",
2981 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2983 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2984 "mov{d|q}\t{$src, $dst|$dst, $src}",
2986 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
2987 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2988 "mov{d|q}\t{$src, $dst|$dst, $src}",
2989 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
2991 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2992 "movd\t{$src, $dst|$dst, $src}",
2994 (v4i32 (scalar_to_vector GR32:$src)))]>;
2995 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2996 "movd\t{$src, $dst|$dst, $src}",
2998 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2999 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3000 "mov{d|q}\t{$src, $dst|$dst, $src}",
3002 (v2i64 (scalar_to_vector GR64:$src)))]>;
3003 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3004 "mov{d|q}\t{$src, $dst|$dst, $src}",
3005 [(set FR64:$dst, (bitconvert GR64:$src))]>;
3007 //===---------------------------------------------------------------------===//
3008 // Move Int Doubleword to Single Scalar
3010 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3011 "movd\t{$src, $dst|$dst, $src}",
3012 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3014 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3015 "movd\t{$src, $dst|$dst, $src}",
3016 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3018 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3019 "movd\t{$src, $dst|$dst, $src}",
3020 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3022 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3023 "movd\t{$src, $dst|$dst, $src}",
3024 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3026 //===---------------------------------------------------------------------===//
3027 // Move Packed Doubleword Int to Packed Double Int
3029 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3030 "movd\t{$src, $dst|$dst, $src}",
3031 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3033 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3034 (ins i32mem:$dst, VR128:$src),
3035 "movd\t{$src, $dst|$dst, $src}",
3036 [(store (i32 (vector_extract (v4i32 VR128:$src),
3037 (iPTR 0))), addr:$dst)]>, VEX;
3038 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3039 "movd\t{$src, $dst|$dst, $src}",
3040 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3042 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3043 "movd\t{$src, $dst|$dst, $src}",
3044 [(store (i32 (vector_extract (v4i32 VR128:$src),
3045 (iPTR 0))), addr:$dst)]>;
3047 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3048 "mov{d|q}\t{$src, $dst|$dst, $src}",
3049 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3051 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3052 "movq\t{$src, $dst|$dst, $src}",
3053 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3055 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3056 "mov{d|q}\t{$src, $dst|$dst, $src}",
3057 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3058 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3059 "movq\t{$src, $dst|$dst, $src}",
3060 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3062 //===---------------------------------------------------------------------===//
3063 // Move Scalar Single to Double Int
3065 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3066 "movd\t{$src, $dst|$dst, $src}",
3067 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3068 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3069 "movd\t{$src, $dst|$dst, $src}",
3070 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3071 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3072 "movd\t{$src, $dst|$dst, $src}",
3073 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3074 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3075 "movd\t{$src, $dst|$dst, $src}",
3076 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3078 //===---------------------------------------------------------------------===//
3079 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3081 let AddedComplexity = 15 in {
3082 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3083 "movd\t{$src, $dst|$dst, $src}",
3084 [(set VR128:$dst, (v4i32 (X86vzmovl
3085 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3087 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3088 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3089 [(set VR128:$dst, (v2i64 (X86vzmovl
3090 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3093 let AddedComplexity = 15 in {
3094 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3095 "movd\t{$src, $dst|$dst, $src}",
3096 [(set VR128:$dst, (v4i32 (X86vzmovl
3097 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3098 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3099 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3100 [(set VR128:$dst, (v2i64 (X86vzmovl
3101 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3104 let AddedComplexity = 20 in {
3105 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3106 "movd\t{$src, $dst|$dst, $src}",
3108 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3109 (loadi32 addr:$src))))))]>,
3111 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3112 "movd\t{$src, $dst|$dst, $src}",
3114 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3115 (loadi32 addr:$src))))))]>;
3117 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3118 (MOVZDI2PDIrm addr:$src)>;
3119 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3120 (MOVZDI2PDIrm addr:$src)>;
3121 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3122 (MOVZDI2PDIrm addr:$src)>;
3125 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3126 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3127 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3128 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3129 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3130 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3131 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3132 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3134 // These are the correct encodings of the instructions so that we know how to
3135 // read correct assembly, even though we continue to emit the wrong ones for
3136 // compatibility with Darwin's buggy assembler.
3137 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3138 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3139 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3140 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3141 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3142 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3143 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3144 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3145 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3146 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3147 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3148 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3150 //===---------------------------------------------------------------------===//
3151 // SSE2 - Move Quadword
3152 //===---------------------------------------------------------------------===//
3154 //===---------------------------------------------------------------------===//
3155 // Move Quadword Int to Packed Quadword Int
3157 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3158 "vmovq\t{$src, $dst|$dst, $src}",
3160 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3161 VEX, Requires<[HasAVX]>;
3162 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3163 "movq\t{$src, $dst|$dst, $src}",
3165 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3166 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3168 //===---------------------------------------------------------------------===//
3169 // Move Packed Quadword Int to Quadword Int
3171 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3172 "movq\t{$src, $dst|$dst, $src}",
3173 [(store (i64 (vector_extract (v2i64 VR128:$src),
3174 (iPTR 0))), addr:$dst)]>, VEX;
3175 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3176 "movq\t{$src, $dst|$dst, $src}",
3177 [(store (i64 (vector_extract (v2i64 VR128:$src),
3178 (iPTR 0))), addr:$dst)]>;
3180 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3181 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3183 //===---------------------------------------------------------------------===//
3184 // Store / copy lower 64-bits of a XMM register.
3186 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3187 "movq\t{$src, $dst|$dst, $src}",
3188 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3189 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3190 "movq\t{$src, $dst|$dst, $src}",
3191 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3193 let AddedComplexity = 20 in
3194 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3195 "vmovq\t{$src, $dst|$dst, $src}",
3197 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3198 (loadi64 addr:$src))))))]>,
3199 XS, VEX, Requires<[HasAVX]>;
3201 let AddedComplexity = 20 in {
3202 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3203 "movq\t{$src, $dst|$dst, $src}",
3205 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3206 (loadi64 addr:$src))))))]>,
3207 XS, Requires<[HasSSE2]>;
3209 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3210 (MOVZQI2PQIrm addr:$src)>;
3211 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3212 (MOVZQI2PQIrm addr:$src)>;
3213 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3216 //===---------------------------------------------------------------------===//
3217 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3218 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3220 let AddedComplexity = 15 in
3221 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3222 "vmovq\t{$src, $dst|$dst, $src}",
3223 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3224 XS, VEX, Requires<[HasAVX]>;
3225 let AddedComplexity = 15 in
3226 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3227 "movq\t{$src, $dst|$dst, $src}",
3228 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3229 XS, Requires<[HasSSE2]>;
3231 let AddedComplexity = 20 in
3232 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3233 "vmovq\t{$src, $dst|$dst, $src}",
3234 [(set VR128:$dst, (v2i64 (X86vzmovl
3235 (loadv2i64 addr:$src))))]>,
3236 XS, VEX, Requires<[HasAVX]>;
3237 let AddedComplexity = 20 in {
3238 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3239 "movq\t{$src, $dst|$dst, $src}",
3240 [(set VR128:$dst, (v2i64 (X86vzmovl
3241 (loadv2i64 addr:$src))))]>,
3242 XS, Requires<[HasSSE2]>;
3244 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3245 (MOVZPQILo2PQIrm addr:$src)>;
3248 // Instructions to match in the assembler
3249 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3250 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3251 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3252 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3253 // Recognize "movd" with GR64 destination, but encode as a "movq"
3254 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3255 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3257 // Instructions for the disassembler
3258 // xr = XMM register
3261 let Predicates = [HasAVX] in
3262 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3263 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3264 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3265 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3267 //===---------------------------------------------------------------------===//
3268 // SSE2 - Misc Instructions
3269 //===---------------------------------------------------------------------===//
3272 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3273 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3274 TB, Requires<[HasSSE2]>;
3276 // Load, store, and memory fence
3277 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3278 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3279 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3280 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3281 def : Pat<(X86LFence), (LFENCE)>;
3282 def : Pat<(X86MFence), (MFENCE)>;
3285 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3286 // was introduced with SSE2, it's backward compatible.
3287 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3289 // Alias instructions that map zero vector to pxor / xorp* for sse.
3290 // We set canFoldAsLoad because this can be converted to a constant-pool
3291 // load of an all-ones value if folding it would be beneficial.
3292 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3293 // JIT implementation, it does not expand the instructions below like
3294 // X86MCInstLower does.
3295 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3296 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3297 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3298 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3299 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3300 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3301 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3302 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3304 //===---------------------------------------------------------------------===//
3305 // SSE3 - Conversion Instructions
3306 //===---------------------------------------------------------------------===//
3308 // Convert Packed Double FP to Packed DW Integers
3309 let Predicates = [HasAVX] in {
3310 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3311 // register, but the same isn't true when using memory operands instead.
3312 // Provide other assembly rr and rm forms to address this explicitly.
3313 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3314 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3315 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3316 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3319 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3320 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3321 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3322 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3325 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3326 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3327 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3328 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3331 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3332 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3333 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3334 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3336 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3337 (VCVTPD2DQYrr VR256:$src)>;
3338 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3339 (VCVTPD2DQYrm addr:$src)>;
3341 // Convert Packed DW Integers to Packed Double FP
3342 let Predicates = [HasAVX] in {
3343 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3344 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3345 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3346 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3347 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3348 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3349 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3350 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3353 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3354 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3355 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3356 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3358 // AVX 256-bit register conversion intrinsics
3359 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3360 (VCVTDQ2PDYrr VR128:$src)>;
3361 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3362 (VCVTDQ2PDYrm addr:$src)>;
3364 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3365 (VCVTPD2DQYrr VR256:$src)>;
3366 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3367 (VCVTPD2DQYrm addr:$src)>;
3369 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3370 (VCVTDQ2PDYrr VR128:$src)>;
3371 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3372 (VCVTDQ2PDYrm addr:$src)>;
3374 //===---------------------------------------------------------------------===//
3375 // SSE3 - Move Instructions
3376 //===---------------------------------------------------------------------===//
3378 //===---------------------------------------------------------------------===//
3379 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3381 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3382 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3383 X86MemOperand x86memop> {
3384 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3385 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3386 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3387 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3388 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3389 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3392 let Predicates = [HasAVX] in {
3393 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3394 v4f32, VR128, memopv4f32, f128mem>, VEX;
3395 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3396 v4f32, VR128, memopv4f32, f128mem>, VEX;
3397 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3398 v8f32, VR256, memopv8f32, f256mem>, VEX;
3399 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3400 v8f32, VR256, memopv8f32, f256mem>, VEX;
3402 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3403 memopv4f32, f128mem>;
3404 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3405 memopv4f32, f128mem>;
3407 let Predicates = [HasSSE3] in {
3408 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3409 (MOVSHDUPrr VR128:$src)>;
3410 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3411 (MOVSHDUPrm addr:$src)>;
3412 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3413 (MOVSLDUPrr VR128:$src)>;
3414 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3415 (MOVSLDUPrm addr:$src)>;
3418 let Predicates = [HasAVX] in {
3419 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3420 (VMOVSHDUPrr VR128:$src)>;
3421 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3422 (VMOVSHDUPrm addr:$src)>;
3423 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3424 (VMOVSLDUPrr VR128:$src)>;
3425 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3426 (VMOVSLDUPrm addr:$src)>;
3427 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3428 (VMOVSHDUPYrr VR256:$src)>;
3429 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3430 (VMOVSHDUPYrm addr:$src)>;
3431 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3432 (VMOVSLDUPYrr VR256:$src)>;
3433 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3434 (VMOVSLDUPYrm addr:$src)>;
3437 //===---------------------------------------------------------------------===//
3438 // Replicate Double FP - MOVDDUP
3440 multiclass sse3_replicate_dfp<string OpcodeStr> {
3441 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3442 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3443 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3444 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3447 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3451 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3452 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3453 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3455 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3456 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3460 let Predicates = [HasAVX] in {
3461 // FIXME: Merge above classes when we have patterns for the ymm version
3462 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3463 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3465 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3467 // Move Unaligned Integer
3468 let Predicates = [HasAVX] in {
3469 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3470 "vlddqu\t{$src, $dst|$dst, $src}",
3471 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3472 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3473 "vlddqu\t{$src, $dst|$dst, $src}",
3474 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3476 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3477 "lddqu\t{$src, $dst|$dst, $src}",
3478 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3480 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3482 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3484 // Several Move patterns
3485 let AddedComplexity = 5 in {
3486 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3487 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3488 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3489 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3490 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3491 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3492 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3493 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3496 //===---------------------------------------------------------------------===//
3497 // SSE3 - Arithmetic
3498 //===---------------------------------------------------------------------===//
3500 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3501 X86MemOperand x86memop, bit Is2Addr = 1> {
3502 def rr : I<0xD0, MRMSrcReg,
3503 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3505 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3506 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3507 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3508 def rm : I<0xD0, MRMSrcMem,
3509 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3511 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3512 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3513 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3516 let Predicates = [HasAVX],
3517 ExeDomain = SSEPackedDouble in {
3518 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3519 f128mem, 0>, TB, XD, VEX_4V;
3520 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3521 f128mem, 0>, TB, OpSize, VEX_4V;
3522 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3523 f256mem, 0>, TB, XD, VEX_4V;
3524 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3525 f256mem, 0>, TB, OpSize, VEX_4V;
3527 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3528 ExeDomain = SSEPackedDouble in {
3529 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3531 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3532 f128mem>, TB, OpSize;
3535 //===---------------------------------------------------------------------===//
3536 // SSE3 Instructions
3537 //===---------------------------------------------------------------------===//
3540 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3541 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3542 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3544 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3545 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3546 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3548 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3550 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3551 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3552 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3554 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3555 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3556 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3558 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3560 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3562 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3564 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3565 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3566 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3569 let Predicates = [HasAVX] in {
3570 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3571 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3572 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3573 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3574 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3575 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3576 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3577 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3578 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3579 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3580 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3581 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3582 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3583 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3584 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3585 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3588 let Constraints = "$src1 = $dst" in {
3589 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3590 int_x86_sse3_hadd_ps>;
3591 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3592 int_x86_sse3_hadd_pd>;
3593 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3594 int_x86_sse3_hsub_ps>;
3595 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3596 int_x86_sse3_hsub_pd>;
3599 //===---------------------------------------------------------------------===//
3600 // SSSE3 - Packed Absolute Instructions
3601 //===---------------------------------------------------------------------===//
3604 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3605 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3606 PatFrag mem_frag128, Intrinsic IntId128> {
3607 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3610 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3613 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3618 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3621 let Predicates = [HasAVX] in {
3622 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3623 int_x86_ssse3_pabs_b_128>, VEX;
3624 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3625 int_x86_ssse3_pabs_w_128>, VEX;
3626 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3627 int_x86_ssse3_pabs_d_128>, VEX;
3630 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3631 int_x86_ssse3_pabs_b_128>;
3632 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3633 int_x86_ssse3_pabs_w_128>;
3634 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3635 int_x86_ssse3_pabs_d_128>;
3637 //===---------------------------------------------------------------------===//
3638 // SSSE3 - Packed Binary Operator Instructions
3639 //===---------------------------------------------------------------------===//
3641 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3642 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3643 PatFrag mem_frag128, Intrinsic IntId128,
3645 let isCommutable = 1 in
3646 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3647 (ins VR128:$src1, VR128:$src2),
3649 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3650 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3651 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3653 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3654 (ins VR128:$src1, i128mem:$src2),
3656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3657 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3659 (IntId128 VR128:$src1,
3660 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3663 let Predicates = [HasAVX] in {
3664 let isCommutable = 0 in {
3665 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3666 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3667 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3668 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3669 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3670 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3671 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3672 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3673 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3674 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3675 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3676 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3677 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3678 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3679 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3680 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3681 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3682 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3683 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3684 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3685 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3686 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3688 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3689 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3692 // None of these have i8 immediate fields.
3693 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3694 let isCommutable = 0 in {
3695 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3696 int_x86_ssse3_phadd_w_128>;
3697 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3698 int_x86_ssse3_phadd_d_128>;
3699 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3700 int_x86_ssse3_phadd_sw_128>;
3701 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3702 int_x86_ssse3_phsub_w_128>;
3703 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3704 int_x86_ssse3_phsub_d_128>;
3705 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3706 int_x86_ssse3_phsub_sw_128>;
3707 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3708 int_x86_ssse3_pmadd_ub_sw_128>;
3709 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3710 int_x86_ssse3_pshuf_b_128>;
3711 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3712 int_x86_ssse3_psign_b_128>;
3713 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3714 int_x86_ssse3_psign_w_128>;
3715 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3716 int_x86_ssse3_psign_d_128>;
3718 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3719 int_x86_ssse3_pmul_hr_sw_128>;
3722 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3723 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3724 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3725 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3727 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3728 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3729 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3730 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3731 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3732 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3734 //===---------------------------------------------------------------------===//
3735 // SSSE3 - Packed Align Instruction Patterns
3736 //===---------------------------------------------------------------------===//
3738 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3739 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3740 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3742 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3744 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3746 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3747 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3749 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3751 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3755 let Predicates = [HasAVX] in
3756 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3757 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
3758 defm PALIGN : ssse3_palign<"palignr">;
3760 let Predicates = [HasSSSE3] in {
3761 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3762 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3763 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3764 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3765 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3766 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3767 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3768 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3771 let Predicates = [HasAVX] in {
3772 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3773 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3774 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3775 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3776 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3777 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3778 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3779 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3782 //===---------------------------------------------------------------------===//
3783 // SSSE3 Misc Instructions
3784 //===---------------------------------------------------------------------===//
3786 // Thread synchronization
3787 let usesCustomInserter = 1 in {
3788 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3789 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3790 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3791 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3794 let Uses = [EAX, ECX, EDX] in
3795 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3796 Requires<[HasSSE3]>;
3797 let Uses = [ECX, EAX] in
3798 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3799 Requires<[HasSSE3]>;
3801 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3802 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3804 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3805 Requires<[In32BitMode]>;
3806 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3807 Requires<[In64BitMode]>;
3809 //===---------------------------------------------------------------------===//
3810 // Non-Instruction Patterns
3811 //===---------------------------------------------------------------------===//
3813 // extload f32 -> f64. This matches load+fextend because we have a hack in
3814 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3816 // Since these loads aren't folded into the fextend, we have to match it
3818 let Predicates = [HasSSE2] in
3819 def : Pat<(fextend (loadf32 addr:$src)),
3820 (CVTSS2SDrm addr:$src)>;
3822 // Bitcasts between 128-bit vector types. Return the original type since
3823 // no instruction is needed for the conversion
3824 let Predicates = [HasXMMInt] in {
3825 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3826 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3827 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3828 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3829 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3830 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3831 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3832 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3833 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3834 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3835 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3836 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3837 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3838 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3839 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3840 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3841 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3842 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3843 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3844 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3845 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3846 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3847 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3848 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3849 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3850 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3851 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3852 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3853 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3854 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3857 // Bitcasts between 256-bit vector types. Return the original type since
3858 // no instruction is needed for the conversion
3859 let Predicates = [HasAVX] in {
3860 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3861 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3862 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3863 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
3864 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3865 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
3866 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3867 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3868 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3869 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
3870 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3871 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
3872 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3873 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3874 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
3875 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3876 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3877 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3878 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3879 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
3880 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3881 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
3882 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
3883 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
3884 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
3885 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
3886 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
3887 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
3888 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
3889 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
3892 // Move scalar to XMM zero-extended
3893 // movd to XMM register zero-extends
3894 let AddedComplexity = 15 in {
3895 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3896 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3897 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3898 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3899 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3900 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3901 (MOVSSrr (v4f32 (V_SET0PS)),
3902 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3903 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3904 (MOVSSrr (v4i32 (V_SET0PI)),
3905 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3908 // Splat v2f64 / v2i64
3909 let AddedComplexity = 10 in {
3910 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3911 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3912 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3913 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3916 // Special unary SHUFPSrri case.
3917 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3918 (SHUFPSrri VR128:$src1, VR128:$src1,
3919 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3920 let AddedComplexity = 5 in
3921 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3922 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3923 Requires<[HasSSE2]>;
3924 // Special unary SHUFPDrri case.
3925 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3926 (SHUFPDrri VR128:$src1, VR128:$src1,
3927 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3928 Requires<[HasSSE2]>;
3929 // Special unary SHUFPDrri case.
3930 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3931 (SHUFPDrri VR128:$src1, VR128:$src1,
3932 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3933 Requires<[HasSSE2]>;
3934 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3935 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3936 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3937 Requires<[HasSSE2]>;
3939 // Special binary v4i32 shuffle cases with SHUFPS.
3940 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3941 (SHUFPSrri VR128:$src1, VR128:$src2,
3942 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3943 Requires<[HasSSE2]>;
3944 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3945 (SHUFPSrmi VR128:$src1, addr:$src2,
3946 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3947 Requires<[HasSSE2]>;
3948 // Special binary v2i64 shuffle cases using SHUFPDrri.
3949 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3950 (SHUFPDrri VR128:$src1, VR128:$src2,
3951 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3952 Requires<[HasSSE2]>;
3954 let AddedComplexity = 20 in {
3955 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3956 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3957 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3959 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3960 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3961 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3963 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3964 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3965 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3966 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3967 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3970 let AddedComplexity = 20 in {
3971 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3972 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3973 (MOVLPSrm VR128:$src1, addr:$src2)>;
3974 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3975 (MOVLPDrm VR128:$src1, addr:$src2)>;
3976 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3977 (MOVLPSrm VR128:$src1, addr:$src2)>;
3978 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3979 (MOVLPDrm VR128:$src1, addr:$src2)>;
3982 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3983 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3984 (MOVLPSmr addr:$src1, VR128:$src2)>;
3985 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3986 (MOVLPDmr addr:$src1, VR128:$src2)>;
3987 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3989 (MOVLPSmr addr:$src1, VR128:$src2)>;
3990 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3991 (MOVLPDmr addr:$src1, VR128:$src2)>;
3993 let AddedComplexity = 15 in {
3994 // Setting the lowest element in the vector.
3995 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3996 (MOVSSrr (v4i32 VR128:$src1),
3997 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3998 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3999 (MOVSDrr (v2i64 VR128:$src1),
4000 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
4002 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
4003 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
4004 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4005 Requires<[HasSSE2]>;
4006 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
4007 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4008 Requires<[HasSSE2]>;
4011 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
4012 // fall back to this for SSE1)
4013 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
4014 (SHUFPSrri VR128:$src2, VR128:$src1,
4015 (SHUFFLE_get_shuf_imm VR128:$src3))>;
4017 // Set lowest element and zero upper elements.
4018 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4019 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4021 // Use movaps / movups for SSE integer load / store (one byte shorter).
4022 // The instructions selected below are then converted to MOVDQA/MOVDQU
4023 // during the SSE domain pass.
4024 let Predicates = [HasSSE1] in {
4025 def : Pat<(alignedloadv4i32 addr:$src),
4026 (MOVAPSrm addr:$src)>;
4027 def : Pat<(loadv4i32 addr:$src),
4028 (MOVUPSrm addr:$src)>;
4029 def : Pat<(alignedloadv2i64 addr:$src),
4030 (MOVAPSrm addr:$src)>;
4031 def : Pat<(loadv2i64 addr:$src),
4032 (MOVUPSrm addr:$src)>;
4034 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4035 (MOVAPSmr addr:$dst, VR128:$src)>;
4036 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4037 (MOVAPSmr addr:$dst, VR128:$src)>;
4038 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4039 (MOVAPSmr addr:$dst, VR128:$src)>;
4040 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4041 (MOVAPSmr addr:$dst, VR128:$src)>;
4042 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4043 (MOVUPSmr addr:$dst, VR128:$src)>;
4044 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4045 (MOVUPSmr addr:$dst, VR128:$src)>;
4046 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4047 (MOVUPSmr addr:$dst, VR128:$src)>;
4048 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4049 (MOVUPSmr addr:$dst, VR128:$src)>;
4052 // Use vmovaps/vmovups for AVX integer load/store.
4053 let Predicates = [HasAVX] in {
4054 // 128-bit load/store
4055 def : Pat<(alignedloadv4i32 addr:$src),
4056 (VMOVAPSrm addr:$src)>;
4057 def : Pat<(loadv4i32 addr:$src),
4058 (VMOVUPSrm addr:$src)>;
4059 def : Pat<(alignedloadv2i64 addr:$src),
4060 (VMOVAPSrm addr:$src)>;
4061 def : Pat<(loadv2i64 addr:$src),
4062 (VMOVUPSrm addr:$src)>;
4064 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4065 (VMOVAPSmr addr:$dst, VR128:$src)>;
4066 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4067 (VMOVAPSmr addr:$dst, VR128:$src)>;
4068 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4069 (VMOVAPSmr addr:$dst, VR128:$src)>;
4070 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4071 (VMOVAPSmr addr:$dst, VR128:$src)>;
4072 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4073 (VMOVUPSmr addr:$dst, VR128:$src)>;
4074 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4075 (VMOVUPSmr addr:$dst, VR128:$src)>;
4076 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4077 (VMOVUPSmr addr:$dst, VR128:$src)>;
4078 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4079 (VMOVUPSmr addr:$dst, VR128:$src)>;
4081 // 256-bit load/store
4082 def : Pat<(alignedloadv4i64 addr:$src),
4083 (VMOVAPSYrm addr:$src)>;
4084 def : Pat<(loadv4i64 addr:$src),
4085 (VMOVUPSYrm addr:$src)>;
4086 def : Pat<(alignedloadv8i32 addr:$src),
4087 (VMOVAPSYrm addr:$src)>;
4088 def : Pat<(loadv8i32 addr:$src),
4089 (VMOVUPSYrm addr:$src)>;
4090 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4091 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4092 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4093 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4094 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4095 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4096 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4097 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4098 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4099 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4100 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4101 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4102 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4103 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4104 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4105 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4108 //===----------------------------------------------------------------------===//
4109 // SSE4.1 - Packed Move with Sign/Zero Extend
4110 //===----------------------------------------------------------------------===//
4112 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4113 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4115 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4117 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4118 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4120 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4124 let Predicates = [HasAVX] in {
4125 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4127 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4129 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4131 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4133 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4135 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4139 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4140 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4141 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4142 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4143 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4144 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4146 // Common patterns involving scalar load.
4147 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4148 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4149 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4150 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4152 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4153 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4154 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4155 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4157 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4158 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4159 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4160 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4162 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4163 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4164 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4165 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4167 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4168 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4169 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4170 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4172 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4173 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4174 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4175 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4178 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4179 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4180 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4181 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4183 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4184 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4186 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4190 let Predicates = [HasAVX] in {
4191 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4193 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4195 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4197 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4201 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4202 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4203 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4204 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4206 // Common patterns involving scalar load
4207 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4208 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4209 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4210 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4212 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4213 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4214 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4215 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4218 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4219 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4220 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4221 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4223 // Expecting a i16 load any extended to i32 value.
4224 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4226 [(set VR128:$dst, (IntId (bitconvert
4227 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4231 let Predicates = [HasAVX] in {
4232 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4234 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4237 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4238 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4240 // Common patterns involving scalar load
4241 def : Pat<(int_x86_sse41_pmovsxbq
4242 (bitconvert (v4i32 (X86vzmovl
4243 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4244 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4246 def : Pat<(int_x86_sse41_pmovzxbq
4247 (bitconvert (v4i32 (X86vzmovl
4248 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4249 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4251 //===----------------------------------------------------------------------===//
4252 // SSE4.1 - Extract Instructions
4253 //===----------------------------------------------------------------------===//
4255 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4256 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4257 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4258 (ins VR128:$src1, i32i8imm:$src2),
4259 !strconcat(OpcodeStr,
4260 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4261 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4263 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4264 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4265 !strconcat(OpcodeStr,
4266 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4269 // There's an AssertZext in the way of writing the store pattern
4270 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4273 let Predicates = [HasAVX] in {
4274 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4275 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4276 (ins VR128:$src1, i32i8imm:$src2),
4277 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4280 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4283 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4284 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4285 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4286 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4287 !strconcat(OpcodeStr,
4288 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 // There's an AssertZext in the way of writing the store pattern
4292 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4295 let Predicates = [HasAVX] in
4296 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4298 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4301 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4302 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4303 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4304 (ins VR128:$src1, i32i8imm:$src2),
4305 !strconcat(OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4309 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4310 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4311 !strconcat(OpcodeStr,
4312 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4313 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4314 addr:$dst)]>, OpSize;
4317 let Predicates = [HasAVX] in
4318 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4320 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4322 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4323 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4324 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4325 (ins VR128:$src1, i32i8imm:$src2),
4326 !strconcat(OpcodeStr,
4327 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4329 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4330 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4331 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4332 !strconcat(OpcodeStr,
4333 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4334 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4335 addr:$dst)]>, OpSize, REX_W;
4338 let Predicates = [HasAVX] in
4339 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4341 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4343 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4345 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4346 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4347 (ins VR128:$src1, i32i8imm:$src2),
4348 !strconcat(OpcodeStr,
4349 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4351 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4353 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4354 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4355 !strconcat(OpcodeStr,
4356 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4357 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4358 addr:$dst)]>, OpSize;
4361 let Predicates = [HasAVX] in {
4362 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4363 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4364 (ins VR128:$src1, i32i8imm:$src2),
4365 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4368 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4370 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4371 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4374 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4375 Requires<[HasSSE41]>;
4377 //===----------------------------------------------------------------------===//
4378 // SSE4.1 - Insert Instructions
4379 //===----------------------------------------------------------------------===//
4381 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4382 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4383 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4385 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4389 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4390 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4391 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4393 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4395 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4397 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4398 imm:$src3))]>, OpSize;
4401 let Predicates = [HasAVX] in
4402 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4403 let Constraints = "$src1 = $dst" in
4404 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4406 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4407 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4408 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4410 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4412 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4414 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4416 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4417 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4419 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4421 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4423 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4424 imm:$src3)))]>, OpSize;
4427 let Predicates = [HasAVX] in
4428 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4429 let Constraints = "$src1 = $dst" in
4430 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4432 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4433 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4434 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4436 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4438 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4440 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4442 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4443 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4445 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4447 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4449 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4450 imm:$src3)))]>, OpSize;
4453 let Predicates = [HasAVX] in
4454 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4455 let Constraints = "$src1 = $dst" in
4456 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4458 // insertps has a few different modes, there's the first two here below which
4459 // are optimized inserts that won't zero arbitrary elements in the destination
4460 // vector. The next one matches the intrinsic and could zero arbitrary elements
4461 // in the target vector.
4462 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4463 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4464 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4466 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4468 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4470 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4472 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4473 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4475 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4477 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4479 (X86insrtps VR128:$src1,
4480 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4481 imm:$src3))]>, OpSize;
4484 let Constraints = "$src1 = $dst" in
4485 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4486 let Predicates = [HasAVX] in
4487 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4489 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4490 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4492 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4493 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4494 Requires<[HasSSE41]>;
4496 //===----------------------------------------------------------------------===//
4497 // SSE4.1 - Round Instructions
4498 //===----------------------------------------------------------------------===//
4500 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4501 X86MemOperand x86memop, RegisterClass RC,
4502 PatFrag mem_frag32, PatFrag mem_frag64,
4503 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4504 // Intrinsic operation, reg.
4505 // Vector intrinsic operation, reg
4506 def PSr : SS4AIi8<opcps, MRMSrcReg,
4507 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4508 !strconcat(OpcodeStr,
4509 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4510 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4513 // Vector intrinsic operation, mem
4514 def PSm : Ii8<opcps, MRMSrcMem,
4515 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4516 !strconcat(OpcodeStr,
4517 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4519 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4521 Requires<[HasSSE41]>;
4523 // Vector intrinsic operation, reg
4524 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4525 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4526 !strconcat(OpcodeStr,
4527 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4528 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4531 // Vector intrinsic operation, mem
4532 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4533 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4534 !strconcat(OpcodeStr,
4535 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4541 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4542 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4543 // Intrinsic operation, reg.
4544 // Vector intrinsic operation, reg
4545 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4546 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4547 !strconcat(OpcodeStr,
4548 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4551 // Vector intrinsic operation, mem
4552 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4553 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4554 !strconcat(OpcodeStr,
4555 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4556 []>, TA, OpSize, Requires<[HasSSE41]>;
4558 // Vector intrinsic operation, reg
4559 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4560 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4561 !strconcat(OpcodeStr,
4562 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4565 // Vector intrinsic operation, mem
4566 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4567 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4568 !strconcat(OpcodeStr,
4569 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4573 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4576 Intrinsic F64Int, bit Is2Addr = 1> {
4577 // Intrinsic operation, reg.
4578 def SSr : SS4AIi8<opcss, MRMSrcReg,
4579 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4581 !strconcat(OpcodeStr,
4582 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4583 !strconcat(OpcodeStr,
4584 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4585 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4588 // Intrinsic operation, mem.
4589 def SSm : SS4AIi8<opcss, MRMSrcMem,
4590 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4592 !strconcat(OpcodeStr,
4593 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4594 !strconcat(OpcodeStr,
4595 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4597 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4600 // Intrinsic operation, reg.
4601 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4602 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4604 !strconcat(OpcodeStr,
4605 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4606 !strconcat(OpcodeStr,
4607 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4608 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4611 // Intrinsic operation, mem.
4612 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4613 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4615 !strconcat(OpcodeStr,
4616 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4617 !strconcat(OpcodeStr,
4618 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4620 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4624 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4626 // Intrinsic operation, reg.
4627 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4628 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4629 !strconcat(OpcodeStr,
4630 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4633 // Intrinsic operation, mem.
4634 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4635 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4636 !strconcat(OpcodeStr,
4637 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4640 // Intrinsic operation, reg.
4641 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4642 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4643 !strconcat(OpcodeStr,
4644 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4647 // Intrinsic operation, mem.
4648 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4649 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4650 !strconcat(OpcodeStr,
4651 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4655 // FP round - roundss, roundps, roundsd, roundpd
4656 let Predicates = [HasAVX] in {
4658 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4659 memopv4f32, memopv2f64,
4660 int_x86_sse41_round_ps,
4661 int_x86_sse41_round_pd>, VEX;
4662 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4663 memopv8f32, memopv4f64,
4664 int_x86_avx_round_ps_256,
4665 int_x86_avx_round_pd_256>, VEX;
4666 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4667 int_x86_sse41_round_ss,
4668 int_x86_sse41_round_sd, 0>, VEX_4V;
4670 // Instructions for the assembler
4671 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4673 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4675 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4678 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4679 memopv4f32, memopv2f64,
4680 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4681 let Constraints = "$src1 = $dst" in
4682 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4683 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4685 //===----------------------------------------------------------------------===//
4686 // SSE4.1 - Packed Bit Test
4687 //===----------------------------------------------------------------------===//
4689 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4690 // the intel intrinsic that corresponds to this.
4691 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4692 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4693 "vptest\t{$src2, $src1|$src1, $src2}",
4694 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4696 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4697 "vptest\t{$src2, $src1|$src1, $src2}",
4698 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4701 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4702 "vptest\t{$src2, $src1|$src1, $src2}",
4703 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4705 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4706 "vptest\t{$src2, $src1|$src1, $src2}",
4707 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4711 let Defs = [EFLAGS] in {
4712 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4713 "ptest \t{$src2, $src1|$src1, $src2}",
4714 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4716 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4717 "ptest \t{$src2, $src1|$src1, $src2}",
4718 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4722 // The bit test instructions below are AVX only
4723 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4724 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4725 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4726 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4727 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4728 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4729 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4730 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4734 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4735 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4736 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4737 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4738 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4741 //===----------------------------------------------------------------------===//
4742 // SSE4.1 - Misc Instructions
4743 //===----------------------------------------------------------------------===//
4745 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4746 "popcnt{w}\t{$src, $dst|$dst, $src}",
4747 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4748 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4749 "popcnt{w}\t{$src, $dst|$dst, $src}",
4750 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4752 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4753 "popcnt{l}\t{$src, $dst|$dst, $src}",
4754 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4755 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4756 "popcnt{l}\t{$src, $dst|$dst, $src}",
4757 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4759 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4760 "popcnt{q}\t{$src, $dst|$dst, $src}",
4761 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4762 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4763 "popcnt{q}\t{$src, $dst|$dst, $src}",
4764 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4768 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4769 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4770 Intrinsic IntId128> {
4771 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4773 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4774 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4775 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4780 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4783 let Predicates = [HasAVX] in
4784 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4785 int_x86_sse41_phminposuw>, VEX;
4786 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4787 int_x86_sse41_phminposuw>;
4789 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4790 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4791 Intrinsic IntId128, bit Is2Addr = 1> {
4792 let isCommutable = 1 in
4793 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4794 (ins VR128:$src1, VR128:$src2),
4796 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4797 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4798 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4799 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4800 (ins VR128:$src1, i128mem:$src2),
4802 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4805 (IntId128 VR128:$src1,
4806 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4809 let Predicates = [HasAVX] in {
4810 let isCommutable = 0 in
4811 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4813 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4815 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4817 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4819 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4821 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4823 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4825 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4827 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4829 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4831 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4835 let Constraints = "$src1 = $dst" in {
4836 let isCommutable = 0 in
4837 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4838 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4839 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4840 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4841 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4842 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4843 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4844 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4845 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4846 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4847 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4850 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4851 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4852 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4853 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4855 /// SS48I_binop_rm - Simple SSE41 binary operator.
4856 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4857 ValueType OpVT, bit Is2Addr = 1> {
4858 let isCommutable = 1 in
4859 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4860 (ins VR128:$src1, VR128:$src2),
4862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4864 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4866 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4867 (ins VR128:$src1, i128mem:$src2),
4869 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4870 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4871 [(set VR128:$dst, (OpNode VR128:$src1,
4872 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4876 let Predicates = [HasAVX] in
4877 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4878 let Constraints = "$src1 = $dst" in
4879 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4881 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4882 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4883 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4884 X86MemOperand x86memop, bit Is2Addr = 1> {
4885 let isCommutable = 1 in
4886 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4887 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
4889 !strconcat(OpcodeStr,
4890 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4891 !strconcat(OpcodeStr,
4892 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4893 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4895 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4896 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
4898 !strconcat(OpcodeStr,
4899 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4900 !strconcat(OpcodeStr,
4901 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4904 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4908 let Predicates = [HasAVX] in {
4909 let isCommutable = 0 in {
4910 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4911 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4912 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4913 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4914 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4915 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4916 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4917 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4918 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4919 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4920 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4921 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4923 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4924 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4925 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4926 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4927 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4928 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4931 let Constraints = "$src1 = $dst" in {
4932 let isCommutable = 0 in {
4933 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4934 VR128, memopv16i8, i128mem>;
4935 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4936 VR128, memopv16i8, i128mem>;
4937 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4938 VR128, memopv16i8, i128mem>;
4939 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4940 VR128, memopv16i8, i128mem>;
4942 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4943 VR128, memopv16i8, i128mem>;
4944 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4945 VR128, memopv16i8, i128mem>;
4948 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4949 let Predicates = [HasAVX] in {
4950 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4951 RegisterClass RC, X86MemOperand x86memop,
4952 PatFrag mem_frag, Intrinsic IntId> {
4953 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4954 (ins RC:$src1, RC:$src2, RC:$src3),
4955 !strconcat(OpcodeStr,
4956 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4957 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4958 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4960 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4961 (ins RC:$src1, x86memop:$src2, RC:$src3),
4962 !strconcat(OpcodeStr,
4963 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4965 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4967 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4971 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4972 memopv16i8, int_x86_sse41_blendvpd>;
4973 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4974 memopv16i8, int_x86_sse41_blendvps>;
4975 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4976 memopv16i8, int_x86_sse41_pblendvb>;
4977 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4978 memopv32i8, int_x86_avx_blendv_pd_256>;
4979 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4980 memopv32i8, int_x86_avx_blendv_ps_256>;
4982 /// SS41I_ternary_int - SSE 4.1 ternary operator
4983 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4984 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4985 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4986 (ins VR128:$src1, VR128:$src2),
4987 !strconcat(OpcodeStr,
4988 "\t{$src2, $dst|$dst, $src2}"),
4989 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4992 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4993 (ins VR128:$src1, i128mem:$src2),
4994 !strconcat(OpcodeStr,
4995 "\t{$src2, $dst|$dst, $src2}"),
4998 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5002 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5003 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5004 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5006 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
5007 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5009 let Predicates = [HasAVX] in
5010 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5011 "vmovntdqa\t{$src, $dst|$dst, $src}",
5012 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5014 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5015 "movntdqa\t{$src, $dst|$dst, $src}",
5016 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5019 //===----------------------------------------------------------------------===//
5020 // SSE4.2 - Compare Instructions
5021 //===----------------------------------------------------------------------===//
5023 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5024 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5025 Intrinsic IntId128, bit Is2Addr = 1> {
5026 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5027 (ins VR128:$src1, VR128:$src2),
5029 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5031 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5033 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5034 (ins VR128:$src1, i128mem:$src2),
5036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5039 (IntId128 VR128:$src1,
5040 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5043 let Predicates = [HasAVX] in
5044 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5046 let Constraints = "$src1 = $dst" in
5047 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5049 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5050 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5051 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5052 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5054 //===----------------------------------------------------------------------===//
5055 // SSE4.2 - String/text Processing Instructions
5056 //===----------------------------------------------------------------------===//
5058 // Packed Compare Implicit Length Strings, Return Mask
5059 multiclass pseudo_pcmpistrm<string asm> {
5060 def REG : PseudoI<(outs VR128:$dst),
5061 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5062 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5064 def MEM : PseudoI<(outs VR128:$dst),
5065 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5066 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5067 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5070 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5071 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5072 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5075 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5076 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5077 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5078 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5079 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5080 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5081 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5084 let Defs = [XMM0, EFLAGS] in {
5085 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5086 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5087 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5088 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5089 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5090 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5093 // Packed Compare Explicit Length Strings, Return Mask
5094 multiclass pseudo_pcmpestrm<string asm> {
5095 def REG : PseudoI<(outs VR128:$dst),
5096 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5097 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5098 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5099 def MEM : PseudoI<(outs VR128:$dst),
5100 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5101 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5102 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5105 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5106 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5107 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5110 let Predicates = [HasAVX],
5111 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5112 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5113 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5114 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5115 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5116 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5117 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5120 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5121 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5122 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5123 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5124 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5125 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5126 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5129 // Packed Compare Implicit Length Strings, Return Index
5130 let Defs = [ECX, EFLAGS] in {
5131 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5132 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5133 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5134 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5135 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5136 (implicit EFLAGS)]>, OpSize;
5137 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5138 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5139 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5140 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5141 (implicit EFLAGS)]>, OpSize;
5145 let Predicates = [HasAVX] in {
5146 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5148 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5150 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5152 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5154 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5156 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5160 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5161 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5162 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5163 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5164 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5165 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5167 // Packed Compare Explicit Length Strings, Return Index
5168 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5169 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5170 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5171 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5172 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5173 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5174 (implicit EFLAGS)]>, OpSize;
5175 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5176 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5177 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5179 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5180 (implicit EFLAGS)]>, OpSize;
5184 let Predicates = [HasAVX] in {
5185 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5187 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5189 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5191 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5193 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5195 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5199 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5200 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5201 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5202 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5203 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5204 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5206 //===----------------------------------------------------------------------===//
5207 // SSE4.2 - CRC Instructions
5208 //===----------------------------------------------------------------------===//
5210 // No CRC instructions have AVX equivalents
5212 // crc intrinsic instruction
5213 // This set of instructions are only rm, the only difference is the size
5215 let Constraints = "$src1 = $dst" in {
5216 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5217 (ins GR32:$src1, i8mem:$src2),
5218 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5220 (int_x86_sse42_crc32_32_8 GR32:$src1,
5221 (load addr:$src2)))]>;
5222 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5223 (ins GR32:$src1, GR8:$src2),
5224 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5226 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5227 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5228 (ins GR32:$src1, i16mem:$src2),
5229 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5231 (int_x86_sse42_crc32_32_16 GR32:$src1,
5232 (load addr:$src2)))]>,
5234 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5235 (ins GR32:$src1, GR16:$src2),
5236 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5238 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5240 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5241 (ins GR32:$src1, i32mem:$src2),
5242 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5244 (int_x86_sse42_crc32_32_32 GR32:$src1,
5245 (load addr:$src2)))]>;
5246 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5247 (ins GR32:$src1, GR32:$src2),
5248 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5250 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5251 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5252 (ins GR64:$src1, i8mem:$src2),
5253 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5255 (int_x86_sse42_crc32_64_8 GR64:$src1,
5256 (load addr:$src2)))]>,
5258 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5259 (ins GR64:$src1, GR8:$src2),
5260 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5262 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5264 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5265 (ins GR64:$src1, i64mem:$src2),
5266 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5268 (int_x86_sse42_crc32_64_64 GR64:$src1,
5269 (load addr:$src2)))]>,
5271 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5272 (ins GR64:$src1, GR64:$src2),
5273 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5275 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5279 //===----------------------------------------------------------------------===//
5280 // AES-NI Instructions
5281 //===----------------------------------------------------------------------===//
5283 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5284 Intrinsic IntId128, bit Is2Addr = 1> {
5285 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5286 (ins VR128:$src1, VR128:$src2),
5288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5290 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5292 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5293 (ins VR128:$src1, i128mem:$src2),
5295 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5296 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5298 (IntId128 VR128:$src1,
5299 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5302 // Perform One Round of an AES Encryption/Decryption Flow
5303 let Predicates = [HasAVX, HasAES] in {
5304 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5305 int_x86_aesni_aesenc, 0>, VEX_4V;
5306 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5307 int_x86_aesni_aesenclast, 0>, VEX_4V;
5308 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5309 int_x86_aesni_aesdec, 0>, VEX_4V;
5310 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5311 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5314 let Constraints = "$src1 = $dst" in {
5315 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5316 int_x86_aesni_aesenc>;
5317 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5318 int_x86_aesni_aesenclast>;
5319 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5320 int_x86_aesni_aesdec>;
5321 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5322 int_x86_aesni_aesdeclast>;
5325 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5326 (AESENCrr VR128:$src1, VR128:$src2)>;
5327 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5328 (AESENCrm VR128:$src1, addr:$src2)>;
5329 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5330 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5331 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5332 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5333 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5334 (AESDECrr VR128:$src1, VR128:$src2)>;
5335 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5336 (AESDECrm VR128:$src1, addr:$src2)>;
5337 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5338 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5339 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5340 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5342 // Perform the AES InvMixColumn Transformation
5343 let Predicates = [HasAVX, HasAES] in {
5344 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5346 "vaesimc\t{$src1, $dst|$dst, $src1}",
5348 (int_x86_aesni_aesimc VR128:$src1))]>,
5350 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5351 (ins i128mem:$src1),
5352 "vaesimc\t{$src1, $dst|$dst, $src1}",
5354 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5357 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5359 "aesimc\t{$src1, $dst|$dst, $src1}",
5361 (int_x86_aesni_aesimc VR128:$src1))]>,
5363 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5364 (ins i128mem:$src1),
5365 "aesimc\t{$src1, $dst|$dst, $src1}",
5367 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5370 // AES Round Key Generation Assist
5371 let Predicates = [HasAVX, HasAES] in {
5372 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5373 (ins VR128:$src1, i8imm:$src2),
5374 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5376 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5378 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5379 (ins i128mem:$src1, i8imm:$src2),
5380 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5382 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5386 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5387 (ins VR128:$src1, i8imm:$src2),
5388 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5390 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5392 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5393 (ins i128mem:$src1, i8imm:$src2),
5394 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5396 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5400 //===----------------------------------------------------------------------===//
5401 // CLMUL Instructions
5402 //===----------------------------------------------------------------------===//
5404 // Carry-less Multiplication instructions
5405 let Constraints = "$src1 = $dst" in {
5406 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5407 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5408 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5411 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5412 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5413 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5417 // AVX carry-less Multiplication instructions
5418 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5419 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5420 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5423 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5424 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5425 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5429 multiclass pclmul_alias<string asm, int immop> {
5430 def : InstAlias<!strconcat("pclmul", asm,
5431 "dq {$src, $dst|$dst, $src}"),
5432 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5434 def : InstAlias<!strconcat("pclmul", asm,
5435 "dq {$src, $dst|$dst, $src}"),
5436 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5438 def : InstAlias<!strconcat("vpclmul", asm,
5439 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5440 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5442 def : InstAlias<!strconcat("vpclmul", asm,
5443 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5444 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5446 defm : pclmul_alias<"hqhq", 0x11>;
5447 defm : pclmul_alias<"hqlq", 0x01>;
5448 defm : pclmul_alias<"lqhq", 0x10>;
5449 defm : pclmul_alias<"lqlq", 0x00>;
5451 //===----------------------------------------------------------------------===//
5453 //===----------------------------------------------------------------------===//
5455 //===----------------------------------------------------------------------===//
5456 // VBROADCAST - Load from memory and broadcast to all elements of the
5457 // destination operand
5459 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5460 X86MemOperand x86memop, Intrinsic Int> :
5461 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5462 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5463 [(set RC:$dst, (Int addr:$src))]>, VEX;
5465 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5466 int_x86_avx_vbroadcastss>;
5467 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5468 int_x86_avx_vbroadcastss_256>;
5469 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5470 int_x86_avx_vbroadcast_sd_256>;
5471 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5472 int_x86_avx_vbroadcastf128_pd_256>;
5474 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5475 (VBROADCASTF128 addr:$src)>;
5477 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
5478 (VBROADCASTSSY addr:$src)>;
5479 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
5480 (VBROADCASTSD addr:$src)>;
5481 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
5482 (VBROADCASTSSY addr:$src)>;
5483 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
5484 (VBROADCASTSD addr:$src)>;
5486 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
5487 (VBROADCASTSS addr:$src)>;
5488 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
5489 (VBROADCASTSS addr:$src)>;
5491 //===----------------------------------------------------------------------===//
5492 // VINSERTF128 - Insert packed floating-point values
5494 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5495 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5496 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5498 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5499 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5500 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5503 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5504 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5505 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5506 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5507 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5508 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5510 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5512 (VINSERTF128rr VR256:$src1, VR128:$src2,
5513 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5514 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5516 (VINSERTF128rr VR256:$src1, VR128:$src2,
5517 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5518 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5520 (VINSERTF128rr VR256:$src1, VR128:$src2,
5521 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5522 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5524 (VINSERTF128rr VR256:$src1, VR128:$src2,
5525 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5526 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5528 (VINSERTF128rr VR256:$src1, VR128:$src2,
5529 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5530 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5532 (VINSERTF128rr VR256:$src1, VR128:$src2,
5533 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5535 // Special COPY patterns
5536 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5537 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5538 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5539 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5540 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5541 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5542 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5543 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5544 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5545 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5546 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5547 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5549 //===----------------------------------------------------------------------===//
5550 // VEXTRACTF128 - Extract packed floating-point values
5552 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5553 (ins VR256:$src1, i8imm:$src2),
5554 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5556 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5557 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5558 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5561 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5562 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5563 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5564 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5565 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5566 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5568 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5569 (v4f32 (VEXTRACTF128rr
5570 (v8f32 VR256:$src1),
5571 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5572 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5573 (v2f64 (VEXTRACTF128rr
5574 (v4f64 VR256:$src1),
5575 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5576 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5577 (v4i32 (VEXTRACTF128rr
5578 (v8i32 VR256:$src1),
5579 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5580 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5581 (v2i64 (VEXTRACTF128rr
5582 (v4i64 VR256:$src1),
5583 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5584 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5585 (v8i16 (VEXTRACTF128rr
5586 (v16i16 VR256:$src1),
5587 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5588 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5589 (v16i8 (VEXTRACTF128rr
5590 (v32i8 VR256:$src1),
5591 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5593 // Special COPY patterns
5594 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5595 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5596 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5597 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5599 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5600 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5601 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5602 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5605 //===----------------------------------------------------------------------===//
5606 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5608 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5609 Intrinsic IntLd, Intrinsic IntLd256,
5610 Intrinsic IntSt, Intrinsic IntSt256,
5611 PatFrag pf128, PatFrag pf256> {
5612 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5613 (ins VR128:$src1, f128mem:$src2),
5614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5615 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5617 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5618 (ins VR256:$src1, f256mem:$src2),
5619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5620 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5622 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5623 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5624 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5625 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5626 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5627 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5629 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5632 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5633 int_x86_avx_maskload_ps,
5634 int_x86_avx_maskload_ps_256,
5635 int_x86_avx_maskstore_ps,
5636 int_x86_avx_maskstore_ps_256,
5637 memopv4f32, memopv8f32>;
5638 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5639 int_x86_avx_maskload_pd,
5640 int_x86_avx_maskload_pd_256,
5641 int_x86_avx_maskstore_pd,
5642 int_x86_avx_maskstore_pd_256,
5643 memopv2f64, memopv4f64>;
5645 //===----------------------------------------------------------------------===//
5646 // VPERMIL - Permute Single and Double Floating-Point Values
5648 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5649 RegisterClass RC, X86MemOperand x86memop_f,
5650 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5651 Intrinsic IntVar, Intrinsic IntImm> {
5652 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5653 (ins RC:$src1, RC:$src2),
5654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5655 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5656 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5657 (ins RC:$src1, x86memop_i:$src2),
5658 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5659 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5661 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5662 (ins RC:$src1, i8imm:$src2),
5663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5664 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5665 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5666 (ins x86memop_f:$src1, i8imm:$src2),
5667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5668 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5671 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5672 memopv4f32, memopv4i32,
5673 int_x86_avx_vpermilvar_ps,
5674 int_x86_avx_vpermil_ps>;
5675 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5676 memopv8f32, memopv8i32,
5677 int_x86_avx_vpermilvar_ps_256,
5678 int_x86_avx_vpermil_ps_256>;
5679 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5680 memopv2f64, memopv2i64,
5681 int_x86_avx_vpermilvar_pd,
5682 int_x86_avx_vpermil_pd>;
5683 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5684 memopv4f64, memopv4i64,
5685 int_x86_avx_vpermilvar_pd_256,
5686 int_x86_avx_vpermil_pd_256>;
5688 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5689 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5690 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5691 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5692 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5693 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5694 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5695 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5697 //===----------------------------------------------------------------------===//
5698 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
5700 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5701 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5702 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5704 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5705 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5706 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5709 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5710 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5711 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5712 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5713 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5714 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5716 def : Pat<(int_x86_avx_vperm2f128_ps_256
5717 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5718 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5719 def : Pat<(int_x86_avx_vperm2f128_pd_256
5720 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5721 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5722 def : Pat<(int_x86_avx_vperm2f128_si_256
5723 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5724 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5726 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5727 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5728 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5729 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5730 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5731 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5732 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5733 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5734 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5735 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5736 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5737 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5739 //===----------------------------------------------------------------------===//
5740 // VZERO - Zero YMM registers
5742 // Zero All YMM registers
5743 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5744 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5746 // Zero Upper bits of YMM registers
5747 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5748 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5750 //===----------------------------------------------------------------------===//
5751 // SSE Shuffle pattern fragments
5752 //===----------------------------------------------------------------------===//
5754 // This is part of a "work in progress" refactoring. The idea is that all
5755 // vector shuffles are going to be translated into target specific nodes and
5756 // directly matched by the patterns below (which can be changed along the way)
5757 // The AVX version of some but not all of them are described here, and more
5758 // should come in a near future.
5760 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5761 // SSE2 loads, which are always promoted to v2i64. The last one should match
5762 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5763 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5764 // we investigate further.
5765 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5767 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5768 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5770 (PSHUFDmi addr:$src1, imm:$imm)>;
5771 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5773 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5775 // Shuffle with PSHUFD instruction.
5776 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5777 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5778 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5779 (PSHUFDri VR128:$src1, imm:$imm)>;
5781 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5782 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5783 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5784 (PSHUFDri VR128:$src1, imm:$imm)>;
5786 // Shuffle with SHUFPD instruction.
5787 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5788 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5789 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5790 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5791 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5792 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5794 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5795 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5796 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5797 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5799 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5800 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5801 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5802 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5804 // Shuffle with SHUFPS instruction.
5805 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5806 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5807 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5808 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5809 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5810 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5812 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5813 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5814 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5815 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5817 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5818 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5819 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5820 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5821 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5822 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5824 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5825 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5826 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5827 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5829 // Shuffle with MOVHLPS instruction
5830 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5831 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5832 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5833 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5835 // Shuffle with MOVDDUP instruction
5836 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5837 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5838 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5839 (MOVDDUPrm addr:$src)>;
5841 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5842 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5843 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5844 (MOVDDUPrm addr:$src)>;
5846 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5847 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5848 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5849 (MOVDDUPrm addr:$src)>;
5851 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5852 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5853 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5854 (MOVDDUPrm addr:$src)>;
5856 def : Pat<(X86Movddup (bc_v2f64
5857 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5858 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5859 def : Pat<(X86Movddup (bc_v2f64
5860 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5861 (MOVDDUPrm addr:$src)>;
5864 // Shuffle with UNPCKLPS
5865 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5866 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5867 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5868 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5870 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5871 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5872 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5873 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5875 // Shuffle with VUNPCKHPSY
5876 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5877 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5878 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5879 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5880 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5881 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5882 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
5883 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5885 // Shuffle with UNPCKHPS
5886 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5887 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5888 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5889 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5891 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5892 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5893 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5894 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5896 // Shuffle with VUNPCKHPSY
5897 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
5898 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5899 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5900 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5902 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
5903 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5904 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5905 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5907 // Shuffle with UNPCKLPD
5908 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5909 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5910 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5911 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5913 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5914 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5915 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5916 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5918 // Shuffle with VUNPCKLPDY
5919 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5920 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5921 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5922 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5924 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
5925 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5926 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5927 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5929 // Shuffle with UNPCKHPD
5930 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5931 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5932 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5933 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5935 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5936 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5937 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5938 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5940 // Shuffle with VUNPCKHPDY
5941 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
5942 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5943 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5944 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5945 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
5946 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5947 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5948 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5950 // Shuffle with MOVLHPS
5951 def : Pat<(X86Movlhps VR128:$src1,
5952 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5953 (MOVHPSrm VR128:$src1, addr:$src2)>;
5954 def : Pat<(X86Movlhps VR128:$src1,
5955 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5956 (MOVHPSrm VR128:$src1, addr:$src2)>;
5957 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5958 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5959 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5960 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5961 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5962 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5964 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5965 // is during lowering, where it's not possible to recognize the load fold cause
5966 // it has two uses through a bitcast. One use disappears at isel time and the
5967 // fold opportunity reappears.
5968 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5969 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5971 // Shuffle with MOVLHPD
5972 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5973 (scalar_to_vector (loadf64 addr:$src2)))),
5974 (MOVHPDrm VR128:$src1, addr:$src2)>;
5976 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5977 // is during lowering, where it's not possible to recognize the load fold cause
5978 // it has two uses through a bitcast. One use disappears at isel time and the
5979 // fold opportunity reappears.
5980 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5981 (scalar_to_vector (loadf64 addr:$src2)))),
5982 (MOVHPDrm VR128:$src1, addr:$src2)>;
5984 // Shuffle with MOVSS
5985 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5986 (MOVSSrr VR128:$src1, FR32:$src2)>;
5987 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5988 (MOVSSrr (v4i32 VR128:$src1),
5989 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5990 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5991 (MOVSSrr (v4f32 VR128:$src1),
5992 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5994 // Shuffle with MOVSD
5995 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5996 (MOVSDrr VR128:$src1, FR64:$src2)>;
5997 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5998 (MOVSDrr (v2i64 VR128:$src1),
5999 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
6000 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
6001 (MOVSDrr (v2f64 VR128:$src1),
6002 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
6003 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
6004 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6005 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
6006 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6008 // Shuffle with PSHUFHW
6009 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
6010 (PSHUFHWri VR128:$src, imm:$imm)>;
6011 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
6012 (PSHUFHWmi addr:$src, imm:$imm)>;
6014 // Shuffle with PSHUFLW
6015 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
6016 (PSHUFLWri VR128:$src, imm:$imm)>;
6017 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
6018 (PSHUFLWmi addr:$src, imm:$imm)>;
6020 // Shuffle with MOVLPS
6021 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
6022 (MOVLPSrm VR128:$src1, addr:$src2)>;
6023 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
6024 (MOVLPSrm VR128:$src1, addr:$src2)>;
6025 def : Pat<(X86Movlps VR128:$src1,
6026 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
6027 (MOVLPSrm VR128:$src1, addr:$src2)>;
6028 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
6029 // is during lowering, where it's not possible to recognize the load fold cause
6030 // it has two uses through a bitcast. One use disappears at isel time and the
6031 // fold opportunity reappears.
6032 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
6033 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6035 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
6036 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6038 // Shuffle with MOVLPD
6039 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6040 (MOVLPDrm VR128:$src1, addr:$src2)>;
6041 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6042 (MOVLPDrm VR128:$src1, addr:$src2)>;
6043 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6044 (scalar_to_vector (loadf64 addr:$src2)))),
6045 (MOVLPDrm VR128:$src1, addr:$src2)>;
6047 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6048 def : Pat<(store (f64 (vector_extract
6049 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6050 (MOVHPSmr addr:$dst, VR128:$src)>;
6051 def : Pat<(store (f64 (vector_extract
6052 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6053 (MOVHPDmr addr:$dst, VR128:$src)>;
6055 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6056 (MOVLPSmr addr:$src1, VR128:$src2)>;
6057 def : Pat<(store (v4i32 (X86Movlps
6058 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6059 (MOVLPSmr addr:$src1, VR128:$src2)>;
6061 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6062 (MOVLPDmr addr:$src1, VR128:$src2)>;
6063 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6064 (MOVLPDmr addr:$src1, VR128:$src2)>;