1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag>, neverHasSideEffects = 1 in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
1636 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1637 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1638 SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
1642 let Pattern = []<dag>, neverHasSideEffects = 1 in {
1643 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1644 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1645 SSE_CVT_SS2SI_32>, XS;
1646 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1647 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1648 SSE_CVT_SS2SI_64>, XS, REX_W;
1649 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1650 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1651 SSEPackedSingle, SSE_CVT_PS>, TB,
1652 Requires<[HasSSE2]>;
1655 let Predicates = [HasAVX] in {
1656 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1657 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1658 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1659 (VCVTSS2SIrm addr:$src)>;
1660 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1661 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1662 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1663 (VCVTSS2SI64rm addr:$src)>;
1666 let Predicates = [HasSSE1] in {
1667 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1668 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1669 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1670 (CVTSS2SIrm addr:$src)>;
1671 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1672 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1673 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1674 (CVTSS2SI64rm addr:$src)>;
1679 // Convert scalar double to scalar single
1680 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1681 (ins FR64:$src1, FR64:$src2),
1682 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1683 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1685 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1686 (ins FR64:$src1, f64mem:$src2),
1687 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1688 [], IIC_SSE_CVT_Scalar_RM>,
1689 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1691 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1694 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1695 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1696 [(set FR32:$dst, (fround FR64:$src))],
1697 IIC_SSE_CVT_Scalar_RR>;
1698 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1699 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1700 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1701 IIC_SSE_CVT_Scalar_RM>,
1703 Requires<[HasSSE2, OptForSize]>;
1705 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1706 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1709 let Constraints = "$src1 = $dst" in
1710 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1711 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1712 SSE_CVT_Scalar>, XS;
1714 // Convert scalar single to scalar double
1715 // SSE2 instructions with XS prefix
1716 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1717 (ins FR32:$src1, FR32:$src2),
1718 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1719 [], IIC_SSE_CVT_Scalar_RR>,
1720 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1722 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1723 (ins FR32:$src1, f32mem:$src2),
1724 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1725 [], IIC_SSE_CVT_Scalar_RM>,
1726 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1728 let Predicates = [HasAVX] in {
1729 def : Pat<(f64 (fextend FR32:$src)),
1730 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1731 def : Pat<(fextend (loadf32 addr:$src)),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1733 def : Pat<(extloadf32 addr:$src),
1734 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1737 def : Pat<(extloadf32 addr:$src),
1738 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1739 Requires<[HasAVX, OptForSpeed]>;
1741 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1742 "cvtss2sd\t{$src, $dst|$dst, $src}",
1743 [(set FR64:$dst, (fextend FR32:$src))],
1744 IIC_SSE_CVT_Scalar_RR>, XS,
1745 Requires<[HasSSE2]>;
1746 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1747 "cvtss2sd\t{$src, $dst|$dst, $src}",
1748 [(set FR64:$dst, (extloadf32 addr:$src))],
1749 IIC_SSE_CVT_Scalar_RM>, XS,
1750 Requires<[HasSSE2, OptForSize]>;
1752 // extload f32 -> f64. This matches load+fextend because we have a hack in
1753 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1755 // Since these loads aren't folded into the fextend, we have to match it
1757 def : Pat<(fextend (loadf32 addr:$src)),
1758 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1759 def : Pat<(extloadf32 addr:$src),
1760 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1762 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1764 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1765 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1767 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1769 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1770 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1771 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1772 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1773 (load addr:$src2)))],
1774 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1776 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1777 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1778 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1779 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1780 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1782 IIC_SSE_CVT_Scalar_RR>, XS,
1783 Requires<[HasSSE2]>;
1784 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1785 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1786 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1787 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1788 (load addr:$src2)))],
1789 IIC_SSE_CVT_Scalar_RM>, XS,
1790 Requires<[HasSSE2]>;
1793 // Convert packed single/double fp to doubleword
1794 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1796 IIC_SSE_CVT_PS_RR>, VEX;
1797 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1798 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1799 IIC_SSE_CVT_PS_RM>, VEX;
1800 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1801 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1802 IIC_SSE_CVT_PS_RR>, VEX;
1803 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1804 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1805 IIC_SSE_CVT_PS_RM>, VEX;
1806 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1807 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1809 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1810 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1813 let Predicates = [HasAVX] in {
1814 def : Pat<(int_x86_sse2_cvtps2dq VR128:$src),
1815 (VCVTPS2DQrr VR128:$src)>;
1816 def : Pat<(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)),
1817 (VCVTPS2DQrm addr:$src)>;
1820 let Predicates = [HasSSE2] in {
1821 def : Pat<(int_x86_sse2_cvtps2dq VR128:$src),
1822 (CVTPS2DQrr VR128:$src)>;
1823 def : Pat<(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)),
1824 (CVTPS2DQrm addr:$src)>;
1827 // Convert Packed Double FP to Packed DW Integers
1828 let Predicates = [HasAVX] in {
1829 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1830 // register, but the same isn't true when using memory operands instead.
1831 // Provide other assembly rr and rm forms to address this explicitly.
1832 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1833 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1834 def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1835 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1838 def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1839 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1840 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1841 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1844 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1845 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
1846 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1847 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1850 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1851 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1853 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1854 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1857 let Predicates = [HasAVX] in {
1858 def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
1859 (VCVTPD2DQrr VR128:$src)>;
1860 def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
1861 (VCVTPD2DQXrm addr:$src)>;
1864 let Predicates = [HasSSE2] in {
1865 def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
1866 (CVTPD2DQrr VR128:$src)>;
1867 def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
1868 (CVTPD2DQrm addr:$src)>;
1871 // Convert with truncation packed single/double fp to doubleword
1872 // SSE2 packed instructions with XS prefix
1873 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1874 "cvttps2dq\t{$src, $dst|$dst, $src}",
1876 (int_x86_sse2_cvttps2dq VR128:$src))],
1877 IIC_SSE_CVT_PS_RR>, VEX;
1878 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1879 "cvttps2dq\t{$src, $dst|$dst, $src}",
1880 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1881 (memop addr:$src)))],
1882 IIC_SSE_CVT_PS_RM>, VEX;
1883 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1884 "cvttps2dq\t{$src, $dst|$dst, $src}",
1886 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1887 IIC_SSE_CVT_PS_RR>, VEX;
1888 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1889 "cvttps2dq\t{$src, $dst|$dst, $src}",
1890 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1891 (memopv8f32 addr:$src)))],
1892 IIC_SSE_CVT_PS_RM>, VEX;
1894 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvttps2dq\t{$src, $dst|$dst, $src}",
1897 (int_x86_sse2_cvttps2dq VR128:$src))],
1899 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1900 "cvttps2dq\t{$src, $dst|$dst, $src}",
1902 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1905 let Predicates = [HasAVX] in {
1906 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1907 (VCVTDQ2PSrr VR128:$src)>;
1908 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1909 (VCVTDQ2PSrm addr:$src)>;
1911 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1912 (VCVTDQ2PSrr VR128:$src)>;
1913 def : Pat<(int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))),
1914 (VCVTDQ2PSrm addr:$src)>;
1916 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1917 (VCVTTPS2DQrr VR128:$src)>;
1918 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1919 (VCVTTPS2DQrm addr:$src)>;
1921 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1922 (VCVTDQ2PSYrr VR256:$src)>;
1923 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1924 (VCVTDQ2PSYrm addr:$src)>;
1926 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1927 (VCVTTPS2DQYrr VR256:$src)>;
1928 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1929 (VCVTTPS2DQYrm addr:$src)>;
1932 let Predicates = [HasSSE2] in {
1933 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1934 (CVTDQ2PSrr VR128:$src)>;
1935 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1936 (CVTDQ2PSrm addr:$src)>;
1938 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1939 (CVTDQ2PSrr VR128:$src)>;
1940 def : Pat<(int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))),
1941 (CVTDQ2PSrm addr:$src)>;
1943 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1944 (CVTTPS2DQrr VR128:$src)>;
1945 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1946 (CVTTPS2DQrm addr:$src)>;
1949 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1952 (int_x86_sse2_cvttpd2dq VR128:$src))],
1953 IIC_SSE_CVT_PD_RR>, VEX;
1954 let isCodeGenOnly = 1 in
1955 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1958 (memop addr:$src)))],
1959 IIC_SSE_CVT_PD_RM>, VEX;
1960 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1961 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1962 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1964 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1965 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1966 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1967 (memop addr:$src)))],
1970 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1971 // register, but the same isn't true when using memory operands instead.
1972 // Provide other assembly rr and rm forms to address this explicitly.
1973 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1974 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
1975 IIC_SSE_CVT_PD_RR>, VEX;
1978 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1979 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1980 IIC_SSE_CVT_PD_RR>, VEX;
1981 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1982 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1983 IIC_SSE_CVT_PD_RM>, VEX;
1986 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1987 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1988 IIC_SSE_CVT_PD_RR>, VEX;
1989 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1990 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1991 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1993 let Predicates = [HasAVX] in {
1994 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1995 (VCVTTPD2DQYrr VR256:$src)>;
1996 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1997 (VCVTTPD2DQYrm addr:$src)>;
1998 } // Predicates = [HasAVX]
2000 // Convert packed single to packed double
2001 let Predicates = [HasAVX] in {
2002 // SSE2 instructions without OpSize prefix
2003 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2004 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2005 IIC_SSE_CVT_PD_RR>, TB, VEX;
2006 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2007 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2008 IIC_SSE_CVT_PD_RM>, TB, VEX;
2009 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2010 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2011 IIC_SSE_CVT_PD_RR>, TB, VEX;
2012 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2013 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2014 IIC_SSE_CVT_PD_RM>, TB, VEX;
2016 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2017 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2018 IIC_SSE_CVT_PD_RR>, TB;
2019 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2020 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2021 IIC_SSE_CVT_PD_RM>, TB;
2023 let Predicates = [HasAVX] in {
2024 def : Pat<(int_x86_sse2_cvtps2pd VR128:$src),
2025 (VCVTPS2PDrr VR128:$src)>;
2028 let Predicates = [HasSSE2] in {
2029 def : Pat<(int_x86_sse2_cvtps2pd VR128:$src),
2030 (CVTPS2PDrr VR128:$src)>;
2033 // Convert Packed DW Integers to Packed Double FP
2034 let Predicates = [HasAVX] in {
2035 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2036 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2037 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2038 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2039 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2040 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2041 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2042 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2045 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2046 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2048 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2049 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2052 // 128 bit register conversion intrinsics
2053 let Predicates = [HasAVX] in
2054 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2055 (VCVTDQ2PDrr VR128:$src)>;
2057 let Predicates = [HasSSE2] in
2058 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2059 (CVTDQ2PDrr VR128:$src)>;
2061 // AVX 256-bit register conversion intrinsics
2062 let Predicates = [HasAVX] in {
2063 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
2064 (VCVTDQ2PDYrr VR128:$src)>;
2065 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
2066 (VCVTDQ2PDYrm addr:$src)>;
2068 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
2069 (VCVTPD2DQYrr VR256:$src)>;
2070 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
2071 (VCVTPD2DQYrm addr:$src)>;
2073 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2074 (VCVTDQ2PDYrr VR128:$src)>;
2075 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2076 (VCVTDQ2PDYrm addr:$src)>;
2077 } // Predicates = [HasAVX]
2079 // Convert packed double to packed single
2080 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2081 // register, but the same isn't true when using memory operands instead.
2082 // Provide other assembly rr and rm forms to address this explicitly.
2083 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2084 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2085 IIC_SSE_CVT_PD_RR>, VEX;
2086 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2087 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2088 IIC_SSE_CVT_PD_RR>, VEX;
2091 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2092 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2093 IIC_SSE_CVT_PD_RR>, VEX;
2094 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2095 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2096 IIC_SSE_CVT_PD_RM>, VEX;
2099 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2100 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2101 IIC_SSE_CVT_PD_RR>, VEX;
2102 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2103 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2104 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2105 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2106 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2108 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2109 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2113 let Predicates = [HasAVX] in {
2114 def : Pat<(int_x86_sse2_cvtpd2ps VR128:$src),
2115 (VCVTPD2PSrr VR128:$src)>;
2116 def : Pat<(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)),
2117 (VCVTPD2PSXrm addr:$src)>;
2120 let Predicates = [HasSSE2] in {
2121 def : Pat<(int_x86_sse2_cvtpd2ps VR128:$src),
2122 (CVTPD2PSrr VR128:$src)>;
2123 def : Pat<(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)),
2124 (CVTPD2PSrm addr:$src)>;
2127 // AVX 256-bit register conversion intrinsics
2128 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2129 // whenever possible to avoid declaring two versions of each one.
2130 let Predicates = [HasAVX] in {
2131 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2132 (VCVTDQ2PSYrr VR256:$src)>;
2133 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2134 (VCVTDQ2PSYrm addr:$src)>;
2136 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2137 (VCVTPD2PSYrr VR256:$src)>;
2138 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2139 (VCVTPD2PSYrm addr:$src)>;
2141 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2142 (VCVTPS2DQYrr VR256:$src)>;
2143 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2144 (VCVTPS2DQYrm addr:$src)>;
2146 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2147 (VCVTPS2PDYrr VR128:$src)>;
2148 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2149 (VCVTPS2PDYrm addr:$src)>;
2151 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2152 (VCVTTPD2DQYrr VR256:$src)>;
2153 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2154 (VCVTTPD2DQYrm addr:$src)>;
2156 // Match fround and fextend for 128/256-bit conversions
2157 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2158 (VCVTPD2PSYrr VR256:$src)>;
2159 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2160 (VCVTPD2PSYrm addr:$src)>;
2162 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2163 (VCVTPS2PDYrr VR128:$src)>;
2164 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2165 (VCVTPS2PDYrm addr:$src)>;
2168 //===----------------------------------------------------------------------===//
2169 // SSE 1 & 2 - Compare Instructions
2170 //===----------------------------------------------------------------------===//
2172 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2173 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2174 Operand CC, SDNode OpNode, ValueType VT,
2175 PatFrag ld_frag, string asm, string asm_alt,
2177 def rr : SIi8<0xC2, MRMSrcReg,
2178 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2179 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2181 def rm : SIi8<0xC2, MRMSrcMem,
2182 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2183 [(set RC:$dst, (OpNode (VT RC:$src1),
2184 (ld_frag addr:$src2), imm:$cc))],
2187 // Accept explicit immediate argument form instead of comparison code.
2188 let neverHasSideEffects = 1 in {
2189 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2190 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2191 IIC_SSE_ALU_F32S_RR>;
2193 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2194 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2195 IIC_SSE_ALU_F32S_RM>;
2199 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2200 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2201 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2203 XS, VEX_4V, VEX_LIG;
2204 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2205 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2206 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2207 SSE_ALU_F32S>, // same latency as 32 bit compare
2208 XD, VEX_4V, VEX_LIG;
2210 let Constraints = "$src1 = $dst" in {
2211 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2212 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2213 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2215 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2216 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2217 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2218 SSE_ALU_F32S>, // same latency as 32 bit compare
2222 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2223 Intrinsic Int, string asm, OpndItins itins> {
2224 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2225 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2226 [(set VR128:$dst, (Int VR128:$src1,
2227 VR128:$src, imm:$cc))],
2229 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2230 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2231 [(set VR128:$dst, (Int VR128:$src1,
2232 (load addr:$src), imm:$cc))],
2236 // Aliases to match intrinsics which expect XMM operand(s).
2237 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2238 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2241 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2242 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2243 SSE_ALU_F32S>, // same latency as f32
2245 let Constraints = "$src1 = $dst" in {
2246 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2247 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2249 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2250 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2251 SSE_ALU_F32S>, // same latency as f32
2256 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2257 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2258 ValueType vt, X86MemOperand x86memop,
2259 PatFrag ld_frag, string OpcodeStr, Domain d> {
2260 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2261 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2262 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2263 IIC_SSE_COMIS_RR, d>;
2264 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2265 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2266 [(set EFLAGS, (OpNode (vt RC:$src1),
2267 (ld_frag addr:$src2)))],
2268 IIC_SSE_COMIS_RM, d>;
2271 let Defs = [EFLAGS] in {
2272 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2273 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2274 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2275 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2277 let Pattern = []<dag> in {
2278 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2279 "comiss", SSEPackedSingle>, TB, VEX,
2281 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2282 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2286 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2287 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2288 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2289 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2291 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2292 load, "comiss", SSEPackedSingle>, TB, VEX;
2293 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2294 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2295 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2296 "ucomiss", SSEPackedSingle>, TB;
2297 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2298 "ucomisd", SSEPackedDouble>, TB, OpSize;
2300 let Pattern = []<dag> in {
2301 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2302 "comiss", SSEPackedSingle>, TB;
2303 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2304 "comisd", SSEPackedDouble>, TB, OpSize;
2307 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2308 load, "ucomiss", SSEPackedSingle>, TB;
2309 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2310 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2312 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2313 "comiss", SSEPackedSingle>, TB;
2314 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2315 "comisd", SSEPackedDouble>, TB, OpSize;
2316 } // Defs = [EFLAGS]
2318 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2319 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2320 Operand CC, Intrinsic Int, string asm,
2321 string asm_alt, Domain d> {
2322 def rri : PIi8<0xC2, MRMSrcReg,
2323 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2324 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2325 IIC_SSE_CMPP_RR, d>;
2326 def rmi : PIi8<0xC2, MRMSrcMem,
2327 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2328 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2329 IIC_SSE_CMPP_RM, d>;
2331 // Accept explicit immediate argument form instead of comparison code.
2332 let neverHasSideEffects = 1 in {
2333 def rri_alt : PIi8<0xC2, MRMSrcReg,
2334 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2335 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2336 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2337 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2338 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2342 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2343 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2345 SSEPackedSingle>, TB, VEX_4V;
2346 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2347 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2348 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2349 SSEPackedDouble>, TB, OpSize, VEX_4V;
2350 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2351 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2352 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2353 SSEPackedSingle>, TB, VEX_4V;
2354 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2355 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2356 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2357 SSEPackedDouble>, TB, OpSize, VEX_4V;
2358 let Constraints = "$src1 = $dst" in {
2359 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2360 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2361 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2362 SSEPackedSingle>, TB;
2363 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2364 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2365 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2366 SSEPackedDouble>, TB, OpSize;
2369 let Predicates = [HasAVX] in {
2370 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2371 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2372 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2373 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2374 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2375 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2376 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2377 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2379 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2380 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2381 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2382 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2383 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2384 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2385 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2386 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2389 let Predicates = [HasSSE1] in {
2390 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2391 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2392 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2393 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2396 let Predicates = [HasSSE2] in {
2397 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2398 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2399 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2400 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2403 //===----------------------------------------------------------------------===//
2404 // SSE 1 & 2 - Shuffle Instructions
2405 //===----------------------------------------------------------------------===//
2407 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2408 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2409 ValueType vt, string asm, PatFrag mem_frag,
2410 Domain d, bit IsConvertibleToThreeAddress = 0> {
2411 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2412 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2413 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2414 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2415 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2416 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2417 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2418 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2419 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2422 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2423 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2424 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2425 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2426 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2427 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2428 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2429 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2430 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2431 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2432 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2433 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2435 let Constraints = "$src1 = $dst" in {
2436 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2437 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2438 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2440 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2441 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2442 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2446 let Predicates = [HasAVX] in {
2447 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2448 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2449 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2450 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2451 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2453 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2454 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2455 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2456 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2457 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2460 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2461 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2462 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2463 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2464 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2466 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2467 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2468 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2469 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2470 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2473 let Predicates = [HasSSE1] in {
2474 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2475 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2476 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2477 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2478 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2481 let Predicates = [HasSSE2] in {
2482 // Generic SHUFPD patterns
2483 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2484 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2485 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2486 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2487 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2490 //===----------------------------------------------------------------------===//
2491 // SSE 1 & 2 - Unpack Instructions
2492 //===----------------------------------------------------------------------===//
2494 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2495 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2496 PatFrag mem_frag, RegisterClass RC,
2497 X86MemOperand x86memop, string asm,
2499 def rr : PI<opc, MRMSrcReg,
2500 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2502 (vt (OpNode RC:$src1, RC:$src2)))],
2504 def rm : PI<opc, MRMSrcMem,
2505 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2507 (vt (OpNode RC:$src1,
2508 (mem_frag addr:$src2))))],
2512 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2513 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2514 SSEPackedSingle>, TB, VEX_4V;
2515 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2516 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 SSEPackedDouble>, TB, OpSize, VEX_4V;
2518 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2519 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 SSEPackedSingle>, TB, VEX_4V;
2521 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2522 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2523 SSEPackedDouble>, TB, OpSize, VEX_4V;
2525 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2526 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2527 SSEPackedSingle>, TB, VEX_4V;
2528 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2529 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2530 SSEPackedDouble>, TB, OpSize, VEX_4V;
2531 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2532 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 SSEPackedSingle>, TB, VEX_4V;
2534 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2535 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 SSEPackedDouble>, TB, OpSize, VEX_4V;
2538 let Constraints = "$src1 = $dst" in {
2539 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2540 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2541 SSEPackedSingle>, TB;
2542 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2543 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2544 SSEPackedDouble>, TB, OpSize;
2545 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2546 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2547 SSEPackedSingle>, TB;
2548 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2549 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2550 SSEPackedDouble>, TB, OpSize;
2551 } // Constraints = "$src1 = $dst"
2553 let Predicates = [HasAVX], AddedComplexity = 1 in {
2554 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2555 // problem is during lowering, where it's not possible to recognize the load
2556 // fold cause it has two uses through a bitcast. One use disappears at isel
2557 // time and the fold opportunity reappears.
2558 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2559 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2562 let Predicates = [HasSSE2] in {
2563 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2564 // problem is during lowering, where it's not possible to recognize the load
2565 // fold cause it has two uses through a bitcast. One use disappears at isel
2566 // time and the fold opportunity reappears.
2567 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2568 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2571 //===----------------------------------------------------------------------===//
2572 // SSE 1 & 2 - Extract Floating-Point Sign mask
2573 //===----------------------------------------------------------------------===//
2575 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2576 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2578 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2579 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2580 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2581 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2582 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2583 IIC_SSE_MOVMSK, d>, REX_W;
2586 let Predicates = [HasAVX] in {
2587 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2588 "movmskps", SSEPackedSingle>, TB, VEX;
2589 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2590 "movmskpd", SSEPackedDouble>, TB,
2592 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2593 "movmskps", SSEPackedSingle>, TB, VEX;
2594 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2595 "movmskpd", SSEPackedDouble>, TB,
2598 def : Pat<(i32 (X86fgetsign FR32:$src)),
2599 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2601 def : Pat<(i64 (X86fgetsign FR32:$src)),
2602 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2604 def : Pat<(i32 (X86fgetsign FR64:$src)),
2605 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2607 def : Pat<(i64 (X86fgetsign FR64:$src)),
2608 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2612 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2613 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2614 SSEPackedSingle>, TB, VEX;
2615 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2616 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2617 SSEPackedDouble>, TB,
2619 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2620 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2621 SSEPackedSingle>, TB, VEX;
2622 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2623 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2624 SSEPackedDouble>, TB,
2628 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2629 SSEPackedSingle>, TB;
2630 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2631 SSEPackedDouble>, TB, OpSize;
2633 def : Pat<(i32 (X86fgetsign FR32:$src)),
2634 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2635 sub_ss))>, Requires<[HasSSE1]>;
2636 def : Pat<(i64 (X86fgetsign FR32:$src)),
2637 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2638 sub_ss))>, Requires<[HasSSE1]>;
2639 def : Pat<(i32 (X86fgetsign FR64:$src)),
2640 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2641 sub_sd))>, Requires<[HasSSE2]>;
2642 def : Pat<(i64 (X86fgetsign FR64:$src)),
2643 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2644 sub_sd))>, Requires<[HasSSE2]>;
2646 //===---------------------------------------------------------------------===//
2647 // SSE2 - Packed Integer Logical Instructions
2648 //===---------------------------------------------------------------------===//
2650 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2652 /// PDI_binop_rm - Simple SSE2 binary operator.
2653 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2654 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2655 X86MemOperand x86memop,
2657 bit IsCommutable = 0,
2659 let isCommutable = IsCommutable in
2660 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2661 (ins RC:$src1, RC:$src2),
2663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2665 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2666 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2667 (ins RC:$src1, x86memop:$src2),
2669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2670 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2671 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2672 (bitconvert (memop_frag addr:$src2)))))],
2675 } // ExeDomain = SSEPackedInt
2677 // These are ordered here for pattern ordering requirements with the fp versions
2679 let Predicates = [HasAVX] in {
2680 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2681 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2682 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2683 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2684 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2685 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2686 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2687 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2690 let Constraints = "$src1 = $dst" in {
2691 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2692 i128mem, SSE_BIT_ITINS_P, 1>;
2693 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2694 i128mem, SSE_BIT_ITINS_P, 1>;
2695 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2696 i128mem, SSE_BIT_ITINS_P, 1>;
2697 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2698 i128mem, SSE_BIT_ITINS_P, 0>;
2699 } // Constraints = "$src1 = $dst"
2701 let Predicates = [HasAVX2] in {
2702 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2703 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2704 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2705 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2706 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2707 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2708 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2709 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2712 //===----------------------------------------------------------------------===//
2713 // SSE 1 & 2 - Logical Instructions
2714 //===----------------------------------------------------------------------===//
2716 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2718 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2719 SDNode OpNode, OpndItins itins> {
2720 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2721 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2724 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2725 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2728 let Constraints = "$src1 = $dst" in {
2729 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2730 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2733 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2734 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2739 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2740 let mayLoad = 0 in {
2741 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2743 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2745 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2749 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2750 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2753 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2755 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2757 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2758 // are all promoted to v2i64, and the patterns are covered by the int
2759 // version. This is needed in SSE only, because v2i64 isn't supported on
2760 // SSE1, but only on SSE2.
2761 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2762 !strconcat(OpcodeStr, "ps"), f128mem, [],
2763 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2764 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2766 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2767 !strconcat(OpcodeStr, "pd"), f128mem,
2768 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2769 (bc_v2i64 (v2f64 VR128:$src2))))],
2770 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2771 (memopv2i64 addr:$src2)))], 0>,
2773 let Constraints = "$src1 = $dst" in {
2774 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2775 !strconcat(OpcodeStr, "ps"), f128mem,
2776 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2777 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2778 (memopv2i64 addr:$src2)))]>, TB;
2780 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2781 !strconcat(OpcodeStr, "pd"), f128mem,
2782 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2783 (bc_v2i64 (v2f64 VR128:$src2))))],
2784 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2785 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2789 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2791 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2793 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2794 !strconcat(OpcodeStr, "ps"), f256mem,
2795 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2796 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2797 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2799 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2800 !strconcat(OpcodeStr, "pd"), f256mem,
2801 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2802 (bc_v4i64 (v4f64 VR256:$src2))))],
2803 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2804 (memopv4i64 addr:$src2)))], 0>,
2808 // AVX 256-bit packed logical ops forms
2809 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2810 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2811 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2812 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2814 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2815 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2816 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2817 let isCommutable = 0 in
2818 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2820 //===----------------------------------------------------------------------===//
2821 // SSE 1 & 2 - Arithmetic Instructions
2822 //===----------------------------------------------------------------------===//
2824 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2827 /// In addition, we also have a special variant of the scalar form here to
2828 /// represent the associated intrinsic operation. This form is unlike the
2829 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2830 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2832 /// These three forms can each be reg+reg or reg+mem.
2835 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2837 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2840 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2841 OpNode, FR32, f32mem,
2842 itins.s, Is2Addr>, XS;
2843 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2844 OpNode, FR64, f64mem,
2845 itins.d, Is2Addr>, XD;
2848 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2851 let mayLoad = 0 in {
2852 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2853 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2855 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2856 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2861 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2864 let mayLoad = 0 in {
2865 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2866 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2868 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2869 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2874 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2877 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2878 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2879 itins.s, Is2Addr>, XS;
2880 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2881 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2882 itins.d, Is2Addr>, XD;
2885 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2888 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2889 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2890 SSEPackedSingle, itins.s, Is2Addr>,
2893 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2894 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2895 SSEPackedDouble, itins.d, Is2Addr>,
2899 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2901 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2902 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2903 SSEPackedSingle, itins.s, 0>, TB;
2905 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2906 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2907 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2910 // Binary Arithmetic instructions
2911 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2912 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2914 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2915 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2917 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2918 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2920 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2921 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2924 let isCommutable = 0 in {
2925 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2926 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2928 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2929 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2930 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2931 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2933 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2934 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2936 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2937 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2939 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2941 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2942 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2944 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2945 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2947 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2948 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2949 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2950 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2954 let Constraints = "$src1 = $dst" in {
2955 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2956 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2957 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2958 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2959 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2960 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2962 let isCommutable = 0 in {
2963 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2965 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2966 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2967 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2968 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2969 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2970 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2971 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2972 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2973 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2974 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2975 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2976 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2981 /// In addition, we also have a special variant of the scalar form here to
2982 /// represent the associated intrinsic operation. This form is unlike the
2983 /// plain scalar form, in that it takes an entire vector (instead of a
2984 /// scalar) and leaves the top elements undefined.
2986 /// And, we have a special variant form for a full-vector intrinsic form.
2988 def SSE_SQRTP : OpndItins<
2989 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2992 def SSE_SQRTS : OpndItins<
2993 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2996 def SSE_RCPP : OpndItins<
2997 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3000 def SSE_RCPS : OpndItins<
3001 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3004 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3005 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3006 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3007 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3008 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3009 [(set FR32:$dst, (OpNode FR32:$src))]>;
3010 // For scalar unary operations, fold a load into the operation
3011 // only in OptForSize mode. It eliminates an instruction, but it also
3012 // eliminates a whole-register clobber (the load), so it introduces a
3013 // partial register update condition.
3014 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3015 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3016 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3017 Requires<[HasSSE1, OptForSize]>;
3018 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3019 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3020 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3021 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3022 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3023 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3026 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3027 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3028 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3029 !strconcat(OpcodeStr,
3030 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3032 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3033 !strconcat(OpcodeStr,
3034 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3035 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3036 (ins VR128:$src1, ssmem:$src2),
3037 !strconcat(OpcodeStr,
3038 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3041 /// sse1_fp_unop_p - SSE1 unops in packed form.
3042 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3044 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3045 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3046 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3047 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3048 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3049 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3052 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3053 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3055 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3056 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3057 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3059 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3060 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3061 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3065 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3066 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3067 Intrinsic V4F32Int, OpndItins itins> {
3068 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3069 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3070 [(set VR128:$dst, (V4F32Int VR128:$src))],
3072 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3073 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3074 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3078 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3079 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3080 Intrinsic V4F32Int, OpndItins itins> {
3081 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3082 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3083 [(set VR256:$dst, (V4F32Int VR256:$src))],
3085 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3086 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3087 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3091 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3092 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3093 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3094 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3095 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3096 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3097 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3098 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3099 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3100 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3101 Requires<[HasSSE2, OptForSize]>;
3102 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3103 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3104 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3105 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3106 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3107 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3110 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3111 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3112 let neverHasSideEffects = 1 in {
3113 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3114 !strconcat(OpcodeStr,
3115 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3117 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3118 !strconcat(OpcodeStr,
3119 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3121 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3122 (ins VR128:$src1, sdmem:$src2),
3123 !strconcat(OpcodeStr,
3124 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3127 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3128 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3129 SDNode OpNode, OpndItins itins> {
3130 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3131 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3132 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3133 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3134 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3135 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3138 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3139 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3141 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3142 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3143 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3145 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3146 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3147 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3151 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3152 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3153 Intrinsic V2F64Int, OpndItins itins> {
3154 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3155 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3156 [(set VR128:$dst, (V2F64Int VR128:$src))],
3158 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3159 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3160 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3164 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3165 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3166 Intrinsic V2F64Int, OpndItins itins> {
3167 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3168 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3169 [(set VR256:$dst, (V2F64Int VR256:$src))],
3171 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3172 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3173 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3177 let Predicates = [HasAVX] in {
3179 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3180 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3182 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3183 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3184 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3185 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3186 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3188 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3190 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3192 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3196 // Reciprocal approximations. Note that these typically require refinement
3197 // in order to obtain suitable precision.
3198 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3199 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3200 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3201 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3203 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3206 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3207 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3208 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3209 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3211 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3215 let AddedComplexity = 1 in {
3216 def : Pat<(f32 (fsqrt FR32:$src)),
3217 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3218 def : Pat<(f32 (fsqrt (load addr:$src))),
3219 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3220 Requires<[HasAVX, OptForSize]>;
3221 def : Pat<(f64 (fsqrt FR64:$src)),
3222 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3223 def : Pat<(f64 (fsqrt (load addr:$src))),
3224 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3225 Requires<[HasAVX, OptForSize]>;
3227 def : Pat<(f32 (X86frsqrt FR32:$src)),
3228 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3229 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3230 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3231 Requires<[HasAVX, OptForSize]>;
3233 def : Pat<(f32 (X86frcp FR32:$src)),
3234 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3235 def : Pat<(f32 (X86frcp (load addr:$src))),
3236 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3237 Requires<[HasAVX, OptForSize]>;
3240 let Predicates = [HasAVX], AddedComplexity = 1 in {
3241 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3242 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3243 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3244 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3246 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3247 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3249 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3250 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3251 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3252 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3254 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3255 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3257 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3258 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3259 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3260 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3262 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3263 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3265 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3266 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3267 (VRCPSSr (f32 (IMPLICIT_DEF)),
3268 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3270 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3271 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3275 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3277 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3278 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3279 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3281 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3282 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3284 // Reciprocal approximations. Note that these typically require refinement
3285 // in order to obtain suitable precision.
3286 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3288 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3289 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3291 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3293 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3294 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3296 // There is no f64 version of the reciprocal approximation instructions.
3298 //===----------------------------------------------------------------------===//
3299 // SSE 1 & 2 - Non-temporal stores
3300 //===----------------------------------------------------------------------===//
3302 let AddedComplexity = 400 in { // Prefer non-temporal versions
3303 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3304 (ins f128mem:$dst, VR128:$src),
3305 "movntps\t{$src, $dst|$dst, $src}",
3306 [(alignednontemporalstore (v4f32 VR128:$src),
3308 IIC_SSE_MOVNT>, VEX;
3309 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3310 (ins f128mem:$dst, VR128:$src),
3311 "movntpd\t{$src, $dst|$dst, $src}",
3312 [(alignednontemporalstore (v2f64 VR128:$src),
3314 IIC_SSE_MOVNT>, VEX;
3316 let ExeDomain = SSEPackedInt in
3317 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3318 (ins f128mem:$dst, VR128:$src),
3319 "movntdq\t{$src, $dst|$dst, $src}",
3320 [(alignednontemporalstore (v2i64 VR128:$src),
3322 IIC_SSE_MOVNT>, VEX;
3324 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3325 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3327 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3328 (ins f256mem:$dst, VR256:$src),
3329 "movntps\t{$src, $dst|$dst, $src}",
3330 [(alignednontemporalstore (v8f32 VR256:$src),
3332 IIC_SSE_MOVNT>, VEX;
3333 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3334 (ins f256mem:$dst, VR256:$src),
3335 "movntpd\t{$src, $dst|$dst, $src}",
3336 [(alignednontemporalstore (v4f64 VR256:$src),
3338 IIC_SSE_MOVNT>, VEX;
3339 let ExeDomain = SSEPackedInt in
3340 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3341 (ins f256mem:$dst, VR256:$src),
3342 "movntdq\t{$src, $dst|$dst, $src}",
3343 [(alignednontemporalstore (v4i64 VR256:$src),
3345 IIC_SSE_MOVNT>, VEX;
3348 let AddedComplexity = 400 in { // Prefer non-temporal versions
3349 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3350 "movntps\t{$src, $dst|$dst, $src}",
3351 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3353 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3354 "movntpd\t{$src, $dst|$dst, $src}",
3355 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3358 let ExeDomain = SSEPackedInt in
3359 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3360 "movntdq\t{$src, $dst|$dst, $src}",
3361 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3364 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3365 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3367 // There is no AVX form for instructions below this point
3368 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3369 "movnti{l}\t{$src, $dst|$dst, $src}",
3370 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3372 TB, Requires<[HasSSE2]>;
3373 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3374 "movnti{q}\t{$src, $dst|$dst, $src}",
3375 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3377 TB, Requires<[HasSSE2]>;
3380 //===----------------------------------------------------------------------===//
3381 // SSE 1 & 2 - Prefetch and memory fence
3382 //===----------------------------------------------------------------------===//
3384 // Prefetch intrinsic.
3385 let Predicates = [HasSSE1] in {
3386 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3387 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3388 IIC_SSE_PREFETCH>, TB;
3389 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3390 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3391 IIC_SSE_PREFETCH>, TB;
3392 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3393 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3394 IIC_SSE_PREFETCH>, TB;
3395 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3396 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3397 IIC_SSE_PREFETCH>, TB;
3401 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3402 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3403 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3405 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3406 // was introduced with SSE2, it's backward compatible.
3407 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3409 // Load, store, and memory fence
3410 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3411 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3412 TB, Requires<[HasSSE1]>;
3413 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3414 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3415 TB, Requires<[HasSSE2]>;
3416 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3417 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3418 TB, Requires<[HasSSE2]>;
3420 def : Pat<(X86SFence), (SFENCE)>;
3421 def : Pat<(X86LFence), (LFENCE)>;
3422 def : Pat<(X86MFence), (MFENCE)>;
3424 //===----------------------------------------------------------------------===//
3425 // SSE 1 & 2 - Load/Store XCSR register
3426 //===----------------------------------------------------------------------===//
3428 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3429 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3430 IIC_SSE_LDMXCSR>, VEX;
3431 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3432 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3433 IIC_SSE_STMXCSR>, VEX;
3435 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3436 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3438 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3439 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3442 //===---------------------------------------------------------------------===//
3443 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3444 //===---------------------------------------------------------------------===//
3446 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3448 let neverHasSideEffects = 1 in {
3449 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3450 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3452 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3453 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3456 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3457 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3459 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3460 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3464 let isCodeGenOnly = 1 in {
3465 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3466 "movdqa\t{$src, $dst|$dst, $src}", [],
3469 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3470 "movdqa\t{$src, $dst|$dst, $src}", [],
3473 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3474 "movdqu\t{$src, $dst|$dst, $src}", [],
3477 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3478 "movdqu\t{$src, $dst|$dst, $src}", [],
3483 let canFoldAsLoad = 1, mayLoad = 1 in {
3484 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3485 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3487 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3488 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3490 let Predicates = [HasAVX] in {
3491 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3492 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3494 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3495 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3500 let mayStore = 1 in {
3501 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3502 (ins i128mem:$dst, VR128:$src),
3503 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3505 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3506 (ins i256mem:$dst, VR256:$src),
3507 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3509 let Predicates = [HasAVX] in {
3510 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3511 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3513 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3514 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3519 let neverHasSideEffects = 1 in
3520 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3521 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3523 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3524 "movdqu\t{$src, $dst|$dst, $src}",
3525 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3528 let isCodeGenOnly = 1 in {
3529 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3530 "movdqa\t{$src, $dst|$dst, $src}", [],
3533 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3534 "movdqu\t{$src, $dst|$dst, $src}",
3535 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3538 let canFoldAsLoad = 1, mayLoad = 1 in {
3539 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3540 "movdqa\t{$src, $dst|$dst, $src}",
3541 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3543 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3544 "movdqu\t{$src, $dst|$dst, $src}",
3545 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3547 XS, Requires<[HasSSE2]>;
3550 let mayStore = 1 in {
3551 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3552 "movdqa\t{$src, $dst|$dst, $src}",
3553 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3555 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3556 "movdqu\t{$src, $dst|$dst, $src}",
3557 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3559 XS, Requires<[HasSSE2]>;
3562 // Intrinsic forms of MOVDQU load and store
3563 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3564 "vmovdqu\t{$src, $dst|$dst, $src}",
3565 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3567 XS, VEX, Requires<[HasAVX]>;
3569 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3570 "movdqu\t{$src, $dst|$dst, $src}",
3571 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3573 XS, Requires<[HasSSE2]>;
3575 } // ExeDomain = SSEPackedInt
3577 let Predicates = [HasAVX] in {
3578 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3579 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3582 //===---------------------------------------------------------------------===//
3583 // SSE2 - Packed Integer Arithmetic Instructions
3584 //===---------------------------------------------------------------------===//
3586 def SSE_PMADD : OpndItins<
3587 IIC_SSE_PMADD, IIC_SSE_PMADD
3590 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3592 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3593 RegisterClass RC, PatFrag memop_frag,
3594 X86MemOperand x86memop,
3596 bit IsCommutable = 0,
3598 let isCommutable = IsCommutable in
3599 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3600 (ins RC:$src1, RC:$src2),
3602 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3603 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3604 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3605 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3606 (ins RC:$src1, x86memop:$src2),
3608 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3609 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3610 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3614 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3615 string OpcodeStr, SDNode OpNode,
3616 SDNode OpNode2, RegisterClass RC,
3617 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3618 ShiftOpndItins itins,
3620 // src2 is always 128-bit
3621 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3622 (ins RC:$src1, VR128:$src2),
3624 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3626 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3628 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3629 (ins RC:$src1, i128mem:$src2),
3631 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3632 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3633 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3634 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3635 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3636 (ins RC:$src1, i32i8imm:$src2),
3638 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3639 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3640 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3643 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3644 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3645 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3646 PatFrag memop_frag, X86MemOperand x86memop,
3648 bit IsCommutable = 0, bit Is2Addr = 1> {
3649 let isCommutable = IsCommutable in
3650 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3651 (ins RC:$src1, RC:$src2),
3653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3655 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3656 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3657 (ins RC:$src1, x86memop:$src2),
3659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3661 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3662 (bitconvert (memop_frag addr:$src2)))))]>;
3664 } // ExeDomain = SSEPackedInt
3666 // 128-bit Integer Arithmetic
3668 let Predicates = [HasAVX] in {
3669 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3670 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3672 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3673 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3674 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3675 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3676 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3677 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3678 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3679 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3680 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3681 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3682 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3683 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3684 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3685 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3686 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3687 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3688 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3689 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3693 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3694 VR128, memopv2i64, i128mem,
3695 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3696 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3697 VR128, memopv2i64, i128mem,
3698 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3699 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3700 VR128, memopv2i64, i128mem,
3701 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3702 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3703 VR128, memopv2i64, i128mem,
3704 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3705 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3706 VR128, memopv2i64, i128mem,
3707 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3708 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3709 VR128, memopv2i64, i128mem,
3710 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3711 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3712 VR128, memopv2i64, i128mem,
3713 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3714 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3715 VR128, memopv2i64, i128mem,
3716 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3717 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3718 VR128, memopv2i64, i128mem,
3719 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3720 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3721 VR128, memopv2i64, i128mem,
3722 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3723 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3724 VR128, memopv2i64, i128mem,
3725 SSE_PMADD, 1, 0>, VEX_4V;
3726 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3727 VR128, memopv2i64, i128mem,
3728 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3729 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3730 VR128, memopv2i64, i128mem,
3731 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3732 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3733 VR128, memopv2i64, i128mem,
3734 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3735 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3736 VR128, memopv2i64, i128mem,
3737 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3738 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3739 VR128, memopv2i64, i128mem,
3740 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3741 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3742 VR128, memopv2i64, i128mem,
3743 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3744 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3745 VR128, memopv2i64, i128mem,
3746 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3749 let Predicates = [HasAVX2] in {
3750 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3751 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3752 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3753 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3754 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3755 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3756 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3757 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3758 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3759 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3760 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3761 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3762 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3763 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3764 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3765 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3766 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3767 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3768 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3769 VR256, memopv4i64, i256mem,
3770 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3773 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3774 VR256, memopv4i64, i256mem,
3775 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3776 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3777 VR256, memopv4i64, i256mem,
3778 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3779 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3780 VR256, memopv4i64, i256mem,
3781 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3782 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3783 VR256, memopv4i64, i256mem,
3784 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3785 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3786 VR256, memopv4i64, i256mem,
3787 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3788 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3789 VR256, memopv4i64, i256mem,
3790 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3791 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3792 VR256, memopv4i64, i256mem,
3793 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3794 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3795 VR256, memopv4i64, i256mem,
3796 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3797 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3798 VR256, memopv4i64, i256mem,
3799 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3800 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3801 VR256, memopv4i64, i256mem,
3802 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3803 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3804 VR256, memopv4i64, i256mem,
3805 SSE_PMADD, 1, 0>, VEX_4V;
3806 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3807 VR256, memopv4i64, i256mem,
3808 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3809 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3810 VR256, memopv4i64, i256mem,
3811 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3812 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3813 VR256, memopv4i64, i256mem,
3814 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3815 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3816 VR256, memopv4i64, i256mem,
3817 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3818 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3819 VR256, memopv4i64, i256mem,
3820 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3821 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3822 VR256, memopv4i64, i256mem,
3823 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3824 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3825 VR256, memopv4i64, i256mem,
3826 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3829 let Constraints = "$src1 = $dst" in {
3830 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3831 i128mem, SSE_INTALU_ITINS_P, 1>;
3832 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3833 i128mem, SSE_INTALU_ITINS_P, 1>;
3834 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3835 i128mem, SSE_INTALU_ITINS_P, 1>;
3836 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3837 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3838 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3839 i128mem, SSE_INTMUL_ITINS_P, 1>;
3840 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3841 i128mem, SSE_INTALU_ITINS_P>;
3842 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3843 i128mem, SSE_INTALU_ITINS_P>;
3844 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3845 i128mem, SSE_INTALU_ITINS_P>;
3846 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3847 i128mem, SSE_INTALUQ_ITINS_P>;
3848 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3849 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3852 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3853 VR128, memopv2i64, i128mem,
3854 SSE_INTALU_ITINS_P>;
3855 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3856 VR128, memopv2i64, i128mem,
3857 SSE_INTALU_ITINS_P>;
3858 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3859 VR128, memopv2i64, i128mem,
3860 SSE_INTALU_ITINS_P>;
3861 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3862 VR128, memopv2i64, i128mem,
3863 SSE_INTALU_ITINS_P>;
3864 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3865 VR128, memopv2i64, i128mem,
3866 SSE_INTALU_ITINS_P, 1>;
3867 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3868 VR128, memopv2i64, i128mem,
3869 SSE_INTALU_ITINS_P, 1>;
3870 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3871 VR128, memopv2i64, i128mem,
3872 SSE_INTALU_ITINS_P, 1>;
3873 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3874 VR128, memopv2i64, i128mem,
3875 SSE_INTALU_ITINS_P, 1>;
3876 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3877 VR128, memopv2i64, i128mem,
3878 SSE_INTMUL_ITINS_P, 1>;
3879 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3880 VR128, memopv2i64, i128mem,
3881 SSE_INTMUL_ITINS_P, 1>;
3882 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3883 VR128, memopv2i64, i128mem,
3885 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3886 VR128, memopv2i64, i128mem,
3887 SSE_INTALU_ITINS_P, 1>;
3888 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3889 VR128, memopv2i64, i128mem,
3890 SSE_INTALU_ITINS_P, 1>;
3891 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3892 VR128, memopv2i64, i128mem,
3893 SSE_INTALU_ITINS_P, 1>;
3894 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3895 VR128, memopv2i64, i128mem,
3896 SSE_INTALU_ITINS_P, 1>;
3897 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3898 VR128, memopv2i64, i128mem,
3899 SSE_INTALU_ITINS_P, 1>;
3900 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3901 VR128, memopv2i64, i128mem,
3902 SSE_INTALU_ITINS_P, 1>;
3903 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3904 VR128, memopv2i64, i128mem,
3905 SSE_INTALU_ITINS_P, 1>;
3907 } // Constraints = "$src1 = $dst"
3909 //===---------------------------------------------------------------------===//
3910 // SSE2 - Packed Integer Logical Instructions
3911 //===---------------------------------------------------------------------===//
3913 let Predicates = [HasAVX] in {
3914 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3915 VR128, v8i16, v8i16, bc_v8i16,
3916 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3917 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3918 VR128, v4i32, v4i32, bc_v4i32,
3919 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3920 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3921 VR128, v2i64, v2i64, bc_v2i64,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3924 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3925 VR128, v8i16, v8i16, bc_v8i16,
3926 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3927 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3928 VR128, v4i32, v4i32, bc_v4i32,
3929 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3930 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3931 VR128, v2i64, v2i64, bc_v2i64,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3934 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3935 VR128, v8i16, v8i16, bc_v8i16,
3936 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3937 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3938 VR128, v4i32, v4i32, bc_v4i32,
3939 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3941 let ExeDomain = SSEPackedInt in {
3942 // 128-bit logical shifts.
3943 def VPSLLDQri : PDIi8<0x73, MRM7r,
3944 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3945 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3947 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3949 def VPSRLDQri : PDIi8<0x73, MRM3r,
3950 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3951 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3955 // PSRADQri doesn't exist in SSE[1-3].
3957 } // Predicates = [HasAVX]
3959 let Predicates = [HasAVX2] in {
3960 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3961 VR256, v16i16, v8i16, bc_v8i16,
3962 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3963 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3964 VR256, v8i32, v4i32, bc_v4i32,
3965 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3966 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3967 VR256, v4i64, v2i64, bc_v2i64,
3968 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3970 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3971 VR256, v16i16, v8i16, bc_v8i16,
3972 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3973 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3974 VR256, v8i32, v4i32, bc_v4i32,
3975 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3976 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3977 VR256, v4i64, v2i64, bc_v2i64,
3978 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3980 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3981 VR256, v16i16, v8i16, bc_v8i16,
3982 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3983 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3984 VR256, v8i32, v4i32, bc_v4i32,
3985 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3987 let ExeDomain = SSEPackedInt in {
3988 // 256-bit logical shifts.
3989 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3990 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3991 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3993 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3995 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3996 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3997 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3999 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4001 // PSRADQYri doesn't exist in SSE[1-3].
4003 } // Predicates = [HasAVX2]
4005 let Constraints = "$src1 = $dst" in {
4006 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4007 VR128, v8i16, v8i16, bc_v8i16,
4008 SSE_INTSHIFT_ITINS_P>;
4009 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4010 VR128, v4i32, v4i32, bc_v4i32,
4011 SSE_INTSHIFT_ITINS_P>;
4012 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4013 VR128, v2i64, v2i64, bc_v2i64,
4014 SSE_INTSHIFT_ITINS_P>;
4016 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4017 VR128, v8i16, v8i16, bc_v8i16,
4018 SSE_INTSHIFT_ITINS_P>;
4019 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4020 VR128, v4i32, v4i32, bc_v4i32,
4021 SSE_INTSHIFT_ITINS_P>;
4022 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4023 VR128, v2i64, v2i64, bc_v2i64,
4024 SSE_INTSHIFT_ITINS_P>;
4026 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4027 VR128, v8i16, v8i16, bc_v8i16,
4028 SSE_INTSHIFT_ITINS_P>;
4029 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4030 VR128, v4i32, v4i32, bc_v4i32,
4031 SSE_INTSHIFT_ITINS_P>;
4033 let ExeDomain = SSEPackedInt in {
4034 // 128-bit logical shifts.
4035 def PSLLDQri : PDIi8<0x73, MRM7r,
4036 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4037 "pslldq\t{$src2, $dst|$dst, $src2}",
4039 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4040 def PSRLDQri : PDIi8<0x73, MRM3r,
4041 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4042 "psrldq\t{$src2, $dst|$dst, $src2}",
4044 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4045 // PSRADQri doesn't exist in SSE[1-3].
4047 } // Constraints = "$src1 = $dst"
4049 let Predicates = [HasAVX] in {
4050 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4051 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4052 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4053 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4054 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4055 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4057 // Shift up / down and insert zero's.
4058 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4059 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4060 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4061 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4064 let Predicates = [HasAVX2] in {
4065 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4066 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4067 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4068 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4071 let Predicates = [HasSSE2] in {
4072 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4073 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4074 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4075 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4076 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4077 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4079 // Shift up / down and insert zero's.
4080 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4081 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4082 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4083 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4086 //===---------------------------------------------------------------------===//
4087 // SSE2 - Packed Integer Comparison Instructions
4088 //===---------------------------------------------------------------------===//
4090 let Predicates = [HasAVX] in {
4091 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4092 VR128, memopv2i64, i128mem,
4093 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4094 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4095 VR128, memopv2i64, i128mem,
4096 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4097 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4098 VR128, memopv2i64, i128mem,
4099 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4100 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4101 VR128, memopv2i64, i128mem,
4102 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4103 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4104 VR128, memopv2i64, i128mem,
4105 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4106 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4107 VR128, memopv2i64, i128mem,
4108 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4111 let Predicates = [HasAVX2] in {
4112 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4113 VR256, memopv4i64, i256mem,
4114 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4115 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4116 VR256, memopv4i64, i256mem,
4117 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4118 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4119 VR256, memopv4i64, i256mem,
4120 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4121 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4122 VR256, memopv4i64, i256mem,
4123 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4124 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4125 VR256, memopv4i64, i256mem,
4126 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4127 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4128 VR256, memopv4i64, i256mem,
4129 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4132 let Constraints = "$src1 = $dst" in {
4133 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4134 VR128, memopv2i64, i128mem,
4135 SSE_INTALU_ITINS_P, 1>;
4136 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4137 VR128, memopv2i64, i128mem,
4138 SSE_INTALU_ITINS_P, 1>;
4139 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4140 VR128, memopv2i64, i128mem,
4141 SSE_INTALU_ITINS_P, 1>;
4142 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4143 VR128, memopv2i64, i128mem,
4144 SSE_INTALU_ITINS_P>;
4145 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4146 VR128, memopv2i64, i128mem,
4147 SSE_INTALU_ITINS_P>;
4148 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4149 VR128, memopv2i64, i128mem,
4150 SSE_INTALU_ITINS_P>;
4151 } // Constraints = "$src1 = $dst"
4153 //===---------------------------------------------------------------------===//
4154 // SSE2 - Packed Integer Pack Instructions
4155 //===---------------------------------------------------------------------===//
4157 let Predicates = [HasAVX] in {
4158 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4159 VR128, memopv2i64, i128mem,
4160 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4161 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4162 VR128, memopv2i64, i128mem,
4163 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4164 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4165 VR128, memopv2i64, i128mem,
4166 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4169 let Predicates = [HasAVX2] in {
4170 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4171 VR256, memopv4i64, i256mem,
4172 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4173 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4174 VR256, memopv4i64, i256mem,
4175 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4176 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4177 VR256, memopv4i64, i256mem,
4178 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4181 let Constraints = "$src1 = $dst" in {
4182 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4183 VR128, memopv2i64, i128mem,
4184 SSE_INTALU_ITINS_P>;
4185 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4186 VR128, memopv2i64, i128mem,
4187 SSE_INTALU_ITINS_P>;
4188 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4189 VR128, memopv2i64, i128mem,
4190 SSE_INTALU_ITINS_P>;
4191 } // Constraints = "$src1 = $dst"
4193 //===---------------------------------------------------------------------===//
4194 // SSE2 - Packed Integer Shuffle Instructions
4195 //===---------------------------------------------------------------------===//
4197 let ExeDomain = SSEPackedInt in {
4198 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4199 def ri : Ii8<0x70, MRMSrcReg,
4200 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4201 !strconcat(OpcodeStr,
4202 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4203 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4205 def mi : Ii8<0x70, MRMSrcMem,
4206 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4207 !strconcat(OpcodeStr,
4208 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4210 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4215 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4216 def Yri : Ii8<0x70, MRMSrcReg,
4217 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4218 !strconcat(OpcodeStr,
4219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4220 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4221 def Ymi : Ii8<0x70, MRMSrcMem,
4222 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4223 !strconcat(OpcodeStr,
4224 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4226 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4227 (i8 imm:$src2))))]>;
4229 } // ExeDomain = SSEPackedInt
4231 let Predicates = [HasAVX] in {
4232 let AddedComplexity = 5 in
4233 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4235 // SSE2 with ImmT == Imm8 and XS prefix.
4236 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4238 // SSE2 with ImmT == Imm8 and XD prefix.
4239 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4241 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4242 (VPSHUFDmi addr:$src1, imm:$imm)>;
4243 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4244 (VPSHUFDri VR128:$src1, imm:$imm)>;
4247 let Predicates = [HasAVX2] in {
4248 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4249 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4250 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4253 let Predicates = [HasSSE2] in {
4254 let AddedComplexity = 5 in
4255 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4257 // SSE2 with ImmT == Imm8 and XS prefix.
4258 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4260 // SSE2 with ImmT == Imm8 and XD prefix.
4261 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4263 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4264 (PSHUFDmi addr:$src1, imm:$imm)>;
4265 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4266 (PSHUFDri VR128:$src1, imm:$imm)>;
4269 //===---------------------------------------------------------------------===//
4270 // SSE2 - Packed Integer Unpack Instructions
4271 //===---------------------------------------------------------------------===//
4273 let ExeDomain = SSEPackedInt in {
4274 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4275 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4276 def rr : PDI<opc, MRMSrcReg,
4277 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4279 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4280 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4281 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4283 def rm : PDI<opc, MRMSrcMem,
4284 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4286 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4287 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4288 [(set VR128:$dst, (OpNode VR128:$src1,
4289 (bc_frag (memopv2i64
4294 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4295 SDNode OpNode, PatFrag bc_frag> {
4296 def Yrr : PDI<opc, MRMSrcReg,
4297 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4298 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4299 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4300 def Yrm : PDI<opc, MRMSrcMem,
4301 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4302 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4303 [(set VR256:$dst, (OpNode VR256:$src1,
4304 (bc_frag (memopv4i64 addr:$src2))))]>;
4307 let Predicates = [HasAVX] in {
4308 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4309 bc_v16i8, 0>, VEX_4V;
4310 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4311 bc_v8i16, 0>, VEX_4V;
4312 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4313 bc_v4i32, 0>, VEX_4V;
4314 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4315 bc_v2i64, 0>, VEX_4V;
4317 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4318 bc_v16i8, 0>, VEX_4V;
4319 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4320 bc_v8i16, 0>, VEX_4V;
4321 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4322 bc_v4i32, 0>, VEX_4V;
4323 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4324 bc_v2i64, 0>, VEX_4V;
4327 let Predicates = [HasAVX2] in {
4328 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4330 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4332 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4334 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4337 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4339 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4341 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4343 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4347 let Constraints = "$src1 = $dst" in {
4348 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4350 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4352 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4354 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4357 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4359 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4361 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4363 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4366 } // ExeDomain = SSEPackedInt
4368 // Patterns for using AVX1 instructions with integer vectors
4369 // Here to give AVX2 priority
4370 let Predicates = [HasAVX] in {
4371 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4372 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4373 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4374 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4375 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4376 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4377 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4378 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4380 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4381 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4382 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4383 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4384 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4385 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4386 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4387 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4390 //===---------------------------------------------------------------------===//
4391 // SSE2 - Packed Integer Extract and Insert
4392 //===---------------------------------------------------------------------===//
4394 let ExeDomain = SSEPackedInt in {
4395 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4396 def rri : Ii8<0xC4, MRMSrcReg,
4397 (outs VR128:$dst), (ins VR128:$src1,
4398 GR32:$src2, i32i8imm:$src3),
4400 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4401 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4403 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4404 def rmi : Ii8<0xC4, MRMSrcMem,
4405 (outs VR128:$dst), (ins VR128:$src1,
4406 i16mem:$src2, i32i8imm:$src3),
4408 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4409 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4411 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4412 imm:$src3))], IIC_SSE_PINSRW>;
4416 let Predicates = [HasAVX] in
4417 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4418 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4419 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4420 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4421 imm:$src2))]>, TB, OpSize, VEX;
4422 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4423 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4424 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4425 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4426 imm:$src2))], IIC_SSE_PEXTRW>;
4429 let Predicates = [HasAVX] in {
4430 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4431 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4432 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4433 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4434 []>, TB, OpSize, VEX_4V;
4437 let Constraints = "$src1 = $dst" in
4438 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4440 } // ExeDomain = SSEPackedInt
4442 //===---------------------------------------------------------------------===//
4443 // SSE2 - Packed Mask Creation
4444 //===---------------------------------------------------------------------===//
4446 let ExeDomain = SSEPackedInt in {
4448 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4449 "pmovmskb\t{$src, $dst|$dst, $src}",
4450 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4451 IIC_SSE_MOVMSK>, VEX;
4452 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4453 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4455 let Predicates = [HasAVX2] in {
4456 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4457 "pmovmskb\t{$src, $dst|$dst, $src}",
4458 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4459 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4460 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4463 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4464 "pmovmskb\t{$src, $dst|$dst, $src}",
4465 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4468 } // ExeDomain = SSEPackedInt
4470 //===---------------------------------------------------------------------===//
4471 // SSE2 - Conditional Store
4472 //===---------------------------------------------------------------------===//
4474 let ExeDomain = SSEPackedInt in {
4477 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4478 (ins VR128:$src, VR128:$mask),
4479 "maskmovdqu\t{$mask, $src|$src, $mask}",
4480 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4481 IIC_SSE_MASKMOV>, VEX;
4483 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4484 (ins VR128:$src, VR128:$mask),
4485 "maskmovdqu\t{$mask, $src|$src, $mask}",
4486 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4487 IIC_SSE_MASKMOV>, VEX;
4490 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4491 "maskmovdqu\t{$mask, $src|$src, $mask}",
4492 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4495 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4496 "maskmovdqu\t{$mask, $src|$src, $mask}",
4497 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4500 } // ExeDomain = SSEPackedInt
4502 //===---------------------------------------------------------------------===//
4503 // SSE2 - Move Doubleword
4504 //===---------------------------------------------------------------------===//
4506 //===---------------------------------------------------------------------===//
4507 // Move Int Doubleword to Packed Double Int
4509 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4510 "movd\t{$src, $dst|$dst, $src}",
4512 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4514 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4515 "movd\t{$src, $dst|$dst, $src}",
4517 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4520 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4521 "mov{d|q}\t{$src, $dst|$dst, $src}",
4523 (v2i64 (scalar_to_vector GR64:$src)))],
4524 IIC_SSE_MOVDQ>, VEX;
4525 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4526 "mov{d|q}\t{$src, $dst|$dst, $src}",
4527 [(set FR64:$dst, (bitconvert GR64:$src))],
4528 IIC_SSE_MOVDQ>, VEX;
4530 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4531 "movd\t{$src, $dst|$dst, $src}",
4533 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4534 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4535 "movd\t{$src, $dst|$dst, $src}",
4537 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4539 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4540 "mov{d|q}\t{$src, $dst|$dst, $src}",
4542 (v2i64 (scalar_to_vector GR64:$src)))],
4544 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4545 "mov{d|q}\t{$src, $dst|$dst, $src}",
4546 [(set FR64:$dst, (bitconvert GR64:$src))],
4549 //===---------------------------------------------------------------------===//
4550 // Move Int Doubleword to Single Scalar
4552 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4553 "movd\t{$src, $dst|$dst, $src}",
4554 [(set FR32:$dst, (bitconvert GR32:$src))],
4555 IIC_SSE_MOVDQ>, VEX;
4557 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4558 "movd\t{$src, $dst|$dst, $src}",
4559 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4562 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4563 "movd\t{$src, $dst|$dst, $src}",
4564 [(set FR32:$dst, (bitconvert GR32:$src))],
4567 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4569 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4572 //===---------------------------------------------------------------------===//
4573 // Move Packed Doubleword Int to Packed Double Int
4575 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4576 "movd\t{$src, $dst|$dst, $src}",
4577 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4578 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4579 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4580 (ins i32mem:$dst, VR128:$src),
4581 "movd\t{$src, $dst|$dst, $src}",
4582 [(store (i32 (vector_extract (v4i32 VR128:$src),
4583 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4585 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4586 "movd\t{$src, $dst|$dst, $src}",
4587 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4588 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4589 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4590 "movd\t{$src, $dst|$dst, $src}",
4591 [(store (i32 (vector_extract (v4i32 VR128:$src),
4592 (iPTR 0))), addr:$dst)],
4595 //===---------------------------------------------------------------------===//
4596 // Move Packed Doubleword Int first element to Doubleword Int
4598 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4599 "mov{d|q}\t{$src, $dst|$dst, $src}",
4600 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4603 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4605 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4606 "mov{d|q}\t{$src, $dst|$dst, $src}",
4607 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4611 //===---------------------------------------------------------------------===//
4612 // Bitcast FR64 <-> GR64
4614 let Predicates = [HasAVX] in
4615 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4616 "vmovq\t{$src, $dst|$dst, $src}",
4617 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4619 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4620 "mov{d|q}\t{$src, $dst|$dst, $src}",
4621 [(set GR64:$dst, (bitconvert FR64:$src))],
4622 IIC_SSE_MOVDQ>, VEX;
4623 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4624 "movq\t{$src, $dst|$dst, $src}",
4625 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4626 IIC_SSE_MOVDQ>, VEX;
4628 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4629 "movq\t{$src, $dst|$dst, $src}",
4630 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4632 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4633 "mov{d|q}\t{$src, $dst|$dst, $src}",
4634 [(set GR64:$dst, (bitconvert FR64:$src))],
4636 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4637 "movq\t{$src, $dst|$dst, $src}",
4638 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4641 //===---------------------------------------------------------------------===//
4642 // Move Scalar Single to Double Int
4644 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4645 "movd\t{$src, $dst|$dst, $src}",
4646 [(set GR32:$dst, (bitconvert FR32:$src))],
4647 IIC_SSE_MOVD_ToGP>, VEX;
4648 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4649 "movd\t{$src, $dst|$dst, $src}",
4650 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4651 IIC_SSE_MOVDQ>, VEX;
4652 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4653 "movd\t{$src, $dst|$dst, $src}",
4654 [(set GR32:$dst, (bitconvert FR32:$src))],
4656 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4657 "movd\t{$src, $dst|$dst, $src}",
4658 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4661 //===---------------------------------------------------------------------===//
4662 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4664 let AddedComplexity = 15 in {
4665 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4666 "movd\t{$src, $dst|$dst, $src}",
4667 [(set VR128:$dst, (v4i32 (X86vzmovl
4668 (v4i32 (scalar_to_vector GR32:$src)))))],
4669 IIC_SSE_MOVDQ>, VEX;
4670 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4671 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4672 [(set VR128:$dst, (v2i64 (X86vzmovl
4673 (v2i64 (scalar_to_vector GR64:$src)))))],
4677 let AddedComplexity = 15 in {
4678 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4679 "movd\t{$src, $dst|$dst, $src}",
4680 [(set VR128:$dst, (v4i32 (X86vzmovl
4681 (v4i32 (scalar_to_vector GR32:$src)))))],
4683 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4684 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4685 [(set VR128:$dst, (v2i64 (X86vzmovl
4686 (v2i64 (scalar_to_vector GR64:$src)))))],
4690 let AddedComplexity = 20 in {
4691 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4692 "movd\t{$src, $dst|$dst, $src}",
4694 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4695 (loadi32 addr:$src))))))],
4696 IIC_SSE_MOVDQ>, VEX;
4697 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4698 "movd\t{$src, $dst|$dst, $src}",
4700 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4701 (loadi32 addr:$src))))))],
4705 let Predicates = [HasAVX] in {
4706 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4707 let AddedComplexity = 20 in {
4708 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4709 (VMOVZDI2PDIrm addr:$src)>;
4710 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4711 (VMOVZDI2PDIrm addr:$src)>;
4713 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4714 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4715 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4716 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4717 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4718 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4719 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4722 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4723 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4724 (MOVZDI2PDIrm addr:$src)>;
4725 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4726 (MOVZDI2PDIrm addr:$src)>;
4729 // These are the correct encodings of the instructions so that we know how to
4730 // read correct assembly, even though we continue to emit the wrong ones for
4731 // compatibility with Darwin's buggy assembler.
4732 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4733 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4734 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4735 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4736 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4737 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4738 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4739 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4740 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4741 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4742 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4743 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4745 //===---------------------------------------------------------------------===//
4746 // SSE2 - Move Quadword
4747 //===---------------------------------------------------------------------===//
4749 //===---------------------------------------------------------------------===//
4750 // Move Quadword Int to Packed Quadword Int
4752 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4753 "vmovq\t{$src, $dst|$dst, $src}",
4755 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4756 VEX, Requires<[HasAVX]>;
4757 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4758 "movq\t{$src, $dst|$dst, $src}",
4760 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4762 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4764 //===---------------------------------------------------------------------===//
4765 // Move Packed Quadword Int to Quadword Int
4767 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4768 "movq\t{$src, $dst|$dst, $src}",
4769 [(store (i64 (vector_extract (v2i64 VR128:$src),
4770 (iPTR 0))), addr:$dst)],
4771 IIC_SSE_MOVDQ>, VEX;
4772 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4773 "movq\t{$src, $dst|$dst, $src}",
4774 [(store (i64 (vector_extract (v2i64 VR128:$src),
4775 (iPTR 0))), addr:$dst)],
4778 //===---------------------------------------------------------------------===//
4779 // Store / copy lower 64-bits of a XMM register.
4781 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4782 "movq\t{$src, $dst|$dst, $src}",
4783 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4784 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4785 "movq\t{$src, $dst|$dst, $src}",
4786 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4789 let AddedComplexity = 20 in
4790 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4791 "vmovq\t{$src, $dst|$dst, $src}",
4793 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4794 (loadi64 addr:$src))))))],
4796 XS, VEX, Requires<[HasAVX]>;
4798 let AddedComplexity = 20 in
4799 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4800 "movq\t{$src, $dst|$dst, $src}",
4802 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4803 (loadi64 addr:$src))))))],
4805 XS, Requires<[HasSSE2]>;
4807 let Predicates = [HasAVX], AddedComplexity = 20 in {
4808 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4809 (VMOVZQI2PQIrm addr:$src)>;
4810 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4811 (VMOVZQI2PQIrm addr:$src)>;
4812 def : Pat<(v2i64 (X86vzload addr:$src)),
4813 (VMOVZQI2PQIrm addr:$src)>;
4816 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4817 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4818 (MOVZQI2PQIrm addr:$src)>;
4819 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4820 (MOVZQI2PQIrm addr:$src)>;
4821 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4824 let Predicates = [HasAVX] in {
4825 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4826 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4827 def : Pat<(v4i64 (X86vzload addr:$src)),
4828 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4831 //===---------------------------------------------------------------------===//
4832 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4833 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4835 let AddedComplexity = 15 in
4836 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4837 "vmovq\t{$src, $dst|$dst, $src}",
4838 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4840 XS, VEX, Requires<[HasAVX]>;
4841 let AddedComplexity = 15 in
4842 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4843 "movq\t{$src, $dst|$dst, $src}",
4844 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4846 XS, Requires<[HasSSE2]>;
4848 let AddedComplexity = 20 in
4849 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4850 "vmovq\t{$src, $dst|$dst, $src}",
4851 [(set VR128:$dst, (v2i64 (X86vzmovl
4852 (loadv2i64 addr:$src))))],
4854 XS, VEX, Requires<[HasAVX]>;
4855 let AddedComplexity = 20 in {
4856 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4857 "movq\t{$src, $dst|$dst, $src}",
4858 [(set VR128:$dst, (v2i64 (X86vzmovl
4859 (loadv2i64 addr:$src))))],
4861 XS, Requires<[HasSSE2]>;
4864 let AddedComplexity = 20 in {
4865 let Predicates = [HasAVX] in {
4866 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4867 (VMOVZPQILo2PQIrm addr:$src)>;
4868 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4869 (VMOVZPQILo2PQIrr VR128:$src)>;
4871 let Predicates = [HasSSE2] in {
4872 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4873 (MOVZPQILo2PQIrm addr:$src)>;
4874 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4875 (MOVZPQILo2PQIrr VR128:$src)>;
4879 // Instructions to match in the assembler
4880 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4881 "movq\t{$src, $dst|$dst, $src}", [],
4882 IIC_SSE_MOVDQ>, VEX, VEX_W;
4883 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4884 "movq\t{$src, $dst|$dst, $src}", [],
4885 IIC_SSE_MOVDQ>, VEX, VEX_W;
4886 // Recognize "movd" with GR64 destination, but encode as a "movq"
4887 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4888 "movd\t{$src, $dst|$dst, $src}", [],
4889 IIC_SSE_MOVDQ>, VEX, VEX_W;
4891 // Instructions for the disassembler
4892 // xr = XMM register
4895 let Predicates = [HasAVX] in
4896 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4897 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4898 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4899 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4901 //===---------------------------------------------------------------------===//
4902 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4903 //===---------------------------------------------------------------------===//
4904 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4905 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4906 X86MemOperand x86memop> {
4907 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4908 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4909 [(set RC:$dst, (vt (OpNode RC:$src)))],
4911 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4913 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4917 let Predicates = [HasAVX] in {
4918 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4919 v4f32, VR128, memopv4f32, f128mem>, VEX;
4920 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4921 v4f32, VR128, memopv4f32, f128mem>, VEX;
4922 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4923 v8f32, VR256, memopv8f32, f256mem>, VEX;
4924 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4925 v8f32, VR256, memopv8f32, f256mem>, VEX;
4927 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4928 memopv4f32, f128mem>;
4929 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4930 memopv4f32, f128mem>;
4932 let Predicates = [HasAVX] in {
4933 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4934 (VMOVSHDUPrr VR128:$src)>;
4935 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4936 (VMOVSHDUPrm addr:$src)>;
4937 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4938 (VMOVSLDUPrr VR128:$src)>;
4939 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4940 (VMOVSLDUPrm addr:$src)>;
4941 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4942 (VMOVSHDUPYrr VR256:$src)>;
4943 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4944 (VMOVSHDUPYrm addr:$src)>;
4945 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4946 (VMOVSLDUPYrr VR256:$src)>;
4947 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4948 (VMOVSLDUPYrm addr:$src)>;
4951 let Predicates = [HasSSE3] in {
4952 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4953 (MOVSHDUPrr VR128:$src)>;
4954 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4955 (MOVSHDUPrm addr:$src)>;
4956 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4957 (MOVSLDUPrr VR128:$src)>;
4958 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4959 (MOVSLDUPrm addr:$src)>;
4962 //===---------------------------------------------------------------------===//
4963 // SSE3 - Replicate Double FP - MOVDDUP
4964 //===---------------------------------------------------------------------===//
4966 multiclass sse3_replicate_dfp<string OpcodeStr> {
4967 let neverHasSideEffects = 1 in
4968 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4969 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4970 [], IIC_SSE_MOV_LH>;
4971 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4972 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4975 (scalar_to_vector (loadf64 addr:$src)))))],
4979 // FIXME: Merge with above classe when there're patterns for the ymm version
4980 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4981 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4983 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4984 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4985 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4988 (scalar_to_vector (loadf64 addr:$src)))))]>;
4991 let Predicates = [HasAVX] in {
4992 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4993 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4996 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4998 let Predicates = [HasAVX] in {
4999 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5000 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5001 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5002 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5003 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5004 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5005 def : Pat<(X86Movddup (bc_v2f64
5006 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5007 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5010 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5011 (VMOVDDUPYrm addr:$src)>;
5012 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5013 (VMOVDDUPYrm addr:$src)>;
5014 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5015 (VMOVDDUPYrm addr:$src)>;
5016 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5017 (VMOVDDUPYrr VR256:$src)>;
5020 let Predicates = [HasSSE3] in {
5021 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5022 (MOVDDUPrm addr:$src)>;
5023 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5024 (MOVDDUPrm addr:$src)>;
5025 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5026 (MOVDDUPrm addr:$src)>;
5027 def : Pat<(X86Movddup (bc_v2f64
5028 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5029 (MOVDDUPrm addr:$src)>;
5032 //===---------------------------------------------------------------------===//
5033 // SSE3 - Move Unaligned Integer
5034 //===---------------------------------------------------------------------===//
5036 let Predicates = [HasAVX] in {
5037 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5038 "vlddqu\t{$src, $dst|$dst, $src}",
5039 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5040 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5041 "vlddqu\t{$src, $dst|$dst, $src}",
5042 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5044 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5045 "lddqu\t{$src, $dst|$dst, $src}",
5046 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5049 //===---------------------------------------------------------------------===//
5050 // SSE3 - Arithmetic
5051 //===---------------------------------------------------------------------===//
5053 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5054 X86MemOperand x86memop, OpndItins itins,
5056 def rr : I<0xD0, MRMSrcReg,
5057 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5059 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5060 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5061 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5062 def rm : I<0xD0, MRMSrcMem,
5063 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5065 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5066 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5067 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5070 let Predicates = [HasAVX] in {
5071 let ExeDomain = SSEPackedSingle in {
5072 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5073 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5074 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5075 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5077 let ExeDomain = SSEPackedDouble in {
5078 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5079 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5080 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5081 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5084 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5085 let ExeDomain = SSEPackedSingle in
5086 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5087 f128mem, SSE_ALU_F32P>, TB, XD;
5088 let ExeDomain = SSEPackedDouble in
5089 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5090 f128mem, SSE_ALU_F64P>, TB, OpSize;
5093 //===---------------------------------------------------------------------===//
5094 // SSE3 Instructions
5095 //===---------------------------------------------------------------------===//
5098 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5099 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5100 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5102 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5104 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5106 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5109 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5110 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5111 IIC_SSE_HADDSUB_RM>;
5113 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5114 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5115 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5117 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5118 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5119 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5121 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5125 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5126 IIC_SSE_HADDSUB_RM>;
5129 let Predicates = [HasAVX] in {
5130 let ExeDomain = SSEPackedSingle in {
5131 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5132 X86fhadd, 0>, VEX_4V;
5133 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5134 X86fhsub, 0>, VEX_4V;
5135 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5136 X86fhadd, 0>, VEX_4V;
5137 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5138 X86fhsub, 0>, VEX_4V;
5140 let ExeDomain = SSEPackedDouble in {
5141 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5142 X86fhadd, 0>, VEX_4V;
5143 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5144 X86fhsub, 0>, VEX_4V;
5145 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5146 X86fhadd, 0>, VEX_4V;
5147 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5148 X86fhsub, 0>, VEX_4V;
5152 let Constraints = "$src1 = $dst" in {
5153 let ExeDomain = SSEPackedSingle in {
5154 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5155 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5157 let ExeDomain = SSEPackedDouble in {
5158 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5159 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5163 //===---------------------------------------------------------------------===//
5164 // SSSE3 - Packed Absolute Instructions
5165 //===---------------------------------------------------------------------===//
5168 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5169 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5170 Intrinsic IntId128> {
5171 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5174 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5177 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5179 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5182 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5186 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5187 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5188 Intrinsic IntId256> {
5189 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5192 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5195 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5200 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5203 let Predicates = [HasAVX] in {
5204 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5205 int_x86_ssse3_pabs_b_128>, VEX;
5206 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5207 int_x86_ssse3_pabs_w_128>, VEX;
5208 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5209 int_x86_ssse3_pabs_d_128>, VEX;
5212 let Predicates = [HasAVX2] in {
5213 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5214 int_x86_avx2_pabs_b>, VEX;
5215 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5216 int_x86_avx2_pabs_w>, VEX;
5217 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5218 int_x86_avx2_pabs_d>, VEX;
5221 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5222 int_x86_ssse3_pabs_b_128>;
5223 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5224 int_x86_ssse3_pabs_w_128>;
5225 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5226 int_x86_ssse3_pabs_d_128>;
5228 //===---------------------------------------------------------------------===//
5229 // SSSE3 - Packed Binary Operator Instructions
5230 //===---------------------------------------------------------------------===//
5232 def SSE_PHADDSUBD : OpndItins<
5233 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5235 def SSE_PHADDSUBSW : OpndItins<
5236 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5238 def SSE_PHADDSUBW : OpndItins<
5239 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5241 def SSE_PSHUFB : OpndItins<
5242 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5244 def SSE_PSIGN : OpndItins<
5245 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5247 def SSE_PMULHRSW : OpndItins<
5248 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5251 /// SS3I_binop_rm - Simple SSSE3 bin op
5252 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5253 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5254 X86MemOperand x86memop, OpndItins itins,
5256 let isCommutable = 1 in
5257 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5258 (ins RC:$src1, RC:$src2),
5260 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5262 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5264 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5265 (ins RC:$src1, x86memop:$src2),
5267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5270 (OpVT (OpNode RC:$src1,
5271 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5274 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5275 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5276 Intrinsic IntId128, OpndItins itins,
5278 let isCommutable = 1 in
5279 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5280 (ins VR128:$src1, VR128:$src2),
5282 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5283 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5284 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5286 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5287 (ins VR128:$src1, i128mem:$src2),
5289 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5292 (IntId128 VR128:$src1,
5293 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5296 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5297 Intrinsic IntId256> {
5298 let isCommutable = 1 in
5299 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5300 (ins VR256:$src1, VR256:$src2),
5301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5302 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5304 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5305 (ins VR256:$src1, i256mem:$src2),
5306 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5308 (IntId256 VR256:$src1,
5309 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5312 let ImmT = NoImm, Predicates = [HasAVX] in {
5313 let isCommutable = 0 in {
5314 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5315 memopv2i64, i128mem,
5316 SSE_PHADDSUBW, 0>, VEX_4V;
5317 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5318 memopv2i64, i128mem,
5319 SSE_PHADDSUBD, 0>, VEX_4V;
5320 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5321 memopv2i64, i128mem,
5322 SSE_PHADDSUBW, 0>, VEX_4V;
5323 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5324 memopv2i64, i128mem,
5325 SSE_PHADDSUBD, 0>, VEX_4V;
5326 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5327 memopv2i64, i128mem,
5328 SSE_PSIGN, 0>, VEX_4V;
5329 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5330 memopv2i64, i128mem,
5331 SSE_PSIGN, 0>, VEX_4V;
5332 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5333 memopv2i64, i128mem,
5334 SSE_PSIGN, 0>, VEX_4V;
5335 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5336 memopv2i64, i128mem,
5337 SSE_PSHUFB, 0>, VEX_4V;
5338 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5339 int_x86_ssse3_phadd_sw_128,
5340 SSE_PHADDSUBSW, 0>, VEX_4V;
5341 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5342 int_x86_ssse3_phsub_sw_128,
5343 SSE_PHADDSUBSW, 0>, VEX_4V;
5344 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5345 int_x86_ssse3_pmadd_ub_sw_128,
5346 SSE_PMADD, 0>, VEX_4V;
5348 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5349 int_x86_ssse3_pmul_hr_sw_128,
5350 SSE_PMULHRSW, 0>, VEX_4V;
5353 let ImmT = NoImm, Predicates = [HasAVX2] in {
5354 let isCommutable = 0 in {
5355 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5356 memopv4i64, i256mem,
5357 SSE_PHADDSUBW, 0>, VEX_4V;
5358 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5359 memopv4i64, i256mem,
5360 SSE_PHADDSUBW, 0>, VEX_4V;
5361 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5362 memopv4i64, i256mem,
5363 SSE_PHADDSUBW, 0>, VEX_4V;
5364 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5365 memopv4i64, i256mem,
5366 SSE_PHADDSUBW, 0>, VEX_4V;
5367 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5368 memopv4i64, i256mem,
5369 SSE_PHADDSUBW, 0>, VEX_4V;
5370 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5371 memopv4i64, i256mem,
5372 SSE_PHADDSUBW, 0>, VEX_4V;
5373 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5374 memopv4i64, i256mem,
5375 SSE_PHADDSUBW, 0>, VEX_4V;
5376 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5377 memopv4i64, i256mem,
5378 SSE_PHADDSUBW, 0>, VEX_4V;
5379 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5380 int_x86_avx2_phadd_sw>, VEX_4V;
5381 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5382 int_x86_avx2_phsub_sw>, VEX_4V;
5383 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5384 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5386 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5387 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5390 // None of these have i8 immediate fields.
5391 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5392 let isCommutable = 0 in {
5393 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5394 memopv2i64, i128mem, SSE_PHADDSUBW>;
5395 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5396 memopv2i64, i128mem, SSE_PHADDSUBD>;
5397 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5398 memopv2i64, i128mem, SSE_PHADDSUBW>;
5399 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5400 memopv2i64, i128mem, SSE_PHADDSUBD>;
5401 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5402 memopv2i64, i128mem, SSE_PSIGN>;
5403 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5404 memopv2i64, i128mem, SSE_PSIGN>;
5405 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5406 memopv2i64, i128mem, SSE_PSIGN>;
5407 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5408 memopv2i64, i128mem, SSE_PSHUFB>;
5409 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5410 int_x86_ssse3_phadd_sw_128,
5412 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5413 int_x86_ssse3_phsub_sw_128,
5415 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5416 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5418 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5419 int_x86_ssse3_pmul_hr_sw_128,
5423 //===---------------------------------------------------------------------===//
5424 // SSSE3 - Packed Align Instruction Patterns
5425 //===---------------------------------------------------------------------===//
5427 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5428 let neverHasSideEffects = 1 in {
5429 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5430 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5432 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5434 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5435 [], IIC_SSE_PALIGNR>, OpSize;
5437 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5438 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5440 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5442 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5443 [], IIC_SSE_PALIGNR>, OpSize;
5447 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5448 let neverHasSideEffects = 1 in {
5449 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5450 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5452 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5455 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5456 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5458 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5463 let Predicates = [HasAVX] in
5464 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5465 let Predicates = [HasAVX2] in
5466 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5467 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5468 defm PALIGN : ssse3_palign<"palignr">;
5470 let Predicates = [HasAVX2] in {
5471 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5472 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5473 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5474 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5475 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5476 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5477 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5478 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5481 let Predicates = [HasAVX] in {
5482 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5483 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5484 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5485 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5486 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5487 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5488 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5489 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5492 let Predicates = [HasSSSE3] in {
5493 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5494 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5495 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5496 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5497 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5498 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5499 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5500 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5503 //===---------------------------------------------------------------------===//
5504 // SSSE3 - Thread synchronization
5505 //===---------------------------------------------------------------------===//
5507 let usesCustomInserter = 1 in {
5508 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5509 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5510 Requires<[HasSSE3]>;
5511 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5512 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5513 Requires<[HasSSE3]>;
5516 let Uses = [EAX, ECX, EDX] in
5517 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5518 TB, Requires<[HasSSE3]>;
5519 let Uses = [ECX, EAX] in
5520 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5521 TB, Requires<[HasSSE3]>;
5523 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5524 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5526 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5527 Requires<[In32BitMode]>;
5528 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5529 Requires<[In64BitMode]>;
5531 //===----------------------------------------------------------------------===//
5532 // SSE4.1 - Packed Move with Sign/Zero Extend
5533 //===----------------------------------------------------------------------===//
5535 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5536 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5538 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5540 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5543 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5547 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5549 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5551 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5553 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5555 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5558 let Predicates = [HasAVX] in {
5559 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5561 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5563 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5565 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5567 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5569 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5573 let Predicates = [HasAVX2] in {
5574 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5575 int_x86_avx2_pmovsxbw>, VEX;
5576 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5577 int_x86_avx2_pmovsxwd>, VEX;
5578 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5579 int_x86_avx2_pmovsxdq>, VEX;
5580 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5581 int_x86_avx2_pmovzxbw>, VEX;
5582 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5583 int_x86_avx2_pmovzxwd>, VEX;
5584 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5585 int_x86_avx2_pmovzxdq>, VEX;
5588 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5589 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5590 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5591 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5592 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5593 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5595 let Predicates = [HasAVX] in {
5596 // Common patterns involving scalar load.
5597 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5598 (VPMOVSXBWrm addr:$src)>;
5599 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5600 (VPMOVSXBWrm addr:$src)>;
5602 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5603 (VPMOVSXWDrm addr:$src)>;
5604 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5605 (VPMOVSXWDrm addr:$src)>;
5607 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5608 (VPMOVSXDQrm addr:$src)>;
5609 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5610 (VPMOVSXDQrm addr:$src)>;
5612 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5613 (VPMOVZXBWrm addr:$src)>;
5614 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5615 (VPMOVZXBWrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5618 (VPMOVZXWDrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5620 (VPMOVZXWDrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5623 (VPMOVZXDQrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5625 (VPMOVZXDQrm addr:$src)>;
5628 let Predicates = [HasSSE41] in {
5629 // Common patterns involving scalar load.
5630 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5631 (PMOVSXBWrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5633 (PMOVSXBWrm addr:$src)>;
5635 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5636 (PMOVSXWDrm addr:$src)>;
5637 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5638 (PMOVSXWDrm addr:$src)>;
5640 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5641 (PMOVSXDQrm addr:$src)>;
5642 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5643 (PMOVSXDQrm addr:$src)>;
5645 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5646 (PMOVZXBWrm addr:$src)>;
5647 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5648 (PMOVZXBWrm addr:$src)>;
5650 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5651 (PMOVZXWDrm addr:$src)>;
5652 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5653 (PMOVZXWDrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5656 (PMOVZXDQrm addr:$src)>;
5657 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5658 (PMOVZXDQrm addr:$src)>;
5661 let Predicates = [HasAVX2] in {
5662 let AddedComplexity = 15 in {
5663 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5664 (VPMOVZXDQYrr VR128:$src)>;
5665 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5666 (VPMOVZXWDYrr VR128:$src)>;
5669 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5670 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5673 let Predicates = [HasAVX] in {
5674 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5675 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5678 let Predicates = [HasSSE41] in {
5679 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5680 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5684 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5685 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5686 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5687 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5689 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5692 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5696 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5698 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5700 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5702 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5703 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5705 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5709 let Predicates = [HasAVX] in {
5710 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5712 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5714 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5716 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5720 let Predicates = [HasAVX2] in {
5721 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5722 int_x86_avx2_pmovsxbd>, VEX;
5723 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5724 int_x86_avx2_pmovsxwq>, VEX;
5725 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5726 int_x86_avx2_pmovzxbd>, VEX;
5727 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5728 int_x86_avx2_pmovzxwq>, VEX;
5731 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5732 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5733 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5734 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5736 let Predicates = [HasAVX] in {
5737 // Common patterns involving scalar load
5738 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5739 (VPMOVSXBDrm addr:$src)>;
5740 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5741 (VPMOVSXWQrm addr:$src)>;
5743 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5744 (VPMOVZXBDrm addr:$src)>;
5745 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5746 (VPMOVZXWQrm addr:$src)>;
5749 let Predicates = [HasSSE41] in {
5750 // Common patterns involving scalar load
5751 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5752 (PMOVSXBDrm addr:$src)>;
5753 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5754 (PMOVSXWQrm addr:$src)>;
5756 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5757 (PMOVZXBDrm addr:$src)>;
5758 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5759 (PMOVZXWQrm addr:$src)>;
5762 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5763 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5765 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5767 // Expecting a i16 load any extended to i32 value.
5768 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5770 [(set VR128:$dst, (IntId (bitconvert
5771 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5775 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5777 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5779 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5781 // Expecting a i16 load any extended to i32 value.
5782 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5784 [(set VR256:$dst, (IntId (bitconvert
5785 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5789 let Predicates = [HasAVX] in {
5790 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5792 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5795 let Predicates = [HasAVX2] in {
5796 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5797 int_x86_avx2_pmovsxbq>, VEX;
5798 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5799 int_x86_avx2_pmovzxbq>, VEX;
5801 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5802 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5804 let Predicates = [HasAVX] in {
5805 // Common patterns involving scalar load
5806 def : Pat<(int_x86_sse41_pmovsxbq
5807 (bitconvert (v4i32 (X86vzmovl
5808 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5809 (VPMOVSXBQrm addr:$src)>;
5811 def : Pat<(int_x86_sse41_pmovzxbq
5812 (bitconvert (v4i32 (X86vzmovl
5813 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5814 (VPMOVZXBQrm addr:$src)>;
5817 let Predicates = [HasSSE41] in {
5818 // Common patterns involving scalar load
5819 def : Pat<(int_x86_sse41_pmovsxbq
5820 (bitconvert (v4i32 (X86vzmovl
5821 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5822 (PMOVSXBQrm addr:$src)>;
5824 def : Pat<(int_x86_sse41_pmovzxbq
5825 (bitconvert (v4i32 (X86vzmovl
5826 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5827 (PMOVZXBQrm addr:$src)>;
5830 //===----------------------------------------------------------------------===//
5831 // SSE4.1 - Extract Instructions
5832 //===----------------------------------------------------------------------===//
5834 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5835 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5836 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5837 (ins VR128:$src1, i32i8imm:$src2),
5838 !strconcat(OpcodeStr,
5839 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5840 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5842 let neverHasSideEffects = 1, mayStore = 1 in
5843 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5844 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5845 !strconcat(OpcodeStr,
5846 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5849 // There's an AssertZext in the way of writing the store pattern
5850 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5853 let Predicates = [HasAVX] in {
5854 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5855 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5856 (ins VR128:$src1, i32i8imm:$src2),
5857 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5860 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5863 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5864 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5865 let neverHasSideEffects = 1, mayStore = 1 in
5866 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5867 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5868 !strconcat(OpcodeStr,
5869 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5872 // There's an AssertZext in the way of writing the store pattern
5873 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5876 let Predicates = [HasAVX] in
5877 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5879 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5882 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5883 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5884 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5885 (ins VR128:$src1, i32i8imm:$src2),
5886 !strconcat(OpcodeStr,
5887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5889 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5890 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5891 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5892 !strconcat(OpcodeStr,
5893 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5894 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5895 addr:$dst)]>, OpSize;
5898 let Predicates = [HasAVX] in
5899 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5901 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5903 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5904 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5905 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5906 (ins VR128:$src1, i32i8imm:$src2),
5907 !strconcat(OpcodeStr,
5908 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5910 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5911 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5912 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5913 !strconcat(OpcodeStr,
5914 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5915 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5916 addr:$dst)]>, OpSize, REX_W;
5919 let Predicates = [HasAVX] in
5920 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5922 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5924 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5926 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5927 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5928 (ins VR128:$src1, i32i8imm:$src2),
5929 !strconcat(OpcodeStr,
5930 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5932 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5934 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5935 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5936 !strconcat(OpcodeStr,
5937 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5938 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5939 addr:$dst)]>, OpSize;
5942 let ExeDomain = SSEPackedSingle in {
5943 let Predicates = [HasAVX] in {
5944 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5945 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5946 (ins VR128:$src1, i32i8imm:$src2),
5947 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5950 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5953 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5954 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5957 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5959 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5962 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5963 Requires<[HasSSE41]>;
5965 //===----------------------------------------------------------------------===//
5966 // SSE4.1 - Insert Instructions
5967 //===----------------------------------------------------------------------===//
5969 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5970 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5971 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5973 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5975 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5977 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5978 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5979 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5981 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5983 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5985 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5986 imm:$src3))]>, OpSize;
5989 let Predicates = [HasAVX] in
5990 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5991 let Constraints = "$src1 = $dst" in
5992 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5994 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5995 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5996 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5998 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6000 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6002 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6004 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6005 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6007 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6009 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6011 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6012 imm:$src3)))]>, OpSize;
6015 let Predicates = [HasAVX] in
6016 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6017 let Constraints = "$src1 = $dst" in
6018 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6020 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6021 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6022 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6024 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6026 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6028 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6030 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6031 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6033 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6035 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6037 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6038 imm:$src3)))]>, OpSize;
6041 let Predicates = [HasAVX] in
6042 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6043 let Constraints = "$src1 = $dst" in
6044 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6046 // insertps has a few different modes, there's the first two here below which
6047 // are optimized inserts that won't zero arbitrary elements in the destination
6048 // vector. The next one matches the intrinsic and could zero arbitrary elements
6049 // in the target vector.
6050 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6051 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6052 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6054 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6056 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6058 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6060 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6061 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6063 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6065 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6067 (X86insrtps VR128:$src1,
6068 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6069 imm:$src3))]>, OpSize;
6072 let ExeDomain = SSEPackedSingle in {
6073 let Predicates = [HasAVX] in
6074 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6075 let Constraints = "$src1 = $dst" in
6076 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6079 //===----------------------------------------------------------------------===//
6080 // SSE4.1 - Round Instructions
6081 //===----------------------------------------------------------------------===//
6083 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6084 X86MemOperand x86memop, RegisterClass RC,
6085 PatFrag mem_frag32, PatFrag mem_frag64,
6086 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6087 let ExeDomain = SSEPackedSingle in {
6088 // Intrinsic operation, reg.
6089 // Vector intrinsic operation, reg
6090 def PSr : SS4AIi8<opcps, MRMSrcReg,
6091 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6092 !strconcat(OpcodeStr,
6093 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6094 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6097 // Vector intrinsic operation, mem
6098 def PSm : SS4AIi8<opcps, MRMSrcMem,
6099 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6100 !strconcat(OpcodeStr,
6101 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6103 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6105 } // ExeDomain = SSEPackedSingle
6107 let ExeDomain = SSEPackedDouble in {
6108 // Vector intrinsic operation, reg
6109 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6110 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6111 !strconcat(OpcodeStr,
6112 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6113 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6116 // Vector intrinsic operation, mem
6117 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6118 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6119 !strconcat(OpcodeStr,
6120 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6122 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6124 } // ExeDomain = SSEPackedDouble
6127 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6130 Intrinsic F64Int, bit Is2Addr = 1> {
6131 let ExeDomain = GenericDomain in {
6133 def SSr : SS4AIi8<opcss, MRMSrcReg,
6134 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6136 !strconcat(OpcodeStr,
6137 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6138 !strconcat(OpcodeStr,
6139 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6142 // Intrinsic operation, reg.
6143 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6144 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6146 !strconcat(OpcodeStr,
6147 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6148 !strconcat(OpcodeStr,
6149 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6150 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6153 // Intrinsic operation, mem.
6154 def SSm : SS4AIi8<opcss, MRMSrcMem,
6155 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6157 !strconcat(OpcodeStr,
6158 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6159 !strconcat(OpcodeStr,
6160 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6162 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6166 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6167 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6169 !strconcat(OpcodeStr,
6170 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6171 !strconcat(OpcodeStr,
6172 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6175 // Intrinsic operation, reg.
6176 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6177 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6179 !strconcat(OpcodeStr,
6180 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6181 !strconcat(OpcodeStr,
6182 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6183 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6186 // Intrinsic operation, mem.
6187 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6188 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6190 !strconcat(OpcodeStr,
6191 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6192 !strconcat(OpcodeStr,
6193 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6195 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6197 } // ExeDomain = GenericDomain
6200 // FP round - roundss, roundps, roundsd, roundpd
6201 let Predicates = [HasAVX] in {
6203 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6204 memopv4f32, memopv2f64,
6205 int_x86_sse41_round_ps,
6206 int_x86_sse41_round_pd>, VEX;
6207 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6208 memopv8f32, memopv4f64,
6209 int_x86_avx_round_ps_256,
6210 int_x86_avx_round_pd_256>, VEX;
6211 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6212 int_x86_sse41_round_ss,
6213 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6215 def : Pat<(ffloor FR32:$src),
6216 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6217 def : Pat<(f64 (ffloor FR64:$src)),
6218 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6219 def : Pat<(f32 (fnearbyint FR32:$src)),
6220 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6221 def : Pat<(f64 (fnearbyint FR64:$src)),
6222 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6223 def : Pat<(f32 (fceil FR32:$src)),
6224 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6225 def : Pat<(f64 (fceil FR64:$src)),
6226 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6227 def : Pat<(f32 (frint FR32:$src)),
6228 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6229 def : Pat<(f64 (frint FR64:$src)),
6230 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6231 def : Pat<(f32 (ftrunc FR32:$src)),
6232 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6233 def : Pat<(f64 (ftrunc FR64:$src)),
6234 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6237 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6238 memopv4f32, memopv2f64,
6239 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6240 let Constraints = "$src1 = $dst" in
6241 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6242 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6244 def : Pat<(ffloor FR32:$src),
6245 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6246 def : Pat<(f64 (ffloor FR64:$src)),
6247 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6248 def : Pat<(f32 (fnearbyint FR32:$src)),
6249 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6250 def : Pat<(f64 (fnearbyint FR64:$src)),
6251 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6252 def : Pat<(f32 (fceil FR32:$src)),
6253 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6254 def : Pat<(f64 (fceil FR64:$src)),
6255 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6256 def : Pat<(f32 (frint FR32:$src)),
6257 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6258 def : Pat<(f64 (frint FR64:$src)),
6259 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6260 def : Pat<(f32 (ftrunc FR32:$src)),
6261 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6262 def : Pat<(f64 (ftrunc FR64:$src)),
6263 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6265 //===----------------------------------------------------------------------===//
6266 // SSE4.1 - Packed Bit Test
6267 //===----------------------------------------------------------------------===//
6269 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6270 // the intel intrinsic that corresponds to this.
6271 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6272 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6273 "vptest\t{$src2, $src1|$src1, $src2}",
6274 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6276 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6277 "vptest\t{$src2, $src1|$src1, $src2}",
6278 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6281 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6282 "vptest\t{$src2, $src1|$src1, $src2}",
6283 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6285 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6286 "vptest\t{$src2, $src1|$src1, $src2}",
6287 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6291 let Defs = [EFLAGS] in {
6292 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6293 "ptest\t{$src2, $src1|$src1, $src2}",
6294 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6296 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6297 "ptest\t{$src2, $src1|$src1, $src2}",
6298 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6302 // The bit test instructions below are AVX only
6303 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6304 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6305 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6306 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6307 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6308 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6309 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6310 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6314 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6315 let ExeDomain = SSEPackedSingle in {
6316 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6317 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6319 let ExeDomain = SSEPackedDouble in {
6320 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6321 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6325 //===----------------------------------------------------------------------===//
6326 // SSE4.1 - Misc Instructions
6327 //===----------------------------------------------------------------------===//
6329 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6330 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6331 "popcnt{w}\t{$src, $dst|$dst, $src}",
6332 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6334 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6335 "popcnt{w}\t{$src, $dst|$dst, $src}",
6336 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6337 (implicit EFLAGS)]>, OpSize, XS;
6339 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6340 "popcnt{l}\t{$src, $dst|$dst, $src}",
6341 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6343 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6344 "popcnt{l}\t{$src, $dst|$dst, $src}",
6345 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6346 (implicit EFLAGS)]>, XS;
6348 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6349 "popcnt{q}\t{$src, $dst|$dst, $src}",
6350 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6352 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6353 "popcnt{q}\t{$src, $dst|$dst, $src}",
6354 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6355 (implicit EFLAGS)]>, XS;
6360 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6361 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6362 Intrinsic IntId128> {
6363 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6366 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6367 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6372 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6375 let Predicates = [HasAVX] in
6376 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6377 int_x86_sse41_phminposuw>, VEX;
6378 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6379 int_x86_sse41_phminposuw>;
6381 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6382 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6383 Intrinsic IntId128, bit Is2Addr = 1> {
6384 let isCommutable = 1 in
6385 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6386 (ins VR128:$src1, VR128:$src2),
6388 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6389 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6390 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6391 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6392 (ins VR128:$src1, i128mem:$src2),
6394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6397 (IntId128 VR128:$src1,
6398 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6401 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6402 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6403 Intrinsic IntId256> {
6404 let isCommutable = 1 in
6405 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6406 (ins VR256:$src1, VR256:$src2),
6407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6408 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6409 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6410 (ins VR256:$src1, i256mem:$src2),
6411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6413 (IntId256 VR256:$src1,
6414 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6417 let Predicates = [HasAVX] in {
6418 let isCommutable = 0 in
6419 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6421 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6423 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6425 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6427 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6429 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6431 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6433 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6435 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6437 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6441 let Predicates = [HasAVX2] in {
6442 let isCommutable = 0 in
6443 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6444 int_x86_avx2_packusdw>, VEX_4V;
6445 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6446 int_x86_avx2_pmins_b>, VEX_4V;
6447 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6448 int_x86_avx2_pmins_d>, VEX_4V;
6449 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6450 int_x86_avx2_pminu_d>, VEX_4V;
6451 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6452 int_x86_avx2_pminu_w>, VEX_4V;
6453 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6454 int_x86_avx2_pmaxs_b>, VEX_4V;
6455 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6456 int_x86_avx2_pmaxs_d>, VEX_4V;
6457 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6458 int_x86_avx2_pmaxu_d>, VEX_4V;
6459 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6460 int_x86_avx2_pmaxu_w>, VEX_4V;
6461 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6462 int_x86_avx2_pmul_dq>, VEX_4V;
6465 let Constraints = "$src1 = $dst" in {
6466 let isCommutable = 0 in
6467 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6468 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6469 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6470 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6471 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6472 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6473 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6474 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6475 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6476 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6479 /// SS48I_binop_rm - Simple SSE41 binary operator.
6480 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6481 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6482 X86MemOperand x86memop, bit Is2Addr = 1> {
6483 let isCommutable = 1 in
6484 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6485 (ins RC:$src1, RC:$src2),
6487 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6488 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6489 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6490 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6491 (ins RC:$src1, x86memop:$src2),
6493 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6494 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6496 (OpVT (OpNode RC:$src1,
6497 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6500 let Predicates = [HasAVX] in {
6501 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6502 memopv2i64, i128mem, 0>, VEX_4V;
6503 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6504 memopv2i64, i128mem, 0>, VEX_4V;
6506 let Predicates = [HasAVX2] in {
6507 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6508 memopv4i64, i256mem, 0>, VEX_4V;
6509 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6510 memopv4i64, i256mem, 0>, VEX_4V;
6513 let Constraints = "$src1 = $dst" in {
6514 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6515 memopv2i64, i128mem>;
6516 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6517 memopv2i64, i128mem>;
6520 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6521 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6522 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6523 X86MemOperand x86memop, bit Is2Addr = 1> {
6524 let isCommutable = 1 in
6525 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6526 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6528 !strconcat(OpcodeStr,
6529 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6530 !strconcat(OpcodeStr,
6531 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6532 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6534 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6535 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6537 !strconcat(OpcodeStr,
6538 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6539 !strconcat(OpcodeStr,
6540 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6543 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6547 let Predicates = [HasAVX] in {
6548 let isCommutable = 0 in {
6549 let ExeDomain = SSEPackedSingle in {
6550 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6551 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6552 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6553 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6555 let ExeDomain = SSEPackedDouble in {
6556 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6557 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6558 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6559 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6561 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6562 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6563 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6564 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6566 let ExeDomain = SSEPackedSingle in
6567 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6568 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6569 let ExeDomain = SSEPackedDouble in
6570 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6571 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6572 let ExeDomain = SSEPackedSingle in
6573 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6574 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6577 let Predicates = [HasAVX2] in {
6578 let isCommutable = 0 in {
6579 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6580 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6581 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6582 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6586 let Constraints = "$src1 = $dst" in {
6587 let isCommutable = 0 in {
6588 let ExeDomain = SSEPackedSingle in
6589 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6590 VR128, memopv4f32, i128mem>;
6591 let ExeDomain = SSEPackedDouble in
6592 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6593 VR128, memopv2f64, i128mem>;
6594 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6595 VR128, memopv2i64, i128mem>;
6596 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6597 VR128, memopv2i64, i128mem>;
6599 let ExeDomain = SSEPackedSingle in
6600 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6601 VR128, memopv4f32, i128mem>;
6602 let ExeDomain = SSEPackedDouble in
6603 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6604 VR128, memopv2f64, i128mem>;
6607 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6608 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6609 RegisterClass RC, X86MemOperand x86memop,
6610 PatFrag mem_frag, Intrinsic IntId> {
6611 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6612 (ins RC:$src1, RC:$src2, RC:$src3),
6613 !strconcat(OpcodeStr,
6614 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6615 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6616 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6618 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6619 (ins RC:$src1, x86memop:$src2, RC:$src3),
6620 !strconcat(OpcodeStr,
6621 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6623 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6625 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6628 let Predicates = [HasAVX] in {
6629 let ExeDomain = SSEPackedDouble in {
6630 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6631 memopv2f64, int_x86_sse41_blendvpd>;
6632 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6633 memopv4f64, int_x86_avx_blendv_pd_256>;
6634 } // ExeDomain = SSEPackedDouble
6635 let ExeDomain = SSEPackedSingle in {
6636 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6637 memopv4f32, int_x86_sse41_blendvps>;
6638 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6639 memopv8f32, int_x86_avx_blendv_ps_256>;
6640 } // ExeDomain = SSEPackedSingle
6641 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6642 memopv2i64, int_x86_sse41_pblendvb>;
6645 let Predicates = [HasAVX2] in {
6646 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6647 memopv4i64, int_x86_avx2_pblendvb>;
6650 let Predicates = [HasAVX] in {
6651 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6652 (v16i8 VR128:$src2))),
6653 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6654 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6655 (v4i32 VR128:$src2))),
6656 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6657 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6658 (v4f32 VR128:$src2))),
6659 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6660 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6661 (v2i64 VR128:$src2))),
6662 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6663 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6664 (v2f64 VR128:$src2))),
6665 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6666 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6667 (v8i32 VR256:$src2))),
6668 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6669 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6670 (v8f32 VR256:$src2))),
6671 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6672 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6673 (v4i64 VR256:$src2))),
6674 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6675 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6676 (v4f64 VR256:$src2))),
6677 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6679 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6681 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6682 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6684 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6686 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6688 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6689 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6691 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6692 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6694 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6697 let Predicates = [HasAVX2] in {
6698 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6699 (v32i8 VR256:$src2))),
6700 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6701 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6703 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6706 /// SS41I_ternary_int - SSE 4.1 ternary operator
6707 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6708 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6710 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6711 (ins VR128:$src1, VR128:$src2),
6712 !strconcat(OpcodeStr,
6713 "\t{$src2, $dst|$dst, $src2}"),
6714 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6717 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6718 (ins VR128:$src1, i128mem:$src2),
6719 !strconcat(OpcodeStr,
6720 "\t{$src2, $dst|$dst, $src2}"),
6723 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6727 let ExeDomain = SSEPackedDouble in
6728 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6729 int_x86_sse41_blendvpd>;
6730 let ExeDomain = SSEPackedSingle in
6731 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6732 int_x86_sse41_blendvps>;
6733 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6734 int_x86_sse41_pblendvb>;
6736 let Predicates = [HasSSE41] in {
6737 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6738 (v16i8 VR128:$src2))),
6739 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6740 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6741 (v4i32 VR128:$src2))),
6742 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6743 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6744 (v4f32 VR128:$src2))),
6745 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6746 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6747 (v2i64 VR128:$src2))),
6748 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6749 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6750 (v2f64 VR128:$src2))),
6751 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6753 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6755 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6756 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6758 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6759 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6761 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6765 let Predicates = [HasAVX] in
6766 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6767 "vmovntdqa\t{$src, $dst|$dst, $src}",
6768 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6770 let Predicates = [HasAVX2] in
6771 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6772 "vmovntdqa\t{$src, $dst|$dst, $src}",
6773 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6775 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6776 "movntdqa\t{$src, $dst|$dst, $src}",
6777 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6780 //===----------------------------------------------------------------------===//
6781 // SSE4.2 - Compare Instructions
6782 //===----------------------------------------------------------------------===//
6784 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6785 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6786 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6787 X86MemOperand x86memop, bit Is2Addr = 1> {
6788 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6789 (ins RC:$src1, RC:$src2),
6791 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6792 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6793 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6795 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6796 (ins RC:$src1, x86memop:$src2),
6798 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6799 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6801 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6804 let Predicates = [HasAVX] in
6805 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6806 memopv2i64, i128mem, 0>, VEX_4V;
6808 let Predicates = [HasAVX2] in
6809 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6810 memopv4i64, i256mem, 0>, VEX_4V;
6812 let Constraints = "$src1 = $dst" in
6813 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6814 memopv2i64, i128mem>;
6816 //===----------------------------------------------------------------------===//
6817 // SSE4.2 - String/text Processing Instructions
6818 //===----------------------------------------------------------------------===//
6820 // Packed Compare Implicit Length Strings, Return Mask
6821 multiclass pseudo_pcmpistrm<string asm> {
6822 def REG : PseudoI<(outs VR128:$dst),
6823 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6824 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6826 def MEM : PseudoI<(outs VR128:$dst),
6827 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6828 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6829 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6832 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6833 let AddedComplexity = 1 in
6834 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6835 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6838 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6839 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6840 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6841 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6843 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6844 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6845 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6848 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6849 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6850 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6851 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6853 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6854 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6855 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6858 // Packed Compare Explicit Length Strings, Return Mask
6859 multiclass pseudo_pcmpestrm<string asm> {
6860 def REG : PseudoI<(outs VR128:$dst),
6861 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6862 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6863 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6864 def MEM : PseudoI<(outs VR128:$dst),
6865 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6866 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6867 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6870 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6871 let AddedComplexity = 1 in
6872 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6873 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6876 let Predicates = [HasAVX],
6877 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6878 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6879 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6880 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6882 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6883 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6884 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6887 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6888 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6889 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6890 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6892 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6893 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6894 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6897 // Packed Compare Implicit Length Strings, Return Index
6898 let Defs = [ECX, EFLAGS] in {
6899 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6900 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6901 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6902 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6903 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6904 (implicit EFLAGS)]>, OpSize;
6905 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6906 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6907 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6908 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6909 (implicit EFLAGS)]>, OpSize;
6913 let Predicates = [HasAVX] in {
6914 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6916 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6918 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6920 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6922 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6924 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6928 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6929 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6930 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6931 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6932 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6933 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6935 // Packed Compare Explicit Length Strings, Return Index
6936 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6937 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6938 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6939 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6940 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6941 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6942 (implicit EFLAGS)]>, OpSize;
6943 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6944 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6945 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6947 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6948 (implicit EFLAGS)]>, OpSize;
6952 let Predicates = [HasAVX] in {
6953 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6955 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6957 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6959 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6961 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6963 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6967 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6968 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6969 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6970 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6971 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6972 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6974 //===----------------------------------------------------------------------===//
6975 // SSE4.2 - CRC Instructions
6976 //===----------------------------------------------------------------------===//
6978 // No CRC instructions have AVX equivalents
6980 // crc intrinsic instruction
6981 // This set of instructions are only rm, the only difference is the size
6983 let Constraints = "$src1 = $dst" in {
6984 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6985 (ins GR32:$src1, i8mem:$src2),
6986 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6988 (int_x86_sse42_crc32_32_8 GR32:$src1,
6989 (load addr:$src2)))]>;
6990 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6991 (ins GR32:$src1, GR8:$src2),
6992 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6994 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6995 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6996 (ins GR32:$src1, i16mem:$src2),
6997 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6999 (int_x86_sse42_crc32_32_16 GR32:$src1,
7000 (load addr:$src2)))]>,
7002 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7003 (ins GR32:$src1, GR16:$src2),
7004 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7006 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7008 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7009 (ins GR32:$src1, i32mem:$src2),
7010 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7012 (int_x86_sse42_crc32_32_32 GR32:$src1,
7013 (load addr:$src2)))]>;
7014 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7015 (ins GR32:$src1, GR32:$src2),
7016 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7018 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7019 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7020 (ins GR64:$src1, i8mem:$src2),
7021 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7023 (int_x86_sse42_crc32_64_8 GR64:$src1,
7024 (load addr:$src2)))]>,
7026 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7027 (ins GR64:$src1, GR8:$src2),
7028 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7030 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7032 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7033 (ins GR64:$src1, i64mem:$src2),
7034 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7036 (int_x86_sse42_crc32_64_64 GR64:$src1,
7037 (load addr:$src2)))]>,
7039 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7040 (ins GR64:$src1, GR64:$src2),
7041 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7043 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7047 //===----------------------------------------------------------------------===//
7048 // AES-NI Instructions
7049 //===----------------------------------------------------------------------===//
7051 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7052 Intrinsic IntId128, bit Is2Addr = 1> {
7053 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7054 (ins VR128:$src1, VR128:$src2),
7056 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7057 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7058 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7060 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7061 (ins VR128:$src1, i128mem:$src2),
7063 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7064 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7066 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7069 // Perform One Round of an AES Encryption/Decryption Flow
7070 let Predicates = [HasAVX, HasAES] in {
7071 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7072 int_x86_aesni_aesenc, 0>, VEX_4V;
7073 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7074 int_x86_aesni_aesenclast, 0>, VEX_4V;
7075 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7076 int_x86_aesni_aesdec, 0>, VEX_4V;
7077 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7078 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7081 let Constraints = "$src1 = $dst" in {
7082 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7083 int_x86_aesni_aesenc>;
7084 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7085 int_x86_aesni_aesenclast>;
7086 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7087 int_x86_aesni_aesdec>;
7088 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7089 int_x86_aesni_aesdeclast>;
7092 // Perform the AES InvMixColumn Transformation
7093 let Predicates = [HasAVX, HasAES] in {
7094 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7096 "vaesimc\t{$src1, $dst|$dst, $src1}",
7098 (int_x86_aesni_aesimc VR128:$src1))]>,
7100 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7101 (ins i128mem:$src1),
7102 "vaesimc\t{$src1, $dst|$dst, $src1}",
7103 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7106 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7108 "aesimc\t{$src1, $dst|$dst, $src1}",
7110 (int_x86_aesni_aesimc VR128:$src1))]>,
7112 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7113 (ins i128mem:$src1),
7114 "aesimc\t{$src1, $dst|$dst, $src1}",
7115 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7118 // AES Round Key Generation Assist
7119 let Predicates = [HasAVX, HasAES] in {
7120 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7121 (ins VR128:$src1, i8imm:$src2),
7122 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7124 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7126 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7127 (ins i128mem:$src1, i8imm:$src2),
7128 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7130 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7133 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7134 (ins VR128:$src1, i8imm:$src2),
7135 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7137 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7139 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7140 (ins i128mem:$src1, i8imm:$src2),
7141 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7143 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7146 //===----------------------------------------------------------------------===//
7147 // PCLMUL Instructions
7148 //===----------------------------------------------------------------------===//
7150 // AVX carry-less Multiplication instructions
7151 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7152 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7153 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7155 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7157 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7158 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7159 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7160 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7161 (memopv2i64 addr:$src2), imm:$src3))]>;
7163 // Carry-less Multiplication instructions
7164 let Constraints = "$src1 = $dst" in {
7165 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7166 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7167 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7169 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7171 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7172 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7173 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7174 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7175 (memopv2i64 addr:$src2), imm:$src3))]>;
7176 } // Constraints = "$src1 = $dst"
7179 multiclass pclmul_alias<string asm, int immop> {
7180 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7181 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7183 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7184 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7186 def : InstAlias<!strconcat("vpclmul", asm,
7187 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7188 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7190 def : InstAlias<!strconcat("vpclmul", asm,
7191 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7192 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7194 defm : pclmul_alias<"hqhq", 0x11>;
7195 defm : pclmul_alias<"hqlq", 0x01>;
7196 defm : pclmul_alias<"lqhq", 0x10>;
7197 defm : pclmul_alias<"lqlq", 0x00>;
7199 //===----------------------------------------------------------------------===//
7200 // SSE4A Instructions
7201 //===----------------------------------------------------------------------===//
7203 let Predicates = [HasSSE4A] in {
7205 let Constraints = "$src = $dst" in {
7206 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7207 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7208 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7209 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7210 imm:$idx))]>, TB, OpSize;
7211 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7212 (ins VR128:$src, VR128:$mask),
7213 "extrq\t{$mask, $src|$src, $mask}",
7214 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7215 VR128:$mask))]>, TB, OpSize;
7217 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7218 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7219 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7220 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7221 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7222 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7223 (ins VR128:$src, VR128:$mask),
7224 "insertq\t{$mask, $src|$src, $mask}",
7225 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7226 VR128:$mask))]>, XD;
7229 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7230 "movntss\t{$src, $dst|$dst, $src}",
7231 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7233 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7234 "movntsd\t{$src, $dst|$dst, $src}",
7235 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7238 //===----------------------------------------------------------------------===//
7240 //===----------------------------------------------------------------------===//
7242 //===----------------------------------------------------------------------===//
7243 // VBROADCAST - Load from memory and broadcast to all elements of the
7244 // destination operand
7246 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7247 X86MemOperand x86memop, Intrinsic Int> :
7248 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7250 [(set RC:$dst, (Int addr:$src))]>, VEX;
7252 // AVX2 adds register forms
7253 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7255 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7256 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7257 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7259 let ExeDomain = SSEPackedSingle in {
7260 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7261 int_x86_avx_vbroadcast_ss>;
7262 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7263 int_x86_avx_vbroadcast_ss_256>;
7265 let ExeDomain = SSEPackedDouble in
7266 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7267 int_x86_avx_vbroadcast_sd_256>;
7268 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7269 int_x86_avx_vbroadcastf128_pd_256>;
7271 let ExeDomain = SSEPackedSingle in {
7272 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7273 int_x86_avx2_vbroadcast_ss_ps>;
7274 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7275 int_x86_avx2_vbroadcast_ss_ps_256>;
7277 let ExeDomain = SSEPackedDouble in
7278 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7279 int_x86_avx2_vbroadcast_sd_pd_256>;
7281 let Predicates = [HasAVX2] in
7282 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7283 int_x86_avx2_vbroadcasti128>;
7285 let Predicates = [HasAVX] in
7286 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7287 (VBROADCASTF128 addr:$src)>;
7290 //===----------------------------------------------------------------------===//
7291 // VINSERTF128 - Insert packed floating-point values
7293 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7294 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7295 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7296 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7299 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7300 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7301 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7305 let Predicates = [HasAVX] in {
7306 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7308 (VINSERTF128rr VR256:$src1, VR128:$src2,
7309 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7310 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7312 (VINSERTF128rr VR256:$src1, VR128:$src2,
7313 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7314 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7316 (VINSERTF128rr VR256:$src1, VR128:$src2,
7317 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7318 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7320 (VINSERTF128rr VR256:$src1, VR128:$src2,
7321 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7322 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7324 (VINSERTF128rr VR256:$src1, VR128:$src2,
7325 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7326 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7328 (VINSERTF128rr VR256:$src1, VR128:$src2,
7329 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7331 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7333 (VINSERTF128rm VR256:$src1, addr:$src2,
7334 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7335 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7337 (VINSERTF128rm VR256:$src1, addr:$src2,
7338 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7339 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7341 (VINSERTF128rm VR256:$src1, addr:$src2,
7342 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7345 //===----------------------------------------------------------------------===//
7346 // VEXTRACTF128 - Extract packed floating-point values
7348 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7349 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7350 (ins VR256:$src1, i8imm:$src2),
7351 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7354 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7355 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7356 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7360 // Extract and store.
7361 let Predicates = [HasAVX] in {
7362 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7363 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7364 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7365 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7366 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7367 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7369 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7370 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7371 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7372 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7373 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7374 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7378 let Predicates = [HasAVX] in {
7379 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7380 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7381 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7382 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7383 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7384 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7386 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7387 (v4f32 (VEXTRACTF128rr
7388 (v8f32 VR256:$src1),
7389 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7390 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7391 (v2f64 (VEXTRACTF128rr
7392 (v4f64 VR256:$src1),
7393 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7394 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7395 (v2i64 (VEXTRACTF128rr
7396 (v4i64 VR256:$src1),
7397 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7398 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7399 (v4i32 (VEXTRACTF128rr
7400 (v8i32 VR256:$src1),
7401 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7402 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7403 (v8i16 (VEXTRACTF128rr
7404 (v16i16 VR256:$src1),
7405 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7406 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7407 (v16i8 (VEXTRACTF128rr
7408 (v32i8 VR256:$src1),
7409 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7412 //===----------------------------------------------------------------------===//
7413 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7415 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7416 Intrinsic IntLd, Intrinsic IntLd256,
7417 Intrinsic IntSt, Intrinsic IntSt256> {
7418 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7419 (ins VR128:$src1, f128mem:$src2),
7420 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7421 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7423 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7424 (ins VR256:$src1, f256mem:$src2),
7425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7426 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7428 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7429 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7431 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7432 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7433 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7435 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7438 let ExeDomain = SSEPackedSingle in
7439 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7440 int_x86_avx_maskload_ps,
7441 int_x86_avx_maskload_ps_256,
7442 int_x86_avx_maskstore_ps,
7443 int_x86_avx_maskstore_ps_256>;
7444 let ExeDomain = SSEPackedDouble in
7445 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7446 int_x86_avx_maskload_pd,
7447 int_x86_avx_maskload_pd_256,
7448 int_x86_avx_maskstore_pd,
7449 int_x86_avx_maskstore_pd_256>;
7451 //===----------------------------------------------------------------------===//
7452 // VPERMIL - Permute Single and Double Floating-Point Values
7454 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7455 RegisterClass RC, X86MemOperand x86memop_f,
7456 X86MemOperand x86memop_i, PatFrag i_frag,
7457 Intrinsic IntVar, ValueType vt> {
7458 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7459 (ins RC:$src1, RC:$src2),
7460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7461 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7462 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7463 (ins RC:$src1, x86memop_i:$src2),
7464 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7465 [(set RC:$dst, (IntVar RC:$src1,
7466 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7468 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7469 (ins RC:$src1, i8imm:$src2),
7470 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7471 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7472 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7473 (ins x86memop_f:$src1, i8imm:$src2),
7474 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7476 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7479 let ExeDomain = SSEPackedSingle in {
7480 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7481 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7482 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7483 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7485 let ExeDomain = SSEPackedDouble in {
7486 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7487 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7488 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7489 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7492 let Predicates = [HasAVX] in {
7493 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7494 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7495 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7496 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7497 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7499 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7500 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7501 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7503 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7504 (VPERMILPDri VR128:$src1, imm:$imm)>;
7505 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7506 (VPERMILPDmi addr:$src1, imm:$imm)>;
7509 //===----------------------------------------------------------------------===//
7510 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7512 let ExeDomain = SSEPackedSingle in {
7513 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7514 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7515 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7516 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7517 (i8 imm:$src3))))]>, VEX_4V;
7518 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7519 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7520 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7521 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7522 (i8 imm:$src3)))]>, VEX_4V;
7525 let Predicates = [HasAVX] in {
7526 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7527 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7528 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7529 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7530 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7531 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7532 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7533 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7534 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7535 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7537 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7538 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7539 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7540 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7541 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7542 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7543 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7544 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7545 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7546 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7547 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7548 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7549 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7550 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7551 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7552 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7553 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7554 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7557 //===----------------------------------------------------------------------===//
7558 // VZERO - Zero YMM registers
7560 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7561 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7562 // Zero All YMM registers
7563 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7564 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7566 // Zero Upper bits of YMM registers
7567 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7568 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7571 //===----------------------------------------------------------------------===//
7572 // Half precision conversion instructions
7573 //===----------------------------------------------------------------------===//
7574 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7575 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7576 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7577 [(set RC:$dst, (Int VR128:$src))]>,
7579 let neverHasSideEffects = 1, mayLoad = 1 in
7580 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7581 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7584 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7585 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7586 (ins RC:$src1, i32i8imm:$src2),
7587 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7588 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7590 let neverHasSideEffects = 1, mayStore = 1 in
7591 def mr : Ii8<0x1D, MRMDestMem, (outs),
7592 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7593 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7597 let Predicates = [HasAVX, HasF16C] in {
7598 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7599 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7600 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7601 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7604 //===----------------------------------------------------------------------===//
7605 // AVX2 Instructions
7606 //===----------------------------------------------------------------------===//
7608 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7609 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7610 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7611 X86MemOperand x86memop> {
7612 let isCommutable = 1 in
7613 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7614 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7615 !strconcat(OpcodeStr,
7616 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7617 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7619 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7620 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7621 !strconcat(OpcodeStr,
7622 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7625 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7629 let isCommutable = 0 in {
7630 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7631 VR128, memopv2i64, i128mem>;
7632 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7633 VR256, memopv4i64, i256mem>;
7636 //===----------------------------------------------------------------------===//
7637 // VPBROADCAST - Load from memory and broadcast to all elements of the
7638 // destination operand
7640 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7641 X86MemOperand x86memop, PatFrag ld_frag,
7642 Intrinsic Int128, Intrinsic Int256> {
7643 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7645 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7646 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7647 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7649 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7650 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7651 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7652 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7653 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7654 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7656 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7659 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7660 int_x86_avx2_pbroadcastb_128,
7661 int_x86_avx2_pbroadcastb_256>;
7662 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7663 int_x86_avx2_pbroadcastw_128,
7664 int_x86_avx2_pbroadcastw_256>;
7665 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7666 int_x86_avx2_pbroadcastd_128,
7667 int_x86_avx2_pbroadcastd_256>;
7668 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7669 int_x86_avx2_pbroadcastq_128,
7670 int_x86_avx2_pbroadcastq_256>;
7672 let Predicates = [HasAVX2] in {
7673 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7674 (VPBROADCASTBrm addr:$src)>;
7675 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7676 (VPBROADCASTBYrm addr:$src)>;
7677 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7678 (VPBROADCASTWrm addr:$src)>;
7679 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7680 (VPBROADCASTWYrm addr:$src)>;
7681 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7682 (VPBROADCASTDrm addr:$src)>;
7683 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7684 (VPBROADCASTDYrm addr:$src)>;
7685 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7686 (VPBROADCASTQrm addr:$src)>;
7687 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7688 (VPBROADCASTQYrm addr:$src)>;
7690 // Provide fallback in case the load node that is used in the patterns above
7691 // is used by additional users, which prevents the pattern selection.
7692 let AddedComplexity = 20 in {
7693 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7695 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7696 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7698 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7699 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7701 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7703 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7705 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7706 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7708 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7709 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7711 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7715 // AVX1 broadcast patterns
7716 let Predicates = [HasAVX] in {
7717 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7718 (VBROADCASTSSYrm addr:$src)>;
7719 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7720 (VBROADCASTSDrm addr:$src)>;
7721 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7722 (VBROADCASTSSYrm addr:$src)>;
7723 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7724 (VBROADCASTSDrm addr:$src)>;
7725 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7726 (VBROADCASTSSrm addr:$src)>;
7727 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7728 (VBROADCASTSSrm addr:$src)>;
7730 // Provide fallback in case the load node that is used in the patterns above
7731 // is used by additional users, which prevents the pattern selection.
7732 let AddedComplexity = 20 in {
7733 // 128bit broadcasts:
7734 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7736 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7737 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7738 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7740 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7743 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7745 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7746 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7748 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7751 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7754 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7756 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7757 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7758 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7760 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7763 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7765 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7766 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7768 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7771 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7776 //===----------------------------------------------------------------------===//
7777 // VPERM - Permute instructions
7780 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7782 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7783 (ins VR256:$src1, VR256:$src2),
7784 !strconcat(OpcodeStr,
7785 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7787 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7788 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7789 (ins VR256:$src1, i256mem:$src2),
7790 !strconcat(OpcodeStr,
7791 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7793 (OpVT (X86VPermv VR256:$src1,
7794 (bitconvert (mem_frag addr:$src2)))))]>,
7798 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7799 let ExeDomain = SSEPackedSingle in
7800 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7802 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7804 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7805 (ins VR256:$src1, i8imm:$src2),
7806 !strconcat(OpcodeStr,
7807 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7809 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7810 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7811 (ins i256mem:$src1, i8imm:$src2),
7812 !strconcat(OpcodeStr,
7813 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7815 (OpVT (X86VPermi (mem_frag addr:$src1),
7816 (i8 imm:$src2))))]>, VEX;
7819 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7820 let ExeDomain = SSEPackedDouble in
7821 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7823 //===----------------------------------------------------------------------===//
7824 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7826 let AddedComplexity = 1 in {
7827 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7828 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7829 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7830 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7831 (i8 imm:$src3))))]>, VEX_4V;
7832 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7833 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7834 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7835 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7836 (i8 imm:$src3)))]>, VEX_4V;
7839 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7840 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7841 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7842 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7843 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7844 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7845 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7847 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7849 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7850 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7851 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7852 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7853 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7855 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7859 //===----------------------------------------------------------------------===//
7860 // VINSERTI128 - Insert packed integer values
7862 let neverHasSideEffects = 1 in {
7863 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7864 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7865 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7868 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7869 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7870 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7874 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7875 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7877 (VINSERTI128rr VR256:$src1, VR128:$src2,
7878 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7879 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7881 (VINSERTI128rr VR256:$src1, VR128:$src2,
7882 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7883 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7885 (VINSERTI128rr VR256:$src1, VR128:$src2,
7886 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7887 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7889 (VINSERTI128rr VR256:$src1, VR128:$src2,
7890 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7893 //===----------------------------------------------------------------------===//
7894 // VEXTRACTI128 - Extract packed integer values
7896 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7897 (ins VR256:$src1, i8imm:$src2),
7898 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7900 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7902 let neverHasSideEffects = 1, mayStore = 1 in
7903 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7904 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7905 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7907 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7908 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7909 (v2i64 (VEXTRACTI128rr
7910 (v4i64 VR256:$src1),
7911 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7912 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7913 (v4i32 (VEXTRACTI128rr
7914 (v8i32 VR256:$src1),
7915 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7916 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7917 (v8i16 (VEXTRACTI128rr
7918 (v16i16 VR256:$src1),
7919 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7920 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7921 (v16i8 (VEXTRACTI128rr
7922 (v32i8 VR256:$src1),
7923 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7926 //===----------------------------------------------------------------------===//
7927 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7929 multiclass avx2_pmovmask<string OpcodeStr,
7930 Intrinsic IntLd128, Intrinsic IntLd256,
7931 Intrinsic IntSt128, Intrinsic IntSt256> {
7932 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7933 (ins VR128:$src1, i128mem:$src2),
7934 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7935 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7936 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7937 (ins VR256:$src1, i256mem:$src2),
7938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7939 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7940 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7941 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7942 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7943 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7944 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7945 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7947 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7950 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7951 int_x86_avx2_maskload_d,
7952 int_x86_avx2_maskload_d_256,
7953 int_x86_avx2_maskstore_d,
7954 int_x86_avx2_maskstore_d_256>;
7955 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7956 int_x86_avx2_maskload_q,
7957 int_x86_avx2_maskload_q_256,
7958 int_x86_avx2_maskstore_q,
7959 int_x86_avx2_maskstore_q_256>, VEX_W;
7962 //===----------------------------------------------------------------------===//
7963 // Variable Bit Shifts
7965 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7966 ValueType vt128, ValueType vt256> {
7967 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7968 (ins VR128:$src1, VR128:$src2),
7969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7971 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7973 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7974 (ins VR128:$src1, i128mem:$src2),
7975 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7977 (vt128 (OpNode VR128:$src1,
7978 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7980 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7981 (ins VR256:$src1, VR256:$src2),
7982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7984 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7986 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7987 (ins VR256:$src1, i256mem:$src2),
7988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7990 (vt256 (OpNode VR256:$src1,
7991 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7995 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7996 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7997 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7998 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7999 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;