1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86pextrb : SDNode<"X86ISD::PEXTRB",
38 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
39 def X86pextrw : SDNode<"X86ISD::PEXTRW",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pinsrb : SDNode<"X86ISD::PINSRB",
42 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
43 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
44 def X86pinsrw : SDNode<"X86ISD::PINSRW",
45 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
46 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
47 def X86insrtps : SDNode<"X86ISD::INSERTPS",
48 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
49 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
50 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
51 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
52 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
53 [SDNPHasChain, SDNPMayLoad]>;
54 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
55 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
57 //===----------------------------------------------------------------------===//
58 // SSE Complex Patterns
59 //===----------------------------------------------------------------------===//
61 // These are 'extloads' from a scalar to the low element of a vector, zeroing
62 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
64 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
65 [SDNPHasChain, SDNPMayLoad]>;
66 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
67 [SDNPHasChain, SDNPMayLoad]>;
69 def ssmem : Operand<v4f32> {
70 let PrintMethod = "printf32mem";
71 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
73 def sdmem : Operand<v2f64> {
74 let PrintMethod = "printf64mem";
75 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
78 //===----------------------------------------------------------------------===//
79 // SSE pattern fragments
80 //===----------------------------------------------------------------------===//
82 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
83 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
84 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
85 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
87 // Like 'store', but always requires vector alignment.
88 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
89 (st node:$val, node:$ptr), [{
90 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
91 return !ST->isTruncatingStore() &&
92 ST->getAddressingMode() == ISD::UNINDEXED &&
93 ST->getAlignment() >= 16;
97 // Like 'load', but always requires vector alignment.
98 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
99 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
100 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
101 LD->getAddressingMode() == ISD::UNINDEXED &&
102 LD->getAlignment() >= 16;
106 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
107 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
108 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
109 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
110 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
111 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
113 // Like 'load', but uses special alignment checks suitable for use in
114 // memory operands in most SSE instructions, which are required to
115 // be naturally aligned on some targets but not on others.
116 // FIXME: Actually implement support for targets that don't require the
117 // alignment. This probably wants a subtarget predicate.
118 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
119 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
120 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
121 LD->getAddressingMode() == ISD::UNINDEXED &&
122 LD->getAlignment() >= 16;
126 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
127 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
128 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
129 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
130 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
131 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
132 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 // FIXME: 8 byte alignment for mmx reads is not required
137 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
139 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
140 LD->getAddressingMode() == ISD::UNINDEXED &&
141 LD->getAlignment() >= 8;
145 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
146 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
147 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
148 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
150 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
151 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
152 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
153 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
154 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
155 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
157 def fp32imm0 : PatLeaf<(f32 fpimm), [{
158 return N->isExactlyValue(+0.0);
161 def PSxLDQ_imm : SDNodeXForm<imm, [{
162 // Transformation function: imm >> 3
163 return getI32Imm(N->getValue() >> 3);
166 def SSE_CC_imm : SDNodeXForm<cond, [{
169 default: Val = 0; assert(0 && "Unexpected CondCode"); break;
170 case ISD::SETOEQ: Val = 0; break;
171 case ISD::SETOLT: Val = 1; break;
172 case ISD::SETOLE: Val = 2; break;
173 case ISD::SETUO: Val = 3; break;
174 case ISD::SETONE: Val = 4; break;
175 case ISD::SETOGE: Val = 5; break;
176 case ISD::SETOGT: Val = 6; break;
177 case ISD::SETO: Val = 7; break;
179 return getI8Imm(Val);
182 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
184 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
185 return getI8Imm(X86::getShuffleSHUFImmediate(N));
188 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
190 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
191 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
194 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
196 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
197 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
200 def SSE_splat_mask : PatLeaf<(build_vector), [{
201 return X86::isSplatMask(N);
202 }], SHUFFLE_get_shuf_imm>;
204 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
205 return X86::isSplatLoMask(N);
208 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isMOVHLPSMask(N);
212 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isMOVHLPS_v_undef_Mask(N);
216 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isMOVHPMask(N);
220 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isMOVLPMask(N);
224 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isMOVLMask(N);
228 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isMOVSHDUPMask(N);
232 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isMOVSLDUPMask(N);
236 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isUNPCKLMask(N);
240 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isUNPCKHMask(N);
244 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
245 return X86::isUNPCKL_v_undef_Mask(N);
248 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
249 return X86::isUNPCKH_v_undef_Mask(N);
252 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
253 return X86::isPSHUFDMask(N);
254 }], SHUFFLE_get_shuf_imm>;
256 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
257 return X86::isPSHUFHWMask(N);
258 }], SHUFFLE_get_pshufhw_imm>;
260 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
261 return X86::isPSHUFLWMask(N);
262 }], SHUFFLE_get_pshuflw_imm>;
264 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
265 return X86::isPSHUFDMask(N);
266 }], SHUFFLE_get_shuf_imm>;
268 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
269 return X86::isSHUFPMask(N);
270 }], SHUFFLE_get_shuf_imm>;
272 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
273 return X86::isSHUFPMask(N);
274 }], SHUFFLE_get_shuf_imm>;
277 //===----------------------------------------------------------------------===//
278 // SSE scalar FP Instructions
279 //===----------------------------------------------------------------------===//
281 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
282 // scheduler into a branch sequence.
283 // These are expanded by the scheduler.
284 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
285 def CMOV_FR32 : I<0, Pseudo,
286 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
287 "#CMOV_FR32 PSEUDO!",
288 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
290 def CMOV_FR64 : I<0, Pseudo,
291 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
292 "#CMOV_FR64 PSEUDO!",
293 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
295 def CMOV_V4F32 : I<0, Pseudo,
296 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
297 "#CMOV_V4F32 PSEUDO!",
299 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
301 def CMOV_V2F64 : I<0, Pseudo,
302 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
303 "#CMOV_V2F64 PSEUDO!",
305 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
307 def CMOV_V2I64 : I<0, Pseudo,
308 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
309 "#CMOV_V2I64 PSEUDO!",
311 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
320 let neverHasSideEffects = 1 in
321 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
322 "movss\t{$src, $dst|$dst, $src}", []>;
323 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
324 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
325 "movss\t{$src, $dst|$dst, $src}",
326 [(set FR32:$dst, (loadf32 addr:$src))]>;
327 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
328 "movss\t{$src, $dst|$dst, $src}",
329 [(store FR32:$src, addr:$dst)]>;
331 // Conversion instructions
332 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
333 "cvttss2si\t{$src, $dst|$dst, $src}",
334 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
335 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
336 "cvttss2si\t{$src, $dst|$dst, $src}",
337 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
338 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
339 "cvtsi2ss\t{$src, $dst|$dst, $src}",
340 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
341 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
342 "cvtsi2ss\t{$src, $dst|$dst, $src}",
343 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
345 // Match intrinsics which expect XMM operand(s).
346 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
347 "cvtss2si\t{$src, $dst|$dst, $src}",
348 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
349 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
350 "cvtss2si\t{$src, $dst|$dst, $src}",
351 [(set GR32:$dst, (int_x86_sse_cvtss2si
352 (load addr:$src)))]>;
354 // Match intrinisics which expect MM and XMM operand(s).
355 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
356 "cvtps2pi\t{$src, $dst|$dst, $src}",
357 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
358 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
359 "cvtps2pi\t{$src, $dst|$dst, $src}",
360 [(set VR64:$dst, (int_x86_sse_cvtps2pi
361 (load addr:$src)))]>;
362 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
363 "cvttps2pi\t{$src, $dst|$dst, $src}",
364 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
365 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
366 "cvttps2pi\t{$src, $dst|$dst, $src}",
367 [(set VR64:$dst, (int_x86_sse_cvttps2pi
368 (load addr:$src)))]>;
369 let Constraints = "$src1 = $dst" in {
370 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
371 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
372 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
375 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
376 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
377 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
378 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
379 (load addr:$src2)))]>;
382 // Aliases for intrinsics
383 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
384 "cvttss2si\t{$src, $dst|$dst, $src}",
386 (int_x86_sse_cvttss2si VR128:$src))]>;
387 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
388 "cvttss2si\t{$src, $dst|$dst, $src}",
390 (int_x86_sse_cvttss2si(load addr:$src)))]>;
392 let Constraints = "$src1 = $dst" in {
393 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
394 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
395 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
396 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
398 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
399 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
400 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
401 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
402 (loadi32 addr:$src2)))]>;
405 // Comparison instructions
406 let Constraints = "$src1 = $dst" in {
407 let neverHasSideEffects = 1 in
408 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
409 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
410 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
411 let neverHasSideEffects = 1, mayLoad = 1 in
412 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
413 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
414 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
417 let Defs = [EFLAGS] in {
418 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
419 "ucomiss\t{$src2, $src1|$src1, $src2}",
420 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
421 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
422 "ucomiss\t{$src2, $src1|$src1, $src2}",
423 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
427 // Aliases to match intrinsics which expect XMM operand(s).
428 let Constraints = "$src1 = $dst" in {
429 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
430 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
431 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
432 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
433 VR128:$src, imm:$cc))]>;
434 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
435 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
436 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
437 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
438 (load addr:$src), imm:$cc))]>;
441 let Defs = [EFLAGS] in {
442 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
443 (ins VR128:$src1, VR128:$src2),
444 "ucomiss\t{$src2, $src1|$src1, $src2}",
445 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
447 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
448 (ins VR128:$src1, f128mem:$src2),
449 "ucomiss\t{$src2, $src1|$src1, $src2}",
450 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
453 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
454 (ins VR128:$src1, VR128:$src2),
455 "comiss\t{$src2, $src1|$src1, $src2}",
456 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
458 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
459 (ins VR128:$src1, f128mem:$src2),
460 "comiss\t{$src2, $src1|$src1, $src2}",
461 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
465 // Aliases of packed SSE1 instructions for scalar use. These all have names that
468 // Alias instructions that map fld0 to pxor for sse.
469 let isReMaterializable = 1 in
470 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
471 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
472 Requires<[HasSSE1]>, TB, OpSize;
474 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
476 let neverHasSideEffects = 1 in
477 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
478 "movaps\t{$src, $dst|$dst, $src}", []>;
480 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
482 let isSimpleLoad = 1 in
483 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
484 "movaps\t{$src, $dst|$dst, $src}",
485 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
487 // Alias bitwise logical operations using SSE logical ops on packed FP values.
488 let Constraints = "$src1 = $dst" in {
489 let isCommutable = 1 in {
490 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
491 "andps\t{$src2, $dst|$dst, $src2}",
492 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
493 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
494 "orps\t{$src2, $dst|$dst, $src2}",
495 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
496 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
497 "xorps\t{$src2, $dst|$dst, $src2}",
498 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
501 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
502 "andps\t{$src2, $dst|$dst, $src2}",
503 [(set FR32:$dst, (X86fand FR32:$src1,
504 (memopfsf32 addr:$src2)))]>;
505 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
506 "orps\t{$src2, $dst|$dst, $src2}",
507 [(set FR32:$dst, (X86for FR32:$src1,
508 (memopfsf32 addr:$src2)))]>;
509 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
510 "xorps\t{$src2, $dst|$dst, $src2}",
511 [(set FR32:$dst, (X86fxor FR32:$src1,
512 (memopfsf32 addr:$src2)))]>;
513 let neverHasSideEffects = 1 in {
514 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
515 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
516 "andnps\t{$src2, $dst|$dst, $src2}", []>;
519 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
520 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
521 "andnps\t{$src2, $dst|$dst, $src2}", []>;
525 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
527 /// In addition, we also have a special variant of the scalar form here to
528 /// represent the associated intrinsic operation. This form is unlike the
529 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
530 /// and leaves the top elements undefined.
532 /// These three forms can each be reg+reg or reg+mem, so there are a total of
533 /// six "instructions".
535 let Constraints = "$src1 = $dst" in {
536 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
537 SDNode OpNode, Intrinsic F32Int,
538 bit Commutable = 0> {
539 // Scalar operation, reg+reg.
540 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
541 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
542 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
543 let isCommutable = Commutable;
546 // Scalar operation, reg+mem.
547 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
548 (ins FR32:$src1, f32mem:$src2),
549 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
550 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
552 // Vector operation, reg+reg.
553 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
554 (ins VR128:$src1, VR128:$src2),
555 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
556 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
557 let isCommutable = Commutable;
560 // Vector operation, reg+mem.
561 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
562 (ins VR128:$src1, f128mem:$src2),
563 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
564 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
566 // Intrinsic operation, reg+reg.
567 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
568 (ins VR128:$src1, VR128:$src2),
569 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
570 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
571 let isCommutable = Commutable;
574 // Intrinsic operation, reg+mem.
575 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
576 (ins VR128:$src1, ssmem:$src2),
577 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
578 [(set VR128:$dst, (F32Int VR128:$src1,
579 sse_load_f32:$src2))]>;
583 // Arithmetic instructions
584 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
585 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
586 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
587 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
589 /// sse1_fp_binop_rm - Other SSE1 binops
591 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
592 /// instructions for a full-vector intrinsic form. Operations that map
593 /// onto C operators don't use this form since they just use the plain
594 /// vector form instead of having a separate vector intrinsic form.
596 /// This provides a total of eight "instructions".
598 let Constraints = "$src1 = $dst" in {
599 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
603 bit Commutable = 0> {
605 // Scalar operation, reg+reg.
606 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
607 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
608 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
609 let isCommutable = Commutable;
612 // Scalar operation, reg+mem.
613 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
614 (ins FR32:$src1, f32mem:$src2),
615 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
616 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
618 // Vector operation, reg+reg.
619 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
620 (ins VR128:$src1, VR128:$src2),
621 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
622 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
623 let isCommutable = Commutable;
626 // Vector operation, reg+mem.
627 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
628 (ins VR128:$src1, f128mem:$src2),
629 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
630 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
632 // Intrinsic operation, reg+reg.
633 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
634 (ins VR128:$src1, VR128:$src2),
635 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
636 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
637 let isCommutable = Commutable;
640 // Intrinsic operation, reg+mem.
641 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
642 (ins VR128:$src1, ssmem:$src2),
643 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
644 [(set VR128:$dst, (F32Int VR128:$src1,
645 sse_load_f32:$src2))]>;
647 // Vector intrinsic operation, reg+reg.
648 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
649 (ins VR128:$src1, VR128:$src2),
650 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
651 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
652 let isCommutable = Commutable;
655 // Vector intrinsic operation, reg+mem.
656 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
657 (ins VR128:$src1, f128mem:$src2),
658 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
659 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
663 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
664 int_x86_sse_max_ss, int_x86_sse_max_ps>;
665 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
666 int_x86_sse_min_ss, int_x86_sse_min_ps>;
668 //===----------------------------------------------------------------------===//
669 // SSE packed FP Instructions
672 let neverHasSideEffects = 1 in
673 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
674 "movaps\t{$src, $dst|$dst, $src}", []>;
675 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
676 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
677 "movaps\t{$src, $dst|$dst, $src}",
678 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
680 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
681 "movaps\t{$src, $dst|$dst, $src}",
682 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
684 let neverHasSideEffects = 1 in
685 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
686 "movups\t{$src, $dst|$dst, $src}", []>;
687 let isSimpleLoad = 1 in
688 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
689 "movups\t{$src, $dst|$dst, $src}",
690 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
691 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
692 "movups\t{$src, $dst|$dst, $src}",
693 [(store (v4f32 VR128:$src), addr:$dst)]>;
695 // Intrinsic forms of MOVUPS load and store
696 let isSimpleLoad = 1 in
697 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
698 "movups\t{$src, $dst|$dst, $src}",
699 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
700 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
701 "movups\t{$src, $dst|$dst, $src}",
702 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
704 let Constraints = "$src1 = $dst" in {
705 let AddedComplexity = 20 in {
706 def MOVLPSrm : PSI<0x12, MRMSrcMem,
707 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
708 "movlps\t{$src2, $dst|$dst, $src2}",
710 (v4f32 (vector_shuffle VR128:$src1,
711 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
712 MOVLP_shuffle_mask)))]>;
713 def MOVHPSrm : PSI<0x16, MRMSrcMem,
714 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
715 "movhps\t{$src2, $dst|$dst, $src2}",
717 (v4f32 (vector_shuffle VR128:$src1,
718 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
719 MOVHP_shuffle_mask)))]>;
721 } // Constraints = "$src1 = $dst"
724 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
725 "movlps\t{$src, $dst|$dst, $src}",
726 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
727 (iPTR 0))), addr:$dst)]>;
729 // v2f64 extract element 1 is always custom lowered to unpack high to low
730 // and extract element 0 so the non-store version isn't too horrible.
731 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movhps\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract
734 (v2f64 (vector_shuffle
735 (bc_v2f64 (v4f32 VR128:$src)), (undef),
736 UNPCKH_shuffle_mask)), (iPTR 0))),
739 let Constraints = "$src1 = $dst" in {
740 let AddedComplexity = 15 in {
741 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
742 "movlhps\t{$src2, $dst|$dst, $src2}",
744 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
745 MOVHP_shuffle_mask)))]>;
747 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
748 "movhlps\t{$src2, $dst|$dst, $src2}",
750 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
751 MOVHLPS_shuffle_mask)))]>;
753 } // Constraints = "$src1 = $dst"
759 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
761 /// In addition, we also have a special variant of the scalar form here to
762 /// represent the associated intrinsic operation. This form is unlike the
763 /// plain scalar form, in that it takes an entire vector (instead of a
764 /// scalar) and leaves the top elements undefined.
766 /// And, we have a special variant form for a full-vector intrinsic form.
768 /// These four forms can each have a reg or a mem operand, so there are a
769 /// total of eight "instructions".
771 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
775 bit Commutable = 0> {
776 // Scalar operation, reg.
777 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
778 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
779 [(set FR32:$dst, (OpNode FR32:$src))]> {
780 let isCommutable = Commutable;
783 // Scalar operation, mem.
784 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
785 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
786 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
788 // Vector operation, reg.
789 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
790 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
791 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
792 let isCommutable = Commutable;
795 // Vector operation, mem.
796 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
797 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
798 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
800 // Intrinsic operation, reg.
801 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
802 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (F32Int VR128:$src))]> {
804 let isCommutable = Commutable;
807 // Intrinsic operation, mem.
808 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
809 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
810 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
812 // Vector intrinsic operation, reg
813 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
816 let isCommutable = Commutable;
819 // Vector intrinsic operation, mem
820 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
821 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
822 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
826 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
827 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
829 // Reciprocal approximations. Note that these typically require refinement
830 // in order to obtain suitable precision.
831 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
832 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
833 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
834 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
837 let Constraints = "$src1 = $dst" in {
838 let isCommutable = 1 in {
839 def ANDPSrr : PSI<0x54, MRMSrcReg,
840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
841 "andps\t{$src2, $dst|$dst, $src2}",
842 [(set VR128:$dst, (v2i64
843 (and VR128:$src1, VR128:$src2)))]>;
844 def ORPSrr : PSI<0x56, MRMSrcReg,
845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
846 "orps\t{$src2, $dst|$dst, $src2}",
847 [(set VR128:$dst, (v2i64
848 (or VR128:$src1, VR128:$src2)))]>;
849 def XORPSrr : PSI<0x57, MRMSrcReg,
850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
851 "xorps\t{$src2, $dst|$dst, $src2}",
852 [(set VR128:$dst, (v2i64
853 (xor VR128:$src1, VR128:$src2)))]>;
856 def ANDPSrm : PSI<0x54, MRMSrcMem,
857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
858 "andps\t{$src2, $dst|$dst, $src2}",
859 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
860 (memopv2i64 addr:$src2)))]>;
861 def ORPSrm : PSI<0x56, MRMSrcMem,
862 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
863 "orps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
865 (memopv2i64 addr:$src2)))]>;
866 def XORPSrm : PSI<0x57, MRMSrcMem,
867 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
868 "xorps\t{$src2, $dst|$dst, $src2}",
869 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
870 (memopv2i64 addr:$src2)))]>;
871 def ANDNPSrr : PSI<0x55, MRMSrcReg,
872 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
873 "andnps\t{$src2, $dst|$dst, $src2}",
875 (v2i64 (and (xor VR128:$src1,
876 (bc_v2i64 (v4i32 immAllOnesV))),
878 def ANDNPSrm : PSI<0x55, MRMSrcMem,
879 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
880 "andnps\t{$src2, $dst|$dst, $src2}",
882 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
883 (bc_v2i64 (v4i32 immAllOnesV))),
884 (memopv2i64 addr:$src2))))]>;
887 let Constraints = "$src1 = $dst" in {
888 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
889 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
890 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
892 VR128:$src, imm:$cc))]>;
893 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
894 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
895 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
896 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
897 (memop addr:$src), imm:$cc))]>;
899 def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
900 (CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
901 def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
902 (CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
904 // Shuffle and unpack instructions
905 let Constraints = "$src1 = $dst" in {
906 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
907 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
908 (outs VR128:$dst), (ins VR128:$src1,
909 VR128:$src2, i32i8imm:$src3),
910 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
912 (v4f32 (vector_shuffle
913 VR128:$src1, VR128:$src2,
914 SHUFP_shuffle_mask:$src3)))]>;
915 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
916 (outs VR128:$dst), (ins VR128:$src1,
917 f128mem:$src2, i32i8imm:$src3),
918 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
920 (v4f32 (vector_shuffle
921 VR128:$src1, (memopv4f32 addr:$src2),
922 SHUFP_shuffle_mask:$src3)))]>;
924 let AddedComplexity = 10 in {
925 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
926 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
927 "unpckhps\t{$src2, $dst|$dst, $src2}",
929 (v4f32 (vector_shuffle
930 VR128:$src1, VR128:$src2,
931 UNPCKH_shuffle_mask)))]>;
932 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
934 "unpckhps\t{$src2, $dst|$dst, $src2}",
936 (v4f32 (vector_shuffle
937 VR128:$src1, (memopv4f32 addr:$src2),
938 UNPCKH_shuffle_mask)))]>;
940 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
942 "unpcklps\t{$src2, $dst|$dst, $src2}",
944 (v4f32 (vector_shuffle
945 VR128:$src1, VR128:$src2,
946 UNPCKL_shuffle_mask)))]>;
947 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
948 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
949 "unpcklps\t{$src2, $dst|$dst, $src2}",
951 (v4f32 (vector_shuffle
952 VR128:$src1, (memopv4f32 addr:$src2),
953 UNPCKL_shuffle_mask)))]>;
955 } // Constraints = "$src1 = $dst"
958 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
959 "movmskps\t{$src, $dst|$dst, $src}",
960 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
961 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
962 "movmskpd\t{$src, $dst|$dst, $src}",
963 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
965 // Prefetch intrinsic.
966 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
967 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
968 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
969 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
970 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
971 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
972 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
973 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
975 // Non-temporal stores
976 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
977 "movntps\t{$src, $dst|$dst, $src}",
978 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
980 // Load, store, and memory fence
981 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
984 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
985 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
986 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
987 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
989 // Alias instructions that map zero vector to pxor / xorp* for sse.
990 let isReMaterializable = 1 in
991 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
993 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
995 let Predicates = [HasSSE1] in {
996 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
997 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
998 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
999 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1003 // FR32 to 128-bit vector conversion.
1004 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1005 "movss\t{$src, $dst|$dst, $src}",
1007 (v4f32 (scalar_to_vector FR32:$src)))]>;
1008 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1009 "movss\t{$src, $dst|$dst, $src}",
1011 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1013 // FIXME: may not be able to eliminate this movss with coalescing the src and
1014 // dest register classes are different. We really want to write this pattern
1016 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1017 // (f32 FR32:$src)>;
1018 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1019 "movss\t{$src, $dst|$dst, $src}",
1020 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1022 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1023 "movss\t{$src, $dst|$dst, $src}",
1024 [(store (f32 (vector_extract (v4f32 VR128:$src),
1025 (iPTR 0))), addr:$dst)]>;
1028 // Move to lower bits of a VR128, leaving upper bits alone.
1029 // Three operand (but two address) aliases.
1030 let Constraints = "$src1 = $dst" in {
1031 let neverHasSideEffects = 1 in
1032 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1033 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1034 "movss\t{$src2, $dst|$dst, $src2}", []>;
1036 let AddedComplexity = 15 in
1037 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1038 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1039 "movss\t{$src2, $dst|$dst, $src2}",
1041 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1042 MOVL_shuffle_mask)))]>;
1045 // Move to lower bits of a VR128 and zeroing upper bits.
1046 // Loading from memory automatically zeroing upper bits.
1047 let AddedComplexity = 20 in
1048 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1049 "movss\t{$src, $dst|$dst, $src}",
1050 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1051 (loadf32 addr:$src))))))]>;
1053 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1054 (MOVZSS2PSrm addr:$src)>;
1056 //===----------------------------------------------------------------------===//
1057 // SSE2 Instructions
1058 //===----------------------------------------------------------------------===//
1060 // Move Instructions
1061 let neverHasSideEffects = 1 in
1062 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1063 "movsd\t{$src, $dst|$dst, $src}", []>;
1064 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1065 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1066 "movsd\t{$src, $dst|$dst, $src}",
1067 [(set FR64:$dst, (loadf64 addr:$src))]>;
1068 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1069 "movsd\t{$src, $dst|$dst, $src}",
1070 [(store FR64:$src, addr:$dst)]>;
1072 // Conversion instructions
1073 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1074 "cvttsd2si\t{$src, $dst|$dst, $src}",
1075 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1076 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1077 "cvttsd2si\t{$src, $dst|$dst, $src}",
1078 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1079 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1080 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1081 [(set FR32:$dst, (fround FR64:$src))]>;
1082 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1083 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1084 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1085 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1086 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1087 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1088 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1089 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1090 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1092 // SSE2 instructions with XS prefix
1093 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1094 "cvtss2sd\t{$src, $dst|$dst, $src}",
1095 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1096 Requires<[HasSSE2]>;
1097 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1098 "cvtss2sd\t{$src, $dst|$dst, $src}",
1099 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1100 Requires<[HasSSE2]>;
1102 // Match intrinsics which expect XMM operand(s).
1103 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1104 "cvtsd2si\t{$src, $dst|$dst, $src}",
1105 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1106 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1107 "cvtsd2si\t{$src, $dst|$dst, $src}",
1108 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1109 (load addr:$src)))]>;
1111 // Match intrinisics which expect MM and XMM operand(s).
1112 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1113 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1114 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1115 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1116 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1117 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1118 (memop addr:$src)))]>;
1119 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1120 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1121 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1122 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1123 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1124 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1125 (memop addr:$src)))]>;
1126 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1127 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1128 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1129 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1130 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1132 (load addr:$src)))]>;
1134 // Aliases for intrinsics
1135 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1136 "cvttsd2si\t{$src, $dst|$dst, $src}",
1138 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1139 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1140 "cvttsd2si\t{$src, $dst|$dst, $src}",
1141 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1142 (load addr:$src)))]>;
1144 // Comparison instructions
1145 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1146 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1147 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1148 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1150 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1151 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1152 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1155 let Defs = [EFLAGS] in {
1156 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1157 "ucomisd\t{$src2, $src1|$src1, $src2}",
1158 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1159 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1160 "ucomisd\t{$src2, $src1|$src1, $src2}",
1161 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1162 (implicit EFLAGS)]>;
1165 // Aliases to match intrinsics which expect XMM operand(s).
1166 let Constraints = "$src1 = $dst" in {
1167 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1168 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1169 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1170 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1171 VR128:$src, imm:$cc))]>;
1172 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1173 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1174 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1175 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1176 (load addr:$src), imm:$cc))]>;
1179 let Defs = [EFLAGS] in {
1180 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1181 "ucomisd\t{$src2, $src1|$src1, $src2}",
1182 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1183 (implicit EFLAGS)]>;
1184 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1185 "ucomisd\t{$src2, $src1|$src1, $src2}",
1186 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1187 (implicit EFLAGS)]>;
1189 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1190 "comisd\t{$src2, $src1|$src1, $src2}",
1191 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1192 (implicit EFLAGS)]>;
1193 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1194 "comisd\t{$src2, $src1|$src1, $src2}",
1195 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1196 (implicit EFLAGS)]>;
1199 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1202 // Alias instructions that map fld0 to pxor for sse.
1203 let isReMaterializable = 1 in
1204 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1205 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1206 Requires<[HasSSE2]>, TB, OpSize;
1208 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1210 let neverHasSideEffects = 1 in
1211 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1212 "movapd\t{$src, $dst|$dst, $src}", []>;
1214 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1216 let isSimpleLoad = 1 in
1217 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1218 "movapd\t{$src, $dst|$dst, $src}",
1219 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1221 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1222 let Constraints = "$src1 = $dst" in {
1223 let isCommutable = 1 in {
1224 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1225 (ins FR64:$src1, FR64:$src2),
1226 "andpd\t{$src2, $dst|$dst, $src2}",
1227 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1228 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1229 (ins FR64:$src1, FR64:$src2),
1230 "orpd\t{$src2, $dst|$dst, $src2}",
1231 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1232 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1233 (ins FR64:$src1, FR64:$src2),
1234 "xorpd\t{$src2, $dst|$dst, $src2}",
1235 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1238 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1239 (ins FR64:$src1, f128mem:$src2),
1240 "andpd\t{$src2, $dst|$dst, $src2}",
1241 [(set FR64:$dst, (X86fand FR64:$src1,
1242 (memopfsf64 addr:$src2)))]>;
1243 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1244 (ins FR64:$src1, f128mem:$src2),
1245 "orpd\t{$src2, $dst|$dst, $src2}",
1246 [(set FR64:$dst, (X86for FR64:$src1,
1247 (memopfsf64 addr:$src2)))]>;
1248 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1249 (ins FR64:$src1, f128mem:$src2),
1250 "xorpd\t{$src2, $dst|$dst, $src2}",
1251 [(set FR64:$dst, (X86fxor FR64:$src1,
1252 (memopfsf64 addr:$src2)))]>;
1254 let neverHasSideEffects = 1 in {
1255 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1256 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1257 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1259 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1260 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1261 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1265 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1267 /// In addition, we also have a special variant of the scalar form here to
1268 /// represent the associated intrinsic operation. This form is unlike the
1269 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1270 /// and leaves the top elements undefined.
1272 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1273 /// six "instructions".
1275 let Constraints = "$src1 = $dst" in {
1276 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1277 SDNode OpNode, Intrinsic F64Int,
1278 bit Commutable = 0> {
1279 // Scalar operation, reg+reg.
1280 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1281 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1282 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1283 let isCommutable = Commutable;
1286 // Scalar operation, reg+mem.
1287 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1288 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1289 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1291 // Vector operation, reg+reg.
1292 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1293 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1294 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1295 let isCommutable = Commutable;
1298 // Vector operation, reg+mem.
1299 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1300 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1301 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1303 // Intrinsic operation, reg+reg.
1304 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1305 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1306 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1307 let isCommutable = Commutable;
1310 // Intrinsic operation, reg+mem.
1311 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1312 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1313 [(set VR128:$dst, (F64Int VR128:$src1,
1314 sse_load_f64:$src2))]>;
1318 // Arithmetic instructions
1319 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1320 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1321 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1322 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1324 /// sse2_fp_binop_rm - Other SSE2 binops
1326 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1327 /// instructions for a full-vector intrinsic form. Operations that map
1328 /// onto C operators don't use this form since they just use the plain
1329 /// vector form instead of having a separate vector intrinsic form.
1331 /// This provides a total of eight "instructions".
1333 let Constraints = "$src1 = $dst" in {
1334 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1338 bit Commutable = 0> {
1340 // Scalar operation, reg+reg.
1341 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1342 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1343 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1344 let isCommutable = Commutable;
1347 // Scalar operation, reg+mem.
1348 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1349 (ins FR64:$src1, f64mem:$src2),
1350 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1351 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1353 // Vector operation, reg+reg.
1354 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1357 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1358 let isCommutable = Commutable;
1361 // Vector operation, reg+mem.
1362 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1363 (ins VR128:$src1, f128mem:$src2),
1364 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1365 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1367 // Intrinsic operation, reg+reg.
1368 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1369 (ins VR128:$src1, VR128:$src2),
1370 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1371 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1372 let isCommutable = Commutable;
1375 // Intrinsic operation, reg+mem.
1376 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1377 (ins VR128:$src1, sdmem:$src2),
1378 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1379 [(set VR128:$dst, (F64Int VR128:$src1,
1380 sse_load_f64:$src2))]>;
1382 // Vector intrinsic operation, reg+reg.
1383 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1384 (ins VR128:$src1, VR128:$src2),
1385 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1386 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1387 let isCommutable = Commutable;
1390 // Vector intrinsic operation, reg+mem.
1391 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1392 (ins VR128:$src1, f128mem:$src2),
1393 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1394 [(set VR128:$dst, (V2F64Int VR128:$src1,
1395 (memopv2f64 addr:$src2)))]>;
1399 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1400 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1401 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1402 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1404 //===----------------------------------------------------------------------===//
1405 // SSE packed FP Instructions
1407 // Move Instructions
1408 let neverHasSideEffects = 1 in
1409 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1410 "movapd\t{$src, $dst|$dst, $src}", []>;
1411 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1412 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1413 "movapd\t{$src, $dst|$dst, $src}",
1414 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1416 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1417 "movapd\t{$src, $dst|$dst, $src}",
1418 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1420 let neverHasSideEffects = 1 in
1421 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1422 "movupd\t{$src, $dst|$dst, $src}", []>;
1423 let isSimpleLoad = 1 in
1424 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1425 "movupd\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1427 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1428 "movupd\t{$src, $dst|$dst, $src}",
1429 [(store (v2f64 VR128:$src), addr:$dst)]>;
1431 // Intrinsic forms of MOVUPD load and store
1432 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1433 "movupd\t{$src, $dst|$dst, $src}",
1434 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1435 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1436 "movupd\t{$src, $dst|$dst, $src}",
1437 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1439 let Constraints = "$src1 = $dst" in {
1440 let AddedComplexity = 20 in {
1441 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1442 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1443 "movlpd\t{$src2, $dst|$dst, $src2}",
1445 (v2f64 (vector_shuffle VR128:$src1,
1446 (scalar_to_vector (loadf64 addr:$src2)),
1447 MOVLP_shuffle_mask)))]>;
1448 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1449 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1450 "movhpd\t{$src2, $dst|$dst, $src2}",
1452 (v2f64 (vector_shuffle VR128:$src1,
1453 (scalar_to_vector (loadf64 addr:$src2)),
1454 MOVHP_shuffle_mask)))]>;
1455 } // AddedComplexity
1456 } // Constraints = "$src1 = $dst"
1458 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1459 "movlpd\t{$src, $dst|$dst, $src}",
1460 [(store (f64 (vector_extract (v2f64 VR128:$src),
1461 (iPTR 0))), addr:$dst)]>;
1463 // v2f64 extract element 1 is always custom lowered to unpack high to low
1464 // and extract element 0 so the non-store version isn't too horrible.
1465 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1466 "movhpd\t{$src, $dst|$dst, $src}",
1467 [(store (f64 (vector_extract
1468 (v2f64 (vector_shuffle VR128:$src, (undef),
1469 UNPCKH_shuffle_mask)), (iPTR 0))),
1472 // SSE2 instructions without OpSize prefix
1473 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1474 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1475 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1476 TB, Requires<[HasSSE2]>;
1477 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1478 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1479 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1480 (bitconvert (memopv2i64 addr:$src))))]>,
1481 TB, Requires<[HasSSE2]>;
1483 // SSE2 instructions with XS prefix
1484 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1485 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1486 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1487 XS, Requires<[HasSSE2]>;
1488 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1489 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1490 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1491 (bitconvert (memopv2i64 addr:$src))))]>,
1492 XS, Requires<[HasSSE2]>;
1494 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1495 "cvtps2dq\t{$src, $dst|$dst, $src}",
1496 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1497 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1498 "cvtps2dq\t{$src, $dst|$dst, $src}",
1499 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1500 (memop addr:$src)))]>;
1501 // SSE2 packed instructions with XS prefix
1502 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1503 "cvttps2dq\t{$src, $dst|$dst, $src}",
1504 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1505 XS, Requires<[HasSSE2]>;
1506 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1507 "cvttps2dq\t{$src, $dst|$dst, $src}",
1508 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1509 (memop addr:$src)))]>,
1510 XS, Requires<[HasSSE2]>;
1512 // SSE2 packed instructions with XD prefix
1513 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1514 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1515 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1516 XD, Requires<[HasSSE2]>;
1517 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1518 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1519 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1520 (memop addr:$src)))]>,
1521 XD, Requires<[HasSSE2]>;
1523 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1524 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1525 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1526 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1527 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1528 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1529 (memop addr:$src)))]>;
1531 // SSE2 instructions without OpSize prefix
1532 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1533 "cvtps2pd\t{$src, $dst|$dst, $src}",
1534 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1535 TB, Requires<[HasSSE2]>;
1536 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1537 "cvtps2pd\t{$src, $dst|$dst, $src}",
1538 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1539 (load addr:$src)))]>,
1540 TB, Requires<[HasSSE2]>;
1542 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1543 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1544 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1545 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1546 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1547 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1548 (memop addr:$src)))]>;
1550 // Match intrinsics which expect XMM operand(s).
1551 // Aliases for intrinsics
1552 let Constraints = "$src1 = $dst" in {
1553 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1554 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1555 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1556 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1558 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1559 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1560 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1561 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1562 (loadi32 addr:$src2)))]>;
1563 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1564 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1565 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1566 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1568 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1569 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1570 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1571 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1572 (load addr:$src2)))]>;
1573 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1575 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1576 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1577 VR128:$src2))]>, XS,
1578 Requires<[HasSSE2]>;
1579 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1580 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1581 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1582 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1583 (load addr:$src2)))]>, XS,
1584 Requires<[HasSSE2]>;
1589 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1591 /// In addition, we also have a special variant of the scalar form here to
1592 /// represent the associated intrinsic operation. This form is unlike the
1593 /// plain scalar form, in that it takes an entire vector (instead of a
1594 /// scalar) and leaves the top elements undefined.
1596 /// And, we have a special variant form for a full-vector intrinsic form.
1598 /// These four forms can each have a reg or a mem operand, so there are a
1599 /// total of eight "instructions".
1601 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1605 bit Commutable = 0> {
1606 // Scalar operation, reg.
1607 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1608 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1609 [(set FR64:$dst, (OpNode FR64:$src))]> {
1610 let isCommutable = Commutable;
1613 // Scalar operation, mem.
1614 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1615 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1616 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1618 // Vector operation, reg.
1619 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1620 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1621 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1622 let isCommutable = Commutable;
1625 // Vector operation, mem.
1626 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1627 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1628 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1630 // Intrinsic operation, reg.
1631 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1633 [(set VR128:$dst, (F64Int VR128:$src))]> {
1634 let isCommutable = Commutable;
1637 // Intrinsic operation, mem.
1638 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1639 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1640 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1642 // Vector intrinsic operation, reg
1643 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1644 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1645 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1646 let isCommutable = Commutable;
1649 // Vector intrinsic operation, mem
1650 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1651 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1652 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1656 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1657 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1659 // There is no f64 version of the reciprocal approximation instructions.
1662 let Constraints = "$src1 = $dst" in {
1663 let isCommutable = 1 in {
1664 def ANDPDrr : PDI<0x54, MRMSrcReg,
1665 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1666 "andpd\t{$src2, $dst|$dst, $src2}",
1668 (and (bc_v2i64 (v2f64 VR128:$src1)),
1669 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1670 def ORPDrr : PDI<0x56, MRMSrcReg,
1671 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1672 "orpd\t{$src2, $dst|$dst, $src2}",
1674 (or (bc_v2i64 (v2f64 VR128:$src1)),
1675 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1676 def XORPDrr : PDI<0x57, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "xorpd\t{$src2, $dst|$dst, $src2}",
1680 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1681 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1684 def ANDPDrm : PDI<0x54, MRMSrcMem,
1685 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1686 "andpd\t{$src2, $dst|$dst, $src2}",
1688 (and (bc_v2i64 (v2f64 VR128:$src1)),
1689 (memopv2i64 addr:$src2)))]>;
1690 def ORPDrm : PDI<0x56, MRMSrcMem,
1691 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1692 "orpd\t{$src2, $dst|$dst, $src2}",
1694 (or (bc_v2i64 (v2f64 VR128:$src1)),
1695 (memopv2i64 addr:$src2)))]>;
1696 def XORPDrm : PDI<0x57, MRMSrcMem,
1697 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1698 "xorpd\t{$src2, $dst|$dst, $src2}",
1700 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1701 (memopv2i64 addr:$src2)))]>;
1702 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1703 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1704 "andnpd\t{$src2, $dst|$dst, $src2}",
1706 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1707 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1708 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1709 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1710 "andnpd\t{$src2, $dst|$dst, $src2}",
1712 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1713 (memopv2i64 addr:$src2)))]>;
1716 let Constraints = "$src1 = $dst" in {
1717 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1718 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1719 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1720 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1721 VR128:$src, imm:$cc))]>;
1722 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1723 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1724 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1725 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1726 (memop addr:$src), imm:$cc))]>;
1728 def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
1729 (CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
1730 def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
1731 (CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
1733 // Shuffle and unpack instructions
1734 let Constraints = "$src1 = $dst" in {
1735 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1736 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1737 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1738 [(set VR128:$dst, (v2f64 (vector_shuffle
1739 VR128:$src1, VR128:$src2,
1740 SHUFP_shuffle_mask:$src3)))]>;
1741 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1742 (outs VR128:$dst), (ins VR128:$src1,
1743 f128mem:$src2, i8imm:$src3),
1744 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 (v2f64 (vector_shuffle
1747 VR128:$src1, (memopv2f64 addr:$src2),
1748 SHUFP_shuffle_mask:$src3)))]>;
1750 let AddedComplexity = 10 in {
1751 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1752 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1753 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1755 (v2f64 (vector_shuffle
1756 VR128:$src1, VR128:$src2,
1757 UNPCKH_shuffle_mask)))]>;
1758 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1759 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1760 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1762 (v2f64 (vector_shuffle
1763 VR128:$src1, (memopv2f64 addr:$src2),
1764 UNPCKH_shuffle_mask)))]>;
1766 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1767 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1768 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1770 (v2f64 (vector_shuffle
1771 VR128:$src1, VR128:$src2,
1772 UNPCKL_shuffle_mask)))]>;
1773 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1775 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1777 (v2f64 (vector_shuffle
1778 VR128:$src1, (memopv2f64 addr:$src2),
1779 UNPCKL_shuffle_mask)))]>;
1780 } // AddedComplexity
1781 } // Constraints = "$src1 = $dst"
1784 //===----------------------------------------------------------------------===//
1785 // SSE integer instructions
1787 // Move Instructions
1788 let neverHasSideEffects = 1 in
1789 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1790 "movdqa\t{$src, $dst|$dst, $src}", []>;
1791 let isSimpleLoad = 1, mayLoad = 1 in
1792 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1793 "movdqa\t{$src, $dst|$dst, $src}",
1794 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1796 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1797 "movdqa\t{$src, $dst|$dst, $src}",
1798 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1799 let isSimpleLoad = 1, mayLoad = 1 in
1800 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1801 "movdqu\t{$src, $dst|$dst, $src}",
1802 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1803 XS, Requires<[HasSSE2]>;
1805 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1806 "movdqu\t{$src, $dst|$dst, $src}",
1807 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1808 XS, Requires<[HasSSE2]>;
1810 // Intrinsic forms of MOVDQU load and store
1811 let isSimpleLoad = 1 in
1812 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1813 "movdqu\t{$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1815 XS, Requires<[HasSSE2]>;
1816 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1817 "movdqu\t{$src, $dst|$dst, $src}",
1818 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1819 XS, Requires<[HasSSE2]>;
1821 let Constraints = "$src1 = $dst" in {
1823 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1824 bit Commutable = 0> {
1825 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1827 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1828 let isCommutable = Commutable;
1830 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1832 [(set VR128:$dst, (IntId VR128:$src1,
1833 (bitconvert (memopv2i64 addr:$src2))))]>;
1836 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1838 Intrinsic IntId, Intrinsic IntId2> {
1839 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1841 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1842 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId VR128:$src1,
1845 (bitconvert (memopv2i64 addr:$src2))))]>;
1846 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1847 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1848 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1851 /// PDI_binop_rm - Simple SSE2 binary operator.
1852 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1853 ValueType OpVT, bit Commutable = 0> {
1854 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1856 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1857 let isCommutable = Commutable;
1859 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1860 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1861 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1862 (bitconvert (memopv2i64 addr:$src2)))))]>;
1865 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1867 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1868 /// to collapse (bitconvert VT to VT) into its operand.
1870 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1871 bit Commutable = 0> {
1872 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1873 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1874 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1875 let isCommutable = Commutable;
1877 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1878 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1879 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1882 } // Constraints = "$src1 = $dst"
1884 // 128-bit Integer Arithmetic
1886 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1887 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1888 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1889 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1891 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1892 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1893 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1894 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1896 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1897 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1898 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1899 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1901 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1902 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1903 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1904 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1906 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1908 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1909 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1910 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1912 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1914 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1915 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1918 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1919 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1920 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1921 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1922 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1925 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1926 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1927 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1928 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1929 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1930 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1932 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1933 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1934 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1935 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1936 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1937 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1939 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1940 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1941 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1942 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1944 // 128-bit logical shifts.
1945 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1946 def PSLLDQri : PDIi8<0x73, MRM7r,
1947 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1948 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1949 def PSRLDQri : PDIi8<0x73, MRM3r,
1950 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1951 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1952 // PSRADQri doesn't exist in SSE[1-3].
1955 let Predicates = [HasSSE2] in {
1956 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1957 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1958 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1959 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1960 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1961 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1963 // Shift up / down and insert zero's.
1964 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1965 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1966 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1967 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1971 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1972 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1973 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1975 let Constraints = "$src1 = $dst" in {
1976 def PANDNrr : PDI<0xDF, MRMSrcReg,
1977 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1978 "pandn\t{$src2, $dst|$dst, $src2}",
1979 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1982 def PANDNrm : PDI<0xDF, MRMSrcMem,
1983 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1984 "pandn\t{$src2, $dst|$dst, $src2}",
1985 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1986 (memopv2i64 addr:$src2))))]>;
1989 // SSE2 Integer comparison
1990 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1991 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1992 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1993 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1994 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1995 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1997 def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETEQ)),
1998 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
1999 def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETEQ)),
2000 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2001 def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETEQ)),
2002 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2003 def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETEQ)),
2004 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2005 def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETEQ)),
2006 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2007 def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETEQ)),
2008 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2010 def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETGT)),
2011 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2012 def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETGT)),
2013 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2014 def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETGT)),
2015 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2016 def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETGT)),
2017 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2018 def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETGT)),
2019 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2020 def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETGT)),
2021 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2024 // Pack instructions
2025 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2026 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2027 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2029 // Shuffle and unpack instructions
2030 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2031 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2032 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2033 [(set VR128:$dst, (v4i32 (vector_shuffle
2034 VR128:$src1, (undef),
2035 PSHUFD_shuffle_mask:$src2)))]>;
2036 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2037 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2038 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2039 [(set VR128:$dst, (v4i32 (vector_shuffle
2040 (bc_v4i32(memopv2i64 addr:$src1)),
2042 PSHUFD_shuffle_mask:$src2)))]>;
2044 // SSE2 with ImmT == Imm8 and XS prefix.
2045 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2046 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2047 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2048 [(set VR128:$dst, (v8i16 (vector_shuffle
2049 VR128:$src1, (undef),
2050 PSHUFHW_shuffle_mask:$src2)))]>,
2051 XS, Requires<[HasSSE2]>;
2052 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2053 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2054 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2055 [(set VR128:$dst, (v8i16 (vector_shuffle
2056 (bc_v8i16 (memopv2i64 addr:$src1)),
2058 PSHUFHW_shuffle_mask:$src2)))]>,
2059 XS, Requires<[HasSSE2]>;
2061 // SSE2 with ImmT == Imm8 and XD prefix.
2062 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2063 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2064 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2065 [(set VR128:$dst, (v8i16 (vector_shuffle
2066 VR128:$src1, (undef),
2067 PSHUFLW_shuffle_mask:$src2)))]>,
2068 XD, Requires<[HasSSE2]>;
2069 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2070 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2071 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set VR128:$dst, (v8i16 (vector_shuffle
2073 (bc_v8i16 (memopv2i64 addr:$src1)),
2075 PSHUFLW_shuffle_mask:$src2)))]>,
2076 XD, Requires<[HasSSE2]>;
2079 let Constraints = "$src1 = $dst" in {
2080 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2081 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2082 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2084 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2085 UNPCKL_shuffle_mask)))]>;
2086 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2087 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2088 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2090 (v16i8 (vector_shuffle VR128:$src1,
2091 (bc_v16i8 (memopv2i64 addr:$src2)),
2092 UNPCKL_shuffle_mask)))]>;
2093 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2094 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2095 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2097 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2098 UNPCKL_shuffle_mask)))]>;
2099 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2100 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2101 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2103 (v8i16 (vector_shuffle VR128:$src1,
2104 (bc_v8i16 (memopv2i64 addr:$src2)),
2105 UNPCKL_shuffle_mask)))]>;
2106 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2107 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2108 "punpckldq\t{$src2, $dst|$dst, $src2}",
2110 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2111 UNPCKL_shuffle_mask)))]>;
2112 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2113 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2114 "punpckldq\t{$src2, $dst|$dst, $src2}",
2116 (v4i32 (vector_shuffle VR128:$src1,
2117 (bc_v4i32 (memopv2i64 addr:$src2)),
2118 UNPCKL_shuffle_mask)))]>;
2119 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2120 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2121 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2123 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2124 UNPCKL_shuffle_mask)))]>;
2125 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2126 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2127 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2129 (v2i64 (vector_shuffle VR128:$src1,
2130 (memopv2i64 addr:$src2),
2131 UNPCKL_shuffle_mask)))]>;
2133 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2134 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2135 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2137 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2138 UNPCKH_shuffle_mask)))]>;
2139 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2140 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2141 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2143 (v16i8 (vector_shuffle VR128:$src1,
2144 (bc_v16i8 (memopv2i64 addr:$src2)),
2145 UNPCKH_shuffle_mask)))]>;
2146 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2147 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2148 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2150 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2151 UNPCKH_shuffle_mask)))]>;
2152 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2153 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2154 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2156 (v8i16 (vector_shuffle VR128:$src1,
2157 (bc_v8i16 (memopv2i64 addr:$src2)),
2158 UNPCKH_shuffle_mask)))]>;
2159 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2160 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2161 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2163 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2164 UNPCKH_shuffle_mask)))]>;
2165 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2166 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2167 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2169 (v4i32 (vector_shuffle VR128:$src1,
2170 (bc_v4i32 (memopv2i64 addr:$src2)),
2171 UNPCKH_shuffle_mask)))]>;
2172 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2173 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2174 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2176 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2177 UNPCKH_shuffle_mask)))]>;
2178 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2179 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2180 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2182 (v2i64 (vector_shuffle VR128:$src1,
2183 (memopv2i64 addr:$src2),
2184 UNPCKH_shuffle_mask)))]>;
2188 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2189 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2190 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2191 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2193 let Constraints = "$src1 = $dst" in {
2194 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2195 (outs VR128:$dst), (ins VR128:$src1,
2196 GR32:$src2, i32i8imm:$src3),
2197 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2199 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2200 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2201 (outs VR128:$dst), (ins VR128:$src1,
2202 i16mem:$src2, i32i8imm:$src3),
2203 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2205 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2210 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2211 "pmovmskb\t{$src, $dst|$dst, $src}",
2212 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2214 // Conditional store
2216 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2217 "maskmovdqu\t{$mask, $src|$src, $mask}",
2218 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2220 // Non-temporal stores
2221 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2222 "movntpd\t{$src, $dst|$dst, $src}",
2223 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2224 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2225 "movntdq\t{$src, $dst|$dst, $src}",
2226 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2227 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2228 "movnti\t{$src, $dst|$dst, $src}",
2229 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2230 TB, Requires<[HasSSE2]>;
2233 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2234 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2235 TB, Requires<[HasSSE2]>;
2237 // Load, store, and memory fence
2238 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2239 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2240 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2241 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2243 //TODO: custom lower this so as to never even generate the noop
2244 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2246 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2247 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2248 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2251 // Alias instructions that map zero vector to pxor / xorp* for sse.
2252 let isReMaterializable = 1 in
2253 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2254 "pcmpeqd\t$dst, $dst",
2255 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2257 // FR64 to 128-bit vector conversion.
2258 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2259 "movsd\t{$src, $dst|$dst, $src}",
2261 (v2f64 (scalar_to_vector FR64:$src)))]>;
2262 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2263 "movsd\t{$src, $dst|$dst, $src}",
2265 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2267 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2268 "movd\t{$src, $dst|$dst, $src}",
2270 (v4i32 (scalar_to_vector GR32:$src)))]>;
2271 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2272 "movd\t{$src, $dst|$dst, $src}",
2274 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2276 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2277 "movd\t{$src, $dst|$dst, $src}",
2278 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2280 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2281 "movd\t{$src, $dst|$dst, $src}",
2282 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2284 // SSE2 instructions with XS prefix
2285 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2286 "movq\t{$src, $dst|$dst, $src}",
2288 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2289 Requires<[HasSSE2]>;
2290 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2291 "movq\t{$src, $dst|$dst, $src}",
2292 [(store (i64 (vector_extract (v2i64 VR128:$src),
2293 (iPTR 0))), addr:$dst)]>;
2295 // FIXME: may not be able to eliminate this movss with coalescing the src and
2296 // dest register classes are different. We really want to write this pattern
2298 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2299 // (f32 FR32:$src)>;
2300 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2301 "movsd\t{$src, $dst|$dst, $src}",
2302 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2304 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2305 "movsd\t{$src, $dst|$dst, $src}",
2306 [(store (f64 (vector_extract (v2f64 VR128:$src),
2307 (iPTR 0))), addr:$dst)]>;
2308 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2309 "movd\t{$src, $dst|$dst, $src}",
2310 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2312 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2313 "movd\t{$src, $dst|$dst, $src}",
2314 [(store (i32 (vector_extract (v4i32 VR128:$src),
2315 (iPTR 0))), addr:$dst)]>;
2317 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2318 "movd\t{$src, $dst|$dst, $src}",
2319 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2320 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2321 "movd\t{$src, $dst|$dst, $src}",
2322 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2325 // Move to lower bits of a VR128, leaving upper bits alone.
2326 // Three operand (but two address) aliases.
2327 let Constraints = "$src1 = $dst" in {
2328 let neverHasSideEffects = 1 in
2329 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2330 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2331 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2333 let AddedComplexity = 15 in
2334 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2335 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2336 "movsd\t{$src2, $dst|$dst, $src2}",
2338 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2339 MOVL_shuffle_mask)))]>;
2342 // Store / copy lower 64-bits of a XMM register.
2343 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2344 "movq\t{$src, $dst|$dst, $src}",
2345 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2347 // Move to lower bits of a VR128 and zeroing upper bits.
2348 // Loading from memory automatically zeroing upper bits.
2349 let AddedComplexity = 20 in {
2350 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2351 "movsd\t{$src, $dst|$dst, $src}",
2353 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2354 (loadf64 addr:$src))))))]>;
2356 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2357 (MOVZSD2PDrm addr:$src)>;
2358 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2359 (MOVZSD2PDrm addr:$src)>;
2360 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2363 // movd / movq to XMM register zero-extends
2364 let AddedComplexity = 15 in {
2365 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2366 "movd\t{$src, $dst|$dst, $src}",
2367 [(set VR128:$dst, (v4i32 (X86vzmovl
2368 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2369 // This is X86-64 only.
2370 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2371 "mov{d|q}\t{$src, $dst|$dst, $src}",
2372 [(set VR128:$dst, (v2i64 (X86vzmovl
2373 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2376 let AddedComplexity = 20 in {
2377 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2378 "movd\t{$src, $dst|$dst, $src}",
2380 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2381 (loadi32 addr:$src))))))]>;
2383 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2384 (MOVZDI2PDIrm addr:$src)>;
2385 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2386 (MOVZDI2PDIrm addr:$src)>;
2388 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2389 "movq\t{$src, $dst|$dst, $src}",
2391 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2392 (loadi64 addr:$src))))))]>, XS,
2393 Requires<[HasSSE2]>;
2395 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2396 (MOVZQI2PQIrm addr:$src)>;
2397 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2398 (MOVZQI2PQIrm addr:$src)>;
2399 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2402 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2403 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2404 let AddedComplexity = 15 in
2405 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2406 "movq\t{$src, $dst|$dst, $src}",
2407 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2408 XS, Requires<[HasSSE2]>;
2410 let AddedComplexity = 20 in {
2411 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2412 "movq\t{$src, $dst|$dst, $src}",
2413 [(set VR128:$dst, (v2i64 (X86vzmovl
2414 (loadv2i64 addr:$src))))]>,
2415 XS, Requires<[HasSSE2]>;
2417 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2418 (MOVZPQILo2PQIrm addr:$src)>;
2421 //===----------------------------------------------------------------------===//
2422 // SSE3 Instructions
2423 //===----------------------------------------------------------------------===//
2425 // Move Instructions
2426 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2427 "movshdup\t{$src, $dst|$dst, $src}",
2428 [(set VR128:$dst, (v4f32 (vector_shuffle
2429 VR128:$src, (undef),
2430 MOVSHDUP_shuffle_mask)))]>;
2431 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2432 "movshdup\t{$src, $dst|$dst, $src}",
2433 [(set VR128:$dst, (v4f32 (vector_shuffle
2434 (memopv4f32 addr:$src), (undef),
2435 MOVSHDUP_shuffle_mask)))]>;
2437 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2438 "movsldup\t{$src, $dst|$dst, $src}",
2439 [(set VR128:$dst, (v4f32 (vector_shuffle
2440 VR128:$src, (undef),
2441 MOVSLDUP_shuffle_mask)))]>;
2442 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2443 "movsldup\t{$src, $dst|$dst, $src}",
2444 [(set VR128:$dst, (v4f32 (vector_shuffle
2445 (memopv4f32 addr:$src), (undef),
2446 MOVSLDUP_shuffle_mask)))]>;
2448 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2449 "movddup\t{$src, $dst|$dst, $src}",
2450 [(set VR128:$dst, (v2f64 (vector_shuffle
2451 VR128:$src, (undef),
2452 SSE_splat_lo_mask)))]>;
2453 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2454 "movddup\t{$src, $dst|$dst, $src}",
2456 (v2f64 (vector_shuffle
2457 (scalar_to_vector (loadf64 addr:$src)),
2459 SSE_splat_lo_mask)))]>;
2462 let Constraints = "$src1 = $dst" in {
2463 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2464 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2465 "addsubps\t{$src2, $dst|$dst, $src2}",
2466 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2468 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2469 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2470 "addsubps\t{$src2, $dst|$dst, $src2}",
2471 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2472 (memop addr:$src2)))]>;
2473 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2474 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2475 "addsubpd\t{$src2, $dst|$dst, $src2}",
2476 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2478 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2479 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2480 "addsubpd\t{$src2, $dst|$dst, $src2}",
2481 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2482 (memop addr:$src2)))]>;
2485 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2486 "lddqu\t{$src, $dst|$dst, $src}",
2487 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2490 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2491 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2492 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2493 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2494 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2495 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2496 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2497 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2498 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2499 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2500 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2501 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2502 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2503 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2504 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2505 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2507 let Constraints = "$src1 = $dst" in {
2508 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2509 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2510 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2511 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2512 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2513 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2514 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2515 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2518 // Thread synchronization
2519 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2520 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2521 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2522 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2524 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2525 let AddedComplexity = 15 in
2526 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2527 MOVSHDUP_shuffle_mask)),
2528 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2529 let AddedComplexity = 20 in
2530 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2531 MOVSHDUP_shuffle_mask)),
2532 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2534 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2535 let AddedComplexity = 15 in
2536 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2537 MOVSLDUP_shuffle_mask)),
2538 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2539 let AddedComplexity = 20 in
2540 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2541 MOVSLDUP_shuffle_mask)),
2542 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2544 //===----------------------------------------------------------------------===//
2545 // SSSE3 Instructions
2546 //===----------------------------------------------------------------------===//
2548 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2549 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2550 Intrinsic IntId64, Intrinsic IntId128> {
2551 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2553 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2555 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2558 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2560 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2563 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2566 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2571 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2574 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2575 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2576 Intrinsic IntId64, Intrinsic IntId128> {
2577 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2579 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2580 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2582 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2587 (bitconvert (memopv4i16 addr:$src))))]>;
2589 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2591 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2592 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2595 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2597 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2600 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2603 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2604 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2605 Intrinsic IntId64, Intrinsic IntId128> {
2606 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2608 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2609 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2611 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2616 (bitconvert (memopv2i32 addr:$src))))]>;
2618 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2621 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2624 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2629 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2632 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2633 int_x86_ssse3_pabs_b,
2634 int_x86_ssse3_pabs_b_128>;
2635 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2636 int_x86_ssse3_pabs_w,
2637 int_x86_ssse3_pabs_w_128>;
2638 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2639 int_x86_ssse3_pabs_d,
2640 int_x86_ssse3_pabs_d_128>;
2642 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2643 let Constraints = "$src1 = $dst" in {
2644 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2645 Intrinsic IntId64, Intrinsic IntId128,
2646 bit Commutable = 0> {
2647 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2648 (ins VR64:$src1, VR64:$src2),
2649 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2650 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2651 let isCommutable = Commutable;
2653 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2654 (ins VR64:$src1, i64mem:$src2),
2655 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2657 (IntId64 VR64:$src1,
2658 (bitconvert (memopv8i8 addr:$src2))))]>;
2660 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2661 (ins VR128:$src1, VR128:$src2),
2662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2663 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2665 let isCommutable = Commutable;
2667 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2668 (ins VR128:$src1, i128mem:$src2),
2669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2671 (IntId128 VR128:$src1,
2672 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2676 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2677 let Constraints = "$src1 = $dst" in {
2678 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2679 Intrinsic IntId64, Intrinsic IntId128,
2680 bit Commutable = 0> {
2681 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2682 (ins VR64:$src1, VR64:$src2),
2683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2684 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2685 let isCommutable = Commutable;
2687 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2688 (ins VR64:$src1, i64mem:$src2),
2689 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2691 (IntId64 VR64:$src1,
2692 (bitconvert (memopv4i16 addr:$src2))))]>;
2694 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2695 (ins VR128:$src1, VR128:$src2),
2696 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2697 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2699 let isCommutable = Commutable;
2701 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2702 (ins VR128:$src1, i128mem:$src2),
2703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2705 (IntId128 VR128:$src1,
2706 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2710 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2711 let Constraints = "$src1 = $dst" in {
2712 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2713 Intrinsic IntId64, Intrinsic IntId128,
2714 bit Commutable = 0> {
2715 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2716 (ins VR64:$src1, VR64:$src2),
2717 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2718 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2719 let isCommutable = Commutable;
2721 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2722 (ins VR64:$src1, i64mem:$src2),
2723 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2725 (IntId64 VR64:$src1,
2726 (bitconvert (memopv2i32 addr:$src2))))]>;
2728 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2729 (ins VR128:$src1, VR128:$src2),
2730 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2731 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2733 let isCommutable = Commutable;
2735 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2736 (ins VR128:$src1, i128mem:$src2),
2737 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2739 (IntId128 VR128:$src1,
2740 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2744 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2745 int_x86_ssse3_phadd_w,
2746 int_x86_ssse3_phadd_w_128, 1>;
2747 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2748 int_x86_ssse3_phadd_d,
2749 int_x86_ssse3_phadd_d_128, 1>;
2750 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2751 int_x86_ssse3_phadd_sw,
2752 int_x86_ssse3_phadd_sw_128, 1>;
2753 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2754 int_x86_ssse3_phsub_w,
2755 int_x86_ssse3_phsub_w_128>;
2756 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2757 int_x86_ssse3_phsub_d,
2758 int_x86_ssse3_phsub_d_128>;
2759 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2760 int_x86_ssse3_phsub_sw,
2761 int_x86_ssse3_phsub_sw_128>;
2762 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2763 int_x86_ssse3_pmadd_ub_sw,
2764 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2765 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2766 int_x86_ssse3_pmul_hr_sw,
2767 int_x86_ssse3_pmul_hr_sw_128, 1>;
2768 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2769 int_x86_ssse3_pshuf_b,
2770 int_x86_ssse3_pshuf_b_128>;
2771 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2772 int_x86_ssse3_psign_b,
2773 int_x86_ssse3_psign_b_128>;
2774 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2775 int_x86_ssse3_psign_w,
2776 int_x86_ssse3_psign_w_128>;
2777 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2778 int_x86_ssse3_psign_d,
2779 int_x86_ssse3_psign_d_128>;
2781 let Constraints = "$src1 = $dst" in {
2782 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2783 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2784 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2786 (int_x86_ssse3_palign_r
2787 VR64:$src1, VR64:$src2,
2789 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2790 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2791 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2793 (int_x86_ssse3_palign_r
2795 (bitconvert (memopv2i32 addr:$src2)),
2798 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2799 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2800 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2802 (int_x86_ssse3_palign_r_128
2803 VR128:$src1, VR128:$src2,
2804 imm:$src3))]>, OpSize;
2805 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2806 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2807 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2809 (int_x86_ssse3_palign_r_128
2811 (bitconvert (memopv4i32 addr:$src2)),
2812 imm:$src3))]>, OpSize;
2815 //===----------------------------------------------------------------------===//
2816 // Non-Instruction Patterns
2817 //===----------------------------------------------------------------------===//
2819 // extload f32 -> f64. This matches load+fextend because we have a hack in
2820 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2821 // Since these loads aren't folded into the fextend, we have to match it
2823 let Predicates = [HasSSE2] in
2824 def : Pat<(fextend (loadf32 addr:$src)),
2825 (CVTSS2SDrm addr:$src)>;
2828 let Predicates = [HasSSE2] in {
2829 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2830 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2831 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2832 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2833 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2834 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2835 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2836 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2837 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2838 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2839 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2840 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2841 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2842 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2843 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2844 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2845 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2846 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2847 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2848 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2849 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2850 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2851 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2852 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2853 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2854 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2855 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2856 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2857 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2858 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2861 // Move scalar to XMM zero-extended
2862 // movd to XMM register zero-extends
2863 let AddedComplexity = 15 in {
2864 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2865 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2866 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2867 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2868 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2869 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2870 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2873 // Splat v2f64 / v2i64
2874 let AddedComplexity = 10 in {
2875 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2876 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2877 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2878 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2879 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2880 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2881 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2882 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2885 // Special unary SHUFPSrri case.
2886 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2887 SHUFP_unary_shuffle_mask:$sm)),
2888 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2889 Requires<[HasSSE1]>;
2890 // Special unary SHUFPDrri case.
2891 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2892 SHUFP_unary_shuffle_mask:$sm)),
2893 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2894 Requires<[HasSSE2]>;
2895 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2896 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2897 SHUFP_unary_shuffle_mask:$sm),
2898 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2899 Requires<[HasSSE2]>;
2900 // Special binary v4i32 shuffle cases with SHUFPS.
2901 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2902 PSHUFD_binary_shuffle_mask:$sm)),
2903 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2904 Requires<[HasSSE2]>;
2905 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2906 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2907 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2908 Requires<[HasSSE2]>;
2909 // Special binary v2i64 shuffle cases using SHUFPDrri.
2910 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2911 SHUFP_shuffle_mask:$sm)),
2912 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2913 Requires<[HasSSE2]>;
2914 // Special unary SHUFPDrri case.
2915 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2916 SHUFP_unary_shuffle_mask:$sm)),
2917 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2918 Requires<[HasSSE2]>;
2920 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2921 let AddedComplexity = 10 in {
2922 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2923 UNPCKL_v_undef_shuffle_mask)),
2924 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2925 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2926 UNPCKL_v_undef_shuffle_mask)),
2927 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2928 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2929 UNPCKL_v_undef_shuffle_mask)),
2930 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2931 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2932 UNPCKL_v_undef_shuffle_mask)),
2933 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2936 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2937 let AddedComplexity = 10 in {
2938 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2939 UNPCKH_v_undef_shuffle_mask)),
2940 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2941 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2942 UNPCKH_v_undef_shuffle_mask)),
2943 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2944 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2945 UNPCKH_v_undef_shuffle_mask)),
2946 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2947 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2948 UNPCKH_v_undef_shuffle_mask)),
2949 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2952 let AddedComplexity = 15 in {
2953 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2954 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2955 MOVHP_shuffle_mask)),
2956 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2958 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2959 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2960 MOVHLPS_shuffle_mask)),
2961 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2963 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2964 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2965 MOVHLPS_v_undef_shuffle_mask)),
2966 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2967 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2968 MOVHLPS_v_undef_shuffle_mask)),
2969 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2972 let AddedComplexity = 20 in {
2973 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2974 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2975 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2976 MOVLP_shuffle_mask)),
2977 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2978 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2979 MOVLP_shuffle_mask)),
2980 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2981 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2982 MOVHP_shuffle_mask)),
2983 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2984 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2985 MOVHP_shuffle_mask)),
2986 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2989 (bc_v4i32 (memopv2i64 addr:$src2)),
2990 MOVLP_shuffle_mask)),
2991 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2992 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2993 MOVLP_shuffle_mask)),
2994 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2995 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2996 (bc_v4i32 (memopv2i64 addr:$src2)),
2997 MOVHP_shuffle_mask)),
2998 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2999 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3000 MOVHP_shuffle_mask)),
3001 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3004 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3005 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3006 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3007 MOVLP_shuffle_mask)), addr:$src1),
3008 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3009 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3010 MOVLP_shuffle_mask)), addr:$src1),
3011 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3012 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3013 MOVHP_shuffle_mask)), addr:$src1),
3014 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3015 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3016 MOVHP_shuffle_mask)), addr:$src1),
3017 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3019 def : Pat<(store (v4i32 (vector_shuffle
3020 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3021 MOVLP_shuffle_mask)), addr:$src1),
3022 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3023 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3024 MOVLP_shuffle_mask)), addr:$src1),
3025 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3026 def : Pat<(store (v4i32 (vector_shuffle
3027 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3028 MOVHP_shuffle_mask)), addr:$src1),
3029 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3030 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3031 MOVHP_shuffle_mask)), addr:$src1),
3032 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3035 let AddedComplexity = 15 in {
3036 // Setting the lowest element in the vector.
3037 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3038 MOVL_shuffle_mask)),
3039 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3040 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3041 MOVL_shuffle_mask)),
3042 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3044 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3045 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3046 MOVLP_shuffle_mask)),
3047 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3048 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3049 MOVLP_shuffle_mask)),
3050 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3053 // Set lowest element and zero upper elements.
3054 let AddedComplexity = 15 in
3055 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3056 MOVL_shuffle_mask)),
3057 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3058 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3059 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3061 // Some special case pandn patterns.
3062 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3064 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3065 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3067 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3068 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3070 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3073 (memop addr:$src2))),
3074 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3075 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3076 (memop addr:$src2))),
3077 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3078 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3079 (memop addr:$src2))),
3080 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3082 // vector -> vector casts
3083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3084 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3085 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3086 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3088 // Use movaps / movups for SSE integer load / store (one byte shorter).
3089 def : Pat<(alignedloadv4i32 addr:$src),
3090 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3091 def : Pat<(loadv4i32 addr:$src),
3092 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3093 def : Pat<(alignedloadv2i64 addr:$src),
3094 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3095 def : Pat<(loadv2i64 addr:$src),
3096 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3098 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3099 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3100 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3101 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3103 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3104 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3105 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3107 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3108 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3109 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3110 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3111 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3112 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3113 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3115 //===----------------------------------------------------------------------===//
3116 // SSE4.1 Instructions
3117 //===----------------------------------------------------------------------===//
3119 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3120 bits<8> opcsd, bits<8> opcpd,
3125 Intrinsic V2F64Int> {
3126 // Intrinsic operation, reg.
3127 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3128 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3129 !strconcat(OpcodeStr,
3130 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3131 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3134 // Intrinsic operation, mem.
3135 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3136 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3137 !strconcat(OpcodeStr,
3138 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3139 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3142 // Vector intrinsic operation, reg
3143 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3144 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3145 !strconcat(OpcodeStr,
3146 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3147 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3150 // Vector intrinsic operation, mem
3151 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3152 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3153 !strconcat(OpcodeStr,
3154 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3156 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3159 // Intrinsic operation, reg.
3160 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3161 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3162 !strconcat(OpcodeStr,
3163 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3167 // Intrinsic operation, mem.
3168 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3169 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3175 // Vector intrinsic operation, reg
3176 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3177 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3180 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3183 // Vector intrinsic operation, mem
3184 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3185 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3186 !strconcat(OpcodeStr,
3187 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3189 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3193 // FP round - roundss, roundps, roundsd, roundpd
3194 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3195 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3196 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3198 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3199 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3200 Intrinsic IntId128> {
3201 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3203 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3205 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3207 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3210 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3213 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3214 int_x86_sse41_phminposuw>;
3216 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3217 let Constraints = "$src1 = $dst" in {
3218 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3219 Intrinsic IntId128, bit Commutable = 0> {
3220 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3221 (ins VR128:$src1, VR128:$src2),
3222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3223 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3225 let isCommutable = Commutable;
3227 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3228 (ins VR128:$src1, i128mem:$src2),
3229 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3231 (IntId128 VR128:$src1,
3232 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3236 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3237 int_x86_sse41_pcmpeqq, 1>;
3238 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3239 int_x86_sse41_packusdw, 0>;
3240 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3241 int_x86_sse41_pminsb, 1>;
3242 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3243 int_x86_sse41_pminsd, 1>;
3244 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3245 int_x86_sse41_pminud, 1>;
3246 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3247 int_x86_sse41_pminuw, 1>;
3248 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3249 int_x86_sse41_pmaxsb, 1>;
3250 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3251 int_x86_sse41_pmaxsd, 1>;
3252 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3253 int_x86_sse41_pmaxud, 1>;
3254 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3255 int_x86_sse41_pmaxuw, 1>;
3258 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3259 let Constraints = "$src1 = $dst" in {
3260 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3261 SDNode OpNode, Intrinsic IntId128,
3262 bit Commutable = 0> {
3263 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3264 (ins VR128:$src1, VR128:$src2),
3265 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3266 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3267 VR128:$src2))]>, OpSize {
3268 let isCommutable = Commutable;
3270 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3271 (ins VR128:$src1, VR128:$src2),
3272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3273 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3275 let isCommutable = Commutable;
3277 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3278 (ins VR128:$src1, i128mem:$src2),
3279 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3281 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3282 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3283 (ins VR128:$src1, i128mem:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3290 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3291 int_x86_sse41_pmulld, 1>;
3292 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3293 int_x86_sse41_pmuldq, 1>;
3296 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3297 let Constraints = "$src1 = $dst" in {
3298 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3299 Intrinsic IntId128, bit Commutable = 0> {
3300 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3301 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3302 !strconcat(OpcodeStr,
3303 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3305 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3307 let isCommutable = Commutable;
3309 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3310 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3311 !strconcat(OpcodeStr,
3312 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3314 (IntId128 VR128:$src1,
3315 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3320 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3321 int_x86_sse41_blendps, 0>;
3322 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3323 int_x86_sse41_blendpd, 0>;
3324 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3325 int_x86_sse41_pblendw, 0>;
3326 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3327 int_x86_sse41_dpps, 1>;
3328 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3329 int_x86_sse41_dppd, 1>;
3330 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3331 int_x86_sse41_mpsadbw, 0>;
3334 /// SS41I_ternary_int - SSE 4.1 ternary operator
3335 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3336 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3337 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3338 (ins VR128:$src1, VR128:$src2),
3339 !strconcat(OpcodeStr,
3340 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3341 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3344 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3345 (ins VR128:$src1, i128mem:$src2),
3346 !strconcat(OpcodeStr,
3347 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3350 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3354 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3355 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3356 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3359 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3360 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3362 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3364 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3367 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3370 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3371 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3372 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3373 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3374 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3375 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3377 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3378 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3379 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3380 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3382 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3383 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3385 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3388 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3389 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3390 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3391 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3393 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3394 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3395 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3396 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3398 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3399 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3401 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3404 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3405 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3408 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3409 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3410 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3411 (ins VR128:$src1, i32i8imm:$src2),
3412 !strconcat(OpcodeStr,
3413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3416 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3417 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3418 !strconcat(OpcodeStr,
3419 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3422 // There's an AssertZext in the way of writing the store pattern
3423 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3426 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3429 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3430 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3431 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3432 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3433 !strconcat(OpcodeStr,
3434 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3437 // There's an AssertZext in the way of writing the store pattern
3438 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3441 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3444 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3445 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3446 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3447 (ins VR128:$src1, i32i8imm:$src2),
3448 !strconcat(OpcodeStr,
3449 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3451 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3452 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3453 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3454 !strconcat(OpcodeStr,
3455 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3456 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3457 addr:$dst)]>, OpSize;
3460 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3463 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3465 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3466 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3467 (ins VR128:$src1, i32i8imm:$src2),
3468 !strconcat(OpcodeStr,
3469 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3471 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3473 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3474 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3475 !strconcat(OpcodeStr,
3476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3477 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3478 addr:$dst)]>, OpSize;
3481 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3483 let Constraints = "$src1 = $dst" in {
3484 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3485 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3486 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3487 !strconcat(OpcodeStr,
3488 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3490 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3491 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3492 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3493 !strconcat(OpcodeStr,
3494 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3496 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3497 imm:$src3))]>, OpSize;
3501 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3503 let Constraints = "$src1 = $dst" in {
3504 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3505 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3506 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3507 !strconcat(OpcodeStr,
3508 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3510 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3512 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3513 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3514 !strconcat(OpcodeStr,
3515 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3517 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3518 imm:$src3)))]>, OpSize;
3522 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3524 let Constraints = "$src1 = $dst" in {
3525 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3526 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3527 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3528 !strconcat(OpcodeStr,
3529 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3531 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3532 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3533 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3534 !strconcat(OpcodeStr,
3535 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3537 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3538 imm:$src3))]>, OpSize;
3542 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3544 let Defs = [EFLAGS] in {
3545 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3546 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3547 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3548 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3551 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3552 "movntdqa\t{$src, $dst|$dst, $src}",
3553 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;