1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
74 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
76 //===----------------------------------------------------------------------===//
77 // SSE Complex Patterns
78 //===----------------------------------------------------------------------===//
80 // These are 'extloads' from a scalar to the low element of a vector, zeroing
81 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
83 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
84 [SDNPHasChain, SDNPMayLoad]>;
85 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
86 [SDNPHasChain, SDNPMayLoad]>;
88 def ssmem : Operand<v4f32> {
89 let PrintMethod = "printf32mem";
90 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
91 let ParserMatchClass = X86MemAsmOperand;
93 def sdmem : Operand<v2f64> {
94 let PrintMethod = "printf64mem";
95 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
96 let ParserMatchClass = X86MemAsmOperand;
99 //===----------------------------------------------------------------------===//
100 // SSE pattern fragments
101 //===----------------------------------------------------------------------===//
103 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
104 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
105 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
106 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
108 // Like 'store', but always requires vector alignment.
109 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
110 (store node:$val, node:$ptr), [{
111 return cast<StoreSDNode>(N)->getAlignment() >= 16;
114 // Like 'load', but always requires vector alignment.
115 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
116 return cast<LoadSDNode>(N)->getAlignment() >= 16;
119 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
120 (f32 (alignedload node:$ptr))>;
121 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
122 (f64 (alignedload node:$ptr))>;
123 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
124 (v4f32 (alignedload node:$ptr))>;
125 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
126 (v2f64 (alignedload node:$ptr))>;
127 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
128 (v4i32 (alignedload node:$ptr))>;
129 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
130 (v2i64 (alignedload node:$ptr))>;
132 // Like 'load', but uses special alignment checks suitable for use in
133 // memory operands in most SSE instructions, which are required to
134 // be naturally aligned on some targets but not on others. If the subtarget
135 // allows unaligned accesses, match any load, though this may require
136 // setting a feature bit in the processor (on startup, for example).
137 // Opteron 10h and later implement such a feature.
138 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
139 return Subtarget->hasVectorUAMem()
140 || cast<LoadSDNode>(N)->getAlignment() >= 16;
143 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
144 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
145 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
146 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
147 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
148 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
149 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
151 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
153 // FIXME: 8 byte alignment for mmx reads is not required
154 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
155 return cast<LoadSDNode>(N)->getAlignment() >= 8;
158 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
159 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
160 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
161 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
163 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
164 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
165 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
166 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
167 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
168 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
170 def vzmovl_v2i64 : PatFrag<(ops node:$src),
171 (bitconvert (v2i64 (X86vzmovl
172 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
173 def vzmovl_v4i32 : PatFrag<(ops node:$src),
174 (bitconvert (v4i32 (X86vzmovl
175 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
177 def vzload_v2i64 : PatFrag<(ops node:$src),
178 (bitconvert (v2i64 (X86vzload node:$src)))>;
181 def fp32imm0 : PatLeaf<(f32 fpimm), [{
182 return N->isExactlyValue(+0.0);
185 // BYTE_imm - Transform bit immediates into byte immediates.
186 def BYTE_imm : SDNodeXForm<imm, [{
187 // Transformation function: imm >> 3
188 return getI32Imm(N->getZExtValue() >> 3);
191 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
193 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
194 return getI8Imm(X86::getShuffleSHUFImmediate(N));
197 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
199 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
200 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
203 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
205 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
206 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
209 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
211 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
212 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
215 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
216 (vector_shuffle node:$lhs, node:$rhs), [{
217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
218 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
221 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
222 (vector_shuffle node:$lhs, node:$rhs), [{
223 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
226 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
227 (vector_shuffle node:$lhs, node:$rhs), [{
228 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
231 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
232 (vector_shuffle node:$lhs, node:$rhs), [{
233 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
236 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
237 (vector_shuffle node:$lhs, node:$rhs), [{
238 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
241 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
242 (vector_shuffle node:$lhs, node:$rhs), [{
243 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
246 def movl : PatFrag<(ops node:$lhs, node:$rhs),
247 (vector_shuffle node:$lhs, node:$rhs), [{
248 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
251 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
252 (vector_shuffle node:$lhs, node:$rhs), [{
253 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
256 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
257 (vector_shuffle node:$lhs, node:$rhs), [{
258 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
261 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
262 (vector_shuffle node:$lhs, node:$rhs), [{
263 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
266 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
267 (vector_shuffle node:$lhs, node:$rhs), [{
268 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
271 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
272 (vector_shuffle node:$lhs, node:$rhs), [{
273 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
276 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
277 (vector_shuffle node:$lhs, node:$rhs), [{
278 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
281 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
282 (vector_shuffle node:$lhs, node:$rhs), [{
283 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
284 }], SHUFFLE_get_shuf_imm>;
286 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
287 (vector_shuffle node:$lhs, node:$rhs), [{
288 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
289 }], SHUFFLE_get_shuf_imm>;
291 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
292 (vector_shuffle node:$lhs, node:$rhs), [{
293 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
294 }], SHUFFLE_get_pshufhw_imm>;
296 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
297 (vector_shuffle node:$lhs, node:$rhs), [{
298 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
299 }], SHUFFLE_get_pshuflw_imm>;
301 def palign : PatFrag<(ops node:$lhs, node:$rhs),
302 (vector_shuffle node:$lhs, node:$rhs), [{
303 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
304 }], SHUFFLE_get_palign_imm>;
306 //===----------------------------------------------------------------------===//
307 // SSE scalar FP Instructions
308 //===----------------------------------------------------------------------===//
310 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
311 // instruction selection into a branch sequence.
312 let Uses = [EFLAGS], usesCustomInserter = 1 in {
313 def CMOV_FR32 : I<0, Pseudo,
314 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
315 "#CMOV_FR32 PSEUDO!",
316 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
318 def CMOV_FR64 : I<0, Pseudo,
319 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
320 "#CMOV_FR64 PSEUDO!",
321 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
323 def CMOV_V4F32 : I<0, Pseudo,
324 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
325 "#CMOV_V4F32 PSEUDO!",
327 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
329 def CMOV_V2F64 : I<0, Pseudo,
330 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
331 "#CMOV_V2F64 PSEUDO!",
333 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
335 def CMOV_V2I64 : I<0, Pseudo,
336 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
337 "#CMOV_V2I64 PSEUDO!",
339 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
343 //===----------------------------------------------------------------------===//
345 //===----------------------------------------------------------------------===//
348 let neverHasSideEffects = 1 in
349 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
350 "movss\t{$src, $dst|$dst, $src}", []>;
351 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
352 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
353 "movss\t{$src, $dst|$dst, $src}",
354 [(set FR32:$dst, (loadf32 addr:$src))]>;
355 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
356 "movss\t{$src, $dst|$dst, $src}",
357 [(store FR32:$src, addr:$dst)]>;
359 // Conversion instructions
360 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
361 "cvttss2si\t{$src, $dst|$dst, $src}",
362 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
363 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
364 "cvttss2si\t{$src, $dst|$dst, $src}",
365 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
366 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
367 "cvtsi2ss\t{$src, $dst|$dst, $src}",
368 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
369 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
370 "cvtsi2ss\t{$src, $dst|$dst, $src}",
371 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
373 // Match intrinsics which expect XMM operand(s).
374 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
375 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
376 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
377 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
379 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
380 "cvtss2si\t{$src, $dst|$dst, $src}",
381 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
382 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
383 "cvtss2si\t{$src, $dst|$dst, $src}",
384 [(set GR32:$dst, (int_x86_sse_cvtss2si
385 (load addr:$src)))]>;
387 // Match intrinisics which expect MM and XMM operand(s).
388 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
389 "cvtps2pi\t{$src, $dst|$dst, $src}",
390 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
391 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
392 "cvtps2pi\t{$src, $dst|$dst, $src}",
393 [(set VR64:$dst, (int_x86_sse_cvtps2pi
394 (load addr:$src)))]>;
395 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
396 "cvttps2pi\t{$src, $dst|$dst, $src}",
397 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
398 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
399 "cvttps2pi\t{$src, $dst|$dst, $src}",
400 [(set VR64:$dst, (int_x86_sse_cvttps2pi
401 (load addr:$src)))]>;
402 let Constraints = "$src1 = $dst" in {
403 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
404 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
405 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
406 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
408 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
409 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
410 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
411 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
412 (load addr:$src2)))]>;
415 // Aliases for intrinsics
416 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
417 "cvttss2si\t{$src, $dst|$dst, $src}",
419 (int_x86_sse_cvttss2si VR128:$src))]>;
420 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
421 "cvttss2si\t{$src, $dst|$dst, $src}",
423 (int_x86_sse_cvttss2si(load addr:$src)))]>;
425 let Constraints = "$src1 = $dst" in {
426 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
427 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
428 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
429 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
431 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
432 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
433 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
434 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
435 (loadi32 addr:$src2)))]>;
438 // Comparison instructions
439 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
440 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
441 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
442 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
444 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
445 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
446 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
449 let Defs = [EFLAGS] in {
450 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
451 "ucomiss\t{$src2, $src1|$src1, $src2}",
452 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
453 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
454 "ucomiss\t{$src2, $src1|$src1, $src2}",
455 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
458 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
459 "comiss\t{$src2, $src1|$src1, $src2}", []>;
460 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
461 "comiss\t{$src2, $src1|$src1, $src2}", []>;
465 // Aliases to match intrinsics which expect XMM operand(s).
466 let Constraints = "$src1 = $dst" in {
467 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
469 (ins VR128:$src1, VR128:$src, SSECC:$cc),
470 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
471 [(set VR128:$dst, (int_x86_sse_cmp_ss
473 VR128:$src, imm:$cc))]>;
474 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
476 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
477 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
478 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
479 (load addr:$src), imm:$cc))]>;
482 let Defs = [EFLAGS] in {
483 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
484 "ucomiss\t{$src2, $src1|$src1, $src2}",
485 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
487 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
488 "ucomiss\t{$src2, $src1|$src1, $src2}",
489 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
492 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
493 "comiss\t{$src2, $src1|$src1, $src2}",
494 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
496 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
497 "comiss\t{$src2, $src1|$src1, $src2}",
498 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
502 // Aliases of packed SSE1 instructions for scalar use. These all have names
503 // that start with 'Fs'.
505 // Alias instructions that map fld0 to pxor for sse.
506 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
508 // FIXME: Set encoding to pseudo!
509 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
510 [(set FR32:$dst, fp32imm0)]>,
511 Requires<[HasSSE1]>, TB, OpSize;
513 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
515 let neverHasSideEffects = 1 in
516 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
517 "movaps\t{$src, $dst|$dst, $src}", []>;
519 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
521 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
522 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
523 "movaps\t{$src, $dst|$dst, $src}",
524 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
526 // Alias bitwise logical operations using SSE logical ops on packed FP values.
527 let Constraints = "$src1 = $dst" in {
528 let isCommutable = 1 in {
529 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
530 (ins FR32:$src1, FR32:$src2),
531 "andps\t{$src2, $dst|$dst, $src2}",
532 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
533 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
534 (ins FR32:$src1, FR32:$src2),
535 "orps\t{$src2, $dst|$dst, $src2}",
536 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
537 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
538 (ins FR32:$src1, FR32:$src2),
539 "xorps\t{$src2, $dst|$dst, $src2}",
540 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
543 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
544 (ins FR32:$src1, f128mem:$src2),
545 "andps\t{$src2, $dst|$dst, $src2}",
546 [(set FR32:$dst, (X86fand FR32:$src1,
547 (memopfsf32 addr:$src2)))]>;
548 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
549 (ins FR32:$src1, f128mem:$src2),
550 "orps\t{$src2, $dst|$dst, $src2}",
551 [(set FR32:$dst, (X86for FR32:$src1,
552 (memopfsf32 addr:$src2)))]>;
553 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
554 (ins FR32:$src1, f128mem:$src2),
555 "xorps\t{$src2, $dst|$dst, $src2}",
556 [(set FR32:$dst, (X86fxor FR32:$src1,
557 (memopfsf32 addr:$src2)))]>;
559 let neverHasSideEffects = 1 in {
560 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
561 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
562 "andnps\t{$src2, $dst|$dst, $src2}", []>;
564 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
565 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
566 "andnps\t{$src2, $dst|$dst, $src2}", []>;
570 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
572 /// In addition, we also have a special variant of the scalar form here to
573 /// represent the associated intrinsic operation. This form is unlike the
574 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
575 /// and leaves the top elements unmodified (therefore these cannot be commuted).
577 /// These three forms can each be reg+reg or reg+mem, so there are a total of
578 /// six "instructions".
580 let Constraints = "$src1 = $dst" in {
581 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
582 SDNode OpNode, Intrinsic F32Int,
583 bit Commutable = 0> {
584 // Scalar operation, reg+reg.
585 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
586 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
587 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
588 let isCommutable = Commutable;
591 // Scalar operation, reg+mem.
592 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
593 (ins FR32:$src1, f32mem:$src2),
594 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
595 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
597 // Vector operation, reg+reg.
598 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
599 (ins VR128:$src1, VR128:$src2),
600 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
601 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
602 let isCommutable = Commutable;
605 // Vector operation, reg+mem.
606 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
607 (ins VR128:$src1, f128mem:$src2),
608 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
609 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
611 // Intrinsic operation, reg+reg.
612 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
613 (ins VR128:$src1, VR128:$src2),
614 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
615 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
617 // Intrinsic operation, reg+mem.
618 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
619 (ins VR128:$src1, ssmem:$src2),
620 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
621 [(set VR128:$dst, (F32Int VR128:$src1,
622 sse_load_f32:$src2))]>;
626 // Arithmetic instructions
627 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
628 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
629 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
630 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
632 /// sse1_fp_binop_rm - Other SSE1 binops
634 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
635 /// instructions for a full-vector intrinsic form. Operations that map
636 /// onto C operators don't use this form since they just use the plain
637 /// vector form instead of having a separate vector intrinsic form.
639 /// This provides a total of eight "instructions".
641 let Constraints = "$src1 = $dst" in {
642 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
646 bit Commutable = 0> {
648 // Scalar operation, reg+reg.
649 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
652 let isCommutable = Commutable;
655 // Scalar operation, reg+mem.
656 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
657 (ins FR32:$src1, f32mem:$src2),
658 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
659 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
661 // Vector operation, reg+reg.
662 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
663 (ins VR128:$src1, VR128:$src2),
664 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
665 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
666 let isCommutable = Commutable;
669 // Vector operation, reg+mem.
670 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
671 (ins VR128:$src1, f128mem:$src2),
672 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
673 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
675 // Intrinsic operation, reg+reg.
676 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
677 (ins VR128:$src1, VR128:$src2),
678 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
680 let isCommutable = Commutable;
683 // Intrinsic operation, reg+mem.
684 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
685 (ins VR128:$src1, ssmem:$src2),
686 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
687 [(set VR128:$dst, (F32Int VR128:$src1,
688 sse_load_f32:$src2))]>;
690 // Vector intrinsic operation, reg+reg.
691 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
692 (ins VR128:$src1, VR128:$src2),
693 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
694 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
695 let isCommutable = Commutable;
698 // Vector intrinsic operation, reg+mem.
699 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
700 (ins VR128:$src1, f128mem:$src2),
701 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
702 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
706 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
707 int_x86_sse_max_ss, int_x86_sse_max_ps>;
708 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
709 int_x86_sse_min_ss, int_x86_sse_min_ps>;
711 //===----------------------------------------------------------------------===//
712 // SSE packed FP Instructions
715 let neverHasSideEffects = 1 in
716 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
717 "movaps\t{$src, $dst|$dst, $src}", []>;
718 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
719 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
720 "movaps\t{$src, $dst|$dst, $src}",
721 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
723 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
724 "movaps\t{$src, $dst|$dst, $src}",
725 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
727 let neverHasSideEffects = 1 in
728 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
729 "movups\t{$src, $dst|$dst, $src}", []>;
730 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
731 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
732 "movups\t{$src, $dst|$dst, $src}",
733 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
734 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
735 "movups\t{$src, $dst|$dst, $src}",
736 [(store (v4f32 VR128:$src), addr:$dst)]>;
738 // Intrinsic forms of MOVUPS load and store
739 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
740 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
741 "movups\t{$src, $dst|$dst, $src}",
742 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
743 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
744 "movups\t{$src, $dst|$dst, $src}",
745 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
747 let Constraints = "$src1 = $dst" in {
748 let AddedComplexity = 20 in {
749 def MOVLPSrm : PSI<0x12, MRMSrcMem,
750 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
751 "movlps\t{$src2, $dst|$dst, $src2}",
754 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
755 def MOVHPSrm : PSI<0x16, MRMSrcMem,
756 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
757 "movhps\t{$src2, $dst|$dst, $src2}",
759 (movlhps VR128:$src1,
760 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
762 } // Constraints = "$src1 = $dst"
765 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
766 (MOVHPSrm VR128:$src1, addr:$src2)>;
768 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
769 "movlps\t{$src, $dst|$dst, $src}",
770 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
771 (iPTR 0))), addr:$dst)]>;
773 // v2f64 extract element 1 is always custom lowered to unpack high to low
774 // and extract element 0 so the non-store version isn't too horrible.
775 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
776 "movhps\t{$src, $dst|$dst, $src}",
777 [(store (f64 (vector_extract
778 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
779 (undef)), (iPTR 0))), addr:$dst)]>;
781 let Constraints = "$src1 = $dst" in {
782 let AddedComplexity = 20 in {
783 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
784 (ins VR128:$src1, VR128:$src2),
785 "movlhps\t{$src2, $dst|$dst, $src2}",
787 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
789 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
790 (ins VR128:$src1, VR128:$src2),
791 "movhlps\t{$src2, $dst|$dst, $src2}",
793 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
795 } // Constraints = "$src1 = $dst"
797 let AddedComplexity = 20 in {
798 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
799 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
800 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
801 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
808 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
810 /// In addition, we also have a special variant of the scalar form here to
811 /// represent the associated intrinsic operation. This form is unlike the
812 /// plain scalar form, in that it takes an entire vector (instead of a
813 /// scalar) and leaves the top elements undefined.
815 /// And, we have a special variant form for a full-vector intrinsic form.
817 /// These four forms can each have a reg or a mem operand, so there are a
818 /// total of eight "instructions".
820 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
824 bit Commutable = 0> {
825 // Scalar operation, reg.
826 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
827 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
828 [(set FR32:$dst, (OpNode FR32:$src))]> {
829 let isCommutable = Commutable;
832 // Scalar operation, mem.
833 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
834 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
835 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
836 Requires<[HasSSE1, OptForSize]>;
838 // Vector operation, reg.
839 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
840 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
841 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
842 let isCommutable = Commutable;
845 // Vector operation, mem.
846 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
847 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
848 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
850 // Intrinsic operation, reg.
851 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
852 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
853 [(set VR128:$dst, (F32Int VR128:$src))]> {
854 let isCommutable = Commutable;
857 // Intrinsic operation, mem.
858 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
859 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
860 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
862 // Vector intrinsic operation, reg
863 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
864 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
865 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
866 let isCommutable = Commutable;
869 // Vector intrinsic operation, mem
870 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
871 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
872 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
876 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
877 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
879 // Reciprocal approximations. Note that these typically require refinement
880 // in order to obtain suitable precision.
881 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
882 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
883 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
884 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
887 let Constraints = "$src1 = $dst" in {
888 let isCommutable = 1 in {
889 def ANDPSrr : PSI<0x54, MRMSrcReg,
890 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
891 "andps\t{$src2, $dst|$dst, $src2}",
892 [(set VR128:$dst, (v2i64
893 (and VR128:$src1, VR128:$src2)))]>;
894 def ORPSrr : PSI<0x56, MRMSrcReg,
895 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
896 "orps\t{$src2, $dst|$dst, $src2}",
897 [(set VR128:$dst, (v2i64
898 (or VR128:$src1, VR128:$src2)))]>;
899 def XORPSrr : PSI<0x57, MRMSrcReg,
900 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
901 "xorps\t{$src2, $dst|$dst, $src2}",
902 [(set VR128:$dst, (v2i64
903 (xor VR128:$src1, VR128:$src2)))]>;
906 def ANDPSrm : PSI<0x54, MRMSrcMem,
907 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
908 "andps\t{$src2, $dst|$dst, $src2}",
909 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
910 (memopv2i64 addr:$src2)))]>;
911 def ORPSrm : PSI<0x56, MRMSrcMem,
912 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
913 "orps\t{$src2, $dst|$dst, $src2}",
914 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
915 (memopv2i64 addr:$src2)))]>;
916 def XORPSrm : PSI<0x57, MRMSrcMem,
917 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
918 "xorps\t{$src2, $dst|$dst, $src2}",
919 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
920 (memopv2i64 addr:$src2)))]>;
921 def ANDNPSrr : PSI<0x55, MRMSrcReg,
922 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
923 "andnps\t{$src2, $dst|$dst, $src2}",
925 (v2i64 (and (xor VR128:$src1,
926 (bc_v2i64 (v4i32 immAllOnesV))),
928 def ANDNPSrm : PSI<0x55, MRMSrcMem,
929 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
930 "andnps\t{$src2, $dst|$dst, $src2}",
932 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
933 (bc_v2i64 (v4i32 immAllOnesV))),
934 (memopv2i64 addr:$src2))))]>;
937 let Constraints = "$src1 = $dst" in {
938 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
939 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
940 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
941 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
942 VR128:$src, imm:$cc))]>;
943 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
944 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
945 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
946 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
947 (memop addr:$src), imm:$cc))]>;
949 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
950 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
951 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
952 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
954 // Shuffle and unpack instructions
955 let Constraints = "$src1 = $dst" in {
956 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
957 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
958 (outs VR128:$dst), (ins VR128:$src1,
959 VR128:$src2, i8imm:$src3),
960 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
962 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
963 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
964 (outs VR128:$dst), (ins VR128:$src1,
965 f128mem:$src2, i8imm:$src3),
966 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
969 VR128:$src1, (memopv4f32 addr:$src2))))]>;
971 let AddedComplexity = 10 in {
972 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
973 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
974 "unpckhps\t{$src2, $dst|$dst, $src2}",
976 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
977 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
978 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
979 "unpckhps\t{$src2, $dst|$dst, $src2}",
981 (v4f32 (unpckh VR128:$src1,
982 (memopv4f32 addr:$src2))))]>;
984 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
985 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
986 "unpcklps\t{$src2, $dst|$dst, $src2}",
988 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
989 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
990 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
991 "unpcklps\t{$src2, $dst|$dst, $src2}",
993 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
995 } // Constraints = "$src1 = $dst"
998 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
999 "movmskps\t{$src, $dst|$dst, $src}",
1000 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1001 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1002 "movmskpd\t{$src, $dst|$dst, $src}",
1003 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1005 // Prefetch intrinsic.
1006 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1007 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1008 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1009 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1010 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1011 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1012 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1013 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1015 // Non-temporal stores
1016 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1017 "movntps\t{$src, $dst|$dst, $src}",
1018 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1020 // Load, store, and memory fence
1021 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1024 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1025 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1026 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1027 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1029 // Alias instructions that map zero vector to pxor / xorp* for sse.
1030 // We set canFoldAsLoad because this can be converted to a constant-pool
1031 // load of an all-zeros value if folding it would be beneficial.
1032 // FIXME: Change encoding to pseudo!
1033 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1034 isCodeGenOnly = 1 in
1035 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1036 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1038 let Predicates = [HasSSE1] in {
1039 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1040 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1041 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1042 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1043 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1046 // FR32 to 128-bit vector conversion.
1047 let isAsCheapAsAMove = 1 in
1048 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1049 "movss\t{$src, $dst|$dst, $src}",
1051 (v4f32 (scalar_to_vector FR32:$src)))]>;
1052 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1053 "movss\t{$src, $dst|$dst, $src}",
1055 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1057 // FIXME: may not be able to eliminate this movss with coalescing the src and
1058 // dest register classes are different. We really want to write this pattern
1060 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1061 // (f32 FR32:$src)>;
1062 let isAsCheapAsAMove = 1 in
1063 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1064 "movss\t{$src, $dst|$dst, $src}",
1065 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1067 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1068 "movss\t{$src, $dst|$dst, $src}",
1069 [(store (f32 (vector_extract (v4f32 VR128:$src),
1070 (iPTR 0))), addr:$dst)]>;
1073 // Move to lower bits of a VR128, leaving upper bits alone.
1074 // Three operand (but two address) aliases.
1075 let Constraints = "$src1 = $dst" in {
1076 let neverHasSideEffects = 1 in
1077 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1078 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1079 "movss\t{$src2, $dst|$dst, $src2}", []>;
1081 let AddedComplexity = 15 in
1082 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1083 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1084 "movss\t{$src2, $dst|$dst, $src2}",
1086 (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
1089 // Move to lower bits of a VR128 and zeroing upper bits.
1090 // Loading from memory automatically zeroing upper bits.
1091 let AddedComplexity = 20 in
1092 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1093 "movss\t{$src, $dst|$dst, $src}",
1094 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1095 (loadf32 addr:$src))))))]>;
1097 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1098 (MOVZSS2PSrm addr:$src)>;
1100 //===---------------------------------------------------------------------===//
1101 // SSE2 Instructions
1102 //===---------------------------------------------------------------------===//
1104 // Move Instructions
1105 let neverHasSideEffects = 1 in
1106 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1107 "movsd\t{$src, $dst|$dst, $src}", []>;
1108 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1109 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1110 "movsd\t{$src, $dst|$dst, $src}",
1111 [(set FR64:$dst, (loadf64 addr:$src))]>;
1112 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1113 "movsd\t{$src, $dst|$dst, $src}",
1114 [(store FR64:$src, addr:$dst)]>;
1116 // Conversion instructions
1117 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1118 "cvttsd2si\t{$src, $dst|$dst, $src}",
1119 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1120 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1121 "cvttsd2si\t{$src, $dst|$dst, $src}",
1122 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1123 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1124 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1125 [(set FR32:$dst, (fround FR64:$src))]>;
1126 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1127 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1128 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1129 Requires<[HasSSE2, OptForSize]>;
1130 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1131 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1132 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1133 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1134 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1135 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1137 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1138 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1139 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1140 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1141 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1142 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1143 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1144 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1145 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1146 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1147 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1148 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1149 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1150 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1151 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1152 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1153 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1154 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1155 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1156 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1158 // SSE2 instructions with XS prefix
1159 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1160 "cvtss2sd\t{$src, $dst|$dst, $src}",
1161 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1162 Requires<[HasSSE2]>;
1163 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1164 "cvtss2sd\t{$src, $dst|$dst, $src}",
1165 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1166 Requires<[HasSSE2, OptForSize]>;
1168 def : Pat<(extloadf32 addr:$src),
1169 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1171 // Match intrinsics which expect XMM operand(s).
1172 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1173 "cvtsd2si\t{$src, $dst|$dst, $src}",
1174 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1175 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1176 "cvtsd2si\t{$src, $dst|$dst, $src}",
1177 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1178 (load addr:$src)))]>;
1180 // Match intrinisics which expect MM and XMM operand(s).
1181 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1182 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1183 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1184 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1185 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1186 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1187 (memop addr:$src)))]>;
1188 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1189 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1190 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1191 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1192 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1193 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1194 (memop addr:$src)))]>;
1195 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1196 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1197 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1198 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1199 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1200 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1201 (load addr:$src)))]>;
1203 // Aliases for intrinsics
1204 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1205 "cvttsd2si\t{$src, $dst|$dst, $src}",
1207 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1208 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1209 "cvttsd2si\t{$src, $dst|$dst, $src}",
1210 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1211 (load addr:$src)))]>;
1213 // Comparison instructions
1214 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1215 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1216 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1217 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1219 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1220 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1221 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1224 let Defs = [EFLAGS] in {
1225 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1226 "ucomisd\t{$src2, $src1|$src1, $src2}",
1227 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1228 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1229 "ucomisd\t{$src2, $src1|$src1, $src2}",
1230 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1231 (implicit EFLAGS)]>;
1232 } // Defs = [EFLAGS]
1234 // Aliases to match intrinsics which expect XMM operand(s).
1235 let Constraints = "$src1 = $dst" in {
1236 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1238 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1239 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1240 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1241 VR128:$src, imm:$cc))]>;
1242 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1244 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1245 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1246 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1247 (load addr:$src), imm:$cc))]>;
1250 let Defs = [EFLAGS] in {
1251 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1252 "ucomisd\t{$src2, $src1|$src1, $src2}",
1253 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1254 (implicit EFLAGS)]>;
1255 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1256 "ucomisd\t{$src2, $src1|$src1, $src2}",
1257 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1258 (implicit EFLAGS)]>;
1260 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1261 "comisd\t{$src2, $src1|$src1, $src2}",
1262 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1263 (implicit EFLAGS)]>;
1264 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1265 "comisd\t{$src2, $src1|$src1, $src2}",
1266 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1267 (implicit EFLAGS)]>;
1268 } // Defs = [EFLAGS]
1270 // Aliases of packed SSE2 instructions for scalar use. These all have names
1271 // that start with 'Fs'.
1273 // Alias instructions that map fld0 to pxor for sse.
1274 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1275 canFoldAsLoad = 1 in
1276 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1277 [(set FR64:$dst, fpimm0)]>,
1278 Requires<[HasSSE2]>, TB, OpSize;
1280 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1282 let neverHasSideEffects = 1 in
1283 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1284 "movapd\t{$src, $dst|$dst, $src}", []>;
1286 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1288 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1289 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1290 "movapd\t{$src, $dst|$dst, $src}",
1291 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1293 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1294 let Constraints = "$src1 = $dst" in {
1295 let isCommutable = 1 in {
1296 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1297 (ins FR64:$src1, FR64:$src2),
1298 "andpd\t{$src2, $dst|$dst, $src2}",
1299 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1300 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1301 (ins FR64:$src1, FR64:$src2),
1302 "orpd\t{$src2, $dst|$dst, $src2}",
1303 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1304 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1305 (ins FR64:$src1, FR64:$src2),
1306 "xorpd\t{$src2, $dst|$dst, $src2}",
1307 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1310 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1311 (ins FR64:$src1, f128mem:$src2),
1312 "andpd\t{$src2, $dst|$dst, $src2}",
1313 [(set FR64:$dst, (X86fand FR64:$src1,
1314 (memopfsf64 addr:$src2)))]>;
1315 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1316 (ins FR64:$src1, f128mem:$src2),
1317 "orpd\t{$src2, $dst|$dst, $src2}",
1318 [(set FR64:$dst, (X86for FR64:$src1,
1319 (memopfsf64 addr:$src2)))]>;
1320 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1321 (ins FR64:$src1, f128mem:$src2),
1322 "xorpd\t{$src2, $dst|$dst, $src2}",
1323 [(set FR64:$dst, (X86fxor FR64:$src1,
1324 (memopfsf64 addr:$src2)))]>;
1326 let neverHasSideEffects = 1 in {
1327 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1328 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1329 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1331 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1332 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1333 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1337 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1339 /// In addition, we also have a special variant of the scalar form here to
1340 /// represent the associated intrinsic operation. This form is unlike the
1341 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1342 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1344 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1345 /// six "instructions".
1347 let Constraints = "$src1 = $dst" in {
1348 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1349 SDNode OpNode, Intrinsic F64Int,
1350 bit Commutable = 0> {
1351 // Scalar operation, reg+reg.
1352 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1353 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1354 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1355 let isCommutable = Commutable;
1358 // Scalar operation, reg+mem.
1359 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1360 (ins FR64:$src1, f64mem:$src2),
1361 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1362 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1364 // Vector operation, reg+reg.
1365 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1366 (ins VR128:$src1, VR128:$src2),
1367 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1368 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1369 let isCommutable = Commutable;
1372 // Vector operation, reg+mem.
1373 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1374 (ins VR128:$src1, f128mem:$src2),
1375 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1376 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1378 // Intrinsic operation, reg+reg.
1379 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1380 (ins VR128:$src1, VR128:$src2),
1381 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1382 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1384 // Intrinsic operation, reg+mem.
1385 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1386 (ins VR128:$src1, sdmem:$src2),
1387 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1388 [(set VR128:$dst, (F64Int VR128:$src1,
1389 sse_load_f64:$src2))]>;
1393 // Arithmetic instructions
1394 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1395 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1396 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1397 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1399 /// sse2_fp_binop_rm - Other SSE2 binops
1401 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1402 /// instructions for a full-vector intrinsic form. Operations that map
1403 /// onto C operators don't use this form since they just use the plain
1404 /// vector form instead of having a separate vector intrinsic form.
1406 /// This provides a total of eight "instructions".
1408 let Constraints = "$src1 = $dst" in {
1409 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1413 bit Commutable = 0> {
1415 // Scalar operation, reg+reg.
1416 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1417 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1418 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1419 let isCommutable = Commutable;
1422 // Scalar operation, reg+mem.
1423 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1424 (ins FR64:$src1, f64mem:$src2),
1425 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1426 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1428 // Vector operation, reg+reg.
1429 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1430 (ins VR128:$src1, VR128:$src2),
1431 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1432 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1433 let isCommutable = Commutable;
1436 // Vector operation, reg+mem.
1437 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1438 (ins VR128:$src1, f128mem:$src2),
1439 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1440 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1442 // Intrinsic operation, reg+reg.
1443 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1444 (ins VR128:$src1, VR128:$src2),
1445 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1446 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1447 let isCommutable = Commutable;
1450 // Intrinsic operation, reg+mem.
1451 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1452 (ins VR128:$src1, sdmem:$src2),
1453 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1454 [(set VR128:$dst, (F64Int VR128:$src1,
1455 sse_load_f64:$src2))]>;
1457 // Vector intrinsic operation, reg+reg.
1458 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1459 (ins VR128:$src1, VR128:$src2),
1460 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1461 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1462 let isCommutable = Commutable;
1465 // Vector intrinsic operation, reg+mem.
1466 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1467 (ins VR128:$src1, f128mem:$src2),
1468 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1469 [(set VR128:$dst, (V2F64Int VR128:$src1,
1470 (memopv2f64 addr:$src2)))]>;
1474 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1475 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1476 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1477 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1479 //===---------------------------------------------------------------------===//
1480 // SSE packed FP Instructions
1482 // Move Instructions
1483 let neverHasSideEffects = 1 in
1484 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1485 "movapd\t{$src, $dst|$dst, $src}", []>;
1486 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1487 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1488 "movapd\t{$src, $dst|$dst, $src}",
1489 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1491 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1492 "movapd\t{$src, $dst|$dst, $src}",
1493 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1495 let neverHasSideEffects = 1 in
1496 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1497 "movupd\t{$src, $dst|$dst, $src}", []>;
1498 let canFoldAsLoad = 1 in
1499 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1500 "movupd\t{$src, $dst|$dst, $src}",
1501 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1502 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1503 "movupd\t{$src, $dst|$dst, $src}",
1504 [(store (v2f64 VR128:$src), addr:$dst)]>;
1506 // Intrinsic forms of MOVUPD load and store
1507 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1508 "movupd\t{$src, $dst|$dst, $src}",
1509 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1510 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1511 "movupd\t{$src, $dst|$dst, $src}",
1512 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1514 let Constraints = "$src1 = $dst" in {
1515 let AddedComplexity = 20 in {
1516 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1517 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1518 "movlpd\t{$src2, $dst|$dst, $src2}",
1520 (v2f64 (movlp VR128:$src1,
1521 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1522 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1523 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1524 "movhpd\t{$src2, $dst|$dst, $src2}",
1526 (v2f64 (movlhps VR128:$src1,
1527 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1528 } // AddedComplexity
1529 } // Constraints = "$src1 = $dst"
1531 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1532 "movlpd\t{$src, $dst|$dst, $src}",
1533 [(store (f64 (vector_extract (v2f64 VR128:$src),
1534 (iPTR 0))), addr:$dst)]>;
1536 // v2f64 extract element 1 is always custom lowered to unpack high to low
1537 // and extract element 0 so the non-store version isn't too horrible.
1538 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1539 "movhpd\t{$src, $dst|$dst, $src}",
1540 [(store (f64 (vector_extract
1541 (v2f64 (unpckh VR128:$src, (undef))),
1542 (iPTR 0))), addr:$dst)]>;
1544 // SSE2 instructions without OpSize prefix
1545 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1546 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1547 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1548 TB, Requires<[HasSSE2]>;
1549 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1550 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1551 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1552 (bitconvert (memopv2i64 addr:$src))))]>,
1553 TB, Requires<[HasSSE2]>;
1555 // SSE2 instructions with XS prefix
1556 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1557 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1558 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1559 XS, Requires<[HasSSE2]>;
1560 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1561 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1562 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1563 (bitconvert (memopv2i64 addr:$src))))]>,
1564 XS, Requires<[HasSSE2]>;
1566 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1567 "cvtps2dq\t{$src, $dst|$dst, $src}",
1568 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1569 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1570 "cvtps2dq\t{$src, $dst|$dst, $src}",
1571 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1572 (memop addr:$src)))]>;
1573 // SSE2 packed instructions with XS prefix
1574 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1575 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1576 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1577 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1579 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1580 "cvttps2dq\t{$src, $dst|$dst, $src}",
1582 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1583 XS, Requires<[HasSSE2]>;
1584 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1585 "cvttps2dq\t{$src, $dst|$dst, $src}",
1586 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1587 (memop addr:$src)))]>,
1588 XS, Requires<[HasSSE2]>;
1590 // SSE2 packed instructions with XD prefix
1591 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1592 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1593 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1594 XD, Requires<[HasSSE2]>;
1595 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1596 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1597 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1598 (memop addr:$src)))]>,
1599 XD, Requires<[HasSSE2]>;
1601 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1602 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1603 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1604 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1605 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1606 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1607 (memop addr:$src)))]>;
1609 // SSE2 instructions without OpSize prefix
1610 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1611 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1612 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1613 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1615 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1616 "cvtps2pd\t{$src, $dst|$dst, $src}",
1617 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1618 TB, Requires<[HasSSE2]>;
1619 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1620 "cvtps2pd\t{$src, $dst|$dst, $src}",
1621 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1622 (load addr:$src)))]>,
1623 TB, Requires<[HasSSE2]>;
1625 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1626 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1627 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1628 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1631 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1633 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1634 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1637 (memop addr:$src)))]>;
1639 // Match intrinsics which expect XMM operand(s).
1640 // Aliases for intrinsics
1641 let Constraints = "$src1 = $dst" in {
1642 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1643 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1644 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1645 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1647 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1648 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1649 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1650 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1651 (loadi32 addr:$src2)))]>;
1652 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1653 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1654 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1655 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1657 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1658 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1659 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1660 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1661 (load addr:$src2)))]>;
1662 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1663 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1664 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1665 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1666 VR128:$src2))]>, XS,
1667 Requires<[HasSSE2]>;
1668 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1669 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1670 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1672 (load addr:$src2)))]>, XS,
1673 Requires<[HasSSE2]>;
1678 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1680 /// In addition, we also have a special variant of the scalar form here to
1681 /// represent the associated intrinsic operation. This form is unlike the
1682 /// plain scalar form, in that it takes an entire vector (instead of a
1683 /// scalar) and leaves the top elements undefined.
1685 /// And, we have a special variant form for a full-vector intrinsic form.
1687 /// These four forms can each have a reg or a mem operand, so there are a
1688 /// total of eight "instructions".
1690 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1694 bit Commutable = 0> {
1695 // Scalar operation, reg.
1696 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1697 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1698 [(set FR64:$dst, (OpNode FR64:$src))]> {
1699 let isCommutable = Commutable;
1702 // Scalar operation, mem.
1703 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1704 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1705 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1707 // Vector operation, reg.
1708 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1709 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1710 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1711 let isCommutable = Commutable;
1714 // Vector operation, mem.
1715 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1716 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1717 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1719 // Intrinsic operation, reg.
1720 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1721 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1722 [(set VR128:$dst, (F64Int VR128:$src))]> {
1723 let isCommutable = Commutable;
1726 // Intrinsic operation, mem.
1727 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1728 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1729 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1731 // Vector intrinsic operation, reg
1732 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1733 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1734 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1735 let isCommutable = Commutable;
1738 // Vector intrinsic operation, mem
1739 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1740 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1741 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1745 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1746 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1748 // There is no f64 version of the reciprocal approximation instructions.
1751 let Constraints = "$src1 = $dst" in {
1752 let isCommutable = 1 in {
1753 def ANDPDrr : PDI<0x54, MRMSrcReg,
1754 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1755 "andpd\t{$src2, $dst|$dst, $src2}",
1757 (and (bc_v2i64 (v2f64 VR128:$src1)),
1758 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1759 def ORPDrr : PDI<0x56, MRMSrcReg,
1760 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1761 "orpd\t{$src2, $dst|$dst, $src2}",
1763 (or (bc_v2i64 (v2f64 VR128:$src1)),
1764 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1765 def XORPDrr : PDI<0x57, MRMSrcReg,
1766 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1767 "xorpd\t{$src2, $dst|$dst, $src2}",
1769 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1770 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1773 def ANDPDrm : PDI<0x54, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1775 "andpd\t{$src2, $dst|$dst, $src2}",
1777 (and (bc_v2i64 (v2f64 VR128:$src1)),
1778 (memopv2i64 addr:$src2)))]>;
1779 def ORPDrm : PDI<0x56, MRMSrcMem,
1780 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1781 "orpd\t{$src2, $dst|$dst, $src2}",
1783 (or (bc_v2i64 (v2f64 VR128:$src1)),
1784 (memopv2i64 addr:$src2)))]>;
1785 def XORPDrm : PDI<0x57, MRMSrcMem,
1786 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1787 "xorpd\t{$src2, $dst|$dst, $src2}",
1789 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1790 (memopv2i64 addr:$src2)))]>;
1791 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1792 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1793 "andnpd\t{$src2, $dst|$dst, $src2}",
1795 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1796 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1797 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1798 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1799 "andnpd\t{$src2, $dst|$dst, $src2}",
1801 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1802 (memopv2i64 addr:$src2)))]>;
1805 let Constraints = "$src1 = $dst" in {
1806 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1807 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1808 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1809 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1810 VR128:$src, imm:$cc))]>;
1811 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1812 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1813 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1815 (memop addr:$src), imm:$cc))]>;
1817 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1818 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1819 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1820 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1822 // Shuffle and unpack instructions
1823 let Constraints = "$src1 = $dst" in {
1824 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1825 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1826 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1828 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1829 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1830 (outs VR128:$dst), (ins VR128:$src1,
1831 f128mem:$src2, i8imm:$src3),
1832 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1835 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1837 let AddedComplexity = 10 in {
1838 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1839 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1842 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1843 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1844 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1845 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1847 (v2f64 (unpckh VR128:$src1,
1848 (memopv2f64 addr:$src2))))]>;
1850 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1851 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1852 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1854 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1855 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1856 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1857 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1859 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1860 } // AddedComplexity
1861 } // Constraints = "$src1 = $dst"
1864 //===---------------------------------------------------------------------===//
1865 // SSE integer instructions
1867 // Move Instructions
1868 let neverHasSideEffects = 1 in
1869 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1870 "movdqa\t{$src, $dst|$dst, $src}", []>;
1871 let canFoldAsLoad = 1, mayLoad = 1 in
1872 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1873 "movdqa\t{$src, $dst|$dst, $src}",
1874 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1876 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1877 "movdqa\t{$src, $dst|$dst, $src}",
1878 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1879 let canFoldAsLoad = 1, mayLoad = 1 in
1880 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1881 "movdqu\t{$src, $dst|$dst, $src}",
1882 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1883 XS, Requires<[HasSSE2]>;
1885 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1886 "movdqu\t{$src, $dst|$dst, $src}",
1887 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1888 XS, Requires<[HasSSE2]>;
1890 // Intrinsic forms of MOVDQU load and store
1891 let canFoldAsLoad = 1 in
1892 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1893 "movdqu\t{$src, $dst|$dst, $src}",
1894 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1895 XS, Requires<[HasSSE2]>;
1896 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1897 "movdqu\t{$src, $dst|$dst, $src}",
1898 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1899 XS, Requires<[HasSSE2]>;
1901 let Constraints = "$src1 = $dst" in {
1903 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1904 bit Commutable = 0> {
1905 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1906 (ins VR128:$src1, VR128:$src2),
1907 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1908 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1909 let isCommutable = Commutable;
1911 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1912 (ins VR128:$src1, i128mem:$src2),
1913 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1914 [(set VR128:$dst, (IntId VR128:$src1,
1915 (bitconvert (memopv2i64
1919 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1921 Intrinsic IntId, Intrinsic IntId2> {
1922 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1923 (ins VR128:$src1, VR128:$src2),
1924 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1925 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1926 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1927 (ins VR128:$src1, i128mem:$src2),
1928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1929 [(set VR128:$dst, (IntId VR128:$src1,
1930 (bitconvert (memopv2i64 addr:$src2))))]>;
1931 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1932 (ins VR128:$src1, i32i8imm:$src2),
1933 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1934 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1937 /// PDI_binop_rm - Simple SSE2 binary operator.
1938 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1939 ValueType OpVT, bit Commutable = 0> {
1940 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1941 (ins VR128:$src1, VR128:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1943 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1944 let isCommutable = Commutable;
1946 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1947 (ins VR128:$src1, i128mem:$src2),
1948 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1949 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1950 (bitconvert (memopv2i64 addr:$src2)))))]>;
1953 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1955 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1956 /// to collapse (bitconvert VT to VT) into its operand.
1958 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1959 bit Commutable = 0> {
1960 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1961 (ins VR128:$src1, VR128:$src2),
1962 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1963 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1964 let isCommutable = Commutable;
1966 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1967 (ins VR128:$src1, i128mem:$src2),
1968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1969 [(set VR128:$dst, (OpNode VR128:$src1,
1970 (memopv2i64 addr:$src2)))]>;
1973 } // Constraints = "$src1 = $dst"
1975 // 128-bit Integer Arithmetic
1977 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1978 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1979 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1980 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1982 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1983 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1984 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1985 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1987 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1988 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1989 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1990 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1992 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1993 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1994 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1995 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1997 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1999 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2000 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2001 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2003 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2005 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2006 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2009 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2010 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2011 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2012 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2013 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2016 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2017 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2018 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2019 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2020 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2021 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2023 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2024 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2025 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2026 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2027 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2028 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2030 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2031 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2032 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2033 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2035 // 128-bit logical shifts.
2036 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2037 def PSLLDQri : PDIi8<0x73, MRM7r,
2038 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2039 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2040 def PSRLDQri : PDIi8<0x73, MRM3r,
2041 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2042 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2043 // PSRADQri doesn't exist in SSE[1-3].
2046 let Predicates = [HasSSE2] in {
2047 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2048 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2049 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2050 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2051 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2052 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2053 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2054 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2055 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2056 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2058 // Shift up / down and insert zero's.
2059 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2060 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2061 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2062 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2066 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2067 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2068 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2070 let Constraints = "$src1 = $dst" in {
2071 def PANDNrr : PDI<0xDF, MRMSrcReg,
2072 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2073 "pandn\t{$src2, $dst|$dst, $src2}",
2074 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2077 def PANDNrm : PDI<0xDF, MRMSrcMem,
2078 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2079 "pandn\t{$src2, $dst|$dst, $src2}",
2080 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2081 (memopv2i64 addr:$src2))))]>;
2084 // SSE2 Integer comparison
2085 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2086 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2087 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2088 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2089 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2090 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2092 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2093 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2094 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2095 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2096 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2097 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2098 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2099 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2100 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2101 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2102 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2103 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2105 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2106 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2107 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2108 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2109 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2110 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2111 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2112 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2113 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2114 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2115 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2116 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2119 // Pack instructions
2120 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2121 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2122 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2124 // Shuffle and unpack instructions
2125 let AddedComplexity = 5 in {
2126 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2127 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2128 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2129 [(set VR128:$dst, (v4i32 (pshufd:$src2
2130 VR128:$src1, (undef))))]>;
2131 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2132 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2133 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2134 [(set VR128:$dst, (v4i32 (pshufd:$src2
2135 (bc_v4i32 (memopv2i64 addr:$src1)),
2139 // SSE2 with ImmT == Imm8 and XS prefix.
2140 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2141 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2142 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2143 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2145 XS, Requires<[HasSSE2]>;
2146 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2147 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2148 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2149 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2150 (bc_v8i16 (memopv2i64 addr:$src1)),
2152 XS, Requires<[HasSSE2]>;
2154 // SSE2 with ImmT == Imm8 and XD prefix.
2155 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2156 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2157 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2158 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2160 XD, Requires<[HasSSE2]>;
2161 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2162 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2163 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2164 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2165 (bc_v8i16 (memopv2i64 addr:$src1)),
2167 XD, Requires<[HasSSE2]>;
2170 let Constraints = "$src1 = $dst" in {
2171 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2173 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2175 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2176 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2177 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2178 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2180 (unpckl VR128:$src1,
2181 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2182 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2183 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2184 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2186 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2187 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2188 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2189 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2191 (unpckl VR128:$src1,
2192 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2193 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2194 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2195 "punpckldq\t{$src2, $dst|$dst, $src2}",
2197 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2198 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2199 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2200 "punpckldq\t{$src2, $dst|$dst, $src2}",
2202 (unpckl VR128:$src1,
2203 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2204 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2205 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2206 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2208 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2209 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2210 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2211 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2213 (v2i64 (unpckl VR128:$src1,
2214 (memopv2i64 addr:$src2))))]>;
2216 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2217 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2218 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2220 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2221 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2222 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2223 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2225 (unpckh VR128:$src1,
2226 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2227 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2228 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2229 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2231 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2232 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2233 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2234 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2236 (unpckh VR128:$src1,
2237 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2238 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2239 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2240 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2242 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2243 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2244 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2245 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2247 (unpckh VR128:$src1,
2248 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2249 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2250 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2251 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2253 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2254 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2255 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2256 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2258 (v2i64 (unpckh VR128:$src1,
2259 (memopv2i64 addr:$src2))))]>;
2263 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2264 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2265 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2266 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2268 let Constraints = "$src1 = $dst" in {
2269 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2270 (outs VR128:$dst), (ins VR128:$src1,
2271 GR32:$src2, i32i8imm:$src3),
2272 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2274 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2275 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2276 (outs VR128:$dst), (ins VR128:$src1,
2277 i16mem:$src2, i32i8imm:$src3),
2278 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2280 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2285 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2286 "pmovmskb\t{$src, $dst|$dst, $src}",
2287 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2289 // Conditional store
2291 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2292 "maskmovdqu\t{$mask, $src|$src, $mask}",
2293 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2296 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2297 "maskmovdqu\t{$mask, $src|$src, $mask}",
2298 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2300 // Non-temporal stores
2301 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2302 "movntpd\t{$src, $dst|$dst, $src}",
2303 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2304 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2305 "movntdq\t{$src, $dst|$dst, $src}",
2306 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2307 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2308 "movnti\t{$src, $dst|$dst, $src}",
2309 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2310 TB, Requires<[HasSSE2]>;
2313 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2314 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2315 TB, Requires<[HasSSE2]>;
2317 // Load, store, and memory fence
2318 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2319 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2320 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2321 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2323 //TODO: custom lower this so as to never even generate the noop
2324 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2326 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2327 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2328 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2331 // Alias instructions that map zero vector to pxor / xorp* for sse.
2332 // We set canFoldAsLoad because this can be converted to a constant-pool
2333 // load of an all-ones value if folding it would be beneficial.
2334 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2335 isCodeGenOnly = 1 in
2336 // FIXME: Change encoding to pseudo.
2337 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2338 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2340 // FR64 to 128-bit vector conversion.
2341 let isAsCheapAsAMove = 1 in
2342 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2343 "movsd\t{$src, $dst|$dst, $src}",
2345 (v2f64 (scalar_to_vector FR64:$src)))]>;
2346 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2347 "movsd\t{$src, $dst|$dst, $src}",
2349 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2351 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2352 "movd\t{$src, $dst|$dst, $src}",
2354 (v4i32 (scalar_to_vector GR32:$src)))]>;
2355 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2356 "movd\t{$src, $dst|$dst, $src}",
2358 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2360 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2361 "movd\t{$src, $dst|$dst, $src}",
2362 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2364 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2365 "movd\t{$src, $dst|$dst, $src}",
2366 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2368 // SSE2 instructions with XS prefix
2369 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2370 "movq\t{$src, $dst|$dst, $src}",
2372 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2373 Requires<[HasSSE2]>;
2374 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2375 "movq\t{$src, $dst|$dst, $src}",
2376 [(store (i64 (vector_extract (v2i64 VR128:$src),
2377 (iPTR 0))), addr:$dst)]>;
2379 // FIXME: may not be able to eliminate this movss with coalescing the src and
2380 // dest register classes are different. We really want to write this pattern
2382 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2383 // (f32 FR32:$src)>;
2384 let isAsCheapAsAMove = 1 in
2385 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2386 "movsd\t{$src, $dst|$dst, $src}",
2387 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2389 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2390 "movsd\t{$src, $dst|$dst, $src}",
2391 [(store (f64 (vector_extract (v2f64 VR128:$src),
2392 (iPTR 0))), addr:$dst)]>;
2393 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2394 "movd\t{$src, $dst|$dst, $src}",
2395 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2397 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2398 "movd\t{$src, $dst|$dst, $src}",
2399 [(store (i32 (vector_extract (v4i32 VR128:$src),
2400 (iPTR 0))), addr:$dst)]>;
2402 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2403 "movd\t{$src, $dst|$dst, $src}",
2404 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2405 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2406 "movd\t{$src, $dst|$dst, $src}",
2407 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2410 // Move to lower bits of a VR128, leaving upper bits alone.
2411 // Three operand (but two address) aliases.
2412 let Constraints = "$src1 = $dst" in {
2413 let neverHasSideEffects = 1 in
2414 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2415 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2416 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2418 let AddedComplexity = 15 in
2419 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2420 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2421 "movsd\t{$src2, $dst|$dst, $src2}",
2423 (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
2426 // Store / copy lower 64-bits of a XMM register.
2427 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2428 "movq\t{$src, $dst|$dst, $src}",
2429 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2431 // Move to lower bits of a VR128 and zeroing upper bits.
2432 // Loading from memory automatically zeroing upper bits.
2433 let AddedComplexity = 20 in {
2434 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2435 "movsd\t{$src, $dst|$dst, $src}",
2437 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2438 (loadf64 addr:$src))))))]>;
2440 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2441 (MOVZSD2PDrm addr:$src)>;
2442 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2443 (MOVZSD2PDrm addr:$src)>;
2444 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2447 // movd / movq to XMM register zero-extends
2448 let AddedComplexity = 15 in {
2449 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2450 "movd\t{$src, $dst|$dst, $src}",
2451 [(set VR128:$dst, (v4i32 (X86vzmovl
2452 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2453 // This is X86-64 only.
2454 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2455 "mov{d|q}\t{$src, $dst|$dst, $src}",
2456 [(set VR128:$dst, (v2i64 (X86vzmovl
2457 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2460 let AddedComplexity = 20 in {
2461 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2462 "movd\t{$src, $dst|$dst, $src}",
2464 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2465 (loadi32 addr:$src))))))]>;
2467 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2468 (MOVZDI2PDIrm addr:$src)>;
2469 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2470 (MOVZDI2PDIrm addr:$src)>;
2471 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2472 (MOVZDI2PDIrm addr:$src)>;
2474 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2475 "movq\t{$src, $dst|$dst, $src}",
2477 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2478 (loadi64 addr:$src))))))]>, XS,
2479 Requires<[HasSSE2]>;
2481 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2482 (MOVZQI2PQIrm addr:$src)>;
2483 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2484 (MOVZQI2PQIrm addr:$src)>;
2485 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2488 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2489 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2490 let AddedComplexity = 15 in
2491 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2492 "movq\t{$src, $dst|$dst, $src}",
2493 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2494 XS, Requires<[HasSSE2]>;
2496 let AddedComplexity = 20 in {
2497 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2498 "movq\t{$src, $dst|$dst, $src}",
2499 [(set VR128:$dst, (v2i64 (X86vzmovl
2500 (loadv2i64 addr:$src))))]>,
2501 XS, Requires<[HasSSE2]>;
2503 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2504 (MOVZPQILo2PQIrm addr:$src)>;
2507 // Instructions for the disassembler
2508 // xr = XMM register
2511 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2512 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2514 //===---------------------------------------------------------------------===//
2515 // SSE3 Instructions
2516 //===---------------------------------------------------------------------===//
2518 // Move Instructions
2519 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2520 "movshdup\t{$src, $dst|$dst, $src}",
2521 [(set VR128:$dst, (v4f32 (movshdup
2522 VR128:$src, (undef))))]>;
2523 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2524 "movshdup\t{$src, $dst|$dst, $src}",
2525 [(set VR128:$dst, (movshdup
2526 (memopv4f32 addr:$src), (undef)))]>;
2528 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2529 "movsldup\t{$src, $dst|$dst, $src}",
2530 [(set VR128:$dst, (v4f32 (movsldup
2531 VR128:$src, (undef))))]>;
2532 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2533 "movsldup\t{$src, $dst|$dst, $src}",
2534 [(set VR128:$dst, (movsldup
2535 (memopv4f32 addr:$src), (undef)))]>;
2537 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2538 "movddup\t{$src, $dst|$dst, $src}",
2539 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2540 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2541 "movddup\t{$src, $dst|$dst, $src}",
2543 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2546 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2548 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2550 let AddedComplexity = 5 in {
2551 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2552 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2553 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2554 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2555 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2556 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2557 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2558 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2562 let Constraints = "$src1 = $dst" in {
2563 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2564 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2565 "addsubps\t{$src2, $dst|$dst, $src2}",
2566 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2568 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2569 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2570 "addsubps\t{$src2, $dst|$dst, $src2}",
2571 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2572 (memop addr:$src2)))]>;
2573 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2575 "addsubpd\t{$src2, $dst|$dst, $src2}",
2576 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2578 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2579 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2580 "addsubpd\t{$src2, $dst|$dst, $src2}",
2581 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2582 (memop addr:$src2)))]>;
2585 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2586 "lddqu\t{$src, $dst|$dst, $src}",
2587 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2590 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2591 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2592 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2593 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2594 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2595 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2596 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2597 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2598 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2599 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2601 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2602 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2603 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2605 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2607 let Constraints = "$src1 = $dst" in {
2608 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2609 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2610 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2611 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2612 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2613 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2614 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2615 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2618 // Thread synchronization
2619 def MONITOR : I<0x01, MRM1r, (outs), (ins), "monitor",
2620 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2621 def MWAIT : I<0x01, MRM1r, (outs), (ins), "mwait",
2622 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2624 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2625 let AddedComplexity = 15 in
2626 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2627 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2628 let AddedComplexity = 20 in
2629 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2630 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2632 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2633 let AddedComplexity = 15 in
2634 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2635 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2636 let AddedComplexity = 20 in
2637 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2638 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2640 //===---------------------------------------------------------------------===//
2641 // SSSE3 Instructions
2642 //===---------------------------------------------------------------------===//
2644 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2645 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2646 Intrinsic IntId64, Intrinsic IntId128> {
2647 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2649 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2651 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2652 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2654 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2656 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2659 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2662 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2664 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2667 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2670 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2671 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2672 Intrinsic IntId64, Intrinsic IntId128> {
2673 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2675 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2676 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2678 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2680 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2683 (bitconvert (memopv4i16 addr:$src))))]>;
2685 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2688 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2691 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2693 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2696 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2699 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2700 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2701 Intrinsic IntId64, Intrinsic IntId128> {
2702 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2705 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2707 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2712 (bitconvert (memopv2i32 addr:$src))))]>;
2714 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2717 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2720 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2725 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2728 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2729 int_x86_ssse3_pabs_b,
2730 int_x86_ssse3_pabs_b_128>;
2731 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2732 int_x86_ssse3_pabs_w,
2733 int_x86_ssse3_pabs_w_128>;
2734 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2735 int_x86_ssse3_pabs_d,
2736 int_x86_ssse3_pabs_d_128>;
2738 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2739 let Constraints = "$src1 = $dst" in {
2740 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2741 Intrinsic IntId64, Intrinsic IntId128,
2742 bit Commutable = 0> {
2743 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2744 (ins VR64:$src1, VR64:$src2),
2745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2746 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2747 let isCommutable = Commutable;
2749 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2750 (ins VR64:$src1, i64mem:$src2),
2751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2753 (IntId64 VR64:$src1,
2754 (bitconvert (memopv8i8 addr:$src2))))]>;
2756 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2757 (ins VR128:$src1, VR128:$src2),
2758 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2759 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2761 let isCommutable = Commutable;
2763 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2764 (ins VR128:$src1, i128mem:$src2),
2765 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2767 (IntId128 VR128:$src1,
2768 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2772 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2773 let Constraints = "$src1 = $dst" in {
2774 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2775 Intrinsic IntId64, Intrinsic IntId128,
2776 bit Commutable = 0> {
2777 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2778 (ins VR64:$src1, VR64:$src2),
2779 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2780 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2781 let isCommutable = Commutable;
2783 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2784 (ins VR64:$src1, i64mem:$src2),
2785 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2787 (IntId64 VR64:$src1,
2788 (bitconvert (memopv4i16 addr:$src2))))]>;
2790 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2791 (ins VR128:$src1, VR128:$src2),
2792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2793 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2795 let isCommutable = Commutable;
2797 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2798 (ins VR128:$src1, i128mem:$src2),
2799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2801 (IntId128 VR128:$src1,
2802 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2806 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2807 let Constraints = "$src1 = $dst" in {
2808 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2809 Intrinsic IntId64, Intrinsic IntId128,
2810 bit Commutable = 0> {
2811 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2812 (ins VR64:$src1, VR64:$src2),
2813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2814 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2815 let isCommutable = Commutable;
2817 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2818 (ins VR64:$src1, i64mem:$src2),
2819 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2821 (IntId64 VR64:$src1,
2822 (bitconvert (memopv2i32 addr:$src2))))]>;
2824 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2825 (ins VR128:$src1, VR128:$src2),
2826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2827 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2829 let isCommutable = Commutable;
2831 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2832 (ins VR128:$src1, i128mem:$src2),
2833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2835 (IntId128 VR128:$src1,
2836 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2840 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2841 int_x86_ssse3_phadd_w,
2842 int_x86_ssse3_phadd_w_128>;
2843 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2844 int_x86_ssse3_phadd_d,
2845 int_x86_ssse3_phadd_d_128>;
2846 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2847 int_x86_ssse3_phadd_sw,
2848 int_x86_ssse3_phadd_sw_128>;
2849 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2850 int_x86_ssse3_phsub_w,
2851 int_x86_ssse3_phsub_w_128>;
2852 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2853 int_x86_ssse3_phsub_d,
2854 int_x86_ssse3_phsub_d_128>;
2855 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2856 int_x86_ssse3_phsub_sw,
2857 int_x86_ssse3_phsub_sw_128>;
2858 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2859 int_x86_ssse3_pmadd_ub_sw,
2860 int_x86_ssse3_pmadd_ub_sw_128>;
2861 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2862 int_x86_ssse3_pmul_hr_sw,
2863 int_x86_ssse3_pmul_hr_sw_128, 1>;
2864 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2865 int_x86_ssse3_pshuf_b,
2866 int_x86_ssse3_pshuf_b_128>;
2867 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2868 int_x86_ssse3_psign_b,
2869 int_x86_ssse3_psign_b_128>;
2870 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2871 int_x86_ssse3_psign_w,
2872 int_x86_ssse3_psign_w_128>;
2873 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2874 int_x86_ssse3_psign_d,
2875 int_x86_ssse3_psign_d_128>;
2877 let Constraints = "$src1 = $dst" in {
2878 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2879 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2880 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2882 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2883 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2884 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2887 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2888 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2889 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2891 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2892 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2893 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2897 // palignr patterns.
2898 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2899 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2900 Requires<[HasSSSE3]>;
2901 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2902 (memop64 addr:$src2),
2904 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2905 Requires<[HasSSSE3]>;
2907 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2908 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2909 Requires<[HasSSSE3]>;
2910 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2911 (memopv2i64 addr:$src2),
2913 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2914 Requires<[HasSSSE3]>;
2916 let AddedComplexity = 5 in {
2917 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2918 (PALIGNR128rr VR128:$src2, VR128:$src1,
2919 (SHUFFLE_get_palign_imm VR128:$src3))>,
2920 Requires<[HasSSSE3]>;
2921 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2922 (PALIGNR128rr VR128:$src2, VR128:$src1,
2923 (SHUFFLE_get_palign_imm VR128:$src3))>,
2924 Requires<[HasSSSE3]>;
2925 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2926 (PALIGNR128rr VR128:$src2, VR128:$src1,
2927 (SHUFFLE_get_palign_imm VR128:$src3))>,
2928 Requires<[HasSSSE3]>;
2929 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2930 (PALIGNR128rr VR128:$src2, VR128:$src1,
2931 (SHUFFLE_get_palign_imm VR128:$src3))>,
2932 Requires<[HasSSSE3]>;
2935 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2936 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2937 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2938 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2940 //===---------------------------------------------------------------------===//
2941 // Non-Instruction Patterns
2942 //===---------------------------------------------------------------------===//
2944 // extload f32 -> f64. This matches load+fextend because we have a hack in
2945 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2947 // Since these loads aren't folded into the fextend, we have to match it
2949 let Predicates = [HasSSE2] in
2950 def : Pat<(fextend (loadf32 addr:$src)),
2951 (CVTSS2SDrm addr:$src)>;
2954 let Predicates = [HasSSE2] in {
2955 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2956 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2957 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2958 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2959 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2960 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2961 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2962 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2963 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2964 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2965 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2966 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2967 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2968 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2969 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2970 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2971 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2972 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2973 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2974 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2975 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2976 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2977 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2978 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2979 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2980 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2981 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2982 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2983 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2984 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2987 // Move scalar to XMM zero-extended
2988 // movd to XMM register zero-extends
2989 let AddedComplexity = 15 in {
2990 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2991 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2992 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2993 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2994 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2995 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2996 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2997 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2998 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
3001 // Splat v2f64 / v2i64
3002 let AddedComplexity = 10 in {
3003 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3004 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3005 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3006 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3007 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3008 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3009 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3010 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3013 // Special unary SHUFPSrri case.
3014 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3015 (SHUFPSrri VR128:$src1, VR128:$src1,
3016 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3017 Requires<[HasSSE1]>;
3018 let AddedComplexity = 5 in
3019 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3020 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3021 Requires<[HasSSE2]>;
3022 // Special unary SHUFPDrri case.
3023 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3024 (SHUFPDrri VR128:$src1, VR128:$src1,
3025 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3026 Requires<[HasSSE2]>;
3027 // Special unary SHUFPDrri case.
3028 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3029 (SHUFPDrri VR128:$src1, VR128:$src1,
3030 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3031 Requires<[HasSSE2]>;
3032 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3033 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3034 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3035 Requires<[HasSSE2]>;
3037 // Special binary v4i32 shuffle cases with SHUFPS.
3038 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3039 (SHUFPSrri VR128:$src1, VR128:$src2,
3040 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3041 Requires<[HasSSE2]>;
3042 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3043 (SHUFPSrmi VR128:$src1, addr:$src2,
3044 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3045 Requires<[HasSSE2]>;
3046 // Special binary v2i64 shuffle cases using SHUFPDrri.
3047 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3048 (SHUFPDrri VR128:$src1, VR128:$src2,
3049 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3050 Requires<[HasSSE2]>;
3052 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3053 let AddedComplexity = 15 in {
3054 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3055 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3056 Requires<[OptForSpeed, HasSSE2]>;
3057 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3058 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3059 Requires<[OptForSpeed, HasSSE2]>;
3061 let AddedComplexity = 10 in {
3062 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3063 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
3064 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3065 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3066 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3067 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3068 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3069 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3072 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3073 let AddedComplexity = 15 in {
3074 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3075 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3076 Requires<[OptForSpeed, HasSSE2]>;
3077 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3078 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3079 Requires<[OptForSpeed, HasSSE2]>;
3081 let AddedComplexity = 10 in {
3082 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3083 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
3084 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3085 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3086 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3087 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3088 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3089 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3092 let AddedComplexity = 20 in {
3093 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3094 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3095 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3097 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3098 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3099 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3101 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3102 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3103 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3104 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3105 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3108 let AddedComplexity = 20 in {
3109 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3110 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3111 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3112 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3113 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3114 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3115 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3116 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3117 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3120 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3121 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3122 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3123 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3124 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3125 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3127 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3128 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3129 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3131 let AddedComplexity = 15 in {
3132 // Setting the lowest element in the vector.
3133 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3134 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3135 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3136 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3138 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3139 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3140 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3141 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3142 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3145 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3146 // fall back to this for SSE1)
3147 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3148 (SHUFPSrri VR128:$src2, VR128:$src1,
3149 (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE1]>;
3151 // Set lowest element and zero upper elements.
3152 let AddedComplexity = 15 in
3153 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3154 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3155 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3156 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3158 // Some special case pandn patterns.
3159 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3161 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3162 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3164 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3165 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3167 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3169 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3170 (memop addr:$src2))),
3171 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3172 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3173 (memop addr:$src2))),
3174 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3175 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3176 (memop addr:$src2))),
3177 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3179 // vector -> vector casts
3180 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3181 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3182 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3183 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3184 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3185 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3186 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3187 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3189 // Use movaps / movups for SSE integer load / store (one byte shorter).
3190 def : Pat<(alignedloadv4i32 addr:$src),
3191 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3192 def : Pat<(loadv4i32 addr:$src),
3193 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3194 def : Pat<(alignedloadv2i64 addr:$src),
3195 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3196 def : Pat<(loadv2i64 addr:$src),
3197 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3199 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3200 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3201 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3202 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3203 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3204 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3205 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3206 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3207 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3208 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3209 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3210 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3211 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3212 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3213 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3214 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3216 //===----------------------------------------------------------------------===//
3217 // SSE4.1 Instructions
3218 //===----------------------------------------------------------------------===//
3220 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3223 Intrinsic V2F64Int> {
3224 // Intrinsic operation, reg.
3225 // Vector intrinsic operation, reg
3226 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3227 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3228 !strconcat(OpcodeStr,
3229 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3230 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3233 // Vector intrinsic operation, mem
3234 def PSm_Int : Ii8<opcps, MRMSrcMem,
3235 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3236 !strconcat(OpcodeStr,
3237 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3239 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3241 Requires<[HasSSE41]>;
3243 // Vector intrinsic operation, reg
3244 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3245 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3246 !strconcat(OpcodeStr,
3247 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3248 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3251 // Vector intrinsic operation, mem
3252 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3253 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3254 !strconcat(OpcodeStr,
3255 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3257 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3261 let Constraints = "$src1 = $dst" in {
3262 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3266 // Intrinsic operation, reg.
3267 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3269 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3270 !strconcat(OpcodeStr,
3271 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3273 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3276 // Intrinsic operation, mem.
3277 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3279 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3280 !strconcat(OpcodeStr,
3281 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3283 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3286 // Intrinsic operation, reg.
3287 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3289 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3290 !strconcat(OpcodeStr,
3291 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3293 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3296 // Intrinsic operation, mem.
3297 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3299 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3300 !strconcat(OpcodeStr,
3301 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3303 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3308 // FP round - roundss, roundps, roundsd, roundpd
3309 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3310 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3311 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3312 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3314 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3315 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3316 Intrinsic IntId128> {
3317 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3320 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3321 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3326 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3329 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3330 int_x86_sse41_phminposuw>;
3332 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3333 let Constraints = "$src1 = $dst" in {
3334 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3335 Intrinsic IntId128, bit Commutable = 0> {
3336 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3337 (ins VR128:$src1, VR128:$src2),
3338 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3339 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3341 let isCommutable = Commutable;
3343 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3344 (ins VR128:$src1, i128mem:$src2),
3345 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3347 (IntId128 VR128:$src1,
3348 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3352 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3353 int_x86_sse41_pcmpeqq, 1>;
3354 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3355 int_x86_sse41_packusdw, 0>;
3356 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3357 int_x86_sse41_pminsb, 1>;
3358 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3359 int_x86_sse41_pminsd, 1>;
3360 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3361 int_x86_sse41_pminud, 1>;
3362 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3363 int_x86_sse41_pminuw, 1>;
3364 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3365 int_x86_sse41_pmaxsb, 1>;
3366 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3367 int_x86_sse41_pmaxsd, 1>;
3368 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3369 int_x86_sse41_pmaxud, 1>;
3370 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3371 int_x86_sse41_pmaxuw, 1>;
3373 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3375 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3376 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3377 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3378 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3380 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3381 let Constraints = "$src1 = $dst" in {
3382 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3383 SDNode OpNode, Intrinsic IntId128,
3384 bit Commutable = 0> {
3385 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3386 (ins VR128:$src1, VR128:$src2),
3387 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3388 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3389 VR128:$src2))]>, OpSize {
3390 let isCommutable = Commutable;
3392 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3393 (ins VR128:$src1, VR128:$src2),
3394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3395 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3397 let isCommutable = Commutable;
3399 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3400 (ins VR128:$src1, i128mem:$src2),
3401 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3403 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3404 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3405 (ins VR128:$src1, i128mem:$src2),
3406 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3408 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3412 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3413 int_x86_sse41_pmulld, 1>;
3415 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3416 let Constraints = "$src1 = $dst" in {
3417 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3418 Intrinsic IntId128, bit Commutable = 0> {
3419 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3420 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3421 !strconcat(OpcodeStr,
3422 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3424 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3426 let isCommutable = Commutable;
3428 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3429 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3430 !strconcat(OpcodeStr,
3431 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3433 (IntId128 VR128:$src1,
3434 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3439 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3440 int_x86_sse41_blendps, 0>;
3441 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3442 int_x86_sse41_blendpd, 0>;
3443 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3444 int_x86_sse41_pblendw, 0>;
3445 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3446 int_x86_sse41_dpps, 1>;
3447 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3448 int_x86_sse41_dppd, 1>;
3449 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3450 int_x86_sse41_mpsadbw, 1>;
3453 /// SS41I_ternary_int - SSE 4.1 ternary operator
3454 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3455 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3456 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3457 (ins VR128:$src1, VR128:$src2),
3458 !strconcat(OpcodeStr,
3459 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3460 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3463 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3464 (ins VR128:$src1, i128mem:$src2),
3465 !strconcat(OpcodeStr,
3466 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3469 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3473 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3474 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3475 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3478 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3479 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3481 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3483 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3484 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3486 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3490 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3491 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3492 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3493 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3494 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3495 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3497 // Common patterns involving scalar load.
3498 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3499 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3500 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3501 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3503 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3504 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3505 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3506 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3508 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3509 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3510 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3511 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3513 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3514 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3515 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3516 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3518 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3519 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3520 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3521 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3523 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3524 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3525 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3526 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3529 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3530 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3531 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3532 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3534 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3537 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3541 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3542 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3543 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3544 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3546 // Common patterns involving scalar load
3547 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3548 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3549 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3550 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3552 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3553 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3554 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3555 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3558 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3559 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3561 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3563 // Expecting a i16 load any extended to i32 value.
3564 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3565 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3566 [(set VR128:$dst, (IntId (bitconvert
3567 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3571 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3572 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3574 // Common patterns involving scalar load
3575 def : Pat<(int_x86_sse41_pmovsxbq
3576 (bitconvert (v4i32 (X86vzmovl
3577 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3578 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3580 def : Pat<(int_x86_sse41_pmovzxbq
3581 (bitconvert (v4i32 (X86vzmovl
3582 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3583 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3586 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3587 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3588 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3589 (ins VR128:$src1, i32i8imm:$src2),
3590 !strconcat(OpcodeStr,
3591 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3592 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3594 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3595 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3596 !strconcat(OpcodeStr,
3597 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3600 // There's an AssertZext in the way of writing the store pattern
3601 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3604 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3607 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3608 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3609 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3610 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3611 !strconcat(OpcodeStr,
3612 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3615 // There's an AssertZext in the way of writing the store pattern
3616 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3619 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3622 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3623 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3624 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3625 (ins VR128:$src1, i32i8imm:$src2),
3626 !strconcat(OpcodeStr,
3627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3629 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3630 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3631 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3632 !strconcat(OpcodeStr,
3633 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3634 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3635 addr:$dst)]>, OpSize;
3638 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3641 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3643 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3644 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3645 (ins VR128:$src1, i32i8imm:$src2),
3646 !strconcat(OpcodeStr,
3647 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3649 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3651 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3652 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3653 !strconcat(OpcodeStr,
3654 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3655 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3656 addr:$dst)]>, OpSize;
3659 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3661 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3662 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3665 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3666 Requires<[HasSSE41]>;
3668 let Constraints = "$src1 = $dst" in {
3669 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3670 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3671 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3672 !strconcat(OpcodeStr,
3673 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3675 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3676 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3677 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3678 !strconcat(OpcodeStr,
3679 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3681 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3682 imm:$src3))]>, OpSize;
3686 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3688 let Constraints = "$src1 = $dst" in {
3689 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3690 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3691 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3692 !strconcat(OpcodeStr,
3693 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3695 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3697 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3698 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3699 !strconcat(OpcodeStr,
3700 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3702 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3703 imm:$src3)))]>, OpSize;
3707 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3709 // insertps has a few different modes, there's the first two here below which
3710 // are optimized inserts that won't zero arbitrary elements in the destination
3711 // vector. The next one matches the intrinsic and could zero arbitrary elements
3712 // in the target vector.
3713 let Constraints = "$src1 = $dst" in {
3714 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3715 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3716 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3717 !strconcat(OpcodeStr,
3718 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3720 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3722 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3723 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3724 !strconcat(OpcodeStr,
3725 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3727 (X86insrtps VR128:$src1,
3728 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3729 imm:$src3))]>, OpSize;
3733 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3735 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3736 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3738 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3739 // the intel intrinsic that corresponds to this.
3740 let Defs = [EFLAGS] in {
3741 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3742 "ptest \t{$src2, $src1|$src1, $src2}",
3743 [(X86ptest VR128:$src1, VR128:$src2),
3744 (implicit EFLAGS)]>, OpSize;
3745 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3746 "ptest \t{$src2, $src1|$src1, $src2}",
3747 [(X86ptest VR128:$src1, (load addr:$src2)),
3748 (implicit EFLAGS)]>, OpSize;
3751 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3752 "movntdqa\t{$src, $dst|$dst, $src}",
3753 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3757 //===----------------------------------------------------------------------===//
3758 // SSE4.2 Instructions
3759 //===----------------------------------------------------------------------===//
3761 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3762 let Constraints = "$src1 = $dst" in {
3763 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3764 Intrinsic IntId128, bit Commutable = 0> {
3765 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3766 (ins VR128:$src1, VR128:$src2),
3767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3768 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3770 let isCommutable = Commutable;
3772 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3773 (ins VR128:$src1, i128mem:$src2),
3774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3776 (IntId128 VR128:$src1,
3777 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3781 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3783 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3784 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3785 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3786 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3788 // crc intrinsic instruction
3789 // This set of instructions are only rm, the only difference is the size
3791 let Constraints = "$src1 = $dst" in {
3792 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3793 (ins GR32:$src1, i8mem:$src2),
3794 "crc32 \t{$src2, $src1|$src1, $src2}",
3796 (int_x86_sse42_crc32_8 GR32:$src1,
3797 (load addr:$src2)))]>, OpSize;
3798 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3799 (ins GR32:$src1, GR8:$src2),
3800 "crc32 \t{$src2, $src1|$src1, $src2}",
3802 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
3804 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3805 (ins GR32:$src1, i16mem:$src2),
3806 "crc32 \t{$src2, $src1|$src1, $src2}",
3808 (int_x86_sse42_crc32_16 GR32:$src1,
3809 (load addr:$src2)))]>,
3811 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3812 (ins GR32:$src1, GR16:$src2),
3813 "crc32 \t{$src2, $src1|$src1, $src2}",
3815 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3817 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3818 (ins GR32:$src1, i32mem:$src2),
3819 "crc32 \t{$src2, $src1|$src1, $src2}",
3821 (int_x86_sse42_crc32_32 GR32:$src1,
3822 (load addr:$src2)))]>, OpSize;
3823 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3824 (ins GR32:$src1, GR32:$src2),
3825 "crc32 \t{$src2, $src1|$src1, $src2}",
3827 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
3829 def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3830 (ins GR64:$src1, i64mem:$src2),
3831 "crc32 \t{$src2, $src1|$src1, $src2}",
3833 (int_x86_sse42_crc32_64 GR64:$src1,
3834 (load addr:$src2)))]>,
3836 def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3837 (ins GR64:$src1, GR64:$src2),
3838 "crc32 \t{$src2, $src1|$src1, $src2}",
3840 (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
3844 // String/text processing instructions.
3845 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3846 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3847 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3848 "#PCMPISTRM128rr PSEUDO!",
3849 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3850 imm:$src3))]>, OpSize;
3851 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3852 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3853 "#PCMPISTRM128rm PSEUDO!",
3854 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3855 imm:$src3))]>, OpSize;
3858 let Defs = [XMM0, EFLAGS] in {
3859 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3860 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3861 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3862 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3863 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3864 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3867 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3868 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3869 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3870 "#PCMPESTRM128rr PSEUDO!",
3872 (int_x86_sse42_pcmpestrm128
3873 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3875 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3876 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3877 "#PCMPESTRM128rm PSEUDO!",
3878 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3879 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3883 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3884 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3885 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3886 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3887 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3888 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3889 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3892 let Defs = [ECX, EFLAGS] in {
3893 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3894 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3895 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3896 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3897 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3898 (implicit EFLAGS)]>, OpSize;
3899 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3900 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3901 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3902 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3903 (implicit EFLAGS)]>, OpSize;
3907 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3908 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3909 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3910 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3911 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3912 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3914 let Defs = [ECX, EFLAGS] in {
3915 let Uses = [EAX, EDX] in {
3916 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3917 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3918 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3919 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3920 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3921 (implicit EFLAGS)]>, OpSize;
3922 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3923 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3924 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3926 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3927 (implicit EFLAGS)]>, OpSize;
3932 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3933 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3934 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3935 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3936 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3937 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;