1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (store node:$val, node:$ptr), [{
102 return cast<StoreSDNode>(N)->getAlignment() >= 16;
105 // Like 'load', but always requires vector alignment.
106 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
107 return cast<LoadSDNode>(N)->getAlignment() >= 16;
110 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
111 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
112 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
113 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
114 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
115 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
117 // Like 'load', but uses special alignment checks suitable for use in
118 // memory operands in most SSE instructions, which are required to
119 // be naturally aligned on some targets but not on others.
120 // FIXME: Actually implement support for targets that don't require the
121 // alignment. This probably wants a subtarget predicate.
122 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAlignment() >= 16;
126 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
127 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
128 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
129 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
130 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
131 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
132 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 // FIXME: 8 byte alignment for mmx reads is not required
137 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
138 return cast<LoadSDNode>(N)->getAlignment() >= 8;
141 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
142 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
143 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
144 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
146 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
147 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
148 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
149 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
150 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
151 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
153 def vzmovl_v2i64 : PatFrag<(ops node:$src),
154 (bitconvert (v2i64 (X86vzmovl
155 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
156 def vzmovl_v4i32 : PatFrag<(ops node:$src),
157 (bitconvert (v4i32 (X86vzmovl
158 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
160 def vzload_v2i64 : PatFrag<(ops node:$src),
161 (bitconvert (v2i64 (X86vzload node:$src)))>;
164 def fp32imm0 : PatLeaf<(f32 fpimm), [{
165 return N->isExactlyValue(+0.0);
168 def PSxLDQ_imm : SDNodeXForm<imm, [{
169 // Transformation function: imm >> 3
170 return getI32Imm(N->getZExtValue() >> 3);
173 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
175 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
176 return getI8Imm(X86::getShuffleSHUFImmediate(N));
179 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
181 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
182 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
185 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
187 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
191 def SSE_splat_mask : PatLeaf<(build_vector), [{
192 return X86::isSplatMask(N);
193 }], SHUFFLE_get_shuf_imm>;
195 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
196 return X86::isSplatLoMask(N);
199 def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
200 return X86::isMOVDDUPMask(N);
203 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
204 return X86::isMOVHLPSMask(N);
207 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
208 return X86::isMOVHLPS_v_undef_Mask(N);
211 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHPMask(N);
215 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVLPMask(N);
219 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVLMask(N);
223 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVSHDUPMask(N);
227 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVSLDUPMask(N);
231 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isUNPCKLMask(N);
235 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isUNPCKHMask(N);
239 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKL_v_undef_Mask(N);
243 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKH_v_undef_Mask(N);
247 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isPSHUFDMask(N);
249 }], SHUFFLE_get_shuf_imm>;
251 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isPSHUFHWMask(N);
253 }], SHUFFLE_get_pshufhw_imm>;
255 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFLWMask(N);
257 }], SHUFFLE_get_pshuflw_imm>;
259 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isSHUFPMask(N);
265 }], SHUFFLE_get_shuf_imm>;
267 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isSHUFPMask(N);
269 }], SHUFFLE_get_shuf_imm>;
272 //===----------------------------------------------------------------------===//
273 // SSE scalar FP Instructions
274 //===----------------------------------------------------------------------===//
276 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
277 // scheduler into a branch sequence.
278 // These are expanded by the scheduler.
279 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
280 def CMOV_FR32 : I<0, Pseudo,
281 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
282 "#CMOV_FR32 PSEUDO!",
283 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
285 def CMOV_FR64 : I<0, Pseudo,
286 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
287 "#CMOV_FR64 PSEUDO!",
288 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
290 def CMOV_V4F32 : I<0, Pseudo,
291 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V4F32 PSEUDO!",
294 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
296 def CMOV_V2F64 : I<0, Pseudo,
297 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
298 "#CMOV_V2F64 PSEUDO!",
300 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
302 def CMOV_V2I64 : I<0, Pseudo,
303 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
304 "#CMOV_V2I64 PSEUDO!",
306 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 let neverHasSideEffects = 1 in
316 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
317 "movss\t{$src, $dst|$dst, $src}", []>;
318 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
319 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
320 "movss\t{$src, $dst|$dst, $src}",
321 [(set FR32:$dst, (loadf32 addr:$src))]>;
322 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
323 "movss\t{$src, $dst|$dst, $src}",
324 [(store FR32:$src, addr:$dst)]>;
326 // Conversion instructions
327 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
328 "cvttss2si\t{$src, $dst|$dst, $src}",
329 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
330 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
331 "cvttss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
333 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
334 "cvtsi2ss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
336 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
337 "cvtsi2ss\t{$src, $dst|$dst, $src}",
338 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
340 // Match intrinsics which expect XMM operand(s).
341 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
342 "cvtss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
344 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
345 "cvtss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (int_x86_sse_cvtss2si
347 (load addr:$src)))]>;
349 // Match intrinisics which expect MM and XMM operand(s).
350 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
351 "cvtps2pi\t{$src, $dst|$dst, $src}",
352 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
353 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
354 "cvtps2pi\t{$src, $dst|$dst, $src}",
355 [(set VR64:$dst, (int_x86_sse_cvtps2pi
356 (load addr:$src)))]>;
357 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
358 "cvttps2pi\t{$src, $dst|$dst, $src}",
359 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
360 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
361 "cvttps2pi\t{$src, $dst|$dst, $src}",
362 [(set VR64:$dst, (int_x86_sse_cvttps2pi
363 (load addr:$src)))]>;
364 let Constraints = "$src1 = $dst" in {
365 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
366 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
367 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
368 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
370 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
371 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
372 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
374 (load addr:$src2)))]>;
377 // Aliases for intrinsics
378 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
379 "cvttss2si\t{$src, $dst|$dst, $src}",
381 (int_x86_sse_cvttss2si VR128:$src))]>;
382 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
383 "cvttss2si\t{$src, $dst|$dst, $src}",
385 (int_x86_sse_cvttss2si(load addr:$src)))]>;
387 let Constraints = "$src1 = $dst" in {
388 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
389 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
390 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
391 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
393 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
394 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
395 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
396 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
397 (loadi32 addr:$src2)))]>;
400 // Comparison instructions
401 let Constraints = "$src1 = $dst" in {
402 let neverHasSideEffects = 1 in
403 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
404 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
405 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
406 let neverHasSideEffects = 1, mayLoad = 1 in
407 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
408 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
409 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
412 let Defs = [EFLAGS] in {
413 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
414 "ucomiss\t{$src2, $src1|$src1, $src2}",
415 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
416 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
417 "ucomiss\t{$src2, $src1|$src1, $src2}",
418 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
422 // Aliases to match intrinsics which expect XMM operand(s).
423 let Constraints = "$src1 = $dst" in {
424 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
425 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
427 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
428 VR128:$src, imm:$cc))]>;
429 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
430 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
431 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
432 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
433 (load addr:$src), imm:$cc))]>;
436 let Defs = [EFLAGS] in {
437 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
438 (ins VR128:$src1, VR128:$src2),
439 "ucomiss\t{$src2, $src1|$src1, $src2}",
440 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
442 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
443 (ins VR128:$src1, f128mem:$src2),
444 "ucomiss\t{$src2, $src1|$src1, $src2}",
445 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
448 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
449 (ins VR128:$src1, VR128:$src2),
450 "comiss\t{$src2, $src1|$src1, $src2}",
451 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
453 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
454 (ins VR128:$src1, f128mem:$src2),
455 "comiss\t{$src2, $src1|$src1, $src2}",
456 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
460 // Aliases of packed SSE1 instructions for scalar use. These all have names that
463 // Alias instructions that map fld0 to pxor for sse.
464 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
465 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
466 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
467 Requires<[HasSSE1]>, TB, OpSize;
469 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
471 let neverHasSideEffects = 1 in
472 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
473 "movaps\t{$src, $dst|$dst, $src}", []>;
475 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
477 let isSimpleLoad = 1 in
478 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
479 "movaps\t{$src, $dst|$dst, $src}",
480 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
482 // Alias bitwise logical operations using SSE logical ops on packed FP values.
483 let Constraints = "$src1 = $dst" in {
484 let isCommutable = 1 in {
485 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
486 "andps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
488 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
489 "orps\t{$src2, $dst|$dst, $src2}",
490 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
491 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
492 "xorps\t{$src2, $dst|$dst, $src2}",
493 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
496 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
497 "andps\t{$src2, $dst|$dst, $src2}",
498 [(set FR32:$dst, (X86fand FR32:$src1,
499 (memopfsf32 addr:$src2)))]>;
500 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1,
503 (memopfsf32 addr:$src2)))]>;
504 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
505 "xorps\t{$src2, $dst|$dst, $src2}",
506 [(set FR32:$dst, (X86fxor FR32:$src1,
507 (memopfsf32 addr:$src2)))]>;
508 let neverHasSideEffects = 1 in {
509 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
510 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
511 "andnps\t{$src2, $dst|$dst, $src2}", []>;
514 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
515 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
516 "andnps\t{$src2, $dst|$dst, $src2}", []>;
520 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
522 /// In addition, we also have a special variant of the scalar form here to
523 /// represent the associated intrinsic operation. This form is unlike the
524 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
525 /// and leaves the top elements undefined.
527 /// These three forms can each be reg+reg or reg+mem, so there are a total of
528 /// six "instructions".
530 let Constraints = "$src1 = $dst" in {
531 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
532 SDNode OpNode, Intrinsic F32Int,
533 bit Commutable = 0> {
534 // Scalar operation, reg+reg.
535 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
536 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
537 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
538 let isCommutable = Commutable;
541 // Scalar operation, reg+mem.
542 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
543 (ins FR32:$src1, f32mem:$src2),
544 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
545 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
547 // Vector operation, reg+reg.
548 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
549 (ins VR128:$src1, VR128:$src2),
550 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
551 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
552 let isCommutable = Commutable;
555 // Vector operation, reg+mem.
556 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
557 (ins VR128:$src1, f128mem:$src2),
558 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
559 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
561 // Intrinsic operation, reg+reg.
562 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
563 (ins VR128:$src1, VR128:$src2),
564 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
565 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
566 let isCommutable = Commutable;
569 // Intrinsic operation, reg+mem.
570 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
571 (ins VR128:$src1, ssmem:$src2),
572 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
573 [(set VR128:$dst, (F32Int VR128:$src1,
574 sse_load_f32:$src2))]>;
578 // Arithmetic instructions
579 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
580 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
581 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
582 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
584 /// sse1_fp_binop_rm - Other SSE1 binops
586 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
587 /// instructions for a full-vector intrinsic form. Operations that map
588 /// onto C operators don't use this form since they just use the plain
589 /// vector form instead of having a separate vector intrinsic form.
591 /// This provides a total of eight "instructions".
593 let Constraints = "$src1 = $dst" in {
594 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
598 bit Commutable = 0> {
600 // Scalar operation, reg+reg.
601 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
602 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
603 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
604 let isCommutable = Commutable;
607 // Scalar operation, reg+mem.
608 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
609 (ins FR32:$src1, f32mem:$src2),
610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
611 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
613 // Vector operation, reg+reg.
614 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
615 (ins VR128:$src1, VR128:$src2),
616 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
617 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
618 let isCommutable = Commutable;
621 // Vector operation, reg+mem.
622 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
623 (ins VR128:$src1, f128mem:$src2),
624 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
625 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
627 // Intrinsic operation, reg+reg.
628 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
629 (ins VR128:$src1, VR128:$src2),
630 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
631 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
632 let isCommutable = Commutable;
635 // Intrinsic operation, reg+mem.
636 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
637 (ins VR128:$src1, ssmem:$src2),
638 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
639 [(set VR128:$dst, (F32Int VR128:$src1,
640 sse_load_f32:$src2))]>;
642 // Vector intrinsic operation, reg+reg.
643 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
644 (ins VR128:$src1, VR128:$src2),
645 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
646 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
647 let isCommutable = Commutable;
650 // Vector intrinsic operation, reg+mem.
651 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
652 (ins VR128:$src1, f128mem:$src2),
653 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
654 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
658 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
659 int_x86_sse_max_ss, int_x86_sse_max_ps>;
660 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
661 int_x86_sse_min_ss, int_x86_sse_min_ps>;
663 //===----------------------------------------------------------------------===//
664 // SSE packed FP Instructions
667 let neverHasSideEffects = 1 in
668 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
669 "movaps\t{$src, $dst|$dst, $src}", []>;
670 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
671 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
672 "movaps\t{$src, $dst|$dst, $src}",
673 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
675 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
676 "movaps\t{$src, $dst|$dst, $src}",
677 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
679 let neverHasSideEffects = 1 in
680 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
681 "movups\t{$src, $dst|$dst, $src}", []>;
682 let isSimpleLoad = 1 in
683 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
684 "movups\t{$src, $dst|$dst, $src}",
685 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
686 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
687 "movups\t{$src, $dst|$dst, $src}",
688 [(store (v4f32 VR128:$src), addr:$dst)]>;
690 // Intrinsic forms of MOVUPS load and store
691 let isSimpleLoad = 1 in
692 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
693 "movups\t{$src, $dst|$dst, $src}",
694 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
695 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
696 "movups\t{$src, $dst|$dst, $src}",
697 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
699 let Constraints = "$src1 = $dst" in {
700 let AddedComplexity = 20 in {
701 def MOVLPSrm : PSI<0x12, MRMSrcMem,
702 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
703 "movlps\t{$src2, $dst|$dst, $src2}",
705 (v4f32 (vector_shuffle VR128:$src1,
706 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
707 MOVLP_shuffle_mask)))]>;
708 def MOVHPSrm : PSI<0x16, MRMSrcMem,
709 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
710 "movhps\t{$src2, $dst|$dst, $src2}",
712 (v4f32 (vector_shuffle VR128:$src1,
713 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
714 MOVHP_shuffle_mask)))]>;
716 } // Constraints = "$src1 = $dst"
719 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
720 "movlps\t{$src, $dst|$dst, $src}",
721 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
722 (iPTR 0))), addr:$dst)]>;
724 // v2f64 extract element 1 is always custom lowered to unpack high to low
725 // and extract element 0 so the non-store version isn't too horrible.
726 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
727 "movhps\t{$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract
729 (v2f64 (vector_shuffle
730 (bc_v2f64 (v4f32 VR128:$src)), (undef),
731 UNPCKH_shuffle_mask)), (iPTR 0))),
734 let Constraints = "$src1 = $dst" in {
735 let AddedComplexity = 20 in {
736 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
737 "movlhps\t{$src2, $dst|$dst, $src2}",
739 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
740 MOVHP_shuffle_mask)))]>;
742 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
743 "movhlps\t{$src2, $dst|$dst, $src2}",
745 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
746 MOVHLPS_shuffle_mask)))]>;
748 } // Constraints = "$src1 = $dst"
750 let AddedComplexity = 20 in
751 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
752 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
759 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
761 /// In addition, we also have a special variant of the scalar form here to
762 /// represent the associated intrinsic operation. This form is unlike the
763 /// plain scalar form, in that it takes an entire vector (instead of a
764 /// scalar) and leaves the top elements undefined.
766 /// And, we have a special variant form for a full-vector intrinsic form.
768 /// These four forms can each have a reg or a mem operand, so there are a
769 /// total of eight "instructions".
771 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
775 bit Commutable = 0> {
776 // Scalar operation, reg.
777 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
778 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
779 [(set FR32:$dst, (OpNode FR32:$src))]> {
780 let isCommutable = Commutable;
783 // Scalar operation, mem.
784 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
785 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
786 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
788 // Vector operation, reg.
789 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
790 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
791 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
792 let isCommutable = Commutable;
795 // Vector operation, mem.
796 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
797 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
798 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
800 // Intrinsic operation, reg.
801 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
802 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (F32Int VR128:$src))]> {
804 let isCommutable = Commutable;
807 // Intrinsic operation, mem.
808 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
809 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
810 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
812 // Vector intrinsic operation, reg
813 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
816 let isCommutable = Commutable;
819 // Vector intrinsic operation, mem
820 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
821 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
822 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
826 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
827 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
829 // Reciprocal approximations. Note that these typically require refinement
830 // in order to obtain suitable precision.
831 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
832 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
833 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
834 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
837 let Constraints = "$src1 = $dst" in {
838 let isCommutable = 1 in {
839 def ANDPSrr : PSI<0x54, MRMSrcReg,
840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
841 "andps\t{$src2, $dst|$dst, $src2}",
842 [(set VR128:$dst, (v2i64
843 (and VR128:$src1, VR128:$src2)))]>;
844 def ORPSrr : PSI<0x56, MRMSrcReg,
845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
846 "orps\t{$src2, $dst|$dst, $src2}",
847 [(set VR128:$dst, (v2i64
848 (or VR128:$src1, VR128:$src2)))]>;
849 def XORPSrr : PSI<0x57, MRMSrcReg,
850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
851 "xorps\t{$src2, $dst|$dst, $src2}",
852 [(set VR128:$dst, (v2i64
853 (xor VR128:$src1, VR128:$src2)))]>;
856 def ANDPSrm : PSI<0x54, MRMSrcMem,
857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
858 "andps\t{$src2, $dst|$dst, $src2}",
859 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
860 (memopv2i64 addr:$src2)))]>;
861 def ORPSrm : PSI<0x56, MRMSrcMem,
862 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
863 "orps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
865 (memopv2i64 addr:$src2)))]>;
866 def XORPSrm : PSI<0x57, MRMSrcMem,
867 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
868 "xorps\t{$src2, $dst|$dst, $src2}",
869 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
870 (memopv2i64 addr:$src2)))]>;
871 def ANDNPSrr : PSI<0x55, MRMSrcReg,
872 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
873 "andnps\t{$src2, $dst|$dst, $src2}",
875 (v2i64 (and (xor VR128:$src1,
876 (bc_v2i64 (v4i32 immAllOnesV))),
878 def ANDNPSrm : PSI<0x55, MRMSrcMem,
879 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
880 "andnps\t{$src2, $dst|$dst, $src2}",
882 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
883 (bc_v2i64 (v4i32 immAllOnesV))),
884 (memopv2i64 addr:$src2))))]>;
887 let Constraints = "$src1 = $dst" in {
888 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
889 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
890 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
892 VR128:$src, imm:$cc))]>;
893 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
894 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
895 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
896 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
897 (memop addr:$src), imm:$cc))]>;
899 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
900 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
901 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
902 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
904 // Shuffle and unpack instructions
905 let Constraints = "$src1 = $dst" in {
906 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
907 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
908 (outs VR128:$dst), (ins VR128:$src1,
909 VR128:$src2, i32i8imm:$src3),
910 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
912 (v4f32 (vector_shuffle
913 VR128:$src1, VR128:$src2,
914 SHUFP_shuffle_mask:$src3)))]>;
915 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
916 (outs VR128:$dst), (ins VR128:$src1,
917 f128mem:$src2, i32i8imm:$src3),
918 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
920 (v4f32 (vector_shuffle
921 VR128:$src1, (memopv4f32 addr:$src2),
922 SHUFP_shuffle_mask:$src3)))]>;
924 let AddedComplexity = 10 in {
925 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
926 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
927 "unpckhps\t{$src2, $dst|$dst, $src2}",
929 (v4f32 (vector_shuffle
930 VR128:$src1, VR128:$src2,
931 UNPCKH_shuffle_mask)))]>;
932 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
934 "unpckhps\t{$src2, $dst|$dst, $src2}",
936 (v4f32 (vector_shuffle
937 VR128:$src1, (memopv4f32 addr:$src2),
938 UNPCKH_shuffle_mask)))]>;
940 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
942 "unpcklps\t{$src2, $dst|$dst, $src2}",
944 (v4f32 (vector_shuffle
945 VR128:$src1, VR128:$src2,
946 UNPCKL_shuffle_mask)))]>;
947 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
948 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
949 "unpcklps\t{$src2, $dst|$dst, $src2}",
951 (v4f32 (vector_shuffle
952 VR128:$src1, (memopv4f32 addr:$src2),
953 UNPCKL_shuffle_mask)))]>;
955 } // Constraints = "$src1 = $dst"
958 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
959 "movmskps\t{$src, $dst|$dst, $src}",
960 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
961 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
962 "movmskpd\t{$src, $dst|$dst, $src}",
963 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
965 // Prefetch intrinsic.
966 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
967 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
968 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
969 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
970 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
971 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
972 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
973 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
975 // Non-temporal stores
976 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
977 "movntps\t{$src, $dst|$dst, $src}",
978 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
980 // Load, store, and memory fence
981 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
984 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
985 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
986 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
987 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
989 // Alias instructions that map zero vector to pxor / xorp* for sse.
990 let isReMaterializable = 1 in
991 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
993 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
995 let Predicates = [HasSSE1] in {
996 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
997 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
998 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
999 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1003 // FR32 to 128-bit vector conversion.
1004 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1005 "movss\t{$src, $dst|$dst, $src}",
1007 (v4f32 (scalar_to_vector FR32:$src)))]>;
1008 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1009 "movss\t{$src, $dst|$dst, $src}",
1011 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1013 // FIXME: may not be able to eliminate this movss with coalescing the src and
1014 // dest register classes are different. We really want to write this pattern
1016 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1017 // (f32 FR32:$src)>;
1018 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1019 "movss\t{$src, $dst|$dst, $src}",
1020 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1022 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1023 "movss\t{$src, $dst|$dst, $src}",
1024 [(store (f32 (vector_extract (v4f32 VR128:$src),
1025 (iPTR 0))), addr:$dst)]>;
1028 // Move to lower bits of a VR128, leaving upper bits alone.
1029 // Three operand (but two address) aliases.
1030 let Constraints = "$src1 = $dst" in {
1031 let neverHasSideEffects = 1 in
1032 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1033 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1034 "movss\t{$src2, $dst|$dst, $src2}", []>;
1036 let AddedComplexity = 15 in
1037 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1038 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1039 "movss\t{$src2, $dst|$dst, $src2}",
1041 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1042 MOVL_shuffle_mask)))]>;
1045 // Move to lower bits of a VR128 and zeroing upper bits.
1046 // Loading from memory automatically zeroing upper bits.
1047 let AddedComplexity = 20 in
1048 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1049 "movss\t{$src, $dst|$dst, $src}",
1050 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1051 (loadf32 addr:$src))))))]>;
1053 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1054 (MOVZSS2PSrm addr:$src)>;
1056 //===----------------------------------------------------------------------===//
1057 // SSE2 Instructions
1058 //===----------------------------------------------------------------------===//
1060 // Move Instructions
1061 let neverHasSideEffects = 1 in
1062 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1063 "movsd\t{$src, $dst|$dst, $src}", []>;
1064 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1065 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1066 "movsd\t{$src, $dst|$dst, $src}",
1067 [(set FR64:$dst, (loadf64 addr:$src))]>;
1068 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1069 "movsd\t{$src, $dst|$dst, $src}",
1070 [(store FR64:$src, addr:$dst)]>;
1072 // Conversion instructions
1073 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1074 "cvttsd2si\t{$src, $dst|$dst, $src}",
1075 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1076 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1077 "cvttsd2si\t{$src, $dst|$dst, $src}",
1078 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1079 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1080 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1081 [(set FR32:$dst, (fround FR64:$src))]>;
1082 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1083 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1084 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1085 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1086 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1087 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1088 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1089 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1090 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1092 // SSE2 instructions with XS prefix
1093 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1094 "cvtss2sd\t{$src, $dst|$dst, $src}",
1095 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1096 Requires<[HasSSE2]>;
1097 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1098 "cvtss2sd\t{$src, $dst|$dst, $src}",
1099 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1100 Requires<[HasSSE2]>;
1102 // Match intrinsics which expect XMM operand(s).
1103 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1104 "cvtsd2si\t{$src, $dst|$dst, $src}",
1105 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1106 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1107 "cvtsd2si\t{$src, $dst|$dst, $src}",
1108 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1109 (load addr:$src)))]>;
1111 // Match intrinisics which expect MM and XMM operand(s).
1112 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1113 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1114 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1115 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1116 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1117 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1118 (memop addr:$src)))]>;
1119 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1120 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1121 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1122 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1123 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1124 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1125 (memop addr:$src)))]>;
1126 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1127 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1128 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1129 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1130 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1132 (load addr:$src)))]>;
1134 // Aliases for intrinsics
1135 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1136 "cvttsd2si\t{$src, $dst|$dst, $src}",
1138 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1139 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1140 "cvttsd2si\t{$src, $dst|$dst, $src}",
1141 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1142 (load addr:$src)))]>;
1144 // Comparison instructions
1145 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1146 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1147 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1148 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1150 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1151 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1152 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1155 let Defs = [EFLAGS] in {
1156 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1157 "ucomisd\t{$src2, $src1|$src1, $src2}",
1158 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1159 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1160 "ucomisd\t{$src2, $src1|$src1, $src2}",
1161 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1162 (implicit EFLAGS)]>;
1165 // Aliases to match intrinsics which expect XMM operand(s).
1166 let Constraints = "$src1 = $dst" in {
1167 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1168 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1169 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1170 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1171 VR128:$src, imm:$cc))]>;
1172 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1173 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1174 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1175 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1176 (load addr:$src), imm:$cc))]>;
1179 let Defs = [EFLAGS] in {
1180 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1181 "ucomisd\t{$src2, $src1|$src1, $src2}",
1182 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1183 (implicit EFLAGS)]>;
1184 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1185 "ucomisd\t{$src2, $src1|$src1, $src2}",
1186 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1187 (implicit EFLAGS)]>;
1189 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1190 "comisd\t{$src2, $src1|$src1, $src2}",
1191 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1192 (implicit EFLAGS)]>;
1193 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1194 "comisd\t{$src2, $src1|$src1, $src2}",
1195 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1196 (implicit EFLAGS)]>;
1199 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1202 // Alias instructions that map fld0 to pxor for sse.
1203 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1204 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1205 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1206 Requires<[HasSSE2]>, TB, OpSize;
1208 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1210 let neverHasSideEffects = 1 in
1211 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1212 "movapd\t{$src, $dst|$dst, $src}", []>;
1214 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1216 let isSimpleLoad = 1 in
1217 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1218 "movapd\t{$src, $dst|$dst, $src}",
1219 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1221 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1222 let Constraints = "$src1 = $dst" in {
1223 let isCommutable = 1 in {
1224 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1225 (ins FR64:$src1, FR64:$src2),
1226 "andpd\t{$src2, $dst|$dst, $src2}",
1227 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1228 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1229 (ins FR64:$src1, FR64:$src2),
1230 "orpd\t{$src2, $dst|$dst, $src2}",
1231 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1232 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1233 (ins FR64:$src1, FR64:$src2),
1234 "xorpd\t{$src2, $dst|$dst, $src2}",
1235 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1238 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1239 (ins FR64:$src1, f128mem:$src2),
1240 "andpd\t{$src2, $dst|$dst, $src2}",
1241 [(set FR64:$dst, (X86fand FR64:$src1,
1242 (memopfsf64 addr:$src2)))]>;
1243 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1244 (ins FR64:$src1, f128mem:$src2),
1245 "orpd\t{$src2, $dst|$dst, $src2}",
1246 [(set FR64:$dst, (X86for FR64:$src1,
1247 (memopfsf64 addr:$src2)))]>;
1248 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1249 (ins FR64:$src1, f128mem:$src2),
1250 "xorpd\t{$src2, $dst|$dst, $src2}",
1251 [(set FR64:$dst, (X86fxor FR64:$src1,
1252 (memopfsf64 addr:$src2)))]>;
1254 let neverHasSideEffects = 1 in {
1255 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1256 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1257 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1259 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1260 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1261 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1265 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1267 /// In addition, we also have a special variant of the scalar form here to
1268 /// represent the associated intrinsic operation. This form is unlike the
1269 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1270 /// and leaves the top elements undefined.
1272 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1273 /// six "instructions".
1275 let Constraints = "$src1 = $dst" in {
1276 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1277 SDNode OpNode, Intrinsic F64Int,
1278 bit Commutable = 0> {
1279 // Scalar operation, reg+reg.
1280 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1281 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1282 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1283 let isCommutable = Commutable;
1286 // Scalar operation, reg+mem.
1287 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1288 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1289 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1291 // Vector operation, reg+reg.
1292 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1293 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1294 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1295 let isCommutable = Commutable;
1298 // Vector operation, reg+mem.
1299 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1300 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1301 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1303 // Intrinsic operation, reg+reg.
1304 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1305 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1306 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1307 let isCommutable = Commutable;
1310 // Intrinsic operation, reg+mem.
1311 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1312 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1313 [(set VR128:$dst, (F64Int VR128:$src1,
1314 sse_load_f64:$src2))]>;
1318 // Arithmetic instructions
1319 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1320 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1321 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1322 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1324 /// sse2_fp_binop_rm - Other SSE2 binops
1326 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1327 /// instructions for a full-vector intrinsic form. Operations that map
1328 /// onto C operators don't use this form since they just use the plain
1329 /// vector form instead of having a separate vector intrinsic form.
1331 /// This provides a total of eight "instructions".
1333 let Constraints = "$src1 = $dst" in {
1334 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1338 bit Commutable = 0> {
1340 // Scalar operation, reg+reg.
1341 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1342 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1343 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1344 let isCommutable = Commutable;
1347 // Scalar operation, reg+mem.
1348 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1349 (ins FR64:$src1, f64mem:$src2),
1350 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1351 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1353 // Vector operation, reg+reg.
1354 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1357 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1358 let isCommutable = Commutable;
1361 // Vector operation, reg+mem.
1362 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1363 (ins VR128:$src1, f128mem:$src2),
1364 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1365 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1367 // Intrinsic operation, reg+reg.
1368 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1369 (ins VR128:$src1, VR128:$src2),
1370 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1371 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1372 let isCommutable = Commutable;
1375 // Intrinsic operation, reg+mem.
1376 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1377 (ins VR128:$src1, sdmem:$src2),
1378 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1379 [(set VR128:$dst, (F64Int VR128:$src1,
1380 sse_load_f64:$src2))]>;
1382 // Vector intrinsic operation, reg+reg.
1383 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1384 (ins VR128:$src1, VR128:$src2),
1385 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1386 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1387 let isCommutable = Commutable;
1390 // Vector intrinsic operation, reg+mem.
1391 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1392 (ins VR128:$src1, f128mem:$src2),
1393 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1394 [(set VR128:$dst, (V2F64Int VR128:$src1,
1395 (memopv2f64 addr:$src2)))]>;
1399 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1400 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1401 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1402 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1404 //===----------------------------------------------------------------------===//
1405 // SSE packed FP Instructions
1407 // Move Instructions
1408 let neverHasSideEffects = 1 in
1409 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1410 "movapd\t{$src, $dst|$dst, $src}", []>;
1411 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1412 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1413 "movapd\t{$src, $dst|$dst, $src}",
1414 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1416 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1417 "movapd\t{$src, $dst|$dst, $src}",
1418 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1420 let neverHasSideEffects = 1 in
1421 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1422 "movupd\t{$src, $dst|$dst, $src}", []>;
1423 let isSimpleLoad = 1 in
1424 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1425 "movupd\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1427 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1428 "movupd\t{$src, $dst|$dst, $src}",
1429 [(store (v2f64 VR128:$src), addr:$dst)]>;
1431 // Intrinsic forms of MOVUPD load and store
1432 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1433 "movupd\t{$src, $dst|$dst, $src}",
1434 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1435 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1436 "movupd\t{$src, $dst|$dst, $src}",
1437 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1439 let Constraints = "$src1 = $dst" in {
1440 let AddedComplexity = 20 in {
1441 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1442 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1443 "movlpd\t{$src2, $dst|$dst, $src2}",
1445 (v2f64 (vector_shuffle VR128:$src1,
1446 (scalar_to_vector (loadf64 addr:$src2)),
1447 MOVLP_shuffle_mask)))]>;
1448 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1449 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1450 "movhpd\t{$src2, $dst|$dst, $src2}",
1452 (v2f64 (vector_shuffle VR128:$src1,
1453 (scalar_to_vector (loadf64 addr:$src2)),
1454 MOVHP_shuffle_mask)))]>;
1455 } // AddedComplexity
1456 } // Constraints = "$src1 = $dst"
1458 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1459 "movlpd\t{$src, $dst|$dst, $src}",
1460 [(store (f64 (vector_extract (v2f64 VR128:$src),
1461 (iPTR 0))), addr:$dst)]>;
1463 // v2f64 extract element 1 is always custom lowered to unpack high to low
1464 // and extract element 0 so the non-store version isn't too horrible.
1465 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1466 "movhpd\t{$src, $dst|$dst, $src}",
1467 [(store (f64 (vector_extract
1468 (v2f64 (vector_shuffle VR128:$src, (undef),
1469 UNPCKH_shuffle_mask)), (iPTR 0))),
1472 // SSE2 instructions without OpSize prefix
1473 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1474 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1475 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1476 TB, Requires<[HasSSE2]>;
1477 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1478 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1479 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1480 (bitconvert (memopv2i64 addr:$src))))]>,
1481 TB, Requires<[HasSSE2]>;
1483 // SSE2 instructions with XS prefix
1484 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1485 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1486 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1487 XS, Requires<[HasSSE2]>;
1488 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1489 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1490 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1491 (bitconvert (memopv2i64 addr:$src))))]>,
1492 XS, Requires<[HasSSE2]>;
1494 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1495 "cvtps2dq\t{$src, $dst|$dst, $src}",
1496 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1497 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1498 "cvtps2dq\t{$src, $dst|$dst, $src}",
1499 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1500 (memop addr:$src)))]>;
1501 // SSE2 packed instructions with XS prefix
1502 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1503 "cvttps2dq\t{$src, $dst|$dst, $src}",
1504 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1505 XS, Requires<[HasSSE2]>;
1506 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1507 "cvttps2dq\t{$src, $dst|$dst, $src}",
1508 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1509 (memop addr:$src)))]>,
1510 XS, Requires<[HasSSE2]>;
1512 // SSE2 packed instructions with XD prefix
1513 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1514 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1515 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1516 XD, Requires<[HasSSE2]>;
1517 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1518 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1519 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1520 (memop addr:$src)))]>,
1521 XD, Requires<[HasSSE2]>;
1523 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1524 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1525 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1526 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1527 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1528 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1529 (memop addr:$src)))]>;
1531 // SSE2 instructions without OpSize prefix
1532 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1533 "cvtps2pd\t{$src, $dst|$dst, $src}",
1534 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1535 TB, Requires<[HasSSE2]>;
1536 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1537 "cvtps2pd\t{$src, $dst|$dst, $src}",
1538 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1539 (load addr:$src)))]>,
1540 TB, Requires<[HasSSE2]>;
1542 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1543 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1544 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1545 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1546 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1547 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1548 (memop addr:$src)))]>;
1550 // Match intrinsics which expect XMM operand(s).
1551 // Aliases for intrinsics
1552 let Constraints = "$src1 = $dst" in {
1553 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1554 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1555 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1556 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1558 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1559 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1560 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1561 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1562 (loadi32 addr:$src2)))]>;
1563 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1564 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1565 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1566 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1568 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1569 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1570 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1571 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1572 (load addr:$src2)))]>;
1573 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1575 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1576 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1577 VR128:$src2))]>, XS,
1578 Requires<[HasSSE2]>;
1579 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1580 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1581 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1582 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1583 (load addr:$src2)))]>, XS,
1584 Requires<[HasSSE2]>;
1589 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1591 /// In addition, we also have a special variant of the scalar form here to
1592 /// represent the associated intrinsic operation. This form is unlike the
1593 /// plain scalar form, in that it takes an entire vector (instead of a
1594 /// scalar) and leaves the top elements undefined.
1596 /// And, we have a special variant form for a full-vector intrinsic form.
1598 /// These four forms can each have a reg or a mem operand, so there are a
1599 /// total of eight "instructions".
1601 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1605 bit Commutable = 0> {
1606 // Scalar operation, reg.
1607 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1608 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1609 [(set FR64:$dst, (OpNode FR64:$src))]> {
1610 let isCommutable = Commutable;
1613 // Scalar operation, mem.
1614 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1615 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1616 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1618 // Vector operation, reg.
1619 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1620 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1621 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1622 let isCommutable = Commutable;
1625 // Vector operation, mem.
1626 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1627 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1628 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1630 // Intrinsic operation, reg.
1631 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1633 [(set VR128:$dst, (F64Int VR128:$src))]> {
1634 let isCommutable = Commutable;
1637 // Intrinsic operation, mem.
1638 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1639 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1640 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1642 // Vector intrinsic operation, reg
1643 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1644 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1645 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1646 let isCommutable = Commutable;
1649 // Vector intrinsic operation, mem
1650 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1651 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1652 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1656 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1657 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1659 // There is no f64 version of the reciprocal approximation instructions.
1662 let Constraints = "$src1 = $dst" in {
1663 let isCommutable = 1 in {
1664 def ANDPDrr : PDI<0x54, MRMSrcReg,
1665 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1666 "andpd\t{$src2, $dst|$dst, $src2}",
1668 (and (bc_v2i64 (v2f64 VR128:$src1)),
1669 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1670 def ORPDrr : PDI<0x56, MRMSrcReg,
1671 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1672 "orpd\t{$src2, $dst|$dst, $src2}",
1674 (or (bc_v2i64 (v2f64 VR128:$src1)),
1675 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1676 def XORPDrr : PDI<0x57, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "xorpd\t{$src2, $dst|$dst, $src2}",
1680 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1681 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1684 def ANDPDrm : PDI<0x54, MRMSrcMem,
1685 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1686 "andpd\t{$src2, $dst|$dst, $src2}",
1688 (and (bc_v2i64 (v2f64 VR128:$src1)),
1689 (memopv2i64 addr:$src2)))]>;
1690 def ORPDrm : PDI<0x56, MRMSrcMem,
1691 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1692 "orpd\t{$src2, $dst|$dst, $src2}",
1694 (or (bc_v2i64 (v2f64 VR128:$src1)),
1695 (memopv2i64 addr:$src2)))]>;
1696 def XORPDrm : PDI<0x57, MRMSrcMem,
1697 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1698 "xorpd\t{$src2, $dst|$dst, $src2}",
1700 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1701 (memopv2i64 addr:$src2)))]>;
1702 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1703 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1704 "andnpd\t{$src2, $dst|$dst, $src2}",
1706 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1707 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1708 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1709 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1710 "andnpd\t{$src2, $dst|$dst, $src2}",
1712 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1713 (memopv2i64 addr:$src2)))]>;
1716 let Constraints = "$src1 = $dst" in {
1717 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1718 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1719 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1720 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1721 VR128:$src, imm:$cc))]>;
1722 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1723 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1724 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1725 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1726 (memop addr:$src), imm:$cc))]>;
1728 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1729 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1730 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1731 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1733 // Shuffle and unpack instructions
1734 let Constraints = "$src1 = $dst" in {
1735 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1736 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1737 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1738 [(set VR128:$dst, (v2f64 (vector_shuffle
1739 VR128:$src1, VR128:$src2,
1740 SHUFP_shuffle_mask:$src3)))]>;
1741 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1742 (outs VR128:$dst), (ins VR128:$src1,
1743 f128mem:$src2, i8imm:$src3),
1744 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 (v2f64 (vector_shuffle
1747 VR128:$src1, (memopv2f64 addr:$src2),
1748 SHUFP_shuffle_mask:$src3)))]>;
1750 let AddedComplexity = 10 in {
1751 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1752 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1753 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1755 (v2f64 (vector_shuffle
1756 VR128:$src1, VR128:$src2,
1757 UNPCKH_shuffle_mask)))]>;
1758 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1759 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1760 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1762 (v2f64 (vector_shuffle
1763 VR128:$src1, (memopv2f64 addr:$src2),
1764 UNPCKH_shuffle_mask)))]>;
1766 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1767 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1768 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1770 (v2f64 (vector_shuffle
1771 VR128:$src1, VR128:$src2,
1772 UNPCKL_shuffle_mask)))]>;
1773 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1775 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1777 (v2f64 (vector_shuffle
1778 VR128:$src1, (memopv2f64 addr:$src2),
1779 UNPCKL_shuffle_mask)))]>;
1780 } // AddedComplexity
1781 } // Constraints = "$src1 = $dst"
1784 //===----------------------------------------------------------------------===//
1785 // SSE integer instructions
1787 // Move Instructions
1788 let neverHasSideEffects = 1 in
1789 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1790 "movdqa\t{$src, $dst|$dst, $src}", []>;
1791 let isSimpleLoad = 1, mayLoad = 1 in
1792 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1793 "movdqa\t{$src, $dst|$dst, $src}",
1794 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1796 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1797 "movdqa\t{$src, $dst|$dst, $src}",
1798 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1799 let isSimpleLoad = 1, mayLoad = 1 in
1800 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1801 "movdqu\t{$src, $dst|$dst, $src}",
1802 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1803 XS, Requires<[HasSSE2]>;
1805 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1806 "movdqu\t{$src, $dst|$dst, $src}",
1807 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1808 XS, Requires<[HasSSE2]>;
1810 // Intrinsic forms of MOVDQU load and store
1811 let isSimpleLoad = 1 in
1812 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1813 "movdqu\t{$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1815 XS, Requires<[HasSSE2]>;
1816 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1817 "movdqu\t{$src, $dst|$dst, $src}",
1818 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1819 XS, Requires<[HasSSE2]>;
1821 let Constraints = "$src1 = $dst" in {
1823 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1824 bit Commutable = 0> {
1825 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1827 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1828 let isCommutable = Commutable;
1830 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1832 [(set VR128:$dst, (IntId VR128:$src1,
1833 (bitconvert (memopv2i64 addr:$src2))))]>;
1836 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1838 Intrinsic IntId, Intrinsic IntId2> {
1839 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1841 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1842 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId VR128:$src1,
1845 (bitconvert (memopv2i64 addr:$src2))))]>;
1846 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1847 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1848 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1851 /// PDI_binop_rm - Simple SSE2 binary operator.
1852 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1853 ValueType OpVT, bit Commutable = 0> {
1854 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1856 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1857 let isCommutable = Commutable;
1859 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1860 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1861 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1862 (bitconvert (memopv2i64 addr:$src2)))))]>;
1865 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1867 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1868 /// to collapse (bitconvert VT to VT) into its operand.
1870 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1871 bit Commutable = 0> {
1872 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1873 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1874 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1875 let isCommutable = Commutable;
1877 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1878 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1879 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1882 } // Constraints = "$src1 = $dst"
1884 // 128-bit Integer Arithmetic
1886 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1887 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1888 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1889 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1891 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1892 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1893 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1894 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1896 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1897 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1898 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1899 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1901 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1902 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1903 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1904 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1906 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1908 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1909 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1910 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1912 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1914 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1915 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1918 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1919 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1920 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1921 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1922 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1925 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1926 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1927 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1928 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1929 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1930 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1932 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1933 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1934 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1935 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1936 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1937 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1939 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1940 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1941 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1942 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1944 // 128-bit logical shifts.
1945 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1946 def PSLLDQri : PDIi8<0x73, MRM7r,
1947 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1948 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1949 def PSRLDQri : PDIi8<0x73, MRM3r,
1950 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1951 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1952 // PSRADQri doesn't exist in SSE[1-3].
1955 let Predicates = [HasSSE2] in {
1956 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1957 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1958 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1959 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1960 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1961 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1962 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1963 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1964 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1965 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1967 // Shift up / down and insert zero's.
1968 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1969 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1970 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1971 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1975 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1976 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1977 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1979 let Constraints = "$src1 = $dst" in {
1980 def PANDNrr : PDI<0xDF, MRMSrcReg,
1981 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1982 "pandn\t{$src2, $dst|$dst, $src2}",
1983 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1986 def PANDNrm : PDI<0xDF, MRMSrcMem,
1987 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1988 "pandn\t{$src2, $dst|$dst, $src2}",
1989 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1990 (memopv2i64 addr:$src2))))]>;
1993 // SSE2 Integer comparison
1994 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1995 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1996 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1997 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1998 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1999 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2001 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2002 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2003 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2004 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2005 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2006 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2007 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2008 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2009 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2010 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2011 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2012 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2014 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2015 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2016 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2017 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2018 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2019 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2020 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2021 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2022 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2023 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2024 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2025 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2028 // Pack instructions
2029 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2030 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2031 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2033 // Shuffle and unpack instructions
2034 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2035 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2036 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2037 [(set VR128:$dst, (v4i32 (vector_shuffle
2038 VR128:$src1, (undef),
2039 PSHUFD_shuffle_mask:$src2)))]>;
2040 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2041 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2042 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2043 [(set VR128:$dst, (v4i32 (vector_shuffle
2044 (bc_v4i32(memopv2i64 addr:$src1)),
2046 PSHUFD_shuffle_mask:$src2)))]>;
2048 // SSE2 with ImmT == Imm8 and XS prefix.
2049 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2050 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2051 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2052 [(set VR128:$dst, (v8i16 (vector_shuffle
2053 VR128:$src1, (undef),
2054 PSHUFHW_shuffle_mask:$src2)))]>,
2055 XS, Requires<[HasSSE2]>;
2056 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2057 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2058 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2059 [(set VR128:$dst, (v8i16 (vector_shuffle
2060 (bc_v8i16 (memopv2i64 addr:$src1)),
2062 PSHUFHW_shuffle_mask:$src2)))]>,
2063 XS, Requires<[HasSSE2]>;
2065 // SSE2 with ImmT == Imm8 and XD prefix.
2066 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2067 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2068 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2069 [(set VR128:$dst, (v8i16 (vector_shuffle
2070 VR128:$src1, (undef),
2071 PSHUFLW_shuffle_mask:$src2)))]>,
2072 XD, Requires<[HasSSE2]>;
2073 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2074 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2075 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2076 [(set VR128:$dst, (v8i16 (vector_shuffle
2077 (bc_v8i16 (memopv2i64 addr:$src1)),
2079 PSHUFLW_shuffle_mask:$src2)))]>,
2080 XD, Requires<[HasSSE2]>;
2083 let Constraints = "$src1 = $dst" in {
2084 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2085 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2086 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2088 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2089 UNPCKL_shuffle_mask)))]>;
2090 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2091 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2092 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2094 (v16i8 (vector_shuffle VR128:$src1,
2095 (bc_v16i8 (memopv2i64 addr:$src2)),
2096 UNPCKL_shuffle_mask)))]>;
2097 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2098 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2099 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2101 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2102 UNPCKL_shuffle_mask)))]>;
2103 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2104 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2105 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2107 (v8i16 (vector_shuffle VR128:$src1,
2108 (bc_v8i16 (memopv2i64 addr:$src2)),
2109 UNPCKL_shuffle_mask)))]>;
2110 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2111 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2112 "punpckldq\t{$src2, $dst|$dst, $src2}",
2114 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2115 UNPCKL_shuffle_mask)))]>;
2116 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2117 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2118 "punpckldq\t{$src2, $dst|$dst, $src2}",
2120 (v4i32 (vector_shuffle VR128:$src1,
2121 (bc_v4i32 (memopv2i64 addr:$src2)),
2122 UNPCKL_shuffle_mask)))]>;
2123 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2124 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2125 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2127 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2128 UNPCKL_shuffle_mask)))]>;
2129 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2130 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2131 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2133 (v2i64 (vector_shuffle VR128:$src1,
2134 (memopv2i64 addr:$src2),
2135 UNPCKL_shuffle_mask)))]>;
2137 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2138 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2139 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2141 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2142 UNPCKH_shuffle_mask)))]>;
2143 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2144 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2145 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2147 (v16i8 (vector_shuffle VR128:$src1,
2148 (bc_v16i8 (memopv2i64 addr:$src2)),
2149 UNPCKH_shuffle_mask)))]>;
2150 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2151 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2152 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2154 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2155 UNPCKH_shuffle_mask)))]>;
2156 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2157 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2158 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2160 (v8i16 (vector_shuffle VR128:$src1,
2161 (bc_v8i16 (memopv2i64 addr:$src2)),
2162 UNPCKH_shuffle_mask)))]>;
2163 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2164 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2165 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2167 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2168 UNPCKH_shuffle_mask)))]>;
2169 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2170 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2171 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2173 (v4i32 (vector_shuffle VR128:$src1,
2174 (bc_v4i32 (memopv2i64 addr:$src2)),
2175 UNPCKH_shuffle_mask)))]>;
2176 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2177 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2178 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2180 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2181 UNPCKH_shuffle_mask)))]>;
2182 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2183 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2184 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2186 (v2i64 (vector_shuffle VR128:$src1,
2187 (memopv2i64 addr:$src2),
2188 UNPCKH_shuffle_mask)))]>;
2192 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2193 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2194 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2195 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2197 let Constraints = "$src1 = $dst" in {
2198 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2199 (outs VR128:$dst), (ins VR128:$src1,
2200 GR32:$src2, i32i8imm:$src3),
2201 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2203 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2204 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2205 (outs VR128:$dst), (ins VR128:$src1,
2206 i16mem:$src2, i32i8imm:$src3),
2207 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2209 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2214 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2215 "pmovmskb\t{$src, $dst|$dst, $src}",
2216 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2218 // Conditional store
2220 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2221 "maskmovdqu\t{$mask, $src|$src, $mask}",
2222 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2224 // Non-temporal stores
2225 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2226 "movntpd\t{$src, $dst|$dst, $src}",
2227 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2228 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2229 "movntdq\t{$src, $dst|$dst, $src}",
2230 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2231 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2232 "movnti\t{$src, $dst|$dst, $src}",
2233 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2234 TB, Requires<[HasSSE2]>;
2237 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2238 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2239 TB, Requires<[HasSSE2]>;
2241 // Load, store, and memory fence
2242 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2243 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2244 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2245 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2247 //TODO: custom lower this so as to never even generate the noop
2248 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2250 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2251 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2252 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2255 // Alias instructions that map zero vector to pxor / xorp* for sse.
2256 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2257 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2258 "pcmpeqd\t$dst, $dst",
2259 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2261 // FR64 to 128-bit vector conversion.
2262 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2263 "movsd\t{$src, $dst|$dst, $src}",
2265 (v2f64 (scalar_to_vector FR64:$src)))]>;
2266 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2267 "movsd\t{$src, $dst|$dst, $src}",
2269 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2271 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2272 "movd\t{$src, $dst|$dst, $src}",
2274 (v4i32 (scalar_to_vector GR32:$src)))]>;
2275 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2276 "movd\t{$src, $dst|$dst, $src}",
2278 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2280 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2281 "movd\t{$src, $dst|$dst, $src}",
2282 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2284 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2285 "movd\t{$src, $dst|$dst, $src}",
2286 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2288 // SSE2 instructions with XS prefix
2289 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2290 "movq\t{$src, $dst|$dst, $src}",
2292 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2293 Requires<[HasSSE2]>;
2294 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2295 "movq\t{$src, $dst|$dst, $src}",
2296 [(store (i64 (vector_extract (v2i64 VR128:$src),
2297 (iPTR 0))), addr:$dst)]>;
2299 // FIXME: may not be able to eliminate this movss with coalescing the src and
2300 // dest register classes are different. We really want to write this pattern
2302 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2303 // (f32 FR32:$src)>;
2304 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2305 "movsd\t{$src, $dst|$dst, $src}",
2306 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2308 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2309 "movsd\t{$src, $dst|$dst, $src}",
2310 [(store (f64 (vector_extract (v2f64 VR128:$src),
2311 (iPTR 0))), addr:$dst)]>;
2312 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2313 "movd\t{$src, $dst|$dst, $src}",
2314 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2316 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2317 "movd\t{$src, $dst|$dst, $src}",
2318 [(store (i32 (vector_extract (v4i32 VR128:$src),
2319 (iPTR 0))), addr:$dst)]>;
2321 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2322 "movd\t{$src, $dst|$dst, $src}",
2323 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2324 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2325 "movd\t{$src, $dst|$dst, $src}",
2326 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2329 // Move to lower bits of a VR128, leaving upper bits alone.
2330 // Three operand (but two address) aliases.
2331 let Constraints = "$src1 = $dst" in {
2332 let neverHasSideEffects = 1 in
2333 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2334 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2335 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2337 let AddedComplexity = 15 in
2338 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2339 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2340 "movsd\t{$src2, $dst|$dst, $src2}",
2342 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2343 MOVL_shuffle_mask)))]>;
2346 // Store / copy lower 64-bits of a XMM register.
2347 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2348 "movq\t{$src, $dst|$dst, $src}",
2349 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2351 // Move to lower bits of a VR128 and zeroing upper bits.
2352 // Loading from memory automatically zeroing upper bits.
2353 let AddedComplexity = 20 in {
2354 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2355 "movsd\t{$src, $dst|$dst, $src}",
2357 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2358 (loadf64 addr:$src))))))]>;
2360 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2361 (MOVZSD2PDrm addr:$src)>;
2362 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2363 (MOVZSD2PDrm addr:$src)>;
2364 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2367 // movd / movq to XMM register zero-extends
2368 let AddedComplexity = 15 in {
2369 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2370 "movd\t{$src, $dst|$dst, $src}",
2371 [(set VR128:$dst, (v4i32 (X86vzmovl
2372 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2373 // This is X86-64 only.
2374 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2375 "mov{d|q}\t{$src, $dst|$dst, $src}",
2376 [(set VR128:$dst, (v2i64 (X86vzmovl
2377 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2380 let AddedComplexity = 20 in {
2381 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2382 "movd\t{$src, $dst|$dst, $src}",
2384 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2385 (loadi32 addr:$src))))))]>;
2387 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2388 (MOVZDI2PDIrm addr:$src)>;
2389 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2390 (MOVZDI2PDIrm addr:$src)>;
2391 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2392 (MOVZDI2PDIrm addr:$src)>;
2394 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2395 "movq\t{$src, $dst|$dst, $src}",
2397 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2398 (loadi64 addr:$src))))))]>, XS,
2399 Requires<[HasSSE2]>;
2401 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2402 (MOVZQI2PQIrm addr:$src)>;
2403 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2404 (MOVZQI2PQIrm addr:$src)>;
2405 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2408 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2409 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2410 let AddedComplexity = 15 in
2411 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2412 "movq\t{$src, $dst|$dst, $src}",
2413 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2414 XS, Requires<[HasSSE2]>;
2416 let AddedComplexity = 20 in {
2417 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2418 "movq\t{$src, $dst|$dst, $src}",
2419 [(set VR128:$dst, (v2i64 (X86vzmovl
2420 (loadv2i64 addr:$src))))]>,
2421 XS, Requires<[HasSSE2]>;
2423 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2424 (MOVZPQILo2PQIrm addr:$src)>;
2427 //===----------------------------------------------------------------------===//
2428 // SSE3 Instructions
2429 //===----------------------------------------------------------------------===//
2431 // Move Instructions
2432 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2433 "movshdup\t{$src, $dst|$dst, $src}",
2434 [(set VR128:$dst, (v4f32 (vector_shuffle
2435 VR128:$src, (undef),
2436 MOVSHDUP_shuffle_mask)))]>;
2437 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2438 "movshdup\t{$src, $dst|$dst, $src}",
2439 [(set VR128:$dst, (v4f32 (vector_shuffle
2440 (memopv4f32 addr:$src), (undef),
2441 MOVSHDUP_shuffle_mask)))]>;
2443 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2444 "movsldup\t{$src, $dst|$dst, $src}",
2445 [(set VR128:$dst, (v4f32 (vector_shuffle
2446 VR128:$src, (undef),
2447 MOVSLDUP_shuffle_mask)))]>;
2448 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2449 "movsldup\t{$src, $dst|$dst, $src}",
2450 [(set VR128:$dst, (v4f32 (vector_shuffle
2451 (memopv4f32 addr:$src), (undef),
2452 MOVSLDUP_shuffle_mask)))]>;
2454 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2455 "movddup\t{$src, $dst|$dst, $src}",
2457 (v2f64 (vector_shuffle VR128:$src, (undef),
2458 MOVDDUP_shuffle_mask)))]>;
2459 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2460 "movddup\t{$src, $dst|$dst, $src}",
2462 (v2f64 (vector_shuffle
2463 (scalar_to_vector (loadf64 addr:$src)),
2464 (undef), MOVDDUP_shuffle_mask)))]>;
2466 def : Pat<(vector_shuffle
2467 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2468 (undef), MOVDDUP_shuffle_mask),
2469 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2470 def : Pat<(vector_shuffle
2471 (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
2472 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2476 let Constraints = "$src1 = $dst" in {
2477 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2478 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2479 "addsubps\t{$src2, $dst|$dst, $src2}",
2480 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2482 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2483 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2484 "addsubps\t{$src2, $dst|$dst, $src2}",
2485 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2486 (memop addr:$src2)))]>;
2487 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2488 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2489 "addsubpd\t{$src2, $dst|$dst, $src2}",
2490 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2492 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2493 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2494 "addsubpd\t{$src2, $dst|$dst, $src2}",
2495 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2496 (memop addr:$src2)))]>;
2499 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2500 "lddqu\t{$src, $dst|$dst, $src}",
2501 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2504 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2505 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2506 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2507 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2508 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2509 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2510 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2511 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2512 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2513 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2514 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2515 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2516 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2517 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2519 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2521 let Constraints = "$src1 = $dst" in {
2522 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2523 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2524 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2525 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2526 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2527 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2528 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2529 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2532 // Thread synchronization
2533 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2534 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2535 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2536 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2538 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2539 let AddedComplexity = 15 in
2540 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2541 MOVSHDUP_shuffle_mask)),
2542 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2543 let AddedComplexity = 20 in
2544 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2545 MOVSHDUP_shuffle_mask)),
2546 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2548 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2549 let AddedComplexity = 15 in
2550 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2551 MOVSLDUP_shuffle_mask)),
2552 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2553 let AddedComplexity = 20 in
2554 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2555 MOVSLDUP_shuffle_mask)),
2556 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2558 //===----------------------------------------------------------------------===//
2559 // SSSE3 Instructions
2560 //===----------------------------------------------------------------------===//
2562 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2563 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2564 Intrinsic IntId64, Intrinsic IntId128> {
2565 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2567 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2569 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2572 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2574 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2576 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2577 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2580 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2582 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2585 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2588 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2589 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2590 Intrinsic IntId64, Intrinsic IntId128> {
2591 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2594 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2596 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2601 (bitconvert (memopv4i16 addr:$src))))]>;
2603 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2606 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2609 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2614 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2617 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2618 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2619 Intrinsic IntId64, Intrinsic IntId128> {
2620 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2622 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2623 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2625 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2630 (bitconvert (memopv2i32 addr:$src))))]>;
2632 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2635 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2638 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2640 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2643 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2646 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2647 int_x86_ssse3_pabs_b,
2648 int_x86_ssse3_pabs_b_128>;
2649 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2650 int_x86_ssse3_pabs_w,
2651 int_x86_ssse3_pabs_w_128>;
2652 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2653 int_x86_ssse3_pabs_d,
2654 int_x86_ssse3_pabs_d_128>;
2656 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2657 let Constraints = "$src1 = $dst" in {
2658 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2659 Intrinsic IntId64, Intrinsic IntId128,
2660 bit Commutable = 0> {
2661 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2662 (ins VR64:$src1, VR64:$src2),
2663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2664 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2665 let isCommutable = Commutable;
2667 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2668 (ins VR64:$src1, i64mem:$src2),
2669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2671 (IntId64 VR64:$src1,
2672 (bitconvert (memopv8i8 addr:$src2))))]>;
2674 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2675 (ins VR128:$src1, VR128:$src2),
2676 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2677 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2679 let isCommutable = Commutable;
2681 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2682 (ins VR128:$src1, i128mem:$src2),
2683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2685 (IntId128 VR128:$src1,
2686 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2690 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2691 let Constraints = "$src1 = $dst" in {
2692 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2693 Intrinsic IntId64, Intrinsic IntId128,
2694 bit Commutable = 0> {
2695 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2696 (ins VR64:$src1, VR64:$src2),
2697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2698 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2699 let isCommutable = Commutable;
2701 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2702 (ins VR64:$src1, i64mem:$src2),
2703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2705 (IntId64 VR64:$src1,
2706 (bitconvert (memopv4i16 addr:$src2))))]>;
2708 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2709 (ins VR128:$src1, VR128:$src2),
2710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2711 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2713 let isCommutable = Commutable;
2715 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2716 (ins VR128:$src1, i128mem:$src2),
2717 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2719 (IntId128 VR128:$src1,
2720 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2724 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2725 let Constraints = "$src1 = $dst" in {
2726 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2727 Intrinsic IntId64, Intrinsic IntId128,
2728 bit Commutable = 0> {
2729 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2730 (ins VR64:$src1, VR64:$src2),
2731 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2732 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2733 let isCommutable = Commutable;
2735 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2736 (ins VR64:$src1, i64mem:$src2),
2737 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2739 (IntId64 VR64:$src1,
2740 (bitconvert (memopv2i32 addr:$src2))))]>;
2742 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2743 (ins VR128:$src1, VR128:$src2),
2744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2745 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2747 let isCommutable = Commutable;
2749 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2750 (ins VR128:$src1, i128mem:$src2),
2751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2753 (IntId128 VR128:$src1,
2754 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2758 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2759 int_x86_ssse3_phadd_w,
2760 int_x86_ssse3_phadd_w_128>;
2761 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2762 int_x86_ssse3_phadd_d,
2763 int_x86_ssse3_phadd_d_128>;
2764 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2765 int_x86_ssse3_phadd_sw,
2766 int_x86_ssse3_phadd_sw_128>;
2767 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2768 int_x86_ssse3_phsub_w,
2769 int_x86_ssse3_phsub_w_128>;
2770 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2771 int_x86_ssse3_phsub_d,
2772 int_x86_ssse3_phsub_d_128>;
2773 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2774 int_x86_ssse3_phsub_sw,
2775 int_x86_ssse3_phsub_sw_128>;
2776 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2777 int_x86_ssse3_pmadd_ub_sw,
2778 int_x86_ssse3_pmadd_ub_sw_128>;
2779 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2780 int_x86_ssse3_pmul_hr_sw,
2781 int_x86_ssse3_pmul_hr_sw_128, 1>;
2782 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2783 int_x86_ssse3_pshuf_b,
2784 int_x86_ssse3_pshuf_b_128>;
2785 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2786 int_x86_ssse3_psign_b,
2787 int_x86_ssse3_psign_b_128>;
2788 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2789 int_x86_ssse3_psign_w,
2790 int_x86_ssse3_psign_w_128>;
2791 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2792 int_x86_ssse3_psign_d,
2793 int_x86_ssse3_psign_d_128>;
2795 let Constraints = "$src1 = $dst" in {
2796 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2797 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2798 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2800 (int_x86_ssse3_palign_r
2801 VR64:$src1, VR64:$src2,
2803 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2804 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2805 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2807 (int_x86_ssse3_palign_r
2809 (bitconvert (memopv2i32 addr:$src2)),
2812 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2813 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2814 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2816 (int_x86_ssse3_palign_r_128
2817 VR128:$src1, VR128:$src2,
2818 imm:$src3))]>, OpSize;
2819 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2820 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2821 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2823 (int_x86_ssse3_palign_r_128
2825 (bitconvert (memopv4i32 addr:$src2)),
2826 imm:$src3))]>, OpSize;
2829 //===----------------------------------------------------------------------===//
2830 // Non-Instruction Patterns
2831 //===----------------------------------------------------------------------===//
2833 // extload f32 -> f64. This matches load+fextend because we have a hack in
2834 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2835 // Since these loads aren't folded into the fextend, we have to match it
2837 let Predicates = [HasSSE2] in
2838 def : Pat<(fextend (loadf32 addr:$src)),
2839 (CVTSS2SDrm addr:$src)>;
2842 let Predicates = [HasSSE2] in {
2843 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2844 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2845 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2846 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2847 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2848 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2849 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2850 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2851 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2852 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2853 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2854 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2855 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2856 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2857 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2858 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2859 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2860 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2861 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2862 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2863 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2864 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2865 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2866 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2867 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2868 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2869 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2870 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2871 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2872 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2875 // Move scalar to XMM zero-extended
2876 // movd to XMM register zero-extends
2877 let AddedComplexity = 15 in {
2878 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2879 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2880 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2881 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2882 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2883 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2884 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2885 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2886 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2889 // Splat v2f64 / v2i64
2890 let AddedComplexity = 10 in {
2891 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2892 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2893 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2894 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2895 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2896 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2897 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2898 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2901 // Special unary SHUFPSrri case.
2902 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2903 SHUFP_unary_shuffle_mask:$sm)),
2904 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2905 Requires<[HasSSE1]>;
2906 // Special unary SHUFPDrri case.
2907 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2908 SHUFP_unary_shuffle_mask:$sm)),
2909 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2910 Requires<[HasSSE2]>;
2911 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2912 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2913 SHUFP_unary_shuffle_mask:$sm),
2914 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2915 Requires<[HasSSE2]>;
2917 // Special binary v4i32 shuffle cases with SHUFPS.
2918 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2919 PSHUFD_binary_shuffle_mask:$sm)),
2920 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2921 Requires<[HasSSE2]>;
2922 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2923 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2924 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2925 Requires<[HasSSE2]>;
2926 // Special binary v2i64 shuffle cases using SHUFPDrri.
2927 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2928 SHUFP_shuffle_mask:$sm)),
2929 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2930 Requires<[HasSSE2]>;
2931 // Special unary SHUFPDrri case.
2932 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2933 SHUFP_unary_shuffle_mask:$sm)),
2934 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2935 Requires<[HasSSE2]>;
2937 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2938 let AddedComplexity = 15 in {
2939 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2940 UNPCKL_v_undef_shuffle_mask:$sm)),
2941 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2942 Requires<[OptForSpeed, HasSSE2]>;
2943 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2944 UNPCKL_v_undef_shuffle_mask:$sm)),
2945 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2946 Requires<[OptForSpeed, HasSSE2]>;
2948 let AddedComplexity = 10 in {
2949 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2950 UNPCKL_v_undef_shuffle_mask)),
2951 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2952 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2953 UNPCKL_v_undef_shuffle_mask)),
2954 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2955 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2956 UNPCKL_v_undef_shuffle_mask)),
2957 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2958 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2959 UNPCKL_v_undef_shuffle_mask)),
2960 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2963 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2964 let AddedComplexity = 15 in {
2965 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2966 UNPCKH_v_undef_shuffle_mask:$sm)),
2967 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2968 Requires<[OptForSpeed, HasSSE2]>;
2969 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2970 UNPCKH_v_undef_shuffle_mask:$sm)),
2971 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2972 Requires<[OptForSpeed, HasSSE2]>;
2974 let AddedComplexity = 10 in {
2975 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2976 UNPCKH_v_undef_shuffle_mask)),
2977 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2978 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2979 UNPCKH_v_undef_shuffle_mask)),
2980 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2981 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2982 UNPCKH_v_undef_shuffle_mask)),
2983 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2984 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2985 UNPCKH_v_undef_shuffle_mask)),
2986 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2989 let AddedComplexity = 20 in {
2990 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2991 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2992 MOVHP_shuffle_mask)),
2993 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2995 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2996 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2997 MOVHLPS_shuffle_mask)),
2998 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3000 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3001 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
3002 MOVHLPS_v_undef_shuffle_mask)),
3003 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3004 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
3005 MOVHLPS_v_undef_shuffle_mask)),
3006 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3009 let AddedComplexity = 20 in {
3010 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3011 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
3012 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3013 MOVLP_shuffle_mask)),
3014 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3015 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3016 MOVLP_shuffle_mask)),
3017 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3018 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3019 MOVHP_shuffle_mask)),
3020 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3021 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3022 MOVHP_shuffle_mask)),
3023 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3025 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3026 (bc_v4i32 (memopv2i64 addr:$src2)),
3027 MOVLP_shuffle_mask)),
3028 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3029 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3030 MOVLP_shuffle_mask)),
3031 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3032 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3033 (bc_v4i32 (memopv2i64 addr:$src2)),
3034 MOVHP_shuffle_mask)),
3035 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3036 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3037 MOVHP_shuffle_mask)),
3038 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3041 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3042 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3043 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3044 MOVLP_shuffle_mask)), addr:$src1),
3045 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3046 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3047 MOVLP_shuffle_mask)), addr:$src1),
3048 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3049 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3050 MOVHP_shuffle_mask)), addr:$src1),
3051 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3052 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3053 MOVHP_shuffle_mask)), addr:$src1),
3054 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3056 def : Pat<(store (v4i32 (vector_shuffle
3057 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3058 MOVLP_shuffle_mask)), addr:$src1),
3059 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3060 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3061 MOVLP_shuffle_mask)), addr:$src1),
3062 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3063 def : Pat<(store (v4i32 (vector_shuffle
3064 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3065 MOVHP_shuffle_mask)), addr:$src1),
3066 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3067 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3068 MOVHP_shuffle_mask)), addr:$src1),
3069 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 let AddedComplexity = 15 in {
3073 // Setting the lowest element in the vector.
3074 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3075 MOVL_shuffle_mask)),
3076 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3077 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3078 MOVL_shuffle_mask)),
3079 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3081 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3082 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3083 MOVLP_shuffle_mask)),
3084 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3085 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3086 MOVLP_shuffle_mask)),
3087 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3090 // Set lowest element and zero upper elements.
3091 let AddedComplexity = 15 in
3092 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3093 MOVL_shuffle_mask)),
3094 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3095 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3096 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3098 // Some special case pandn patterns.
3099 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3101 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3102 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3104 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3105 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3107 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3109 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3110 (memop addr:$src2))),
3111 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3112 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3113 (memop addr:$src2))),
3114 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3115 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3116 (memop addr:$src2))),
3117 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3119 // vector -> vector casts
3120 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3121 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3122 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3123 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3124 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3125 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3126 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3127 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3129 // Use movaps / movups for SSE integer load / store (one byte shorter).
3130 def : Pat<(alignedloadv4i32 addr:$src),
3131 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3132 def : Pat<(loadv4i32 addr:$src),
3133 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3134 def : Pat<(alignedloadv2i64 addr:$src),
3135 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3136 def : Pat<(loadv2i64 addr:$src),
3137 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3139 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3140 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3141 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3142 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3143 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3144 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3145 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3146 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3147 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3148 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3149 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3150 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3151 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3152 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3153 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3154 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3156 //===----------------------------------------------------------------------===//
3157 // SSE4.1 Instructions
3158 //===----------------------------------------------------------------------===//
3160 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3163 Intrinsic V2F64Int> {
3164 // Intrinsic operation, reg.
3165 // Vector intrinsic operation, reg
3166 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3167 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3168 !strconcat(OpcodeStr,
3169 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3170 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3173 // Vector intrinsic operation, mem
3174 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3175 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3176 !strconcat(OpcodeStr,
3177 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3179 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3182 // Vector intrinsic operation, reg
3183 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3184 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3185 !strconcat(OpcodeStr,
3186 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3187 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3190 // Vector intrinsic operation, mem
3191 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3192 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3193 !strconcat(OpcodeStr,
3194 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3196 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3200 let Constraints = "$src1 = $dst" in {
3201 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3205 // Intrinsic operation, reg.
3206 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3208 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3209 !strconcat(OpcodeStr,
3210 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3212 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3215 // Intrinsic operation, mem.
3216 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3218 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3219 !strconcat(OpcodeStr,
3220 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3222 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3225 // Intrinsic operation, reg.
3226 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3228 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3229 !strconcat(OpcodeStr,
3230 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3232 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3235 // Intrinsic operation, mem.
3236 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3238 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3239 !strconcat(OpcodeStr,
3240 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3242 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3247 // FP round - roundss, roundps, roundsd, roundpd
3248 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3249 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3250 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3251 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3253 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3254 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3255 Intrinsic IntId128> {
3256 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3258 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3259 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3260 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3262 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3265 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3268 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3269 int_x86_sse41_phminposuw>;
3271 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3272 let Constraints = "$src1 = $dst" in {
3273 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3274 Intrinsic IntId128, bit Commutable = 0> {
3275 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3276 (ins VR128:$src1, VR128:$src2),
3277 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3278 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3280 let isCommutable = Commutable;
3282 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3283 (ins VR128:$src1, i128mem:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 (IntId128 VR128:$src1,
3287 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3291 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3292 int_x86_sse41_pcmpeqq, 1>;
3293 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3294 int_x86_sse41_packusdw, 0>;
3295 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3296 int_x86_sse41_pminsb, 1>;
3297 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3298 int_x86_sse41_pminsd, 1>;
3299 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3300 int_x86_sse41_pminud, 1>;
3301 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3302 int_x86_sse41_pminuw, 1>;
3303 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3304 int_x86_sse41_pmaxsb, 1>;
3305 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3306 int_x86_sse41_pmaxsd, 1>;
3307 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3308 int_x86_sse41_pmaxud, 1>;
3309 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3310 int_x86_sse41_pmaxuw, 1>;
3312 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3313 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3314 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3315 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3318 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3319 let Constraints = "$src1 = $dst" in {
3320 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3321 SDNode OpNode, Intrinsic IntId128,
3322 bit Commutable = 0> {
3323 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3324 (ins VR128:$src1, VR128:$src2),
3325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3326 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3327 VR128:$src2))]>, OpSize {
3328 let isCommutable = Commutable;
3330 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3331 (ins VR128:$src1, VR128:$src2),
3332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3333 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3335 let isCommutable = Commutable;
3337 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3338 (ins VR128:$src1, i128mem:$src2),
3339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3341 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3342 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3343 (ins VR128:$src1, i128mem:$src2),
3344 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3346 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3350 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3351 int_x86_sse41_pmulld, 1>;
3352 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3353 int_x86_sse41_pmuldq, 1>;
3356 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3357 let Constraints = "$src1 = $dst" in {
3358 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3359 Intrinsic IntId128, bit Commutable = 0> {
3360 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3361 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3362 !strconcat(OpcodeStr,
3363 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3365 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3367 let isCommutable = Commutable;
3369 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3370 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3371 !strconcat(OpcodeStr,
3372 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3374 (IntId128 VR128:$src1,
3375 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3380 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3381 int_x86_sse41_blendps, 0>;
3382 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3383 int_x86_sse41_blendpd, 0>;
3384 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3385 int_x86_sse41_pblendw, 0>;
3386 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3387 int_x86_sse41_dpps, 1>;
3388 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3389 int_x86_sse41_dppd, 1>;
3390 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3391 int_x86_sse41_mpsadbw, 1>;
3394 /// SS41I_ternary_int - SSE 4.1 ternary operator
3395 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3396 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3397 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3398 (ins VR128:$src1, VR128:$src2),
3399 !strconcat(OpcodeStr,
3400 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3401 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3404 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3405 (ins VR128:$src1, i128mem:$src2),
3406 !strconcat(OpcodeStr,
3407 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3410 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3414 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3415 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3416 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3419 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3420 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3421 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3422 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3424 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3427 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3431 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3432 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3433 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3434 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3435 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3436 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3438 // Common patterns involving scalar load.
3439 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3440 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3441 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3442 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3444 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3445 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3446 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3447 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3449 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3450 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3451 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3452 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3454 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3455 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3456 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3457 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3459 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3460 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3461 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3462 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3464 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3465 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3466 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3467 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3470 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3471 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3472 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3473 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3475 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3478 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3482 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3483 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3484 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3485 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3487 // Common patterns involving scalar load
3488 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3489 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3490 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3491 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3493 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3494 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3495 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3496 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3499 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3500 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3502 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3504 // Expecting a i16 load any extended to i32 value.
3505 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3506 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3507 [(set VR128:$dst, (IntId (bitconvert
3508 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3512 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3513 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3515 // Common patterns involving scalar load
3516 def : Pat<(int_x86_sse41_pmovsxbq
3517 (bitconvert (v4i32 (X86vzmovl
3518 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3519 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3521 def : Pat<(int_x86_sse41_pmovzxbq
3522 (bitconvert (v4i32 (X86vzmovl
3523 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3524 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3527 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3528 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3529 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3530 (ins VR128:$src1, i32i8imm:$src2),
3531 !strconcat(OpcodeStr,
3532 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3533 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3535 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3536 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3537 !strconcat(OpcodeStr,
3538 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3541 // There's an AssertZext in the way of writing the store pattern
3542 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3545 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3548 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3549 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3550 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3551 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3552 !strconcat(OpcodeStr,
3553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3556 // There's an AssertZext in the way of writing the store pattern
3557 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3560 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3563 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3564 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3565 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3566 (ins VR128:$src1, i32i8imm:$src2),
3567 !strconcat(OpcodeStr,
3568 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3570 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3571 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3572 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3573 !strconcat(OpcodeStr,
3574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3575 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3576 addr:$dst)]>, OpSize;
3579 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3582 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3584 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3585 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3586 (ins VR128:$src1, i32i8imm:$src2),
3587 !strconcat(OpcodeStr,
3588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3590 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3592 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3593 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3594 !strconcat(OpcodeStr,
3595 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3596 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3597 addr:$dst)]>, OpSize;
3600 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3602 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3603 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3606 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3607 Requires<[HasSSE41]>;
3609 let Constraints = "$src1 = $dst" in {
3610 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3611 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3612 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3613 !strconcat(OpcodeStr,
3614 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3616 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3617 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3618 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3619 !strconcat(OpcodeStr,
3620 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3622 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3623 imm:$src3))]>, OpSize;
3627 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3629 let Constraints = "$src1 = $dst" in {
3630 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3631 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3632 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3633 !strconcat(OpcodeStr,
3634 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3636 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3638 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3639 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3640 !strconcat(OpcodeStr,
3641 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3643 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3644 imm:$src3)))]>, OpSize;
3648 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3650 let Constraints = "$src1 = $dst" in {
3651 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3652 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3653 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3654 !strconcat(OpcodeStr,
3655 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3657 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3658 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3659 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3660 !strconcat(OpcodeStr,
3661 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3663 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3664 imm:$src3))]>, OpSize;
3668 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3670 let Defs = [EFLAGS] in {
3671 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3672 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3673 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3674 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3677 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3678 "movntdqa\t{$src, $dst|$dst, $src}",
3679 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3681 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3682 let Constraints = "$src1 = $dst" in {
3683 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3684 Intrinsic IntId128, bit Commutable = 0> {
3685 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3686 (ins VR128:$src1, VR128:$src2),
3687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3688 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3690 let isCommutable = Commutable;
3692 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3693 (ins VR128:$src1, i128mem:$src2),
3694 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3696 (IntId128 VR128:$src1,
3697 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3701 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3703 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3704 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3705 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3706 (PCMPGTQrm VR128:$src1, addr:$src2)>;