1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86pextrb : SDNode<"X86ISD::PEXTRB",
38 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
39 def X86pextrw : SDNode<"X86ISD::PEXTRW",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pinsrb : SDNode<"X86ISD::PINSRB",
42 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
43 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
44 def X86pinsrw : SDNode<"X86ISD::PINSRW",
45 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
46 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
47 def X86insrtps : SDNode<"X86ISD::INSERTPS",
48 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
49 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
51 //===----------------------------------------------------------------------===//
52 // SSE 'Special' Instructions
53 //===----------------------------------------------------------------------===//
55 let isImplicitDef = 1 in {
56 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
58 [(set VR128:$dst, (v4f32 (undef)))]>,
60 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
62 [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
63 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
65 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
68 //===----------------------------------------------------------------------===//
69 // SSE Complex Patterns
70 //===----------------------------------------------------------------------===//
72 // These are 'extloads' from a scalar to the low element of a vector, zeroing
73 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
75 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
76 [SDNPHasChain, SDNPMayLoad]>;
77 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
78 [SDNPHasChain, SDNPMayLoad]>;
80 def ssmem : Operand<v4f32> {
81 let PrintMethod = "printf32mem";
82 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
84 def sdmem : Operand<v2f64> {
85 let PrintMethod = "printf64mem";
86 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
89 //===----------------------------------------------------------------------===//
90 // SSE pattern fragments
91 //===----------------------------------------------------------------------===//
93 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
94 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
95 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
96 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
98 // Like 'store', but always requires vector alignment.
99 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
100 (st node:$val, node:$ptr), [{
101 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
102 return !ST->isTruncatingStore() &&
103 ST->getAddressingMode() == ISD::UNINDEXED &&
104 ST->getAlignment() >= 16;
108 // Like 'load', but always requires vector alignment.
109 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
110 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
111 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
112 LD->getAddressingMode() == ISD::UNINDEXED &&
113 LD->getAlignment() >= 16;
117 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
118 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
119 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
120 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
121 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
122 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
124 // Like 'load', but uses special alignment checks suitable for use in
125 // memory operands in most SSE instructions, which are required to
126 // be naturally aligned on some targets but not on others.
127 // FIXME: Actually implement support for targets that don't require the
128 // alignment. This probably wants a subtarget predicate.
129 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
130 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
131 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
132 LD->getAddressingMode() == ISD::UNINDEXED &&
133 LD->getAlignment() >= 16;
137 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
138 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
139 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
140 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
141 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
142 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
143 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
145 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
147 // FIXME: 8 byte alignment for mmx reads is not required
148 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
149 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
150 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
151 LD->getAddressingMode() == ISD::UNINDEXED &&
152 LD->getAlignment() >= 8;
156 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
157 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
158 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
159 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
161 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
162 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
163 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
164 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
165 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
166 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
168 def fp32imm0 : PatLeaf<(f32 fpimm), [{
169 return N->isExactlyValue(+0.0);
172 def PSxLDQ_imm : SDNodeXForm<imm, [{
173 // Transformation function: imm >> 3
174 return getI32Imm(N->getValue() >> 3);
177 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
179 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
180 return getI8Imm(X86::getShuffleSHUFImmediate(N));
183 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
185 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
186 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
189 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
191 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
192 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
195 def SSE_splat_mask : PatLeaf<(build_vector), [{
196 return X86::isSplatMask(N);
197 }], SHUFFLE_get_shuf_imm>;
199 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
200 return X86::isSplatLoMask(N);
203 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
204 return X86::isMOVHLPSMask(N);
207 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
208 return X86::isMOVHLPS_v_undef_Mask(N);
211 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHPMask(N);
215 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVLPMask(N);
219 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVLMask(N);
223 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVSHDUPMask(N);
227 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVSLDUPMask(N);
231 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isUNPCKLMask(N);
235 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isUNPCKHMask(N);
239 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKL_v_undef_Mask(N);
243 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKH_v_undef_Mask(N);
247 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isPSHUFDMask(N);
249 }], SHUFFLE_get_shuf_imm>;
251 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isPSHUFHWMask(N);
253 }], SHUFFLE_get_pshufhw_imm>;
255 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFLWMask(N);
257 }], SHUFFLE_get_pshuflw_imm>;
259 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isSHUFPMask(N);
265 }], SHUFFLE_get_shuf_imm>;
267 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isSHUFPMask(N);
269 }], SHUFFLE_get_shuf_imm>;
271 //===----------------------------------------------------------------------===//
272 // SSE scalar FP Instructions
273 //===----------------------------------------------------------------------===//
275 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
276 // scheduler into a branch sequence.
277 // These are expanded by the scheduler.
278 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
279 def CMOV_FR32 : I<0, Pseudo,
280 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
281 "#CMOV_FR32 PSEUDO!",
282 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
284 def CMOV_FR64 : I<0, Pseudo,
285 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
286 "#CMOV_FR64 PSEUDO!",
287 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
289 def CMOV_V4F32 : I<0, Pseudo,
290 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V4F32 PSEUDO!",
293 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
295 def CMOV_V2F64 : I<0, Pseudo,
296 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
297 "#CMOV_V2F64 PSEUDO!",
299 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
301 def CMOV_V2I64 : I<0, Pseudo,
302 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
303 "#CMOV_V2I64 PSEUDO!",
305 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
309 //===----------------------------------------------------------------------===//
311 //===----------------------------------------------------------------------===//
314 let neverHasSideEffects = 1 in
315 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
316 "movss\t{$src, $dst|$dst, $src}", []>;
317 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
318 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
319 "movss\t{$src, $dst|$dst, $src}",
320 [(set FR32:$dst, (loadf32 addr:$src))]>;
321 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
322 "movss\t{$src, $dst|$dst, $src}",
323 [(store FR32:$src, addr:$dst)]>;
325 // Conversion instructions
326 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
327 "cvttss2si\t{$src, $dst|$dst, $src}",
328 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
329 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
330 "cvttss2si\t{$src, $dst|$dst, $src}",
331 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
332 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
333 "cvtsi2ss\t{$src, $dst|$dst, $src}",
334 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
335 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
336 "cvtsi2ss\t{$src, $dst|$dst, $src}",
337 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
339 // Match intrinsics which expect XMM operand(s).
340 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
341 "cvtss2si\t{$src, $dst|$dst, $src}",
342 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
343 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
344 "cvtss2si\t{$src, $dst|$dst, $src}",
345 [(set GR32:$dst, (int_x86_sse_cvtss2si
346 (load addr:$src)))]>;
348 // Match intrinisics which expect MM and XMM operand(s).
349 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
350 "cvtps2pi\t{$src, $dst|$dst, $src}",
351 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
352 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
353 "cvtps2pi\t{$src, $dst|$dst, $src}",
354 [(set VR64:$dst, (int_x86_sse_cvtps2pi
355 (load addr:$src)))]>;
356 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
357 "cvttps2pi\t{$src, $dst|$dst, $src}",
358 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
359 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
360 "cvttps2pi\t{$src, $dst|$dst, $src}",
361 [(set VR64:$dst, (int_x86_sse_cvttps2pi
362 (load addr:$src)))]>;
363 let isTwoAddress = 1 in {
364 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
365 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
366 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
367 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
369 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
370 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
371 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
372 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
373 (load addr:$src2)))]>;
376 // Aliases for intrinsics
377 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
378 "cvttss2si\t{$src, $dst|$dst, $src}",
380 (int_x86_sse_cvttss2si VR128:$src))]>;
381 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
382 "cvttss2si\t{$src, $dst|$dst, $src}",
384 (int_x86_sse_cvttss2si(load addr:$src)))]>;
386 let isTwoAddress = 1 in {
387 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
388 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
389 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
390 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
392 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
393 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
394 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
395 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
396 (loadi32 addr:$src2)))]>;
399 // Comparison instructions
400 let isTwoAddress = 1 in {
401 let neverHasSideEffects = 1 in
402 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
403 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
404 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
405 let neverHasSideEffects = 1, mayLoad = 1 in
406 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
407 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
408 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
411 let Defs = [EFLAGS] in {
412 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
413 "ucomiss\t{$src2, $src1|$src1, $src2}",
414 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
415 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
416 "ucomiss\t{$src2, $src1|$src1, $src2}",
417 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
421 // Aliases to match intrinsics which expect XMM operand(s).
422 let isTwoAddress = 1 in {
423 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
424 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
425 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
426 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
427 VR128:$src, imm:$cc))]>;
428 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
429 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
430 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
431 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
432 (load addr:$src), imm:$cc))]>;
435 let Defs = [EFLAGS] in {
436 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
437 (ins VR128:$src1, VR128:$src2),
438 "ucomiss\t{$src2, $src1|$src1, $src2}",
439 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
441 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
442 (ins VR128:$src1, f128mem:$src2),
443 "ucomiss\t{$src2, $src1|$src1, $src2}",
444 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
447 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
448 (ins VR128:$src1, VR128:$src2),
449 "comiss\t{$src2, $src1|$src1, $src2}",
450 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
452 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
453 (ins VR128:$src1, f128mem:$src2),
454 "comiss\t{$src2, $src1|$src1, $src2}",
455 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
459 // Aliases of packed SSE1 instructions for scalar use. These all have names that
462 // Alias instructions that map fld0 to pxor for sse.
463 let isReMaterializable = 1 in
464 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
465 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
466 Requires<[HasSSE1]>, TB, OpSize;
468 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
470 let neverHasSideEffects = 1 in
471 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
472 "movaps\t{$src, $dst|$dst, $src}", []>;
474 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
476 let isSimpleLoad = 1 in
477 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
478 "movaps\t{$src, $dst|$dst, $src}",
479 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
481 // Alias bitwise logical operations using SSE logical ops on packed FP values.
482 let isTwoAddress = 1 in {
483 let isCommutable = 1 in {
484 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
485 "andps\t{$src2, $dst|$dst, $src2}",
486 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
487 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
488 "orps\t{$src2, $dst|$dst, $src2}",
489 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
490 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
491 "xorps\t{$src2, $dst|$dst, $src2}",
492 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
495 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
496 "andps\t{$src2, $dst|$dst, $src2}",
497 [(set FR32:$dst, (X86fand FR32:$src1,
498 (memopfsf32 addr:$src2)))]>;
499 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
500 "orps\t{$src2, $dst|$dst, $src2}",
501 [(set FR32:$dst, (X86for FR32:$src1,
502 (memopfsf32 addr:$src2)))]>;
503 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
504 "xorps\t{$src2, $dst|$dst, $src2}",
505 [(set FR32:$dst, (X86fxor FR32:$src1,
506 (memopfsf32 addr:$src2)))]>;
507 let neverHasSideEffects = 1 in {
508 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
509 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
510 "andnps\t{$src2, $dst|$dst, $src2}", []>;
513 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
514 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
515 "andnps\t{$src2, $dst|$dst, $src2}", []>;
519 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
521 /// In addition, we also have a special variant of the scalar form here to
522 /// represent the associated intrinsic operation. This form is unlike the
523 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
524 /// and leaves the top elements undefined.
526 /// These three forms can each be reg+reg or reg+mem, so there are a total of
527 /// six "instructions".
529 let isTwoAddress = 1 in {
530 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
531 SDNode OpNode, Intrinsic F32Int,
532 bit Commutable = 0> {
533 // Scalar operation, reg+reg.
534 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
535 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
536 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
537 let isCommutable = Commutable;
540 // Scalar operation, reg+mem.
541 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
542 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
543 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
545 // Vector operation, reg+reg.
546 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
547 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
548 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
549 let isCommutable = Commutable;
552 // Vector operation, reg+mem.
553 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
554 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
555 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
557 // Intrinsic operation, reg+reg.
558 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
559 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
561 let isCommutable = Commutable;
564 // Intrinsic operation, reg+mem.
565 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
566 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
567 [(set VR128:$dst, (F32Int VR128:$src1,
568 sse_load_f32:$src2))]>;
572 // Arithmetic instructions
573 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
574 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
575 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
576 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
578 /// sse1_fp_binop_rm - Other SSE1 binops
580 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
581 /// instructions for a full-vector intrinsic form. Operations that map
582 /// onto C operators don't use this form since they just use the plain
583 /// vector form instead of having a separate vector intrinsic form.
585 /// This provides a total of eight "instructions".
587 let isTwoAddress = 1 in {
588 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
592 bit Commutable = 0> {
594 // Scalar operation, reg+reg.
595 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
596 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
597 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
598 let isCommutable = Commutable;
601 // Scalar operation, reg+mem.
602 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
603 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
604 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
606 // Vector operation, reg+reg.
607 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
608 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
609 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
610 let isCommutable = Commutable;
613 // Vector operation, reg+mem.
614 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
615 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
616 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
618 // Intrinsic operation, reg+reg.
619 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
620 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
621 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
622 let isCommutable = Commutable;
625 // Intrinsic operation, reg+mem.
626 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
627 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
628 [(set VR128:$dst, (F32Int VR128:$src1,
629 sse_load_f32:$src2))]>;
631 // Vector intrinsic operation, reg+reg.
632 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
633 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
634 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
635 let isCommutable = Commutable;
638 // Vector intrinsic operation, reg+mem.
639 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
640 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
641 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
645 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
646 int_x86_sse_max_ss, int_x86_sse_max_ps>;
647 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
648 int_x86_sse_min_ss, int_x86_sse_min_ps>;
650 //===----------------------------------------------------------------------===//
651 // SSE packed FP Instructions
654 let neverHasSideEffects = 1 in
655 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
656 "movaps\t{$src, $dst|$dst, $src}", []>;
657 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
658 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
659 "movaps\t{$src, $dst|$dst, $src}",
660 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
662 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
663 "movaps\t{$src, $dst|$dst, $src}",
664 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
666 let neverHasSideEffects = 1 in
667 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
668 "movups\t{$src, $dst|$dst, $src}", []>;
669 let isSimpleLoad = 1 in
670 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
671 "movups\t{$src, $dst|$dst, $src}",
672 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
673 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
674 "movups\t{$src, $dst|$dst, $src}",
675 [(store (v4f32 VR128:$src), addr:$dst)]>;
677 // Intrinsic forms of MOVUPS load and store
678 let isSimpleLoad = 1 in
679 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
680 "movups\t{$src, $dst|$dst, $src}",
681 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
682 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
683 "movups\t{$src, $dst|$dst, $src}",
684 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
686 let isTwoAddress = 1 in {
687 let AddedComplexity = 20 in {
688 def MOVLPSrm : PSI<0x12, MRMSrcMem,
689 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
690 "movlps\t{$src2, $dst|$dst, $src2}",
692 (v4f32 (vector_shuffle VR128:$src1,
693 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
694 MOVLP_shuffle_mask)))]>;
695 def MOVHPSrm : PSI<0x16, MRMSrcMem,
696 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
697 "movhps\t{$src2, $dst|$dst, $src2}",
699 (v4f32 (vector_shuffle VR128:$src1,
700 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
701 MOVHP_shuffle_mask)))]>;
705 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
706 "movlps\t{$src, $dst|$dst, $src}",
707 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
708 (iPTR 0))), addr:$dst)]>;
710 // v2f64 extract element 1 is always custom lowered to unpack high to low
711 // and extract element 0 so the non-store version isn't too horrible.
712 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
713 "movhps\t{$src, $dst|$dst, $src}",
714 [(store (f64 (vector_extract
715 (v2f64 (vector_shuffle
716 (bc_v2f64 (v4f32 VR128:$src)), (undef),
717 UNPCKH_shuffle_mask)), (iPTR 0))),
720 let isTwoAddress = 1 in {
721 let AddedComplexity = 15 in {
722 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
723 "movlhps\t{$src2, $dst|$dst, $src2}",
725 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
726 MOVHP_shuffle_mask)))]>;
728 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
729 "movhlps\t{$src2, $dst|$dst, $src2}",
731 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
732 MOVHLPS_shuffle_mask)))]>;
740 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
742 /// In addition, we also have a special variant of the scalar form here to
743 /// represent the associated intrinsic operation. This form is unlike the
744 /// plain scalar form, in that it takes an entire vector (instead of a
745 /// scalar) and leaves the top elements undefined.
747 /// And, we have a special variant form for a full-vector intrinsic form.
749 /// These four forms can each have a reg or a mem operand, so there are a
750 /// total of eight "instructions".
752 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
756 bit Commutable = 0> {
757 // Scalar operation, reg.
758 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
759 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
760 [(set FR32:$dst, (OpNode FR32:$src))]> {
761 let isCommutable = Commutable;
764 // Scalar operation, mem.
765 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
766 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
767 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
769 // Vector operation, reg.
770 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
771 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
772 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
773 let isCommutable = Commutable;
776 // Vector operation, mem.
777 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
778 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
779 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
781 // Intrinsic operation, reg.
782 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
783 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
784 [(set VR128:$dst, (F32Int VR128:$src))]> {
785 let isCommutable = Commutable;
788 // Intrinsic operation, mem.
789 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
791 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
793 // Vector intrinsic operation, reg
794 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
795 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
796 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
797 let isCommutable = Commutable;
800 // Vector intrinsic operation, mem
801 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
802 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
807 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
808 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
810 // Reciprocal approximations. Note that these typically require refinement
811 // in order to obtain suitable precision.
812 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
813 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
814 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
815 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
818 let isTwoAddress = 1 in {
819 let isCommutable = 1 in {
820 def ANDPSrr : PSI<0x54, MRMSrcReg,
821 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
822 "andps\t{$src2, $dst|$dst, $src2}",
823 [(set VR128:$dst, (v2i64
824 (and VR128:$src1, VR128:$src2)))]>;
825 def ORPSrr : PSI<0x56, MRMSrcReg,
826 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
827 "orps\t{$src2, $dst|$dst, $src2}",
828 [(set VR128:$dst, (v2i64
829 (or VR128:$src1, VR128:$src2)))]>;
830 def XORPSrr : PSI<0x57, MRMSrcReg,
831 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
832 "xorps\t{$src2, $dst|$dst, $src2}",
833 [(set VR128:$dst, (v2i64
834 (xor VR128:$src1, VR128:$src2)))]>;
837 def ANDPSrm : PSI<0x54, MRMSrcMem,
838 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
839 "andps\t{$src2, $dst|$dst, $src2}",
840 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
841 (memopv2i64 addr:$src2)))]>;
842 def ORPSrm : PSI<0x56, MRMSrcMem,
843 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
844 "orps\t{$src2, $dst|$dst, $src2}",
845 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
846 (memopv2i64 addr:$src2)))]>;
847 def XORPSrm : PSI<0x57, MRMSrcMem,
848 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
849 "xorps\t{$src2, $dst|$dst, $src2}",
850 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
851 (memopv2i64 addr:$src2)))]>;
852 def ANDNPSrr : PSI<0x55, MRMSrcReg,
853 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
854 "andnps\t{$src2, $dst|$dst, $src2}",
856 (v2i64 (and (xor VR128:$src1,
857 (bc_v2i64 (v4i32 immAllOnesV))),
859 def ANDNPSrm : PSI<0x55, MRMSrcMem,
860 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
861 "andnps\t{$src2, $dst|$dst, $src2}",
863 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
864 (bc_v2i64 (v4i32 immAllOnesV))),
865 (memopv2i64 addr:$src2))))]>;
868 let isTwoAddress = 1 in {
869 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
870 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
871 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
873 VR128:$src, imm:$cc))]>;
874 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
875 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
876 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
877 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
878 (load addr:$src), imm:$cc))]>;
881 // Shuffle and unpack instructions
882 let isTwoAddress = 1 in {
883 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
884 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
885 (outs VR128:$dst), (ins VR128:$src1,
886 VR128:$src2, i32i8imm:$src3),
887 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
889 (v4f32 (vector_shuffle
890 VR128:$src1, VR128:$src2,
891 SHUFP_shuffle_mask:$src3)))]>;
892 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
893 (outs VR128:$dst), (ins VR128:$src1,
894 f128mem:$src2, i32i8imm:$src3),
895 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
897 (v4f32 (vector_shuffle
898 VR128:$src1, (memopv4f32 addr:$src2),
899 SHUFP_shuffle_mask:$src3)))]>;
901 let AddedComplexity = 10 in {
902 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
903 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
904 "unpckhps\t{$src2, $dst|$dst, $src2}",
906 (v4f32 (vector_shuffle
907 VR128:$src1, VR128:$src2,
908 UNPCKH_shuffle_mask)))]>;
909 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
910 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
911 "unpckhps\t{$src2, $dst|$dst, $src2}",
913 (v4f32 (vector_shuffle
914 VR128:$src1, (memopv4f32 addr:$src2),
915 UNPCKH_shuffle_mask)))]>;
917 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
918 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
919 "unpcklps\t{$src2, $dst|$dst, $src2}",
921 (v4f32 (vector_shuffle
922 VR128:$src1, VR128:$src2,
923 UNPCKL_shuffle_mask)))]>;
924 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
925 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
926 "unpcklps\t{$src2, $dst|$dst, $src2}",
928 (v4f32 (vector_shuffle
929 VR128:$src1, (memopv4f32 addr:$src2),
930 UNPCKL_shuffle_mask)))]>;
935 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
936 "movmskps\t{$src, $dst|$dst, $src}",
937 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
938 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
939 "movmskpd\t{$src, $dst|$dst, $src}",
940 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
942 // Prefetching loads.
943 // TODO: no intrinsics for these?
944 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
945 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
946 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
947 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
949 // Non-temporal stores
950 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
951 "movntps\t{$src, $dst|$dst, $src}",
952 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
954 // Load, store, and memory fence
955 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
958 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
959 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
960 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
961 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
963 // Alias instructions that map zero vector to pxor / xorp* for sse.
964 let isReMaterializable = 1 in
965 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
967 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
969 // FR32 to 128-bit vector conversion.
970 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
971 "movss\t{$src, $dst|$dst, $src}",
973 (v4f32 (scalar_to_vector FR32:$src)))]>;
974 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
975 "movss\t{$src, $dst|$dst, $src}",
977 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
979 // FIXME: may not be able to eliminate this movss with coalescing the src and
980 // dest register classes are different. We really want to write this pattern
982 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
984 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
985 "movss\t{$src, $dst|$dst, $src}",
986 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
988 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
989 "movss\t{$src, $dst|$dst, $src}",
990 [(store (f32 (vector_extract (v4f32 VR128:$src),
991 (iPTR 0))), addr:$dst)]>;
994 // Move to lower bits of a VR128, leaving upper bits alone.
995 // Three operand (but two address) aliases.
996 let isTwoAddress = 1 in {
997 let neverHasSideEffects = 1 in
998 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
999 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1000 "movss\t{$src2, $dst|$dst, $src2}", []>;
1002 let AddedComplexity = 15 in
1003 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1004 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1005 "movss\t{$src2, $dst|$dst, $src2}",
1007 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1008 MOVL_shuffle_mask)))]>;
1011 // Move to lower bits of a VR128 and zeroing upper bits.
1012 // Loading from memory automatically zeroing upper bits.
1013 let AddedComplexity = 20 in
1014 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1015 "movss\t{$src, $dst|$dst, $src}",
1016 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV_bc,
1017 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1018 MOVL_shuffle_mask)))]>;
1021 //===----------------------------------------------------------------------===//
1022 // SSE2 Instructions
1023 //===----------------------------------------------------------------------===//
1025 // Move Instructions
1026 let neverHasSideEffects = 1 in
1027 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1028 "movsd\t{$src, $dst|$dst, $src}", []>;
1029 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1030 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1031 "movsd\t{$src, $dst|$dst, $src}",
1032 [(set FR64:$dst, (loadf64 addr:$src))]>;
1033 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1034 "movsd\t{$src, $dst|$dst, $src}",
1035 [(store FR64:$src, addr:$dst)]>;
1037 // Conversion instructions
1038 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1039 "cvttsd2si\t{$src, $dst|$dst, $src}",
1040 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1041 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1042 "cvttsd2si\t{$src, $dst|$dst, $src}",
1043 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1044 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1045 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1046 [(set FR32:$dst, (fround FR64:$src))]>;
1047 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1048 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1049 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1050 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1051 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1052 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1053 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1054 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1055 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1057 // SSE2 instructions with XS prefix
1058 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1059 "cvtss2sd\t{$src, $dst|$dst, $src}",
1060 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1061 Requires<[HasSSE2]>;
1062 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1063 "cvtss2sd\t{$src, $dst|$dst, $src}",
1064 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1065 Requires<[HasSSE2]>;
1067 // Match intrinsics which expect XMM operand(s).
1068 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1069 "cvtsd2si\t{$src, $dst|$dst, $src}",
1070 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1071 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1072 "cvtsd2si\t{$src, $dst|$dst, $src}",
1073 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1074 (load addr:$src)))]>;
1076 // Match intrinisics which expect MM and XMM operand(s).
1077 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1078 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1079 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1080 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1081 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1082 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1083 (load addr:$src)))]>;
1084 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1085 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1086 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1087 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1088 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1089 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1090 (load addr:$src)))]>;
1091 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1092 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1093 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1094 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1095 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1096 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1097 (load addr:$src)))]>;
1099 // Aliases for intrinsics
1100 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1101 "cvttsd2si\t{$src, $dst|$dst, $src}",
1103 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1104 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1105 "cvttsd2si\t{$src, $dst|$dst, $src}",
1106 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1107 (load addr:$src)))]>;
1109 // Comparison instructions
1110 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1111 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1112 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1113 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1115 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1116 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1117 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1120 let Defs = [EFLAGS] in {
1121 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1122 "ucomisd\t{$src2, $src1|$src1, $src2}",
1123 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1124 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1125 "ucomisd\t{$src2, $src1|$src1, $src2}",
1126 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1127 (implicit EFLAGS)]>;
1130 // Aliases to match intrinsics which expect XMM operand(s).
1131 let isTwoAddress = 1 in {
1132 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1133 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1134 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1135 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1136 VR128:$src, imm:$cc))]>;
1137 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1138 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1139 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1140 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1141 (load addr:$src), imm:$cc))]>;
1144 let Defs = [EFLAGS] in {
1145 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1146 "ucomisd\t{$src2, $src1|$src1, $src2}",
1147 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1148 (implicit EFLAGS)]>;
1149 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1150 "ucomisd\t{$src2, $src1|$src1, $src2}",
1151 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1152 (implicit EFLAGS)]>;
1154 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1155 "comisd\t{$src2, $src1|$src1, $src2}",
1156 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1157 (implicit EFLAGS)]>;
1158 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1159 "comisd\t{$src2, $src1|$src1, $src2}",
1160 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1161 (implicit EFLAGS)]>;
1164 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1167 // Alias instructions that map fld0 to pxor for sse.
1168 let isReMaterializable = 1 in
1169 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1170 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1171 Requires<[HasSSE2]>, TB, OpSize;
1173 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1175 let neverHasSideEffects = 1 in
1176 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1177 "movapd\t{$src, $dst|$dst, $src}", []>;
1179 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1181 let isSimpleLoad = 1 in
1182 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1183 "movapd\t{$src, $dst|$dst, $src}",
1184 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1186 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1187 let isTwoAddress = 1 in {
1188 let isCommutable = 1 in {
1189 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1190 "andpd\t{$src2, $dst|$dst, $src2}",
1191 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1192 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1193 "orpd\t{$src2, $dst|$dst, $src2}",
1194 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1195 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1196 "xorpd\t{$src2, $dst|$dst, $src2}",
1197 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1200 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1201 "andpd\t{$src2, $dst|$dst, $src2}",
1202 [(set FR64:$dst, (X86fand FR64:$src1,
1203 (memopfsf64 addr:$src2)))]>;
1204 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1205 "orpd\t{$src2, $dst|$dst, $src2}",
1206 [(set FR64:$dst, (X86for FR64:$src1,
1207 (memopfsf64 addr:$src2)))]>;
1208 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1209 "xorpd\t{$src2, $dst|$dst, $src2}",
1210 [(set FR64:$dst, (X86fxor FR64:$src1,
1211 (memopfsf64 addr:$src2)))]>;
1213 let neverHasSideEffects = 1 in {
1214 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1215 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1216 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1218 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1219 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1220 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1224 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1226 /// In addition, we also have a special variant of the scalar form here to
1227 /// represent the associated intrinsic operation. This form is unlike the
1228 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1229 /// and leaves the top elements undefined.
1231 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1232 /// six "instructions".
1234 let isTwoAddress = 1 in {
1235 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1236 SDNode OpNode, Intrinsic F64Int,
1237 bit Commutable = 0> {
1238 // Scalar operation, reg+reg.
1239 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1240 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1241 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1242 let isCommutable = Commutable;
1245 // Scalar operation, reg+mem.
1246 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1247 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1248 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1250 // Vector operation, reg+reg.
1251 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1252 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1253 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1254 let isCommutable = Commutable;
1257 // Vector operation, reg+mem.
1258 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1259 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1260 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1262 // Intrinsic operation, reg+reg.
1263 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1264 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1265 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1266 let isCommutable = Commutable;
1269 // Intrinsic operation, reg+mem.
1270 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1271 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1272 [(set VR128:$dst, (F64Int VR128:$src1,
1273 sse_load_f64:$src2))]>;
1277 // Arithmetic instructions
1278 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1279 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1280 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1281 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1283 /// sse2_fp_binop_rm - Other SSE2 binops
1285 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1286 /// instructions for a full-vector intrinsic form. Operations that map
1287 /// onto C operators don't use this form since they just use the plain
1288 /// vector form instead of having a separate vector intrinsic form.
1290 /// This provides a total of eight "instructions".
1292 let isTwoAddress = 1 in {
1293 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1297 bit Commutable = 0> {
1299 // Scalar operation, reg+reg.
1300 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1301 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1302 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1303 let isCommutable = Commutable;
1306 // Scalar operation, reg+mem.
1307 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1308 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1309 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1311 // Vector operation, reg+reg.
1312 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1313 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1314 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1315 let isCommutable = Commutable;
1318 // Vector operation, reg+mem.
1319 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1320 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1321 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1323 // Intrinsic operation, reg+reg.
1324 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1325 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1326 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1327 let isCommutable = Commutable;
1330 // Intrinsic operation, reg+mem.
1331 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1332 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1333 [(set VR128:$dst, (F64Int VR128:$src1,
1334 sse_load_f64:$src2))]>;
1336 // Vector intrinsic operation, reg+reg.
1337 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1338 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1339 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1340 let isCommutable = Commutable;
1343 // Vector intrinsic operation, reg+mem.
1344 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1345 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1346 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1350 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1351 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1352 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1353 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1355 //===----------------------------------------------------------------------===//
1356 // SSE packed FP Instructions
1358 // Move Instructions
1359 let neverHasSideEffects = 1 in
1360 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1361 "movapd\t{$src, $dst|$dst, $src}", []>;
1362 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1363 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1364 "movapd\t{$src, $dst|$dst, $src}",
1365 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1367 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1368 "movapd\t{$src, $dst|$dst, $src}",
1369 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1371 let neverHasSideEffects = 1 in
1372 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1373 "movupd\t{$src, $dst|$dst, $src}", []>;
1374 let isSimpleLoad = 1 in
1375 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1376 "movupd\t{$src, $dst|$dst, $src}",
1377 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1378 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1379 "movupd\t{$src, $dst|$dst, $src}",
1380 [(store (v2f64 VR128:$src), addr:$dst)]>;
1382 // Intrinsic forms of MOVUPD load and store
1383 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1384 "movupd\t{$src, $dst|$dst, $src}",
1385 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1386 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1387 "movupd\t{$src, $dst|$dst, $src}",
1388 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1390 let isTwoAddress = 1 in {
1391 let AddedComplexity = 20 in {
1392 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1393 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1394 "movlpd\t{$src2, $dst|$dst, $src2}",
1396 (v2f64 (vector_shuffle VR128:$src1,
1397 (scalar_to_vector (loadf64 addr:$src2)),
1398 MOVLP_shuffle_mask)))]>;
1399 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1400 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1401 "movhpd\t{$src2, $dst|$dst, $src2}",
1403 (v2f64 (vector_shuffle VR128:$src1,
1404 (scalar_to_vector (loadf64 addr:$src2)),
1405 MOVHP_shuffle_mask)))]>;
1406 } // AddedComplexity
1409 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1410 "movlpd\t{$src, $dst|$dst, $src}",
1411 [(store (f64 (vector_extract (v2f64 VR128:$src),
1412 (iPTR 0))), addr:$dst)]>;
1414 // v2f64 extract element 1 is always custom lowered to unpack high to low
1415 // and extract element 0 so the non-store version isn't too horrible.
1416 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1417 "movhpd\t{$src, $dst|$dst, $src}",
1418 [(store (f64 (vector_extract
1419 (v2f64 (vector_shuffle VR128:$src, (undef),
1420 UNPCKH_shuffle_mask)), (iPTR 0))),
1423 // SSE2 instructions without OpSize prefix
1424 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1425 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1427 TB, Requires<[HasSSE2]>;
1428 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1429 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1430 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1431 (bitconvert (memopv2i64 addr:$src))))]>,
1432 TB, Requires<[HasSSE2]>;
1434 // SSE2 instructions with XS prefix
1435 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1436 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1437 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1438 XS, Requires<[HasSSE2]>;
1439 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1440 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1441 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1442 (bitconvert (memopv2i64 addr:$src))))]>,
1443 XS, Requires<[HasSSE2]>;
1445 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1446 "cvtps2dq\t{$src, $dst|$dst, $src}",
1447 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1448 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1449 "cvtps2dq\t{$src, $dst|$dst, $src}",
1450 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1451 (load addr:$src)))]>;
1452 // SSE2 packed instructions with XS prefix
1453 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1454 "cvttps2dq\t{$src, $dst|$dst, $src}",
1455 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1456 XS, Requires<[HasSSE2]>;
1457 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1458 "cvttps2dq\t{$src, $dst|$dst, $src}",
1459 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1460 (load addr:$src)))]>,
1461 XS, Requires<[HasSSE2]>;
1463 // SSE2 packed instructions with XD prefix
1464 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1465 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1466 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1467 XD, Requires<[HasSSE2]>;
1468 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1469 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1470 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1471 (load addr:$src)))]>,
1472 XD, Requires<[HasSSE2]>;
1474 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1475 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1476 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1477 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1478 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1479 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1480 (load addr:$src)))]>;
1482 // SSE2 instructions without OpSize prefix
1483 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1484 "cvtps2pd\t{$src, $dst|$dst, $src}",
1485 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1486 TB, Requires<[HasSSE2]>;
1487 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1488 "cvtps2pd\t{$src, $dst|$dst, $src}",
1489 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1490 (load addr:$src)))]>,
1491 TB, Requires<[HasSSE2]>;
1493 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1494 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1495 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1496 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1497 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1498 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1499 (load addr:$src)))]>;
1501 // Match intrinsics which expect XMM operand(s).
1502 // Aliases for intrinsics
1503 let isTwoAddress = 1 in {
1504 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1505 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1506 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1507 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1509 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1510 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1511 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1512 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1513 (loadi32 addr:$src2)))]>;
1514 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1515 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1516 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1517 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1519 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1520 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1521 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1522 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1523 (load addr:$src2)))]>;
1524 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1525 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1526 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1527 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1528 VR128:$src2))]>, XS,
1529 Requires<[HasSSE2]>;
1530 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1531 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1532 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1533 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1534 (load addr:$src2)))]>, XS,
1535 Requires<[HasSSE2]>;
1540 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1542 /// In addition, we also have a special variant of the scalar form here to
1543 /// represent the associated intrinsic operation. This form is unlike the
1544 /// plain scalar form, in that it takes an entire vector (instead of a
1545 /// scalar) and leaves the top elements undefined.
1547 /// And, we have a special variant form for a full-vector intrinsic form.
1549 /// These four forms can each have a reg or a mem operand, so there are a
1550 /// total of eight "instructions".
1552 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1556 bit Commutable = 0> {
1557 // Scalar operation, reg.
1558 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1559 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1560 [(set FR64:$dst, (OpNode FR64:$src))]> {
1561 let isCommutable = Commutable;
1564 // Scalar operation, mem.
1565 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1566 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1567 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1569 // Vector operation, reg.
1570 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1571 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1572 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1573 let isCommutable = Commutable;
1576 // Vector operation, mem.
1577 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1578 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1579 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1581 // Intrinsic operation, reg.
1582 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1583 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1584 [(set VR128:$dst, (F64Int VR128:$src))]> {
1585 let isCommutable = Commutable;
1588 // Intrinsic operation, mem.
1589 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1590 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1591 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1593 // Vector intrinsic operation, reg
1594 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1595 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1596 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1597 let isCommutable = Commutable;
1600 // Vector intrinsic operation, mem
1601 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1602 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1603 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1607 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1608 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1610 // There is no f64 version of the reciprocal approximation instructions.
1613 let isTwoAddress = 1 in {
1614 let isCommutable = 1 in {
1615 def ANDPDrr : PDI<0x54, MRMSrcReg,
1616 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1617 "andpd\t{$src2, $dst|$dst, $src2}",
1619 (and (bc_v2i64 (v2f64 VR128:$src1)),
1620 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1621 def ORPDrr : PDI<0x56, MRMSrcReg,
1622 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1623 "orpd\t{$src2, $dst|$dst, $src2}",
1625 (or (bc_v2i64 (v2f64 VR128:$src1)),
1626 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1627 def XORPDrr : PDI<0x57, MRMSrcReg,
1628 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1629 "xorpd\t{$src2, $dst|$dst, $src2}",
1631 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1632 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1635 def ANDPDrm : PDI<0x54, MRMSrcMem,
1636 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1637 "andpd\t{$src2, $dst|$dst, $src2}",
1639 (and (bc_v2i64 (v2f64 VR128:$src1)),
1640 (memopv2i64 addr:$src2)))]>;
1641 def ORPDrm : PDI<0x56, MRMSrcMem,
1642 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1643 "orpd\t{$src2, $dst|$dst, $src2}",
1645 (or (bc_v2i64 (v2f64 VR128:$src1)),
1646 (memopv2i64 addr:$src2)))]>;
1647 def XORPDrm : PDI<0x57, MRMSrcMem,
1648 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1649 "xorpd\t{$src2, $dst|$dst, $src2}",
1651 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1652 (memopv2i64 addr:$src2)))]>;
1653 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1654 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1655 "andnpd\t{$src2, $dst|$dst, $src2}",
1657 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1658 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1659 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1660 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1661 "andnpd\t{$src2, $dst|$dst, $src2}",
1663 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1664 (memopv2i64 addr:$src2)))]>;
1667 let isTwoAddress = 1 in {
1668 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1669 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1670 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1672 VR128:$src, imm:$cc))]>;
1673 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1674 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1675 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1677 (load addr:$src), imm:$cc))]>;
1680 // Shuffle and unpack instructions
1681 let isTwoAddress = 1 in {
1682 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1683 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1684 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1685 [(set VR128:$dst, (v2f64 (vector_shuffle
1686 VR128:$src1, VR128:$src2,
1687 SHUFP_shuffle_mask:$src3)))]>;
1688 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1689 (outs VR128:$dst), (ins VR128:$src1,
1690 f128mem:$src2, i8imm:$src3),
1691 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1693 (v2f64 (vector_shuffle
1694 VR128:$src1, (memopv2f64 addr:$src2),
1695 SHUFP_shuffle_mask:$src3)))]>;
1697 let AddedComplexity = 10 in {
1698 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1699 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1700 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1702 (v2f64 (vector_shuffle
1703 VR128:$src1, VR128:$src2,
1704 UNPCKH_shuffle_mask)))]>;
1705 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1706 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1707 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1709 (v2f64 (vector_shuffle
1710 VR128:$src1, (memopv2f64 addr:$src2),
1711 UNPCKH_shuffle_mask)))]>;
1713 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1717 (v2f64 (vector_shuffle
1718 VR128:$src1, VR128:$src2,
1719 UNPCKL_shuffle_mask)))]>;
1720 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1721 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1722 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1724 (v2f64 (vector_shuffle
1725 VR128:$src1, (memopv2f64 addr:$src2),
1726 UNPCKL_shuffle_mask)))]>;
1727 } // AddedComplexity
1731 //===----------------------------------------------------------------------===//
1732 // SSE integer instructions
1734 // Move Instructions
1735 let neverHasSideEffects = 1 in
1736 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1737 "movdqa\t{$src, $dst|$dst, $src}", []>;
1738 let isSimpleLoad = 1, mayLoad = 1 in
1739 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1740 "movdqa\t{$src, $dst|$dst, $src}",
1741 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1743 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1744 "movdqa\t{$src, $dst|$dst, $src}",
1745 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1746 let isSimpleLoad = 1, mayLoad = 1 in
1747 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1748 "movdqu\t{$src, $dst|$dst, $src}",
1749 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1750 XS, Requires<[HasSSE2]>;
1752 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1753 "movdqu\t{$src, $dst|$dst, $src}",
1754 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1755 XS, Requires<[HasSSE2]>;
1757 // Intrinsic forms of MOVDQU load and store
1758 let isSimpleLoad = 1 in
1759 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1760 "movdqu\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1762 XS, Requires<[HasSSE2]>;
1763 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1764 "movdqu\t{$src, $dst|$dst, $src}",
1765 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1766 XS, Requires<[HasSSE2]>;
1768 let isTwoAddress = 1 in {
1770 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1771 bit Commutable = 0> {
1772 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1773 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1774 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1775 let isCommutable = Commutable;
1777 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1778 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1779 [(set VR128:$dst, (IntId VR128:$src1,
1780 (bitconvert (memopv2i64 addr:$src2))))]>;
1783 /// PDI_binop_rm - Simple SSE2 binary operator.
1784 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1785 ValueType OpVT, bit Commutable = 0> {
1786 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1787 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1788 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1789 let isCommutable = Commutable;
1791 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1793 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1794 (bitconvert (memopv2i64 addr:$src2)))))]>;
1797 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1799 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1800 /// to collapse (bitconvert VT to VT) into its operand.
1802 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1803 bit Commutable = 0> {
1804 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1805 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1806 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1807 let isCommutable = Commutable;
1809 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1810 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1811 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1816 // 128-bit Integer Arithmetic
1818 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1819 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1820 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1821 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1823 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1824 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1825 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1826 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1828 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1829 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1830 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1831 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1833 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1834 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1835 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1836 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1838 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1840 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1841 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1842 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1844 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1846 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1847 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1850 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1851 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1852 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1853 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1854 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1857 defm PSLLW : PDI_binop_rm_int<0xF1, "psllw", int_x86_sse2_psll_w>;
1858 defm PSLLD : PDI_binop_rm_int<0xF2, "pslld", int_x86_sse2_psll_d>;
1859 defm PSLLQ : PDI_binop_rm_int<0xF3, "psllq", int_x86_sse2_psll_q>;
1861 defm PSRLW : PDI_binop_rm_int<0xD1, "psrlw", int_x86_sse2_psrl_w>;
1862 defm PSRLD : PDI_binop_rm_int<0xD2, "psrld", int_x86_sse2_psrl_d>;
1863 defm PSRLQ : PDI_binop_rm_int<0xD3, "psrlq", int_x86_sse2_psrl_q>;
1865 defm PSRAW : PDI_binop_rm_int<0xE1, "psraw", int_x86_sse2_psra_w>;
1866 defm PSRAD : PDI_binop_rm_int<0xE2, "psrad", int_x86_sse2_psra_d>;
1868 // Some immediate variants need to match a bit_convert.
1869 def PSLLWri : PDIi8<0x71, MRM6r, (outs VR128:$dst),
1870 (ins VR128:$src1, i32i8imm:$src2),
1871 "psllw\t{$src2, $dst|$dst, $src2}",
1872 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1873 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1874 def PSLLDri : PDIi8<0x72, MRM6r, (outs VR128:$dst),
1875 (ins VR128:$src1, i32i8imm:$src2),
1876 "pslld\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1878 (scalar_to_vector (i32 imm:$src2))))]>;
1879 def PSLLQri : PDIi8<0x73, MRM6r, (outs VR128:$dst),
1880 (ins VR128:$src1, i32i8imm:$src2),
1881 "psllq\t{$src2, $dst|$dst, $src2}",
1882 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1883 (bc_v2i64 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1885 def PSRLWri : PDIi8<0x71, MRM2r, (outs VR128:$dst),
1886 (ins VR128:$src1, i32i8imm:$src2),
1887 "psrlw\t{$src2, $dst|$dst, $src2}",
1888 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1889 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1890 def PSRLDri : PDIi8<0x72, MRM2r, (outs VR128:$dst),
1891 (ins VR128:$src1, i32i8imm:$src2),
1892 "psrld\t{$src2, $dst|$dst, $src2}",
1893 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1894 (scalar_to_vector (i32 imm:$src2))))]>;
1895 def PSRLQri : PDIi8<0x73, MRM2r, (outs VR128:$dst),
1896 (ins VR128:$src1, i32i8imm:$src2),
1897 "psrlq\t{$src2, $dst|$dst, $src2}",
1898 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1899 (bc_v2i64 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1901 def PSRAWri : PDIi8<0x71, MRM4r, (outs VR128:$dst),
1902 (ins VR128:$src1, i32i8imm:$src2),
1903 "psraw\t{$src2, $dst|$dst, $src2}",
1904 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1905 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1906 def PSRADri : PDIi8<0x72, MRM4r, (outs VR128:$dst),
1907 (ins VR128:$src1, i32i8imm:$src2),
1908 "psrad\t{$src2, $dst|$dst, $src2}",
1909 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1910 (scalar_to_vector (i32 imm:$src2))))]>;
1912 // PSRAQ doesn't exist in SSE[1-3].
1914 // 128-bit logical shifts.
1915 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1916 def PSLLDQri : PDIi8<0x73, MRM7r,
1917 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1918 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1919 def PSRLDQri : PDIi8<0x73, MRM3r,
1920 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1921 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1922 // PSRADQri doesn't exist in SSE[1-3].
1925 let Predicates = [HasSSE2] in {
1926 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1927 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1928 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1929 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1930 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1931 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1935 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1936 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1937 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1939 let isTwoAddress = 1 in {
1940 def PANDNrr : PDI<0xDF, MRMSrcReg,
1941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1942 "pandn\t{$src2, $dst|$dst, $src2}",
1943 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1946 def PANDNrm : PDI<0xDF, MRMSrcMem,
1947 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1948 "pandn\t{$src2, $dst|$dst, $src2}",
1949 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1950 (memopv2i64 addr:$src2))))]>;
1953 // SSE2 Integer comparison
1954 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1955 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1956 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1957 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1958 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1959 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1961 // Pack instructions
1962 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1963 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1964 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1966 // Shuffle and unpack instructions
1967 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1968 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1969 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1970 [(set VR128:$dst, (v4i32 (vector_shuffle
1971 VR128:$src1, (undef),
1972 PSHUFD_shuffle_mask:$src2)))]>;
1973 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1974 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1975 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1976 [(set VR128:$dst, (v4i32 (vector_shuffle
1977 (bc_v4i32(memopv2i64 addr:$src1)),
1979 PSHUFD_shuffle_mask:$src2)))]>;
1981 // SSE2 with ImmT == Imm8 and XS prefix.
1982 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1983 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1984 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1985 [(set VR128:$dst, (v8i16 (vector_shuffle
1986 VR128:$src1, (undef),
1987 PSHUFHW_shuffle_mask:$src2)))]>,
1988 XS, Requires<[HasSSE2]>;
1989 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1990 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1991 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1992 [(set VR128:$dst, (v8i16 (vector_shuffle
1993 (bc_v8i16 (memopv2i64 addr:$src1)),
1995 PSHUFHW_shuffle_mask:$src2)))]>,
1996 XS, Requires<[HasSSE2]>;
1998 // SSE2 with ImmT == Imm8 and XD prefix.
1999 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2000 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2001 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2002 [(set VR128:$dst, (v8i16 (vector_shuffle
2003 VR128:$src1, (undef),
2004 PSHUFLW_shuffle_mask:$src2)))]>,
2005 XD, Requires<[HasSSE2]>;
2006 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2007 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2008 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2009 [(set VR128:$dst, (v8i16 (vector_shuffle
2010 (bc_v8i16 (memopv2i64 addr:$src1)),
2012 PSHUFLW_shuffle_mask:$src2)))]>,
2013 XD, Requires<[HasSSE2]>;
2016 let isTwoAddress = 1 in {
2017 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2018 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2019 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2021 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2022 UNPCKL_shuffle_mask)))]>;
2023 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2024 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2025 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2027 (v16i8 (vector_shuffle VR128:$src1,
2028 (bc_v16i8 (memopv2i64 addr:$src2)),
2029 UNPCKL_shuffle_mask)))]>;
2030 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2031 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2032 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2034 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2035 UNPCKL_shuffle_mask)))]>;
2036 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2037 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2038 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2040 (v8i16 (vector_shuffle VR128:$src1,
2041 (bc_v8i16 (memopv2i64 addr:$src2)),
2042 UNPCKL_shuffle_mask)))]>;
2043 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2044 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2045 "punpckldq\t{$src2, $dst|$dst, $src2}",
2047 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2048 UNPCKL_shuffle_mask)))]>;
2049 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2050 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2051 "punpckldq\t{$src2, $dst|$dst, $src2}",
2053 (v4i32 (vector_shuffle VR128:$src1,
2054 (bc_v4i32 (memopv2i64 addr:$src2)),
2055 UNPCKL_shuffle_mask)))]>;
2056 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2057 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2058 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2060 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2061 UNPCKL_shuffle_mask)))]>;
2062 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2063 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2064 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2066 (v2i64 (vector_shuffle VR128:$src1,
2067 (memopv2i64 addr:$src2),
2068 UNPCKL_shuffle_mask)))]>;
2070 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2071 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2072 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2074 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2075 UNPCKH_shuffle_mask)))]>;
2076 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2077 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2078 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2080 (v16i8 (vector_shuffle VR128:$src1,
2081 (bc_v16i8 (memopv2i64 addr:$src2)),
2082 UNPCKH_shuffle_mask)))]>;
2083 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2084 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2085 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2087 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2088 UNPCKH_shuffle_mask)))]>;
2089 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2090 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2091 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2093 (v8i16 (vector_shuffle VR128:$src1,
2094 (bc_v8i16 (memopv2i64 addr:$src2)),
2095 UNPCKH_shuffle_mask)))]>;
2096 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2097 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2098 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2100 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2101 UNPCKH_shuffle_mask)))]>;
2102 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2103 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2104 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2106 (v4i32 (vector_shuffle VR128:$src1,
2107 (bc_v4i32 (memopv2i64 addr:$src2)),
2108 UNPCKH_shuffle_mask)))]>;
2109 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2110 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2111 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2113 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2114 UNPCKH_shuffle_mask)))]>;
2115 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2116 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2117 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2119 (v2i64 (vector_shuffle VR128:$src1,
2120 (memopv2i64 addr:$src2),
2121 UNPCKH_shuffle_mask)))]>;
2125 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2126 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2127 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2128 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2130 let isTwoAddress = 1 in {
2131 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2132 (outs VR128:$dst), (ins VR128:$src1,
2133 GR32:$src2, i32i8imm:$src3),
2134 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2136 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2137 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2138 (outs VR128:$dst), (ins VR128:$src1,
2139 i16mem:$src2, i32i8imm:$src3),
2140 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2142 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2147 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2148 "pmovmskb\t{$src, $dst|$dst, $src}",
2149 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2151 // Conditional store
2153 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2154 "maskmovdqu\t{$mask, $src|$src, $mask}",
2155 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2157 // Non-temporal stores
2158 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2159 "movntpd\t{$src, $dst|$dst, $src}",
2160 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2161 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2162 "movntdq\t{$src, $dst|$dst, $src}",
2163 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2164 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2165 "movnti\t{$src, $dst|$dst, $src}",
2166 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2167 TB, Requires<[HasSSE2]>;
2170 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2171 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2172 TB, Requires<[HasSSE2]>;
2174 // Load, store, and memory fence
2175 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2176 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2177 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2178 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2180 //TODO: custom lower this so as to never even generate the noop
2181 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2183 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2184 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2185 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2188 // Alias instructions that map zero vector to pxor / xorp* for sse.
2189 let isReMaterializable = 1 in
2190 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2191 "pcmpeqd\t$dst, $dst",
2192 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2194 // FR64 to 128-bit vector conversion.
2195 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2196 "movsd\t{$src, $dst|$dst, $src}",
2198 (v2f64 (scalar_to_vector FR64:$src)))]>;
2199 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2200 "movsd\t{$src, $dst|$dst, $src}",
2202 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2204 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2205 "movd\t{$src, $dst|$dst, $src}",
2207 (v4i32 (scalar_to_vector GR32:$src)))]>;
2208 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2209 "movd\t{$src, $dst|$dst, $src}",
2211 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2213 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2214 "movd\t{$src, $dst|$dst, $src}",
2215 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2217 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2218 "movd\t{$src, $dst|$dst, $src}",
2219 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2221 // SSE2 instructions with XS prefix
2222 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2223 "movq\t{$src, $dst|$dst, $src}",
2225 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2226 Requires<[HasSSE2]>;
2227 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2228 "movq\t{$src, $dst|$dst, $src}",
2229 [(store (i64 (vector_extract (v2i64 VR128:$src),
2230 (iPTR 0))), addr:$dst)]>;
2232 // FIXME: may not be able to eliminate this movss with coalescing the src and
2233 // dest register classes are different. We really want to write this pattern
2235 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2236 // (f32 FR32:$src)>;
2237 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2238 "movsd\t{$src, $dst|$dst, $src}",
2239 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2241 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2242 "movsd\t{$src, $dst|$dst, $src}",
2243 [(store (f64 (vector_extract (v2f64 VR128:$src),
2244 (iPTR 0))), addr:$dst)]>;
2245 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2246 "movd\t{$src, $dst|$dst, $src}",
2247 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2249 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2250 "movd\t{$src, $dst|$dst, $src}",
2251 [(store (i32 (vector_extract (v4i32 VR128:$src),
2252 (iPTR 0))), addr:$dst)]>;
2254 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2255 "movd\t{$src, $dst|$dst, $src}",
2256 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2257 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2258 "movd\t{$src, $dst|$dst, $src}",
2259 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2262 // Move to lower bits of a VR128, leaving upper bits alone.
2263 // Three operand (but two address) aliases.
2264 let isTwoAddress = 1 in {
2265 let neverHasSideEffects = 1 in
2266 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2267 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2268 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2270 let AddedComplexity = 15 in
2271 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2272 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2273 "movsd\t{$src2, $dst|$dst, $src2}",
2275 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2276 MOVL_shuffle_mask)))]>;
2279 // Store / copy lower 64-bits of a XMM register.
2280 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2281 "movq\t{$src, $dst|$dst, $src}",
2282 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2284 // Move to lower bits of a VR128 and zeroing upper bits.
2285 // Loading from memory automatically zeroing upper bits.
2286 let AddedComplexity = 20 in
2287 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2288 "movsd\t{$src, $dst|$dst, $src}",
2290 (v2f64 (vector_shuffle immAllZerosV_bc,
2291 (v2f64 (scalar_to_vector
2292 (loadf64 addr:$src))),
2293 MOVL_shuffle_mask)))]>;
2295 // movd / movq to XMM register zero-extends
2296 let AddedComplexity = 15 in {
2297 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2298 "movd\t{$src, $dst|$dst, $src}",
2300 (v4i32 (vector_shuffle immAllZerosV,
2301 (v4i32 (scalar_to_vector GR32:$src)),
2302 MOVL_shuffle_mask)))]>;
2303 // This is X86-64 only.
2304 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2305 "mov{d|q}\t{$src, $dst|$dst, $src}",
2307 (v2i64 (vector_shuffle immAllZerosV_bc,
2308 (v2i64 (scalar_to_vector GR64:$src)),
2309 MOVL_shuffle_mask)))]>;
2312 let AddedComplexity = 20 in {
2313 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2314 "movd\t{$src, $dst|$dst, $src}",
2316 (v4i32 (vector_shuffle immAllZerosV,
2317 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2318 MOVL_shuffle_mask)))]>;
2319 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2320 "movq\t{$src, $dst|$dst, $src}",
2322 (v2i64 (vector_shuffle immAllZerosV_bc,
2323 (v2i64 (scalar_to_vector (loadi64 addr:$src))),
2324 MOVL_shuffle_mask)))]>, XS,
2325 Requires<[HasSSE2]>;
2328 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2329 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2330 let AddedComplexity = 15 in
2331 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2332 "movq\t{$src, $dst|$dst, $src}",
2333 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2335 MOVL_shuffle_mask)))]>,
2336 XS, Requires<[HasSSE2]>;
2338 let AddedComplexity = 20 in
2339 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2340 "movq\t{$src, $dst|$dst, $src}",
2341 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2342 (memopv2i64 addr:$src),
2343 MOVL_shuffle_mask)))]>,
2344 XS, Requires<[HasSSE2]>;
2346 //===----------------------------------------------------------------------===//
2347 // SSE3 Instructions
2348 //===----------------------------------------------------------------------===//
2350 // Move Instructions
2351 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2352 "movshdup\t{$src, $dst|$dst, $src}",
2353 [(set VR128:$dst, (v4f32 (vector_shuffle
2354 VR128:$src, (undef),
2355 MOVSHDUP_shuffle_mask)))]>;
2356 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2357 "movshdup\t{$src, $dst|$dst, $src}",
2358 [(set VR128:$dst, (v4f32 (vector_shuffle
2359 (memopv4f32 addr:$src), (undef),
2360 MOVSHDUP_shuffle_mask)))]>;
2362 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2363 "movsldup\t{$src, $dst|$dst, $src}",
2364 [(set VR128:$dst, (v4f32 (vector_shuffle
2365 VR128:$src, (undef),
2366 MOVSLDUP_shuffle_mask)))]>;
2367 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2368 "movsldup\t{$src, $dst|$dst, $src}",
2369 [(set VR128:$dst, (v4f32 (vector_shuffle
2370 (memopv4f32 addr:$src), (undef),
2371 MOVSLDUP_shuffle_mask)))]>;
2373 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2374 "movddup\t{$src, $dst|$dst, $src}",
2375 [(set VR128:$dst, (v2f64 (vector_shuffle
2376 VR128:$src, (undef),
2377 SSE_splat_lo_mask)))]>;
2378 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2379 "movddup\t{$src, $dst|$dst, $src}",
2381 (v2f64 (vector_shuffle
2382 (scalar_to_vector (loadf64 addr:$src)),
2384 SSE_splat_lo_mask)))]>;
2387 let isTwoAddress = 1 in {
2388 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2389 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2390 "addsubps\t{$src2, $dst|$dst, $src2}",
2391 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2393 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2394 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2395 "addsubps\t{$src2, $dst|$dst, $src2}",
2396 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2397 (load addr:$src2)))]>;
2398 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2399 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2400 "addsubpd\t{$src2, $dst|$dst, $src2}",
2401 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2403 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2404 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2405 "addsubpd\t{$src2, $dst|$dst, $src2}",
2406 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2407 (load addr:$src2)))]>;
2410 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2411 "lddqu\t{$src, $dst|$dst, $src}",
2412 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2415 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2416 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2417 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2418 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2419 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2420 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2421 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2422 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2423 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2424 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2425 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2426 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2427 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2428 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2430 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2432 let isTwoAddress = 1 in {
2433 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2434 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2435 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2436 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2437 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2438 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2439 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2440 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2443 // Thread synchronization
2444 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2445 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2446 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2447 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2449 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2450 let AddedComplexity = 15 in
2451 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2452 MOVSHDUP_shuffle_mask)),
2453 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2454 let AddedComplexity = 20 in
2455 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2456 MOVSHDUP_shuffle_mask)),
2457 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2459 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2460 let AddedComplexity = 15 in
2461 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2462 MOVSLDUP_shuffle_mask)),
2463 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2464 let AddedComplexity = 20 in
2465 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2466 MOVSLDUP_shuffle_mask)),
2467 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2469 //===----------------------------------------------------------------------===//
2470 // SSSE3 Instructions
2471 //===----------------------------------------------------------------------===//
2473 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2474 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2475 Intrinsic IntId64, Intrinsic IntId128> {
2476 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2478 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2480 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2481 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2483 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2485 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2488 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2491 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2493 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2496 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2499 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2500 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2501 Intrinsic IntId64, Intrinsic IntId128> {
2502 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2504 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2505 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2507 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2512 (bitconvert (memopv4i16 addr:$src))))]>;
2514 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2517 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2520 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2525 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2528 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2529 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2530 Intrinsic IntId64, Intrinsic IntId128> {
2531 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2534 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2536 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2538 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2541 (bitconvert (memopv2i32 addr:$src))))]>;
2543 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2545 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2546 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2549 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2554 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2557 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2558 int_x86_ssse3_pabs_b,
2559 int_x86_ssse3_pabs_b_128>;
2560 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2561 int_x86_ssse3_pabs_w,
2562 int_x86_ssse3_pabs_w_128>;
2563 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2564 int_x86_ssse3_pabs_d,
2565 int_x86_ssse3_pabs_d_128>;
2567 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2568 let isTwoAddress = 1 in {
2569 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2570 Intrinsic IntId64, Intrinsic IntId128,
2571 bit Commutable = 0> {
2572 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2573 (ins VR64:$src1, VR64:$src2),
2574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2575 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2576 let isCommutable = Commutable;
2578 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2579 (ins VR64:$src1, i64mem:$src2),
2580 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2582 (IntId64 VR64:$src1,
2583 (bitconvert (memopv8i8 addr:$src2))))]>;
2585 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2586 (ins VR128:$src1, VR128:$src2),
2587 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2588 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2590 let isCommutable = Commutable;
2592 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2593 (ins VR128:$src1, i128mem:$src2),
2594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2596 (IntId128 VR128:$src1,
2597 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2601 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2602 let isTwoAddress = 1 in {
2603 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2604 Intrinsic IntId64, Intrinsic IntId128,
2605 bit Commutable = 0> {
2606 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2607 (ins VR64:$src1, VR64:$src2),
2608 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2609 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2610 let isCommutable = Commutable;
2612 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2613 (ins VR64:$src1, i64mem:$src2),
2614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2616 (IntId64 VR64:$src1,
2617 (bitconvert (memopv4i16 addr:$src2))))]>;
2619 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2620 (ins VR128:$src1, VR128:$src2),
2621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2622 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2624 let isCommutable = Commutable;
2626 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2627 (ins VR128:$src1, i128mem:$src2),
2628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2630 (IntId128 VR128:$src1,
2631 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2635 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2636 let isTwoAddress = 1 in {
2637 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2638 Intrinsic IntId64, Intrinsic IntId128,
2639 bit Commutable = 0> {
2640 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2641 (ins VR64:$src1, VR64:$src2),
2642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2643 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2644 let isCommutable = Commutable;
2646 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2647 (ins VR64:$src1, i64mem:$src2),
2648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2650 (IntId64 VR64:$src1,
2651 (bitconvert (memopv2i32 addr:$src2))))]>;
2653 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2654 (ins VR128:$src1, VR128:$src2),
2655 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2656 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2658 let isCommutable = Commutable;
2660 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2661 (ins VR128:$src1, i128mem:$src2),
2662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2664 (IntId128 VR128:$src1,
2665 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2669 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2670 int_x86_ssse3_phadd_w,
2671 int_x86_ssse3_phadd_w_128, 1>;
2672 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2673 int_x86_ssse3_phadd_d,
2674 int_x86_ssse3_phadd_d_128, 1>;
2675 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2676 int_x86_ssse3_phadd_sw,
2677 int_x86_ssse3_phadd_sw_128, 1>;
2678 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2679 int_x86_ssse3_phsub_w,
2680 int_x86_ssse3_phsub_w_128>;
2681 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2682 int_x86_ssse3_phsub_d,
2683 int_x86_ssse3_phsub_d_128>;
2684 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2685 int_x86_ssse3_phsub_sw,
2686 int_x86_ssse3_phsub_sw_128>;
2687 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2688 int_x86_ssse3_pmadd_ub_sw,
2689 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2690 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2691 int_x86_ssse3_pmul_hr_sw,
2692 int_x86_ssse3_pmul_hr_sw_128, 1>;
2693 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2694 int_x86_ssse3_pshuf_b,
2695 int_x86_ssse3_pshuf_b_128>;
2696 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2697 int_x86_ssse3_psign_b,
2698 int_x86_ssse3_psign_b_128>;
2699 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2700 int_x86_ssse3_psign_w,
2701 int_x86_ssse3_psign_w_128>;
2702 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2703 int_x86_ssse3_psign_d,
2704 int_x86_ssse3_psign_d_128>;
2706 let isTwoAddress = 1 in {
2707 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2708 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2709 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2711 (int_x86_ssse3_palign_r
2712 VR64:$src1, VR64:$src2,
2714 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2715 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2716 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2718 (int_x86_ssse3_palign_r
2720 (bitconvert (memopv2i32 addr:$src2)),
2723 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2724 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2725 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2727 (int_x86_ssse3_palign_r_128
2728 VR128:$src1, VR128:$src2,
2729 imm:$src3))]>, OpSize;
2730 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2731 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2732 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2734 (int_x86_ssse3_palign_r_128
2736 (bitconvert (memopv4i32 addr:$src2)),
2737 imm:$src3))]>, OpSize;
2740 //===----------------------------------------------------------------------===//
2741 // Non-Instruction Patterns
2742 //===----------------------------------------------------------------------===//
2744 // 128-bit vector undef's.
2745 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2746 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2747 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2748 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2749 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2750 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2752 // extload f32 -> f64. This matches load+fextend because we have a hack in
2753 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2754 // Since these loads aren't folded into the fextend, we have to match it
2756 let Predicates = [HasSSE2] in
2757 def : Pat<(fextend (loadf32 addr:$src)),
2758 (CVTSS2SDrm addr:$src)>;
2761 let Predicates = [HasSSE2] in {
2762 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2763 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2764 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2765 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2766 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2767 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2768 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2769 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2770 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2771 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2772 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2773 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2774 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2775 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2776 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2777 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2778 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2779 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2780 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2781 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2782 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2783 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2784 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2785 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2786 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2787 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2788 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2789 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2790 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2791 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2794 // Move scalar to XMM zero-extended
2795 // movd to XMM register zero-extends
2796 let AddedComplexity = 15 in {
2797 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2798 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
2799 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2800 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2801 def : Pat<(v4f32 (vector_shuffle immAllZerosV_bc,
2802 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2803 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2806 // Splat v2f64 / v2i64
2807 let AddedComplexity = 10 in {
2808 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2809 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2810 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2811 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2812 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2813 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2814 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2815 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2819 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2820 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2821 Requires<[HasSSE1]>;
2823 // Special unary SHUFPSrri case.
2824 // FIXME: when we want non two-address code, then we should use PSHUFD?
2825 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2826 SHUFP_unary_shuffle_mask:$sm)),
2827 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2828 Requires<[HasSSE1]>;
2829 // Special unary SHUFPDrri case.
2830 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2831 SHUFP_unary_shuffle_mask:$sm)),
2832 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2833 Requires<[HasSSE2]>;
2834 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2835 def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
2836 SHUFP_unary_shuffle_mask:$sm),
2837 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2838 Requires<[HasSSE2]>;
2839 // Special binary v4i32 shuffle cases with SHUFPS.
2840 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2841 PSHUFD_binary_shuffle_mask:$sm)),
2842 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2843 Requires<[HasSSE2]>;
2844 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2845 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2846 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2847 Requires<[HasSSE2]>;
2848 // Special binary v2i64 shuffle cases using SHUFPDrri.
2849 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2850 SHUFP_shuffle_mask:$sm)),
2851 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2852 Requires<[HasSSE2]>;
2853 // Special unary SHUFPDrri case.
2854 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2855 SHUFP_unary_shuffle_mask:$sm)),
2856 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2857 Requires<[HasSSE2]>;
2859 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2860 let AddedComplexity = 10 in {
2861 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2862 UNPCKL_v_undef_shuffle_mask)),
2863 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2864 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2865 UNPCKL_v_undef_shuffle_mask)),
2866 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2867 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2868 UNPCKL_v_undef_shuffle_mask)),
2869 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2870 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2871 UNPCKL_v_undef_shuffle_mask)),
2872 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2875 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2876 let AddedComplexity = 10 in {
2877 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2878 UNPCKH_v_undef_shuffle_mask)),
2879 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2880 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2881 UNPCKH_v_undef_shuffle_mask)),
2882 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2883 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2884 UNPCKH_v_undef_shuffle_mask)),
2885 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2886 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2887 UNPCKH_v_undef_shuffle_mask)),
2888 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2891 let AddedComplexity = 15 in {
2892 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2893 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2894 MOVHP_shuffle_mask)),
2895 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2897 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2898 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2899 MOVHLPS_shuffle_mask)),
2900 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2902 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2903 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2904 MOVHLPS_v_undef_shuffle_mask)),
2905 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2906 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2907 MOVHLPS_v_undef_shuffle_mask)),
2908 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2911 let AddedComplexity = 20 in {
2912 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2913 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2914 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2915 MOVLP_shuffle_mask)),
2916 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2917 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2918 MOVLP_shuffle_mask)),
2919 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2920 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2921 MOVHP_shuffle_mask)),
2922 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2923 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2924 MOVHP_shuffle_mask)),
2925 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2927 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2928 MOVLP_shuffle_mask)),
2929 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2930 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2931 MOVLP_shuffle_mask)),
2932 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2933 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2934 MOVHP_shuffle_mask)),
2935 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2936 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2937 MOVLP_shuffle_mask)),
2938 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2941 let AddedComplexity = 15 in {
2942 // Setting the lowest element in the vector.
2943 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2944 MOVL_shuffle_mask)),
2945 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2946 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2947 MOVL_shuffle_mask)),
2948 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2950 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2951 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2952 MOVLP_shuffle_mask)),
2953 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2954 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2955 MOVLP_shuffle_mask)),
2956 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2959 // Set lowest element and zero upper elements.
2960 let AddedComplexity = 15 in
2961 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
2962 MOVL_shuffle_mask)),
2963 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2966 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2967 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2968 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2969 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2970 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2971 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2972 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2973 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2974 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2975 Requires<[HasSSE2]>;
2976 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2977 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2978 Requires<[HasSSE2]>;
2979 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2980 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2981 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2982 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2983 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2984 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2985 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2986 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2987 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2988 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2989 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2990 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2991 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2992 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2993 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2994 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2996 // Some special case pandn patterns.
2997 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2999 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3000 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3002 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3003 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3005 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3007 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3008 (memopv2i64 addr:$src2))),
3009 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3010 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3011 (memopv2i64 addr:$src2))),
3012 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3013 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3014 (memopv2i64 addr:$src2))),
3015 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3017 // vector -> vector casts
3018 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3019 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3020 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3021 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3023 // Use movaps / movups for SSE integer load / store (one byte shorter).
3024 def : Pat<(alignedloadv4i32 addr:$src),
3025 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3026 def : Pat<(loadv4i32 addr:$src),
3027 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3028 def : Pat<(alignedloadv2i64 addr:$src),
3029 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3030 def : Pat<(loadv2i64 addr:$src),
3031 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3033 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3034 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3035 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3036 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3037 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3038 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3039 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3040 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3041 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3042 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3043 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3044 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3045 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3046 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3047 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3048 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3050 //===----------------------------------------------------------------------===//
3051 // SSE4.1 Instructions
3052 //===----------------------------------------------------------------------===//
3054 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3055 bits<8> opcsd, bits<8> opcpd,
3060 Intrinsic V2F64Int> {
3061 // Intrinsic operation, reg.
3062 def SSr_Int : SS4AI<opcss, MRMSrcReg,
3063 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3064 !strconcat(OpcodeStr,
3065 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3066 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3069 // Intrinsic operation, mem.
3070 def SSm_Int : SS4AI<opcss, MRMSrcMem,
3071 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3072 !strconcat(OpcodeStr,
3073 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3074 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3077 // Vector intrinsic operation, reg
3078 def PSr_Int : SS4AI<opcps, MRMSrcReg,
3079 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3080 !strconcat(OpcodeStr,
3081 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3082 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3085 // Vector intrinsic operation, mem
3086 def PSm_Int : SS4AI<opcps, MRMSrcMem,
3087 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3088 !strconcat(OpcodeStr,
3089 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3090 [(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
3093 // Intrinsic operation, reg.
3094 def SDr_Int : SS4AI<opcsd, MRMSrcReg,
3095 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3096 !strconcat(OpcodeStr,
3097 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3098 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3101 // Intrinsic operation, mem.
3102 def SDm_Int : SS4AI<opcsd, MRMSrcMem,
3103 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3104 !strconcat(OpcodeStr,
3105 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3106 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3109 // Vector intrinsic operation, reg
3110 def PDr_Int : SS4AI<opcpd, MRMSrcReg,
3111 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3112 !strconcat(OpcodeStr,
3113 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3114 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3117 // Vector intrinsic operation, mem
3118 def PDm_Int : SS4AI<opcpd, MRMSrcMem,
3119 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3120 !strconcat(OpcodeStr,
3121 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3122 [(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
3126 // FP round - roundss, roundps, roundsd, roundpd
3127 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3128 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3129 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3131 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3132 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3133 Intrinsic IntId128> {
3134 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3136 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3137 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3138 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3140 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3143 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3146 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3147 int_x86_sse41_phminposuw>;
3149 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3150 let isTwoAddress = 1 in {
3151 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3152 Intrinsic IntId128, bit Commutable = 0> {
3153 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3154 (ins VR128:$src1, VR128:$src2),
3155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3156 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3158 let isCommutable = Commutable;
3160 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3161 (ins VR128:$src1, i128mem:$src2),
3162 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3164 (IntId128 VR128:$src1,
3165 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3169 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3170 int_x86_sse41_pcmpeqq, 1>;
3171 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3172 int_x86_sse41_packusdw, 0>;
3173 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3174 int_x86_sse41_pminsb, 1>;
3175 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3176 int_x86_sse41_pminsd, 1>;
3177 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3178 int_x86_sse41_pminud, 1>;
3179 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3180 int_x86_sse41_pminuw, 1>;
3181 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3182 int_x86_sse41_pmaxsb, 1>;
3183 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3184 int_x86_sse41_pmaxsd, 1>;
3185 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3186 int_x86_sse41_pmaxud, 1>;
3187 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3188 int_x86_sse41_pmaxuw, 1>;
3189 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
3190 int_x86_sse41_pmuldq, 1>;
3193 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3194 let isTwoAddress = 1 in {
3195 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, SDNode OpNode,
3196 Intrinsic IntId128, bit Commutable = 0> {
3197 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3198 (ins VR128:$src1, VR128:$src2),
3199 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3200 [(set VR128:$dst, (OpNode (v4i32 VR128:$src1),
3201 VR128:$src2))]>, OpSize {
3202 let isCommutable = Commutable;
3204 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3205 (ins VR128:$src1, VR128:$src2),
3206 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3207 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3209 let isCommutable = Commutable;
3211 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3212 (ins VR128:$src1, i128mem:$src2),
3213 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3215 (OpNode VR128:$src1, (memopv4i32 addr:$src2)))]>, OpSize;
3216 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3217 (ins VR128:$src1, i128mem:$src2),
3218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3220 (IntId128 VR128:$src1, (memopv4i32 addr:$src2)))]>,
3224 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul,
3225 int_x86_sse41_pmulld, 1>;
3228 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate
3229 let isTwoAddress = 1 in {
3230 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3231 Intrinsic IntId128, bit Commutable = 0> {
3232 def rri : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3233 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3234 !strconcat(OpcodeStr,
3235 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3237 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3239 let isCommutable = Commutable;
3241 def rmi : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3242 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3243 !strconcat(OpcodeStr,
3244 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3246 (IntId128 VR128:$src1,
3247 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3252 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3253 int_x86_sse41_blendps, 0>;
3254 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3255 int_x86_sse41_blendpd, 0>;
3256 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3257 int_x86_sse41_pblendw, 0>;
3258 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3259 int_x86_sse41_dpps, 1>;
3260 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3261 int_x86_sse41_dppd, 1>;
3262 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3263 int_x86_sse41_mpsadbw, 0>;
3266 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate
3267 let Uses = [XMM0], isTwoAddress = 1 in {
3268 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3269 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3270 (ins VR128:$src1, VR128:$src2),
3271 !strconcat(OpcodeStr,
3272 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3273 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3276 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3277 (ins VR128:$src1, i128mem:$src2),
3278 !strconcat(OpcodeStr,
3279 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3282 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3286 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3287 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3288 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3291 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3292 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3293 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3294 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3296 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3297 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3299 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3302 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3303 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3304 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3305 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3306 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3307 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3309 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3310 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3311 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3312 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3314 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3317 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3320 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3321 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3322 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3323 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3325 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3326 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3327 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3328 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3330 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3331 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3333 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3336 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3337 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3340 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3341 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3342 def rr : SS4AI<opc, MRMSrcReg, (outs GR32:$dst),
3343 (ins VR128:$src1, i32i8imm:$src2),
3344 !strconcat(OpcodeStr,
3345 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3346 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3348 def mr : SS4AI<opc, MRMDestMem, (outs),
3349 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3350 !strconcat(OpcodeStr,
3351 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3354 // There's an AssertZext in the way of writing the store pattern
3355 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3358 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3361 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3362 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3363 def mr : SS4AI<opc, MRMDestMem, (outs),
3364 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3365 !strconcat(OpcodeStr,
3366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3369 // There's an AssertZext in the way of writing the store pattern
3370 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3373 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3376 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3377 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3378 def rr : SS4AI<opc, MRMSrcReg, (outs GR32:$dst),
3379 (ins VR128:$src1, i32i8imm:$src2),
3380 !strconcat(OpcodeStr,
3381 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3383 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3384 def mr : SS4AI<opc, MRMDestMem, (outs),
3385 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3386 !strconcat(OpcodeStr,
3387 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3388 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3389 addr:$dst)]>, OpSize;
3392 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3395 /// SS41I_extractf32 - SSE 4.1 extract 32 bits to fp reg or memory destination
3396 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3397 def rr : SS4AI<opc, MRMSrcReg, (outs FR32:$dst),
3398 (ins VR128:$src1, i32i8imm:$src2),
3399 !strconcat(OpcodeStr,
3400 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3402 (extractelt (v4f32 VR128:$src1), imm:$src2))]>, OpSize;
3403 def mr : SS4AI<opc, MRMDestMem, (outs),
3404 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3405 !strconcat(OpcodeStr,
3406 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 [(store (extractelt (v4f32 VR128:$src1), imm:$src2),
3408 addr:$dst)]>, OpSize;
3411 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3413 let isTwoAddress = 1 in {
3414 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3415 def rr : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3416 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3417 !strconcat(OpcodeStr,
3418 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3420 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3421 def rm : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3422 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3423 !strconcat(OpcodeStr,
3424 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3426 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3427 imm:$src3))]>, OpSize;
3431 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3433 let isTwoAddress = 1 in {
3434 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3435 def rr : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3436 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3437 !strconcat(OpcodeStr,
3438 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3440 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3442 def rm : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3443 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3444 !strconcat(OpcodeStr,
3445 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3447 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3448 imm:$src3)))]>, OpSize;
3452 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3454 let isTwoAddress = 1 in {
3455 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3456 def rr : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3457 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3458 !strconcat(OpcodeStr,
3459 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3461 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3462 def rm : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3463 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3464 !strconcat(OpcodeStr,
3465 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3467 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3468 imm:$src3))]>, OpSize;
3472 defm INSERTPS : SS41I_insertf32<0x31, "insertps">;