1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (store node:$val, node:$ptr), [{
102 return cast<StoreSDNode>(N)->getAlignment() >= 16;
105 // Like 'load', but always requires vector alignment.
106 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
107 return cast<LoadSDNode>(N)->getAlignment() >= 16;
110 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
111 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
112 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
113 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
114 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
115 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
117 // Like 'load', but uses special alignment checks suitable for use in
118 // memory operands in most SSE instructions, which are required to
119 // be naturally aligned on some targets but not on others.
120 // FIXME: Actually implement support for targets that don't require the
121 // alignment. This probably wants a subtarget predicate.
122 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAlignment() >= 16;
126 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
127 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
128 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
129 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
130 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
131 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
132 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 // FIXME: 8 byte alignment for mmx reads is not required
137 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
138 return cast<LoadSDNode>(N)->getAlignment() >= 8;
141 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
142 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
143 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
144 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
146 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
147 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
148 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
149 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
150 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
151 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
153 def vzmovl_v2i64 : PatFrag<(ops node:$src),
154 (bitconvert (v2i64 (X86vzmovl
155 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
156 def vzmovl_v4i32 : PatFrag<(ops node:$src),
157 (bitconvert (v4i32 (X86vzmovl
158 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
160 def vzload_v2i64 : PatFrag<(ops node:$src),
161 (bitconvert (v2i64 (X86vzload node:$src)))>;
164 def fp32imm0 : PatLeaf<(f32 fpimm), [{
165 return N->isExactlyValue(+0.0);
168 def PSxLDQ_imm : SDNodeXForm<imm, [{
169 // Transformation function: imm >> 3
170 return getI32Imm(N->getZExtValue() >> 3);
173 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
175 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
176 return getI8Imm(X86::getShuffleSHUFImmediate(N));
179 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
181 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
182 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
185 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
187 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
191 def SSE_splat_mask : PatLeaf<(build_vector), [{
192 return X86::isSplatMask(N);
193 }], SHUFFLE_get_shuf_imm>;
195 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
196 return X86::isSplatLoMask(N);
199 def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
200 return X86::isMOVDDUPMask(N);
203 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
204 return X86::isMOVHLPSMask(N);
207 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
208 return X86::isMOVHLPS_v_undef_Mask(N);
211 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHPMask(N);
215 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVLPMask(N);
219 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVLMask(N);
223 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVSHDUPMask(N);
227 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVSLDUPMask(N);
231 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isUNPCKLMask(N);
235 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isUNPCKHMask(N);
239 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKL_v_undef_Mask(N);
243 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKH_v_undef_Mask(N);
247 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isPSHUFDMask(N);
249 }], SHUFFLE_get_shuf_imm>;
251 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isPSHUFHWMask(N);
253 }], SHUFFLE_get_pshufhw_imm>;
255 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFLWMask(N);
257 }], SHUFFLE_get_pshuflw_imm>;
259 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isSHUFPMask(N);
265 }], SHUFFLE_get_shuf_imm>;
267 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isSHUFPMask(N);
269 }], SHUFFLE_get_shuf_imm>;
272 //===----------------------------------------------------------------------===//
273 // SSE scalar FP Instructions
274 //===----------------------------------------------------------------------===//
276 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
277 // scheduler into a branch sequence.
278 // These are expanded by the scheduler.
279 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
280 def CMOV_FR32 : I<0, Pseudo,
281 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
282 "#CMOV_FR32 PSEUDO!",
283 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
285 def CMOV_FR64 : I<0, Pseudo,
286 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
287 "#CMOV_FR64 PSEUDO!",
288 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
290 def CMOV_V4F32 : I<0, Pseudo,
291 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V4F32 PSEUDO!",
294 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
296 def CMOV_V2F64 : I<0, Pseudo,
297 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
298 "#CMOV_V2F64 PSEUDO!",
300 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
302 def CMOV_V2I64 : I<0, Pseudo,
303 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
304 "#CMOV_V2I64 PSEUDO!",
306 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 let neverHasSideEffects = 1 in
316 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
317 "movss\t{$src, $dst|$dst, $src}", []>;
318 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
319 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
320 "movss\t{$src, $dst|$dst, $src}",
321 [(set FR32:$dst, (loadf32 addr:$src))]>;
322 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
323 "movss\t{$src, $dst|$dst, $src}",
324 [(store FR32:$src, addr:$dst)]>;
326 // Conversion instructions
327 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
328 "cvttss2si\t{$src, $dst|$dst, $src}",
329 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
330 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
331 "cvttss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
333 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
334 "cvtsi2ss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
336 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
337 "cvtsi2ss\t{$src, $dst|$dst, $src}",
338 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
340 // Match intrinsics which expect XMM operand(s).
341 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
342 "cvtss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
344 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
345 "cvtss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (int_x86_sse_cvtss2si
347 (load addr:$src)))]>;
349 // Match intrinisics which expect MM and XMM operand(s).
350 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
351 "cvtps2pi\t{$src, $dst|$dst, $src}",
352 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
353 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
354 "cvtps2pi\t{$src, $dst|$dst, $src}",
355 [(set VR64:$dst, (int_x86_sse_cvtps2pi
356 (load addr:$src)))]>;
357 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
358 "cvttps2pi\t{$src, $dst|$dst, $src}",
359 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
360 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
361 "cvttps2pi\t{$src, $dst|$dst, $src}",
362 [(set VR64:$dst, (int_x86_sse_cvttps2pi
363 (load addr:$src)))]>;
364 let Constraints = "$src1 = $dst" in {
365 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
366 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
367 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
368 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
370 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
371 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
372 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
374 (load addr:$src2)))]>;
377 // Aliases for intrinsics
378 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
379 "cvttss2si\t{$src, $dst|$dst, $src}",
381 (int_x86_sse_cvttss2si VR128:$src))]>;
382 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
383 "cvttss2si\t{$src, $dst|$dst, $src}",
385 (int_x86_sse_cvttss2si(load addr:$src)))]>;
387 let Constraints = "$src1 = $dst" in {
388 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
389 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
390 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
391 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
393 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
394 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
395 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
396 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
397 (loadi32 addr:$src2)))]>;
400 // Comparison instructions
401 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
402 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
403 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
404 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
406 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
407 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
408 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
411 let Defs = [EFLAGS] in {
412 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
413 "ucomiss\t{$src2, $src1|$src1, $src2}",
414 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
415 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
416 "ucomiss\t{$src2, $src1|$src1, $src2}",
417 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
421 // Aliases to match intrinsics which expect XMM operand(s).
422 let Constraints = "$src1 = $dst" in {
423 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
424 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
425 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
426 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
427 VR128:$src, imm:$cc))]>;
428 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
429 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
430 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
431 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
432 (load addr:$src), imm:$cc))]>;
435 let Defs = [EFLAGS] in {
436 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
437 "ucomiss\t{$src2, $src1|$src1, $src2}",
438 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
440 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
441 "ucomiss\t{$src2, $src1|$src1, $src2}",
442 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
445 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
446 "comiss\t{$src2, $src1|$src1, $src2}",
447 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
449 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
450 "comiss\t{$src2, $src1|$src1, $src2}",
451 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
455 // Aliases of packed SSE1 instructions for scalar use. These all have names that
458 // Alias instructions that map fld0 to pxor for sse.
459 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
460 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
461 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
462 Requires<[HasSSE1]>, TB, OpSize;
464 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
466 let neverHasSideEffects = 1 in
467 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
468 "movaps\t{$src, $dst|$dst, $src}", []>;
470 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
472 let canFoldAsLoad = 1 in
473 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
474 "movaps\t{$src, $dst|$dst, $src}",
475 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
477 // Alias bitwise logical operations using SSE logical ops on packed FP values.
478 let Constraints = "$src1 = $dst" in {
479 let isCommutable = 1 in {
480 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
481 (ins FR32:$src1, FR32:$src2),
482 "andps\t{$src2, $dst|$dst, $src2}",
483 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
484 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
485 (ins FR32:$src1, FR32:$src2),
486 "orps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
488 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
489 (ins FR32:$src1, FR32:$src2),
490 "xorps\t{$src2, $dst|$dst, $src2}",
491 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
494 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
495 (ins FR32:$src1, f128mem:$src2),
496 "andps\t{$src2, $dst|$dst, $src2}",
497 [(set FR32:$dst, (X86fand FR32:$src1,
498 (memopfsf32 addr:$src2)))]>;
499 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
500 (ins FR32:$src1, f128mem:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1,
503 (memopfsf32 addr:$src2)))]>;
504 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
505 (ins FR32:$src1, f128mem:$src2),
506 "xorps\t{$src2, $dst|$dst, $src2}",
507 [(set FR32:$dst, (X86fxor FR32:$src1,
508 (memopfsf32 addr:$src2)))]>;
510 let neverHasSideEffects = 1 in {
511 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
512 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
513 "andnps\t{$src2, $dst|$dst, $src2}", []>;
515 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
516 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
517 "andnps\t{$src2, $dst|$dst, $src2}", []>;
521 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
523 /// In addition, we also have a special variant of the scalar form here to
524 /// represent the associated intrinsic operation. This form is unlike the
525 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
526 /// and leaves the top elements undefined.
528 /// These three forms can each be reg+reg or reg+mem, so there are a total of
529 /// six "instructions".
531 let Constraints = "$src1 = $dst" in {
532 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
533 SDNode OpNode, Intrinsic F32Int,
534 bit Commutable = 0> {
535 // Scalar operation, reg+reg.
536 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
537 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
538 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
539 let isCommutable = Commutable;
542 // Scalar operation, reg+mem.
543 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
544 (ins FR32:$src1, f32mem:$src2),
545 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
546 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
548 // Vector operation, reg+reg.
549 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
550 (ins VR128:$src1, VR128:$src2),
551 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
552 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
553 let isCommutable = Commutable;
556 // Vector operation, reg+mem.
557 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
558 (ins VR128:$src1, f128mem:$src2),
559 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
562 // Intrinsic operation, reg+reg.
563 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
564 (ins VR128:$src1, VR128:$src2),
565 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
566 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
567 let isCommutable = Commutable;
570 // Intrinsic operation, reg+mem.
571 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
572 (ins VR128:$src1, ssmem:$src2),
573 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
574 [(set VR128:$dst, (F32Int VR128:$src1,
575 sse_load_f32:$src2))]>;
579 // Arithmetic instructions
580 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
581 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
582 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
583 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
585 /// sse1_fp_binop_rm - Other SSE1 binops
587 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
588 /// instructions for a full-vector intrinsic form. Operations that map
589 /// onto C operators don't use this form since they just use the plain
590 /// vector form instead of having a separate vector intrinsic form.
592 /// This provides a total of eight "instructions".
594 let Constraints = "$src1 = $dst" in {
595 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
599 bit Commutable = 0> {
601 // Scalar operation, reg+reg.
602 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
603 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
604 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
605 let isCommutable = Commutable;
608 // Scalar operation, reg+mem.
609 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
610 (ins FR32:$src1, f32mem:$src2),
611 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
612 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
614 // Vector operation, reg+reg.
615 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
616 (ins VR128:$src1, VR128:$src2),
617 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
618 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
619 let isCommutable = Commutable;
622 // Vector operation, reg+mem.
623 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
624 (ins VR128:$src1, f128mem:$src2),
625 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
626 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
628 // Intrinsic operation, reg+reg.
629 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
630 (ins VR128:$src1, VR128:$src2),
631 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
633 let isCommutable = Commutable;
636 // Intrinsic operation, reg+mem.
637 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
638 (ins VR128:$src1, ssmem:$src2),
639 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
640 [(set VR128:$dst, (F32Int VR128:$src1,
641 sse_load_f32:$src2))]>;
643 // Vector intrinsic operation, reg+reg.
644 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
645 (ins VR128:$src1, VR128:$src2),
646 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
647 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
648 let isCommutable = Commutable;
651 // Vector intrinsic operation, reg+mem.
652 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
653 (ins VR128:$src1, f128mem:$src2),
654 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
655 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
659 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
660 int_x86_sse_max_ss, int_x86_sse_max_ps>;
661 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
662 int_x86_sse_min_ss, int_x86_sse_min_ps>;
664 //===----------------------------------------------------------------------===//
665 // SSE packed FP Instructions
668 let neverHasSideEffects = 1 in
669 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
670 "movaps\t{$src, $dst|$dst, $src}", []>;
671 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
672 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
673 "movaps\t{$src, $dst|$dst, $src}",
674 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
676 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
677 "movaps\t{$src, $dst|$dst, $src}",
678 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
680 let neverHasSideEffects = 1 in
681 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
682 "movups\t{$src, $dst|$dst, $src}", []>;
683 let canFoldAsLoad = 1 in
684 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
685 "movups\t{$src, $dst|$dst, $src}",
686 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
687 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
688 "movups\t{$src, $dst|$dst, $src}",
689 [(store (v4f32 VR128:$src), addr:$dst)]>;
691 // Intrinsic forms of MOVUPS load and store
692 let canFoldAsLoad = 1 in
693 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
694 "movups\t{$src, $dst|$dst, $src}",
695 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
696 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
697 "movups\t{$src, $dst|$dst, $src}",
698 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
700 let Constraints = "$src1 = $dst" in {
701 let AddedComplexity = 20 in {
702 def MOVLPSrm : PSI<0x12, MRMSrcMem,
703 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
704 "movlps\t{$src2, $dst|$dst, $src2}",
706 (v4f32 (vector_shuffle VR128:$src1,
707 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
708 MOVLP_shuffle_mask)))]>;
709 def MOVHPSrm : PSI<0x16, MRMSrcMem,
710 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
711 "movhps\t{$src2, $dst|$dst, $src2}",
713 (v4f32 (vector_shuffle VR128:$src1,
714 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
715 MOVHP_shuffle_mask)))]>;
717 } // Constraints = "$src1 = $dst"
720 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
721 "movlps\t{$src, $dst|$dst, $src}",
722 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
723 (iPTR 0))), addr:$dst)]>;
725 // v2f64 extract element 1 is always custom lowered to unpack high to low
726 // and extract element 0 so the non-store version isn't too horrible.
727 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
728 "movhps\t{$src, $dst|$dst, $src}",
729 [(store (f64 (vector_extract
730 (v2f64 (vector_shuffle
731 (bc_v2f64 (v4f32 VR128:$src)), (undef),
732 UNPCKH_shuffle_mask)), (iPTR 0))),
735 let Constraints = "$src1 = $dst" in {
736 let AddedComplexity = 20 in {
737 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
738 "movlhps\t{$src2, $dst|$dst, $src2}",
740 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
741 MOVHP_shuffle_mask)))]>;
743 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "movhlps\t{$src2, $dst|$dst, $src2}",
746 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
747 MOVHLPS_shuffle_mask)))]>;
749 } // Constraints = "$src1 = $dst"
751 let AddedComplexity = 20 in
752 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
753 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
760 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
762 /// In addition, we also have a special variant of the scalar form here to
763 /// represent the associated intrinsic operation. This form is unlike the
764 /// plain scalar form, in that it takes an entire vector (instead of a
765 /// scalar) and leaves the top elements undefined.
767 /// And, we have a special variant form for a full-vector intrinsic form.
769 /// These four forms can each have a reg or a mem operand, so there are a
770 /// total of eight "instructions".
772 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
776 bit Commutable = 0> {
777 // Scalar operation, reg.
778 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
779 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
780 [(set FR32:$dst, (OpNode FR32:$src))]> {
781 let isCommutable = Commutable;
784 // Scalar operation, mem.
785 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
786 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
787 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
789 // Vector operation, reg.
790 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
792 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
793 let isCommutable = Commutable;
796 // Vector operation, mem.
797 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
798 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
799 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
801 // Intrinsic operation, reg.
802 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
803 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
804 [(set VR128:$dst, (F32Int VR128:$src))]> {
805 let isCommutable = Commutable;
808 // Intrinsic operation, mem.
809 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
810 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
811 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
813 // Vector intrinsic operation, reg
814 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
815 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
816 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
817 let isCommutable = Commutable;
820 // Vector intrinsic operation, mem
821 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
822 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
823 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
827 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
828 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
830 // Reciprocal approximations. Note that these typically require refinement
831 // in order to obtain suitable precision.
832 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
833 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
834 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
835 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
838 let Constraints = "$src1 = $dst" in {
839 let isCommutable = 1 in {
840 def ANDPSrr : PSI<0x54, MRMSrcReg,
841 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
842 "andps\t{$src2, $dst|$dst, $src2}",
843 [(set VR128:$dst, (v2i64
844 (and VR128:$src1, VR128:$src2)))]>;
845 def ORPSrr : PSI<0x56, MRMSrcReg,
846 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
847 "orps\t{$src2, $dst|$dst, $src2}",
848 [(set VR128:$dst, (v2i64
849 (or VR128:$src1, VR128:$src2)))]>;
850 def XORPSrr : PSI<0x57, MRMSrcReg,
851 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
852 "xorps\t{$src2, $dst|$dst, $src2}",
853 [(set VR128:$dst, (v2i64
854 (xor VR128:$src1, VR128:$src2)))]>;
857 def ANDPSrm : PSI<0x54, MRMSrcMem,
858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
859 "andps\t{$src2, $dst|$dst, $src2}",
860 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
861 (memopv2i64 addr:$src2)))]>;
862 def ORPSrm : PSI<0x56, MRMSrcMem,
863 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
864 "orps\t{$src2, $dst|$dst, $src2}",
865 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
866 (memopv2i64 addr:$src2)))]>;
867 def XORPSrm : PSI<0x57, MRMSrcMem,
868 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
869 "xorps\t{$src2, $dst|$dst, $src2}",
870 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
871 (memopv2i64 addr:$src2)))]>;
872 def ANDNPSrr : PSI<0x55, MRMSrcReg,
873 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
874 "andnps\t{$src2, $dst|$dst, $src2}",
876 (v2i64 (and (xor VR128:$src1,
877 (bc_v2i64 (v4i32 immAllOnesV))),
879 def ANDNPSrm : PSI<0x55, MRMSrcMem,
880 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
881 "andnps\t{$src2, $dst|$dst, $src2}",
883 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
884 (bc_v2i64 (v4i32 immAllOnesV))),
885 (memopv2i64 addr:$src2))))]>;
888 let Constraints = "$src1 = $dst" in {
889 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
890 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
891 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
892 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
893 VR128:$src, imm:$cc))]>;
894 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
895 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
896 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
898 (memop addr:$src), imm:$cc))]>;
900 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
901 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
902 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
903 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
905 // Shuffle and unpack instructions
906 let Constraints = "$src1 = $dst" in {
907 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
908 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
909 (outs VR128:$dst), (ins VR128:$src1,
910 VR128:$src2, i32i8imm:$src3),
911 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
913 (v4f32 (vector_shuffle
914 VR128:$src1, VR128:$src2,
915 SHUFP_shuffle_mask:$src3)))]>;
916 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
917 (outs VR128:$dst), (ins VR128:$src1,
918 f128mem:$src2, i32i8imm:$src3),
919 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
921 (v4f32 (vector_shuffle
922 VR128:$src1, (memopv4f32 addr:$src2),
923 SHUFP_shuffle_mask:$src3)))]>;
925 let AddedComplexity = 10 in {
926 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
927 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
928 "unpckhps\t{$src2, $dst|$dst, $src2}",
930 (v4f32 (vector_shuffle
931 VR128:$src1, VR128:$src2,
932 UNPCKH_shuffle_mask)))]>;
933 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
934 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
935 "unpckhps\t{$src2, $dst|$dst, $src2}",
937 (v4f32 (vector_shuffle
938 VR128:$src1, (memopv4f32 addr:$src2),
939 UNPCKH_shuffle_mask)))]>;
941 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
942 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
943 "unpcklps\t{$src2, $dst|$dst, $src2}",
945 (v4f32 (vector_shuffle
946 VR128:$src1, VR128:$src2,
947 UNPCKL_shuffle_mask)))]>;
948 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
949 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
950 "unpcklps\t{$src2, $dst|$dst, $src2}",
952 (v4f32 (vector_shuffle
953 VR128:$src1, (memopv4f32 addr:$src2),
954 UNPCKL_shuffle_mask)))]>;
956 } // Constraints = "$src1 = $dst"
959 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
960 "movmskps\t{$src, $dst|$dst, $src}",
961 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
962 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
963 "movmskpd\t{$src, $dst|$dst, $src}",
964 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
966 // Prefetch intrinsic.
967 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
968 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
969 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
970 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
971 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
972 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
973 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
974 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
976 // Non-temporal stores
977 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
978 "movntps\t{$src, $dst|$dst, $src}",
979 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
981 // Load, store, and memory fence
982 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
985 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
986 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
987 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
988 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
990 // Alias instructions that map zero vector to pxor / xorp* for sse.
991 // We set canFoldAsLoad because this can be converted to a constant-pool
992 // load of an all-zeros value if folding it would be beneficial.
993 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
994 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
996 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
998 let Predicates = [HasSSE1] in {
999 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1001 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1003 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1006 // FR32 to 128-bit vector conversion.
1007 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1008 "movss\t{$src, $dst|$dst, $src}",
1010 (v4f32 (scalar_to_vector FR32:$src)))]>;
1011 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1012 "movss\t{$src, $dst|$dst, $src}",
1014 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1016 // FIXME: may not be able to eliminate this movss with coalescing the src and
1017 // dest register classes are different. We really want to write this pattern
1019 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1020 // (f32 FR32:$src)>;
1021 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1022 "movss\t{$src, $dst|$dst, $src}",
1023 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1025 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1026 "movss\t{$src, $dst|$dst, $src}",
1027 [(store (f32 (vector_extract (v4f32 VR128:$src),
1028 (iPTR 0))), addr:$dst)]>;
1031 // Move to lower bits of a VR128, leaving upper bits alone.
1032 // Three operand (but two address) aliases.
1033 let Constraints = "$src1 = $dst" in {
1034 let neverHasSideEffects = 1 in
1035 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1036 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1037 "movss\t{$src2, $dst|$dst, $src2}", []>;
1039 let AddedComplexity = 15 in
1040 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1041 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1042 "movss\t{$src2, $dst|$dst, $src2}",
1044 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1045 MOVL_shuffle_mask)))]>;
1048 // Move to lower bits of a VR128 and zeroing upper bits.
1049 // Loading from memory automatically zeroing upper bits.
1050 let AddedComplexity = 20 in
1051 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1052 "movss\t{$src, $dst|$dst, $src}",
1053 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1054 (loadf32 addr:$src))))))]>;
1056 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1057 (MOVZSS2PSrm addr:$src)>;
1059 //===----------------------------------------------------------------------===//
1060 // SSE2 Instructions
1061 //===----------------------------------------------------------------------===//
1063 // Move Instructions
1064 let neverHasSideEffects = 1 in
1065 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1066 "movsd\t{$src, $dst|$dst, $src}", []>;
1067 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1068 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1069 "movsd\t{$src, $dst|$dst, $src}",
1070 [(set FR64:$dst, (loadf64 addr:$src))]>;
1071 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1072 "movsd\t{$src, $dst|$dst, $src}",
1073 [(store FR64:$src, addr:$dst)]>;
1075 // Conversion instructions
1076 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1077 "cvttsd2si\t{$src, $dst|$dst, $src}",
1078 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1079 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1080 "cvttsd2si\t{$src, $dst|$dst, $src}",
1081 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1082 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1083 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1084 [(set FR32:$dst, (fround FR64:$src))]>;
1085 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1086 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1087 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1088 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1089 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1090 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1091 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1092 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1093 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1095 // SSE2 instructions with XS prefix
1096 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1097 "cvtss2sd\t{$src, $dst|$dst, $src}",
1098 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1099 Requires<[HasSSE2]>;
1100 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1101 "cvtss2sd\t{$src, $dst|$dst, $src}",
1102 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1103 Requires<[HasSSE2]>;
1105 // Match intrinsics which expect XMM operand(s).
1106 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1107 "cvtsd2si\t{$src, $dst|$dst, $src}",
1108 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1109 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1110 "cvtsd2si\t{$src, $dst|$dst, $src}",
1111 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1112 (load addr:$src)))]>;
1114 // Match intrinisics which expect MM and XMM operand(s).
1115 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1116 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1117 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1118 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1119 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1120 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1121 (memop addr:$src)))]>;
1122 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1123 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1124 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1125 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1126 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1127 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1128 (memop addr:$src)))]>;
1129 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1130 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1132 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1133 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1134 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1135 (load addr:$src)))]>;
1137 // Aliases for intrinsics
1138 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1139 "cvttsd2si\t{$src, $dst|$dst, $src}",
1141 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1142 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1143 "cvttsd2si\t{$src, $dst|$dst, $src}",
1144 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1145 (load addr:$src)))]>;
1147 // Comparison instructions
1148 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1149 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1150 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1151 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1153 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1154 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1155 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1158 let Defs = [EFLAGS] in {
1159 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1160 "ucomisd\t{$src2, $src1|$src1, $src2}",
1161 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1162 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1163 "ucomisd\t{$src2, $src1|$src1, $src2}",
1164 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1165 (implicit EFLAGS)]>;
1166 } // Defs = [EFLAGS]
1168 // Aliases to match intrinsics which expect XMM operand(s).
1169 let Constraints = "$src1 = $dst" in {
1170 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1171 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1172 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1173 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1174 VR128:$src, imm:$cc))]>;
1175 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1176 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1177 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1178 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1179 (load addr:$src), imm:$cc))]>;
1182 let Defs = [EFLAGS] in {
1183 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1184 "ucomisd\t{$src2, $src1|$src1, $src2}",
1185 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1186 (implicit EFLAGS)]>;
1187 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1188 "ucomisd\t{$src2, $src1|$src1, $src2}",
1189 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1190 (implicit EFLAGS)]>;
1192 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1193 "comisd\t{$src2, $src1|$src1, $src2}",
1194 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1195 (implicit EFLAGS)]>;
1196 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1197 "comisd\t{$src2, $src1|$src1, $src2}",
1198 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1199 (implicit EFLAGS)]>;
1200 } // Defs = [EFLAGS]
1202 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1205 // Alias instructions that map fld0 to pxor for sse.
1206 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1207 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1208 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1209 Requires<[HasSSE2]>, TB, OpSize;
1211 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1213 let neverHasSideEffects = 1 in
1214 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1215 "movapd\t{$src, $dst|$dst, $src}", []>;
1217 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1219 let canFoldAsLoad = 1 in
1220 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1221 "movapd\t{$src, $dst|$dst, $src}",
1222 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1224 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1225 let Constraints = "$src1 = $dst" in {
1226 let isCommutable = 1 in {
1227 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1228 (ins FR64:$src1, FR64:$src2),
1229 "andpd\t{$src2, $dst|$dst, $src2}",
1230 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1231 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1232 (ins FR64:$src1, FR64:$src2),
1233 "orpd\t{$src2, $dst|$dst, $src2}",
1234 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1235 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1236 (ins FR64:$src1, FR64:$src2),
1237 "xorpd\t{$src2, $dst|$dst, $src2}",
1238 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1241 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1242 (ins FR64:$src1, f128mem:$src2),
1243 "andpd\t{$src2, $dst|$dst, $src2}",
1244 [(set FR64:$dst, (X86fand FR64:$src1,
1245 (memopfsf64 addr:$src2)))]>;
1246 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1247 (ins FR64:$src1, f128mem:$src2),
1248 "orpd\t{$src2, $dst|$dst, $src2}",
1249 [(set FR64:$dst, (X86for FR64:$src1,
1250 (memopfsf64 addr:$src2)))]>;
1251 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1252 (ins FR64:$src1, f128mem:$src2),
1253 "xorpd\t{$src2, $dst|$dst, $src2}",
1254 [(set FR64:$dst, (X86fxor FR64:$src1,
1255 (memopfsf64 addr:$src2)))]>;
1257 let neverHasSideEffects = 1 in {
1258 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1259 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1260 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1262 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1263 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1264 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1268 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1270 /// In addition, we also have a special variant of the scalar form here to
1271 /// represent the associated intrinsic operation. This form is unlike the
1272 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1273 /// and leaves the top elements undefined.
1275 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1276 /// six "instructions".
1278 let Constraints = "$src1 = $dst" in {
1279 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1280 SDNode OpNode, Intrinsic F64Int,
1281 bit Commutable = 0> {
1282 // Scalar operation, reg+reg.
1283 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1284 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1285 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1286 let isCommutable = Commutable;
1289 // Scalar operation, reg+mem.
1290 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1291 (ins FR64:$src1, f64mem:$src2),
1292 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1293 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1295 // Vector operation, reg+reg.
1296 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1297 (ins VR128:$src1, VR128:$src2),
1298 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1299 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1300 let isCommutable = Commutable;
1303 // Vector operation, reg+mem.
1304 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1305 (ins VR128:$src1, f128mem:$src2),
1306 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1307 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1309 // Intrinsic operation, reg+reg.
1310 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1311 (ins VR128:$src1, VR128:$src2),
1312 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1313 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1314 let isCommutable = Commutable;
1317 // Intrinsic operation, reg+mem.
1318 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1319 (ins VR128:$src1, sdmem:$src2),
1320 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1321 [(set VR128:$dst, (F64Int VR128:$src1,
1322 sse_load_f64:$src2))]>;
1326 // Arithmetic instructions
1327 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1328 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1329 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1330 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1332 /// sse2_fp_binop_rm - Other SSE2 binops
1334 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1335 /// instructions for a full-vector intrinsic form. Operations that map
1336 /// onto C operators don't use this form since they just use the plain
1337 /// vector form instead of having a separate vector intrinsic form.
1339 /// This provides a total of eight "instructions".
1341 let Constraints = "$src1 = $dst" in {
1342 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1346 bit Commutable = 0> {
1348 // Scalar operation, reg+reg.
1349 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1350 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1351 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1352 let isCommutable = Commutable;
1355 // Scalar operation, reg+mem.
1356 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1357 (ins FR64:$src1, f64mem:$src2),
1358 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1359 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1361 // Vector operation, reg+reg.
1362 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1363 (ins VR128:$src1, VR128:$src2),
1364 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1365 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1366 let isCommutable = Commutable;
1369 // Vector operation, reg+mem.
1370 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1371 (ins VR128:$src1, f128mem:$src2),
1372 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1373 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1375 // Intrinsic operation, reg+reg.
1376 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1377 (ins VR128:$src1, VR128:$src2),
1378 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1379 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1380 let isCommutable = Commutable;
1383 // Intrinsic operation, reg+mem.
1384 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1385 (ins VR128:$src1, sdmem:$src2),
1386 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1387 [(set VR128:$dst, (F64Int VR128:$src1,
1388 sse_load_f64:$src2))]>;
1390 // Vector intrinsic operation, reg+reg.
1391 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1394 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1395 let isCommutable = Commutable;
1398 // Vector intrinsic operation, reg+mem.
1399 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1400 (ins VR128:$src1, f128mem:$src2),
1401 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1402 [(set VR128:$dst, (V2F64Int VR128:$src1,
1403 (memopv2f64 addr:$src2)))]>;
1407 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1408 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1409 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1410 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1412 //===----------------------------------------------------------------------===//
1413 // SSE packed FP Instructions
1415 // Move Instructions
1416 let neverHasSideEffects = 1 in
1417 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1418 "movapd\t{$src, $dst|$dst, $src}", []>;
1419 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1420 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1421 "movapd\t{$src, $dst|$dst, $src}",
1422 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1424 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1425 "movapd\t{$src, $dst|$dst, $src}",
1426 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1428 let neverHasSideEffects = 1 in
1429 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1430 "movupd\t{$src, $dst|$dst, $src}", []>;
1431 let canFoldAsLoad = 1 in
1432 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1433 "movupd\t{$src, $dst|$dst, $src}",
1434 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1435 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1436 "movupd\t{$src, $dst|$dst, $src}",
1437 [(store (v2f64 VR128:$src), addr:$dst)]>;
1439 // Intrinsic forms of MOVUPD load and store
1440 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1441 "movupd\t{$src, $dst|$dst, $src}",
1442 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1443 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1444 "movupd\t{$src, $dst|$dst, $src}",
1445 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1447 let Constraints = "$src1 = $dst" in {
1448 let AddedComplexity = 20 in {
1449 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1450 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1451 "movlpd\t{$src2, $dst|$dst, $src2}",
1453 (v2f64 (vector_shuffle VR128:$src1,
1454 (scalar_to_vector (loadf64 addr:$src2)),
1455 MOVLP_shuffle_mask)))]>;
1456 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1457 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1458 "movhpd\t{$src2, $dst|$dst, $src2}",
1460 (v2f64 (vector_shuffle VR128:$src1,
1461 (scalar_to_vector (loadf64 addr:$src2)),
1462 MOVHP_shuffle_mask)))]>;
1463 } // AddedComplexity
1464 } // Constraints = "$src1 = $dst"
1466 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1467 "movlpd\t{$src, $dst|$dst, $src}",
1468 [(store (f64 (vector_extract (v2f64 VR128:$src),
1469 (iPTR 0))), addr:$dst)]>;
1471 // v2f64 extract element 1 is always custom lowered to unpack high to low
1472 // and extract element 0 so the non-store version isn't too horrible.
1473 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1474 "movhpd\t{$src, $dst|$dst, $src}",
1475 [(store (f64 (vector_extract
1476 (v2f64 (vector_shuffle VR128:$src, (undef),
1477 UNPCKH_shuffle_mask)), (iPTR 0))),
1480 // SSE2 instructions without OpSize prefix
1481 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1482 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1483 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1484 TB, Requires<[HasSSE2]>;
1485 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1486 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1487 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1488 (bitconvert (memopv2i64 addr:$src))))]>,
1489 TB, Requires<[HasSSE2]>;
1491 // SSE2 instructions with XS prefix
1492 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1493 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1494 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1495 XS, Requires<[HasSSE2]>;
1496 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1497 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1498 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1499 (bitconvert (memopv2i64 addr:$src))))]>,
1500 XS, Requires<[HasSSE2]>;
1502 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1503 "cvtps2dq\t{$src, $dst|$dst, $src}",
1504 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1505 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1506 "cvtps2dq\t{$src, $dst|$dst, $src}",
1507 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1508 (memop addr:$src)))]>;
1509 // SSE2 packed instructions with XS prefix
1510 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1511 "cvttps2dq\t{$src, $dst|$dst, $src}",
1512 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1513 XS, Requires<[HasSSE2]>;
1514 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1515 "cvttps2dq\t{$src, $dst|$dst, $src}",
1516 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1517 (memop addr:$src)))]>,
1518 XS, Requires<[HasSSE2]>;
1520 // SSE2 packed instructions with XD prefix
1521 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1522 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1523 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1524 XD, Requires<[HasSSE2]>;
1525 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1526 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1527 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1528 (memop addr:$src)))]>,
1529 XD, Requires<[HasSSE2]>;
1531 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1532 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1533 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1534 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1535 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1536 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1537 (memop addr:$src)))]>;
1539 // SSE2 instructions without OpSize prefix
1540 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1541 "cvtps2pd\t{$src, $dst|$dst, $src}",
1542 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1543 TB, Requires<[HasSSE2]>;
1544 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1545 "cvtps2pd\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1547 (load addr:$src)))]>,
1548 TB, Requires<[HasSSE2]>;
1550 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1551 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1552 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1553 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1554 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1555 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1556 (memop addr:$src)))]>;
1558 // Match intrinsics which expect XMM operand(s).
1559 // Aliases for intrinsics
1560 let Constraints = "$src1 = $dst" in {
1561 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1562 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1563 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1566 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1567 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1568 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1570 (loadi32 addr:$src2)))]>;
1571 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1572 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1573 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1576 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1577 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1578 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1580 (load addr:$src2)))]>;
1581 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1582 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1583 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1584 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1585 VR128:$src2))]>, XS,
1586 Requires<[HasSSE2]>;
1587 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1588 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1589 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1590 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1591 (load addr:$src2)))]>, XS,
1592 Requires<[HasSSE2]>;
1597 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1599 /// In addition, we also have a special variant of the scalar form here to
1600 /// represent the associated intrinsic operation. This form is unlike the
1601 /// plain scalar form, in that it takes an entire vector (instead of a
1602 /// scalar) and leaves the top elements undefined.
1604 /// And, we have a special variant form for a full-vector intrinsic form.
1606 /// These four forms can each have a reg or a mem operand, so there are a
1607 /// total of eight "instructions".
1609 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1613 bit Commutable = 0> {
1614 // Scalar operation, reg.
1615 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1616 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1617 [(set FR64:$dst, (OpNode FR64:$src))]> {
1618 let isCommutable = Commutable;
1621 // Scalar operation, mem.
1622 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1623 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1624 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1626 // Vector operation, reg.
1627 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1628 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1629 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1630 let isCommutable = Commutable;
1633 // Vector operation, mem.
1634 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1636 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1638 // Intrinsic operation, reg.
1639 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1640 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1641 [(set VR128:$dst, (F64Int VR128:$src))]> {
1642 let isCommutable = Commutable;
1645 // Intrinsic operation, mem.
1646 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1647 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1648 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1650 // Vector intrinsic operation, reg
1651 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1652 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1653 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1654 let isCommutable = Commutable;
1657 // Vector intrinsic operation, mem
1658 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1659 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1660 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1664 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1665 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1667 // There is no f64 version of the reciprocal approximation instructions.
1670 let Constraints = "$src1 = $dst" in {
1671 let isCommutable = 1 in {
1672 def ANDPDrr : PDI<0x54, MRMSrcReg,
1673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1674 "andpd\t{$src2, $dst|$dst, $src2}",
1676 (and (bc_v2i64 (v2f64 VR128:$src1)),
1677 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1678 def ORPDrr : PDI<0x56, MRMSrcReg,
1679 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1680 "orpd\t{$src2, $dst|$dst, $src2}",
1682 (or (bc_v2i64 (v2f64 VR128:$src1)),
1683 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1684 def XORPDrr : PDI<0x57, MRMSrcReg,
1685 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1686 "xorpd\t{$src2, $dst|$dst, $src2}",
1688 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1689 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1692 def ANDPDrm : PDI<0x54, MRMSrcMem,
1693 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1694 "andpd\t{$src2, $dst|$dst, $src2}",
1696 (and (bc_v2i64 (v2f64 VR128:$src1)),
1697 (memopv2i64 addr:$src2)))]>;
1698 def ORPDrm : PDI<0x56, MRMSrcMem,
1699 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1700 "orpd\t{$src2, $dst|$dst, $src2}",
1702 (or (bc_v2i64 (v2f64 VR128:$src1)),
1703 (memopv2i64 addr:$src2)))]>;
1704 def XORPDrm : PDI<0x57, MRMSrcMem,
1705 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1706 "xorpd\t{$src2, $dst|$dst, $src2}",
1708 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1709 (memopv2i64 addr:$src2)))]>;
1710 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1711 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1712 "andnpd\t{$src2, $dst|$dst, $src2}",
1714 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1715 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1716 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1717 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1718 "andnpd\t{$src2, $dst|$dst, $src2}",
1720 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1721 (memopv2i64 addr:$src2)))]>;
1724 let Constraints = "$src1 = $dst" in {
1725 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1726 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1727 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1729 VR128:$src, imm:$cc))]>;
1730 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1731 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1732 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1733 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1734 (memop addr:$src), imm:$cc))]>;
1736 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1737 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1738 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1739 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1741 // Shuffle and unpack instructions
1742 let Constraints = "$src1 = $dst" in {
1743 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1744 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1745 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 [(set VR128:$dst, (v2f64 (vector_shuffle
1747 VR128:$src1, VR128:$src2,
1748 SHUFP_shuffle_mask:$src3)))]>;
1749 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1750 (outs VR128:$dst), (ins VR128:$src1,
1751 f128mem:$src2, i8imm:$src3),
1752 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1754 (v2f64 (vector_shuffle
1755 VR128:$src1, (memopv2f64 addr:$src2),
1756 SHUFP_shuffle_mask:$src3)))]>;
1758 let AddedComplexity = 10 in {
1759 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1760 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1761 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1763 (v2f64 (vector_shuffle
1764 VR128:$src1, VR128:$src2,
1765 UNPCKH_shuffle_mask)))]>;
1766 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1767 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1768 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1770 (v2f64 (vector_shuffle
1771 VR128:$src1, (memopv2f64 addr:$src2),
1772 UNPCKH_shuffle_mask)))]>;
1774 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1775 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1776 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1778 (v2f64 (vector_shuffle
1779 VR128:$src1, VR128:$src2,
1780 UNPCKL_shuffle_mask)))]>;
1781 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1782 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1783 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1785 (v2f64 (vector_shuffle
1786 VR128:$src1, (memopv2f64 addr:$src2),
1787 UNPCKL_shuffle_mask)))]>;
1788 } // AddedComplexity
1789 } // Constraints = "$src1 = $dst"
1792 //===----------------------------------------------------------------------===//
1793 // SSE integer instructions
1795 // Move Instructions
1796 let neverHasSideEffects = 1 in
1797 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1798 "movdqa\t{$src, $dst|$dst, $src}", []>;
1799 let canFoldAsLoad = 1, mayLoad = 1 in
1800 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1801 "movdqa\t{$src, $dst|$dst, $src}",
1802 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1804 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1805 "movdqa\t{$src, $dst|$dst, $src}",
1806 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1807 let canFoldAsLoad = 1, mayLoad = 1 in
1808 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1809 "movdqu\t{$src, $dst|$dst, $src}",
1810 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1811 XS, Requires<[HasSSE2]>;
1813 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1814 "movdqu\t{$src, $dst|$dst, $src}",
1815 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1816 XS, Requires<[HasSSE2]>;
1818 // Intrinsic forms of MOVDQU load and store
1819 let canFoldAsLoad = 1 in
1820 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1821 "movdqu\t{$src, $dst|$dst, $src}",
1822 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1823 XS, Requires<[HasSSE2]>;
1824 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1825 "movdqu\t{$src, $dst|$dst, $src}",
1826 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1827 XS, Requires<[HasSSE2]>;
1829 let Constraints = "$src1 = $dst" in {
1831 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1832 bit Commutable = 0> {
1833 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1835 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1836 let isCommutable = Commutable;
1838 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1839 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1840 [(set VR128:$dst, (IntId VR128:$src1,
1841 (bitconvert (memopv2i64 addr:$src2))))]>;
1844 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1846 Intrinsic IntId, Intrinsic IntId2> {
1847 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1849 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1850 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1851 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1852 [(set VR128:$dst, (IntId VR128:$src1,
1853 (bitconvert (memopv2i64 addr:$src2))))]>;
1854 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1856 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1859 /// PDI_binop_rm - Simple SSE2 binary operator.
1860 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1861 ValueType OpVT, bit Commutable = 0> {
1862 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1864 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1865 let isCommutable = Commutable;
1867 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1868 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1869 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1870 (bitconvert (memopv2i64 addr:$src2)))))]>;
1873 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1875 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1876 /// to collapse (bitconvert VT to VT) into its operand.
1878 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1879 bit Commutable = 0> {
1880 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1882 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1883 let isCommutable = Commutable;
1885 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1886 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1887 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1890 } // Constraints = "$src1 = $dst"
1892 // 128-bit Integer Arithmetic
1894 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1895 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1896 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1897 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1899 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1900 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1901 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1902 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1904 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1905 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1906 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1907 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1909 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1910 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1911 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1912 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1914 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1916 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1917 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1918 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1920 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1922 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1923 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1926 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1927 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1928 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1929 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1930 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1933 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1934 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1935 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1936 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1937 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1938 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1940 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1941 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1942 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1943 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1944 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1945 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1947 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1948 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1949 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1950 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1952 // 128-bit logical shifts.
1953 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1954 def PSLLDQri : PDIi8<0x73, MRM7r,
1955 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1956 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1957 def PSRLDQri : PDIi8<0x73, MRM3r,
1958 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1959 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1960 // PSRADQri doesn't exist in SSE[1-3].
1963 let Predicates = [HasSSE2] in {
1964 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1965 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1966 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1967 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1968 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1969 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1970 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1971 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1972 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1973 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1975 // Shift up / down and insert zero's.
1976 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1977 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1978 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1979 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1983 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1984 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1985 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1987 let Constraints = "$src1 = $dst" in {
1988 def PANDNrr : PDI<0xDF, MRMSrcReg,
1989 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1990 "pandn\t{$src2, $dst|$dst, $src2}",
1991 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1994 def PANDNrm : PDI<0xDF, MRMSrcMem,
1995 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1996 "pandn\t{$src2, $dst|$dst, $src2}",
1997 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1998 (memopv2i64 addr:$src2))))]>;
2001 // SSE2 Integer comparison
2002 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2003 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2004 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2005 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2006 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2007 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2009 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2010 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2011 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2012 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2013 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2014 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2015 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2016 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2017 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2018 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2019 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2020 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2022 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2023 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2024 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2025 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2026 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2027 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2028 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2029 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2030 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2031 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2032 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2033 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2036 // Pack instructions
2037 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2038 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2039 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2041 // Shuffle and unpack instructions
2042 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2043 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2044 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2045 [(set VR128:$dst, (v4i32 (vector_shuffle
2046 VR128:$src1, (undef),
2047 PSHUFD_shuffle_mask:$src2)))]>;
2048 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2049 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2050 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2051 [(set VR128:$dst, (v4i32 (vector_shuffle
2052 (bc_v4i32(memopv2i64 addr:$src1)),
2054 PSHUFD_shuffle_mask:$src2)))]>;
2056 // SSE2 with ImmT == Imm8 and XS prefix.
2057 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2058 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2059 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2060 [(set VR128:$dst, (v8i16 (vector_shuffle
2061 VR128:$src1, (undef),
2062 PSHUFHW_shuffle_mask:$src2)))]>,
2063 XS, Requires<[HasSSE2]>;
2064 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2065 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2066 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set VR128:$dst, (v8i16 (vector_shuffle
2068 (bc_v8i16 (memopv2i64 addr:$src1)),
2070 PSHUFHW_shuffle_mask:$src2)))]>,
2071 XS, Requires<[HasSSE2]>;
2073 // SSE2 with ImmT == Imm8 and XD prefix.
2074 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2075 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2076 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2077 [(set VR128:$dst, (v8i16 (vector_shuffle
2078 VR128:$src1, (undef),
2079 PSHUFLW_shuffle_mask:$src2)))]>,
2080 XD, Requires<[HasSSE2]>;
2081 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2082 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2083 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2084 [(set VR128:$dst, (v8i16 (vector_shuffle
2085 (bc_v8i16 (memopv2i64 addr:$src1)),
2087 PSHUFLW_shuffle_mask:$src2)))]>,
2088 XD, Requires<[HasSSE2]>;
2091 let Constraints = "$src1 = $dst" in {
2092 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2093 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2094 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2096 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2097 UNPCKL_shuffle_mask)))]>;
2098 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2099 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2100 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2102 (v16i8 (vector_shuffle VR128:$src1,
2103 (bc_v16i8 (memopv2i64 addr:$src2)),
2104 UNPCKL_shuffle_mask)))]>;
2105 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2106 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2107 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2109 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2110 UNPCKL_shuffle_mask)))]>;
2111 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2112 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2113 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2115 (v8i16 (vector_shuffle VR128:$src1,
2116 (bc_v8i16 (memopv2i64 addr:$src2)),
2117 UNPCKL_shuffle_mask)))]>;
2118 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2119 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2120 "punpckldq\t{$src2, $dst|$dst, $src2}",
2122 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2123 UNPCKL_shuffle_mask)))]>;
2124 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2125 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2126 "punpckldq\t{$src2, $dst|$dst, $src2}",
2128 (v4i32 (vector_shuffle VR128:$src1,
2129 (bc_v4i32 (memopv2i64 addr:$src2)),
2130 UNPCKL_shuffle_mask)))]>;
2131 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2132 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2133 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2135 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2136 UNPCKL_shuffle_mask)))]>;
2137 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2138 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2139 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2141 (v2i64 (vector_shuffle VR128:$src1,
2142 (memopv2i64 addr:$src2),
2143 UNPCKL_shuffle_mask)))]>;
2145 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2146 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2147 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2149 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2150 UNPCKH_shuffle_mask)))]>;
2151 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2152 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2153 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2155 (v16i8 (vector_shuffle VR128:$src1,
2156 (bc_v16i8 (memopv2i64 addr:$src2)),
2157 UNPCKH_shuffle_mask)))]>;
2158 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2159 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2160 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2162 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2163 UNPCKH_shuffle_mask)))]>;
2164 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2165 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2166 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2168 (v8i16 (vector_shuffle VR128:$src1,
2169 (bc_v8i16 (memopv2i64 addr:$src2)),
2170 UNPCKH_shuffle_mask)))]>;
2171 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2173 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2175 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2176 UNPCKH_shuffle_mask)))]>;
2177 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2178 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2179 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2181 (v4i32 (vector_shuffle VR128:$src1,
2182 (bc_v4i32 (memopv2i64 addr:$src2)),
2183 UNPCKH_shuffle_mask)))]>;
2184 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2185 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2186 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2188 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2189 UNPCKH_shuffle_mask)))]>;
2190 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2191 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2192 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2194 (v2i64 (vector_shuffle VR128:$src1,
2195 (memopv2i64 addr:$src2),
2196 UNPCKH_shuffle_mask)))]>;
2200 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2201 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2202 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2203 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2205 let Constraints = "$src1 = $dst" in {
2206 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2207 (outs VR128:$dst), (ins VR128:$src1,
2208 GR32:$src2, i32i8imm:$src3),
2209 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2211 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2212 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2213 (outs VR128:$dst), (ins VR128:$src1,
2214 i16mem:$src2, i32i8imm:$src3),
2215 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2217 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2222 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2223 "pmovmskb\t{$src, $dst|$dst, $src}",
2224 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2226 // Conditional store
2228 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2229 "maskmovdqu\t{$mask, $src|$src, $mask}",
2230 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2232 // Non-temporal stores
2233 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2234 "movntpd\t{$src, $dst|$dst, $src}",
2235 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2236 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2237 "movntdq\t{$src, $dst|$dst, $src}",
2238 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2239 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2240 "movnti\t{$src, $dst|$dst, $src}",
2241 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2242 TB, Requires<[HasSSE2]>;
2245 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2246 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2247 TB, Requires<[HasSSE2]>;
2249 // Load, store, and memory fence
2250 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2251 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2252 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2253 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2255 //TODO: custom lower this so as to never even generate the noop
2256 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2258 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2259 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2260 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2263 // Alias instructions that map zero vector to pxor / xorp* for sse.
2264 // We set canFoldAsLoad because this can be converted to a constant-pool
2265 // load of an all-ones value if folding it would be beneficial.
2266 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2267 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2268 "pcmpeqd\t$dst, $dst",
2269 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2271 // FR64 to 128-bit vector conversion.
2272 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2273 "movsd\t{$src, $dst|$dst, $src}",
2275 (v2f64 (scalar_to_vector FR64:$src)))]>;
2276 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2277 "movsd\t{$src, $dst|$dst, $src}",
2279 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2281 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2282 "movd\t{$src, $dst|$dst, $src}",
2284 (v4i32 (scalar_to_vector GR32:$src)))]>;
2285 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2286 "movd\t{$src, $dst|$dst, $src}",
2288 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2290 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2291 "movd\t{$src, $dst|$dst, $src}",
2292 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2294 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2295 "movd\t{$src, $dst|$dst, $src}",
2296 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2298 // SSE2 instructions with XS prefix
2299 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2300 "movq\t{$src, $dst|$dst, $src}",
2302 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2303 Requires<[HasSSE2]>;
2304 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2305 "movq\t{$src, $dst|$dst, $src}",
2306 [(store (i64 (vector_extract (v2i64 VR128:$src),
2307 (iPTR 0))), addr:$dst)]>;
2309 // FIXME: may not be able to eliminate this movss with coalescing the src and
2310 // dest register classes are different. We really want to write this pattern
2312 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2313 // (f32 FR32:$src)>;
2314 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2315 "movsd\t{$src, $dst|$dst, $src}",
2316 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2318 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2319 "movsd\t{$src, $dst|$dst, $src}",
2320 [(store (f64 (vector_extract (v2f64 VR128:$src),
2321 (iPTR 0))), addr:$dst)]>;
2322 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2323 "movd\t{$src, $dst|$dst, $src}",
2324 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2326 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2327 "movd\t{$src, $dst|$dst, $src}",
2328 [(store (i32 (vector_extract (v4i32 VR128:$src),
2329 (iPTR 0))), addr:$dst)]>;
2331 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2332 "movd\t{$src, $dst|$dst, $src}",
2333 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2334 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2335 "movd\t{$src, $dst|$dst, $src}",
2336 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2339 // Move to lower bits of a VR128, leaving upper bits alone.
2340 // Three operand (but two address) aliases.
2341 let Constraints = "$src1 = $dst" in {
2342 let neverHasSideEffects = 1 in
2343 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2344 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2345 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2347 let AddedComplexity = 15 in
2348 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2349 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2350 "movsd\t{$src2, $dst|$dst, $src2}",
2352 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2353 MOVL_shuffle_mask)))]>;
2356 // Store / copy lower 64-bits of a XMM register.
2357 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2358 "movq\t{$src, $dst|$dst, $src}",
2359 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2361 // Move to lower bits of a VR128 and zeroing upper bits.
2362 // Loading from memory automatically zeroing upper bits.
2363 let AddedComplexity = 20 in {
2364 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2365 "movsd\t{$src, $dst|$dst, $src}",
2367 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2368 (loadf64 addr:$src))))))]>;
2370 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2371 (MOVZSD2PDrm addr:$src)>;
2372 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2373 (MOVZSD2PDrm addr:$src)>;
2374 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2377 // movd / movq to XMM register zero-extends
2378 let AddedComplexity = 15 in {
2379 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2380 "movd\t{$src, $dst|$dst, $src}",
2381 [(set VR128:$dst, (v4i32 (X86vzmovl
2382 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2383 // This is X86-64 only.
2384 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2385 "mov{d|q}\t{$src, $dst|$dst, $src}",
2386 [(set VR128:$dst, (v2i64 (X86vzmovl
2387 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2390 let AddedComplexity = 20 in {
2391 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2392 "movd\t{$src, $dst|$dst, $src}",
2394 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2395 (loadi32 addr:$src))))))]>;
2397 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2398 (MOVZDI2PDIrm addr:$src)>;
2399 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2400 (MOVZDI2PDIrm addr:$src)>;
2401 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2402 (MOVZDI2PDIrm addr:$src)>;
2404 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2405 "movq\t{$src, $dst|$dst, $src}",
2407 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2408 (loadi64 addr:$src))))))]>, XS,
2409 Requires<[HasSSE2]>;
2411 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2412 (MOVZQI2PQIrm addr:$src)>;
2413 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2414 (MOVZQI2PQIrm addr:$src)>;
2415 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2418 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2419 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2420 let AddedComplexity = 15 in
2421 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2422 "movq\t{$src, $dst|$dst, $src}",
2423 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2424 XS, Requires<[HasSSE2]>;
2426 let AddedComplexity = 20 in {
2427 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2428 "movq\t{$src, $dst|$dst, $src}",
2429 [(set VR128:$dst, (v2i64 (X86vzmovl
2430 (loadv2i64 addr:$src))))]>,
2431 XS, Requires<[HasSSE2]>;
2433 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2434 (MOVZPQILo2PQIrm addr:$src)>;
2437 //===----------------------------------------------------------------------===//
2438 // SSE3 Instructions
2439 //===----------------------------------------------------------------------===//
2441 // Move Instructions
2442 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2443 "movshdup\t{$src, $dst|$dst, $src}",
2444 [(set VR128:$dst, (v4f32 (vector_shuffle
2445 VR128:$src, (undef),
2446 MOVSHDUP_shuffle_mask)))]>;
2447 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2448 "movshdup\t{$src, $dst|$dst, $src}",
2449 [(set VR128:$dst, (v4f32 (vector_shuffle
2450 (memopv4f32 addr:$src), (undef),
2451 MOVSHDUP_shuffle_mask)))]>;
2453 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2454 "movsldup\t{$src, $dst|$dst, $src}",
2455 [(set VR128:$dst, (v4f32 (vector_shuffle
2456 VR128:$src, (undef),
2457 MOVSLDUP_shuffle_mask)))]>;
2458 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2459 "movsldup\t{$src, $dst|$dst, $src}",
2460 [(set VR128:$dst, (v4f32 (vector_shuffle
2461 (memopv4f32 addr:$src), (undef),
2462 MOVSLDUP_shuffle_mask)))]>;
2464 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2465 "movddup\t{$src, $dst|$dst, $src}",
2467 (v2f64 (vector_shuffle VR128:$src, (undef),
2468 MOVDDUP_shuffle_mask)))]>;
2469 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2470 "movddup\t{$src, $dst|$dst, $src}",
2472 (v2f64 (vector_shuffle
2473 (scalar_to_vector (loadf64 addr:$src)),
2474 (undef), MOVDDUP_shuffle_mask)))]>;
2476 def : Pat<(vector_shuffle
2477 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2478 (undef), MOVDDUP_shuffle_mask),
2479 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2480 def : Pat<(vector_shuffle
2481 (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
2482 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2486 let Constraints = "$src1 = $dst" in {
2487 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2488 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2489 "addsubps\t{$src2, $dst|$dst, $src2}",
2490 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2492 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2493 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2494 "addsubps\t{$src2, $dst|$dst, $src2}",
2495 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2496 (memop addr:$src2)))]>;
2497 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2498 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2499 "addsubpd\t{$src2, $dst|$dst, $src2}",
2500 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2502 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2503 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2504 "addsubpd\t{$src2, $dst|$dst, $src2}",
2505 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2506 (memop addr:$src2)))]>;
2509 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2510 "lddqu\t{$src, $dst|$dst, $src}",
2511 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2514 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2515 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2516 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2517 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2518 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2519 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2520 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2521 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2522 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2523 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2524 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2525 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2526 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2527 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2528 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2529 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2531 let Constraints = "$src1 = $dst" in {
2532 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2533 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2534 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2535 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2536 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2537 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2538 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2539 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2542 // Thread synchronization
2543 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2544 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2545 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2546 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2548 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2549 let AddedComplexity = 15 in
2550 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2551 MOVSHDUP_shuffle_mask)),
2552 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2553 let AddedComplexity = 20 in
2554 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2555 MOVSHDUP_shuffle_mask)),
2556 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2558 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2559 let AddedComplexity = 15 in
2560 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2561 MOVSLDUP_shuffle_mask)),
2562 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2563 let AddedComplexity = 20 in
2564 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2565 MOVSLDUP_shuffle_mask)),
2566 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2568 //===----------------------------------------------------------------------===//
2569 // SSSE3 Instructions
2570 //===----------------------------------------------------------------------===//
2572 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2573 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2574 Intrinsic IntId64, Intrinsic IntId128> {
2575 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2576 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2577 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2579 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2582 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2584 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2587 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2590 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2595 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2598 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2599 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2600 Intrinsic IntId64, Intrinsic IntId128> {
2601 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2603 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2604 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2606 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2608 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2611 (bitconvert (memopv4i16 addr:$src))))]>;
2613 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2616 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2619 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2621 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2624 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2627 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2628 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2629 Intrinsic IntId64, Intrinsic IntId128> {
2630 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2633 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2635 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2637 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2640 (bitconvert (memopv2i32 addr:$src))))]>;
2642 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2645 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2648 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2653 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2656 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2657 int_x86_ssse3_pabs_b,
2658 int_x86_ssse3_pabs_b_128>;
2659 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2660 int_x86_ssse3_pabs_w,
2661 int_x86_ssse3_pabs_w_128>;
2662 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2663 int_x86_ssse3_pabs_d,
2664 int_x86_ssse3_pabs_d_128>;
2666 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2667 let Constraints = "$src1 = $dst" in {
2668 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2669 Intrinsic IntId64, Intrinsic IntId128,
2670 bit Commutable = 0> {
2671 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2672 (ins VR64:$src1, VR64:$src2),
2673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2674 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2675 let isCommutable = Commutable;
2677 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2678 (ins VR64:$src1, i64mem:$src2),
2679 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2681 (IntId64 VR64:$src1,
2682 (bitconvert (memopv8i8 addr:$src2))))]>;
2684 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2685 (ins VR128:$src1, VR128:$src2),
2686 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2687 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2689 let isCommutable = Commutable;
2691 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2692 (ins VR128:$src1, i128mem:$src2),
2693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2695 (IntId128 VR128:$src1,
2696 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2700 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2701 let Constraints = "$src1 = $dst" in {
2702 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2703 Intrinsic IntId64, Intrinsic IntId128,
2704 bit Commutable = 0> {
2705 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2706 (ins VR64:$src1, VR64:$src2),
2707 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2708 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2709 let isCommutable = Commutable;
2711 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2712 (ins VR64:$src1, i64mem:$src2),
2713 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 (IntId64 VR64:$src1,
2716 (bitconvert (memopv4i16 addr:$src2))))]>;
2718 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2719 (ins VR128:$src1, VR128:$src2),
2720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2721 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2723 let isCommutable = Commutable;
2725 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2726 (ins VR128:$src1, i128mem:$src2),
2727 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2729 (IntId128 VR128:$src1,
2730 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2734 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2735 let Constraints = "$src1 = $dst" in {
2736 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2737 Intrinsic IntId64, Intrinsic IntId128,
2738 bit Commutable = 0> {
2739 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2740 (ins VR64:$src1, VR64:$src2),
2741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2742 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2743 let isCommutable = Commutable;
2745 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2746 (ins VR64:$src1, i64mem:$src2),
2747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2749 (IntId64 VR64:$src1,
2750 (bitconvert (memopv2i32 addr:$src2))))]>;
2752 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2753 (ins VR128:$src1, VR128:$src2),
2754 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2755 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2757 let isCommutable = Commutable;
2759 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2760 (ins VR128:$src1, i128mem:$src2),
2761 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2763 (IntId128 VR128:$src1,
2764 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2768 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2769 int_x86_ssse3_phadd_w,
2770 int_x86_ssse3_phadd_w_128>;
2771 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2772 int_x86_ssse3_phadd_d,
2773 int_x86_ssse3_phadd_d_128>;
2774 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2775 int_x86_ssse3_phadd_sw,
2776 int_x86_ssse3_phadd_sw_128>;
2777 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2778 int_x86_ssse3_phsub_w,
2779 int_x86_ssse3_phsub_w_128>;
2780 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2781 int_x86_ssse3_phsub_d,
2782 int_x86_ssse3_phsub_d_128>;
2783 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2784 int_x86_ssse3_phsub_sw,
2785 int_x86_ssse3_phsub_sw_128>;
2786 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2787 int_x86_ssse3_pmadd_ub_sw,
2788 int_x86_ssse3_pmadd_ub_sw_128>;
2789 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2790 int_x86_ssse3_pmul_hr_sw,
2791 int_x86_ssse3_pmul_hr_sw_128, 1>;
2792 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2793 int_x86_ssse3_pshuf_b,
2794 int_x86_ssse3_pshuf_b_128>;
2795 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2796 int_x86_ssse3_psign_b,
2797 int_x86_ssse3_psign_b_128>;
2798 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2799 int_x86_ssse3_psign_w,
2800 int_x86_ssse3_psign_w_128>;
2801 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2802 int_x86_ssse3_psign_d,
2803 int_x86_ssse3_psign_d_128>;
2805 let Constraints = "$src1 = $dst" in {
2806 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2807 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2808 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2810 (int_x86_ssse3_palign_r
2811 VR64:$src1, VR64:$src2,
2813 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2814 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2815 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2817 (int_x86_ssse3_palign_r
2819 (bitconvert (memopv2i32 addr:$src2)),
2822 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2823 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2824 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2826 (int_x86_ssse3_palign_r_128
2827 VR128:$src1, VR128:$src2,
2828 imm:$src3))]>, OpSize;
2829 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2830 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2831 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2833 (int_x86_ssse3_palign_r_128
2835 (bitconvert (memopv4i32 addr:$src2)),
2836 imm:$src3))]>, OpSize;
2839 //===----------------------------------------------------------------------===//
2840 // Non-Instruction Patterns
2841 //===----------------------------------------------------------------------===//
2843 // extload f32 -> f64. This matches load+fextend because we have a hack in
2844 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2845 // Since these loads aren't folded into the fextend, we have to match it
2847 let Predicates = [HasSSE2] in
2848 def : Pat<(fextend (loadf32 addr:$src)),
2849 (CVTSS2SDrm addr:$src)>;
2852 let Predicates = [HasSSE2] in {
2853 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2854 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2855 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2856 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2857 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2858 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2859 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2860 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2861 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2862 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2863 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2864 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2865 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2866 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2867 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2868 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2869 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2870 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2871 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2872 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2873 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2874 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2875 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2876 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2877 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2878 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2879 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2880 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2881 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2882 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2885 // Move scalar to XMM zero-extended
2886 // movd to XMM register zero-extends
2887 let AddedComplexity = 15 in {
2888 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2889 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2890 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2891 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2892 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2893 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2894 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2895 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2896 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2899 // Splat v2f64 / v2i64
2900 let AddedComplexity = 10 in {
2901 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2902 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2903 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2904 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2905 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2906 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2907 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2908 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2911 // Special unary SHUFPSrri case.
2912 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2913 SHUFP_unary_shuffle_mask:$sm)),
2914 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2915 Requires<[HasSSE1]>;
2916 // Special unary SHUFPDrri case.
2917 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2918 SHUFP_unary_shuffle_mask:$sm)),
2919 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2920 Requires<[HasSSE2]>;
2921 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2922 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2923 SHUFP_unary_shuffle_mask:$sm),
2924 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2925 Requires<[HasSSE2]>;
2927 // Special binary v4i32 shuffle cases with SHUFPS.
2928 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2929 PSHUFD_binary_shuffle_mask:$sm)),
2930 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2931 Requires<[HasSSE2]>;
2932 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2933 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2934 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2935 Requires<[HasSSE2]>;
2936 // Special binary v2i64 shuffle cases using SHUFPDrri.
2937 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2938 SHUFP_shuffle_mask:$sm)),
2939 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2940 Requires<[HasSSE2]>;
2941 // Special unary SHUFPDrri case.
2942 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2943 SHUFP_unary_shuffle_mask:$sm)),
2944 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2945 Requires<[HasSSE2]>;
2947 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2948 let AddedComplexity = 15 in {
2949 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2950 UNPCKL_v_undef_shuffle_mask:$sm)),
2951 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2952 Requires<[OptForSpeed, HasSSE2]>;
2953 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2954 UNPCKL_v_undef_shuffle_mask:$sm)),
2955 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2956 Requires<[OptForSpeed, HasSSE2]>;
2958 let AddedComplexity = 10 in {
2959 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2960 UNPCKL_v_undef_shuffle_mask)),
2961 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2962 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2963 UNPCKL_v_undef_shuffle_mask)),
2964 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2965 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2966 UNPCKL_v_undef_shuffle_mask)),
2967 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2968 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2969 UNPCKL_v_undef_shuffle_mask)),
2970 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2973 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2974 let AddedComplexity = 15 in {
2975 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2976 UNPCKH_v_undef_shuffle_mask:$sm)),
2977 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2978 Requires<[OptForSpeed, HasSSE2]>;
2979 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2980 UNPCKH_v_undef_shuffle_mask:$sm)),
2981 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2982 Requires<[OptForSpeed, HasSSE2]>;
2984 let AddedComplexity = 10 in {
2985 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2986 UNPCKH_v_undef_shuffle_mask)),
2987 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2988 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2989 UNPCKH_v_undef_shuffle_mask)),
2990 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2991 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2992 UNPCKH_v_undef_shuffle_mask)),
2993 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2994 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2995 UNPCKH_v_undef_shuffle_mask)),
2996 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2999 let AddedComplexity = 20 in {
3000 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3001 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3002 MOVHP_shuffle_mask)),
3003 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3005 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3006 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3007 MOVHLPS_shuffle_mask)),
3008 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3010 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3011 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
3012 MOVHLPS_v_undef_shuffle_mask)),
3013 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3014 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
3015 MOVHLPS_v_undef_shuffle_mask)),
3016 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3019 let AddedComplexity = 20 in {
3020 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3021 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
3022 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
3023 MOVLP_shuffle_mask)),
3024 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3025 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
3026 MOVLP_shuffle_mask)),
3027 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3028 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
3029 MOVHP_shuffle_mask)),
3030 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3031 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
3032 MOVHP_shuffle_mask)),
3033 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3035 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
3036 MOVLP_shuffle_mask)),
3037 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3038 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
3039 MOVLP_shuffle_mask)),
3040 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3041 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
3042 MOVHP_shuffle_mask)),
3043 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3044 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
3045 MOVHP_shuffle_mask)),
3046 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3049 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3050 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3051 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
3052 MOVLP_shuffle_mask)), addr:$src1),
3053 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3054 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
3055 MOVLP_shuffle_mask)), addr:$src1),
3056 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3057 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
3058 MOVHP_shuffle_mask)), addr:$src1),
3059 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3060 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
3061 MOVHP_shuffle_mask)), addr:$src1),
3062 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3064 def : Pat<(store (v4i32 (vector_shuffle
3065 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
3066 MOVLP_shuffle_mask)), addr:$src1),
3067 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3068 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
3069 MOVLP_shuffle_mask)), addr:$src1),
3070 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3071 def : Pat<(store (v4i32 (vector_shuffle
3072 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
3073 MOVHP_shuffle_mask)), addr:$src1),
3074 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3075 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
3076 MOVHP_shuffle_mask)), addr:$src1),
3077 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3080 let AddedComplexity = 15 in {
3081 // Setting the lowest element in the vector.
3082 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3083 MOVL_shuffle_mask)),
3084 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3085 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3086 MOVL_shuffle_mask)),
3087 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3089 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3090 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3091 MOVLP_shuffle_mask)),
3092 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3093 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3094 MOVLP_shuffle_mask)),
3095 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3098 // Set lowest element and zero upper elements.
3099 let AddedComplexity = 15 in
3100 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3101 MOVL_shuffle_mask)),
3102 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3103 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3104 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3106 // Some special case pandn patterns.
3107 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3109 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3110 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3112 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3113 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3115 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3117 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3118 (memop addr:$src2))),
3119 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3120 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3121 (memop addr:$src2))),
3122 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3123 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3124 (memop addr:$src2))),
3125 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3127 // vector -> vector casts
3128 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3129 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3130 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3131 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3132 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3133 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3134 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3135 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3137 // Use movaps / movups for SSE integer load / store (one byte shorter).
3138 def : Pat<(alignedloadv4i32 addr:$src),
3139 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3140 def : Pat<(loadv4i32 addr:$src),
3141 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3142 def : Pat<(alignedloadv2i64 addr:$src),
3143 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3144 def : Pat<(loadv2i64 addr:$src),
3145 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3147 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3148 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3149 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3150 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3151 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3152 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3153 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3154 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3155 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3156 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3157 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3158 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3159 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3160 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3161 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3162 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3164 //===----------------------------------------------------------------------===//
3165 // SSE4.1 Instructions
3166 //===----------------------------------------------------------------------===//
3168 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3171 Intrinsic V2F64Int> {
3172 // Intrinsic operation, reg.
3173 // Vector intrinsic operation, reg
3174 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3175 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3176 !strconcat(OpcodeStr,
3177 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3178 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3181 // Vector intrinsic operation, mem
3182 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3183 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3184 !strconcat(OpcodeStr,
3185 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3187 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3190 // Vector intrinsic operation, reg
3191 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3192 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3193 !strconcat(OpcodeStr,
3194 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3195 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3198 // Vector intrinsic operation, mem
3199 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3200 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3201 !strconcat(OpcodeStr,
3202 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3204 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3208 let Constraints = "$src1 = $dst" in {
3209 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3213 // Intrinsic operation, reg.
3214 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3216 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3217 !strconcat(OpcodeStr,
3218 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3220 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3223 // Intrinsic operation, mem.
3224 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3226 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3227 !strconcat(OpcodeStr,
3228 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3230 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3233 // Intrinsic operation, reg.
3234 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3236 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3237 !strconcat(OpcodeStr,
3238 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3240 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3243 // Intrinsic operation, mem.
3244 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3246 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3247 !strconcat(OpcodeStr,
3248 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3250 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3255 // FP round - roundss, roundps, roundsd, roundpd
3256 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3257 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3258 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3259 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3261 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3262 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3263 Intrinsic IntId128> {
3264 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3266 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3267 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3268 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3270 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3273 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3276 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3277 int_x86_sse41_phminposuw>;
3279 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3280 let Constraints = "$src1 = $dst" in {
3281 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3282 Intrinsic IntId128, bit Commutable = 0> {
3283 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3284 (ins VR128:$src1, VR128:$src2),
3285 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3288 let isCommutable = Commutable;
3290 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3291 (ins VR128:$src1, i128mem:$src2),
3292 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3294 (IntId128 VR128:$src1,
3295 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3299 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3300 int_x86_sse41_pcmpeqq, 1>;
3301 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3302 int_x86_sse41_packusdw, 0>;
3303 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3304 int_x86_sse41_pminsb, 1>;
3305 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3306 int_x86_sse41_pminsd, 1>;
3307 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3308 int_x86_sse41_pminud, 1>;
3309 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3310 int_x86_sse41_pminuw, 1>;
3311 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3312 int_x86_sse41_pmaxsb, 1>;
3313 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3314 int_x86_sse41_pmaxsd, 1>;
3315 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3316 int_x86_sse41_pmaxud, 1>;
3317 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3318 int_x86_sse41_pmaxuw, 1>;
3320 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3322 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3323 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3324 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3325 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3327 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3328 let Constraints = "$src1 = $dst" in {
3329 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3330 SDNode OpNode, Intrinsic IntId128,
3331 bit Commutable = 0> {
3332 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3333 (ins VR128:$src1, VR128:$src2),
3334 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3335 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3336 VR128:$src2))]>, OpSize {
3337 let isCommutable = Commutable;
3339 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3340 (ins VR128:$src1, VR128:$src2),
3341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3342 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3344 let isCommutable = Commutable;
3346 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3347 (ins VR128:$src1, i128mem:$src2),
3348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3350 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3351 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3352 (ins VR128:$src1, i128mem:$src2),
3353 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3355 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3359 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3360 int_x86_sse41_pmulld, 1>;
3362 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3363 let Constraints = "$src1 = $dst" in {
3364 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3365 Intrinsic IntId128, bit Commutable = 0> {
3366 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3367 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3368 !strconcat(OpcodeStr,
3369 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3371 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3373 let isCommutable = Commutable;
3375 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3376 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3377 !strconcat(OpcodeStr,
3378 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3380 (IntId128 VR128:$src1,
3381 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3386 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3387 int_x86_sse41_blendps, 0>;
3388 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3389 int_x86_sse41_blendpd, 0>;
3390 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3391 int_x86_sse41_pblendw, 0>;
3392 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3393 int_x86_sse41_dpps, 1>;
3394 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3395 int_x86_sse41_dppd, 1>;
3396 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3397 int_x86_sse41_mpsadbw, 1>;
3400 /// SS41I_ternary_int - SSE 4.1 ternary operator
3401 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3402 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3403 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3404 (ins VR128:$src1, VR128:$src2),
3405 !strconcat(OpcodeStr,
3406 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3407 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3410 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3411 (ins VR128:$src1, i128mem:$src2),
3412 !strconcat(OpcodeStr,
3413 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3416 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3420 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3421 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3422 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3425 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3426 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3427 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3428 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3430 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3433 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3437 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3438 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3439 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3440 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3441 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3442 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3444 // Common patterns involving scalar load.
3445 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3446 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3447 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3448 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3450 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3451 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3452 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3453 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3455 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3456 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3457 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3458 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3460 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3461 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3462 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3463 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3465 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3466 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3467 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3468 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3470 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3471 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3472 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3473 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3476 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3477 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3478 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3479 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3481 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3484 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3488 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3489 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3490 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3491 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3493 // Common patterns involving scalar load
3494 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3495 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3496 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3497 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3499 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3500 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3501 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3502 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3505 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3506 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3507 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3508 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3510 // Expecting a i16 load any extended to i32 value.
3511 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3513 [(set VR128:$dst, (IntId (bitconvert
3514 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3518 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3519 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3521 // Common patterns involving scalar load
3522 def : Pat<(int_x86_sse41_pmovsxbq
3523 (bitconvert (v4i32 (X86vzmovl
3524 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3525 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3527 def : Pat<(int_x86_sse41_pmovzxbq
3528 (bitconvert (v4i32 (X86vzmovl
3529 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3530 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3533 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3534 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3535 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3536 (ins VR128:$src1, i32i8imm:$src2),
3537 !strconcat(OpcodeStr,
3538 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3539 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3541 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3542 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3543 !strconcat(OpcodeStr,
3544 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3547 // There's an AssertZext in the way of writing the store pattern
3548 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3551 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3554 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3555 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3556 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3557 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3558 !strconcat(OpcodeStr,
3559 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3562 // There's an AssertZext in the way of writing the store pattern
3563 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3566 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3569 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3570 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3571 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3572 (ins VR128:$src1, i32i8imm:$src2),
3573 !strconcat(OpcodeStr,
3574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3576 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3577 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3578 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3579 !strconcat(OpcodeStr,
3580 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3581 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3582 addr:$dst)]>, OpSize;
3585 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3588 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3590 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3591 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3592 (ins VR128:$src1, i32i8imm:$src2),
3593 !strconcat(OpcodeStr,
3594 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3596 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3598 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3599 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3600 !strconcat(OpcodeStr,
3601 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3602 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3603 addr:$dst)]>, OpSize;
3606 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3608 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3609 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3612 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3613 Requires<[HasSSE41]>;
3615 let Constraints = "$src1 = $dst" in {
3616 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3617 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3618 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3619 !strconcat(OpcodeStr,
3620 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3622 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3623 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3624 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3625 !strconcat(OpcodeStr,
3626 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3628 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3629 imm:$src3))]>, OpSize;
3633 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3635 let Constraints = "$src1 = $dst" in {
3636 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3637 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3638 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3639 !strconcat(OpcodeStr,
3640 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3642 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3644 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3645 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3646 !strconcat(OpcodeStr,
3647 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3649 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3650 imm:$src3)))]>, OpSize;
3654 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3656 let Constraints = "$src1 = $dst" in {
3657 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3658 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3659 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3660 !strconcat(OpcodeStr,
3661 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3663 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3664 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3665 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3666 !strconcat(OpcodeStr,
3667 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3669 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3670 imm:$src3))]>, OpSize;
3674 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3676 let Defs = [EFLAGS] in {
3677 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3678 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3679 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3680 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3683 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3684 "movntdqa\t{$src, $dst|$dst, $src}",
3685 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3687 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3688 let Constraints = "$src1 = $dst" in {
3689 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3690 Intrinsic IntId128, bit Commutable = 0> {
3691 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3692 (ins VR128:$src1, VR128:$src2),
3693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3694 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3696 let isCommutable = Commutable;
3698 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3699 (ins VR128:$src1, i128mem:$src2),
3700 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3702 (IntId128 VR128:$src1,
3703 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3707 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3709 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3710 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3711 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3712 (PCMPGTQrm VR128:$src1, addr:$src2)>;